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Advanced Power MOSFET SFS9634

FEATURES
BVDSS = -250 V
Avalanche Rugged Technology
Rugged Gate Oxide Technology
RDS(on) = 1.3 Ω
Lower Input Capacitance ID = -3.4 A
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10 µA (Max.) @ VDS = -250V
TO-220F
Low RDS(ON) : 0.876 Ω (Typ.)

1
2
3

1.Gate 2. Drain 3. Source

Absolute Maximum Ratings
Symbol Characteristic Value Units
VDSS Drain-to-Source Voltage -250 V
o
Continuous Drain Current (TC=25 C) -3.4
ID o A
Continuous Drain Current (TC=100 C) -2.6
IDM Drain Current-Pulsed O
1 -14 A
VGS Gate-to-Source Voltage +
_ 30 V
EAS Single Pulsed Avalanche Energy O
2 145 mJ
IAR Avalanche Current O
1 -3.4 A
EAR Repetitive Avalanche Energy O
1 3.3 mJ
dv/dt Peak Diode Recovery dv/dt O
3 -4.8 V/ns
o
Total Power Dissipation (TC=25 C) 33 W
PD o
Linear Derating Factor 0.26 W/ C
Operating Junction and
TJ , TSTG - 55 to +150
Storage Temperature Range
o
Maximum Lead Temp. for Soldering C
TL 300
Purposes, 1/8 “ from case for 5-seconds

Thermal Resistance
Symbol Characteristic Typ. Max. Units
RθJC Junction-to-Case -- 3.79 o
C/W
RθJA Junction-to-Ambient -- 62.5

Rev. B

©1999 Fairchild Semiconductor Corporation

nC ID=-5.ID=-1. Starting T =25 C AS DD G J _ _ _ O3 ISD <-5. -10 VDS=-250V IDSS Drain-to-Source Leakage Current µA o -. -. 16 40 See Fig 13 O 4 O 5 Qg Total Gate Charge -. V =-50V. -. Duty Cycle <_ 2% O5 Essentially Independent of Operating Temperature . -4. Typ.7A O 4 Ciss Input Capacitance -.0A Qrr Reverse Recovery Charge -. -. VDD < BVDSS .VDS=-25V. Coeff. -. -0.17 -. -. 1. V VGS=0V.VGS=0V o trr Reverse Recovery Time -. R =27Ω*.0 V TJ=25 C.ID=-1. 45 65 td(on) Turn-On Delay Time -. 3.ID=-5. Ω VDS=-40V. ns TJ=25 C. -. 100 VGS=30V -. Max. -.3 Ω VGS=-10V.0 -. -3.4 -. -.IS=-3. 170 -.VGS=-10V.ID=-250µA ∆BV/∆TJ Breakdown Voltage Temp. Typ. Units Test Condition BVDSS Drain-Source Breakdown Voltage -250 -.22 -- o V/ C ID=-250µA See Fig 7 VGS(th) Gate Threshold Voltage -2.ID=-250µA Gate-Source Leakage .TC=125 C Static Drain-Source RDS(on) -.4 Integral reverse pn-diode A ISM Pulsed-Source Current O 1 -.7A O 4 On-State Resistance gfs Forward Transconductance -. Units Test Condition IS Continuous Source Current -. -100 VDS=-200V. 20 50 ns RG=12 Ω td(off) Turn-Off Delay Time -. -14 in the MOSFET o VSD Diode Forward Voltage O4 -. I =-3. 5. 750 975 VGS=0V. -100 VGS=-30V IGSS nA Gate-Source Leakage . P-CHANNEL SFS9634 POWER MOSFET Electrical Characteristics (TC=25oC unless otherwise specified) Symbol Characteristic Min. 15. O1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature o O2 L=20mH.IF=-5.5 -. -5. See Fig 6 & Fig 12 O 4 O 5 Source-Drain Diode Ratings and Characteristics Symbol Characteristic Min. -.0A. Starting T J =25oC O4 Pulse Test : Pulse Width = 250 µs.0A. Forward -. 29 37 VDS=-200V.0 V VDS=-5V.2 -. tr Rise Time -. Reverse -. 13 35 VDD=-125V. 1. µC diF/dt=100A/µs O 4 Notes .0A Qgd Gate-Drain( “ Miller “ ) Charge -. -. di/dt < 400A/µs. Qgs Gate-Source Charge -. 110 165 pF See Fig 5 Crss Reverse Transfer Capacitance -. 40 90 tf Fall Time -.4A.4A.f =1MHz Coss Output Capacitance -. Max.

Gate Charge vs.5.5 1.0 150 oC @ Notes : 25 oC 1.5 4. Output Characteristics Fig 2. Drain Current Fig 4.10 V 101 .0 1.0 V . VGS = 0 V 0.5 2.0 V Bottom : .0 A 0 0 100 101 0 5 10 15 20 25 30 -VDS .5 V . 250 µs Pulse Test 3. TC = 25 oC 10-1 10-1 10-1 100 101 2 4 6 8 10 -VDS .0 10-1 0 3 6 9 12 15 18 21 0.4. P-CHANNEL POWER MOSFET SFS9634 Fig 1. Capacitance vs.5 RDS(on) .8.55 oC 2.0 4. On-Resistance vs.0 V .0 3.0 -IDR .6. Source-Drain Diode Forward Voltage [A] Drain-Source On-Resistance 3. VGS = 0 V 2.15 V [A] [A] 101 .5 V 100 100 150 oC 25 oC @ Notes : 1.0 2.5 100 1. VDS = -40 V 1.5 3. Gate-Source Voltage 1500 [V] Ciss= Cgs+ Cgd ( Cds= shorted ) Coss= Cds+ Cgd VDS = -50 V 10 [pF] -VGS . Drain Current .5 -ID . Drain Current [A] -VSD . 250 µs Pulse Test @ Note : TJ = 25 oC 0. f = 1 MHz @ Notes : ID =-5. Drain-Source Voltage Fig 6.0 VGS = -10 V 1. Gate-Source Voltage [V] Fig 3. Drain-Source Voltage [V] -VGS . Drain Current -ID . Drain-Source Voltage [V] QG . Transfer Characteristics V GS Top : . 250 µs Pulse Test . Source-Drain Voltage [V] Fig 5. Total Gate Charge [nC] .5. VGS = 0 V @ Notes : 2. Gate-Source Voltage Crss= Cgd VDS = -125 V C iss VDS = -200 V 1000 Capacitance C oss 5 @ Notes : 500 C rss 1.5 VGS = -20 V 2.7. [Ω ] 2. Reverse Drain Current 101 2.0 V -ID .

5 1.02 (t) . P-CHANNEL SFS9634 POWER MOSFET Fig 7. ID = -250 µA 2. Safe Operating Area Fig 10. Junction Temperature [oC] Fig 9.0 Drain-Source On-Resistance -BVDSS . D=t1 /t 2 0. TC = 25 oC 2. Max. TJ = 150 oC 1 10-1 3.0 0.1 100 10 1 t 1 . VGS = -10 V 2. Single Pulse 0 100 101 102 25 50 75 100 125 150 -VDS .5 A 0. Temperature Fig 8. TJ M -T C =P D M *Z θ J C (t) 0. Breakdown Voltage vs.3 10 .0 1. θJC single pulse Z 10.2 3. ID = -2.2 10 . t2. Case Temperature [A] 4 [A] Operation in This Area -ID . 10.01 t1. Max.1 0. Drain Current 101 3 0. On-Resistance vs.0 1.79 2. 0.4 10 . Temperature Drain-Source Breakdown Voltage 1.5 10. Case Temperature [oC] Fig 11.8 0. Thermal Response Thermal Response D=0.1 3.5 1. (Normalized) 2.05 P.2 1. Drain Current is Limited by R DS(on) -ID .DM 0.1 ms 1 ms 10 ms 0 2 10 DC @ Notes : 1. Drain-Source Voltage [V] Tc .1 2. Square Wave Pulse Duration [sec] . VGS = 0 V 0.5 @ Notes : 10 0 o C/W Max. Drain Current vs.9 @ Notes : @ Notes : 1. Duty Factor.5 1. Zθ J C (t)=3. (Normalized) RDS(on) . Junction Temperature [ C] TJ .0 -75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175 o TJ .

Resistive Switching Test Circuit & Waveforms RL t on t off Vout tf td(on) tr td(off) Vin VDD ( 0.LL IAS2 -------------------- VDS 2 BVDSS -. Unclamped Inductive Switching Test Circuit & Waveforms BVDSS LL 1 EAS = ---.VDD Vary tp to obtain ID tp Time required peak ID VDD VDS (t) RG C VDD ID (t) DUT -10V IAS tp BVDSS . P-CHANNEL POWER MOSFET SFS9634 Fig 12.5 rated VDS ) Vin 10% RG DUT -10V 90% Vout Fig 14. Gate Charge Test Circuit & Waveform “ Current Regulator ” VGS Same Type 50KΩ as DUT Qg 12V 200nF 300nF -10V VDS VGS Qgs Qgd DUT -3mA R1 R2 Current Sampling (IG) Current Sampling (ID) Charge Resistor Resistor Fig 13.

Body Diode Forward Current Vf VDS ( DUT ) Body Diode VDD Forward Voltage Drop Body Diode Recovery dv/dt . Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT -- IS L Driver VGS Compliment of DUT RG (N-Channel) VDD VGS • dv/dt controlled by “RG” • IS controlled by Duty Factor “D” Gate Pulse Width VGS D = -------------------------- Gate Pulse Period 10V ( Driver ) Body Diode Reverse Current IRM IS ( DUT ) di/dt IFM . P-CHANNEL SFS9634 POWER MOSFET Fig 15.

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