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XV Workshop Iberchip, Buenos Aires - Argentina, 25 - 27 de Marzo de 2009

CMOS Integrate and Fire Neuron for Temporal
Logarithmic Encoding
Julio Saldaña Taliana Herrera Emilio Del-Moral-Hernández
Escola Politécnica Grupo de Microelectrónica Escola Politécnica
Universidade de São Paulo Pontificia Universidad Católica del Perú Universidade de São Paulo
Email: jsaldana@lsi.usp.br Email: a20040399@pucp.edu.pe Email: emilio@lsi.usp.br

Abstract—It is presented the design of an integrate and fire determine if a set of analogue inputs are in a determined
neuron which produces action potentials in times that are related proportion. The system shown in figure 1 is based in the
to the logarithm of an input reference current. The circuit is proposal of Hopfield. It resolves the analogue match problem
aimed to the implementation of a system based on the model
provided by J. Hopfield for the pattern-recognition computation as explained here.
using action potential timing for stimulus representation [1]. The
circuit is based on a 0.35 µm CMOS technology and consumes
330 µW . This consumption corresponds to input currents ranging
from 10 µA to 90 µA encoded in phase differences between 140
µs and 375 µs.

I. I NTRODUCTION
The prodigious capability of biological nervous systems
has motivated the development of artificial models of neurons.
These models can be made at different levels of abstraction.
For example the artificial neural networks are based on
simplified models of neurons which produce a continuous
output representing a sigmoidal function of the overall input.
We can also find conductance based models of neurons
implemented in VLSI [2].
Figure 1. System based on Hopfield model
Unlike a conductance based neuron, an integrate and fire
circuit represents separately the potential prior to the axonal The system receives a set of analogue inputs (V1 , V2 , ..., Vn )
trigger zone and the action potential [3]. In this work it is and must detect if it satisfies the equation 1.
presented the design of a CMOS integrate and fire neuron
aimed to the implementation of the model proposed by V1 V2 Vn
= = ... = =k (1)
Hopfield in [1]. In that model the information is represented p1 p2 pn
by the timing of action potentials. The relative phase of these
spikes with respect to a reference sub-threshold oscillation Encoding neurons (Ci ) generate a train of pulses delayed
is a logarithmic function of the input to be represented. with respect to a reference signal (clk). This delay (φi ) is
For a VLSI implementation of this model it is necessary a a logarithmic function of the respective input (Vi ).
circuit that codifies an input signal in spikes with such a
logarithmic timing. The circuit presented here reproduces that φi = ln(Vi ) + B (2)
codification. Differently from a previous work [4] in this case
an integrate an fire neuron is presented. In the next section Delay elements (Si ) adds other delays (δi ) defined by
it is reviewed the Hopfield model, then in section 3 the parameters (wi ). These delays have the relation:
integrated and fire neuron is described. In section 4 the results 1
are summarized and finally in section 5 the conclusions of δi = ln( )+C (3)
pi
this work are presented.
Then the overall delay after Si is:

II. T HE H OPFIELD M ODEL Vi
λi = φi + δi = ln( )+D (4)
The model proposed by Hopfield, can be viewed as a pi
possible explanation on the way the human brain resolves If the input set satisfies the equation 1 all the delays λi
the analogue match problem [1]. This problem consists in would be equals, so a coincidence detector R would generate

417

M 3. It consists of R tspk = −τ.Iin ) (7) an exponential current generator and a schmitt trigger circuit. According to [6] strong inversion operation is guaranteed if the normalized Vref − t current of the transistor is greater than 100: Iexp = . and M 8. Especial care must a time constant of τ = R. This voltage at the gate of M 4 is minimal. the exponential current returns to its maximal value and N 3 goes up again. otherwise it is near a difference between the phases of the respective output spikes. if4 = if5 > 100 (9) voltage at node N 3 is high and voltage at node spk is low. A1. XV Workshop Iberchip. M 4 and M 5 form the exponential For two different inputs I1 and I2 we have: current generator.C . In this case M 2 is open. interpreted as action potential. In order to avoid this and M 5 we have a current which varies periodically and condition the following procedure was used. then C is discharged.e τ (6) R While the exponential current is greater than the input one. is generated at ISQ. spk.ln( ) (8) as in [5]. That current is compared of the current the current mirror M 4 − M 5 must operate in with the input current Iin at node N 3. M 10.ln( . Transistor M 1 discharges capacitor C to ground periodically. W L 418 . then it is possible that R process restarts every time clk discharges C. gnd. so through M 4 M 3 enters in triode region of operation. For a good copy exponentially inside each period. opening M 2. Encoding Neuron a pulse indicating that the proportion is satisfied. In this ID if = (10) way a pulse. When the exponential current is lower With the aid of the equation 10 it is possible to calculate than Iin voltage at node N 3 goes down and spk goes up the aspect ratios of M 4 and M 5. Buenos Aires .(1 − e− τ ) (5) M 3 also is at its maximum. CMOS I NTEGRATE AND F IRE N EURON The circuit is represented in the figure 2. As the current is exponential with respect the time. Vref The exponential current generator is based on an RC circuit. C. When the saturation current of M 5 is greater than So the relation between to input currents is translated to that of M 7 the voltage at N 3 is near V dd. The circuit formed by M 5 and M 7 acts as a current Vref I2 comparator. M 12 and M 13 R I1 form the schmitt trigger circuit which does the same function t1 − t2 = −τ. whenever the exponential current equals Iin. 25 .27 de Marzo de 2009 VDD M4 M5 M12 Vref + M3 M8 M10 M14 A1 − Vdd N2 N3 spk R Iin N1 M9 M11 M15 M1 M2 M6 M7 clk C M13 GND Figure 2. be take in the calculus of M 3 dimensions.Argentina. M 9. For the calculus of transistors dimensions it was used the The voltage at node N 1 rises exponentially toward V ref with Advanced Compact Model of Mosfet [6]. strong inversion even at the minimum current. the output node. the time of the pulse generation is a logarithmic function of Iin. III. When the current t of resistor is at its maximum value the voltage at the gate of VN 1 = Vref . M 11. As the current is maximal the Current through R falls from V ref exponentially to 0. In figure 2 R.

5 0 200 400 600 800 1000 1200 10µA to 90µA corresponding to a spike delays from 140µs Time [us] to 375µs.5 Voltage [V] W W 2 ( )4 = ( )5 = 2 (11) L L 1. In the figure 5 it is presented the curve 2 relating the delays of spikes with the input current. where Vref = 1v. The output N3 of the current comparator.( 1 + if + 3) (14) (b) we obtain if3 = 80 and then using equation 10: Figure 3. The reference clk is presented 3. To prove 1.5 the normalized current for the case of maximum current: 0 100µA 0 200 400 600 800 1000 1200 if4max = = 2000 (12) Time [us] 25nA. First we calculate 0. As 2. this is due to the current mode operation unlike the voltage mode presented in [4]. Buenos Aires .27 de Marzo de 2009 In the equation 10 ISQ is a technological parameter. the exponential of those delays is calculated and the plot is presented in figure 6.( 1 + if − 2 + ln( 1 + if − 1)) (13) 2 Voltage [V] 1. In this version an external capacitor is 30 considered.3V .5 in 3(a) and the exponential current is shown in 4(a).5k the exponential current varies 20 from 100µA to 5µA.5 the input current increases.5 lower than 1.3V − 1V = 300mV . Time [us] In figure 3(b) it is represented the pulse generated when a (a) 15µA input current is applied.5 Where φT is the thermal voltage and VP is the pinch-off 1 voltage. 419 . The input current ranges from 0. ID = 5µA and ISQP MOS = 25nA we 3 obtain: 2. the number of spikes inside each Voltage [V] clock period increases. namely N 3 is presented in 4(b). We obtain the minimum gate voltage of M 4 equal to 1.5 Knowing this aspect ratio it is possible to calculate the 1 minimum value of the gate voltage of M 4. the frequency of the clk can be increased 10 0 200 400 600 800 1000 1200 but the input current range would be reduced. worst speed and worst power cases are almost the same.5 0 200 400 600 800 1000 1200 Time [us] VDsat = φT . With a clk of 2. 25 . It means that the saturation voltage of M 3 must be 0. 70 Current [uA] 60 IV. 3.Argentina. R ESULTS 50 For a time constant of 100µs values of R = 10k and 40 C = 10n were chosen. (b) We made worst case analysis of the circuit. The results in Figure 4. 3 For input currents lower than 15µA no spike is generated.2 (a) Then the minimum value for the gate voltage is calculated 3.5 clk placing if = 100. XV Workshop Iberchip. clk and spk for an 15 uA input current W 100 ( )3 = 125 (15) Iexp L 90 Iin Results validating this calculus are presented at the end of 80 the next section in figure 7.5 VP − VS = φT . With this 0 restriction and with the aid of equation 14: −0.5 the logarithmic dependence. 1 As shown in figure 6 the logarithmic encoding is better than the previous one reported in [4]. Re.5 spk with the aid of the following equation: 3 2. Circuit response for a 15 uA input current the typical.

6 2. pp. Cunha. 19. 1. 1995. 1995. Del-Moral-Hernandez. Silva. 10. 150 R EFERENCES 100 10 20 30 40 50 60 70 80 90 [1] J. no. Indiveri. Farfán. E.Argentina. C. Delay/ au 25 [5] A. A.” Nature. 6.27 de Marzo de 2009 400 works include a low power version of the integrate and fire neuron presented here like that reported in [7]. vol. Solid-State Circuits. Neural Networks.8 1. 25 .6 1. pp. XV Workshop Iberchip. 2005. 1991. 17. 1998. Figure 5. “Pattern recognition computation using action potential Input [uA] timing for stimulus representation. Navarro. Jabri. Delays of spikes vs. “A silicon neuron. 1357– 40 1358. 5 typical [7] G. and W. “CMOS Encoder for Scale-Independent Pattern Recognition. A controlled refractory period can also be included by placing an additional block 250 between the output spike and the transistor that discharges the 200 capacitor.” IEEE J.C = 10µs is a problem to be solved in a future work. vol.2007. Saldaña.4 2. no. pp. Schneider. This circuit represents an improved version of that presented in [4]. The integration of the time constant R. For the design the ACM Mosfet model was used. 33. pp. pp. “A 20 CMOS Implementation of the Sine-Circle Map. and R.6.” in 48th Midwest Sym- posium on Circuit and Systems. and C. Del-Moral-Hernández. 376. pp. E.” Electronics Letters.2 Voltage [V] 2 1. 35 [4] J. Chicca. “A VLSI Array of Low-Power 0 Spiking Neurons and Bistable Synapses with Spike-Timing Dependent 10 20 30 40 50 60 70 80 90 Plasticity. 45 [3] S. input current [2] M. Simulations was made with the Cadence Spectre simulator. Rı́o de Janeiro 30 . C. M.” IEEE Trans. no. vol. “An MOS transistor 10 model for analog circuit design. e 15 [6] A. 16. and the 350 implementation of the system that resolves the analogue match Delay [us] 300 problem described in the section 1. 2. For that case of complex parametric analysis it was used the Cadence OCEAN tool. Input [uA] 2006. 345. 31.35µm. 515–518. vol. Douglas. Buenos Aires .Brazil. no. E. C ONCLUSION It was presented the design of a circuit that encodes input currents into phase delays of outputs spikes. Exponential of the delays 2. V. and C. The technology chosen for fabrication was AMS 0.2 0 500 1000 1500 2000 Time [us] Figure 7. “Analogue VLSI integrate-and-fire neuron with frequency adaptation. vol. J. Schultz and M.” in SBCCI.4 1.” Nature. September 3 . Noije. Galup-Montoro. Mahowald and R. The input can range from 10µA to 90µA and the output delays varies from 140µs to 375µs and consumes 330µW . 1510–1519. vol. 1502–1505. Figure 6. 211–221. 33–36. Hopfield. Voltage at the gate of M4 V. Future 420 . no. J. Douglas. where OCEAN stands for Open Command Environment for Analysis and allows the development of simulations scripts that simplifies the task of design and characterization.