You are on page 1of 6

World Academy of Science, Engineering and Technology 45 2008

Design of Folded Cascode OTA in Different
Regions of Operation through gm/ID
Methodology
H. Daoud Dammak, S. Bensalem, S. Zouari, and M. Loulou

OTA is a basic element in this type of circuit whether
Abstract—This paper presents an optimized methodology to switched capacitors technique is kept for ADC design.
folded cascode operational transconductance amplifier (OTA) design. Our target was to design a folded cascode OTA circuit in
The design is done in different regions of operation, weak inversion, sight of Sigma Delta analog-to-digital converter design using
strong inversion and moderate inversion using the gm/ID methodology for wide band radio applications.
in order to optimize MOS transistor sizing.
This paper is organized as follows. Folded cascode OTA
Using 0.35µm CMOS process, the designed folded cascode OTA
achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz structure is analyzed in section II. Section III presents the
in strong inversion mode. In moderate inversion mode, it has a 92dB OTA circuit design in the three regions of operation. Section
DC gain and provides a gain bandwidth product of around 69MHz. IV gives design window. Finally some concluding remarks are
The OTA circuit has a DC gain of 75.5dB and unity-gain frequency provided after evaluating our study toward other works.
limited to 19.14MHZ in weak inversion region.
II. FOLDED OTA STRUCTURE
Keywords—CMOS IC design, Folded Cascode OTA, gm/ID A. NMOS Input Transistor
methodology, optimization. The input stage provides the gain of the operational
amplifier. Due to the greater mobility of NMOS device,
I. INTRODUCTION PMOS input differential pair presents a lower

T HE evolution of the microelectronics industry is
distinguished by the raising level of integration and
complexity. It aims to decrease exponentially the minimum
transconductance than carrier a NMOS pair. Thus, NMOS
transistor has been chosen to ensure the largest gain required.
B. Architecture Analysis
feature sizes used to design integrated circuits. The cost of
design is a great problem to the continuation of this evolution.
Vdd
Senior designer’s knowledge and skills are required to ensure
a good analogue integrated circuit design. To fulfill the given
requirements, the designer must choose the suitable circuit
M1 M2 M 12
architecture, although different tools partially automating the
topology synthesis appeared in the past [1]-[4].
The optimization becomes an important method; a heuristic
process was developed in [5]. Nominal circuits design was Ibias
M3 M4
considered in [6]-[7], sizing problems were discussed in [8]- V1
[10], and worst-case optimization in [11]-[13]. Several +
M9 M 10 Vo +

Vo −
Vin Vin
optimization tools were developed, such as equation based
GPCAD [14]-[15], AMG using a symbolic simulator and the M5 M6
simulation based ASTRX/OBLX [16]-[18]. Recently, the V2

sizing problem from different aspects are addressed in Ibias
numerous papers ([13], [19]-[24]).
M7 M8
Designing high-performance base band analog circuits is
still a hard task toward reduced supply voltages and increased M 11
frequency. Current tendency focus on some radio-software
receivers which suppose a RF signal conversion just after the Vss
antenna. Thus, a very higher sampling frequency and
resolution analog-to-digital converter design is required. The Fig. 1 Folded cascode OTA topology

H. Daoud Dammak, S. Bensalem, S. Zouari and M. Loulou are with the The main bottleneck in an analog circuit is the operational
national National School of Engineering of Sfax, B.P. 3038, Sfax, Tunisia (e-
amplifier. Different types of OTA configuration are available
mails: daoud.houda@tunet.tn, samir.bensalem@isecs.rnu.tn,
zouari@enis.rnu.tn, mourad.loulou@ieee.org). to the designer who tend to improve performances

28

and M9. we introduce the design of the folded cascode OTA amplifier in B. In our design. Table I.g m 6 (4) A = V ID 2 (λ N 2 + λ P 2 ) III. But. bias currents. Flandre and Silveira [27].g. transistor sizing. linear or saturated mode. • gm9 and gm9/ID yield the bias current ID and furthermore We set specifications to the circuit of Fig. Transistors biasing in weak synthesis methodology for CMOS OTA architectures (Fig. The open-loop voltage gain and gain bandwidth are given by (1) and (2) below: g m 9 . we will study the folded cascode to determine the unknowns that are MOS device sizes and bias OTA behaviour in the three regions of operation. • W/L is finally given by ID/I'.g m 4 (1) AV = 2 ID (g m 4λ N + g m 6λ P ) 2 2 gm9 g I (2) GBW = m9 D ID C L Where. 29 . 2 Design flow m4 m6 The gain expression becomes: g m 9 . λN and λP are the parameters related to channel length modulation respectively for NMOS and PMOS devices. In this paper. quasi-static or high-frequency operation [30]. M6 and M9. three regions of operation of transistor. e. These transistors present a low optimize for example: gain and unity gain frequency in order thermal noise. 4. The universal gm/ID as a function of ID/(W/L) characteristic amp due to its large gain and high bandwidth performances. This design applies a synthesis The operating range of transistors can be entirely exploited: procedure based on the gm/ID methodology introduced by weak. gm4.2) inversion provide higher transconductance and supply a larger [28]. World Academy of Science. this last starts by fixing the specifications to gain with a smaller current. gm6 and gm9 are respectively the transconductances of transistors M4. M6. ID is the bias gm9/ID ID current flowing in Mosfets M4. is favorable for this operating mode. whereas gm9/ID As shown in Fig. CL is the capacitance at the output node. we note that weak inversion presents is derived from the specified DC open-loop gain and higher gm/ID values with smaller current. noise and so on. In fact. so an increased gain the chosen technology using equation (4). FOLDED CASCODE OTA DESIGN The op-amp is characterized by various performances like open-loop voltage gain. 1 presented by gm9/ID gives I' where I'= ID/(W /L). characteristic is obtained by simulation and defined in the To understand the operation of the folded cascode OTA.. Engineering and Technology 45 2008 requirements design [25]. slew rate. of the CMOS technology under consideration (0. Weak Inversion Region the three regions of operation. current: C. We opt for a “folded cascode” op.g m 6 . Mosfets M11 and M12 provide the DC AV GBW bias voltages to M1-M2-M7-M8 transistors. moderate or strong inversion. 3). These performances measures are fixed by the design parameters. This loads of a diff-pair and changing the Mosfets to n-channels). Taking into account the complementarity I’= ID/(W/L)9 (W/L)9 between the transistors M4 and M6: g =g (3) Fig. they can be operated in strong The formulation of a design flow clarifies a top-down inversion or weak inversion. and other component values [26]. this last has a differential stage consisting of NMOS transistors M9 and M10. The aim of this work is to determine values of the design Fig.35µm of Fig. The transistors are traditionally biased in the saturation A Sizing Algorithm mode in analogue circuits. 3 gm/ID as a function of ID/(W/L) parameters that optimize an objective feature whereas satisfying specifications or constraints. Design in Weak Inversion • Equation (2) directly yields gm9 from the given transition frequency and capacitive load. 1 presents the folded cascode OTA (the name “folded AMS) is exploited in order to apply the method quoted cascode” comes from folding down p-channel cascode active previously and compute the design parameters (Fig. unity-gain bandwidth.

Thus. It consumes TABLE IV 0. Engineering and Technology 45 2008 TABLE I D.3V/µs.5 bandwidth product isn’t raised and necessary enough to satisfy CL (fF) 10 Vdd/Vss (V) ±1 wide band applications.2.7. In order to improve this parameter. the gain GBW (MHz) 21. 7). The circuit denotes an are collected in Table IV.6µW.6. we propose specifications obtain the parameters computed and summarized in Table II.14MHz with phase margin of W 9. Its transconductance is about 65µS (Fig. 6).7 126.8 (µm) 1 W1.4 Vdd/Vss (V) ±2 W11 (µm) 2 Channel length (µm) 1 V1 = V2 (mV) -428 Likewise. 5).12 (µm) 5. the gain and GBW characteristics are interesting.5degres (Fig. relatively with the same Channel length (µm) 1 lower consumption. 0. 4).10 (µm) 9 67degrees (Fig. The design parameters found with the BSIM3V3 MOSFET model.96V and 0.95V. World Academy of Science. also a wide input and output swings are maintained. a good common mode rejection ratio of W 3.8 (µm) 1 CL (pF) 0. hence. the design strategy described in section A is The designed folded cascode OTA is biased at ±1V power adopted keeping small signals model invariant in different supply voltage using CMOS technology of 0. we will study the design of the OTA in After applying the design strategy clarified previously.2. common-mode range of [-0.8µS kept constant W 5.99V.98V]. 6 Gain and phase curve Fig.4 (µm) 2. It dissipates 48µW.5 Av (dB) 100 W 3.8dB and a low transconductance of 1. a Slew Rate of 3.12 (µm) 5.6. 5 OTA’s transconductance in weak inversion region 30 . W11 (µm) 2 V1 = V2 (mV) -256 The OTA circuit can reach a DC gain of 92dB. TABLE II DESIGN PARAMETERS IN WEAK INVERSION TABLE III Parameters Values SPECIFICATIONS ID (nA) 50 Specifications Values W 9. In this behaviour mode. a wide input fixed at -256mV.1 W1.4mV. we moderate inversion region. Fig. The voltages V1 and V2 are well offset voltage of 0. DESIGN PARAMETERS IN MODERATE INVERSION Moreover. illustrated by Table III that put more constraints on OTA gain bandwidth product. a unity-gain frequency of 69MHz with phase margin of 74.10 (µm) 3.5dB. Design in Moderate Inversion SPECIFICATIONS Specifications Values In weak inversion. a bandwidth of 19.4 for a wide range of frequency (Fig.7. a wide output common-mode range between -0. we succeed in reaching good Av (dB) 105 performances with very low consumption.7 GBW (MHz) 70 W 5. our device is able to achieve a degrading gain of Parameters Values ID (µA) 2 75.35 µm of AMS operation’s regions of transistor. 4 Gain and phase curve Fig.4 (µm) 2.

7 OTA’s transconductance in moderate inversion region As illustrated in Fig. In moderate inversion. current in this region of operation. World Academy of Science.8 W11 (µm) 4 V1 = V2 (mV) -318 The folded cascode OTA has a gain of 77.5dB. IV. 9 Unity gain frequency as a function of drain source current in TABLE VI strong inversion region DESIGN PARAMETERS IN STRONG INVERSION Parameters Values ID (µA) 27. 8). a large unity-gain frequency of 430MHz and a phase margin of 58. we fixed specifications given by Table V. According to the application and its constraints. It is Fig. We conclude that the sizes found in strong inversion are more important than those obtained in weak and moderate inversion. This comparison is given in Table VIII. The performance of the folded cascode OTA from this work has been compared to two recent OTA circuits design. inversion region. we choose the mode of operation of transistors. 8 OTA’s transconductance in strong inversion region 31 . Fig. Fig. Its transconductance is about 396µS (Fig. This topology works in various frequency ranges. The first is a Class-AB OTA [29].4 W 5.10 (µm) 14 W 3. using MATLAB tool.5µA leads to a unity-gain frequency of E. considerable. ID) values.6. 10 Unity gain frequency as a function of drain source current in moderate inversion region V. The second was a telescopic OTA architecture presented in [30]. we estimate reaching bandwidths satisfying wide We notice that unity gain frequency increases in moderate band applications requirements.8 (µm) 2 W1.12 (µm) 10.7. 10.1 Vdd/Vss (V) ±2 Channel length (µm) 1 The Mosfets sizes are computed as a result of the design flow (Table VI). Design in Strong Inversion 460MHz.5 W 9. in strong inversion. we try to present a design window in different regions of operation that yields a different couple of (Ft. 9 and Fig. so we have to take the change of small We remark that gm/ID ratio decreased as a function of signals model in moderate inversion into account. COMPARISON OF RESULTS After discussing the different parameters of OTA design we can evaluate our study toward other works. In weak inversion and for bias current relatively GBW value is around 90MHz. DESIGN WINDOW To verify some design parameters namely unity gain frequency and drain source current. this can be explained by the use of high current towards other regions. Then. a drain current of 27. TABLE V SPECIFICATIONS Caractéristiques Valeurs Av (dB) 80 GBW (MHz) 450 CL (pF) 0. Fig.4 (µm) 5. Engineering and Technology 45 2008 Several characteristics were depicted in folded cascode OTA designing step (Table VII).2degrees.2. for a current fixed at 2µA.

so.18 0.57 92 77.94 .84 .14 69 430 Transconductance (µS) 1. 1.6 48 660 TABLE VIII PERFORMANCES COMPARISON Performance/Design Yao & Steyaert [29] Craig Brendan Keogh [30] This work OTA Architecture Class-AB Telescopic Folded cascode Technology (µm) 0.98] [-1. n (dB) 18 45. fulfilled.5 Supply voltage (V) ±1 ±2 ±2 Bias current (µA) 0. CONCLUSION sizing in different function modes to reach extremely Consequently. World Academy of Science. cascode OTA in the three operation’s modes of transistor: weak inversion. 0. 1.925 1 Power consumption (µW) 80 4.96 .5 196 CMRR (dB) 126. applications to use it in wide band analog-to-digital This contribution presents the strategy design of folded converters.35 DC Gain (dB) 50 79 75.09 0. strong inversion and moderate inversion. Engineering and Technology 45 2008 clearly seen that with folded cascode OTA architecture.72] Input swing (V) [-0. We estimate that gm/ID methodology is well adopted for VI.8 65 396 Phase margin (degrees) 67 74.87] [-1.4 246 337 Output swing (V) [-0.84] [-1.5 58 Offset voltage (µV) 430. we the goal to reach high gain and large bandwidth has been reach low power low voltage topology with high static gain. 0. integrated circuits constitutes a complex activity requiring the Future work would involve the exploitation of these results command of many concepts. 1. the synthesis of high-performance analog performances offered by a given technology.3 16. As a result.95 .53 GBW (MHz) 19.57 GBW (MHz) 57 8. the analog designer on folded cascode OTA for low consumption and wide band remains a rare and highly-valued engineer worldwide. 1.5 19.1 4 55 Power consumption (µW) 0.6 0.8 133 114 PSRR p.14 Phase margin (degrees) 57 78 67 Supply voltage (V) 1 0.95] [-1.99 .6 32 .95 .7 46.87] Slew Rate (V/µs) 3. TABLE VII FOLDED CASCODE OTA SPECIFICATIONS Specifications Weak inversion Moderate inversion Strong inversion DC Gain (dB) 75.

Sangiovanni-Vincentelli. World Academy of Science. vol.C. 7. NO. pp.K. 703-717. Carley and R. 11. 273-294. vol. “GPCAD: A tool for received his Ph. J. Computer-Aided Design vol. 8. 481-492. Dec. 19.” Integrated circuit quality optimization the National School of Engineering of Sfax "ENIS". pp. Since [16] G. (2003). 20.” int. degree in Electronic at the same [20] R. pp. no. S. New York. 25. He [14] M. no. 6.vol. vol. 11. (1868-1879). (1995). 1. M. “Fully Differential Operational of switched current memory cells through a heuristic. Computer-Aided Design. M. "A gm/ID based methodology framework for synthesizing CMOS band BiCMOS analog circuits.A. no.. 8. (1998). Cas-29.” 1998 IEEE/ACM.Antreich. [4] J. (1995).C. He received the Engineering Diploma from the Comm. mixed and RF CMOS integrated circuits design and design optimization based on symbolic simulation and simulated automation. “A Sigma-Delta Modulator in 90-nm CMOS". IEEE. "Low-Power Multi-Bit Σ∆–Modulator Design [7] W. pp. Wieser. (1996). 707-713.” IEEE J. France.M. July-Aug. no. “Automated robust design and optimization of Mourad Loulou was born in Sfax. 113-125. Gray. Masmoudi. Solid-State circuits. 4.C. no. Sansen. 23. Diploma then the Master degree in electronics from [10] P.”An analogue module generator for mixed 2004 he has been an associate Professor at the same analogue/digital ASIC design. pp. pp.” IEEE J. (1996). Gielen. “Design centering by yield prediction. Elmasry and B. Visvanthan. School of Engineering of Sfax from 1999.” Circuit analysis and of Sfax "LETI" since 2004 and he has been a PhD optimization driven by worst-case distances. No. Exhibition. 2. "A 1–V 140-µW 88-dB Audio [6] R. National de la Recherche Scientifique.” IEEE Trans. Degrauwe et al. pp.57. Lee. 13. Nov. del Mar Hershenson. the design of integrated circuits.J. J.S. Apr. “Sunthesis of high. 1-21. vol. He joints the no.” IEEE Trans. Feb. National School of Engineering of Sfax in 1993. pp. (1988). integrated circuits by means of penalty functions. June (2000).. H. United States. of Solid State Circuits.A. W.” Int.. Fakhfakh. vol. (1992). 31. “CMOS op-amp sizing using a geometric programming formulation.. Sansen. 825-839. both from the National School of Engineering simultaneous yield and robustness optimization. Cas-29. "Conception et Optimisation no. vol. no. Oct. using surface integrals .Harjani. pp. [13] A. “Anaconda: simulation-based synthesis of analog for front end receiver.1.”IEEE Trans. Libin. no. (1994). C.. (2001). 6. H.. “The simplicial approximation approach to design centering. Computer. d’un Amplificateur Opérationnel Rail to Rail CMOS Faible Tension [3] H. 3 June (1990).Comput-Aided system design from the University of Bordeaux Design. Leung. He joints the electronic and information [15] M. Circuits Syst.E. December (1990).. 1.” for the design of CMOS analog circuits and application to the synthesis IEEE Trans.pp.. R. 19. (2001). no. pp. Carley.D. (1989). He received the Electrical Engineering IEEE Trans. ISBN:0-07- [2] R. M. G. optimization of VLSI circuit performances.. in 2004 and 2005. Feldmannand S. Jan. 22-38.” Journal of Amplifier with Accurate Output Balancing. He received the electrical engineering degree in 2002 Computer-Aided Design vol.G.M.D. (2001). His current research interests are on analogue [12] A.pp. no. (2001). Koh. Schwencker et al. (1999). 4. New York. [29] Y.” IEEE Trans.” Analog circuit interests are on analogue. annealing. Computer-Aided Design. 12. Actually he supervises the Analogue and no. Stockholm. Harvey.” Proc. Computer- Aided Design vol. Loulou. 1402-1417.. Tunisia in 1968. Sfax "ENIS" from 2005.P. Engineering and Technology 45 2008 REFERENCES [24] P. Kang. [23] F. Electron. I. Schenkel et al.SPICE: An optimization–based system for for portable Audio Application".”IEEE Trans. Loulou. “STAIC: An interactive [27] Silveira. R. student at the National School of Engineering of Aided Design vol. L.” IEEE Journal of Solid Analog Integrated Circuits and Signal Processing.G. Computer-Aided Design vol. "Design of Analog CMOS Integrated Circuit".R. Computer-Aided Design. 12. Boyd and T. pp. And circuit for wireless communication transceivers.” in 1980.” IEEE Trans. no. pp. IEEE J. Brayton.D. 12.P. Ait Ali and N. M. Mandal and V. no. [25] Behzad Razavi. “Optimal design of a technology laboratory of Sfax "LETI" since 1998 CMOS op-amp via geometric programming. [8] S. of a SOI micropower OTA". “Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search. 38th DAC. pp.J. Springer Editor. 4. [18] E. no. and W.R. pp. 10.(1987). and Master degree on electronics and communication [19] G. (1982). Tunisia [9] K.Circuit theory and App. Los Alamitos. Hraeb and C. circuit. 1334-1364. 296-303. (2006). Gielen.. no. CMOS circuits. Jan.I. 33 . Nye et al. 501-519. vol. “IDAC: An interactive design tool for analog 20.H.” IEEE Trans. 308-311.D.P. and he has been assistant Professor at the National Aided Design vol. Walscharts and W. no. Director and G. “Optimizing performances [28] M. 39. circuitsvia stochastic pattern search. Electronic and Information Technology Laboratory [11] K. N°. His current research [17] G.A Rutenbar. no. (2003).. Dharchoudhury and S. 6. especially the design of active RF oscillator and filter [21] R. Mukherjee. “Efficient handling of operating range and manufacturing line variations in analog cell synthesis. Tsividis. pp. S. November (2004). 47-56.” IEEE Trans. S. 88-96. Computer-Aided Design vol. pp. Boyd and T.Antreich and R.Apr.H Séquin and P. Conf. pp.” IEEE Trans.” IEEE Trans. “OPASYN: A compiler for Faible Consommation" Journal Scientifique Libannais.Solid-State circuits. Hachtel and A. 12. vol. (1982). Circuits Syst. no. Khoury.” IEEE Trans. Feb. of Sfax (ENIS). He is currently working Conf. IEEE Journal of Solid State survey of optimization techniques for integrated-circuit design. sept. pp. 323-327.”IEEE Trans.Liban Vol. (1998).Dec. His research interest is to design RF integrated by consideration of structural constraints. TheMcGraw-Hill Companies. 14. Banu. Masmoudi. Lee. Jan. dec.” Proc. 1247-1266. State circuits. Director. 1. Tunisia. Samir Ben Salem was born in 1976 in Sfax.G. respectively. [30] Craig Brendan Keogh. Carley. [5] M. pp. 11. Vol. 1981. D.” 1998 IEEE/ACM Int. vol. 1. Aug.W. Jespers.. Phelps et al. [26] M.A. Int. J. “Worst-case analysis and CMOS integrated circuits design. pp.” DATE Conf. pp. pp. March (2005). 2. (1990).Computer-Aided Design. Y.R. and Y.K Koblitz. Computer-Aided Design vol. 23. analog circuit synthesis. Flandre et P. Rutenbar and L.H. 4. 75-90. Steyaert.U. toward the Ph.269-283. 57-71. “Efficient analog circuit synthesis with in 2003. Gielen at al. Mar. and N.E. “OASYS: A framework for 118815-0. [22] T. le Conseil CMOS operational amplifiers.R. 3. “Automating the sizing of analog CMOS circuits school.. Tunisia. I. “DELIGHT. performances analog circuits in ASTRX/OBLX. Debyser and G. Rutenbar and L. vol. sc-22. Hachtel. 1106-1116. n.R. [1] M.Ochotta. (2000). 69. 88-96 Houda Daoud Dammak was born in Sfax. 15. 1993.. pp.Computer-Aided Design. 1999.L. Mixed Mode Design Group of LETI Laboratory. New York. Computer. institution. degree in 1998 in electronics CMOS op-amp synthesis. Inc. Dec. 8. 22-38. Burmen et al. del Mar Hershenson. Vol. 9.