Application-Dependent Testing of FPGAs
Mehdi Tahoori, Member, IEEE
Abstract—Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic block testing, the configuration of used logic resources remains unchanged, while the interconnect configuration and unused logic resources are modified. Logic testing is performed in only one test configuration whereas interconnect testing is done in a logarithmic number of test configurations. This approach is able to achieve 100% fault coverage. Index Terms—Field-programmable gate array (FPGA), testing.



RAM-BASED field programmable gate arrays (FPGAs) are 2-D arrays of logic blocks and programmable switch matrices, surrounded by programmable input/output (I/O) blocks on the periphery. FPGAs are widely used in many applications such as networking, storage systems, communication, and adaptive computing, due to their reprogrammability, and reduced time-to-market compared to full-custom designs. Unlike other design styles such as application-specific integrated circuits (ASICs) or microprocessor-based designs, testability issues are not explicitly considered in the FPGA-based design flow. This means that the FPGA users rely on the manufacturing test of FPGAs completely. There is no internal scan insertion phase, built-in self-test (BIST) circuitry implementation, or test generation in typical FPGA-based design flow. Hence, the designs mapped into the FPGAs may not be fully testable. There are two main trends in the testing of FPGAs, application-independent (manufacturing) test and application-dependent test. In application-independent testing, which is used as the manufacturing (production) test of these devices, all resources in the FPGA chip are tested. This test is independent of the particular application (design) to be mapped to the FPGA chip. In application-dependent testing, however, the correct functionality of the particular application mapped into the chip is of interest. In this test, only the FPGA resources used in the mapping of that design are tested. FPGA application-dependent testing can be used for systemlevel testing. It has also been used for defect tolerance in order to improve the manufacturing yield [37]. The reprogrammability of FPGAs results in much faster design and debug cycle compared to ASIC implementation. However, once the design is

Manuscript received December 12, 2005; revised April 28, 2006 and May 9, 2006. The author is with the Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 USA (e-mail: mtahoori@ece.neu. edu). Digital Object Identifier 10.1109/TVLSI.2006.884053

finalized and fixed, the programmability becomes useless and costly if further changes in the design during lifetime operation of the system are not required.1 This is why FPGAs are very costly for high volume fixed designs compared to ASICs. FPGA defect tolerance is based on the fact that some FPGA chips that do not pass the application-independent test may be still usable for some particular fixed designs. In this case, defects are located in some areas of the chip not used by those designs. These FPGAs, which are good only for particular designs and do not have the general programmability of typical FPGAs, are called application-specific FPGAs (ASFPGAs). ASFPGAs are profitable for relatively large volume designs which have been completely finalized, i.e., when the final placed and routed version is fixed. In order to achieve a high degree of reliability, this type of test must achieve a very high defect coverage. So, the target fault list must be as comprehensive as possible. Moreover, the application-dependent testing of FPGAs plays a major role in adaptive fault tolerant based on self-repair [12]. During system operation, periodic application-dependent testing is performed to identify defective system components (permanent faults). High-resolution diagnosis is then exploited to precisely locate the defective resources so that efficient repair can be performed. Finally, the design is remapped to bypass the defective components. For this purpose, test time is very crucial since it directly affects the down time of the system. Therefore, the total number of test configurations, which dominates the test time, must be minimized. In this paper, we present a comprehensive application-dependent testing of FPGAs for both logic and interconnect resources, in which test vectors and configurations are automatically generated. The test is performed in two different sets of test configurations. The first set of test configurations targets the faults in the global interconnect whereas testing of faults in the logic blocks and local interconnects is performed in the second set of test configurations. For interconnect testing, the logic blocks of the FPGA used by the mapped design are reprogrammed, and the configuration of the interconnect remains unchanged. Hence, no extra placement and routing are necessary for test configuration generation. The fault list includes all pairwise bridging faults, all multiple stuck-at, and open faults. For logic testing (including local interconnects), the configurations of used logic blocks remain unchanged while the configurations of global interconnect resources and unused logic blocks are modified. An exhaustive test set which is able to cover all functional faults in logic blocks, inclusive of all stuck-at faults, is applied during this phase. The rest of this paper is organized as follows. In Section II, a review of FPGA architecture along with the previous work in FPGA testing is presented. In Section III, the interconnect
1Note that in some applications for various reasons such as changes in protocols, fault tolerance, and temporal adaptive computing, the ability to reconfigure the FPGA is an important feature during lifetime operation of these systems.

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A short fault can be a switch stuck-closed or a bridging fault between two routing resources. A new FPGA architecture with design for testability features is presented in [25]. and [34]. [13]. Testing of local bridging faults in designs mapped into FPGAs was presented in [32]. the design is remapped to avoid faulty resources. In this paper. Also. Typically. However in this paper. with a variety of length. Inter-CLB routing resources provide interconnections among CLBs whereas intra-CLB resources are located inside each CLB. such as SRAM-based FPGAs. as will be redefined and explained in Section III-A. stuck-at. buffers. For instance. the number of programmable elements in the interconnection network is far more than the number of programmable elements in the logic blocks. fanout branches of a net are tested in different test configurations. Due to the complexity of configuration generation algorithm. it cannot be applied to large designs. we presented a technique for application-dependent interconnect testing where we first introduced the notion of single-term function in FPGA testing [33]. every CLB used in the mapped design is reconfigured as transparent logic followed by flip-flops in order to construct scan chains. open and bridging faults must be explicitly considered in interconnect testing. distinguishing FPGAs from other integrated circuits (ICs). resulting in a number of test configurations. In Section IV. C. These techniques target the faults in the entire FPGA for all possible configurations. provide selective and configurable connectivity among the line segments. the fault list was limited to bridges between adjacent wires at the inputs of each LUT. The interconnect resources inside CLBs are called intra-CLB (local) interconnects. A programmable switch stuck-open fault causes the switch to be permanently open regardless of the value of the SRAM cell controlling it. Inter-CLB resources include programmable switch blocks. Since the defects in the interconnects do not manifest themselves only as stuck-at faults. Switch matrices. In the segmented routing scheme. An approach based on Boolean satisfiability was used for test configuration generation. the programmable switches are replaced by programmable multiplexers that provide a more deterministic routing structure [3]. III. Detecting faults within inter-CLB routing resources is addressed in this section. the terms “CLB” and “logic block” are used interchangeably. mainly stuck-at faults are considered. Previous Work Application-independent (manufacturing) testing of FPGAs has been described in [1]. many designs can be mapped into the same silicon over the lifetime of the FPGA. In our earlier publication. we present an application-dependent testing approach for all resources of the FPGA including local and global interconnects as well as the logic resources. functional fault model is considered which is super-set of stuck-at faults and contains any faulty behavior that changes the functionality of the logic function implemented in the logic resources. In [31]. and speed [36]. Intra-CLB interconnects include programmable multiplexers and wires inside CLBs. [24].. These FPGAs use memory cells to store the functional configuration. and wiring channels connecting switch blocks and CLBs. testing of stuck-at faults in the interconnects and logic blocks was presented in which two test configurations for interconnect stuck-at fault testing and one test configuration for CLB stuck-at fault testing were used. and an abundance of line segments. dependent logic cones are tested in different configuration. open. Finally. the configuration of routing resources remains unchanged while the configuration . unlike the previous work. Then. in adaptive reliable computing based on online self-repair. [7]. [30]. [27]. Some discussion regarding the presented application-dependent testing method is presented in Section V. There are two basic FPGA architectures. For inter-CLB interconnect test. the majority of line segments and programmable switches and/or multiplexers are buffered. the interconnection network consists of a 2-D array of identical switch matrices. Fault Models For FPGA interconnect testing we consider stuck-at faults. II. B. opens and shorts. and additional logic for speeding up the implementation of arithmetic functions. In this paper. In order to provide fast interconnection. For FPGA logic testing. Application-dependent diagnosis (fault localization) is also very crucial to many domains in which application-dependent testing is used. Interconnection between these logic blocks are provided by the interconnection network (inter-CLB or global interconnects). Application-dependent testing of FPGAs has been addressed in [5]. i. BACKGROUND AND PREVIOUS WORK A. which consist of programmable switches. For bridging faults. the resources within each CLB are divided into a number of identical logic slices. [16].TAHOORI: APPLICATION-DEPENDENT TESTING OF FPGAS 1025 testing approach is presented. In both cases. a comprehensive fault list including all possible bridging faults.e. The FPGA is a suitable platform for implementation of almost any digital design. programmable sequential elements. and functional faults is targeted. [17]. and [25]. However. In this paper. size. [26]. In the technique presented in [5]. An open fault can be a programmable switch stuck-open or an open on a line segment. Preliminaries A FPGA is a 2-D array of configurable logic blocks (CLBs) and on-chip memory blocks within a programmable interconnection network with programmable I/O blocks on the periphery. the existence of faults in the system is first identified (application-dependent test) and faulty resources are precisely diagnosed afterwards (application-dependent diagnosis). CLBs consist of look-up tables (LUTs). [28]. In reprogrammable FPGAs. Section VI concludes the paper. In the multiplexer-based architectures. INTERCONNECT TESTING The interconnect resources in FPGAs can be categorized as inter-CLB and intra-CLB resources. wired bridging fault models (wired-OR and wired-AND) as well as dominant bridging faults are considered [4]. the logic testing technique is presented. A switch stuck-closed fault causes the switch to be permanently closed regardless of the value of memory cell controlling that switch.

14.g. The general form of a single-term function is a logic AND or a logic OR function with possibly some inversions at the inputs and/or the output. A fault is sensitized if the values of the signals at the fault site are different from faulty values. inputs and output of a LUT). An example of a single-term function is shown in Fig. . more than eight metal layers are exploited for the wiring channels in the interconnection network [6]. the bridging fault between and is detected. such that the values of the inputs of every function form the activating input of that function. VOL. Because the original term is the activating term and the value of the fault term is different from the value of the . the above mentioned faults in the inputs and output of that LUT will be detected. all the sensitized faults are detected. Now. 2 shows an example of a network of single-term functions with test vector 100011. All sensitized faults. that it is sensitized. and are detected. and are also detected. . and the input pattern . This function has only one maxterm. is expressed in Theorem 1.. the situation is a fault prop1 functions with a stuck-at fault at the fault agation path of site. Theorem 2: Consider a network of single-term functions . This means that if is a stuck-at fault is set to by applying . Fig. original term the fault-free output is different from the faulty output and the fault is detected. stuck-at. 1.. i. the bridging faults between and . and if is a bridging fault . Single-term function with activating input pattern. it is only sufficient to propagate the fault to the output. Theorem 1: For a single-term function . For this purpose. and for each pair net with value . all sensitized stuck-at and bridging faults are detected. will be bypassed. these logic elements. For a given fault list for the pin faults (e. Hence. all sensitized faults are detected. If this function is implemented in a LUT. Testing of intra-CLB interconnects along with logic resources are discussed in Section IV. This test vector results in activating inputs at the inputs of all single-term functions in this logic network.for all the nets with value and bridging faults for all pairs with opposite values. 9. This issue is addressed in Section III-B in details. if used in the original configuration. Since ( stuck-at-1 fault). only one function in the fault propagation path. is proven. the value of only one term in the truth table is different from the value of all other terms. which is an OR function with inversions at the second and fourth inputs. the fault effect will appear on all reachable primary outputs. [35]. with . the fault effect at the input of the first function on this path will be propagated to its output since the values appearing at the inputs of this function form its activating input. and are set to different values. The separation between inter-CLB and intra-CLB is made because in contemporary FPGAs the programmable logic resources are not limited to LUTs. the fault effect must be propagated from the fault site to the primary outputs. For inter-CLB interconnect testing. A. In order to detect . Corollary 1: If the conditions of Theorem 2 hold. and therefore. other logic resources such as carry generation/propagation logic and cascade chains are included in CLBs. for every is detected. the configuration of used logic resources (inclusive of intra-CLB interconnects) is kept unchanged while the configuration of inter-CLB interconnects as well as unused logic resources are changed. be detected by the activating input vector. no fault masking (causing undetected faults) can occur due to existence of this circuitry in the interconnect test mode. . Note that the sensitized faults (stuck-at and bridging) are totally dependent on the particular single-term function and the corresponding activating input vector. Moreover. stuck-at of nets. The proof is based on an induction on the number of functions on the fault propagation path from the fault site to the primary outputs. the term corresponding to the faulty inputs . The input combination corresponding to this specific minterm (or maxterm) is called the activating input. In other words. NO. 1. . For example in the exor are not sensitized and will not ample of Fig. In other words. The interesting testing property of single-term functions holds for any combinational network of single-term functions. For a single-term function. Then. if the applied input vector is the activating input. More than 80% of the transistors in an FPGA are used in the interconnect network. Therefore. and .e. the majority of the defects in an FPGA chip are located in the interconnection network. Based on the induction hypothesis. Hence. different single-term functions must be implemented to cover all faults. Testability of Single-Term Functions A single-term function is a logic function which has only one minterm or only one maxterm. . Proof: In order to detect the fault. . Since the fault is already sensitized. as expressed by the following theorem.. the activating input (0101) is applied. Also. Based sider a fault propagation path with on Theorem 1. the fault effect will appear at the primary outputs. SEPTEMBER 2006 Fig. These defects manifest themselves as open and short (bridging) faults. Con1 functions. Note that short to the power rails in the interconnects are considered as conventional stuck-at faults. The following theorem generalizes the previous example and expresses the conditions for detectability of faults in single-term functions. if the applied input vector is the activating input . 1. the fault term. . is different from the original term .1026 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. The fault effect appearing at the output of the first function along the path behaves as a stuck-at fault at the corresponding input of the second function along the path (the one connected to the output of the first function). Proof: Consider a fault (stuck-at or bridging fault) such . of logic resources is modified. . as is a single-term.e. are detected. i. The basis of the induction.

at most clock cycles are required to propagate this fault effect. the fault effect will be propagated to all primary outputs that are structurally reachable from the original fault site. 3. . Therefore. The preset values of the flip-flops are also shown. all possible combinations of multiple faults which are sensitized will be detected. Moreover. multiple stuck-at faults. which is the number of bistables along the longest path from any primary input to any reachable primary output. and L8. Therefore. Test Configuration Generation As explained in Section III-A. The preset value of FF2. where is equal to the maximum number of bistables from any path from primary inputs to the primary outputs (maximum sequential depth). level by level. 4. the maximum sequential depth is four. This fault will be captured in the next rank of bistables or will be propagated to the primary outputs in the next clock cycle. combination of stuck-at and bridging faults) will be propagated in the fault cones corresponding to each fault and appear at the reachable primary outputs. An example of a sequential circuit with single-term functions which satisfies all these conditions is shown in Fig. while the preset value of FF5 and FF7 must be set to 0. Therefore. L3. all sensitized faults will be propagated to the primary outputs and/or captured in bistable(s) by the first application of the clock pulse. Similar testability properties exist in sequential networks of single-term functions.TAHOORI: APPLICATION-DEPENDENT TESTING OF FPGAS 1027 Fig. . two test clock cycles must be applied and the test vector (1101) must remain unchanged during these two clock cycles. . Here. However. Proof: Based on Theorem 1 and 2. In other words. all the sensitized faults will be detected provided the same primary input vector is kept unchanged for clock cycles. As an example. hence. in order to propagate the fault effect captured in the first rank of the bistables in the first clock cycle. Corollary 2: If the conditions of Theorem 2 hold. the fault effects corresponding to multiple faults (e. Fig. and are followed by flip-flops in their corresponding logic blocks. 2. and FF9 should be set to 1. Based on Theorem 1 and 2. Sequential logic network of single-term functions. Sequential network of single-term functions with feedbacks. the behavior of this circuit in the first clock cycle is exactly similar to a com- Fig. Note that the same fault detection properties hold for a sequential network of single-term functions with feedbacks. to the primary outputs. 3. where is equal to the sequential depth of this circuit. Proof: Consider the logic cone(s) originating from the fault site(s) towards the primary outputs. single-term functions guarantee the detection of all sensitized faults if the appropriate pri- . 4. no fault masking occurs in such logic network with the given conditions for the primary input vector. . Any fault captured in a bistable behaves as a stuck-at fault at the data output of that bistable in the next clock cycle. B. Lemma 1: Consider a sequential network consisting of only single-term combinational functions and data flip-flops (D-FF) or latches. L4. FF4. In this example. L7. binational circuit satisfying those conditions.g. where L8 is not sequential and. The required number of test clock cycles is four. The number of these test clock cycles depends on the maximum sequential depth of the network. If the primary input vector and the preset values of the latches (or flip-flops) are set such that the value appearing at the inputs of each single-term function form its activating input. the fault effect appearing at the input of any function will be propagated to its output. Proof: Since the initial state of the bistables are set such that to satisfy the conditions of the Theorem 2. as the longest path of the circuit is through L2. Therefore. the initial state of the circuit.. multiple bridging faults. Logic network of single-term functions. consider a sequential network of single-term functions with feedbacks shown in Fig. The following lemma formally expresses these conditions for a sequential network. based on Theorem 2. the fault effect will be propagated to its output as well. for any function in the fault cone that the fault effect appears at its input. the same input vector must be applied to the circuit for a number of clock cycles to ensure that the fault effect captured in any bistable will be propagated to the primary outputs. which is set by the primary input vector and the present value of bistables (data flip-flop or latches) must satisfy the conditions of Theorem 2.

open. where configuration generation algorithm is is the number of LUTs and is the number of nets in the design. consider a sequential mapped design shown in Fig. 9. NO. The values of primary input nets form the test vector for that configuration. mary input vector is applied. the used CLBs are configured only as LUTs followed by flip-flops (if those flip-flops are originally used in the user configuration). Based on the fault-free values of the nets in each test configuration. It needs to be mentioned that the present value of individual bistables (flip-flops or latches) in the CLBs is part of the configuration data. which is equal to the maximum sequential depth of the design. SEPTEMBER 2006 Fig. we assume that nets extend from an LUT output to LUT input(s). 5 . and . shows these test vectors for six wires We exploit these Walsh vectors in FPGA application-dependent test generation in order to activate all faults. Fig. coverage is only As an example. its preset value is set to the value of the net driving its data input. bridging fault testing is not explicitly addressed in the test flow. based on its activating input value and the value of its output net. This circuit has 14 nets and Walsh codes give vectors for these 14 nets: the following 4 . Since each LUT is supposed to implement a single-term Fig. this test vector must remain unchanged during all test clock cycles. similar to the LUT configuration. In other words. Note that the computational complexity of this automatic test . each Walsh vector correspond to a test configuration and the same faults that are detected by that Walsh vector are sensitized and detected in the corresponding single-term test configuration. All nets in the mapped design are first considered as a row for the Walsh table. particularly for ASICs. These set of test configurations guarantee the detection of all stuck-at. detected in at least one test configuration. The number of all possible single stuck-at faults in a circuit is linear with the size of the circuit whereas the number of all pairwise bridging faults is quadratic with the size of the circuit. This is mainly due to the fact that finding an appropriate fault list for bridging faults is not as straightforward as that for stuck-at faults. For nets in the circuit. any additional logic resources in CLBs (such as carry generation/propagation XORs. and nets (wires) can be easily perpairwise bridging faults) for test vectors. the number of test configurations can be further reduced if a particular fault list (i. Here. In other words. open. 14. The pseudocode for the test configuration generation algorithm is shown in Fig.e. Fig. open. etc. activating all possible faults (stuck-at. Since this technique detects all possible pairwise bridging faults. inductive fault analysis methods have been proposed which try to extract a tractable fault list for bridging faults from physical layout information [8] by selecting a subset of bridging faults with high probability of occurrence. [15]. Note that only one test vector is used per each test configuration. the particular single-term function can be identified. and stuck-at faults for six wires. However. 7 with 4 LUTs and 14 nets. . These single-term functions are implemented in all LUTs used in the user design. As a result. Walsh codes (columns) are generated. However. Therefore. The required number of test configuration for 100% fault . [14]. hence. the value of each net is considered as the activating input value for the LUT driven by that net. For each flip-flop used in the design. For sequential designs. This list is quite intractable for large circuits.). there is no need to extract probable bridging fault list from the layout information using time-consuming inductive fault analysis methods. Each Walsh vector is converted into the fault-free values of nets in a test configuration. there is no need to control these flip-flops from primary inputs to change their present value.. The single-term functions implemented in the user LUTs correspond to a test configuration which detect the interconnect faults sensitized in that test configuration. 8 shows the test vectors and configurations generated using this approach for this design. This is done to avoid fault masking due to additional logic in the CLBs. will be bypassed. faults must be sensitized using a set of single-term functions and test vectors. Algorithm 1: Test vector and configuration generation algorithm. and bridging faults (all pairs) in the interconnects. For each vector. The objective is to come up with a minimum number of test configurations such that all faults in the fault list are sensitized and. Hence. These vectors formed using only are columns of binary representations of numbers 1 to using bits and called Walsh codes. the initial state of the flip-flops can be individually set as a part of FPGA configuration. these methods are very time-consuming and cannot be easily applied for large circuits. Testing for bridging faults has always been a challenging issue. However. 6. We first discuss the target fault list and then describe test vector and configuration generation method. To solve this problem. Since these test configurations target faults in inter-CLB interconnect. . 6 (Algorithm 1). This is because the number of test configurations is logarithmic to the number of faults in the fault list. if used. multipliers. VOL. smaller than the comprehensive fault list) is used. In order to detect all faults in the fault list.1028 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 5. function. single-term functions to be implemented in the LUTs of a mapped design can be obtained. This concept was originally used for bus interconnect testing [9]. Logarithmic test set to activate all possible bridging.

Therefore. . and single stuck-at faults) in the fault list. based on this theorem. Algorithm 1 will assign it to both 0 and 1 in two distinct test configurations. 0) in at least one test configuration. Since this is a single-term LUT L3 are . Test vector and configurations for the circuit of Fig. For example. or dominance). The preset value of each value is also determined based on the activating value of the net connected to its data input.r. Therefore. both stuck-at-1 and stuck-at-0 faults on all nets will be detected. such as L3 in the third configuration. then B becomes faulty. Algorithm 1 guarantees that 0. The configuration of each LUT is determined by the activating input values for its input nets and the value of its output net. 8. Based on that. 7.TAHOORI: APPLICATION-DEPENDENT TESTING OF FPGAS 1029 TABLE I TEST CONFIGURATIONS FOR ISCAS’89 CIRCUITS MAPPED INTO XILINX VIRTEX FPGAS Fig. D. one of these nets gets a faulty value.t. A becomes faulty. and bridging fault detection is given below. 1) Detection of Open and Stuck-At Faults: For any inter-CLB net in the design. Proof of Fault Coverage The proof of open. the open fault will also be detected. opposite values assigned into these nets (case 1: 1. Since the single-term implementations of all LUTs are derived from the assigned values of the nets. the conditions of Theorem 2 (as well as Lemma 1) will be satisfied. 7. opens. For example. in the first configuration. For this purpose. wired-AND. since each net is assigned to opposite values and both stuck-at faults on the net are detected. the fault list given in Section II-C is achieved. Sequential design with 4 LUTs and 14 nets. we figure out the upper bound on the number of required test configurations . we calculate the upper bound on the number of nets for an arbitrary design to be implemented on an FPGA device with LUTs. it should be of AND type and output net is . The last column shows the number of test configurations for 100% fault coverage (stuck-at. Depending on the values of these two signals in that test configuration and the particular bridging fault model (wired-AND. Each of these vectors is converted to a test configuration by interpreting the value of each net in each test vector as the activating value for that net. Upper-Bounds on Number of Test Configurations Here we estimate the maximum number of test configurations for application-dependent interconnect testing for any FPGA device. the activating input values of and its output is . or if it is a B-dominant fault. C. The third column shows the number of faults (pairwise bridging faults. Fig. or case 2: 1. wired-OR. Results Table I shows the number of test configurations required for comprehensive application-dependent testing of the ISCAS’89 sequential circuits mapped into Xilinx Virtex FPGAs. Since conditions of Theorem 2 are guaranteed to be satisfied by Algorithm 1. 100% fault coverage w. 2) Detection of Bridging Fault: Consider a bridging fault between two arbitrary nets A and B. and bridging faults). If the function. all pairwise wired-OR. The second column shows the number of CLBs used for mapping each circuit. Then. then the value of the faulty signal will be propagated to reachable primary outputs and detected. stuck-at. Moreover. in case 1 if it is a wired-AND fault. the single term function is OR type. and dominant bridging faults will be detected. opens.

In other words. and each LUT Assume that the FPGA device has has inputs. a common bus which is routed using available unused routing resources in the test configuration directly connects the test signals to each logic block. This approach can be framed as a BIST mechanism as described next. IV. it is practical to apply an exhaustive test (all possible input combinations) or a super-exhaustive test (all possible input transitions) for testing each used logic block. It is also possible to generate a super-exhaustive test to be able to also detect delay faults in the logic blocks by using two LFSRs generating all possible transitions. The test signals can be connected to the primary inputs for an off-chip test or to a test pattern generator implemented using unused on-chip resources for a BIST implementation. Table II shows these upper bounds on the number of interconnect test configurations for Xilinx Virtex II FPGA series [36]. the number of test configuration for 100% fault coverage ranges from 12 to 19. as described in Section III-B. parity predictor. 9. The response compactor can be combined with a response predictor such that a unique pass/fail signal can be generated. the response predictor can be precomputed and stored in the unused logic blocks (LUT bit locations or on-chip memory). 9. Note that the number of faults ranges from 3. whereas the configuration of the global interconnects and unused logic blocks are changed to exhaustively (and even super-exhaustively) test all used logic blocks. SEPTEMBER 2006 TABLE II MAXIMUM NUMBER OF TEST CONFIGURATIONS FOR XILINX VIRTEX II FPGAS Fig. BIST Scheme to detect all inter-CLB interconnect faults. Using this upper bound on the number of nets. namely test pattern generator.08 10 depending on the size of the FPGA device. This way. intra-CLB interconnects as well as logic resources. The key point of this approach is to keep the configuration of used logic blocks unchanged while applying test and observing the outputs of these logic blocks by exploiting inter-CLB interconnects and unused logic blocks. There are three main components in this BIST scheme. each logic block is tested in the same conditions it is used in the application configuration. A BIST version of this test scheme is shown in Fig. On the other hand. 1) Test Pattern Generator (TPG): A linear feedback shift register (LFSR) modified as a De Bruijn counter [21]. In this scheme. Since the user configuration of the logic blocks are known at the test time. changing the configuration of the inter-CLB interconnects and unused logic blocks allows us to facilitate the access to each logic block. each used logic block will be exhaustively (or super-exhaustively) tested while all these logic blocks are tested concurrently. NO. the upper bound on the number of test configurations based on the approach of Section III-B is as follows: . The size of the bus is equal to the number of logic block inputs to apply an exhaustive test for each logic block. Note that this is a loose upper bound since the LUT outputs are connected to the inputs of other LUTs. In this approach. LOGIC TESTING This section describes the approach for testing faults located inside the logic blocks. As can be shown in this table. This confirms that this approach is absolutely tractable for the large FPGAs. The global interconnect is reprogrammed in such a way that the test signals are routed to each logic block. 9. the outputs of many logic blocks can be observed using a small number of off-chip outputs. 14. and parity checker modules. The fourth column shows the number of all pairwise bridging faults associated with the maximum number of nets. and there are fanouts in the circuit. used by the mapped design. which is basigns to be mapped into this FPGA is sically allocating one separate net for each input and the output of every LUT in the FPGA. implemented in the unused logic blocks. Since the number of the inputs of each logic block is very small (less than ten inputs for each logic slice). Due to the small number of logic block inputs which usually ranges from 3 to 5 . This way. VOL.3 10 to 1. The logic block outputs are observed through an internal response compactor. The number of LUTs for each device is shown in the second column. The upper bounds on the number of nets are shown in the third column. A.1030 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. (a) Original configuration. generates the exhaustive sequence. (b) BIST configuration to test used logic blocks. The upper bound on the number of nets for any de. LUTs. This parallel connection allows testing the entire set of logic blocks concurrently. Note that these LUTs have four inputs ( 4). the original configuration of the used logic blocks is preserved.

the used logic blocks can be partitioned into two subsets and each subset can be tested in a separate test configuration. Hence. the second column gives the number . using available unused logic the function blocks. the BIST circuitry must be small enough to fit in the unused logic blocks. the size of the parity checker is a function of the size of the mapped design (the number of user logic blocks). Hence. since these test patterns are generated on-chip. the hardware resources (unused logic blocks and interconnect) already exist and any BIST circuitry is usually considered as free [29]. The number and the structure of the partitions can be determined based on the routing constraints. the number of used logic blocks in that test configuration is always less than the total number of logic blocks in the FPGA. then the parity checker implements are denoted by .TAHOORI: APPLICATION-DEPENDENT TESTING OF FPGAS 1031 per LUT (10–12 for a logic slice). If any odd number of logic blocks produce erroneous outputs. This parity predictor block stores the precomputed parity of all user logic blocks for each input combination. Therefore. So. The ex- Fig. the BIST circuitry (TPG. If there are user logic blocks in the design and their outputs . In this table. Alternatively. ample of partitioning using multiple LFSRs and parity checkers are the original used logic is shown in Fig. and associated routing) will definitely fit in unused logic blocks. The number of inputs of this parity checker is equal to the number of used logic blocks plus one. In the presented technique. Since the configuration of used logic blocks are preserved. [36]. B. All functional faults inclusive of stuck-at faults are covered by this test. the presented BIST architecture can be partitioned: instead of connecting the outputs of one TPG to all logic blocks. Test partitioning in logic BIST. However. the parity bit according to the expected outputs of all logic blocks is precomputed (obtained by simulation) and stored in the corresponding bit location of the LUT(s) implementing the parity predictor. [19] or segment verification testing [20] techniques can be used in which different segments (partitions) of the circuit under test (in this case user CLB) are exhaustively tested. However in the worst case. As a result. all the resources in the user logic blocks. The parity checker is the largest module in the BIST circuitry. 10 ( blocks). This could be a potential problem for very large designs. Moreover. the test signal cannot be routed to all logic blocks. an exhaustive or super-exhaustive testing of the logic block is performed with only a small number of vectors. unlike general combinational circuits where parity prediction can be expensive [23]. inclusive of all logic resources and local interconnect. the output of the parity predictor. Implementation When dealing with FPGAs and not with ASICs. the configuration of the parity predictor block stores the precomputed parity bits. such as carry generation and propagation logic. if the overhead of the BIST circuitry is small then it is not necessary to partition the circuit and use an extra test configuration. will be tested exhaustively. the availability of spare logic resources and the IOs. more than 20). 2) Parity Predictor: An additional logic block generates a parity bit of the outputs of the logic blocks used in the user application for each input combination of logic blocks. In order to solve this problem. Such segmentation reduces the total number of test vectors required for testing and make pseudoexhaustive testing tractable. The logic blocks in contemporary FPGAs contain other logic components besides LUTs. For each input combination of the logic blocks. One problem with this approach could be the routing congestion since the test signals (LFSR outputs) must be routed to the inputs of all used logic blocks. 10.. the errors will be detected by the parity checker. In each test configuration. it is desirable if the BIST circuitry can fit in the unused resources of the smallest FPGA device that it used to map the original user application. only one extra logic block is required to implement the parity prediction circuitry. In other words. TPG and parity predictor.g. and the width of TPG is chosen to generate tests for all used inputs of logic blocks. in which their sizes are independent of the size of the mapped design. if due to the routing complexity of the original design. 3) Parity Checker: The outputs of logic blocks and the parity block are checked using a parity checker. Unlike the other two modules. Table III shows the overhead of the BIST circuitry for ISCAS’89 sequential circuits mapped into Xilinx Virtex FPGAs. More parity bits (similar to Hamming codes and extensions) can be included to detect situations when even a number of logic blocks produce errors. the number of inputs of this parity predictor block is equal to the number of inputs of the logic blocks since all logic blocks obtain the same set of inputs from the test pattern generator in the test mode. multiple TPGs can be used and the outputs of each TPG are connected to only a subset of logic blocks. The simplest implementation of this parity checking module is a classical XOR tree. the test application time is also very small compared to off-chip test application alternatives. verification testing [18]. cascade chains. parity predictor. When the number of CLB inputs exceeds some limit such that the CLB cannot be exhaustively tested (e. all used logic resources and intra-CLB interconnect are tested. parity checker. Multiple parity checkers can also be used depending on the availability of I/O pins. in this case two test configurations are required for testing of used logic blocks and intra-CLB interconnects. and programmable multiplexers [3].

Therefore. no flip-flop is added to or removed from the original design in test configurations. 5) Compatibility: This technique relies only on reprogrammability of logic resources. The partial reconfiguration for loading next test configuration requires loading only those frames containing logic configuration bits. Hence. If the bridging fault only disturbs the configuration line and it then affects the state of a configuration bit. By performing high-resolution diagnosis. then it becomes a reliability and test quality issue. the original configuration of the routing resources of the design remains unchanged. which is a very small portion of the configuration data (less than 5% of the total configuration bits [36]). instead of saving the complete configuration data for each test configurations. this technique can be easily applied for various FPGA or CPLD families from a variety of programmable logic vendors [3]. 3) Test Time Reduction: The only difference among the test configurations is the contents of the LUTs. it results in a fault in the interconnect (open or bridging fault) or logic resources (logic fault). VOL. 9. The overhead is given in the fourth column as a percentage of the initial circuit implementation. V. The placement and routing of the original design are used for the test configurations. Some frames contain configuration bits for both logic and interconnects whereas others contain only interconnect configuration bits. then based on reliability constraints and criticality of the application. the user application is directly affected and depending whether this signal line is a global interconnect or inside a CLB. i. If the value of the signal line is disturbed. the third column represents the number of CLBs required to implement the entire BIST scheme with the LFSR. there might be a situation in which there is a fault in the resources used to test but not used for the application. the timing of the original design is preserved. For the circuits with zero overhead. only the LUT contents need to be stored for each test configuration (differential compression). Once the failure is diagnosed to be in a resource not originally utilized by the user application. 14. 4) Test Configuration Compression: As the only difference among the original design and the test configurations is the contents of LUTs. This situation never happens in our approach.e. Each CLB column is divided into a number of frames. The advantages of this approach are as follows. [36].1032 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. it was possible to map the entire BIST circuitry in the unused LUTs and logic slices of the partially-used CLBs by the original design. For example. DISCUSSION In the presented interconnect testing method. parity predictor. bridging faults between the resources decomposed into different test configurations cannot be detected [5]. SEPTEMBER 2006 TABLE III OVERHEAD OF BIST LOGIC TESTING of CLBs required to implement the original circuit. 1) Reduced Test Configuration Generation Effort: There is no need to perform placement and routing for generating the test configurations. Faults in the logic configuration bits affect the functionality of the logic blocks which will be detected in the logic BIST method (Section IV). Since the logic is modified for interconnect testing and the interconnect is modeled for logic testing. Also.. This feature exists in all families of reprogrammable (SRAM-based) FPGAs and complex programmable logic devices (CPLDs). 2) No Fault Missed: Since no partitioning of the resources over multiple configurations is performed. Note that a bridging fault between a signal line and a configuration line will directly or indirectly affect the user application. test configuration loading time can be drastically reduced by partial reconfiguration. Since the increase in the CLB usage is only a few percents. Note that each CLB in Xilinx Virtex FPGAs contains four LUTs and storage elements. The presented techniques for testing interconnect and logic resources are also able to detect the faults that occur in the configuration circuitry. only the preset values of some flip-flops are modified. If the defective resource is physically very close to user resources. For example. the design might be remapped such that the used resources by the application is not too close to the defective resources since the . the reconfiguration scheme in Xilinx FPGAs is framebased. it can be identified whether the defective resources are used in the user application or not. no fault is missed by decomposition. and parity checker as well as the circuit under test (original user configuration). The presented test methods are able to detect this fault. the entire BIST circuitry will still fit into the smallest FPGA device that the original design would fit. NO. The overhead for bigger circuits is much smaller. it will be detected in the first or second set of test configurations. achieving up to 20 test configuration compression ratio. The faults in the routing configuration bits manifest themselves as open and bridging faults in the mapped design which will be detected in the first set of test configurations (Section III).

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