R

E A L

W

O R L D

S

I G N A L

P

TM

R O C E S S I N G

Clocks and Timing Selection Guide
4Q 2003

. . . . . . . . . . . . . . . . . . .13 Selection Guide . . . . . . . . . . . contact your nearest TI Product Information Center listed at the end of this guide or select from the TI Worldwide options at: www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-V Phase Lock Loop Clock Driver for DDR II . . . .3-V 1:8 Zero Delay (PLL) x4 Clock Multiplier . . . . . . . . . . . . . . . . . . .9 Advanced PLL-Based Synthesizers Featured Products CDC7005 — Low Phase Noise Clock Synthesizer with Multiplying. . . . . To get answers to your technical questions.5 Clock Buffers/Drivers (Non-PLL) Featured Product CDCM1804—Differential and Single-Ended Output in One Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . In addition. Applications Support Do you need help selecting the timing devices for your board designs? Are you concerned about jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . zero-delay and other parameters affecting your timing budget? The TI technical application support team will work with you on TI’s clock and timer products and provide solution options for your boardlevel concerns. . . . . . . . . . . . . . .ti. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Clock Selection by Number of Outputs and Signaling Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . .4 Signal-Level Comparisons .15 Introduction Texas Instruments (TI) offers a wide selection of timing support devices. . . . . . . . . . . . .13 Real-Time Clocks (RTCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 CDCF5801 — Low-Jitter Clock Multiplier/Divider with Programmable Delay and Phase Alignment . . .5-V Phase Lock Loop Clock Drivers for Speeds up to DDR400 . . . . .15 For More Information . . . . . . . . . . . . . . . . . . . . . . . . . .8 CDCU877 — 1. . . . . . . . . . . . . . . . . . . . from non-PLL-based buffers to high-performance PLL clock synchronizers. . . . . . . . . . . . . . . . . . skew. . . . . . . . . . . . . . . . . . . . . . . .Table of Contents Overview Clock Distribution Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com/clocks 2 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 . . . . . . . . . . . . . . . . . . . Dividing and Jitter Cleaning . . . . . . . . . . . . . . . .7 PLL Clock Buffers (Zero-Delay) Featured Products CDCFR83/CDCR61A — 533-MHz Direct RambusTM Clock Generator with Phase Aligner and 400-MHz without Phase Aligner . . There is also a selection of clock drivers for memory applications. . . . . . . . . . . . . . . . . . . . . . . . .12 CDCVF25084 — 3. . . many of the PLL devices are spread spectrum clock (SSC) compatible. Included in the TI clock family are zero-delay PLL clock drivers and a series of PLL-based multipliers and dividers designed to help manage clock jitter and skew for a variety of standard signal levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Clock Selection by Speed and Signaling Type . . . . . . . . .6 Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Selection Guide . . . . . .8 CDCVF857/CDCV857B — 2. . . . . . . . . . . . . . . . . . . .12 Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Resources Literature . . . . . . . .

visit: www.Overview Clock Distribution Circuits Clock Buffers (Non-PLL) Pages 6-7 PLL Clock Buffers (Zero-Delay) Pages 8-9 Advanced PLL-Based Synthesizers Pages 10-12 Differential LVPECL/LVDS/ MLVDS Single-Ended LVTTL/CMOS x1 PLL-Based Buffers Multipliers/ Dividers Double Data Rate (DDR) Jitter Cleaners Crosspoint Switches Direct RambusTM PC Synthesizers Mixed-Signal Buffers LVTTL + LVPECL Real-Time Clocks (RTCs) Integrated Circuits Pages 13-14 Modules (Includes Battery and Crystal) Pages 13-14 For more information.com/clocks 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 3 .ti.

Zero-Delay PLL Clock Buffers — TI offers zero-delay buffers that target the latest memory standards (DDR400.0 V VOH = 1.135 V 310 mV 2.10 V VIH = VREF + 0.0 V VOL = 1.4 V 1100 mV 200 mV VOH = 2.825 V 700 mV VIL = VREF – 0.20 V 400 mV VIL = VREF – 0.25 V VOH = 1.5 V/ 0.5-V HSTL 2.925 V Signal-Level Definitions VREF = Input Reference Voltage VOH = High Output Voltage VIH = High Input Voltage VIL = Low Input Voltage VOL = Low Output Voltage VID = Differential Input Voltage VOD = Differential Output Voltage 4 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 .35 V 700 mV VREF = 1.75 V 0V VIH = VREF – 0.25 V 0.0 V 1.5 V/ 0. DDR-2 for example) as well as buffers that provide single-ended PLL functions for general-purpose applications.2 × VDD VOL = 0.4 V VOH = 2.475 V 250 to 450 mV VIL = 1.4 V VOL = 0.4 V VOH = 2.68 V VOL = 0. TI also offers low-jitter (<1-ps phase noise) multiplying and dividing functions in this category.7 × VDD VIH = 2.3 V 1.3-V LVDS 3.7 × VDD VIL = 0.6 V VIL = 0.5 GHz in a variety of fan-out options.8 V VOL = 0.8 V VIH = 0. TI also offers a mixed-signal option for customers needing differential signals (LVPECL) and single-ended signals (LVTTL/LVCMOS) from the same device.Overview (Continued) Clock Distribution Circuits Clock Buffers/Drivers (Non-PLL) — TI offers both single-ended and differential clock buffers that perform from below 200 MHz up to 3.2 V VOH = 1.2 × VDD 1.3-V LVPECL VIH = 2.75 V VOH = 1.3 V 2.0 V 0V 3.55 V 2.0 V VIL = 0.4 V VIH = 2.5-V/3.55 V VOL = 0.4 V VIH = 0.82 V 2.35 V VCM = 2.5-V CMOS Traditional CMOS LVTTL/LVCMOS 5-V TTL VOH = 2.68 V 0V VOL = 0.0 V VIL = 0.275 V 600 mV VX = 1. Advanced PLL-Based Synthesizers — The advanced PLL family consists of devices that assist with high-performance requirements such as cleaning the jitter from a noisy clock source (CDC7005) or providing phase adjustment (CDC5801).5-V SSTL-2 2. In addition to simple buffering.20 V VREF = 0.8 V VOL = 0. Signal-Level Comparisons 3.

Overview (Continued) Clock Selection by Speed and Signaling Type Signal Type SSTL-2/RSL (DDR/Rambus®) CDCV850 CDCV855 CDCU877 CDCV857B CDCR61A CDCVF857 CDCR83 SN65LVDS116 SN65LVDS117 SN65LVDS104 SN65LVDS105 SN65LVDS108 SN65LVDS109 CDCFR83 CDCLVD110 CDCM1804 CDCP1803 SN65CML100 CDCVF111 CDC5801 CDC7005 LVPECL/LVDS MLVDS/CML SN65MLVD201 SN65LVDS100 SN65LVDS101 CDCLVP110 LVTTL/HCMOS CDC2536 CDC2582 CDC509 CDCVF2509 CDCVF2505 CDC2586 CDC516 CDCVF2510 CDCVF25081 CDC536 CDC2509 CDC582 CDC2510 CDC586 CDC2516 CDCV304 CDCVF25084 CDCVF2310 CDC351 CDC2351 CDC950 CDC960 CDC318A CDC319 Clock Buffers/Drivers (Non-PLL)—Pages 6-7 PLL Clock Buffers (Zero-Delay)—Pages 8-9 CDC329A CDC337 CMOS/TTL CDC339 CDC328A CDC340 CDC391 CDC341 80 100 125 140 175 200 300 Advanced PLL-Based Synthesizers—Pages 10-12 400 500 533 750 800 900 1 – 3.5 GHz Maximum Speed (MHz) Clock Selection by Number of Outputs and Signaling Type Signal Type SSTL-2/RSL (DDR/Rambus®) CDCR61A CDCR83 CDCFR83 CDCV855 CDCV850 CDCV857B CDCVF857B CDCU877 SN65LVDS108 SN65LVDS109 CDCVF111 CDCLVP110 CDC5801 SN65LVDS104 SN65LVDS100 SN65LVDS101 LVPECL/LVDS SN65CML100 MLVDS/CML SN65MLVD201 CDCP1803 3-LVPECL CDCM1804 3-LVPECL 1-LVTTL LVTTL/HCMOS CDC7005 SN65LVDS105 CDCLVD110 SN65LVDS116 SN65LVDS117 CDCV304 CDCVF2505 CDC536 CDC2536 CDC582 CDC509 CDC2582 CDC2351 CDC2509C CDC586 CDCVF2509 CDC351 CDC2586 CDCVF2310 CDC319 CDCVF25084 CDCVF25081 CDC2510C CDCVF2510 CDC516 CDC2516 CDC318A CMOS/TTL CDC208 CDC328A CDC329A CDC391 CDC208 CDC337 CDC339 CDC340 CDC341 8 9 Clock Buffers/Drivers (Non-PLL)—Pages 6-7 PLL Clock Buffers (Zero-Delay)—Pages 8-9 Advanced PLL-Based Synthesizers—Pages 10-12 1 4 5 6 10 12 16 18 Number of Outputs 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 5 .

This output is delayed by 1 ns over the three PECL output stages to minimize noise impact during signal transitions. • VCC range 3.com/clocks 6 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 . very often less than 1 ps (rms). Key Features • Distributes one differential clock input to three LVPECL differential clock outputs and one LVCMOS single-ended output • Programmable output divider for two LVPECL outputs and one LVCMOS output • Low-output 20-ps (typical) skew for clock distribution applications for LVEPCL outputs. It is specifically designed for driving 50-Ω transmission lines.3 V (IMAX < 1. An advantage for buffers is they add a very low amount of jitter. visit: www. minimizing noise CDCM1804 Functional Diagram IN LVPECL IN Y0 Y0 Div 1 Div 2 Div 4 Div 8 Div 16 CMOS Y3 Y1 LVPECL Y1 VBB Bias Generator VDD – 1.0 to 3. datasheets and app.6 V • Signaling rate up to 800 MHz for LVPECL and 200 MHz for LVCMOS • Differential input stage for very wide common-mode range also provides VBB bias-voltage output for single-ended input signals • Receiver input threshold ±75 mV • 24-pin MLF package (4 mm x 4 mm) Get samples.5 mA) Y2 LVPECL Y2 S1 S0 Control EN For more information. the CDCM1804 offers a single-ended LVCMOS output Y3. 1-ns output skew between LVCMOS and LVPECL transitions. reports at: www.ti. Additionally.Clock Buffers/Drivers (Non-PLL) Non-PLL-based buffers will add a delay (skew) from the input to the output.ti.com/sc/device/CDCM1804 Featured Product CDCM1804 — Differential and Single-Ended Output in One Buffer The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and /Y[2:0] with minimum skew for clock distribution.

5 V) 0 to 200 MHz (VDD = 3.3 230 to 370 ps 2.3 1.0 ns 1.6 to 4.5 V 1.3 3.5 ns 2.97 5. TTL CMOS 0 to 80 MHz four 1/2x outputs.05 1.5 to 5.52 2.3 400 to 900 ps 400 to 900 ps 550 to 800 ps 700 to 1000 ps 250 to 1000 ps 40 ps 40 ps 20 ps 20 ps 50 ps –40 to 85 16/SOIC/TSSOP –40 to 85 16/SOIC/TSSOP –40 to 85 16/SOIC/TSSOP –40 to 85 16/SOIC/TSSOP –40 to 85 38/TSSOP 4.30 3.97 6. 3-state outputs CDC340 1:8 with fast tpd fanout TTL TTL/CMOS 0 to 80 MHz CDC341 1:8 with fast tpd fanout TTL TTL/CMOS 0 to 80 MHz CDC351 1:10 with fast tpd fanout.5 to 3.3 3.8 ns 100 ps @ 3.8 ns 3.2 ns 1.3 2.5 ns 1.5/3.2 to 4.10 2.5 V) 170 ps @ 2.52 2.5 ns 250 to 800 ps 1 to 2.6 to 4.7 ns 1. dollars in quantities of 1. LVTTL LVTTL/ 0 to 100 MHz 3-state outputs LVCMOS Crosspoint Switch SN65LVDS122 2x2 crosspoint switch LVDS LVDS 750 MHz SN65LVDT122 2x2 crosspoint switch LVDS LVDS 750 MHz w/terminators SN65LVCP22 2x2 crosspoint switch LVDS LVDS 500 MHz DS90CP22 footprint SN65LVCP23 2x2 crosspoint LVPECL LVPECL 1 GHz SN65LVDS1252 4x4 crosspoint LVDS LVDS 750 MHz Mixed-Signal Buffers CDCM18042 1:3 LVPECL + 1 LVTTL w/dividers 5 3.3 3.9 ns 3 to 4 ns 1.38 1.3 3.3 V –40 to 85 24/TSSOP (VDD = 2.3 3 ns (max) 450 to 600 ps 200 to 800 ps 400 to 900 ps 2.0 ns 1.0 ns 1 ns 250 ps 250 ps 500 ps 600 ps 900 ps 900 ps 600 ps 600 ps 500 ps 500 ps 100 ps –40 to 85 20/SOIC 0 to 70 48/SSOP 0 to 70 28/SSOP –40 to 85 16/SOIC/SSOP –40 to 85 16/SOIC –40 to 85 20/SOIC –40 to 85 20/SOIC/SSOP 0 to 70 0 to 70 0 to 70 –40 to 85 –40 to 85 20/SOIC 20/SOIC 24/SOIC/SSOP 16/SOIC 8/TSSOP 3.00 5.3 TBA TBA TBA 24/MLF For more information regarding test conditions used to obtain measurements.3 3.ti.4 ns Dual 1:4 fanout.3 V) CDC23513 1:10 with fast tpd fanout.5 GHz 0 to 900 MHz 0 to 650 MHz 1 GHz 1 GHz 315 MHz 315 MHz 311 MHz 311 MHz 311 MHz 311 MHz 750 MHz 100 MHz VCC (V) 3.7 to 5.S.6 to 4.3 3.3 3.24 1.9 ns 4 to 9 ns 3 to 9 ns 2.5/3.94 3. LVTTL LVTTL/ 0 to 100 MHz 3-state outputs LVCMOS CDC391 1:6 clock with selectable polarity TTL TTL 0 to 100 MHz and 3-state outputs CDCV304 1:4 fanout for PCI-X and LVTTL LVCMOS 0 to 140 MHz general apps CDCVF23103 1:10 clock with 2 banks for LVTTL/ LVTTL/ 0 to 170 MHz general-purpose apps LVCMOS LVCMOS (VDD = 2.00 4.70 2.5 to 5.41 3. see datasheets at: www.6 to 4. See Web for details.22 2.75 4.8 ns 500 ps 0 to 70 24/SOIC/SSOP 3.3 3.3 3.3 5 3. 3-state outputs CDC339 1:8 clock with four 1x outputs.8 to 3.3 3.97 2.4 to 3.5 ns (VDD = 3.6 to 4.000 2Expected release 4Q 2003.3 3.96 3.36 3.3 V) 3.2 to 4.8 to 4.1 to 4.com/clocks 1Suggested resale price in U. LVTTL LVTTL/ 0 to 100 MHz 3-state outputs LVCMOS CDC2351Q 1:10 with fast tpd fanout.2 to 3.6 ns 1.96 4.5 ns 1.3 3.36 2.3 5 5 5 5 5 5 3.95 See Web See Web LVPECL LVPECL+ LVTTL 800 MHz 3.80 3.00 7.6 to 10.22 4.3 3.5 3. 3With series output resistors Preview devices appear in BOLD BLUE 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 7 .3 3.3 to 2. TTL CMOS 0 to 80 MHz four 1/2x outputs. (°C) –40 to 85 –40 to 85 –40 to 85 0 to 70 –40 to 85 –40 to 85 –40 to 85 –40 to 85 –40 to 85 –40 to 85 –40 to 85 –40 to 85 –40 to 85 –40 to 85 # Pins/Pkg 24/MLF 32/LQFP 32/TQFP 28/PLCC 8/SOIC/MSOP 8/SOIC/MSOP 16/SOIC 16/SOIC 38/TSSOP 38/TSSOP 64/TSSOP 64/TSSOP 8/SOIC/MSOP 8/SOIC Price1 See Web 5. Temp.3 6.05 5.89 1.60 7.Clock Buffers/Drivers (Non-PLL) Selection Guide Device Description Differential Clocking CDCP18032 1:3 buffer with dividers CDCLVP110 CDCLVD110 CDCVF111 SN65LVDS100 SN65LVDS101 SN65LVDS104 SN65LVDS105 SN65LVDS108 SN65LVDS109 SN65LVDS116 SN65LVDS117 SN65CML100 SN65MLVD201 Single-Ended CDC208 CDC318A CDC319 CDC328A CDC329A CDC337 1:10 LVPECL/HSTL with selectable input clock 1:10 programmable LVDS clock 1:9 diff LVPECL clock 1:1 buffer 1:1 buffer 1:4 buffer 1:4 buffer 1:8 buffer Dual 1:4 buffer 1:16 buffer Dual 1:8 buffer 1:1 buffer 1:1 driver and receiver Input Level LVPECL LVPECL/ HSTL LVDS LVPECL LVDS LVDS LVDS LVTTL LVDS LVDS LVDS LVDS LVDS LVTTL/ MLVDS Output Level LVPECL LVPECL LVDS LVPECL LVDS LVPECL LVDS LVDS LVDS LVDS LVDS LVDS CML MLVDS/ LVTTL Frequency 0 to 800 MHz 0 to 3.3 3.5 ns 1.8 ns 500 ps –40 to 125 24/SOIC/SSOP 4.52 2. 3-state outputs TTL CMOS 0 to 60 MHz 1:18 clock with I2C control interface LVTTL LVTTL 0 to 100 MHz 1:10 clock with I2C control interface LVTTL LVTTL 0 to 140 MHz 1:6 fanout with selectable polarity TTL TTL 0 to 100 MHz 1:6 fanout with selectable polarity TTL CMOS 0 to 80 MHz 1:8 clock with four 1x outputs.89 4.2 ns 1.2 to 4.25 5.3 3.3 Propagation Delay TBA Output Skew TBA 30 ps 30 ps (typ) 50 ps — — 100 ps 100 ps 300 ps 550 ps 300 ps 550 ps — — Char.75 3.42 3.

Input clock resistors. reports at: www. Y9 Y9 FBOUT FBOUT Y5 CDCVF857/CDCV857B/CDCU877 — Phase Lock Loop Drivers for DDR and DDR-II Memory CDCV857B and CDCU877 are highperformance. This is best suited for applications that need to be synchronous.75-MHz crystal oscillator • CDCFR83 has a wide input-frequency range from 33 to 100 MHz • CDCFR83 has SSC tracking capability to reduce EMI Applications • CDCR61A is a 400-MHz differential clock source for the 800-MHz Direct Rambus clock system • CDCR83 and CDCFR83 provide clock multiplication and phase alignment for Direct Rambus memory systems Get samples. datasheets and app. high-speed Rambus® channel-compatible output pair and one single-ended output at half the crystal frequency.com/sc/device/CDCFR83 PLLCLK CLK CLKB PACLK REFCLK B PLL A Phase Aligner D 2 MULT0 MULT1 PCLKM SYNCLKN meet or exceed JEDEC spec for DDRI and DDRII. low-crossover-voltage. The CDCR83 and CDCFR83 provide clock multiplication and phase alignment for Direct RambusTM memory systems to enable synchronous communication between the Rambus channel and the ASIC clock domains. OS or OE Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 CLK CLK 10 kΩ to 100 kΩ PLL Y6 Y6 Y7 FBIN FBIN Y7 Y8 Y8 *The logic detect (LD) powers down the device when a logic low is applied to both CK and CK. datasheets and app. These devices 8 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 . low-skew and low-jitter zero-delay clock buffers that distribute a differential clock input pair to 10 differential pairs of clock outputs and one differential pair of feedback clock outputs.ti.ti. reports at: www. lowpower. Key Features • External feedback pins (FBIN.com/sc/device/CDCU877 CDCU877 Functional Diagram OE OS AVDD PLL bypass LD* Power Down Control and Test Logic LD* or OE Y0 Y0 LD*. Note.ti.PLL Clock Buffers (Zero-Delay) Zero-delay PLL-based buffers lock onto the incoming clock signal and provide an output synchronous to the input. DDRI PLL has power-down input. CDCR61A Functional Diagram PWRDWNB S0 S1 S2 STOPB Test MUX Bypass MUX ByPCLK Featured Products CDCFR83/CDCR61A — 533-MHz Direct RambusTM Clock Generator with Phase Aligner and 400-MHz without Phase Aligner The CDCR61A is an independent clock generator that provides one differential.com/sc/device/CDCV857B www. OE and OS inputs are for DDRII only. Key Features • CDCR61A requires an external 18. respectively.com/sc/device/CDCR61A www. FBINB) to synchronize outputs to the input clock • SSC-compatible • CDCV857B enters low-power mode when no CLK input signal is applied or PWRDWN is low • CDCVF857 is compatible with JEDEC DDR400 spec • CDCU877 can be used in single-ended input and output modes Applications • CDCV857B can be used in all applications requiring distribution of SSTL2level clock signals • CDCV857B is the clocking solution for DDR200/266/333 memory modules • CDCV857B is particularly well-suited for applications requiring clock distribution to onboard DDR DRAMs • CDCU877 is designed for the clocking DDRII memory module Get samples.ti.

SSC LVTTL CDCVF857 1:10 PLL differential clock driver for DDR 200/266/333 and DDR 400.3 3.5/ C-C: ±50 ps 2.5 C-C: ±75 ps (100 to 200 MHz) 2. see datasheets at: www.50 3. SSC 1:12 for SDRAM with 1/2x or 2x Price2 2. Temp.15 3.5 C-C: ±50 ps (100 to 180 MHz) 2. SSC 1For 2Suggested CMOS CMOS CMOS RSL6 RSL6 RSL6 1.11 4.3 3. SSC LVTTL CDCV857A 1:10 PLL differential clock for SSTL-2/ SSTL-2 60 to 180 DDR 200/266.3 267 to 400 3.77 0.06 48/TSSOP 48/TSSOP 56/µBGA4 48/TSSOP 56/µBGA4 48/TSSOP 40/MLF 52/µBGA4 40/MLF 3.5 C-C: ±50 ps (100 to 200 MHz) –50/+180 ps (133 MHz) 75 –40 to 85 48/TSSOP 1.8 C-C: ±40 ps (200 to 333 MHz) CDCU877 5 ±100 ps 50 –40 to 85 (100 to 180 MHz) ±100 ps (66 75 0 to 85 to 167 MHz) ±100 ps (100 75 0 to 85 to 180 MHz) ±50 ps (min/ 70 (typ) –40 to 85 max) (100 to 200 MHz) ±50 ps (min/ 40 (typ) –40 to 85 max) (100 to 200 MHz) ±50 ps (min/ 40 (typ) –40 to 85 max) (200 to 333 MHz) — ±100 ps ±100 ps — — — 0 to 85 –40 to 85 –40 to 85 28/TSSOP 1.07 2.46 SSTL-2 60 to 220 2.000 3With series output resistors 4µBGA = MicroStar BGATM 5Expected release 4Q 2003 6Rambus signaling levels New products appear in BOLD RED Preview devices appear in BOLD BLUE 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 9 .6 (100 to 200 MHz) SSTL-2 200 to 333 1. SSC LVTTL CDCV857B 1:10 PLL differential clock driver SSTL-2/ SSTL-2 60 to 200 for DDR 200/266/333.3 3. SSC 1:9 low-power PLL clock for PC 133 and beyond apps.PLL Clock Buffers (Zero-Delay) Selection Guide Input Level LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Output Frequency VCC Level (MHz) (V) LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL 25 to 125 25 to 125 25 to 125 25 to 125 25 to 125 25 to 125 25 to 125 25 to 125 25 to 125 24 to 200 10 to 200 50 to 175 50 to 175 3. SSC CDCR83 400-MHz Direct Rambus clock generator.5 ns Char.3 3.3 3.64 1.3 C-C: 50 ps (400 MHz) 267 to 533 3.27 2.S.3 C-C: ±100 ps (66 to 200 MHz) 3. SSC 1:8 low-power PLL clock with two banks.3 C-C: 40 ps (533 MHz) 300/400 16/TSSOP 24/SSOP 24/SSOP 1. SSC PLL for DDR-II SSTL-2/ LVTTL SSTL-2/ LVTTL 3.16 2.78 2.05 5. (°C) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 85 0 to 70 0 to 70 0 to 85 0 to 70 # Pins/ Pkg 24/TSSOP 48/TSSOP 24/TSSOP 24/TSSOP 24/TSSOP 24/TSSOP 24/TSSOP 24/TSSOP 48/TSSOP Device Description x1 PLL-Based Buffers CDC509 1:9 PLL clock CDC516 1:16 PLL clock CDC2509 1:9 PLL w/narrow loop BW CDC2509B3 1:9 PLL clock with SSC CDC2509C3 1:9 PLL clock with SSC CDC2510 CDC2510B3 CDC2510C3 CDC25163 CDCVF25053 CDCVF250813 CDCVF25093 CDCVF25103 1:10 PLL w/narrow loop BW 1:10 PLL clock with SSC 1:10 PLL clock with SSC 1:16 PLL clock 1:5 PLL clock driver for general-purpose.70 1.82 5.3 C-C: |65| ps (typ) (100 to 166 MHz) 3.8/ C-C: 100 ps (400 MHz) 3.3 3.82 2.07 2. SSC CDCFR83 533-MHz Direct Rambus clock generator.3 3. SSC 1:10 low-power PLL clock driver for PC 133 and beyond apps.52 CDC582/ LVPECL LVTTL 25 to 50/ CDC25823 50 to 100 Double Data Rate (DDR) CDCV850 1:10 PLL clock for DDR apps. dollars in quantities of 1.3 C-C: 70 ps (typ) (66 to 200 MHz) 3.5 C-C: ±30 ps (100 to 133 MHz) 2.com/clocks resale price in U.89 more information regarding test conditions used to obtain measurements. SSTL-2/ SSTL-2 60 to 140 SSC compatible with two-line universal serial interface CDCV855 1:4 (plus feedback pair) PLL SSTL-2/ SSTL-2 60 to 180 differential clock for DDR LVTTL apps.40 Direct RambusTM CDCR61A 400-MHz Direct Rambus clock generator-lite.50 2.ti.15 3.3 Jitter (Peak-to-Peak [P-P] or Cycle-to-Cycle [C-C]) P-P: ±100 ps (>66 MHz) P-P: ±100 ps (>66 MHz) P-P: ±100 ps (>66 MHz) P-P: ±80 ps (66 to 100 MHz) C-C: max |100| ps (66 to 100 MHz) P-P: ±100 ps (>66 MHz) P-P: ±80 ps (66 to 100 MHz) C-C: max |100| ps (66 to 100 MHz) P-P: ±100 ps (>66 MHz) Phase Error1 100/+480 ps –80/+400 ps –500 to –50 ps ±200 ps ±150 ps –500 to –50 ps ±200 ps ±150 ps –700/+180 ps (typ) — ±150 ps (66 to 200 MHz) ±125 ps (66 to 166 MHz) ±125 ps (66 to 166 MHz) ±500 ps Output Skew (max) (ps) 200 200 200 200 200 200 200 200 200 150 150 100 100 0.59 1.11 2. SSC CDCV857 1:10 PLL differential clock for SSTL-2/ SSTL-2 60 to 200 DDR 200/266.5 C-C: ±50 ps (100 to 180 MHz) 2.3 C-C: |65| ps (typ) (100 to 166 MHz) 3.3 P-P: 200 ps –40 to 85 8/TSSOP/ SOIC –40 to 85 16/TSSOP/ SOIC 0 to 85 24/TSSOP 0 to 85 0 to 70 24/TSSOP 52/QFP 2.05 2.3 3.

Phase Adjustment — Some applications require phase alignment to adjust for delays within a system (varying lengths on a backplane can sometimes require phase adjustment). Internal PLL-based devices in general will add more jitter than devices that synchronize to an external VCXO. however.com/sc/device/CDC7005 CDC7005 Functional Diagram OPA_IN OPA OPA_IP STATUS_REF STATUS_VCXO Hold REF_IN LVCMOS Input Program Divider M Program Divider N CTRL_LE CTRL_DATA CTRL_CLK NPD NRESET SPI LOGIC PECL 2 LVTTL VI Reference I_REF Program Delay M Program Delay N PFD Charge Pump STATUS_LOCK CP_OUT OPA_OUT MUX_SEL 5 P Divider 5 /1 /2 VCXO_IN PECL Input VCXO_INB /8 5 /16 /4 5 PECL MUX0 PECL Latch PECL Out Y0 Y0B PECL MUX1 PECL Latch PECL Out Y1 Y1B PECL MUX2 PECL Latch PECL Out Y2 Y2B PECL MUX3 PECL Latch PECL Out Y3 Y3B 5 For more information. In addition to synchronizing the system clock.Advanced PLL-Based Synthesizers System Clock Synchronizers — A synchronizing clock can be used to take a system clock signal (from a backplane. Featured Products CDC7005 — Low Phase Noise Clock Synthesizer with Multiplying. Dividing and Jitter Cleaning Key Features • High-performance 1:5 PLL clock synchronizer and jitter cleaner • Programmable multiplier and divider • Two clock inputs: VCXO_IN clock is synchronized to REF_IN clock • VCXO is external to allow for flexible application frequencies • Supports five differential LVPECL outputs • Efficient jitter cleaning from low PLL loop bandwidth • Low-phase noise characteristic • Programmable delay for phase adjustments • Packaged in a 64-pin BGA (0.ti. The jitter added for PLLbased devices will vary. Clock synthesizers are very common in the PC space.8-mm pitch — ZVA) • Industrial temperature range –40°C to 85°C Get samples. The key difference is the level of jitter the application can tolerate. the performance of the latter is dependent on the VCXO chosen and design of the feedback path. synchronizers can also remove jitter from the clock source. reports at: www. clock division can be accomplished through internal logic dividers in either non-PLL buffers or PLL-based buffers. visit: www.com/clocks PECL MUX4 PECL Latch PECL Out Y4 Y4B 10 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 .ti. The jitter on non-PLL-based buffers will be very close to the jitter of the source clock. Clock Dividers — Unlike multipliers. Clock Multipliers — Clock circuits can multiply a frequency either by having an internal PLL or by synchronizing the input frequency to a faster voltagecontrolled crystal oscillator (VCXO). Synthesizers — Synthesizers typically take an oscillator as a direct input and then generate several frequencies through internal PLLs. for example) and provide outputs to a subsystem at the same frequency or an even multiple/divisor of that frequency. datasheets and app.

very often subsystems (especially those with SerDes or data converters) will require a very low-jitter clock source.72 MHz) M N Example Values 0 ps PFD 0 ps CP Loop Filter Need to Jitter Clean and/or Synchronize a Clock Signal? REF_IN Y YB Jittery Clock Clean Clock SPI MUX Very often a system clock will develop jitter after traveling over a backplane. Example Values SPI MUX VCXO (120 MHz) P /1 /2 /4 /8 /16 MUX MUX MUX MUX MUX 120 MHz 120 MHz 60 MHz 30 MHz 15 MHz LVPECL Outputs 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 11 .25 MHz LVPECL Outputs Need Overall Phase Adjustment to Keep a System in Sync? CDC7005 for Phase Adjustment CDC7005 OPA REF_IN Y YB Y YB Phase Delayed Phase Advanced REF_IN (120 MHz) M N 2. the CDC7005 will maintain a very low-jitter output.76 MHz 122. Whether multiplying or dividing.88 MHz 61.Advanced PLL-Based Synthesizers (Continued) Featured Products (Continued) Applications CDC7005 as a Clock Synchronizer/Jitter Cleaner CDC7005 OPA REF_IN (30. VCXO (245.5 MHz 11.72 MHz 15. 8 or 16 from the VCXO frequency.75 ns PFD 0 ps CP Loop Filter Sometimes the phase of a clock needs to be adjusted to account for delays in a system (sometimes due to trace length over a backplane). SPI MUX VCXO (180 MHz) Low Noise P /1 /2 /4 /8 /16 MUX MUX MUX MUX MUX 180 MHz 90 MHz 45 MHz 22.44 MHz 30. In addition to synchronizing the system clock. The CDC7005 can provide up to 2. However.36 MHz LVPECL Outputs (<1 ps RMS jitter possible) Multiply or Divide with Low Jitter REF_IN Y YB 60 MHz CDC7005 as a Multiplier/Divider CDC7005 180 MHz REF_IN (60 MHz) 250 750 Example Values 0 ps PFD 0 ps CP OPA Low BW Loop Filter The VCXO selected can be at a higher frequency than the input clock.76 MHz) P /1 /2 /4 /8 /16 MUX MUX MUX MUX MUX 245.75 ns of phase adjustment. 2. the CDC7005 can also clean the jitter from that system clock source. Each output can then be divided by 1. 4. which results in the input clock being multiplied to the outputs.

reports at: www. x2.. datasheets and app. LVDS and LVTTL • Spread spectrum clock tracking ability to reduce EMI • Industrial temperature range: –40°C to 85°C Applications • Phase adjustment • Low-jitter multiplier • Low-jitter divider Get samples.6-mUI programmable bidirectional delay steps • One single-ended input and one differential output pair (input tolerates LVPECL and LVTTL) • Output can drive LVPECL.5 MHz to 45 MHz • Output frequency range: 10 MHz to 180 MHz • LVCMOS/LVTT I/O compatible • Low jitter (cycle-cycle): ±120 ps over the range 75 MHz to 180 MHz • Distributes one clock input to two banks of four outputs 25Ω 25Ω 25Ω 1Y3 8 S2 9 S1 Input Select Decoding 6 25Ω 2Y0 2Y1 2Y2 2Y3 7 25Ω 10 25Ω 11 25Ω 12 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 . It also allows delay or advance of the CLKOUT/CLKOUTB with steps of 2.com/sc/device/CDCVF25084 CDCVF25084 Functional Diagram 16 1 Divide by 4 FBIN CLKIN PLL MUX 25Ω 2 1Y0 3 1Y1 14 1Y2 15 CDCVF25084 — 3..240) (0..280) MHz CLKOUTB Delay (Step Size = 1/(384 x f)) VDDREF/2 01 00 11 Div2 Div4 Div8 CLK VDDO DLY+ DLY– 10 Div16 2 MULT[0:1] VDDPD/2 2 P[1:2] DLYCTRL LEADLAG (0. Key Features • Low-jitter clock multiplier x1.280) MHz MHz • Auto frequency detection to disable device (power-down mode) • Operates from single 3.3-V supply • Industrial temperature range –40°C to 85°C • 25 on-chip series damping resistors • No external RC network required • Spread spectrum clock compatible (SSC) • Available in 16-pin TSSOP package Get samples..ti.5 to 240 MHz – Output frequency: 25 to 280 MHz • 2. reports at: www. x4 or x8: – Input frequency: 12.com/sc/device/CDCF5801 CDCF5801 Functional Diagram PWRDNB P0 CDCF5801 StopB Control VDDP GNDP VDDPA GNDPA Phase Aligner 00 Div2 11 Div4 10 Div8 01 GNDO REFCLK (12.ti.5..3-V 1:8 Zero Delay (PLL) x4 Clock Multiplier Key Features • Phase-locked loop-based multiplier by four • Input frequency range: 2. datasheets and app..Advanced PLL-Based Synthesizers (Continued) Featured Products (Continued) CDCF5801 — Low-Jitter Clock Multiplier/Divider with Programmable Delay and Phase Alignment The CDCF5801 provides clock multiplication and division from a reference clock (REFCLK) signal.6 mUI through a unique phase aligner..240) MHz PLL CLKOUT (25..

05 5. The address/data multiplexed devices have fewer pins but may require more logic to interface. 3-state outputs CDCVF25084 1:8 low-power 4x multiplier LVTTL with two banks.05 4. Temp.5 to 62. LVTTL Division mode = 75 ps LVTTL LVTTL LVTTL LVTTL LVTTL TTL LVTTL 25 to 100 25 to 100 25 to 100 25 to 100 25 to 100 25 to 100 10 to 180 3.80 ±500 ps ±500 ps ±500 ps ±500 ps ±500 ps ±500 ps — 500 500 500 500 500 500 150 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 –40 to 85 28/SSOP 52/TQFP 52/TQFP 28/SSOP 52/TQFP 52/TQFP 16/TSSOP 1.52 5.89 4.30 more information regarding test conditions used to obtain measurements. the memory address lines and data lines share the same pins. dollars in quantities of 1. (°C) –40 to 85 –40 to 85 # Pins/ Pkg 64/BGA 24/SSOP Device Description Jitter Cleaners CDC7005 Jitter cleaner.00 2.or 5-V Operation — The RTCs can run from a 5-V or 3-V rail.05 2.000 3With series output resistors New products appear in BOLD RED Preview devices appear in BOLD BLUE Real-Time Clocks (RTCs) Data Bus Type — There are two bus types available: (1) address/data multiplexed and (2) parallel. the address lines and data lines are separate and the interface is the same as a static RAM. LVDS/ PA active = 70 ps.3 C-C: ±100 ps (66 to 180 MHz) — — –40 to 85 24/SSOP 2.5 PA active = 70 ps. 5 LVPECL LVCMOS Phase Aligners CDC5801 Multiplier/divider with LVCMOS programmable delay and phase alignment CDCF5801 Multiplier/divider with LVCMOS programmable delay and phase alignment Multipliers/Dividers CDC536 1:6 PLL clock with 1/2x or TTL 2x output.3 P-P: PA bypassed = 40 ps.S. With (2). 3-state outputs CDC25823 1:12 PLL clock with 1/2x LVPECL or 2x output CDC25863 1:12 PLL clock with 1/2x or TTL 2x output.3 P-P: 200 ps 3.52 5. SSC 1For 2Suggested Price2 10.3 P-P: 200 ps 3.3 P-P: 200 ps 3. LVTTL Division mode = 75 ps LVPECL/ 25 to 280 3.com/clocks 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 13 . see datasheets at: www. • Onboard NVSRAM • VCC tolerance • Package type Features • Real-time clock counts seconds through centuries in BCD format • Complete surface-mount solution with SNAPHAT TM package • Less than 500 nA of current consumption in battery backup mode • Clock accuracy (modules) better than 1 minute per month • Up to 512K x 8 of onboard NVSRAM • 3.3 P-P: 200 ps 3. 3-state outputs CDC582 1:12 PLL with 1/2x or LVPECL 2x output CDC586 1:12 clock with 1/2x or LVTTL 2x output. With (1). LVDS/ 12. visit: www.3 Jitter (Peak-to-Peak [P-P] or Cycle-to-Cycle [C-C]) — Phase Error1 — — Output Skew (max) (ps) 200 — Char.ti. 3.3 P-P: 200 ps 3. CPU Supervisor — Some parts include a full CPU supervisor that provides: • CPU reset (power-on and push-button) • Power-fail interrupt • Watchdog timer • Non-volatile control for additional NVSRAM The integration of the supervisor on the RTC can reduce the component count in a design.ti. 3-state outputs CDC25363 1:6 PLL clock with 1/2x or TTL 2x output.or 5-V operation • Fully integrated CPU supervisor For more information.3 P-P: PA bypassed = 40 ps.Advanced PLL-Based Synthesizers Selection Guide Input Level Output Level LVPECL Frequency VCC (MHz) (V) 10 to 800 3.com/clocks resale price in U.3 P-P: 200 ps 3.80 LVPECL/ 150 to 500/ 3.

00 2.20 4.35 10.30 2The resale price in U.50 9.35 2.00 3.79 3.20 2.Real-Time Clocks (RTCs) Family of Products Integrated Circuits Address/Data Multiplexed On-Chip NVSRAM On-Chip & External RAM Control 5V — bq4285 3V — bq4802LY Parallel External RAM Control 5V — bq4845 — bq4845Y — bq4802Y 3V — bq3285LD — bq3285LF 5V — bq3285 — bq3285E Modules (Includes Battery and Crystal) Address/Data Multiplexed On-Chip NVSRAM On-Chip & External RAM Control 114 Bytes — bq4287 — bq4287E On-Chip NVSRAM No CPU Supervisor — bq4830Y — bq4850Y CPU Supervisor — bq4822Y — bq4832Y — bq4842Y — bq4852Y Parallel On-Chip & External RAM Control 3V — bq4802LY 5V — bq4847 — bq4847Y — bq4802Y 114 Bytes — bq3287 — bq3287A 242 Bytes — bq3287E — bq3287EA Real-Time Clocks (RTCs) Selection Guide Device Parallel Interface bq4802Y bq4802LY bq4845 bq4845Y bq4830Y bq4822Y bq4832Y bq4842Y bq4852Y bq4847 bq4847Y bq4850Y Address/Data Multiplexed bq3285 bq3285E bq3285LD bq3285LF bq3287 bq3287A2 bq3287E bq3287EA2 bq4285 bq4285E bq4287 1Suggested VCC Level (V) 5 3 5 5 5 5 5 5 5 5 5 5 5 5 3 3 5 5 5 5 5 5 5 VCC Tolerance (%) 10 10 5 10 10 10 10 10 10 5 10 10 10 10 10 10 10 10 10 10 10 10 10 CPU Supervisor Yes Yes Yes Yes No No No No No Yes Yes No No No No No No No No No No No No Onboard NVSRAM No No No No 32K x 8 8K x 8 32K x 8 128K x 8 512K x 8 No No 512K x 8 114 bytes 242 bytes 242 bytes 240 bytes 114 bytes 114 bytes 242 bytes 242 bytes 114 bytes 114 bytes 114 bytes External NVSRAM Control Yes Yes Yes Yes No No No No No Yes Yes No No No No No No No No No Yes Yes Yes Package 28-pin SOIC.50 12.95 25.95 4.S.35 2.00 2.79 3. dollars in quantities of 1.79 3.35 2.50 14.00 2.000 "A" versions have a RAM clear input pin 14 Clocks and Timing Selection Guide Texas Instruments 4Q 2003 .79 2.00 4.50 29. TSSOP or SNAPHAT 28-pin SOIC or TSSOP 28-pin SOIC 28-pin SOIC 28-pin DIP Module 28-pin DIP Module 32-pin DIP Module 32-pin DIP Module 36-pin DIP Module 28-pin DIP Module 28-pin DIP Module 32-pin DIP Module 24-pin SOIC 24-pin SOIC or SSOP 24-pin SSOP 24-pin SSOP 24-pin DIP Module 24-pin DIP Module 24-pin DIP Module 24-pin DIP Module 24-pin SOIC 24-pin SOIC 24-pin DIP Module Price1 2.00 2.

ti.ti. B010203 © 2003 Texas Instruments Incorporated Printed in the U. HSTL. Phase Offset (Phase Error) Design and Layout Guidelines for the CDCVF2505 Clock Driver Design Considerations for TI’s CDCV857/CDCV857A DDR PLL Filtering Techniques: Isolating Analog and Digital Power Supplies in TI’s PLL-Based CDC Devices HSTL Clock Buffer Using the CDCV850 Interfacing Between LVPECL. Description Defining Skew. All other trademarks are the property of their respective owners. No.Resources Literature The literature below is available to download as Acrobat Reader files at www-s.com/sc/pic/americas.com Internet support. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Incorporated.htm Europe.com/clocks or contact your nearest TI Product Information Center listed below. Dallas. customer’s applications or product designs. TI assumes no liability for applications assistance.jp/pic support.ti. and CML Real-Time Clock Notes U-500 Using the bq4845 for a Low-Cost RTC/NVSRAM Subsystem U-502 Time-Base Oscillator for RTC IC U-503 Using the bq3285/7E in a Green or Portable Environment Using RAM Clear Function with bq3285/bq3287A RTCs Lit.ti.com/clocks by selecting an icon for Application Notes.A.ti. LVDS. and Africa +32 (0) 27 45 55 32 +358 (0) 9 25173948 +33 (0) 1 30 70 11 64 +49 (0) 8161 80 33 11 1800 949 0107 800 79 11 37 +31 (0) 546 87 95 45 +34 902 35 40 28 +46 (0) 8587 555 22 +44 (0) 1604 66 33 99 +(49) (0) 8161 80 2045 epic@ti. or infringement of patents.htm Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale.com TI Semiconductor KnowledgeBase Home Page support. The publication of information regarding any other company’s products or services does not constitute TI’s approval. Middle East. scaa055 scaa045 scaa054 scaa048 scaa058 scaa056 scaa047 scaa051 scaa043 scaa050 For More Information For more information. Real World Signal Processing. scaa049 scaa052 scaa059 scaa062 slua031 slua051 slua094 slua052 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page Japan Fax Internet/Email International Domestic International Domestic +81-3-3344-5317 0120-81-0036 support.com/sc/pic/japan.com/sc/knowledgebase Product Information Centers Americas Phone Fax Internet/Email Phone Belgium (English) Finland (English) France Germany Israel (English) Italy Netherlands (English) Spain Sweden (English) United Kingdom Fax Email Internet +1(972) 644-5580 +1(972) 927-6377 support. Propagation-Delay.S. software performance. please visit www.htm Asia Phone International +886-2-23786800 Domestic Toll-Free Number Australia 1-800-999-084 China 108-00-886-0015 Hong Kong 800-96-5941 Indonesia 001-803-8861-1006 Korea 080-551-2804 Malaysia 1-800-80-3973 New Zealand 0800-446-934 Philippines 1-800-765-7404 Singapore 800-886-1028 Taiwan 0800-006800 Thailand 001-800-886-0010 Fax 886-2-2378-6808 Email tiasia@ti.com/sc/pic/euro.com/sc/pic/asia. Description Using TI’s CDC111/CDCVF111 with TLK3104SA Serial Transceiver for Gigabit Ethernet and Backplane Applications Using TI’s CDCV304 with Backplane Transceiver (TLK1201/1501/2201/2501/2701/2711/3101) AC-Coupling Between Differential LVPECL. the black/red banner and MicroStar BGA are trademarks of Texas Instruments. HSTL and CML DC-Coupling Between Differential LVPECL.ti.com/sc/techlit/litnumber by replacing litnumber with the Literature Number shown below.ti. and CML Jitter Performance of TI’s CDC111/CDCVF111 Output Jitter of CDC111/CDCVF111 in an ASIC Networking Application Using the CDC857 and CDCV850 to Transform a Single-Ended Clock Signal Into Differential Outputs Using TI’s CDCVF111 with SLK2501 Serial Gigabit Transceiver for SONET and Gigabit Ethernet Applications Lit. Other literature is available at www.ti.ti. LVDS. by ____________________. No.htm www. warranty or endorsement thereof.tij. LVDS. TX Printed on recycled paper.co.com support. 4Q 2003 Texas Instruments Clocks and Timing Selection Guide 15 .

R E A L W O R L D S I G N A L P TM R O C E S S I N G Navigate Our Website Faster to Find the Information You Need Visit: analog. TX PERMIT NO. POSTAGE PAID DALLAS. Just click on the icon of the product type you are interested in and get easy access to datasheets.com TI’s new and improved Web interface makes it faster and easier for you to find the tools you need to speed your designs to completion. software emulation tools and technical support. Box 954 Santa Clarita. evaluation modules (EVMs). Samples shipped within 24 hours of receiving the order (please allow extra time for delivery in China).S. 2758 SLYB104 .ti. CA 91380 Address service requested PRSRT STD U. Need samples fast? Order these online from the product folder or by phone at 1-800-477-8924 (in North America).O. Texas Instruments Incorporated P. application reports. samples. See page 15 for contact information for other regions.