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A Fast Simulation Approach for

Inductive Effects of VLSI
Interconnects

• Abstract
• Introduction
• What is Interconnect?
• Inductance effects on Bus wires
• System overview
• Modeling for accurate inductive effect
• Simulation examples
• Conclusion
• References

in the workplace. Results ABSTRACT:Modeling on-chip show that this simulation approach is inductive effects for interconnects of upto 68x faster than SPICE while multiGHz microprocessors remains maintaining 95% accuracy.Electronics as we know it today linearity of drivers in conjunction with is characterized by reliability. a fast and accurate time- disciplines. The advances will be made in the next proposed method models the non- decade. the effect of this field in a relatively short time and it non-ideal ground and de-coupling is also certain that even more dramatic capacitors in a bus structure. challenging. ground bounce simulations. non-ideal integrated circuit has made possible the ground and de-coupling capacitor design of powerful and flexible models enable accurate signal and . extremely low weight and waveforms at each driver output are volume. and in domain transient analysis approach is leisure activities. This is true on inductive effect.The simulation. and low cost with an ability to incorporated into an interconnect cope easily with a high degree of reduced-order simulator for fast transient sophistication and complexity. Linearized dissipation. which captures the non- The revolutionary changes have taken in linearity of circuit drivers. In addition. ignoring the nonlinear behavior of drivers in a fast linear circuit There is no doubt that our daily lives are significantly affected by electronic simulator results in large errors for the engineering technology. SPICE simulation of these effects is very slow because of the large number of mutual inductances. low power specific bus geometries. presented. in our professional In this paper. I: INTRODUCTION Meanwhile. the domestic scene.

Now we are display a scaling behavior that is beginning to see the emergence of the different from the active devices. . 2.The very first An interconnect in VLSI design integrated circuit (IC) emerged at the consists of actual path between global beginning of 1960 and since that time routs and actual circuit. Their fifth generation. effects: capacitive. large have a dominant influence on the circuit scale integration (LSI). processor which provide high intelligent and adaptable devices for the user. This situation is 1980 1990 2000 Technology Invention Discrete SSI MSI aggravated by the fact that of the components improvements in technology make the transistor production of ever-larger die sizes Approximate 1 1 10 100-1000 number of economically feasible. Junction Planar Counters. are reduced and dominate the performance in submicron Year 1947 1950 1961 1966 1971 technologies. All three have a dual effect on Reduction in . which Ease of . introduces R. While there have already been four generations interconnect the physical metal lines of ICs: small scale integration (SSI). inter connect wire and in the associated products transistor devices. . Multiplexers parasitic effects. also this parasitic effects integration (VLSI).L. over years 1. An introduction of noise. very large scale operation. resistive and flops inductive. simple medium Interconnect affects the reliability of the circuit.C parameters that can medium scale integration (MSI). flip. ultra large scale effect increases as device dimensions integration (ULSI). 12μm 7μm-10μm feature size circuit behavior. An increase in propagation delay. . which results in transistors an increase in the average length of an per chip Typical .Interconnect wire and diode logic adders introduces three types of parasitic gates. II: WHAT IS The vast majority of present day electronics is the result of the invention INTERCONNECT of the transistor in 1947.

This paper figure 1. ignoring the parasitic when only the victim signal switches. a fast and yet accurate time- domain transient simulation including inductance is desirable. inductance of on-chip interconnects may Due to the long-range nature of the cause inaccurate delay and noise mutual inductive coupling. the additive inductive coupling from all number of mutual inductances is n (n- parallel wires.1 shows a victim’s far-end EFFECTS ON BUS waveform in a bus structure on three WIRES layers. When all the signals switch in the same direction. the simple truncation of mutual inductance couplings in an inductance matrix can lead to large simulation errors and even result in an unstable circuit model. There is no significant inductive effect when only the victim switches. SPICE runs very slowly and is not feasible for large industry examples.and Therefore. modeling and transient simulation for onchip buses.III: INDUCTANCE Figure. 1)/2. and significant wires in a bus are cut into n segments inductive noise. A stage-delay pushout is due to focuses on fast and accurate inductance inductance. the proposed return limited mutual inductance between parallel bus assumption may not be valid for on-chip wires can cause additional timing delay bus simulations.Meanwhile. This is due to the for the RLC distributed effect. Because of the in-efficiency of SPICE simulation. wider estimations. Because of the huge number of mutual inductances in a bus. may switch simultaneously. overshoots. if all the variations. Inductive effects are quite buses can cause more inductive evident in on-chip buses where signals problems for delays and noise. Self. . there are delay push-out In multi-gigahertz microprocessor and over-shoots compared with the case designs. In addition.

work on improving the efficiency of Meanwhile. linearity of drivers is one of the keys to the mutual inductance is not included. works in terms of pre-characterizing the parameters of a time varying Thevenin In this paper. the non-linearity of devices simulating interconnects including plays an important role in inductive inductance. It effective capacitance load values. The efficient Ceff model effects. While these chip buses is proposed. the non-linearity of drivers. the To avoid the expensive procedure in the effect of non-ideal ground and de- above model is due to a Padé coupling capacitors (decaps).e. it is the mutual a bus structure. and the approximation. accurately model the inductive effect in For on-chip buses. Kashyap proposed a 3-D geometries of interconnects. There is no reported work on fast method for RC interconnect simulation simulation for the impact of device has been extended to RLC interconnect nonlinearity on the mutual inductive simulation. packaging worse and jeopardizes the signal parasitics (i. captures the self-/mutual inductance effect. synthesis procedure for RLC circuits To accurately model the inductive effect. that guarantees a realizable reduced a fast and practical order circuit using the first four moments precharacterization technique for on- of the input admittance. non-ideal grounds) are integrity. In addition. Pre-characterization needs to include the mutual inductance for each specific bus IV:SYSTEM structure. The non- methods work well with self-inductance. the Ceff method OVERVIEW and its related techniques are based on the timing analysis theory and may not There has been some previously reported work properly with noise estimations. an efficient transient voltage source model (in series with a analysis tool to model the RLC effect fixed resistor) over a wide range of on timing and noise is presented. The effective capacitance noise. . In order to have a inductance that makes signal cross-talk realistic bus simulation.

a complete multi-bus V: MODELING FOR structure is constructed automatically. Figure 2. used for a device in a linear circuit Among the other parameters that users simulator. Flow chart of the RLC interconnect simulation tool. which is sufficient for an RC can input are drivers/receivers. capabilities. a . In Section V. In Section VI. Together with RC EFFECT wire models. signal In Section VII the conclusions are wires and shields on the top. victim and present. specified bus geometries (i. a circuit netlist for a reduce-order interconnect simulation can A: Modeling for the Non- Linearity of Drivers be generated. For inductance simulation. Based on the user. taps simulation.included with on-chip de-coupling along each power/ground wire. A fast reduce-order circuit simulator is used to generate the Traditionally. Incorporating the device non- linear behavior in a reduce-order linear circuit simulator significantly increases inductance simulation speed while maintaining a good accuracy. decaps capacitors (decaps).and INDUCTIVE mutual inductance. and signal input waveforms. a linear resistor model is waveforms for timing and noise analysis. which is one of the key contributions of this work. bottom layers plus power/grounds on a power layer). simulation results from the microprocessor designs are presented Figure 2 illustrates the flow chart of the to validate the RLC simulation implemented tool. The non- ideal ground modeling with decaps is also discussed. ACCURATE Fasthenry is used to calculate self.e. a non-linear driver modeling approach for accurate inductive effect is proposed..

the correct waveforms at the driver To accurately model the waveforms at outputs. The interaction between captured. In terms of delay simulation. This is due to the fact that the the self-/mutual inductance and the linear driver model does not capture the driver output voltage are not properly fast di/dt behavior and can not produce captured by a linear driver model. a fast precharacterization is done based on the actual interconnect geometries and the driver models. Figure 3.the overshoot/undershoot due to the non-linearity of and fast ramp-up time are not properly drivers/devices. like SPICE. although Figure 4 shows a driver output the linear model can predict delay with waveform of a 16-bit bus on M6. A non-linear driver model results in a much linear driver models lead to the underestimating of faster amp-up time and a waveform with a small inductive noise by 70%. is used to extract . ledge. the waveform is not difference between the two waveforms is accurate . Simulations show that a linear driver model leads to the underestimating of the signal inductive noise by 70% (Figure 3).linear driver model is unable to capture the inductance (especially the mutual inductance) interaction with the drivers. A non-linear circuit simulator. the driver output and capture the non- linearity of a device. The about 15% error. Cross-talk at a victim wire within a 16-bit bus on M6: figure 4.

noise and delay). model. In other words. the interconnect far-end Parameter n is the number of segments waveforms can be accurately obtained used to model the distributed effects. With a complete wire circuit per length of the transmission line. (i. but it is not modeled as ideal voltage connections. C are the resistance.. waveforms will be plotted for accuracy instead of the values for per length. inductance waveforms and the real driver and capacitance values. conductance. accurate enough to calculate the far-end the ground/power wires should be signal waveforms. but with fewer Ideal Ground and Decaps segments to have a fast precharacterization using SPICE. presents the same impedance information to the driver as a complete B: Modeling for the Non- distributed wire model. respectively. The connection waveforms at the interconnect near-end .and mutual inductance between the different output waveform depending on wires are preserved.the waveforms based on simplified have a very good match against SPICE circuit models for the interconnects to simulation with wire models using n speed up the pre-characterization. Each active driver can have a self. The Unlike an RC extraction/simulation simplified model is accurate to calculate where power/ground wires may be the near-end waveforms. modeled by distributed RLC elements in Results show that the pre-characterized RLC simulation. It comparison. the impedance which a coupling. G. but all segments. In Section VI. uses these waveforms as interconnect conductance. L. A piece-wise linear (PWL) approximation is then used to represent the characterized waveforms for each driver. the The simplified circuit model uses the pre-characterized piece-wise linear total resistance. drivers on driver sees is different layers and at a different bit position within a bus will have different waveforms. For a transmission the wires which it connects to and their line system.e. A fast linear circuit simulator Where R. inductance and capacitance inputs.

less ground compared. The waveforms show the bounce). Decaps provide charging and discharging currents at very high frequencies when the on-chip ground/power can not draw enough Figure 5. All the signals switch from low to high. with the one from SPICE simulation for accuracy comparison. With the help of in order to exaggerate the inductive decaps. . In Figure 5. a 16-bit same layer bus with The decap values are distributed along only two ground shields is constructed the VSS/VDD wires. and only the ninth signal keeps low. The non-ideal ground is modeled using RLC tap models. The first peak noise is negative which is mainly due to the inductive effect while VI: SIMULATION the first positive noise is largely due to EXAMPLES the capacitive coupling. The pre- currents through the taps from the on- characterized driver PWL waveform is plotted board power sources. Results from the new tool are compared with the ones from the full SPICE simulation which includes all the non-linear drivers..between any ground/power wires to the on-board VSS/VDD (e. decaps are modeled based on the area (that the bus structure covers) and the estimated decap values per chip area.e.g. C4 bumps) needs to be modeled for any inductance ground bounce. Using 0.18 μm technology. the local VSS/VDD effects so that the accuracy can be better becomes more stable (i.. noise at the far end of the victim wire. In this work. Various examples from microprocessor designs are simulated with typical values to demonstrate the validity of the proposed scheme.

Figure 7. all the signals switch in the tap model are used. the noise local ground wire on M6 is also plotted waveform shows that the major noise is to illustrate the ground bounce. The inductance in the tap model is 500 pH and the fully shielded. Fig. A more complicated example consists of three-layer buses with 12 bits on M6. The signal delay (Figure 6(a)) and inductive noise is observed with a non- noise (Figure 6(b)) are plotted for the ideal ground model. A three-layer bus example: the noise 48bits on M4 and M2. In the where an ideal and a non-ideal ground simulation. The inductance and resistance associated victim wire is in the middle of the bus in with the ground/power taps. In Figure 6(b). but the shield widths are resistance is 5 Ω comparable to the signal wires and they Figure. The delay and noise waveform of the victim wire on M4 is compared with the ones from the full SPICE simulation. For . Both signal delay and noise waveforms are almost indistinguishable from the ones with the full SPICE simulation. from the inductive coupling since there is no capacitive coupling between the signals in a fully shielded co-planar structure. The signal on a victim wire. 6(b) Noise Figure 6. 7 shows the two noise do not serve as completely effective waveforms of a signal wire within a bus shields for inductive effects. a larger M4. 6(a) Delay Fig. All signals are becomes larger due to the non-ideal ground. Due to the parasitic same direction at the same time.

simultaneous switching of signals in a [4]: IEEE Journal on ‘On-chip bus. [3]: Digital integrated circuits – Due to parallel routing and possible Jan M. mutual and self-inductance can cause additional delays and inductive wiring design challenges for noise for bus signals. With tap models and decaps. than the one with decaps. VIII: REFERENCES .Pucknell. The capability to include the nonlinearity of drivers in a reduced-order linear circuit simulator enables a much faster yet accurate simulation of on-chip interconnects with inductance. accurate time-domain transient waveform simulation approach for RLC interconnect is presented. A fast and gigahertz operation’. Kamran Eshraghian. April 2001.Rabaey. [2]: Modern VLSI design – Wayne VII: CONCLUSIONS Wolf. and ground bounce can also be observed.decap effect. Results from the proposed method are in a very good agreement with the ones from SPICE simulation while the simulation is 68X faster for large examples. one simulation shows the [1]: Basic VLSI design – Douglas delay of a bit in the center of a three layer bus without decaps is 15% larger A. bus simulation becomes more realistic.