FAST LOCKING DIGITAL PHASE LOCKED LOOP DESIGN DISSERTATION Submitted in partial fulfillment of the requirements of the MS Microelectronics

Degree programme By

Bharat B Roonwal 2008HB99501
Under the supervision of
Mr. Shivaraj G Dharne, Engineering Manager,

Intel Technology India Pvt. Ltd. Dissertation work carried out at Professional Development Centre, Bangalore

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE Pilani (Rajasthan) INDIA

January, 2011 MEL PDC ZG629T DISSERTATION FAST LOCKING DIGITAL PHASE LOCKED LOOP DESIGN DISSERTATION Submitted in partial fulfillment of the requirements of the MS Microelectronics Degree programme By

Bharat B Roonwal 2008HB99501
Under the supervision of
Mr. Shivaraj G Dharne, Engineering Manager, Intel Technology India Pvt. Ltd.

Dissertation work carried out at Professional Development Centre, Bangalore

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE Pilani (Rajasthan) INDIA

Project Guide Mr. Shivaraj G Dharne Engineering Manager, Intel India

BITS Co-ordinator Prof.D.V.Pooraniah

BHARAT ROONWAL.01.2011 Name: Shivaraj G Dharne Designation: Engineering Manager . ID.No. 2008HB99501 in partial fulfillment of the requirements of MEL PDC ZG629T Dissertation embodies the work done by him under my supervision. Signature of the Supervisor Place: Bangalore Date: 07.4 (61) BHARAT ROONWAL 2008HB99501 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE Pilani (Rajasthan) INDIA CERTIFICATE This is to certify that the Dissertation entitled “FAST LOCKING DIGITAL PHASE LOCKED LOOP DESIGN” submitted by Mr.

.............................................28 1.................................................................................................... 16 1.................................................... 61 ........................................................................19 1.........................................................................2 Frequency Synthesizer................................................................12 1...............................................................................................................32 1..............41 1...............................19...........................................................................................................................................................................................................16.....................................19..................................................17..7 Thesis Organization..............................................................2 Phase Detector Incorporated in Proposed PLL...................................................................................................................................................................16 Phase Frequency Detector................15 CHAPTER 2 :A BRIEF REVIEW OF PREVIOUS WORK................................12 1........60 ...................................25 1.......................1 Conventional Phase Detector................................................................................ 7 ABSTRACT........ 58 GLOSSARY OF TERMS USED................................2 Significance of PLL............................................20 Frequency Divider.................................17...............................................................................19 1....................................................................9 Phase Detector ...................42 1..........................10 Voltage-Controlled Oscillator...13 Analog ................................42 1..........................................................................3 High speed ring oscillator with dual delay paths..61 CHECKLIST...................................................................... 18 1.............................................................18 Loop Filter Design................20.....................................53 CHAPTER 5 :CONCLUSION AND FUTURE SCOPE...................14 Popular PLL Integrated Circuits (IC’s)...........................23 1.......2 Ring oscillator architecture..........................................1 Conventional Charge Pump ..................................................................................................................................................14 1.........................................18...........................25 1.......................................................................3 Phase Locked Loop Fundamentals.......3 Simulation Output and Results of Incorporated Phase Frequency Detector.....................................................................................................5 Classification of PLLs ........................11 Loop Filter ..16.........................14 1.....1 The most important specifications of the VCO..8 Background.............36 1... 13 1................................................................................................................. 61 ....................................10 1................48 1...........46 1...........................2 Charge pump incorporated in the proposed PLL.........................22 1.....................34 1...............................................16...................................3............49 CHAPTER 4 : SIMULATION RESULTS.........................................................................................................24 CHAPTER 3 :PROPOSED APPROACH AND IMPLEMENTATION.............................................39 1.................................................................................................................................30 1.......................................................................................3.....................5 (61) BHARAT ROONWAL 2008HB99501 TABLE OF CONTENT ACKNOWLEDGMENTS.16 1.......................................................................................................................................19 Voltage Controlled Oscillator (VCO).................................26 1.......................9 CHAPTER 1 :INTRODUCTION.................................................................................................56 REFERENCES..............6 Goal ............................................... Digital.............10 1.............10 1.............................25 1...........................19...................1 Digital dividers.............17 Charge Pump and Loop Filter...15 Architecture of proposed PLL............................... 39 1...............................................................11 1..4 Applications of PLL ...........1 Linear model of PLL.................................................1 Problem Definition .....................................1 Loop Filter......................... and Hybrid PLL’S....12 Configuration of PLL Application .........................

.........6 (61) BHARAT ROONWAL 2008HB99501 LIST OF FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1-1: Basic pll block diagram..............................................................................22 2-8:Synthesizer PLL..........................................................................................................................................................................................28 3-12:Phase Frequency Detector......................................................................................................................................................................................................23 3-9: Block diagram of the proposed PLL....17 2-4: Phase detector characteristic......................................................................................................................................................................................................22 2-7: Ranges of the dynamic limit of a PLL.21 2-6:Figure (a) Passive filter (b) Active Filter........................29 .......................................................................18 2-5 : linear model of the phase locked loop........27 3-11: Phase detector using TSPC type D flip flop..............................11 1-2 Basic frequency Synthesizer...........25 3-10 :Conventional phase detector using NAND gates..................................13 2-3 Conventional PLL Block Diagram....

...................43 Figure 3-26: delay stage cell schematic in VCO............. I would like to express my deepest gratitude to my thesis advisor.................. Throughout the course of implementing this work....................................................................................................52 Figure 3-35:Output waveforms of the frequency divider......................................................................... I had the opportunity to interact with the best of minds in the field of analog circuit design............... I feel motivated and encouraged every time I attend his classes...................................... Pooraniah for his guidance................50 Figure 3-34: Proposed 6 bit frequency divider.. ........................................................................................................37 Figure 3-20:The output of control voltage when up signal got activated................................34 Figure 3-17:Conventional Charge pump........................................................... Pooraniah for giving me opportunity to act as a Class Co-ordinator..... .................................................................................................48 Figure 3-31: output waveforms of the VCO for different control voltage.... Foremost..................................43 Figure 3-25: problem of insufficient gain.................... for his friendly behaviour during my studies at BITs PDC........... patience.................46 Figure 3-29:ring oscillator structure with dual delay paths........39 Figure 3-22: Linear model of PLL.........49 Figure 3-32: Divide by 2 frequency divider output..................................................... and most importantly............................................................................................... Shivaraj G Dharne...................................................31 Figure 3-15:when Vref is exactly in phase with Fout.......................................... which helped me in improving my leadership and mangement skills........ motivation and guidance...........................................................39 Figure 3-23: Loop filter of PLL.........................................31 Figure 3-14: when Vref is lagging Fout. I would like to gratefully and sincerely thanks Prof........ Mr..... understanding..................34 Figure 3-18:Proposed charge pump circuit........... the success of this project depends largely on the encouragement and guidelines of many others................. I take this opportunity to express my gratitude to the people who have been instrumental in the successful completion of this project................................................. I would like to thank again Prof........50 Figure 3-33: D Flip flop...........................................32 Figure 3-16: when Vref is exactly in phase with Fout........................................................7 (61) BHARAT ROONWAL 2008HB99501 Figure 3-13 : when Vref is leading Fout..............................................40 Figure 3-24:Basic structure of the ring oscillator....... Same time I thanks all the faculties who taught me during my MS course at BITs PDC..............................................................................54 ACKNOWLEDGMENTS Apart from the efforts of me........53 Figure 4-36: Full loop simulation of the PLL....................................................36 Figure 3-19: Bias generator used in the charge pump............45 Figure 3-28 : simulation results of three types of VCO’s.....38 Figure 3-21:The output of control voltage when dn signal got activated........................44 Figure 3-27: Load used in proposed ring oscillator showing inductive impedance......... I like to thank for everything you’ve done for me..............47 Figure 3-30: output waveforms of the VCO for different control voltage and linearity range.............................................................................. He encouraged me to not only grow as a professionally but also as an instructor and an independent thinker......... for his vision................................

for their constant encouragement. and to my Brothers& Sister. Pavan. Rajkiran.8 (61) BHARAT ROONWAL 2008HB99501 The guidance and support received from all my friends Pranjal. for teaching me the value in accumulating the wealth of knowledge. Gopal K Roonwal and Sheela Roonwal. Chaitanya. BHARAT B ROONWAL MS (BITs PDC) . Akhilesh Pathak. Hari K. Nagendra . I am grateful for their constant support and help. I am deeply indebted to my parents.

Frequency divider etc. which has low-power consumption and fast locking considerations. we present the design of Fast Locking Digital Phase Locked Loop (DPLL). PILANI SECOND SEMESTER 2010-2011 MEL PDC ZG629T DISSERTATION Dissertation Title: Fast Locking Digital Phase Locked Loop Name of Supervisor: Mr. Key Words: Phase locked loop. Shivaraj G Dharne Name of Student: Bharat B Roonwal ID No. process technology.9 (61) BHARAT ROONWAL 2008HB99501 BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE. Charge pump. PDF. . both classifications and comparisons are made. Here we first systematically analyzed the working of basic PLL and its inner blocks from aspects of theoretical analysis and circuit operation. The lock time of proposed PLL is less than 50ns and average power consumption is 7mw. VCO . The speed of the proposed phase frequency detector is up to 16 GHz. The simulated PLL will use 100 MHz reference frequency. Charge pump current is aimed at 150 μA and the output-frequency range of the oscillator is from 2 GHz to 7 GHz for 100mv to 500mv control voltage range. Based on the circuit architecture. CMOS process. Then we propose a high speed phase frequency detector. The previously proposed circuits for various units of PLL are modified for better performance and characteristics. The proposed phase frequency detector is simple in its structure and has no glitch output as well as better phase characteristics.loop filter. of Student: 2008HB99501 ABSTRACT In this thesis.

exploring and learning about attractions.10 (61) BHARAT ROONWAL 2008HB99501 CHAPTER 1 : INTRODUCTION 1. Tourist sites are providing wireless devices to aid tourists in navigating. Without AFC consumers radios had a frequency stability of 0. there has been a tremendous growth in the popularity of wireless networking technologies [2].0004% . digital satellite systems. With that era’s high gain amplifiers(G=250). generally until the 60’s. Similarly in today’s fast growing fields like radio. Schools and universities are providing wireless access to students and faculty members. of mobile broadband networks is popularly known as “WiMAX. Worldwide Interoperability for Microwave Access.the control circuit would yields a frequency stability of about 0. the emergence of new computing paradigms such as pervasiveness. ubiquity. is designed to deliver wireless broadband bitrates.” WiMAX.1 Problem Definition For many years. 1. with .In color television the color subcarrier at 3. Moreover. Over the past decade.recovers the carrier from satellite transmission signals[2].1% . Malls are providing customers with wireless connectivity to allow them to search products. early radios did not have automatic frequency synchronization or Automatic Fine Tune (AFC).There are many other fields where frequency and phase synchronization and frequency synthesis is required . telecommunication and computers where we need to recovers signals from noisy communication channel .158 Mhz required precise phase control to maintain color picture stability in NTSC format[1] . cordless phones.One of the electronic circuit which can be used for above application is PLL. there is widespread and growing use of cellular phones. Currently. performs frequency and phase modulation and demodulation and synthesize exact frequencies for receiver tuning .2 Significance of PLL The number of telecommunications innovations grew rapidly during the last half of the 20th century [1].fourth generation (4G). and mobility has necessitated the rapid deployment of wireless networks as an infrastructure underneath such technologies. and personal mobile radio networks. So we need a control system or electronic circuit which can automatically synchronizing the signals in phase and frequency and also generate various frequencies signals . virtually navigate shops. One of the technologies that can lay the foundation for the next generation . and interact with services.

A basic form of a PLL consists of three fundamental functional blocks namely [3] • A Phase Detector (PD) • A Loop Filter (LF) • A voltage controlled oscillator (VCO) with the circuit configuration shown in Figure 1. As the name suggests. it generates an output voltage.1 Figure 1-1: Basic pll block diagram The phase detector compares the phase of the output signal to the phase of the reference signal. The property of making its output frequency an exact multiple of the reference frequency makes the Phase Locked Loop (PLL) the circuit of choice for frequency synthesizers.11 (61) BHARAT ROONWAL 2008HB99501 Quality of Service (QoS) guarantees for different traffic classes.3 Phase Locked Loop Fundamentals A Phase Locked Loop or a PLL is a feedback control circuit. The . When both signals are synchronized the PLL is said to be in lock condition. They are at the heart of circuits and systems ranging from clock recovery blocks in data communications to the local oscillators that power the ubiquitous cellular phones. Phase Locked Loop has become one of the most versatile building blocks in electronics [5]. A significant part in WiMax system is the phase-locked loop. If there is a phase difference between the two signals. and mobility. PLL is also used for aligning various clocks in synchronous systems and for a myriad of applications ranging from tracking satellite Doppler shift to sensing minute reactance changes in industrial proximity sensors. the output signal will be in phase with the reference signal. which is proportional to the phase error of the two signals. the phase locked loop operates by trying to lock to the phase of a very accurate input signal through the use of its negative feedback path. 1. robust security. Due to this self correcting technique. This output voltage passes through the loop filter and then as an input to the voltage controlled oscillator (VCO) controls the output frequency.

Since higher order loop filters offer better noise cancelation. The ac part is undesired as an input to the VCO. 1. voltage controlled oscillator and on the loop filter[3]. The output of PD consists of a dc component superimposed with an ac component. such as from 600 MHz to 800 MHz in steps of 200 KHz. This period of frequency acquisition. The programmable divider divides the output of the VCO by N and locks to the reference frequency generated by a crystal oscillator. a phase-locked loop frequency synthesizer technique is used to generate 101 different frequencies.2 Frequency Synthesizer One of the most common uses of a PLL is in Frequency synthesizers of Wireless systems[2].3. the PLL eventually locks onto the input signal. a loop filter of order 2 or more are used in most of the critical application PLL circuits. in most of the FM radios. hence a low pass filter is used to filter out the ac component. which in turn is a parameter in determining the bandwidth of the PLL. For example. A loop filter introduces poles to the PLL transfer function. Loop filter is one of the most important functional blocks in determining the performance of the loop. Many applications in communication require a range of frequencies or a multiplication of a periodic signal.1 Loop Filter The filtering operation of the error voltage (coming out from the Phase Detector) is performed by the loop filter. this can be very long or very short. is referred as pull-in time. such as spectrum analyzers and modulation analyzers. . 1. Besides a PLL. it also includes a very stable crystal oscillator with a divide by N-programmable divider in the feedback loop.3. depending on the bandwidth of the PLL. The bandwidth of a PLL depends on the characteristics of the phase detector (PD).12 (61) BHARAT ROONWAL 2008HB99501 phase error between the two signals is zero or almost zero at this. Frequency Synthesizers are also widely used in signal generators and in instrumentation systems. varying in precise steps. Also most of the wireless transceiver designs employ a frequency synthesizer to generate highly accurate frequencies. A frequency synthesizer generates a range of output frequencies from a single stable reference frequency of a crystal oscillator [9]. As long as the initial difference between the input signal and the VCO is not too big.

13 (61) BHARAT ROONWAL 2008HB99501 Figure 1-2 Basic frequency Synthesizer The output frequency of VCO is a function of the control voltage generated by the PD.1) This implies that the output frequency is equal to f0=Nfr (1. Phase-locked loops can also be used to demodulate frequency-modulated signals.2) Using this technique one can produce a number of frequencies separated by and a multiple of N. the output frequencies will be in the proportional range. Other applications include: • Demodulation of both FM and AM signals . if N is a range of numbers.768 MHz In the same way.4 Applications of PLL Phase-locked loops are widely used for synchronization purposes. This relation can be expressed as fr =f0/N (1. control the frequency of the VCO. in space communications for coherent demodulation and threshold extension. The VCO frequency is thus maintained. This basic technique can be used to develop a frequency synthesizer from a single reference frequency. In radio transmitters. a PLL is used to synthesize new frequencies which are a multiple of a reference frequency. The Output of the phase comparator. and symbol synchronization. 1. So the phase comparator input from the VCO through the programmable divider remains in phase with the reference input of crystal oscillator. bit synchronization. with the same stability as the reference frequency[2]. This is the most basic form of a frequency synthesizer using phase locked loop technique. which is proportional to the phase difference between the signals applied at its two inputs. For example if the input frequency is 24KHz and the N is selected to be 32 ( a single integer ) then the output frequency will be 0.

 Reference frequency is 100MHz  Charge pump current is 150µA  Loop filter is of second order  VCO gain is 18GHz/v  Linearity range of VCO is 400mV(100mV-500mV) . modems. but the remaining blocks were still analog.5. rather by a computer program.14 (61) BHARAT ROONWAL 2008HB99501 • Recovery of small signals that otherwise would be lost in noise (lock-in amplifier) • Recovery of clock timing information from a data stream such as from a disk drive • Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections.5. the function of the PLL is no longer performed by a piece of hardware. An analog multiplier was used as the phase detector. the PLL drifted slowly but steadily into digital territory. In this case. from an EXOR gate or a JK flip-flop).4 Software PLL: PLLs can also be implemented ―by software.3 All digital PLL: A few years later. which appeared around 1970. This type of PLL is known as the linear PLL (LPLL) today. hence it doesn‘t contain any passive components like resistors and capacitors. 1. was in effect a hybrid device: only the phase detector was built from a digital circuit(for instance. That is why it is a semi analog circuit. This type of PLL is referred to as SPLL. 1.5. the loop filter was built from a passive or active RC filter. the ―all digital PLL (ADPLL) was invented.6 Goal My goal is to design PLL circuit which can be used for frequency synchronization and frequency synthesis with fast locking. 1. while maintaining precise timing relationships • DTMF decoders. and other tone decoders.5.1 Linear PLL: The first PLL ICs appeared around 1965 and were also purely analog devices. The very first digital PLL(DPLL). The ADPLL is exclusively built from digital function blocks. less power consumption and with below specification . for remote control and telecommunications.2 Digital PLL: In the years that followed. and the well-known voltagecontrolled oscillator (VCO) was used to generate the output signal of the PLL. 1.5 Classification of PLLs 1. 1.

In Chapter 3 the proposed arechitecture and various units of PLL are compare.15 (61) BHARAT ROONWAL 2008HB99501  Frequency divider is 6 bit  Lock time of PLL is less than 50ns  Power consumption of PLL in locked state is 7mW  PLL output is 2 to 7 Ghz GHz . Chapter 2 cover the literature survey of Phase Locked Loops.Chapter 5 talks about the conclusion of the thesis and scope of future work in this area. In this chapter we present basic fundamental of PLL. . the proposed one in the circuit with the conventional ones.Error is 10MHz (0.7 Thesis Organization The thesis is organized as follows.15%) 1. Chapter 4 includes the simulation results for all the units of PLL and top level PLL .

the DPLL‘s can be made more flexible and versatile. speed. their advantages and the assumptions on which each is based. .8 Background Continued progress in increasing performance. Consequently. aIl digital modems. and the simultaneous reduction in size and cost of integrated circuits (LSI and VLSI) has resulted in strong interest in the implementation of the phase locked loop (PLL) in the digital domain. would be of tremendous value to the engineer trying to decide what particular analysis procedure is applicable to his peculiar problem. Aside from the obvious advantages associated with digital systems. and the need for initial calibration and periodic adjustments. A survey on analog PLL’s in 1975[4] included over 40 publications in this direction. their relationship to one another. 1. their shortcomings. reliability. it is anticipated that the use of this signal processing technology will continue to expand rapidly in the development of advanced communications tracking receives. Like most aspects. with the ability to perform elaborate realtime processing on the signal samples. one major purpose of this chapter is to provide the reader with a survey and an overview of the theoretical and experimental work accomplished to date. e. In addition. In contrast to the matured status of the study of the analog PLL (APLL) the development of the all DPLL has just started to take shape over the last ten years.g. namely. In addition. This survey is particularly motivated by the fact that microprocessor technology is advancing rapidly to the extent that sophisticated and flexible signal processing algorithms for communications and control can be realized in the digital domain.The DPLL represent the heart of the blocks required in the implementation of coherent (all digital) communications and tracking receivers[6].16 (61) BHARAT ROONWAL 2008HB99501 CHAPTER 2 : A BRIEF REVIEW OF PREVIOUS WORK The purpose of this chapter is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase locked loop (DPLL’s) during the period of 1960 to 2010. a digital version of the PLL (DPLL) alleviates some of the problems associated with its analog counterpart. difficulties encountered in building higher order loops. the I feel that a tutorial article revealing the various theories. sensitivity to dc drifts and component saturations. thereby offering speedy access to the techniques and hardware developments which have been presented in a scattered literature[3]. In fact.

Towards the end of the 1963.1972. Perhaps the first “all digital loop” was reported by Drogin [3] in 1967.g. Apparently. the loop filter is a simple RC low-pass circuit. They are: 1) Flip-Flop IFF) -DPLL in which the phase error is derived from the duration between the set and reset time of a flip-flop triggered by positive zero crossings of the input signal and the . We have found it convenient to categorize the different implementations into four classes based on the mechanization of the phase detector. and the VCO is tuned by adjusting the bias voltage on a varicap in the tuned circuit controlling the resonant frequency of the VCO. This error voltage is filtered and used to control the instantaneous frequency of the VCO. It was designed to track a relatively slow 30-Hz sine wave. In 1962. the most noticeable years being 1968. Since then. Different authors explored various avenues and aspects of implementing the DPLL concept. He introduced a sample and hold circuit at the output of the loop filter in order to take advantage of the improvements offered by a digital VCO. the PD is a balanced mixer. 2-1 . The earliest efforts on DPLL’s concentrated on partially replacing the APLL components with digital ones. All three components are realized with analog circuitry.17 (61) BHARAT ROONWAL 2008HB99501 Figure 2-3 Conventional PLL Block Diagram of engineering. The classical APLL consists of three major functional units: 1) a phase detector (PD). 2) a loop filter and 3) a voltage-controlled oscillator (VCO)[1]. The second-order loop built and tested was used as a VHF omnidirectional range fiider. A block diagram of the APLL is shown in Fig. researchers in the field turned their attention to the implementation and design of digital PLL‘s. All digital components were clocked synchronously by a common 1. the work on DPLL’s is motivated by the steady availability of components that offer advantages over the conventional ones. As another example along the same line in 1968 analyzed the effect of replacing the loop fiiter with a digital one. Westlake was the fit to document the work in this direction in 1960.. the DPLL field has been somewhat active.The incoming signal whose phase is to be tracked is mixed with a locally generated sine wave to produce a voltage proportional to their instantaneous phase difference. e. Byrne analyzed the performance of a PLL when the phase detector was implemented with a flipflop and hence exhibited a sawtooth PD characteristic.097 MHz reference.

It operates as a multiplier. Accordingly. 2) Nyquist Rate (NR)-DPLL in which the input signal is sampled at the Nyquist rate.18 (61) BHARAT ROONWAL 2008HB99501 local clock.+n) for sawtooth PD. For this reason. +pai/2).DPLL in which the PD determines at each cycle whether the input leads or lags the locally generated clock. and 4) LeadlLag (LL). 3) Zero Crossing (2C)-DPLL in which the loop tries to sample at the zero crossings of the incoming signal. 3). they are often called digital phase detectors. the sinusoidal PD’s and the square signal PD’s. Figure 2-4: Phase detector characteristic .9 Phase Detector There are two types of PD’s. namely. Sequential PD’s contain memory of past events. and (-2pai. Increasing PD phase detection interval provides a larger tracking range. in the case of 2). are implemented by sequential logic circuits. which can generate PD characteristics that are difficult or impossible to obtain with multiplier circuits. A sinusoidal PD inherently has phase detection interval (-pai/2. and 4) the phase of the incoming signal is measured against the reconstructed signal. 2) is often referred to as a uniform sampling scheme whereas l). They are usually built up from digital circuits and operate with binary rectangular input waveforms. The square signal PD’s. than those obtainable from a sinusoidal PD. +pai/2) for triangular PD.The different PD’s all have the same factor K d . 3) and 4) are nonuniform sampling schemes.+2pai) for sequential phase/frequency detector (PFD) [6] . larger lock limit. (-pai. The characteristics of the square signal PD’s are of the linear type over the phase detection interval (-pai/2. which is a zero memory device[7]. Notice that in I). However. the phase of the signal is measured against a reference. also called sequential PD’s. 1.

and YIG-tuned oscillators. The phase stability requirement is in direct opposition to all other four requirements. Any PLL is at least a type-one loop because of the perfect integrator inherent in the VCO. 3) stabilizing temperature. where F( s) is the loop transfer function. Tuning of the YIG-tuned oscillator is accomplished by altering a magnetic field. 1. The closed-loop transfer function of the PLL for the passive filter is given by For the active filter . and the ILF output voltage is proportional to phase error. and 4) keeping mechanical stability. then the loop is type two. The phase error voltage we is filtered by the loop filter. whereas a PLL with a passive filter is type one. junction capacitance of a diode. Most of the phase jitter of an oscillator arises from noise in the associated amplifier. and Clapp circuits make their appearance. YIG-tuned Gunn oscillators have become popular. 2) maintaining low noise in the amplifier portion. At microwave frequencies. The tuning is accomplished by means of a varactor. an LC oscillator must be used.19 (61) BHARAT ROONWAL 2008HB99501 1. The widely used passive and active filters for the PLL are discuss. 2) large frequency deviation. The main requirements for the VCO are 1) phase stability. If a wider frequency range is required. 3) high modulation sensitivity K. A second-order PLL with a high-gain active filter can be approximated as a type-two loop. It is used to suppress the noise and high-frequency signal components from the I’D and provide a dc-controlled signal for the VCO. such as modulation and automatic frequency control. that the PD is linear. RC multivibrators. resonator oscillators. and 5) capability for accepting wide-band modulation[17]. In this application. We assume that the loop is in lock. namely. voltage controlled crystal oscillators (VCXO’s). Colpitts. If the loop filter contains one perfect integrator. the type of the loop is determined by the number of perfect integrators within the loop. The phase stability can be enhanced by a number of ways: 1) using high Q crystal and circuit.11 Loop Filter The LF in PLL is a low-pass filter. The servo scheme of the PLL in linear locking state is shown in Fig.10 Voltage-Controlled Oscillator The voltage-controlled oscillators (VCO’s) used in the PLL basically are not different from those employed for other applications. Four types of VCO commonly used are given in the order of decreasing stability. 4) linearity of frequency versus control voltage. According to servo terminology. 3. the standard Hartley.

is the natural frequency of the loop and eta is the damping ratio. The relevant parameters for passive filter are . both above can be rewritten into the forms in which w.20 (61) BHARAT ROONWAL 2008HB99501 For convenience in description.

We argue here that a higher order loop has nearly the same lock limit. As a fair approximation. The lock-in range AWL can be approximately estimated as . but for the secondor higher order loops. there is a frequency interval. The frequency range over which the loop acquires phase to lock without slips is called the lock-in range of the PLL. a PLL locks up with just a phase transient. it is common practice to build loop filters with equal numbers of poles and zeros. Besides. Define the hold-in range of a loop as AWH = KO. In a first-order loop.F(oo). If the input frequency is sufficiently close to the VCO frequency. smaller than the hold-in interval and larger than the lock-in interval. The lock-in limit of a first-order loop is equal to the loop gain. there is no cycle slipping prior to lock. over which the loop will acquire lock after slipping cycles for a while.Kd << PLL has the form A large value of KO is usually required for achieving a good performance of the loop . we can say that the higher order loop has the same lock-in range as the equivalent-gain first-order loop. At high frequencies the loop is indistinguishable from a first-order loop with gain K = KdK. the lock-in range is equal to the hold-in range. To ensure stable tracking. This interval is called the pull-in range. Their relations are indicated in Fig. 2-3. the lock-in range is always less than the hold-in range.21 (61) BHARAT ROONWAL 2008HB99501 Figure 2-5 : linear model of the phase locked loop And The two transfer functions are nearly the same if 1/K.

PLL's are widely applied in versatile systems as reference signal sources or oscillators. which are suitable for use in a variety of frequency-selective demodulation. PLL techniques in communication are well developed and widely used for FM. A typical phase-locked indirect synthesizer is shown in Fig 2-4 and 2-5. Besides. The self-acquisition of frequency is known as frequency pull-in. AM. signal processing. The modulating signal m(t) combining with the phase error from the PD modulates the PLL to achieve a phase modulation and indirect frequency modulation. The output frequency is synthesized by N. in which N is the division factor. or lock-in. 6 is a phase modulator formed by the phase-locked loop.fref . and the self-acquisition of phase is known as phase lock-in. . video. PLL is frequently realized as a signal modulator or synthesizer due to its inherent configuration. or frequencysynthesis applications. Figure 2-6:Figure (a) Passive filter (b) Active Filter Figure 2-7: Ranges of the dynamic limit of a PLL 1.22 (61) BHARAT ROONWAL 2008HB99501 Acquisition of frequency in PLL is more difficult and slower. Fig. signal conditioning.12 Configuration of PLL Application Integrated phase-locked loops developed since the 1970's are versatile systems. and requires more design attention than phase acquisition. telecommunication systems. etc. or simply pull-in.

A hybrid PLL realized by combining discrete analog and digital components was then achieved. frequency modulation. The difficulty for realizing chip PLL is how to constitute a highfrequency VCO on a single chip IC.pai/2to +pai/2. which operates at a frequency above 2. the versatile PLL’s components for improving the locking performance are developed in succession. Hereafter. such as speed or position. and a variety of other applications. Nowadays. motor-speed control. The type of PLL used in the realization system is determined according to the application.13 Analog . A PLS system is a frequency feedback control configuration that continuously maintains the motor speed or the motor position by tracking the phase and frequency of the incoming reference signal that corresponds to the input command. programmable counter. prescaler. but most of them are hybrids composed of both analog and digital components. were developed by Signetics and RCA in the 1970’s. signal detection. . The first analog PLL IC’s. the Motorola digital PFD MC4044 capable of phase-detection range from -2pai to + 2pai was proposed in 1972 . The phase detector is a multiplier. demodulation. and VCO on a chip IC to form a PLL module device. and a VCO.5 GHz [20]. it is a futureexploited trend to integrate the PD. whose phase-lock range is from . They are integrated on a chip including a sinusoidal PD. Figure 2-8:Synthesizer PLL 1. frequency synthesis. an LF. In order to extend-the lock-in range of PLL. The configuration of PLL’s can be either analog or digital. Digital. the integrated PLL has been developed for filtering. and Hybrid PLL’S Due to rapid progress in analog and digital IC’s in the 1970’s.23 (61) BHARAT ROONWAL 2008HB99501 The use of PLL with analog PLL IC (NE565 developed by Signe tics) for a synchronous motor and for a dc motor began in the 1970's[2] . NE565 and CD4046.

Both two PLL synthesizers operate at a low power consumption (5 V and 30 mA). The device has one fixed 12C BUS address and three programmable addresses.7. and emitter coupled logic (ECL). respectively. programmed by applying a specific input voltage to one of the current-limited outputs. The information on these ports can be read via the 12C BUS. and programmable counter) and discrete higher frequency VCO’s. The SP5655 capable of standard 12C BUS[2] control format contains two addressable current-limited outputs and four addressable bidirectional open collector ports.4-GHz and a 2. Nowadays. It is designed for the high-frequency local oscillator of an RF transceiver in handheld communication applications. such as Exar XR-215 PLL. prescaler. Besides. 2.1 GHz were introduced in 1995 [23]. The Motorola MC 12210 is a 2. new Motorola VCO’s MC12147 and MC12149 with operating frequency up to 1. Nowadays.5 mA. The GEC Plessey SP5070 and SP5655 are.GHz single modulus frequency synthesizers for use in satellite TV receivers.14 Popular PLL Integrated Circuits (IC’s) A wide variety of IC’s for PLL are available from semiconductor manufacturers. This PLL IC can operate at a minimum supply voltage of 2. one of which is a three bit ADC.7 V for input frequencies up to 2.5 GHz with a typical current drain of 9. The techniques widely used to implement the PLL are transistor-transistor logic (TTL). This enables two or more synthesizers to be used in a system. It is an important trend to realize fully integrated higher frequency PLL formed by constituting a high-frequency VCO into a modulus device in the near future. fully integrated PLL on a single chip can operate at frequencies up to 35 MHz.5GHz bipolar monolithic series-input phase locked loop synthesizer with phase-swallow function.5 GHz.24 (61) BHARAT ROONWAL 2008HB99501 1. and C-band with frequency doubling mixer. complementary metaloxide-semiconductor (CMOS). Motorola and Plessey are developing versatile PLL IC’s operating at frequencies above 2. high IF cable tuning systems. . A dual modulus prescaler is integrated to provide either a 32/33 or 64/65 divide ratio [21]. Other higher frequency PLL’s are easily achieved by combining sub-PLL IC’s (including only PD.

loop filter. has an advantage of better linearity range from -2 to +2 and is the most widely used phase detector in phase locked loop. voltage controlled oscillator and frequency divider[8] as shown in fig 3-1. charge pump. Its purpose is to detect phase difference between the two signals applied at the input. mentioned in chapter 2. Figure 3-9: Block diagram of the proposed PLL 1. The most important design considerations for a tri-state phase detector are: • • Dead Zone Power Consumption .16 Phase Frequency Detector The phase detector is the foremost unit of a phase locked loop. A tri-state phase detector.15 Architecture of proposed PLL The basic building blocks of the proposed PLL are phase frequency detector.25 (61) BHARAT ROONWAL 2008HB99501 CHAPTER 3 : PROPOSED APPROACH AND IMPLEMENTATION 1. Due to this we incorporate a tri-state phase detector in our phase locked loop.

1 Conventional Phase Detector Figure 3. As seen. The power consumption can be kept minimum by using minimum number of transistors and using lower supply voltage.26 (61) BHARAT ROONWAL 2008HB99501 • Maximum frequency of operation Dead zone. . this PD consists of D type flip flop made up of NAND gates [10]. as in that case it would limit the maximum frequency of operation and cause more ripples on the control voltage line (due to inherent current mismatch). there exists a finite reset pulse width. Also. resulting in undetectable phase difference between the inputs. In order to overcome its limitation a pre-charge type (PT) phase detector was proposed by Kondoh et al [5]. Also. can be minimized by designing the circuit such that. which corresponds to an excessively large number of transistors and thereby requiring a large chip area. large number of transistors results in large power consumption.16. 1. which is implemented using static CMOS technology.2 shows one of the conventional phase detectors. the error detecting range of this phase detector was limited to . It worked on dynamic CMOS technology. it should not be too wide. It consists of large number of NAND gates. However. The reset pulse width should be wide enough to just turn on the charge pump. This PD has severe limitations. utilizing the voltage generated at various nodes.to + . when the two input signals are exactly in phase.

27 (61) BHARAT ROONWAL 2008HB99501 Figure 3-10 :Conventional phase detector using NAND gates .

28 (61) BHARAT ROONWAL 2008HB99501 Figure 3-11: Phase detector using TSPC type D flip flop This limitation is removed by phase detector proposed by Lee et al [11]. It removes the reset circuitry which was required by the PD of figure 3-3. without sacrificing on its performance. It again works on dynamic CMOS technology and uses a TSPC-type D flip flop structure. 1. It works on dynamic CMOS technology and is similar to the previously mentioned PD. but consumes static power when the NOR gate output is low and also the logic becomes ratioed.2 Phase Detector Incorporated in Proposed PLL The phase detector incorporated in the proposed PLL is shown in figure 3-4. . It has good performance characteristic in terms of dead zone and provides a linearity range of -2 to +2 . The pseudo-NMOS NOR gate makes the operation fast. but requires an additional reset circuitry consisting of a pseudo-NMOS NOR gate.16.

This is because node C is prevented from being pulled up as m4 is off (due to charges at node A). The circuit will remain in this state. . Figure 3-12:Phase Frequency Detector Consider the case when Fref lead Fout in phase. node C discharges to ground potential and thereby causing UP to go high instantaneously. Thus. This high UP signal switches on m3 and m8. even if Fref goes low. When rising edge of Fref (leading in phase) arrives. This also results in switching on of N-MOS transistors m6 and m12.29 (61) BHARAT ROONWAL 2008HB99501 Working: Initially both Fref and Fout are low therefore the transistors m1 and m7 are on (P-MOS). Due to this node A and node B gets charged to Vdd and hence switching off transistors m4 and m10. it causes N-MOS transistor m5 to turn on and hence creating a low resistance path from node C to ground (m6 already on).

there exists a contention if Fout arrives when Fref is already low (in case of Fref leading Fout). Node A (B) must have a stronger pull down path than pull up. m3 (m8. A short duration reset pulse is seen on DN signal when the reset operation takes place. The reset pulse generated is of sufficient width such that dead zone is almost completely eliminated.3 Simulation Output and Results of Incorporated Phase Frequency Detector Figure 3. When both Fref and Fout are in phase. when rising edge Fout (lagging in phase) arrives DN signal goes high by similar mechanism as explained before. Similarly strengths of m4 and m10 should be weak in order to prevent UP and DN signal to go low until node A and node B are completely discharged to ground potential. The combined strength of m2. 1. and hence eliminating the need for extra reset circuitry.16. this UP signal is then reset by the rising edge of Fout. the above PD circuit utilizes the UP and DN signal directly for the reset operation. .30 (61) BHARAT ROONWAL 2008HB99501 Now. in order to get discharged. transistors m2 and m9 are turned on causing a low resistance path for node A and node B. This is because. node A and node B discharges to ground potential.5 shows the simulation output for the case when Fref is leading Fout. The rising edge of Fref sets the UP signal. Due to this node C and node D are pulled up and causing UP and DN signal to go low. Proper relative sizing of various transistors is required in order have rail to rail swings. m9) should be more than m1 (m7). Therefore. reset pulses are obtained at UP and DN signals. Thus. which results in P-MOS transistors m4 and m10 turning on. The PD consists of minimum number (16) of transistors. When this DN signal becomes sufficiently high. Exactly the reverse happens when Fout leads Fref. The strengths of m5 (m11) and m6 (m12) should be high in order to generate instant response from the rising edge of Fref (Fout).

31 (61) BHARAT ROONWAL 2008HB99501 Figure 3-13 : when Vref is leading Fout 2. this DN signal is then reset by the rising edge of Fref. Figure 3-6 shows the simulation output for the case when Fout is leading Fref.7) shows the simulation output for the case when Fref and Fout is exactly in phase. A short duration reset pulse is seen on UP signal when the reset operation takes place. These pulses are essential . (3. As seen. Fig. Figure 3-14: when Vref is lagging Fout 3. The rising edge of Fout sets the DN signal. only short duration reset pulse are obtained at UP and DN signal.

32 (61) BHARAT ROONWAL 2008HB99501 in order to eliminate dead zone. When PLL is in locked state. The important design considerations for an effective charge pump circuit are • There should be minimum peak current mismatch • The charge sharing phenomenon should be avoided . the control voltage is constant with some inherent ripples.17 Charge Pump and Loop Filter The charge pump is the second unit of PLL. in order to pump in or pump out the charge from the loop filter capacitor[13]. the reset pulses are shown on a magnified scale. Also. It utilizes the UP and DN signal provided by the phase detector. Figure 3-15:when Vref is exactly in phase with Fout 1. It is responsible for generating necessary control voltage to the VCO unit.

If IUP and IDN are different.33 (61) BHARAT ROONWAL 2008HB99501 • The effect caused by channel charge injection and clock feed through should be minimized • Output voltage range provided should be large Minimum peak current mismatch ensures minimum static phase error between the two input signals (Fref and Fout) in locked state.1). The reason for this is as follows. charge injection and clock feed through phenomenon results in periodic ripples and sudden jumps on the control voltage line.1) . This means that quantity of charge Qcharge and the one of discharge Qdischarge must be equal and given by eqn. (3. This becomes critical when PLL is used as a frequency multiplier in a local oscillator of a transceiver [14]. which further helps to decrease the sensitivity of VCO to sudden variations on control voltage line. These non ideal effects can be reduced by suitable circuit level manipulations.1) where TUP and TDN are duration of UP and DN pulses in locked state. This helps to keep the VCO gain to a lower value (for a given operating frequency range). . (3. then there has to be some difference between the duration of UP and DN pulse in order to satisfy eqn. or charging and discharging time in one cycle. In locked state the phase detector generates equal UP & DN pulses and the control voltage (Vctrl) is supposed to be constant. The output voltage range provided by charge pump should be as large as possible. thus creates a static phase difference between its inputs in order to maintain the difference between the duration of UP and DN pulse in accordance with eqn. The charge sharing.1) Qcharge=IUP* TUP = Qdischarge = IDN * TDN (3. This results in generation of spurious tones and jitters at the output. The PLL.(3.

The transistors m6 and m7 acts as switch and transistors m4 and m5 act as a constant . Figure 3-17:Conventional Charge pump The conventional charge pump is based on the conceptual circuit of figure 3-1 and is shown in figure 3-9. This results in a staircase waveform during the transient period. When there is an UP pulse the charge pump pumps in charge to the loop filter capacitor[15].1 Conventional Charge Pump Figure 3-16: when Vref is exactly in phase with Fout Figure 3-8 shows the conceptual circuit of the charge pump. It consists of two switched current sources. when there is a DN pulse the charge pump pumps out the charge from the loop filter capacitor.34 (61) BHARAT ROONWAL 2008HB99501 1. When the PLL is locked. the output voltage remains constant. The current sources are switched by UP/DN pulses from the phase detector. Similarly.17.

The desired value of current is mirrored from Iref via current mirror configuration formed by m1. node Y and output voltage Vctrl. This happens when the MOS switch. As the technology node decreases this circuit shows significant . The charge sharing is due to balancing of charge between node X. Vt is the threshold voltage and C is the output capacitance (loop filter capacitance) Clock feed through results due to non ideal behavior of MOS switches. clock feed through and channel charge injection. in on condition operating in triode region. the circuit of figure 3-2 shows many non ideal effects like charge sharing. m2. The magnitude of the error caused by clock feed through is given by ∆V= (3. when the equal duration UP/DN pulse arrives (during locked state of PLL). These errors cause sudden jumps on the control voltage line.35 (61) BHARAT ROONWAL 2008HB99501 current source. The magnitude of voltage error is given by ∆V= = (3. the circuit should be designed carefully enough such that the parasitic capacitance Cpar is made to be a small fraction of the loop filter capacitance C. These phenomenons tend to produce ripples on control voltage line. at the drain terminal. is suddenly turned off. Cpar is the parasitic gate to drain capacitance. There are some circuit level techniques to suppress the effects due to above mentioned nonidealities. However. In order to minimize the error due to clock feed through.2) Where k is the fraction of channel charge moving to drain. hence minimize sudden jumps. m4. Cox is the oxide capacitance. which presents a parasitic gate to drain capacitance. The circuit eliminates all the non ideal effects completely by isolating the output node from the switching transistors and thus making the output is free from sudden jumps. Chang and Kuo’s model provides one of the best solutions for charge pump design. Channel charge injection occurs due to flow of part of the channel charge from the channel to the output load capacitor (loop filter capacitor). For example in order to suppress the effects due to charge sharing an OP AMP is connected in unity gain configuration and to suppress the effect due to channel charge injection and clock feed through ‘dummy switches’ are connected. which is transformed in phase noise and spurious tones in VCO output. m5 and m3. Vgs is the gate to source voltage. Qch is the channel charge. which creates opposite effect to the one created by UP/DN signal.3) Where Vdd and Vss are the high and low values of UP/DN signal.

m6 also constitutes the other current source. we have to use the bias generator to generate the bias voltages and then these bias voltages are used to produce the constant current sources. m2 constitutes the current source and m5.36 (61) BHARAT ROONWAL 2008HB99501 mismatch in pump up and pumps down currents.17. The current mismatch further results in static phase error between the inputs when PLL is in locked state. 1. This is due to Channel Length Modulation (CLM) effects which becomes prominent at short channel lengths. Figure 3-18:Proposed charge pump circuit Here m1. The circuit is as follows. At first for the drain of transistor m9 we have to give minimum voltage and calculate the width and length of the transistor for getting required current 150 µA. . The internal circuit of the bias generator is shown in figure 3-11 and the working and design is also explained.2 Charge pump incorporated in the proposed PLL In order to remove the channel length modulation effects. Similarly do the same procedure for m14 also. The bias voltages for these constant current sources come from the bias generator shown in the figure 3-10.

From this plot we can observe that current is not varying with the output voltage that means the channel length modulation effect is neglected[15]. m6 and m10. m10 and m11 should be 6 times that of the transistor m14. . m6. The resistor value should be selected in such a way that the output current must be 150µA when simulated. m12 and m13 should be 6 times of the width of the transistor m9. Gate voltage of m9 is given to m3. m4. Bias voltages biasp and biaspc will come from the gate voltage of m12 and m13 respectively. m7. m3. m2. The widths of the transistors m5. By using these bias voltages we can make constant current sources. m4 and m13. m8. And the bias voltages biasn and biasnc will come from the gate voltages of m7 and m14 respectively.37 (61) BHARAT ROONWAL 2008HB99501 Figure 3-19: Bias generator used in the charge pump when the simulation is started the m9 and m14 will produce 150 µA current and the gate voltage of m14 is given to m5. The width of the transistors m1. The simulated output of the pump in current with respect to the output voltage is shown.

Figure 3-20:The output of control voltage when up signal got activated.38 (61) BHARAT ROONWAL 2008HB99501 The working of the charge pump circuit is explained with the help of the figure 3. Similarly m5 and m6 with bias voltages biasn and biasnc will constitute a current source so when dn signal goes high then transistor m4 will get switched on then the charge will be pump out of the capacitor.3. Transistors m1 and m2 with bias voltages biasp and biaspc will constitute a current source so when the up signal goes high then the transistor m3 will get switched on so the charge will be pumped through m3 into the loop filter capacitor. .

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BHARAT ROONWAL 2008HB99501

Figure 3-21:The output of control voltage when dn signal got activated.

1.18
1.18.1

Loop Filter Design
Linear model of PLL

Figure 3-22: Linear model of PLL

The linear mathematical model of a PLL is shown in figure 3-14. Even though PLL is a highly non linear system, it can be approximated to a linear system using continuous time approximation, wherein the sampling nature of the PFD is ignored .

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BHARAT ROONWAL 2008HB99501

In the figure 3-14 KPD is the gain of PFD+CP combination. F(s) is the transfer function of the loop filter. KVCO/s is the transfer function of VCO. When PLL is in locked state, the phase transfer function is given by: H(s) = = (3.3)

If a single capacitor (C) is used as a loop filter (like PLL) the transfer function becomes.

H(s) =

=

(3.4)

As seen from eqn. 3-15 the transfer function of the closed loop system has two poles on imaginary axis and hence unstable. It would result in un-damped oscillations at the output and the output will never settle. A zero added to the above system ( by adding a resistor (R1) in series to loop filter capacitor (C1)) makes the system stable, but cause sudden jumps on the voltage control line, which can further result in potential overload of VCO. Therefore, to avoid it (sudden jumps), another capacitor (C2) is added in parallel to the series combination of resistor and loop filter capacitor, as shown in figure 3.10.

Figure 3-23: Loop filter of PLL

Thus, a PLL requires a minimum of second order loop filter to ensure its stability. The loop filter is important to the performance of the PLL because 1) Removes high frequency noise of the detector

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BHARAT ROONWAL 2008HB99501

2) Influences the capture and tracking ranges 3) Influences the switching speed of the loop in lock. 4) Easy way to change the dynamics of the PLL We will consider the filters that give us more flexibility in controlling the characteristics of the PLL. Filters are of two types: passive filters and active filters. The advantages of the passive filters are they are linear, relatively low noise and unlimited frequency range. We have some disadvantages also in using the passive filters. If the filter components are larger in value(c>200pF and R>100kohm) then they are hard to integrate. Another disadvantage is it is difficult to get a pole at the origin (increase the order of the type of PLL). In order to remove the drawbacks of passive filters we will go for the active filters. Active filters can reduce the sizes of the passive elements but the disadvantages are they will produce more noise, consume more power and it has some frequency limitations. The loop filter component values are R1 is 500 ohms, capacitor c1 is 100pF and c2 is 10pF. Generally the ratio of c1/c2 should be 10.

1.19

Voltage Controlled Oscillator (VCO)

Voltage controlled oscillators are one of the important blocks of data communication systems and have wide applications, from data modulating in transmitters to demodulation and clock recovery in receivers[18]. A CMOS VCO can be built using ring structures, relaxation circuits, or an LC resonant circuit. Ring inverter based oscillators have some advantages among the other oscillators that have made them a good choice for designers. Compared to other alternatives, especially the LC resonator-based oscillators, the ring oscillator are having the following advantages.

The ring oscillator is compact, as it doesn’t need on chip inductors [19] Its tuning range can span orders of magnitude as the ring oscillator is tuned by

• voltage.

it is desirable to scale down the current consumption of the VCO proportional to frequency variations which can be reached using ring oscillators.1 The most important specifications of the VCO Electrical tuning range: The tunable frequency range of the VCO must be able to cover the entire required frequency range of the interested application.2 Ring oscillator architecture The ring oscillators consist of delay cells connected in cascade as shown in figure 3-16.19.19. when we design the circuit of the VCO. of the whole system [20]. we should pay attention to the main problems of the tuning range. These are connected in a closed loop for providing enough gain and phase shift to satisfy the Bark hausen´s oscillation criteria [21]. the switching noise will also couple to Vdd of the VCO and influence its output waveform. Ring oscillators with differential delay stages exhibit greater immunity to supply disturbance and substrate induced noise than single delay stage ones. the switching activities of the digital circuits will influence the supply voltage.42 (61) BHARAT ROONWAL 2008HB99501 Meanwhile. Kvco at the entire frequency range. has large short-circuit power consumption. A constant VCO gain can simplifies the design procedure of a PLL. noise. power consumption and linearity. Power consumption: The VCO at high frequency has large dynamic power consumption and at low frequency. Vdd. so reducing the power of the VCO is very important. Tuning linearity: An ideal VCO has a constant VCO gain. According to above analyses. 1. . ring oscillators suffer from low Q factor and consequently larger phase noise. Besides. 1. Therefore the dependency of the VCO oscillation frequency on the supply voltage must be as low as possible. Supply voltage sensitivity: Since there are many digital circuits in a modern transceiver circuit. However. The main power consumption of the PLL comes from the VCO.

shows that the increase of the oscillators speed can be realized by two ways: through the reduction of the delay time in the cell or by decreasing the number of cells in the ring. each cell contributes with a frequency dependent phase shift of 180°/N and the dc phase shift provides the 180° remaining. as N diminishes it is more difficult to satisfy the Barkhausen´s oscillation criteria: the steady oscillation in a ring oscillator requires a total phase shift of 360º around the loop at a frequency where the small signal gain is above 0 dB. the loop gain is less than 0 dB. However. Insufficient gain means that at the frequency where the frequency-dependent absolute phase shift reaches 180º. in other . Figure 3-25: problem of insufficient gain The reduction of the number of cells is very attractive not only for the operation speed increment but for the power consumption reduction and the saving in area for its implementation. For small N the problem of insufficient gain (or insufficient phase shift) arises.43 (61) BHARAT ROONWAL 2008HB99501 Figure 3-24:Basic structure of the ring oscillator In these topologies the oscillation frequency is given as Where N is the number of delay cells in the ring and is the delay time in the cell. In N cells ring oscillator.

as is shown in figure 3-18. Figure 3-26: delay stage cell schematic in VCO In this delay stage. In this project. a new differential ring oscillator with new composite load is proposed. single control voltage relaxes the implementation of charge pumps and loop filters in the PLLs. The single control voltage also eases the implementation of the charge pump and loop filter within the PLL. The size of m3 and m4 determines the tuning range. . resulting in relatively higher frequencies and wider tuning ranges.44 (61) BHARAT ROONWAL 2008HB99501 words. while the pmos transistors m7 and m8 form the input pair for secondary loop. the nmos transistors m1 and m2 create the input pair for primary loop. Furthermore. The transistors m3 and m4 are utilized to control the frequency of operation by varying their gate voltage.m7 & m10) and feed-forward technique to reduce the delay of each cell. Figure 3-18 shows the schematic of delay stage. The proposed differential ring oscillator uses composite load (m8 & m9. Applying control voltage to pmos transistors helps avoiding tail current control mode and increasing output voltage swing and reducing 1/f noise. the crossover points of the phase (-180º) and the unity loop gain are different and the oscillation criteria cannot be met simultaneously.

the cross-coupled nmos pair can also help to improve the phase noise . As shown in Figure 3-19. the impedance at the drain of m8 is always inductive. Considering that the nmos switches faster than the pmos. the impedance at the drain of M3 is always inductive. In addition to that. showing inductive impedance at the drain of m7 and m8. is introduced at between the outputs to provide the essential self-balancing of the delay cell to prevent the differential ouputs from settling to the same voltage. Therefore. a cross coupled nmos pair m5 and m6. considering the gate source capacitance of m8 we have: Figure 3-27: Load used in proposed ring oscillator showing inductive impedance Therefore. This new load helps the cell to oscillate at higher frequency and reaches wider tuning ranges.45 (61) BHARAT ROONWAL 2008HB99501 The nmos transistors m9 and m10 are used as a load besides m8 and m7 to create a composite load. Its magnitude can be changed by varying the widths of m9 and m10. Its magnitude can be changed by varying the widths of M7 and M8.

To solve this frequency-limitation problem. The dual-delay scheme means that both the negative skewed delay paths and the normal delay paths exist in the same ring oscillator. higher operation frequency can be obtained. a single-ended ring oscillator with a negative skewed delay scheme has been used [20].46 (61) BHARAT ROONWAL 2008HB99501 performance of the oscillator by a significant amount since the positive feedback within the delay cell provided by this nmos pair helps to reduce the transition time of the output nodes. and the oscillator is sensitive to the power-supply noise and not controllable. Hence the frequency of the oscillator is decided by the delay time of one delay element. If the delay cell is single ended. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time. the frequency range of the VCO can be wider than that of an oscillator with only skewed delay paths. the maximum frequency of the VCO is limited by the delay time of the basic inverter delay cell. Figure 3-28 : simulation results of three types of VCO’s . The delay time cannot be smaller than that of a single inverter. the oscillation frequency is determined . As a result. higher operation frequency and wider tuning range are achieved simultaneously. In this work. where N is the number of stages and t is the unit delay time of a delay cell. by using a dual-delay scheme to implement the VCO. Since the normal delay paths also exist. therefore. 1.19.3 High speed ring oscillator with dual delay paths In a conventional ring oscillator.

In figure 4. To utilize both the negative skewed and the normal delay paths. Changing the control voltage between 100mV-500mV. as shown in figure 3-21. and only negative skewed delay path. and the normal delay paths are the paths which are coming from outputs of previous stage to the inputs in1+ and in1-. are added to the PMOS loads of the delay cell and are used to take the negative skewed signals. and the normal signal is connected to the NMOS input of the delay cell. the frequency varies between 7GHz .2 GHz in differential voltage . Figure 3-29:ring oscillator structure with dual delay paths The negative skewed signal is connected to the PMOS input of the delay cell. This operation enhances the rise time of the output and contributes to reducing the phase noise of the overall VCO. a pair of PMOS transistors. the negative skewed delay paths are the paths which are coming from the outputs to the inputs of in2+ and in2-. with dual-delay path.47 (61) BHARAT ROONWAL 2008HB99501 Figure 3-20 shows the simulation results of the three types of VCO. The signal prematurely turns on the PMOS during the output transition and compensates for the performance of the PMOS. which is usually slower than that of the NMOS. Figure 3-21 illustrates the tuning characteristics of proposed VCO. The same types of delay cells are used to implement the VCO’s. only normal delay path. The figure shows that the dual delay scheme achieves both a high oscillation frequency and a wide tuning range. The negative skewed signal is taken from the two stages before the current delay stage.6.

The VCO gain is 18GHz/v. Figure 3-22 is the plot of output waveforms of the VCO for different control voltages. the output of the voltage-controlled oscillator (VCO) is divided down by the frequency divider to a stable reference frequency signal produced by the crystal oscillator[21]. From this we can understand that as the control voltage is increasing the VCO is taking more time to change Figure 3-30: output waveforms of the VCO for different control voltage and linearity range. It shows linear characteristics and wide tuning range of oscillator.48 (61) BHARAT ROONWAL 2008HB99501 controlled ring oscillator.20 Frequency Divider The frequency divider is an important building block in today’s RFIC and microwave circuits because it is an integral part of the phase-locked loop (PLL) circuit. 1. In a typical PLL loop. The divided signal and .

For a series of three of these. It is implemented using only one D flip-flop. By adding additional logic gates to the chain of flip flops. 100. Such division is frequency and phase coherent to the source over environmental variations including temperature. Additional registers can be added to provide additional integer divisors. the third bit is 1/4 the rate. 011. other division ratios can be obtained. . and 001. An arrangement of flip-flops is a classic method for integer-n division. The output signal is derived from the combination of the register outputs. For example. The three valid values for each register are 000. 111. This is a type of shift register network that is clocked by the input signal. 1. The output phase difference is used to adjust the VCO output frequency. etc. a divide-by-3 divider can be constructed with a 3-register Johnson counter.49 (61) BHARAT ROONWAL 2008HB99501 reference frequency signal are fed into the phase detector for comparison. This pattern repeats each time the network is clocked by the input signal. Figure 3-31: output waveforms of the VCO for different control voltage In the figure 4. The last register’s complemented output is fed back to the first register’s input. 110.1 we give a frequency divider which divides the frequency by two. clocked by the input signal. a simple binary counter can be used.20.1 Digital dividers To divide a digital signal by an integer multiple a Johnson counter is used. such system would be a divide-by-8. the next bit is the 1/2 the rate. For power-of-2 integer division. The values 000 and 111 occur with three clock pulses apart and control the state change of the output signal. The easiest configuration is a series where each flip-flop is a divide-by-2. The least-significant output bit alternates at the same rate as the input.

The same event repeats for every two input clock cycle. inverted output again is fed back to the input. The proposed DFF uses two sets of clocks. As shown in Figure 4. and the clocks applied on gates M2 and M4 are denoted clk_d and clkbar_d clocks are generated by delaying clocks clk and clkbar. which causes the output to toggle. Thus. Figure 3-33: D Flip flop . The inverted output is fed back to the input port D.50 (61) BHARAT ROONWAL 2008HB99501 It is essentially an edge triggered master/slave D flip-flop (DFF). respectively. with two stages of inverters [22].2. each positive input clock cycle is loaded into the DFF. output frequency is half of the input frequency. It is why toggle DFF is a more descriptive name for this circuit. Figure 3-32: Divide by 2 frequency divider output Now we will see the implementation of the D flip flop. The clocks applied on transmission gates M1 and M3 are denoted clk and clkbar. On the next cycle.

The proposed DFF uses two sets of clocks. Since the transmission gate M1 is now open. causing the data previously stored at node B to be propagated to node A. The proposed design uses two sets of clocks on gates M1 and M2. If the clock goes high before node B changes to the present state. Then. Let us see what happens if we use same clock that is instead of clk_d we use clk signal only. Assume that the clock is high and the input data changes from low to high. through the path of node A. the data stored in the first memory unit is propagated to the output terminal. with two stages of inverters. due to the delay of inverters inv1. the transmission gate M2 will be closed. clock clk_d . If the clock is too fast. Since clock clk_d is the delayed version of clock clk.When clock clk. as soon as the new data is propagated to the output of INV1. the data D is loaded to node A and stored in the first memory unit composed of inverters inv and inv2. When the clock clk is high. If the previous data is different from the new data. the clock can go low and the new data can be propagated to the output of the DFF. the final state of node A is uncertain and the DFF may function incorrectly[22]. node B is still in the previous state. inv1. The clocks applied on transmission gates M1 and M3 are denoted clk and clkbar. respectively. is high. the DFF will not have sufficient setup time and the following scenario might cause the DFF to not function correctly. they will ‘fight’ with each other. The proposed static DFF has a reduced setup time compared to that of a conventional static DFF. but in our proposed D flip flop we have two clocks. then the signal at node A will change from low to high. the new data is propagated to node A through M1. and inv2. At this moment. When the clock clk goes low. In the conventional static DFF we will not have two clocks. In order for the DFF to function correctly. when clock clk goes high. a sufficiently large setup time is required to allow the new data to be propagated to node B. and inv2.51 (61) BHARAT ROONWAL 2008HB99501 Now we will see the implementation of the D flip flop. and the clocks applied on gates M2 and M4 are denoted clk_d and clkbar_d clocks are generated by delaying clocks clk and clkbar.

Let us suppose the frequency of the clock given to the first D flip flop is “ f ” then the output of that flip flop is coming out to be the half of the frequency of the input clock i. Simulation results of the proposed D flip flop: Setup time of the flip flop = 50 ps Hold time of the flip flop = 22 ps In the proposed PLL we have used 6 bit frequency divider.52 (61) BHARAT ROONWAL 2008HB99501 is still low.e. Figure 3-34: Proposed 6 bit frequency divider The output waveforms of the frequency divider are shown below. Thus gate M2 is still open and the previous data stored at node B cannot be propagated to node A through M2. In this way our frequency divider will produce the output frequency which 1/64th of the input frequency. The ‘fighting’ condition between the new data and the previous data is then avoided. the setup time of the proposed DFF is reduced. This output is given to the next flip flop as clock then the frequency of output of the second flip flop will the half of the input clock i. . This output is given to third flip flop then the frequency of the output of that flip flop will be f/8.e. output of fifth flip flop is f/32 and the output of the sixth flip flop is f/64. As a result. f/2. f/4. Like this the output of the forth flip flop is f/16.

53 (61) BHARAT ROONWAL 2008HB99501 Figure 3-35:Output waveforms of the frequency divider CHAPTER 4 : SIMULATION RESULTS Full loop simulation of the proposed PLL is shown in the following figure 4. So as the reference frequency is 100MHz and the frequency divider is 6 bit.1. the output frequency of the VCO should be 7GHz. . So the control voltage should get settled to a specified value such that the output frequency of VCO is 7GHz. Initial control voltage given at the starting of the simulation is Vdd.

54 (61) BHARAT ROONWAL 2008HB99501 Figure 4-36: Full loop simulation of the PLL .

This is clearly shown in the figure 4-1.15%) . the output frequency of the frequency divider should be in phase.e. The control voltage got stabilized to 50mV after time of 50ns. When the PLL is in locked state the reference frequency and the feedback signal i. So the lock time of the PLL is 50 ns. The time taken by the PLL to get lock to a new specified frequency is called lock time. Summary of overall PLL:  Reference frequency is 100MHz  Charge pump current is 150µA  Loop filter is of second order  VCO gain is 18GHz/v  Linearity range of VCO is 400mV(100mV-500mV)  Frequency divider is 6 bit  Lock time of PLL is less than 50ns  Power consumption of PLL in locked state is 7mW  PLL output is 4-7Ghz GHz  Error is 10MHz (0.55 (61) BHARAT ROONWAL 2008HB99501 When the PLL is in locked state the control voltage should be stabilized to a constant value which is clearly shown in the figure 4-1.

In the proposed digital PLL.4 µW of power. . It incorporates a high performance phase frequency detector that requires minimum number of transistors and consumes as low as 0. the previously proposed circuits for various units of DPLL were modified for better performance. It provides a linearity range of -2π to +2 π and eliminates dead zone almost completely.56 (61) BHARAT ROONWAL 2008HB99501 CHAPTER 5 : CONCLUSION AND FUTURE SCOPE In this thesis we presented the design of CMOS based Fast Locking DPLL for generating high frequency clocks.

. The average power consumption is 0. fast locking and low static phase error. Therefore no sudden jump phenomenon was observed in output during pump up or pump down operation. The average power consumption of the VCO circuit is 0.57 (61) BHARAT ROONWAL 2008HB99501 The charge pump unit incorporated in the proposed PLL gave satisfactory simulation results. clock feed through and charge sharing) that were present in conventional charge pump were eliminated. To validate the performance of this PLL Layout drawing. The transfer characteristic of VCO was satisfactory in the operating range provided by charge pump (100mV. Various non idealities (channel charge injection. The proposed PLL obtained by integrating all the units gave good simulation results. The problem of current mismatch that was present before (due to channel length modulation (CLM) effect) was suppressed by using stable bias voltages which are generated by the bias generator.5 µW at 5GHz frequency and the frequency divider used is 6 bit. The proposed circuit (DPLL) is suitable for various applications in high speed systems due to advantages of low power.45µs and the average power consumption in locked state is 7 mw. The charge pump is designed to produce an output current of 150µA. extraction and post layout simulation are important So this may be part of future work.PFD and VCO are control through programmable unit which allow very fast locking .625 µW. The static phase error of proposed PLL is as low as 57 ps. The VCO unit incorporated will have dual delay paths in order to reduce delay of the single delay stage so that the frequency of operation will get maximized. Future scope includes making this PLL programmable PLL in which CP.500 mV). The lock time of PLL is less than 0.

1998. Simulation and Analysis. CRC Press. Donald R Stephens.theory and application. Roland Best. Design of Analog CMOS ICs. Phase locked Loop Design. Phase locked loop . Oxford Uni Press. Bocca Raton. 2001. Behzad Razavi. Phase locked loop for wireless communication for Digital. 1997. Philip & Holberg. 3 4 5 . Analog and optical communication. CMOS Analog Circuit Design Second Editio. CRC Press LLC. Kluwer Academic Publishers. stensby. 2002. TATA MCGRAW HILL Edition.58 (61) BHARAT ROONWAL 2008HB99501 REFERENCES TEXT BOOKs: 1 2 John L. 1997.

“Fast frequency acquisition phase frequency detector with zero blind zone in PLL. Hua Ma and Jianwei Zhang. pp. Jinbao Lan. S.. pp. (23). 56. Elsemary. . 14 Lee. NO. “A Fast Locking Digital Phase-Locked Loop using Programmable Charge Pump”.59 (61) BHARAT ROONWAL 2008HB99501 IEEE PAPERs 6 Behzad Razavi. pp. and Liu. 8. vol. 7 8 Jinbao Lan. 12 Ali. Zekry. Zhou. I.. Reg. pp. L. Dec. Papers. June 2010. 10 Jun Pan and Tsutomu Yoshihara. Lett. and Chih-Kong Ken Yang. Dean Liu. 11 Mozhgan Mansuri.Page 755.393–396. July 2010. P. 2009. C.. pp..S. M. Lim.. “A Nonlinear Phase Frequency Detector with Zero Blind Zone for Fast-Locking Phase-Locked Loops”. Yuxin Wang. pp. Oct. (5). 56.. 2010. Zhiqiang Gao. IEEE Trans. 9 W. Vol 46. “The Role of PLLs in Future Wireline Transmitters”. Oct. Sept. Wang. and Kim. Y. 1907–1908. Page(s): 135 – 138..-I.1331–1334. IEEE Conf.. “Charge pump with perfect current matching characteristics in phase-locked loops”.” in IEEE Electron Devices and Solid-State Circuits Conf. 2004. 15 Lin. vol. Mak . Chunglen and X.S.H. “A fast lock phase-locked loop using a continuous- time phase frequency detector.Y. M. 32. Circuits Syst. J. “Dynamic current-matching charge pump and gated- offset linearization technique for delta-sigma fractional-N PLLs”. 1018-1020. 1117-1120. Ruzhang Li. Keel.” Electronics Letters. 43. IEEE Conf. in IEEE 8th International Conf. on ASIC (ASICON 2009). Ti. VOL. 13 Chen. 2007. Shawkey.H. “Self-tracking charge pump for fast-locking PLL”. 2007. 41–44. H. 37. AUGUST 2009. Solid-State Circuits. Lintao Liu. “A nonlinear phase frequency detector for fast-lock phase-locked loops”. “Fast frequency acquisition phase-frequency detectors for GSamples/s phaselocked loops”. Hu. 877–885. IEEE TRAN ON Circuits and Systems. vol. 2002. 35. IEEE J.I. T. H. 2009.L. Electron.. pp.IEEE Electronics Letters. Fengchang Lai.

W. “A CMOS VCO for lV.2 GHz CMOS Dual-input Two-stage Ring VCO”. Geiger.” IEEE J. 2006. Vol27 .Feb 2007 . Aug 2001. 18 Huiting Chen.C.11. GLOSSARY OF TERMS USED CMOS UDSM PFD IC DSP CP VCO PLL PSRR CMRR CMR MOSFET WiMAX. “A FAST-Locking Digital Phase Locked Loop”. 19 Wei-Hsuan Tu.. 1996. 48.G. 1723-1732 Nov. “A 50-GHz Phase-Locked Loop in 130-nm CMOS”. M. vol. Vol26 pp 21-24 .. pp. pages(s) 742-746 . pp.” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing.K.S. 21 Changhua Cao..T. Jyh-Yih Yeh. O. “A 900 MHz CMOS Low Phase noise voltage controlled ring oscillator. Vaishnava.Ch'ing. Yanping Ding.60 (61) BHARAT ROONWAL 2008HB99501 16 Kuo-Hsing Cheng . Luong. Vol 1. page 150-155 Aug. pp. vol. 17 J. IEEE CICC . 20 Yan. 22 Wagdy. 134-137 Aug. . August 2002. Complimentary Metal Oxide Semiconductor Ultra Deep Sub Micron Phase Frequency Detector Integrated Circuit Digital Signal Processing Charge Pump Voltage Control Oscillator Phase Lock Loop Power Supply Rejection Ratio Common Mode Rejection Ratio Common Mode Range Metal Oxide Semiconductor Field Effect Transistor Worldwide Interoperability for Microwave Access. Maneatis.8V 2.216 – 221. IEEE Proc. pp 66-70 . . “Transfer characterization of CMOS ring voltage controlled oscillators”.5-5.Wen Lai and Yu-Lung Lo.F.2004. Hung-Chieh and Tsai Chorng-Kuang Wang. K.. S. IEEE Conf. IEEE Conf.. “Low-jitter process-independent DLL and PLL based on self-biased techniques. H. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.31 no.2004. “A 1. Solid-Srare Circuits. lGHz PLL Applications”.

ii.61 (61) BHARAT ROONWAL 2008HB99501 CHECKLIST Is the Cover page in proper format? Is the Title page in proper format? Is the Certificate from the Supervisor in proper format? Has it been signed? Is Abstract included in the Report? Is it properly written? Does the Table of Contents page include chapter page numbers? Does the Report contain a summary of the literature survey? Are the Pages numbered properly? Y Are the Figures numbered properly? Y Are the Captions for the Figures and Tables proper? Are the Appendices numbered? Y Does the Report have Conclusion / Recommendations of the work? Are References/Bibliography given in the Report? Y Have the References been cited in the Report? Is the citation of References / Bibliography in proper format? Y a) b) c) d) e) f) Y Y Y Y Y Y Y Y Y i. iii. . iv.

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