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**13µm Adder for DSP Block in Wireless Sensor Node
**

S.Saravanan Department of ECE, K.S.R.College of Technology Tiruchengode637215, India. saravanan.nivi@gmail.com Abstract-This paper explores the design approach of a low power Hybrid Encoded Booth Multiplier (HEBM) with Reduced Switching Activity Technique (RSAT) and low power 0.13µm adder for DSP functions that encounter a wide diversity of operating scenarios in battery powered low power wireless sensor network system. This RSAT approach has been applied on the hybrid encoder of the multiplier to reduce the power consumption. The hybrid encoder in the low power multiplier uses both the Booth and proposed technique. If the number of 1’s less than or equal to three the proposed encoding technique used otherwise go for Booth technique. The proposed adder cell used in the multiplier block consumes less power than the other previous adder techniques. The switching activity of the proposed multiplier has been reduced by 86% and 46% compared with conventional and Booth multiplier respectively. It is observed from the device level simulation using TANNER 12.6 EDA that the power consumption of the proposed multiplier has been reduced by 87% and 26% compared with conventional and Booth multiplier. Keywords-low power, Hybrid Encoded Booth Multiplier, RSAT, wireless sensor node. M.Madheswaran Department of ECE

**Muthayammal Engineering College
**

Rasipuram-647408, India madheswaran.dr@gmail.com

efficient Digital Signal Processing (DSP) modules are becoming necessary in wireless sensor networks, in which tens to thousands of battery operated micro sensor nodes are deployed remotely and used to relay sensing data to the end user [1-4]. The DSP functions mostly make use of the Multiply and Accumulate (MAC) operation in which the multiplication function is the most power consuming task. It is essential to implement the power-efficient multipliers for low power DSP modules. The development of multiplier with short critical path and low power consumption has become the important area of investigation. The inclusion of multiplying capabilities to processor architecture can provide increase in performance for low power wireless multimedia and DSP applications. These DSP applications may be Fourier Transform (FFT), Discrete Cosine Transform (DCT), quantization, or neural networks. It is well known that the clamp down approach of dynamic power which is the major part of total power dissipation may provide significant reduction in power consumption. This can be achieved by minimizing the transition capacitance. The reduction of dynamic power consumption by minimizing the switched capacitance has been reported by many researchers [5-11]. Choi et al [5] proposed Partially Guarded Computation (PGC) which divides the arithmetic units such as adders and multipliers into two parts, and freeze the unused part to minimize the power consumption. The reported results show that the PGC can reduce power consumption by 10% to 44% in an array multiplier with 30% to 36% area overhead in speech related applications. A 32-bit 2’s complement adder equipping a DynamicRange Determination (DRD) unit and a sign-extension unit was reported by Chen et al [6]. This design tends to reduce the power dissipation of conventional adders for multimedia applications. Chen et al [7] presented a multiplier using the DRD unit to select the input operand with a smaller effective dynamic range to yield the Booth codes and it saves 30% power dissipation than conventional ones. Benini et al [8] reported that, the technique for glitching power minimization by replacing some existing gates with functionally equivalent one. This saves 6.3% of total power dissipation since it operates in the layout level environment which is tightly restricted. The double-switch circuit-block switch scheme

I.

INTRODUCTION

Wireless sensor networks are composed of a set of autonomous microsystems scattered in a specific environment. Each node monitors physical quantities of its close environment and the measured data are stored and then sent through the self organized network to a base station. Main applications of these sensor networks are monitoring of environmental physical quantities such as temperature, humidity or vibrations in different places such as buildings, industries or automotive environments. Low power and low energy VLSI circuits have become an important issue in today's consumer electronics. The number of embedded devices that must run with battery power or parasitic power are increased. The traditional approaches for designing these systems vary according to the need of low power design. Improving the performance and reduce the power consumption of the circuit designs are having the challenges in low power VLSI Design. The energy

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low power multiplier architecture with reduced switching activity technique has been introduced. 1. The complementary pass transistor logic full adder with swing restoration structure uses 32 transistors was reported by A. Zhuang [18].Ko [14] and P.transistor logic and the complementary CMOS logic styles is that the source side of the pass logic transistor network is connected to some input signals instead of the power lines. The combination of the signal flow optimization (SFO). however the actual inputs to the multiplier are typically less such as 8 bit. division. like adders. Today CMOS circuits become complete digital systems through the combination of functional units. A node’s digital signal processing circuits are typically used for digital signal processing of collected data and implementation of the protocol stack. DSP and radio transceiver. and upper/lower split structure was incorporated in the design to optimize the array multipliers by Huang [11] and it is reported that the new approach can save about 20% power dissipation. The basic difference between the pass. In general. This multiplier can be used in the DSP blocks of the wireless sensor nodes. P. The ensemble of different size multipliers . exponentiation and MAC units reported by U. A Transmission Function full Adder (TFA) based on the transmission function theory was presented by N. Chandrakasan [17]. as shown in Fig 2. which results in smaller number of transistors and smaller input load. The complementary CMOS full adder is based on the regular CMOS structure with pMOS pull-up and nMOS pulldown transistors was reported by A. Chang et al [20] proposed a hybrid style full adder circuit in which the sum and carry generation circuits are designed using hybrid logic styles. The advantage is that one pass-transistor network is sufficient to implement the logic function. In practice. Full adder is the core element of complex arithmetic units like addition. data processing. These are the fundamental building blocks of DSP and microcontrollers for protocol stacks. The micro sensor network consists of hundreds to thousands of nodes and individual node consists of an array of sensors.Song [15]. such as 64 bit. Calculating an 8-bit multiplication on a 64-bit multiplier can lead to serious energy inefficiencies due to unnecessary digital switching on the high bits. Multiplier circuits are typically designed for a fixed maximum operand size. Shams [16]. A/D conversion. communicating and power supply as shown in Fig. Wen et al [12] reported that the turning off some columns in the multiplier array whenever their outputs are known can save 10% power consumption for random inputs. II. In order to improve the performance of the multiplier in this paper. An architectural solution to high input bit width diversity is the incorporation of additional smaller multipliers of varying sizes. Figure 2.H.J. multipliers and memory cells. The input bit size variation of the multiplication is a source of operational diversity and large monolithic multiplier circuits are insufficiently power aware. left-to-right leapfrog (LRLF) structure.capable of reducing power dissipation during down time by shortening the settling time after reactivation was proposed by Henzler [9].Chen [13] reported that the spurious power suppression technique has been applied on both compression tree and modified Booth encoder to enlarge the power reduction. K. multiplication. they can be broadly divided into two major categories: the complementary CMOS and the passtransistor logic circuits. WIRELESS SENSOR NETWORK Figure 1. Huang et [10] also presented the arithmetic details about the signal gating schemes and illustrates 10% to 45% power reduction for adders.Weste [19] presented a Transmission Gate Adder (TGA) using CMOS transmission gates circuit is a special kind of pass-transistor logic circuit. N. Several varieties of static CMOS logic styles have been used to implement low-power one bit adder cells. In a Wireless Sensor Network (WSN) the node consists of four major components: sensing.

The ensemble routes each pair of incoming operands to the smallest multiplier that can compare the result to take advantage of the lower energy consumption of the smaller circuit. each of which is energy efficient for a small range of inputs. III. In the Partial Product (PP) compression the row bypassing has been used when the entire row of the PP is zero. The detection logic circuit used to detect the effective data range. If the condition is satisfied control goes to the proposed technique other wise control goes to modified Booth encoding. A glue circuit has been used to control the carry and sign extension unit which will manage the sign. When a portion of data does not affect the final computing results. reducing the energy overhead of unused bits. Now the 16 bit is separated in to two 8 bit and again check for three 1’s. This is done by freeze the adder at that time of the above scene occurs and it will avoid the unwanted switching activity and save power. consider the entire 16 bit other wise go for 8 bit encoding. takes the place of a single system whose energy consumption does not scale as gracefully with input. the data controlling circuit latch this portion to avoid useless data transitions. In the adder unit a column bypassing provision is available to avoid the unwanted addition operation where ever it’s possible. multiplier and controller. An ensemble of point systems. It consists of three major working units as hybrid encoder. Block diagram of proposed hybrid encoded low power multiplier Operation Position of the 1 . HYBRID ENCODED BOOTH MULTIPLIER The proposed hybrid encoded low power multiplier basic block diagram has been shown in Figure 3. Incoming multiplications are routed to the smallest multiplier that can compute the result. Consider a 16 bit encoding if the number of 1’s in the multiplier less than or equal to three. The power consumption has been reduced further by using the proposed low power multiplier and low power adder. MULTIPLICATION Multiplicand CONTROLING Multiplicand Multiplier ENCODING Multiplie r PP Generator Recode Selector Proposed Encoder Booth Encoder Row Bypassing Detection Logic PP Compression Asserting Circuit Glue Circuit Final Adder with Column Bypassing Sign Extension Register Category Number of 1's in the multiplier PRODUCT Figure 3. This proposed multiplier uses hybrid encoding technique and reduced switching activity technique.

5% and 25% compared with conventional and Booth encoding respectively.1 1st bit Add 0 to Multiplicand (M) B Here a new hybrid encoding scheme has been proposed 1 as shown in the following Table I. add M and shift the result left by i transistor is shown in Fig 6. If Here a pull down nMOS transistor is connected near the the number of 1’s has been more than three then the carry output which has been used to give the undistorted carry h th output. j and multiplier split in to two and the same above process is continued. Figure 3. the Shift M left by i-1 and can be defined. The proposed full adder cell is shown in Figure 5 which consists of both sum and carry circuit. add M and shift the result left by i-1 E 3 st th =1 .13µm TSMC technology files were used for simulation. The sum and carry circuit are designed according to the following equations. Moreover in our proposed technique no need for 2’s complement process and virtual 0 which is to be placed as a first bit of Booth recoding. Shift M left by i-1 and add M D 2 i and i+jth bit th C = AB + BC + CA S = A′B′C + A′BC ′ + AB′C ′ + ABC (1) (2) Shift M left by j . number of 1’s in Figure 5. add M and shift the result left by j-i. Figure 8. The proposed full adder cell the multiplier has been one and its position is first bit. Figure 2. For this 0. C HYBRID ENCODING SCHEME 2 1st and ith bit IV. 0 1 0 1 0 1 0 1 Multiplicand (85) X 0 0 1 0 0 0 1 0 0 Multiplier (34) +1 -2 +1 -2 Booth recoding (4PP) Proposed recoding (1PP) Group 4 1 0 1 1 0 1 0 0 1 0 1 0 Result (2890) Figure 6. the 3 result has been arrived by add zero to the multiplicand (M). add M and shift the result left by j-i. operation add 0 TABLE I. Figure 6. LOW POWER ADDER CIRCUIT DESIGN Figure 1. Figure 5. Figure 4. . According to the number ith bit of one’s and the position of 1 presented in the multiplier. Hybrid encoded multiplication . The constant value bit is now multiplied with the the sum and carry circuits are joined together. Figure 7. multiplication it needs The output wave form of the full adder with pull down 8 partial products for conventional multiplication and 4 hift M by k-j . By this the number of switching activity has been reduced to12. In the above proposed adder four inverters are used . add M and shift the result left by i-1 h F For example according to category A. partial products for Booth recoding but only one partial product is enough for our proposed hybrid encoding method. j and kth bit hift M by k-j . Output wave form of the full adder Figure 4. Here the kth 34 neighbouring value 85 as shown in Figure 4.

33 0.83 0.49 0.18 0. TABLE II. pp.28 0. Macii.9. J. and Y. 418–433.Cho. and D. Jeon.12 4.0 2.H. TGA.13µm adder has been presented.77 11. Wang.32 0.Chandrakasaran.35 1.36 In this paper the design approach of a low power Hybrid Encoded Booth Multiplier (HEBM) with Reduced Switching Activity Technique (RSAT) and low power 0. 11.26 4. Micheli. The power and delay of above mentioned adders with supply voltage ranges from 0. pp.Chandrakasan.33 0.” IEEE Transaction on Very Large Scale Integration (VLSI) System.12 4.360-365.Schmitt-Landsiedel.4 V are shown in the Table II for comparison.28. no. “Energy-centric enabling technologies for wireless sensor networks.4 Booth multiplier which needs 4PP and proposed multiplier which needs 1PP. vol. 103–104.51 0.26 0. Wang.8 V. 19.8 1. N.2 0.Chandrakasan. Scarsi. R.42 1.02 0. L.05 1.39 1.0 2. pp. The hybrid encoder in the low power multiplier uses both the Booth and proposed technique. The power consumption of the proposed multiplier has been reduced by 87% and 26% compared with conventional and Booth multiplier. CPL.66 1. REFERENCES [1] [2] A. 2. 40. This RSAT approach has been applied on the hybrid encoder of the multiplier to reduce the power consumption.39.71 3. 2002.” in Proceedings of IEEE International Symposium on Low Power Electron. TFA. Choi. J.32 0. The proposed adder cell used in the multiplier block consumes less power than the other previous adder techniques.9 17.12 2. pp.32 0.26 0. Jan.” IEEE Signal Processing magazine vol. pp. O.90 15. 8.92 0.” IEEE Transaction on Very Large Scale Integration (VLSI) System.6 2. vol. vol.60 3. additional buffers are required at each output.6.Min.29 0. vol.4 [5] 0.27 0.19 0. and K. M.Min and P. Choi.” Electronics Letter. This low power multiplier can be used in DSP functions that encounter a wide diversity of operating scenarios in battery powered low power wireless sensor network system. “Energy.59 0. VI. By this proposed technique the number of partial products reduced.6 10. 3.33 Delay in ns 0. S.19 0. The operating frequency is set at 100 MHz. 9.8 1. [3] [4] POWER AND DELAY ANALYSIS OF DIFFERENT MULTIPLIERS Parameter Power (mw) Delay (ns) Power (mw) Delay (ns) Power (mw) Delay (ns) Vdd in volts 0. 2003.84 1. “Power minimization of functional units by partially guarded computation.8 V to 2.2 10.25 0. D.4.32 0. E.16 2. [9] . Dec.23 0. pp.25 0.757-772.83 8. J. G. vol.17 0.80 0.93 0. S. Aug.04 0.42 0. no 4.39 0.6 16. RESULTS AND DISCUSSIONS The various adder circuits like C-CMOS. Chen. 2000. Aug.77 0. TFA and TGA have lesser transistor count but due to the lack of drivability.6 EDA the switching activity of the proposed multiplier has been reduced by 86% and 46% compared with conventional and Booth multiplier respectively. The excessive power dissipation and long delay are attributed to the threshold voltage drop problem and the poor driving capability of some internal nodes at input combinations that create non full-swing transitions. M. R. Sheen. S.Wang and A.2002. Hybrid is slightly faster than C-CMOS and as a result.01 1.98 0.5 15.08 0. It is shown that the proposed adder cell consumes less power than the other adder cells in all operating voltage ranges. Despite being the fastest circuit. it exhibits smaller power-delay-product than C-CMOS except at very low voltage of 0.aware architectures for a real-valued FFT implementation. Wang and A. vol.56 0.49 0. July 2002.6 EDA tool. pp. It is observed from the device level simulation using TANNER 12. 2003. CONCLUSON Adder type Power in µw C-CMOS [16] CPL [17] TFA [18] TGA [19] Hybrid [20] Proposed C-CMOS [16] CPL [17] TFA [18] TGA [19] Hybrid [20] Proposed TABLE III.48 1. CPL consumes higher power than hybrid and CCMOS because of its dual-rail structure and the substantial number of internal nodes.17 0.64 3. R.28 [6] [7] [8] Table III shows the power consumption comparison of conventional multiplier which needs 8 partial products (PP). Jun. 10. “Quantifying and enhancing power awareness of VLSI systems. pp.11 1.03 1. Berthold.53 0. “Energy efficient DSPs for wireless networks.06 0.9 4. Chen. “A low power adder operating on effective dynamic data ranges.2 1. “Minimization of switching activities of partial products for designing low-power multipliers. no 4. no. Benini. no.” proceedings of IEE Wireless Communications. A. G.91 5.Chandrasekaran.” IEEE Transaction on Very Large Scale Integration (VLSI) System.25 6. 2002.24 0. The switching activity of the proposed multiplier has been reduced by 86% and 46% compared with conventional and Booth multiplier respectively. Bhardwaj. Multiplier type Conventional multiplier Booth multiplier Proposed multiplier 0. 287–297.01 4. Wu.75 1.Shih. Devices.30 2. “Fast power-efficient circuit-block switch off scheme. 131–136. W. A.6 2.60 0. Wang and A. hybrid and proposed adders are simulated using the TSPICE TANNER 12.0 8.7 17.50 1.25 2.27 0.”Proceedings of International Symposium on Low Power Electronics and Design. E.27 0.” IEEE Transaction on Very Large Scale Integration (VLSI) System. POWER AND DELAY ANALYSIS OF DIFFERENT ADDERS Vdd in volts 0. no.79 0. M.09 0.40 2.435–453. June 2000.03 11. O.Bhardwaj.53 1.91 1.64 6. 2004. and R.V.68-78. Macii. no.P. The power consumption of the proposed multiplier has been reduced by 87% and 26% compared with conventional and Booth multiplier. Georgakos. and S. “Glitching power minimization by selective gate freezing. Henzler. A.27 0. pp.Ickes.53 2. Poncino. August. which increase their short-circuit power as well as switching power.3.2 1.

M. M.” IEEE Journal on Solid-State Circuits. N.performance CMOS adders. volume. Gu. pp.327-333. U. Ercegovac. pp.J. MA: Kluwer. 27. 13. “A low power multiplier with spurious power suppression technique. P. Sep. MA: Addison-Wesley. Z.C. “Low-power parallel multiplier with column by passing. K.Song and G.S.” IEEE Transaction on Very Large Scale Integrartion (VLSI) System. Shams. “A review of 0.” IEEE Transaction on Very Large Scale Integration (VLSI) System vol.2. Brodersen.speed multiplication. 20–29. Systems & Computer.D.1991 A.” IEEE Journal on Solid-State Circuits. pp. May 1992 N.right array multiplier design.J. P. 12. pp. Norwell. 2005. A. 5. pp.Balsara and W. Zhang. 3. W.H. “Performance analysis of low power 1-bit CMOS full adder cells.Huang and M.1184-1198.pp. vol. T. “Circuit and architecture trade-offs for high. 15.” IEEE Transaction on. July 2007.” IEEE Transaction on Computer. 840–844. 54.Very Large Scale Integration (VLSI) System.9. “Low-power design techniques for high. May 2005. 846–850. “High performance low power leftto. Eshraghian. Chandrakasan and R. .” IEEE Transaction on Very Large Scale Integration (VLSI) System. 1995. Zhuang and H.7.Weste and K.867-871. [15] [16] [17] [18] [19] [20] P. Huang and M. pp. J. Reading. Wang and Y.Chen and Y. “On signal-gating schemes for low power adders. Bayoumi. 41. S. 1993. 1. March 2005. 10. Wen. no. no. “A new design of the CMOS full adder. 686– 695. June 1995.Ercegovac.H.3.vol.[10] [11] [12] [13] [14] Z. no.Lee.Chu. pp. D. no. C. Vol.Ko. 581–583.6.no. no. Feb.Perspective. vol. Hu.18-µm full adder performances for tree structured arithmetic circuits.” Electronic Letter vol. Principles of CMOS VLSI Design.. vol. 272-283. 2002. N. Lin. Low Power Digital CMOS Design. 2001.26. Chang. pp. no.De Micheli.” Proceeding of 35th Asilomar Conference on Signal. Darwish and M. no. A System.

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