SPWNE555D

Elektronische Bauelemente
RoHS Compliant Product

Single Timer

DIP-8

Description
The SPWNE555D is a highly stable timer integrated circuit. It can be operated in Astable mode and Monostable mode. With monostable operation, the time delay is controlled by one external and one capacitor. With a stable operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor.

D
GAUGE PLANE

Features
A

E

* Turn Off Time Less Than 2uSec * Adjustable Duty Cycle

SEATING PLANE Z Z

b
L
SECTION Z - Z

* Timing From uSec to Hours * High Current Driver Capability (=200mA)
REF. A A1 A2 b b1 b2 b3 c

b

e

Applications
* Time Delay Generation * Pulse Generation

* Precistion Timing

0.381 2.921 0.356 0.356 1.143 0.762 0.203

Millimeter Min. Max.

REF. c1 D E E1 e HE L

0.5334 4.953 0.559 0.508 1.778 1.143 0.356

0.203 0.279 9.017 10.16 6.096 7.112 7.620 8.255 2.540 BSC 10.92 2.921 3.810

Millimeter Min. Max.

Block Diagram & Pin Configuration

rogrammed by pacitor CT to ground .Operation 500kHz nts up to

This is the reference output .It provides charging current for capacitor CT

http://www.SeCoSGmbH.com/

Any changing of specification will not be informed individual

01-Jun-2002 Rev. A

c

Page 1 of 5

55 this pin (with 5. Note2: Tested at VCC=5V and VCC=15V. 16 6 15 Unit V mA mA % ppm/ : Electrical Characteristics Parameter Supply Voltage Symbol VCC ICC Supply Current (Note 1) Timing Error(monostable) Initial Accurary (Note 1) Drift with Temperature Drift with Supply Voltage Timing Error(astable) Initial Accurary (Note 1) Drift with Temperature Drift with Supply Voltage Control Voltage Threshold Voltage Threshold Current (Note 3) Trigger Voltage Trigger Current Reset Voltage Reset Current Low Output Voltage VCC=5V.67 2.4 mA 0. Isink=100mA tR tF ILKG %/V High Output Voltage Reset Time of Output Fall Time of Output Discharge leakage Current 2. http://www.5 Typ.1 F t/ VCC VCC=15V VC VCC=5V VCC=15V VTH VCC=5V ITH VCC=5V nd resistor set Vtr VCC=15V Itr Vtr=0 Vrst Irst VCC=15V.0 11.1 1. Isink=50mA VCC=5V.0 V 2.1 F t/ VCC ACCUR RA=1k to 100k t/ T C=0.3 15 2.5 5 5.0 V 9.33 4. A Page 2 of 5 .SeCoSGmbH.2 10. 3 10 1.1 Unit V mA mW : : : Max. Note3: This will determine the maximum value of RA+RB for 15V operation.3 5 100 nSec 100 nSec 20 100 nA Note1: Supply current when output is high typically 1mA less at VCC=5V.0 A 0. RL= VCC=15V. Isink=200mA VOH VCC=15V.6 V 2.1 0.05 0.25 V 0.0uF Pin on time of the0.2 V low frequency rolloff and input impedance.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev.75 13.3 %/V 9.0 10.7M .25 % ppm/ : 150 0.25 A 1.0 10. Isink=100mA VCC=5V.7 1.06 0.4 0.SPWNE555D Elektronische Bauelemente Single Timer : Absolute Maximum Ratings (Ta=25 : ) Parameter Supply Voltage Output Current Power Dissipation Lead Temperature (10sec) Operating Temperature Storage Temperature Symbol VCC IO Pd Tlead Topr Tstg (TA=25 : V CC=5 ~ 15V) Value 16 200 600 300 0 ~ 70 -65 ~ 150 Test Conditions Min 4. Isink=5mA VCC=15V.33 capacitor at V 2) 3.5 V 12.0 V 0.3 0. and for 5V operation the maximum total is R=6.35 12. Isink=10mA VOL VCC=15V.0 50 0.6 3. RL= ACCUR RA=1k to 100k t/ T C=0. the maximum total is R=20M .75 0.75 3.1 a3.1 circuit is affected by the 0.8 V 3. The 4.

SPWNE555D Elektronische Bauelemente Single Timer Characteristics Curve (UVLO) VCC = 15 V ht tp://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 3 of 5 .

A Page 4 of 5 . Output Power è è è è Load http://www.SPWNE555D Elektronische Bauelemente Single Timer vs.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev.SeCoSGmbH.

RB and discharge through RB only. one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3). One input of lower comparator is at voltage of 1/3VCC. flip-flop circuit is set output high.693 (RA+RB) C1 and the discharge time (output is low) T2 is 0. That is.44 1.44 (RA+2RB)*C1 (RA+2RB)*C1 The duty cycle is given by D. In the internal circuit of SPWNE555D.C. output is high and when C1 discharge through RB. Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). 1 VccVcc Vcc 3 Vcc Vcc 2 Vcc Vcc VccVcc 1 Vcc 3 In =0. The external capacitor C1 of Pin 6 and Pin 2 charges through RA.693*(RA+RB)*C1 T2=0. Then the frequency of astable mode is given by f= 1 T = 1. A Page 5 of 5 . The charge time (output is high) t1 is 0. another input is connected to Pin 6. when C1 charges through RA and RB. transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1.693(RA+2RB)*C1. output is low.693*RB*C1 Thus the total period time T is given by T=T1+T2=0. the flip-flop circuit is reset and output is low. = T2 T = RB RA+2RB RA+2RB . http://www. discharge transistor Q1 turn off and C1 charges through RA and RB.SPWNE555D Elektronische Bauelemente Single Timer Application Circuit FLIP-FLOP Application Notes The application circuit shows astable mode configuration.693 T1=0.SeCoSGmbH. Therefore.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev.693RB*C1. Therefore. As soon as C1 is charging to higher than 2/3VCC.

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