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BYU ECEn 320
Know Your Unit Prefixes
deka- D 101 -hecto- h 102 -kilo- k, K 103 210 k = 103 and K = 210 mega- M 106 220 giga- G 109 230 tera- T 1012 240 peta- P 1015 250 exaE 1018 260 zetta- Z 1021 270 yotta- Y 1024 280
BYU ECEn 320
deci- d centi- c milli- m micronanopicofemtoattozeptoyocto-
10-1 10-2 10-3 10-6 10-9 10-12 10-15 10-18 10-21 10-24
n p f a z y
Synchronous System Timing
Clock Jitter, Setup Time, Hold Time
BYU ECEn 320
• Very important with most sequential circuits
– State variables change state at clock edge.
BYU ECEn 320
Sample Clock Specifications
Virtex 2.5V FPGA Datasheet Xilinx Corporation Version 1.3, 1999
256Mb SDRAM Datasheet Micron Corporation 2002
BYU ECEn 320
• Jitter is the phase variations that happens in a clock signal as a result of noise, patterns, or other causes, with a frequency of variation greater than a few tens of Hertz. • Slower changes in phase due to temperature, voltage, and other physical changes are usually referred to as "wander." • Period Jitter: The short-term variations in the clock period.
BYU ECEn 320
Measurement of Clock Jitter
• The variations in every clock period sampled are plotted as a histogram of the number of periods with a given length. It has normal distribution. • The outer curve is the accumulated count (in this case, 865,000 samples). Peak-to-peak period jitter is 56.2 ps. • The inner curve is the latest sampled count of 1000 periods. Peakto-peak period jitter is 34.2 ps.
BYU ECEn 320
Clock Jitter Example
Spartan-II 2.5V FPGA Family DC and Switching Characteristics Xilinx Corporation Version 2.6, August 2002
BYU ECEn 320
D flip-flop timing parameters • Clock-to-q propagation delay (from CLK) • Setup time (D before CLK) • Hold time (D after CLK) tres BYU ECEn 320 Xilinx Flip-Flop Variations BYU ECEn 320 5 .
Xilinx Flip-Flop Variations BYU ECEn 320 Xilinx Flip-Flop Timing BYU ECEn 320 6 .
The input is not stable long enough before the clock edge. Input Tsu Clock BYU ECEn 320 7 . Ts ) Minimum time before the clocking event by which the input must be stable Hold Time (Th ) Minimum time after the clocking event during which the input must remain stable Input Tsu Clock BYU ECEn 320 Setup and Hold Time Violations Invalid! Input value changes after the setup time.Setup and Hold Times There is a timing There is a timing "window" around the "window" around the clocking event clocking event during which the input during which the input must remain stable must remain stable and unchanged and unchanged in order in order to be recognized to be recognized Th Setup Time (Tsu .
Th Input Clock BYU ECEn 320 Taking your friend to the train . you will miss the train. The input is not stable long enough after the clock edge. If you leave before 7:40.Setup and Hold Time Violations Invalid! Input value changes before the hold time. . when should you leave your house? At 7:40! (“setup time” is 20 minutes before the event) If you leave after 7:40. . If the train leaves at 8:00 (the event) and you live 20 minutes away from the station. BYU ECEn 320 8 . you should have enough time to get to the station before it leaves.
If he does not have continuous help for five minutes.Helping your friend onto the train . This allows the input to change slightly before the clock edge without disturbing the operation of the flip-flop. BYU ECEn 320 9 . The region can be to The region can be to the right or left of the the right or left of the clock edge when the clock edge when the setup or hold times setup or hold times are negative. he will fall off the train. When the hold time is negative. the valid region is to the left of the clock edge. clock edge. . . your friend will fall off the train. are negative. your friend needs help staying on the train. How long should you help your friend stay on the train after the train has left the station? At least five minutes (“hold time”) or 8:05 at the earliest. Once the train has started. BYU ECEn 320 Negative Hold Time Input Tsu Th (Negative Hold Time) Clock The valid region or The valid region or "window" associated "window" associated with the clock event with the clock event does not have to be does not have to be centered around the centered around the clock edge. Without your help for the full 5 minutes.
BYU ECEn 320 10 . the valid region is to the right of the clock edge. clock edge.Negative Setup Time The valid region or The valid region or "window" associated "window" associated with the clock event with the clock event does not have to be does not have to be centered around the centered around the clock edge. D Clk Tplh Q Tcq T phl Tcq The propagation delay is usually different for the low to high and high to low transitions. BYU ECEn 320 Clock-to-Q Propagation Delay The output of a flip-flip does not change instantaneously at the clock edge. The change in output occurs after a propagation delay through the flip flop. The region can be to The region can be to the right or left of the the right or left of the clock edge when the clock edge when the setup or hold times setup or hold times are negative. Note: you cannot have both a negative setup time and a negative hold time! Input Tsu (Negative Setup Time) Clock Th When the setup time is negative. are negative. This allows the input to change slightly after the clock edge without disturbing the operation of the flip-flop.
max and typical) D Tsu 20 ns Th 5 ns Tw 25 ns Tplh 25 ns 13 ns T su 20 ns Th 5 ns Clk Q T phl 40 ns 25 ns All measurements are made from the clocking event that is.Timing Specifications 74LS74 Positive Edge Triggered D Flipflop • Setup time • Hold time • Minimum clock width • Propagation delays (low to high. the rising edge of the clock BYU ECEn 320 Cascaded Flip-Flops IN D Q Q0 D Q Q1 C Q CLK C Q Clock IN Q0 Q1 BYU ECEn 320 11 . high to low.
IN.Cascaded Flip-Flops Are the Setup and Hold Times met? Q0: Input is IN IN D Q Q0 D Q Q1 C Q CLK C Q Setup and hold times are met if the input. Won’t this violate the hold time of Q1? Does it violate the setup time of Q1? C Q CLK C Q Clock IN Q0 Q1 BYU ECEn 320 12 . does not change within the valid region or window. Clock IN Q0 Q1 BYU ECEn 320 Cascaded Flip-Flops Are the Setup and Hold Times met? Q1: Input is Q0 IN D Q Q0 D Q Q1 Wait! Q0 is changing right at the clock edge.
Cascaded Flip-Flops Are the Setup and Hold times of Q1 met? IN Tcq Q0 Th Q1 Th Tcq As long as Tplh > Th and Tphl > Th Do we use Tplh min or max? BYU ECEn 320 Cascaded Flip-Flops Are the Setup and Hold times of Q1 met? IN Tcq Q0 Th Q1 Tcq Th If Tplh < Th or Tphl < Th. there is a hold time violation! BYU ECEn 320 13 .
BYU ECEn 320 14 .Tskew • Jitter has no effect on hold time margin since hold time margin is not a function of the clock period.Thold IN D Q Q0 Q0’ Comb D Q Q1 C Q CLK C Q • Hold-Time Margin with clock skew (discussed next lecture) = Tcq_min + Tcomb_min .Cascading Flip-Flops • Flip-flop families are designed to guarantee that Tcq(min) > Th • You can safely mix within a flip-flop family • If you mix flip-flop families.Thold . you need to make sure that Tcq(min)_fam1 > Th_fam2 & Tcq(min)_fam2 > Th_fam1 • You cannot solve this kind of problem by slowing down the clock. • Problem occurs when you mix fast flip-flops with slow ones (propagation delay of fast flip-flop). – Artificial delays may need to be added BYU ECEn 320 Hold-Time Margin • Tcq_min + Tcomb_min ≥ Thold • Hold-Time Margin = Tcq_min + Tcomb_min .
Cascaded Flip-Flops How fast can you clock this circuit? IN D Q Q0 D Q Q1 C Q CLK C Q T ? clk Clock Q0 Q1 BYU ECEn 320 Cascaded Flip-Flops How fast can you clock this circuit? IN D Q Q0 D Q Q1 C Q CLK C Q Tclk > Tcq + Tsetup Clock Do we use Tp min or max? Tcq Q0 Q1 T setup BYU ECEn 320 15 .
Synchronous Circuit How fast can you clock this circuit? IN D Q Q0 Q0’ D Q Q1 C Q CLK C Q Clock IN Q0 Q0’ Q1 BYU ECEn 320 Synchronous Circuit How fast can you clock this circuit? IN D Q Q0 Q0’ D Q Q1 C Q CLK C Q Clock IN Q0 Q0’ Q1 Tcq T pinv T setup Tclk > Tcq + Tpinv + Tsetup BYU ECEn 320 16 .
(Tcq + Tcomb + Tsetup) – Provide timing margin for unexpected circumstances – Marginal components. brown outs • Clock Jitter – Must account for worst-case clock jitter – Tclkmin = Tclk .Tmaxjitter – Tclk ≥ Tcq + Tcomb + Tsetup + Tmaxjitter BYU ECEn 320 Synchronous Design Methodology • All loops have at least one flip-flop in the loop.Setup-Time Margin • Tclk ≥ Tcq + Tcomb + Tsetup • Setup Time Margin = Tclk . • All flip-flops clocked by the same common clock – Asynchronous preset/clear not used (except for initialization) – The clock is not gated • All inputs to the design are synchronous to the clock Combinational Logic Flip-Flops BYU ECEn 320 Synchronous Inputs 17 . engineering errors.
Synchronous Circuit Synchronous Inputs Combinational Logic Flip-Flops • There may be many flip-flops in the design • There will be many wire/gate paths from flip-flop output to flip-flop input • Minimum Clock Period: Tclk > Tcq(max) + Tdelaymax + Tsetup • Task: Identify worst-case flip-flop to flip-flop timing path BYU ECEn 320 State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A B A D Q Q B B CLK BYU ECEn 320 18 .
State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A Tp_fl 40 ns B A D Q Q B B CLK BYU ECEn 320 State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A Tp_fl + Tp_ifl 40 + 22 + 22 ns B A D Q Q B B CLK BYU ECEn 320 19 .
State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A Tp_fl + Tp_ifl + Tsu 40 + 22 + 22 + 20 = 104 ns B A D Q Q B B CLK BYU ECEn 320 State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A Tinput 35 ns B A D Q Q B B CLK BYU ECEn 320 20 .
State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A Tinput + Tp_ifl 35 + 22 + 22 ns B A D Q Q B B CLK BYU ECEn 320 State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) X B D Q Q A Z A Tinput + Tp_ifl + Tsu 35 + 22 + 22 + 20 = 99 ns B A D Q Q B B CLK BYU ECEn 320 21 .
6 MHz) X B D Q Q A Z A B A D Q Q B B CLK BYU ECEn 320 State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) Output Timing X B D Q Q A Z A Tp_fl 40 ns B A D Q Q B B CLK BYU ECEn 320 22 .State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) Feedback Path: 104 ns Input Path: 99 ns Critical Path: 104 ns (9.
State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) Output Timing X B D Q Q A Z A Tp_fl + Tp_ofl 40 + 22 = 62 ns B A D Q Q B B CLK BYU ECEn 320 State Machine Example Flip-Flop Timing Th Tsu Tplh Tphl 5 ns 20 ns 25 ns (max) 10 ns (min) 40 ns (max) 20 ns (min) Tplh Tphl Input Timing Tinput 35 ns (max) 25 ns (min) Gate Timing 22 ns (max) 10 ns (min) 15 ns (max) 8 ns (min) Output Path: 62 ns Critical Path: 104 ns (9.6 MHz) X B D Q Q A Z A B A D Q Q B B CLK BYU ECEn 320 23 .
683 6.977 clkdivide<14> 2.188 6.536 switches_d<0> 2.Static Timing Analysis • Static timing analysis tools are used to identify worst-case signal delays – Identifies every combinational path in the circuit – Calculates timing on each path – Identifies the worst-case design path • Delay file: delay of each independent net (not combinational paths) – .F4 cathodes_4_OBUF.698 N103 6.259 N104 6.866 switches_d<2> 1.F4 cathodes_0_OBUF.963 clkdivide<18>.200 anodes_2_OBUF 2.472 6.G4 cathodes_0_OBUF.dly file in the project implementation directory • Trace file: delay of each combinational path – Must run trce command on placed and routed design trce -a -v vendingmachine.ncd – .YQ 5.427 loadswitches 2.G3 BYU ECEn 320 24 .422 6.IN 0.746 GLOBAL_LOGIC0 --------------------------------- N103 u1_u1.184 switches_d<1> 1.871 switches_d<3> 1.886 anodes_3_OBUF 1.493 6.twr output file from trce command BYU ECEn 320 Delay File Example Mon Sep 16 10:50:12 2002 File: vendingmachine.986 clkdivide<13> 2.865 digitselect_d<0> 1.441 cathodes_1_OBUF.437 clkdivide<19> 3.F1 cathodes_1_OBUF.DOA3 6.986 cathodes_6_OBUF 1.G1 cathodes_5_OBUF.184 N105 5.300 N106 6.G1 clkdivide<19> clkdivide<18>.dly The 20 Worst Net Delays are: ------------------------------| Max Delay (ns) | Netname | ------------------------------6.698 6.G4 cathodes_4_OBUF.825 digitselect_d<1> 1.437 slowclkbuf.888 cathodes_5_OBUF 1.861 switches_d<4> 1.
427ns route) (54.478(R)| 0.--------------------------Total 18.130(R)| anodes<1> | 12.355(R)| 0.556 cathodes<6> cathodes_6_OBUF cathodes<6> ------------------------------------------------.621ns (data path) Source: u1_u1.A Destination: cathodes<6> Data Path Delay: 18.761(R)| cathodes<1> | 20.985 Delay(ns) BYU ECEn 320 Trace File Example Setup/Hold to clock clk ---------------+------------+------------+ | Setup to | Hold to | Source Pad | clk (edge) | clk (edge) | ---------------+------------+------------+ switches<0> | 0.432(R)| cathodes<0> | 19. 8.582(R)| cathodes<5> | 20.PAD Tioop 5.436(R)| 0.A CLB_R10C42.621ns (10.DOA3 Tbcko 3.A to cathodes<6> Location Delay type Physical Resource Logical Resource(s) ------------------u1_u1 u1_u1.300(R)| 0.001(R)| switches<1> | 0.131(R)| cathodes<4> | 19.124(R)| ---------------+------------+------------+ Clock clk to Pad ---------------+------------+ | clk (edge) | Destination Pad| to PAD | ---------------+------------+ anodes<0> | 13.7% logic.710(R)| anodes<3> | 13.S0.194ns logic.986 cathodes_6_OBUF P148.S0.441 N103 CLB_R10C42.301(R)| 0.920(R)| cathodes<3> | 19. 45.621ns (Levels of Logic = 3) Source Clock: CLK_BUFGP rising Data Path: u1_u1.406(R)| cathodes<6> | 20.452(R)| ---------------+------------+ BYU ECEn 320 25 .500(R)| anodes<2> | 13.084(R)| cathodes<2> | 18.180(R)| switches<4> | 0.179(R)| switches<2> | 0.Trace File Example -------------------------------------------------------------------------------Delay: 18.653 cathodes_4_OBUF Mrom_cathodes_inst_lut4_6 P148.G1 net (fanout=7) 6.043(R)| switches<3> | 0.Y Tilo 0.O net (fanout=1) 1.3% route) ------------------------------------------------RAMB4_R2C1.
the clock seen at one flip-flop may be slightly delayed with respect to the clock at another flip-flop • The relative delay of the clock is called clock skew BYU ECEn 320 26 .Clock Skew BYU ECEn 320 Clock Skew • Proper operation of synchronous systems requires that all registered elements are clocked at the same time • Some times this is not possible .
Causes of Clock Skew • Natural delays in clock wiring • Capacitance on clock line • Artificial delay due to improper design • Wiring delays between chips BYU ECEn 320 Three Cases of Skew • Skew is in same direction as dataflow • Skew is in opposite direction of dataflow • Type of skew is not known. IN D Q C CLK0 Q0 D Q Q1 C δ skew CLK1 IN D Q C Q0 D Q Q1 C CLK1 δ skew CLK0 Q0 D Q Q1 C IN D Q C Clock Network BYU ECEn 320 27 .
Clock Skew (Type 1)
IN D C Q Q0 D C Q Q1
• Clock CLK1 is a delayed version of CLK0 • Clock skew = tskew
BYU ECEn 320
Clock Skew (Type 1)
IN D C Q Q0 D C Q Q1
Assuming the setup and hold times for Q0 are met, are the setup and hold times for Q1 met?
Q0 CLK1 Tskew δ
BYU ECEn 320
Clock Skew (Type 1)
IN D C Q Q0 D C Q Q1
Q0 Tskew CLK1 Tsu Th Tsu Th Tsu Th
BYU ECEn 320
Clock Skew (Type 1)
IN Tcq Q0 Ts CLK1 Th Tskew T cq Ts Th Tskew
Hold Time Margin = Tcq − Thold − Tskew > 0
Should we use Tcq(min) or Tcq(max)?
BYU ECEn 320
Clock Skew (Type 1)
IN Tcq Q0 Ts CLK1 Th Tskew T cq Ts Th Tskew
Hold Time Margin = Tcq(min) − Thold − Tskew > 0 How should combinational propagation delays be handled?
BYU ECEn 320
Clock Skew and Hold Time Margin
• Hold time margin with combinational delay and skew in direction of data : Hold Time Margin = Tcq(min) + Tcomb(min) − Thold − Tskew(max) > 0 • First two terms are minimum time after clock edge that a D input changes • Hold time is earliest time that the input may change • Clock skew subtracts from the available hold-time margin • Compensating for clock skew:
– Longer flip-flop propagation delay – Explicit combinational delays – Shorter (even negative) flip-flop hold times
BYU ECEn 320
Very Long Clock Skew
IN Tcq Q0 Ts CLK1 Th Tskew Tcq Ts Th Tskew
The clock skew can be so long that setup and hold times are met. What is wrong with this condition?
BYU ECEn 320
Clock Skew and Clock Rate
IN D C Q Q0 D C Q Q1
Assuming hold-times are met, how does clock skew affect minimum clock rate on this circuit?
BYU ECEn 320
Clock Skew and Clock Rate CLK0 IN Tcq Q0 Tcq Ts CLK1 Th Tskew Tclk Assuming hold-times are met. how does clock skew affect minimum clock rate? BYU ECEn 320 Clock Skew and Clock Rate CLK0 IN Tcq Q0 Tcq Ts CLK1 Th Tskew Tclk Setup Time Margin = Tclk − (Tcq + Tsetup − Tskew) > 0 Tclk > Tcq + Tsetup − Tskew BYU ECEn 320 32 .
Tcq(min) + Tcomb(min) − Thold − Tskew(max) Decrease BYU ECEn 320 Example of bad clock distribution BYU ECEn 320 33 . assume worse case.Summary of Effects of Skew Type of Skew Skew is in same direction as data Hold Time Margin Tcq(min) + Tcomb(min) − Thold − Tskew(max) Decrease Setup Time Margin Tclk − (Tcq(max) + Tcomb(max) Tsetup − Tskew(max)) Increase Tclk − (Tcq(max) + Tcomb(max) Tsetup + Tskew(max)) Decrease Tclk − (Tcq(max) + Tcomb(max) Tsetup + Tskew(max)) Decrease Max Frequency Tcq(max) + Tcomb(max) Tsetup − Tskew(max) Increase Tcq(max) + Tcomb(max) Tsetup + Tskew(max) Decrease Tcq(max) + Tcomb(max) Tsetup + Tskew(max) Decrease Skew is in Tcq(min) + Tcomb(min) opposite direction − Thold + Tskew(max) of data Increase Skew type not specified or unknown.
fast metal (low R ==> fast RC time constant) BYU ECEn 320 34 .Clock distribution in ASICs • This is what a typical ASIC router will do if you don’t lay out the clock by hand. BYU ECEn 320 “Clock-tree” solution • Often laid out by hand • Wide.
Clock Skew in FPGAs • Wiring delays in FPGAs are relatively long – Wiring delay much longer than gate delay – Custom ICs: gate delays dominate wiring delay • FPGAs use a segmented routing structure – Each wire consumes multiple routing segments – Routing segments connected by routing boxes: switches & gates – Each wire segment and routing box consume delay • It is very difficult to guarantee that all clock wires will arrive at the flip-flops at the same time BYU ECEn 320 FPGA Routing Example Routing Box Routing Box Local Interconnect Routing Box Long Line Global Line Routing Box Global Line Routing Box BYU ECEn 320 35 .
The following clock nets use non-dedicated resources: slowclock • Go back and fix design to make sure low-skew BUFG used in design BYU ECEn 320 36 .Clock Skew in FPGAs • Solution: Provide a dedicated low-skew clock wire – Single wire routed throughout entire device – Delay of wire carefully controlled (same at each FF) – High-speed (short rise and fall time) • Spartan 2 (3) FPGA – Provides 4 (8) global clock wires – Must use the BUFG primitive to use a clock wire BYU ECEn 320 Clock Skew in FPGAs • Timing reports indicate high-skew clock net WARNING:Timing:2554 . Clock skew on these resources will not be automatically addressed during path analysis.Clock nets using non-dedicated resources were found in this design. To create a timing report that analyzes clock skew for these paths. run trce with the '-skew' option.
However. there will be considerable skew between flip-flops outside of FPGA and flip-flops inside FPGA BYU ECEn 320 37 .DLL-Based Clock Design Xilinx AppNote: xapp462 BYU ECEn 320 Conventional Clock Driver CLK_PIN CLK Delay is introduced in the BUFG driver ( output of BUFG delayed from output of IBUFG ) Common delay does not increase clock skew between internal flip-flops.
CLKDLL adds appropriate delay to insure input of IBUFG (clk_pin) and output of BUFG (clk) are in phase (i.e. BYU ECEn 320 38 . Output clock is 50% duty cycle and very low jitter. delay of both BUFG and IBUFG are hidden).Xilinx Delay-Locked Loop ( DLL ) • Used to synchronize two clocks – Minimize internal clock skew – Remove internal clock buffer delays • Operates using feedback – Compares the phase of the input clock and feedback clock – Adds delay to insure CLKFB and CLKIN are in phase BYU ECEn 320 Using a Delay-Locked Loop CLK_PIN CLK The delay of an IBUFG has been characterized and is compensated for in the DLL Using feedback from BUFG output.
CLK180. and other spurious movement – The LOCKED output pin indicates that the DLL has locked synchronization – You must allow proper starting of flip-flops driven by DLL by using LOCKED signal • Input clock frequency must be stable and fall within specified frequency range • Resetting DLL: – DLL must be reset when input frequency changes – DLL must be reset when device is reconfigured • The phase and duty cycle can be controlled with attributes – CLK0. – Output clocks may introduce glitches. spikes. and CLK270 output pins BYU ECEn 320 39 . Set Set Set Set ‘0’ D Q D Q D Q D Q RST This ensures main system is reset for about 4 cycles after DCM locks BYU ECEn 320 DLL Notes • The DLL may take several thousand clock cycles to synchronize clocks. CLK90.Using a Single DLL IBUFG CLKIN_IBUFG CLKIN_IN CLKIN CLKFB This synchronizes CLK_IN with CLK… That gives control over setup times for external inputs … BUFG CLK0 CLK0 CLK To rest of FPGA… Tie to a push button DLL won’t start locking process until Rst is low. force Rst high. Until then. These are asynchronous Sets – you want them to work even before clock does RST_IN DLL LOCKED LOCKED_OUT RST Locked is asserted when the DLL has acquired the lock on the input clock.
IBUFG CLKIN_IN CLKIN CLKFB RST CLK0 DLL LOCKED BUFG To on-chip circuits To reset circuitry The DLL must be reset until the input clock is stable BYU ECEn 320 Clock Division and Multiplication CLK BUFG CLK2x CLK/16 BUFG CLKDV_DIVIDE=16 Custom outputs for 2x clock multiplier and for programmable clock division (divide by 1. the I/O buffers turn on.Dealing with Late Starting Clocks These FFs power up to the low state ‘1’ D Q … D Q When FPGA configuration is done.5 to 16) Multiple DLLs needed for further multiplication/division BYU ECEn 320 40 . Reset the DLL until after the clock starts so the DLL can acquire the lock properly. However. the input clock pin starts toggling a little late.
• Each DLL has many outputs including: – – – – CLK0: the “normal” clock output CLK90: 90 degree phase delay CLK180: 180 degree phase delay CLK270: 270 degree phase delay Coarse Phase Adjustment Using DLLs • Useful in special contexts • Not useful for “globally synchronous” designs BYU ECEn 320 The First Attempt at Clocking the SDRAM CLKIN To FPGA core… To SDRAM OBUF BYU ECEn 320 41 .
The problem is there is skew between the on-chip clock and the clock that goes to the SDRAM.The Results (not good) Setup and Hold times are not met at the SDRAM. BYU ECEn 320 Removing Board-Level Skew Clock leaving chip is synchronized to input clock (feedback delay includes board wiring) Internal clock synchronized to input clock SDRAM BYU ECEn 320 42 .
Dual DLLs One DLL gets feedback from off-chip Generates clock for off-chip devices Second DLL generates clock for on-chip Both add enough delay to achieve ideal clock alignment Entire board now behaves as one large globally synchronous system Clk-to-Q times for signals leaving FPGA are large. but all synchronous devices share one clock This solves many problems BYU ECEn 320 Dual DLLs IBUFG CLK_IN SCLK_FB From off-chip circuits CLKBUF FBBUF OBUF CLKIN CLKFB RST EXTCLK0 SCLK To off-chip circuits EXTDLL LOCKED EXTLOCK IBUF INTRST RST CLKIN CLKFB BUFG CLK0 INTDLL LOCKED CLK To on-chip circuits LOCKED_OUT To reset circuitry BYU ECEn 320 43 .
use ieee. component BUFG port ( I : in O : out end component. component CLKDLL port ( clkin : in clkfb : in rst : in clk0 : out clkdv : out locked : out ). Defined for you in UNISIM. clk_in is aligned with both clk and sclk_fb. std_logic BYU ECEn 320 44 .numeric_std. BYU ECEn 320 library ieee. std_logic). count starts counting. clk_in and sclk_fb are not aligned. std_logic. Instancing The Building Blocks Provides component definitions.Vcomponents. 6. DLL advances sclk so clk_in and sclk_fb are aligned. use UNISIM. std_logic. 2. std_logic. starts internal DLL. Reset falls. std_logic). External DLL locks. std_logic. Also provides simulation capability for your design that is ignored in synthesis… component IBUFG port ( I : in O : out end component. 4.ALL. Internal DLL locks.ALL.Simulation of Dual DLL 1 2 3 4 5 6 1. library UNISIM. 3.std_logic_1164. 5.Vcomponents std_logic. std_logic. std_logic. use ieee.ALL.
Q HIGH LOW LOW HIGH LOW HIGH HIGH LOW BYU ECEn 320 45 . say.Metastability BYU ECEn 320 The Bistable Element • The simplest sequential circuit • Two stable states – One state variable.
5V rail • Theoretical threshold center is 2.Analog Analysis • Assume pure CMOS thresholds.5 V BYU ECEn 320 Dynamic Analysis Vout1 = Vin2 Top inverter reflection line Bottom inverter Vin1= Vout2 Points of crossing indicate stable states BYU ECEn 320 Vin1 = Vout2 Vin2 = Vout1 46 .
Dynamic Analysis Vout1 = Vin2 4 3 2 Vin1 = Vout2 Vin2 = Vout1 1 Vin1= Vout2 Vout1 = T (T (T (Vin1 ))) 1 3 2 Vout 1 1 24 4 3 Vout 2 BYU ECEn 320 Metastable State • Metastability is inherent in any bistable circuit 2.5 V Vin1= Vout2 Vin1 = Vout2 Vin2 = Vout1 • Two stable points.5 V 2.5 V 2. one metastable point BYU ECEn 320 47 .5 V Vout1 = Vin2 2.
Metastability 6 4 5 2 3 1 BYU ECEn 320 Another look at metastability BYU ECEn 320 48 .
products. tcq BYU ECEn 320 49 . • Many digital designers. “metastability resolution time” can be longer than one clock period. BYU ECEn 320 Flip-Flop Decision Window If D is not stable during the decision window then metastability may occur. and companies have been burned by this phenomenon. • Especially severe in high-speed systems – since clock periods are so short.Why Study Metastability? • All real systems are subject to it – Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times.
Metastability resolution time tcq tr = Resolution time is the extra time needed to resolve the logic state BYU ECEn 320 Metastability Resolution Time • Various manufacturers use various definitions of Tr – Extra time beyond tcq to resolve metastable output – Total time after clock edge to resolve it • Pay attention to the examples to ensure you understand which it is… BYU ECEn 320 50 .
The probability that data will arrive during T0 in a clock period Tclk is: P= T0 = T0 f Tclk The probability of a metastable event happening Tclk BYU ECEn 320 Metastability Resolution Time P = e − tr /τ The probability of a metastable event lasting longer than some time.Metastability Window T0 tcq tcq tcq HOLD Assume that data arrives uniformly over clock cycle. Tclk. tr 1 τ : “Resolving Time Constant” P tr BYU ECEn 320 Linear on semi-log plot 51 .
The tallies of these masks reveal the population decay rate.How Resolution Time is Measured VOHmin Exponential decay of failures Failures VOLmax tcqMax A digital oscilloscope is used to count failure events by zones (masks). The number of masks should be chosen so that enough decay rate is observed. BYU ECEn 320 Analysis of Failure Counts Semi-log scale − 1 τ = b a BYU ECEn 320 52 . The width of each mask represents a time unit for comparing events at different times.
t P = e − t /τ r MTBF = 1 / Error Rate BYU ECEn 320 Flip-Flop Metastability Failure Time e MTBF (t r ) = T0 ⋅ f ⋅a MTBF(tr) = mean-time between synchronizer failures.Mean Time Between Failure Error Rate = Frequency of asynchronous events P=a x The probability of a metastable event happening x P = T0 f The probability of a metastable event lasting longer than some time. where a failure occurs if metastability persists beyond time tr after Tcq. f a T0 frequency of flip-flop clock number of asynchronous input changes per second Metastability time window (describes the likelihood of going metastable) Resolving time constant (describes the speed at which the metastable condition is being resolved) BYU ECEn 320 ( tr / τ ) τ 53 .
051 ns 54 .Typical flip-flop metastability parameters MTBF (t r ) r = e T0 ⋅ f ⋅ a ( t /τ ) flip-flop dependent constants BYU ECEn 320 τ and T0 are Xilinx Metastability Measurements XAPP 094 • T0 = 0.1 · 10-9 – XC4000-3 IOB: – XC4000-3 CLB: BYU ECEn 320 τ = .062 ns τ = .
increase tr) • Waiting longer usually doesn’t hurt performance • …unless there is a critical “round-trip” handshake. then some system experiences a mysterious failure every week.e. • How to get better MTBFs? – Use faster flip-flops – Wait for multiple clock ticks to get a longer metastability resolution time (i.4 · 107 · 105) = 3. BYU ECEn 320 55 .000 copies of the product.MTBF Metastability Example 10 MHz microprocessor clock Asynchronous input changes 100.5 / (0.000 times/second T0 = 0.4 (for 74LS74) τ = 1.6 · 1011 sec (~100 centuries) Note: if you ship 10. • Real-world MTBFs must be much higher. one will fail every year BYU ECEn 320 ( tr / τ ) Is 1000 years enough? • If MTBF = 1000 years and you ship 52.5ns (for 74LS74) Output must be stable 80 ns after Tcq e MTBF (t r ) = T0 ⋅ f ⋅a MTBF(80 ns) = e80/1.000 copies of your system.
Asynchronous Inputs and Synchronizers BYU ECEn 320 Asynchronous inputs • Not all inputs are synchronized with the clock – – – – – Keystrokes Switches & buttons Sensor inputs Interrupt signals Asynchronous communication protocols (UART. etc.) • Asynchronous inputs must be synchronized with system clock before being used within the system – Asynchronous inputs can cause data integrity problems if the signals are not synchronized properly. BYU ECEn 320 56 .
– Output may enter a metastable state – Time in this state is theoretically unbounded (although probability decreases exponentially with time) – Some gates may interpret metastable state as a “1” while others will interpret it as a “0” BYU ECEn 320 A One-Stage Synchronizer BYU ECEn 320 57 .Synchronization Problems • A flip-flop output may not operate correctly when setup and hold times are not met.
Maximum metastability resolution time • Maximum time that the output can remain metastable without causing synchronizer failure – The flip-flop may be metastable for a short time and return to normal before being sampled by the next FF clock ff-out tr < setup-time margin tr < Tclk − tcq(max − tcomb(max) − tsetup tcq tcomb setuptime tr BYU ECEn 320 margin setup t tr(max) = setup time margin A Two-Stage Synchronizer • If FF1 resolves in less than tr = tclk − tcq(max) − tsetup time. • SYNCIN is valid early in the clock cycle.Metastability Resolution Time • Max tr . • Easy to calculate the probability of “synchronizer failure” (FF1 still metastable when META sampled) • This is the recommended synchronizer circuit for most cases. then only META goes meta-stable. giving maximal setup margin to the synchronous system. BYU ECEn 320 58 .
4 · 107 · 105) = 3.4 (for 74LS74) τ = 1.5ns (for 74LS74) e MTBF (t r ) = T0 ⋅ f ⋅a MTBF(80 ns) = e80/1.000 times/second T0 = 0.000 copies of your system. one will fail every year BYU ECEn 320 ( tr / τ ) 59 .MTBF Metastability Example Asynchronous interrupt to a microprocessor system 10 MHz system clock Use the following synchronizer circuit Use 74LS74 parts Step 1: compute Max tr = setup time margin to FF2 tr = tclk − tcq(max) − tsetup = 100 ns − 10 − 10 = 80 ns BYU ECEn 320 MTBF Metastability Example Step 2: Compute MTBF 10 MHz microprocessor clock Asynchronous input changes 100.6 · 1011 sec (~100 centuries) Note: if you ship 10.5 / (0.
5/1.5ns − 10 − 0 − 10 = 42.MTBF Metastability Example #2 Increase clock rate to 16 MHz tr = tclk − tcq(max) − tcomb − tsetup = 62.5 ns MTBF(42.4 · 107 · 105) = 3.1 sec ! BYU ECEn 320 Multiple-cycle synchronizer tr = n · tclk − tcq(max) − tsetup MTBF (tr ) = e BYU ECEn 320 ( n ⋅ tclk − tcq (max) − tsetup ) / τ T0 ⋅ f ⋅ a What is wrong with this circuit? 60 .5 / (0.5 ns) = e42.
Multiple-cycle synchronizer Clock-skew problem BYU ECEn 320 Deskewed multiple-cycle synchronizer • Necessary in really high-speed systems • DSYNCIN is valid for almost an entire clock period BYU ECEn 320 61 .
any logic in this path must be carefully crafted and verified. possibly violating the destination flip-flop setup or hold times.. BYU ECEn 320 62 . and causing it to enter a metastable condition.Cascaded Synchronizer ASYNCIN MET1 MET2 METn . not across multiple clock domains.. • Static timing analysis tools can only operate within a clock domain. such as – Inverted clocks – Half frequency clocks • A signal driven from one clock domain arrives as an asynchronous signal in the destination-clock domain. • Paths that cross clock domains are false paths (paths that cannot be analyzed by static timing tools). CLOCK Skew problem can be eliminated by using cascaded synchronizers Probability of failure the product of failure for n+1 flip-flops ( n⋅( tclk − tcq (max) − t setup ) /τ ) ( n⋅tr /τ ) MTBF (tr ) = e =e T0⋅ f ⋅a T0⋅ f ⋅a Note that this not as effective as the multiple-cycle synchronizer since the setup-time and cq-time must be subtracted for each flip-flop BYU ECEn 320 Multiple Clock Domains • A clock domain is defined as all synchronous logic and signals driven by a single clock or multiple derived clocks that have constant phase relationships to the primary clock.
The exact delay from the signal in to out is not specified. or data • Maintain event/data order BYU ECEn 320 CLK2 Synchronous Domain Level Synchronization in out A level-signal synchronized with clk1 is translated into a level-signal synchronized with clk2. Synchronizer IN META OUT clk1 clk2 CLK2 BYU ECEn 320 63 . or drop any data • Don’t duplicate any events.Synchronizers Between Different Clock Domains Synchronizer CLK1 Synchronous Domain Synchronizer Synchronization Objectives: • Don’t miss any events.
Pulse Catcher IN CLK1 CLK2 EN RST RST clk1 clk2 Synchronizer META OUT BYU ECEn 320 Understanding the Failure Modes • Divergence of an Asynchronous Signal A divergence of an asynchronous signal can cause functional errors • Convergence of Asynchronous Signals The combinational logic with asynchronous inputs can cause glitches that are caught by the synchronizer. • Convergence of Synchronized Signals Once synchronization is completed. the structures beyond the synchronizers still matter. creating functional errors. The design must ensure that the synchronized signals do not converge—reconvergence can create functional errors. BYU ECEn 320 64 . The exact delay from the signal in to out is not specified.Pulse Synchronization in out A pulsed-signal synchronized with clk1 is translated into a pulsed-signal synchronized with clk2.
Divergence of an Asynchronous Signal SYNC1 ≠ SYNC2 BYU ECEn 320 Even Worse Divergent Paths • Combinational delays to the two synchronizers are likely to be different. BYU ECEn 320 65 .
2. 4. State A is reset. then it is propagated to the state machine. in changes near clock edge. One-hot State Machine Synchronizer B A IN (ASYNC) B CLOCK BYU ECEn 320 66 . both flip-flops go metastable. game over ! BYU ECEn 320 The Solution to this Problem A in in in is captured by a single synchronizer. but state B is not set. IN (ASYNC) in is asserted asynchronously. State machine is stuck in invalid state.Example of the Problem One-hot State Machine A in CLOCK in A B B 1. 3.
BYU ECEn 320 67 . creating functional errors. Timing cannot be checked by a static timing checker. BYU ECEn 320 Convergence of Asynchronous Signals X Combinational Logic Synchronizer Y CLKA CLKB Combinational logic can cause glitches that are caught by the synchronizer.The Way to Do It • One synchronizer per input • Carefully locate the synchronization points in a system.
Timing can be checked by static timing analyzer. Sequence of Xsync and Ysync cannot be assured during synchronization if X and Y change concurrently.The Way to Do It X Combinational Logic Synchronizer Y CLKA CLKB Add a flip-flip to filter out the glitches. because the propagation delay through the synchronizers is not predictable resulting in the loss of correlation among signals crossing clock domains. Register all signals before crossing clock boundaries. BYU ECEn 320 68 . The relative timing (order of changes) that exists between X and Y do not exist between Xsync and Ysync. BYU ECEn 320 Convergence of Synchronized Signals Synchronizer X Xsync Synchronizer Y Ysync Combinational Logic CLKA CLKB The logic beyond the synchronizers still matters. Simultaneity of Xsync and Ysync cannot be assured during synchronization.
determine what kind of synchronizer is needed. • For data bus crossings. BYU ECEn 320 69 .The Way to Do It X Combinational Logic Synchronizer Y CLKA CLKB Consolidate signals before they are sent to reduce the number of registers and eliminate the issue of relative timing between synchronized signals. it's important to eliminate the need for these arrival order (timing) dependencies between synchronizes signals. BYU ECEn 320 Multiple Clock Domain Design • Identify all of the clock domains in your circuit. Instead. define a handshake protocol. • Check for faulty structures (CAD tools can help): – Divergence of an Asynchronous Signal – Convergence of Asynchronous Signals – Convergence of Synchronized Signals • For each crossing signal. When planning the design. Try to limit the number of signal that cross boundaries. and only synchronize the control signals. • Identify signals that go from one clock domain to another. do not synchronize data.
• Errors are nearly impossible to detect in simulation and easily missed in product validation.Transferring Data Across Different Clock Domains BYU ECEn 320 Multi-Clock Systems • With increasing system integration. BYU ECEn 320 70 . • Because of the asynchronous nature of these designs. passing data or control signals between logic operating on different clock frequencies presents a special set of problems. systems operating with multiple I/O standards using multiple asynchronous clock frequencies are becoming more common. often dependent on the clock frequencies.
If you put a synchronizer in the control path the data path will work properly.Transferring Data from ACLK to BCLK Data0 Data1 Data2 ACLK BCLK Why won’t this work? • What happens if ACLK is faster than BCLK? • What happens if ACLK is slower than BCLK? • What happens if wire delays on data signals are not equal? • Can these problems be solved by putting synchronizers in the data path? BYU ECEn 320 Transferring Data from ACLK to BCLK Basic structure of data transfer circuit from ACLK domain to BCLK domain. Pulse Catcher ALOAD EN RST Synchronizer NEW BYTE META FF1 RST BLOAD FF2 Control path ACLK BCLK ALOAD CE BLOAD CE SDATA[7:0] D BDATA[7:0] Data path ADATA[7:0] D AREG BREG BYU ECEn 320 71 .
.tsetup BCLK tcq META tr tsetup tcq tr tsetup BLOAD BDATA[7:0] BYU ECEn 320 Or else .. META Resolves Low Pulse Catcher ALOAD ACLK BCLK ACLK ALOAD SDATA[7:0] NEWBYTE EN RST Synchronizer NEW BYTE META FF1 RST BLOAD FF2 tr = Tbclk − tcq .BLOAD Circuit Timing Pulse Catcher ALOAD ACLK BCLK ACLK ALOAD SDATA[7:0] NEWBYTE EN RST Synchronizer NEW BYTE META FF1 RST BLOAD FF2 tr = Tbclk − tcq .tsetup woops BCLK tcq META tr tsetup BLOAD BDATA[7:0] BYU ECEn 320 woops 72 .
second ALOAD is lost BDATA gets the wrong data First data is missed woops BCLK tcq META tr tsetup BLOAD BDATA[7:0] BYU ECEn 320 woops Resolving Timing Problems • Increase the minimum time between ALOADs to handle the worse case timing (homework problem) – Reduces the bandwidth to 1 byte / 10 ACLK periods. – Requires half as many BLOAD signals. • Increase the number of bytes transferred during each BLOAD signal – Transfer twice as much data across clock domains in same time.Timing Problems • • • • ACLK ALOAD SDATA[7:0] NEWBYTE ALOAD comes too early NEWBYTE does not get set. – New ALOAD would not be generated until after the acknowledge. • Use a handshake protocol with feedback (an Acknowledge) to insure no data is lost or duplicated. BYU ECEn 320 73 . – Increases bandwidth to 2 bytes / 10 ACLK periods. – May slightly reduce bandwidth due to overhead of the handshaking.
BYU ECEn 320 74 . the circuit synchronizes only handshake signals that signify the validity of data being transferred to the destination clock domain. ALOAD1 can happen in parallel with BLOAD because of double buffer. the system clocks the data directly to the destination module. • Normally. BYU ECEn 320 Transferring Data Across Clock Domains ALOAD ACLK ACK BCLK BLOAD SDATA • The synchronizer guarantees that signals will settle following a metastability violation. thereby preventing undetermined signal levels from propagating to the destination module.Transfer More Data at a Time Buffer two bytes of Adata before transferring both data bytes between ACLK and BCLK domains ADATA[7:0] ALOAD1 AREG1 D CE DOUBLE BUFFER D CE BLOAD BREG1 D CE AREG2 ALOAD2 ACLK D CE BCLK BREG2 D CE BLOAD generated half as often (only after ALOAD2). • Once the handshake signals transfer to the destination-clock domain. • The handshake protocol maintains signals levels long enough to ensure that the system does not miss signal events or wrongly interpret them as multiple events.
not levels • Positive and negative edge event driven • Fast • Works with any clock frequency BYU ECEn 320 75 .Handshake Protocol The handshake protocol must ensure that • the data holds stable long enough for circuitry to sample it once in the destination-clock domain • a new data-valid signal can not be asserted until the destination has acknowledged that the first data valid signal was received • data transfer works independent of both TX and RX clock frequencies TX Data Domain A RX Data Domain B BYU ECEn 320 Data Valid Ack Data Valid Ack Two-Phase Handshake Protocol • Req and Ack are signaled by edges.
4. 3.Four-Phase Handshake Protocol • Req and Ack are signaled by levels • Levels must be restored before next transfer • More slow and complex the two-phase • Works with any clock frequency BYU ECEn 320 Four-Phase Handshake Protocol Transfer of relatively low-bandwidth signals can be done using a four-phase handshaking protocol 1. Sender de-asserts data and control signal Receiver de-asserts ack signaling that it is ready for more data 1 Req (data valid) 3 2 4 Ack (data ack) valid data BYU ECEn 320 76 . Receiver signals that the data has been received (ack). Sender drives data on to bus and provides a signal indicating that data is available (req). 2.
the system immediately readies itself for another transaction. • The deassertion acknowledgment occurs without the need for a second round trip to restore all control signals to their proper logical states.Four-Phase Level-Handshake Protocol Synchronizer REQ REQsync Sender FSM Synchronizer ACKsync Q D CLK ACK Receiver FSM EN Data Bus (not synchronized) EN BYU ECEn 320 The Two-Phase Handshake “Toggle” Protocol • By using the change in the handshake’s signal level and not the level itself to communicate through the synchronizer. BYU ECEn 320 77 . as a four-phase round trip requires.
The Two-Phase Handshake “Toggle” Protocol SDATA ALOAD BLOAD ACK BDATA BYU ECEn 320 Toggle-Handshake Protocol Circuit BLOAD ALOAD ACK BYU ECEn 320 78 .
Using FIFOs to Transfer Data • Most high-speed data transfers occur in bursts rather than evenly spaced data streams – Large blocks of data arriving at random times – Often modeled with a Poisson distribution e − λ λx p ( x) = – Example: Disk & Video I/O x! • It is difficult to transfer such data using the simple circuit described earlier – Can’t keep up during burst data mode – Is sitting idle when no data transfer is occurring • First-in First out (FIFO) memories are often used to transfer such data BYU ECEn 320 First-In First-Out (FIFO) • FIFO is implemented with memory – Depth of FIFO is limited – Analysis must be performed to ensure overflow does not occur • Two ports for FIFO memory – Write port: Port for writing data into the FIFO (via a write pointer) – Read port: Port for reading data from the FIFO (via a read pointer) • Control Signals: – FIFO empty: indicates to the read port that there is no data available in the FIFO – FIFO full: indicates to the write port that the FIFO is full • Synchronous FIFO: Read and Write port accessed with a common clock • Asynchronous FIFO: Different clocks can be used for the read and write ports BYU ECEn 320 79 .
they can introduce a race condition through the synchronizer.FIFO-Handshake Protocols • Due to bursty data and the difference in clock speeds. BYU ECEn 320 Synchronizing FIFO • Valid data on in (out) when ivalid (ovalid) is true • FIFO (output client) able to accept data on in (out) when iready (oready) is true • Data exchanged on input (output) when ivalid & iready (ovalid & oready) • iready = not full • oready = not empty clkin domain BYU ECEn 320 clkout domain 80 . you must implement the input and output pointers as Gray Code counters to ensure that only one bit changes at a time. • Because the pointers contain multiple bits. the FIFO empty and full conditions perform the handshaking. To avoid this problem. • In this situation. • Asynchronous FIFOs must pass the read and write pointers between clock domains (write clock/read clock). a latency-absorbing FIFO often acts as a data buffer between different clock domains.
– Gray code these two counters BYU ECEn 320 BlockRAM FIFO FIFO Full Synchronization and Control Logic Counter INC BRAM ADDR WE ADDR FIFO Data Present Write Counter INC Read DataIn Write Clock DataOut DATA IN DATA OUT Read Clock BYU ECEn 320 81 .FIFO Full and Empty • Head points to next location from which to read • Tail points to next location to which to write • FIFO empty when head = tail and no data in FIFO • FIFO full when head = tail and all locations full • Hard to tell the two apart • Simple solution – leave one location empty – FIFO full when (tail+1) = head (gray coded increment) • Need to compare head (clkout domain) with tail (clkin domain) to compute full and empty – Requires synchronizers to get head in clkin domain and tail in clkout domain.
what is the mean time to failure of this circuit? Is it acceptable if you are planning to sell 100.and destination clock frequencies. For the same parameters as above. for example) and manually analyze the behavior of the implementation on a timing diagram for at least two consecutive transactions. BYU ECEn 320 Homework Unit 4 1. Tsetup= 3 ns. ASYNCIN . What are the setup-time and holdtime margins for the second flipflop in the circuit below if Tcq is 8 ns (min) and 10 ns (max). as well as the strobe signal. not the data lines. • Simulation cannot hope to duplicate the infinite number of clock and signal-edge relationships that are possible in a clock-domaincrossing design.Common Pitfalls • In level-handshakes protocols. clock-to-q prop time is 1 ns. • A designer must neither assume nor require any fixed relationship between the source. • When inspecting a clock-domain-crossing design.5 ns. – Then. if asyncin changes 106 times per second. Only put synchronizers on the control signals.. setup time is 0. Assume the period of the clock is tclk. assuming the opposite clock-frequency relationship. how many flip-flops are needed below to create a synchronizer with a MTBF of a million years. T0=10-10sec and τ=. Tsetup is 3 ns and Thold is 5 ns. • Clocking of the data. repeat the analysis.051 ns. given: Tcq (clock-to-q prop time) = 8 ns (min) and 10 ns (max). For the circuit below. 4. What is the maximum frequency that a synchronous system can operate. Clk Network CLOCK BYU ECEn 320 82 . through the synchronizers causes a race condition. you must initiate second round trip to restore the logical level of the handshake signals to their original state—doubling the protocol latency. Tskew is 1 ns max. in preparation for the next handshake. – First.000 of them? 2. Thold = 5 ns.. assume one extreme clock-frequency relationship (10 to one. the clock frequency is 333 MHz. you must fully analyze two cases. 3. Tprop (total combinational logic prop time) = 12 ns (min) and 21 ns (max) Tskew= 1 ns max.
Hint: Worse case scenario is when Tclk2 > Tclk1 . Show how you could alter the circuit to increase the MTBF.Homework Unit 4 5. and it takes another clk2 cycle to get meta to go high. Consider the pulse synchronizer circuit below. Tclk2. Tsetup. Trapped pulse TRAP comes barely too late to meet the setup and hold times of the middle flip-flop. BYU ECEn 320 83 . Suppose the MTBF of the synchronizer was not enough. what is the maximum rate (or minimum period) of input pulses that can be handled by this circuit. META eventually resolves low. a. in terms of Tclk1. Show how you could alter the circuit to produce a two clk2-cycle pulse in response to a single cycle pulse at the input. Thold. which goes meta-stable. and clockto-q time Tcq. TRAP IN CLK1 CLK2 EN RST RST META OUT c. b. Considering the worse case scenario.
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