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5 4 3 2 1

DESIGN CURRENT 0.1A +3VL


B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7 DESIGN CURRENT 5A +5VALW
PCH_PWR_EN#

P-CHANNEL
+5VALW_PCH
SUSP# AO-3413
D D
DESIGN CURRENT 2A +1.8VS
SY8032ABC

SUSP#

DESIGN CURRENT 6A +5VS


TPS22966DPUR

RT8243AZQW KB_LED
DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
AO-3413

+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191-330T1U

ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW

DESIGN CURRENT 330mA +3V_LAN


C WOWL_EN# C

DESIGN CURRENT 3A +3V_WLAN


P-CHANNEL
AO-3413

PCH_PWR_EN#

P-CHANNEL
+3VALW_PCH
AO-3413
SUSP#

DESIGN CURRENT 6A +3VS


TPS22966DPUR
LCD_ENVDD

DESIGN CURRENT 1.5A +LCD_VDD


APL3512ABI

DGPU_PWR_EN
DESIGN CURRENT 0.1A +3VS_DGPU
P-CHANNEL
AO-3413

VR_ON
DESIGN CURRENT 65A +CPU_CORE
NCP81012BMNR DESIGN CURRENT 40A +GFX_CORE
B B

SUSP#

Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A +1.05VS_VCCP


SY8208QKC
VGA_PWROK#
DESIGN CURRENT 3A +1.05VS_DGPU
N-CHANNEL
AO3416

VCCP_PWRGOOD
DESIGN CURRENT 6A +VCCSA
G978F11U
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=18A DESIGN CURRENT 2A +1.5V
RT8207M 0.75VR_ON
DESIGN CURRENT 1.5A +0.75VS
SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU


FDS6676AS
DESIGN CURRENT 2A +1.5VS
1.5_PWR_EN#
A A

N-CHANNEL DESIGN CURRENT 11A +VRAM_1.5VS


FDS6676AS
DGPU_PWR_EN
Ipeak=59A, Imax=45.7A, Iocp min=70A DESIGN CURRENT 30A +VGA_CORE
NCP81172MNTWG
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 3 of 56
5 4 3 2 1
A B C D E

( O MEANS ON X MEANS OFF )


Voltage Rails BTO Option Table
+5VS Function SKU PCH GPU VRAM EC ISPD
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW description Optimus Panther Point N14M-GL N14P-GV2 Dual Rank EC HDMI Logo
+1.8VS
power +1.5VS explain Optimus HM76 HM70 N14M-GL N14P-GV2 Dual Rank KB9012 NPCE885N HDMI Logo
1 plane +1.05VS 1

HM76R1@ HM70R1@ N14MGL@ N14PGV2@


+0.75VS
BTO OPT@ DRANK@ 9012@ 885@ HDMI45@
+CPU_CORE N14MGLR1@ N14PGV2R1@
HM76R3@ HM70R3@
+VGA_CORE N14MGLR3@ N14PGV2R3@
+GFX_CORE
+VTT
State Function LVDS-eDP Camera & Mic USB S&C CRT Touch Screen
+VRAM_1.5VS
+3VS_DGPU description LVDS-eDP Camera & Mic 14640 14641 CRT Touch Screen
+1.05VS_DGPU
explain LVDS eDP Camera & Mic 14640 14641 w/ CRT w/o CRT Touch Screen

BTO LVDS@ IEDP@ CAM_EMI@ 14640@ 14641@ CRT@ CRT_EMI@ NOCRT@ TOUCH_EMI@

S0
O O O O O O
Function WOWL G-SENSOR ZPODD GCLK VRAM SKU for GV2
S1
O O O O O O description WOWL G-SENSOR ZPODD GCLK non-GCLK Single Rank Dual Rank

S3 explain w/ w/o G-SENSOR w/ w/o GCLK non-GCLK Single Rank Dual Rank
2 O O O O O X 2

BTO WOWL@ NOWOWL@ GSENSOR@ ZPODD@ NONZP@ GCLK@ NOGCLK@ GVSR@ GVDR@
S5 S4/AC
O O O O X X
S5 S4/ Battery only Function Sleep & Music KB Light EMI/ESD part
O O O X X X
description Sleep & Music KB Light EMI/ESD part
S5 S4/AC & Battery
don't exist
O X X X X X
explain w/ S&M w/o S&M KB Light EMI/ESD part

BTO 269@ 259@ KBL@ EMI@ ESD@

PCH SM Bus Address

Power Device HEX Address


+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
3
+3VS WLAN/WIMAX 3

+3VS Touch Pad 2C H 0010 1100 b

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH

+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL Smart Charger 12 H 0001 0010 b +3VS NVIDIA GPU 9E H 1001 1010 b
S4 (Suspend to Disk) LOW LOW HIGH
+3VL USB S&C 14640 35 H 0011 0101 b +3VS G-Sensor 40 H 0100 0000 b
S5 (Soft OFF) LOW LOW LOW

G3 LOW LOW LOW


4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 4 of 56
A B C D E
5 4 3 2 1

Stuff R41 and R42 if do not support eDP


JCPUB

100 MHz +1.05VS_VCCP

@ A28
BCLK CLK_CPU_DMI <26>
1000P_0402_50V7K 2 1 CC62 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_EDP# RC1571 LVDS@ 2 1K_0402_5%

MISC

CLOCKS
<30> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <26>
120 MHz CLK_CPU_EDP RC1581 LVDS@ 2 1K_0402_5%
T1 PAD TP_SKTOCC# AN34
ESD@ SKTOCC# A16 CLK_CPU_EDP
1 2 CC63 DPLL_REF_CLK A15 CLK_CPU_EDP <26>
180P_0402_50V8J H_PWRGOOD CLK_CPU_EDP#
DPLL_REF_CLK# CLK_CPU_EDP# <26>
D D

by ESD requestion and place near CPU T2 PAD H_CATERR# AL33 @ESD@
CATERR# H_DRAMRST# 1 2
CC34 180P_0402_50V8J

THERMAL
H_PECI AN33 R8 H_DRAMRST#
+1.05VS_VCCP <41> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
by ESD requestion and place near CPU

DDR3
MISC
RC44 2 1 62_0402_5% H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 RC56 2 1 140_0402_1%
<41> H_PROCHOT# PROCHOT# SM_RCOMP[0]
RC159 56_0402_5% A5 SM_RCOMP_1 RC59 2 1 25.5_0402_1%
SM_RCOMP[1] A4 SM_RCOMP_2 RC61 2 1 200_0402_1%
SM_RCOMP[2]
DDR3 Compensation Signals
RC45 2 1 10K_0402_5% H_PWRGOOD AN32 Layout Note:Place these
<30> H_THERMTRIP# THERMTRIP#
resistors near Processor

AP29
PRDY# AP27
PREQ#
AR26 XDP_TCK T13 PAD
TCK AR27 XDP_TMS T15 PAD

PWR MANAGEMENT
TMS

JTAG & BPM


@ H_PM_SYNC AM34 AP30 XDP_TRST# 1 2
<27> H_PM_SYNC PM_SYNC TRST#
1000P_0402_50V7K 2 1 CC70 H_PECI RC55 51_0402_5%
AR28 XDP_TDI
@ TDI AP26 XDP_TDO T7 PAD
1000P_0402_50V7K 2 1 CC67 H_PM_SYNC H_PWRGOOD 1 Rshort@ 2 H_PWRGOOD_R AP33 TDO T10 PAD
<30> H_PWRGOOD UNCOREPWRGOOD
RC183 0_0402_5%
@
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST# AL35
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8 DBR#
C SM_DRAMPWROK Close to CPU side C
RC170 130_0402_5%
AT28
BPM#[0] AR29
Please place near JCPU BPM#[1] AR30
BUF_CPU_RST# AR33 BPM#[2] AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
BPM#[7]
+3VALW_PCH

2 1 DRAMPWROK +3VALW_PCH
RC11 200_0402_5% +1.5V_CPU TYCO_2013620-2_IVY BRIDGE

Conn@
1

0206: Delete 0.1uF

RC14
UC3 200_0402_5%
5

10K_0402_5% 74AHC1G09GW_TSSOP5
2

2 RC13 1 1
P

+3VS B 4 PM_SYS_PWRGD_BUF
2 O
<27> DRAMPWROK A
G
3

B B

FAN Control Circuit


+5VS
Buffered Reset to CPU
+3VS
1A
1 Rshort@ 2 +FAN1

1
+3VS R1 0_0603_5%
JFAN
R2
10K_0402_5% 6
5 G6
0206: Delete 0.1uF 4 G5

2
3 4
+1.05VS_VCCP <41> FANPWM 3
2
PLT_RST# <29,35,36,41> <41> FAN_SPEED1 2
+FAN1 1
1
1

UC2 ACES_50273-0040N-001
1 RC38 Conn@
OE# 5 75_0402_5%
VCC

1
2 RC35 1
2

IN 43_0402_1%
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# D1 C5
3 OUT 10U_0603_6.3V6M
GND BAS16_SOT23-3 2

2
A 74AHC1G125GW_SOT353-5 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_JTAG/XDP/FAN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 5 of 56
5 4 3 2 1
5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be


+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical

1
impedance = 43 m ohm (4 mils)
RC1
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)

2
J22 PEG_COMP
PEG_ICOMPI J21
D B27 PEG_ICOMPO H22 D
<27> DMI_PTX_CRX_N0 B25 DMI_RX#[0] PEG_RCOMPO
<27> DMI_PTX_CRX_N1 A25 DMI_RX#[1]
<27> DMI_PTX_CRX_N2 B24 DMI_RX#[2] K33 PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N[0..3] <13>
<27> DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0] M35 PCIE_GTX_C_CRX_N1
B28 PEG_RX#[1] L34 PCIE_GTX_C_CRX_N2
<27> DMI_PTX_CRX_P0 B26 DMI_RX[0] PEG_RX#[2] J35 PCIE_GTX_C_CRX_N3
<27> DMI_PTX_CRX_P1 A24 DMI_RX[1] PEG_RX#[3] J32

DMI
<27> DMI_PTX_CRX_P2 B23 DMI_RX[2] PEG_RX#[4] H34
<27> DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5] H31
G21 PEG_RX#[6] G33
<27> DMI_CTX_PRX_N0 E22 DMI_TX#[0] PEG_RX#[7] G30
<27> DMI_CTX_PRX_N1 F21 DMI_TX#[1] PEG_RX#[8] F35
<27> DMI_CTX_PRX_N2 D21 DMI_TX#[2] PEG_RX#[9] E34
<27> DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] E32
G22 PEG_RX#[11] D33
<27> DMI_CTX_PRX_P0 D22 DMI_TX[0] PEG_RX#[12] D31
<27> DMI_CTX_PRX_P1 F20 DMI_TX[1] PEG_RX#[13] B33
<27> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]

PCI EXPRESS* - GRAPHICS


C21 C32
<27> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PCIE_GTX_C_CRX_P[0..3] <13>
PCIE_GTX_C_CRX_P0
PEG_RX[0] L35 PCIE_GTX_C_CRX_P1
PEG_RX[1] K34 PCIE_GTX_C_CRX_P2
A21 PEG_RX[2] H35 PCIE_GTX_C_CRX_P3
<27> FDI_CTX_PRX_N0 H19 FDI0_TX#[0] PEG_RX[3] H32
<27> FDI_CTX_PRX_N1 E19 FDI0_TX#[1] PEG_RX[4] G34
<27> FDI_CTX_PRX_N2 F18 FDI0_TX#[2] PEG_RX[5] G31
<27> FDI_CTX_PRX_N3 B21 FDI0_TX#[3] PEG_RX[6] F33

Intel(R) FDI
<27> FDI_CTX_PRX_N4 C20 FDI1_TX#[0] PEG_RX[7] F30
<27> FDI_CTX_PRX_N5 D18 FDI1_TX#[1] PEG_RX[8] E35
<27> FDI_CTX_PRX_N6 E17 FDI1_TX#[2] PEG_RX[9] E33
<27> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] F32
C PEG_RX[11] D34 C
A22 PEG_RX[12] E31
<27> FDI_CTX_PRX_P0 G19 FDI0_TX[0] PEG_RX[13] C33
<27> FDI_CTX_PRX_P1 E20 FDI0_TX[1] PEG_RX[14] B32
<27> FDI_CTX_PRX_P2 G18 FDI0_TX[2] PEG_RX[15]
<27> FDI_CTX_PRX_P3 B20 FDI0_TX[3] M29 PCIE_CTX_GRX_N0 1 2 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N[0..3] <13>
CC8 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P4 C19 FDI1_TX[0] PEG_TX#[0] M32 PCIE_CTX_GRX_N1 1 2 PCIE_CTX_C_GRX_N1
CC11 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P5 D19 FDI1_TX[1] PEG_TX#[1] M31 PCIE_CTX_GRX_N2 1 2 PCIE_CTX_C_GRX_N2
CC16 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P6 F17 FDI1_TX[2] PEG_TX#[2] L32 PCIE_CTX_GRX_N3 1 2 PCIE_CTX_C_GRX_N3
CC20 0.22U_0402_16V7K
<27> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] L29
J18 PEG_TX#[4] K31
<27> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
J17 K28
<27> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] J30
H20 PEG_TX#[7] J28
<27> FDI_INT FDI_INT PEG_TX#[8] H29
J19 PEG_TX#[9] G27
<27> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
H17 E29
<27> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] F27
PEG_TX#[12] D28
PEG_TX#[13] F26
PEG_TX#[14] E25
RC2 1 2 24.9_0402_1% EDP_COMP A18 PEG_TX#[15]
+1.05VS_VCCP eDP_COMPIO PCIE_CTX_C_GRX_P[0..3] <13>
A17 M28 PCIE_CTX_GRX_P0 CC10 1 2 0.22U_0402_16V7K PCIE_CTX_C_GRX_P0
H_EDP_HPD# B16 eDP_ICOMPO PEG_TX[0] M33 PCIE_CTX_GRX_P1 CC5 1 2 0.22U_0402_16V7K PCIE_CTX_C_GRX_P1
eDP_HPD# PEG_TX[1] M30 PCIE_CTX_GRX_P2 1 2 PCIE_CTX_C_GRX_P2
eDP_COMP signals should be PEG_TX[2]
CC6 0.22U_0402_16V7K
L31 PCIE_CTX_GRX_P3 CC7 1 2 0.22U_0402_16V7K PCIE_CTX_C_GRX_P3
shorted near balls and C15 PEG_TX[3] L28
<22> H_EDP_AUXP eDP_AUX PEG_TX[4]
routed with typical <22> H_EDP_AUXN
D15
eDP_AUX# PEG_TX[5]
K30
K27
impedance <25m ohm
eDP

PEG_TX[6] J29
C17 PEG_TX[7] J27
<22> H_EDP_TXP0 F16 eDP_TX[0] PEG_TX[8] H28
B <22> H_EDP_TXP1 C16 eDP_TX[1] PEG_TX[9] G28 B
G15 eDP_TX[2] PEG_TX[10] E28
eDP_TX[3] PEG_TX[11] F28
C18 PEG_TX[12] D27
<22> H_EDP_TXN0 E16 eDP_TX#[0] PEG_TX[13] E26
<22> H_EDP_TXN1 D16 eDP_TX#[1] PEG_TX[14] D25
F15 eDP_TX#[2] PEG_TX[15] PEG DG suggest AC cap
eDP_TX#[3]

+1.05VS_VCCP
TYCO_2013620-2_IVY BRIDGE Gen1/Gen2 75 nF~265 nF
Conn@ IVY Bridge
Gen3 180 nF~265 nF
2

RC9 SANDY Bridge Gen1/Gen2 180 nF~265 nF


1K_0402_5%

NV N14x Gen1/2/3 Suggest 220 nF


1

H_EDP_HPD#
1
OUT

2
<22> CPU_EDP_HPD IN
GND

QC1
DTC124EKAT146_SC59-3
3

IEDP@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_DMI/PEG/FDI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1

JCPUC JCPUD
<11> DDR_A_D[0..63]
<12> DDR_B_D[0..63]

AB6 AE2
SA_CLK[0] AA6 DDRA_CLK0 <11> SB_CLK[0] AD2 DDRB_CLK0 <12>
C5 SA_CLK#[0] V9 DDRA_CLK0# <11> C9 SB_CLK#[0] R9 DDRB_CLK0# <12>
DDR_A_D0 DDR_B_D0
DDR_A_D1 D5 SA_DQ[0] SA_CKE[0] DDRA_CKE0 <11> DDR_B_D1 A7 SB_DQ[0] SB_CKE[0] DDRB_CKE0 <12>
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D C6 SA_DQ[4] SA_CLK[1] AB5 DDRA_CLK1 <11> A8 SB_DQ[4] SB_CLK[1] AD1 DDRB_CLK1 <12> D
DDR_A_D5 DDR_B_D5
DDR_A_D6 C2 SA_DQ[5] SA_CLK#[1] V10 DDRA_CLK1# <11> DDR_B_D6 D9 SB_DQ[5] SB_CLK#[1] R10 DDRB_CLK1# <12>
DDR_A_D7 C3 SA_DQ[6] SA_CKE[1] DDRA_CKE1 <11> DDR_B_D7 D8 SB_DQ[6] SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D8 F10 SA_DQ[7] DDR_B_D8 G4 SB_DQ[7]
DDR_A_D9 F8 SA_DQ[8] DDR_B_D9 F4 SB_DQ[8]
DDR_A_D10 G10 SA_DQ[9] AB4 DDR_B_D10 F1 SB_DQ[9] AB2
DDR_A_D11 G9 SA_DQ[10] RSVD_TP[1] AA4 DDR_B_D11 G1 SB_DQ[10] RSVD_TP[11] AA2
DDR_A_D12 F9 SA_DQ[11] RSVD_TP[2] W9 DDR_B_D12 G5 SB_DQ[11] RSVD_TP[12] T9
DDR_A_D13 F7 SA_DQ[12] RSVD_TP[3] DDR_B_D13 F5 SB_DQ[12] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[13] DDR_B_D14 F2 SB_DQ[13]
DDR_A_D15 G7 SA_DQ[14] DDR_B_D15 G2 SB_DQ[14]
DDR_A_D16 K4 SA_DQ[15] AB3 DDR_B_D16 J7 SB_DQ[15] AA1
DDR_A_D17 K5 SA_DQ[16] RSVD_TP[4] AA3 DDR_B_D17 J8 SB_DQ[16] RSVD_TP[14] AB1
DDR_A_D18 K1 SA_DQ[17] RSVD_TP[5] W10 DDR_B_D18 K10 SB_DQ[17] RSVD_TP[15] T10
DDR_A_D19 J1 SA_DQ[18] RSVD_TP[6] DDR_B_D19 K9 SB_DQ[18] RSVD_TP[16]
DDR_A_D20 J5 SA_DQ[19] DDR_B_D20 J9 SB_DQ[19]
DDR_A_D21 J4 SA_DQ[20] DDR_B_D21 J10 SB_DQ[20]
DDR_A_D22 J2 SA_DQ[21] AK3 DDR_B_D22 K8 SB_DQ[21] AD3
K2 SA_DQ[22] SA_CS#[0] AL3 DDRA_SCS0# <11> K7 SB_DQ[22] SB_CS#[0] AE3 DDRB_SCS0# <12>
DDR_A_D23 DDR_B_D23
M8 SA_DQ[23] SA_CS#[1] AG1 DDRA_SCS1# <11> M5 SB_DQ[23] SB_CS#[1] AD6 DDRB_SCS1# <12>
DDR_A_D24 DDR_B_D24
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] AH1 DDR_B_D25 N4 SB_DQ[24] RSVD_TP[17] AE6
DDR_A_D26 N8 SA_DQ[25] RSVD_TP[8] DDR_B_D26 N2 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N1 SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 M4 SB_DQ[27]
DDR_A_D29 M9 SA_DQ[28] AH3 DDR_B_D29 N5 SB_DQ[28] AE4
N9 SA_DQ[29] SA_ODT[0] AG3 DDRA_ODT0 <11> M2 SB_DQ[29] SB_ODT[0] AD4 DDRB_ODT0 <12>
DDR_A_D30 DDR_B_D30
DDRA_ODT1 <11> DDRB_ODT1 <12>

DDR SYSTEM MEMORY B


DDR_A_D31 M7 SA_DQ[30] SA_ODT[1] AG2 DDR_B_D31 M1 SB_DQ[30] SB_ODT[1] AD5

DDR SYSTEM MEMORY A


DDR_A_D32 AG6 SA_DQ[31] RSVD_TP[9] AH2 DDR_B_D32 AM5 SB_DQ[31] RSVD_TP[19] AE5
DDR_A_D33 AG5 SA_DQ[32] RSVD_TP[10] DDR_B_D33 AM6 SB_DQ[32] RSVD_TP[20]
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#0 DDR_A_DQS#[0..7] <11> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#0 DDR_B_DQS#[0..7] <12> C
DDR_A_D38 AJ5 SA_DQ[37] SA_DQS#[0] G6 DDR_A_DQS#1 DDR_B_D38 AN1 SB_DQ[37] SB_DQS#[0] F3 DDR_B_DQS#1
DDR_A_D39 AJ6 SA_DQ[38] SA_DQS#[1] J3 DDR_A_DQS#2 DDR_B_D39 AP2 SB_DQ[38] SB_DQS#[1] K6 DDR_B_DQS#2
DDR_A_D40 AJ8 SA_DQ[39] SA_DQS#[2] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[39] SB_DQS#[2] N3 DDR_B_DQS#3
DDR_A_D41 AK8 SA_DQ[40] SA_DQS#[3] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[40] SB_DQS#[3] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 DDR_A_DQS#5 DDR_B_D42 AT5 SB_DQ[41] SB_DQS#[4] AP9 DDR_B_DQS#5
DDR_A_D43 AK9 SA_DQ[42] SA_DQS#[5] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[42] SB_DQS#[5] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 SA_DQ[43] SA_DQS#[6] AM15 DDR_A_DQS#7 DDR_B_D44 AP6 SB_DQ[43] SB_DQS#[6] AP15 DDR_B_DQS#7
DDR_A_D45 AH9 SA_DQ[44] SA_DQS#[7] DDR_B_D45 AN8 SB_DQ[44] SB_DQS#[7]
DDR_A_D46 AL9 SA_DQ[45] DDR_B_D46 AR6 SB_DQ[45]
DDR_A_D47 AL8 SA_DQ[46] DDR_B_D47 AR5 SB_DQ[46]
DDR_A_D48 AP11 SA_DQ[47] DDR_B_D48 AR9 SB_DQ[47]
AN11 SA_DQ[48] D4 DDR_A_DQS[0..7] <11> AJ11 SB_DQ[48] C7 DDR_B_DQS[0..7] <12>
DDR_A_D49 DDR_A_DQS0 DDR_B_D49 DDR_B_DQS0
DDR_A_D50 AL12 SA_DQ[49] SA_DQS[0] F6 DDR_A_DQS1 DDR_B_D50 AT8 SB_DQ[49] SB_DQS[0] G3 DDR_B_DQS1
DDR_A_D51 AM12 SA_DQ[50] SA_DQS[1] K3 DDR_A_DQS2 DDR_B_D51 AT9 SB_DQ[50] SB_DQS[1] J6 DDR_B_DQS2
DDR_A_D52 AM11 SA_DQ[51] SA_DQS[2] N6 DDR_A_DQS3 DDR_B_D52 AH11 SB_DQ[51] SB_DQS[2] M3 DDR_B_DQS3
DDR_A_D53 AL11 SA_DQ[52] SA_DQS[3] AL5 DDR_A_DQS4 DDR_B_D53 AR8 SB_DQ[52] SB_DQS[3] AN6 DDR_B_DQS4
DDR_A_D54 AP12 SA_DQ[53] SA_DQS[4] AM9 DDR_A_DQS5 DDR_B_D54 AJ12 SB_DQ[53] SB_DQS[4] AP8 DDR_B_DQS5
DDR_A_D55 AN12 SA_DQ[54] SA_DQS[5] AR11 DDR_A_DQS6 DDR_B_D55 AH12 SB_DQ[54] SB_DQS[5] AK11 DDR_B_DQS6
DDR_A_D56 AJ14 SA_DQ[55] SA_DQS[6] AM14 DDR_A_DQS7 DDR_B_D56 AT11 SB_DQ[55] SB_DQS[6] AP14 DDR_B_DQS7
DDR_A_D57 AH14 SA_DQ[56] SA_DQS[7] DDR_B_D57 AN14 SB_DQ[56] SB_DQS[7]
DDR_A_D58 AL15 SA_DQ[57] DDR_B_D58 AR14 SB_DQ[57]
DDR_A_D59 AK15 SA_DQ[58] DDR_B_D59 AT14 SB_DQ[58]
AL14 SA_DQ[59] DDR_A_MA[0..15] <11> AT12 SB_DQ[59]
DDR_A_D60 DDR_B_D60
DDR_A_D61 AK14 SA_DQ[60] AD10 DDR_A_MA0 DDR_B_D61 AN15 SB_DQ[60] AA8 DDR_B_MA0 DDR_B_MA[0..15] <12>
DDR_A_D62 AJ15 SA_DQ[61] SA_MA[0] W1 DDR_A_MA1 DDR_B_D62 AR15 SB_DQ[61] SB_MA[0] T7 DDR_B_MA1
DDR_A_D63 AH15 SA_DQ[62] SA_MA[1] W2 DDR_A_MA2 DDR_B_D63 AT15 SB_DQ[62] SB_MA[1] R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] W7 DDR_A_MA3 SB_DQ[63] SB_MA[2] T6 DDR_B_MA3
SA_MA[3] V3 DDR_A_MA4 SB_MA[3] T2 DDR_B_MA4
SA_MA[4] V2 DDR_A_MA5 SB_MA[4] T4 DDR_B_MA5
SA_MA[5] W3 DDR_A_MA6 SB_MA[5] T3 DDR_B_MA6
AE10 SA_MA[6] W6 DDR_A_MA7 AA9 SB_MA[6] R2 DDR_B_MA7
B <11> DDR_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 <12> DDR_B_BS0 AA7 SB_BS[0] SB_MA[7] T5 B
DDR_A_MA8 DDR_B_MA8
<11> DDR_A_BS1 V6 SA_BS[1] SA_MA[8] W5 <12> DDR_B_BS1 R6 SB_BS[1] SB_MA[8] R3
DDR_A_MA9 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] AD8 DDR_A_MA10 <12> DDR_B_BS2 SB_BS[2] SB_MA[9] AB7 DDR_B_MA10
SA_MA[10] V4 DDR_A_MA11 SB_MA[10] R1 DDR_B_MA11
SA_MA[11] W4 DDR_A_MA12 SB_MA[11] T1 DDR_B_MA12
AE8 SA_MA[12] AF8 DDR_A_MA13 AA10 SB_MA[12] AB10 DDR_B_MA13
<11> DDR_A_CAS# AD9 SA_CAS# SA_MA[13] V5 <12> DDR_B_CAS# AB8 SB_CAS# SB_MA[13] R5
DDR_A_MA14 DDR_B_MA14
<11> DDR_A_RAS# AF9 SA_RAS# SA_MA[14] V7 DDR_A_MA15 <12> DDR_B_RAS# AB9 SB_RAS# SB_MA[14] R4 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE


Conn@ Conn@

+1.5V
1

RC76
1K_0402_5%

RC77
2

QC3 1K_0402_5%
3 1
S

DDR3_DRAMRST#_R 1 2
<5> H_DRAMRST# SM_DRAMRST# <11,12>
2

BSS138_NL_SOT23-3
RC78
G
2

4.99K_0402_1%
A A
1

1 Rshort@ 2 DRAMRST_CNTRL
<26,9> DRAMRST_CNTRL_PCH
RC73 0_0402_5%

1
CC37 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K 2012/12/07 2013/12/07 Title
Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_DDR3
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

+CPU_CORE

JCPUF POWER +1.05VS_VCCP +1.05VS_VCCP

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
ESD@ CC17

ESD@ CC18

ESD@ CC19
1 1 1
53A
AG35 8.5A
D AG34 VCC1 AH13 2 2 2 D
AG33 VCC2 VCCIO1 AH10
AG32 VCC3 VCCIO2 AG10
AG31 VCC4 VCCIO3 AC10
AG30 VCC5 VCCIO4 Y10
AG29 VCC6 VCCIO5 U10
AG28 VCC7 VCCIO6 P10
AG27 VCC8 VCCIO7 L10
AG26 VCC9 VCCIO8 J14
AF35 VCC10 VCCIO9 J13
VCC11 VCCIO10 by ESD requestion and place near CPU
AF34 J12
AF33 VCC12 VCCIO11 J11
AF32 VCC13 VCCIO12 H14
AF31 VCC14 VCCIO13 H12
AF30 VCC15 VCCIO14 H11
AF29 VCC16 VCCIO15 G14
AF28 VCC17 VCCIO16 G13
AF27 VCC18 VCCIO17 G12
PEG AND DDR
AF26 VCC19 VCCIO18 F14
AD35 VCC20 VCCIO19 F13
AD34 VCC21 VCCIO20 F12
AD33 VCC22 VCCIO21 F11
AD32 VCC23 VCCIO22 E14
AD31 VCC24 VCCIO23 E12
AD30 VCC25 VCCIO24
AD29 VCC26 E11
AD28 VCC27 VCCIO25 D14
AD27 VCC28 VCCIO26 D13
AD26 VCC29 VCCIO27 D12
AC35 VCC30 VCCIO28 D11
AC34 VCC31 VCCIO29 C14
AC33 VCC32 VCCIO30 C13
C AC32 VCC33 VCCIO31 C12 C
AC31 VCC34 VCCIO32 C11
AC30 VCC35 VCCIO33 B14
AC29 VCC36 VCCIO34 B12
AC28 VCC37 VCCIO35 A14
AC27 VCC38 VCCIO36 A13
AC26 VCC39 VCCIO37 A12
AA35 VCC40 VCCIO38 A11
AA34 VCC41 VCCIO39
AA33 VCC42 J23
AA32 VCC43 VCCIO40
AA31 VCC44
AA30 VCC45
AA29 VCC46
AA28 VCC47
AA27 VCC48
AA26 VCC49
Y35 VCC50
CORE SUPPLY

Y34 VCC51
Y33 VCC52 +1.05VS_VCCP +1.05VS_VCCP
Y32 VCC53
Y31 VCC54
Y30 VCC55
VCC56
1

Y29
Y28 VCC57 RC91 RC89
Y27 VCC58 130_0402_5% 75_0402_5%
Y26 VCC59
V35 VCC60
2

V34 VCC61 AJ29 H_CPU_SVIDALRT# 1 2


SVID

V33 VCC62 VIDALERT# AJ30 VR_SVID_ALRT# <51>


RC90 43_0402_1%
V32 VCC63 VIDSCLK AJ28 VR_SVID_CLK <51>
V31 VCC64 VIDSOUT VR_SVID_DAT <51>
B V30 VCC65 B
VCC66 Pull high resistor on VR side
V29
V28 VCC67
V27 VCC68
V26 VCC69
U35 VCC70
U34 VCC71
U33 VCC72
U32 VCC73
U31 VCC74
U30 VCC75
U29 VCC76
U28 VCC77
U27 VCC78 +CPU_CORE
U26 VCC79
R35 VCC80
R34 VCC81
VCC82
2

R33
R32 VCC83
VCC84
RC93 Close to CPU
R31 100_0402_1%
R30 VCC85
R29 VCC86
1

R28 VCC87
SENSE LINES

R27 VCC88 AJ35


R26 VCC89 VCC_SENSE AJ34 VCCSENSE <51>
P35 VCC90 VSS_SENSE VSSSENSE <51>
P34 VCC91
VCC92
1

P33
P32 VCC93 B10 RC97
P31 VCC94 VCCIO_SENSE A10 VCCIO_SENSE <49>
100_0402_1%
P30 VCC95 VSS_SENSE_VCCIO
VCC96
1

P29
2

A P28 VCC97 RC96 RC98 A


P27 VCC98 10_0402_1% 10_0402_1%
P26 VCC99
VCC100
2

+1.05VS_VCCP

Close to CPU Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

Conn@
TYCO_2013620-2_IVY BRIDGE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_POWER-1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

+GFX_CORE Intel DDR Vref M3 Place near SO-DIMM side

1
+GFX_CORE

JCPUG
POWER RC105
10_0402_1%
Close to CPU
BSS138_NL_SOT23-3
QC7
33A

2
3 1

D
+VREF_DQA_M3 +VREF_DQA
AT24 AK35

SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 VCC_AXG_SENSE <51>
D AT21 VAXG2 VSSAXG_SENSE VSS_AXG_SENSE <51> D

G
2
AT20 VAXG3 1 RC106 2
AT18 VAXG4 10_0402_1%
AT17 VAXG5
AR24 VAXG6 DRAMRST_CNTRL_PCH <26,7>
AR23 VAXG7 +V_SM_VREF should +1.5V_CPU
VAXG8 have 20 mil trace width

2
G
AR21 RC120
AR20 VAXG9 1 1K_0402_0.5%
2
AR18 VAXG10 AL1 +V_SM_VREF 3 1
VAXG11 SM_VREF +VREF_DQB_M3 +VREF_DQB
AR17 1 1K_0402_0.5%
2

D
AP24 VAXG12 RC109 QC8
1

VREF
AP23 VAXG13 BSS138_NL_SOT23-3
AP21 VAXG14 CC65
AP20 VAXG15 B4 0.1U_0402_10V7K
VAXG16 SA_DIMM_VREFDQ +VREF_DQA_M3 2
AP18 D1
VAXG17 SB_DIMM_VREFDQ +VREF_DQB_M3
AP17
AN24 VAXG18
AN23 VAXG19
AN21 VAXG20
VAXG21
VREF traces should be at least
AN20 +1.5V_CPU
AN18 VAXG22 +1.5V_CPU Decoupling: 20 mils wide and 20 mils spacing
VAXG23 5A to other signals/planes.

DDR3 -1.5V RAILS


AN17
AM24 VAXG24 AF7 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
1X 47U (MLCC), 6X 10U

GRAPHICS
AM23 VAXG25 VDDQ1 AF4
AM21 VAXG26 VDDQ2 AF1
VAXG27 VDDQ3 1 1 1 1 1 1

1
AM20 AC7 CC57 CC51 CC52 CC55 CC54 CC56 CC50
AM18 VAXG28 VDDQ4 AC4 47U_0805_6.3V6M
AM17 VAXG29 VDDQ5 AC1 @

2
AL24 VAXG30 VDDQ6 Y7 2 2 2 2 2 2
AL23 VAXG31 VDDQ7 Y4
AL21 VAXG32 VDDQ8 Y1 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
AL20 VAXG33 VDDQ9 U7
C AL18 VAXG34 VDDQ10 U4 C
AL17 VAXG35 VDDQ11 U1
AK24 VAXG36 VDDQ12 P7
AK23 VAXG37 VDDQ13 P4
AK21 VAXG38 VDDQ14 P1
AK20 VAXG39 VDDQ15
AK18 VAXG40 +VCCSA Decoupling:
VAXG41
AK17
AJ24 VAXG42 1X 47U (MLCC), 3X 10U
AJ23 VAXG43
AJ21 VAXG44 +VCCSA
VAXG45 Bottom Socket Cavity VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ20
AJ18 VAXG46 6A
AJ17 VAXG47 M27
VAXG48 VCCSA1
10U_0603_6.3V6M 0 0 0.90 V
AH24 M26 For Sandy Bridge
SA RAIL

AH23 VAXG49 VCCSA2 L26


AH21 VAXG50 VCCSA3 J26
VAXG51 VCCSA4 1 1 1 0 1 0.80 V

1
AH20 J25 CC42 CC41 CC43 CC44
AH18 VAXG52 VCCSA5 J24 47U_0805_6.3V6M
AH17 VAXG53 VCCSA6 H26 @ 1 0 0.725 V

2
VAXG54 VCCSA7 H25 2 2 2
VCCSA8
10U_0603_6.3V6M 10U_0603_6.3V6M 1 1 0.675 V
VCCPLL Decoupling: Bottom Socket Edge
1.8V RAIL

1X 10U, 1x 1U VCCSA_SENSE
H23
1.2A
1 Rshort@ 2 +1.8VS_VCCPLL B6
+1.8VS VCCPLL1
RC119 0_0805_5% A6 C22
MISC

A2 VCCPLL2 VCCSA_VID[0] C24 H_VCCSA_VID0 <50>


H_VCCSA_VID1 <50>
Please kindly check whether
B VCCPLL3 VCCSA_VID[1] B
1 1 there is pull-down resister
CC59 CC60 in PWR-side or HW-side
10U_0603_6.3V6M A19 10/3: confirmed with PWR, IC intergrate PD
2 2 VCCIO_SEL

1U_0402_6.3V6K TYCO_2013620-2_IVY BRIDGE

+1.5V_CPU JP@ +1.5VS


Conn@ PJ1
2 1
+1.5V_CPU +1.5V 2 1
JUMP_43X39
Vgs=10V,Id=14.5A,Rds=6mohm +1.5V
CC46 1 2 0.1U_0402_10V7K QC4
@ 1 8
CC47 1 2 0.1U_0402_10V7K 2 S D 7
S D

2
@ 1 3 6
CC48 1 2 0.1U_0402_10V7K RC203 CC68 4 S D 5
@ 470_0805_5% 10U_0603_6.3V6M G D
CC45 1 2 0.1U_0402_10V7K FDS6676AS_SO8 RC204
@ 2 RUN_ON_CPU1.5VS3 1 2
B+

3 1
220K_0402_5%

6
1
QC5B 1
CC69 RC205 QC5A
SUSP 5 0.1U_0402_25V6 820K_0402_5%
2 SUSP
2 SUSP <43>
2N7002DW-T/R7_SOT363-6

2
2N7002DW-T/R7_SOT363-6

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_POWER-2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

JCPUH JCPUI
JCPUE CFG Straps for Processor
AT35 AJ22 (CFG[17:0] internal pull high 5~15K to VCCIO)
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS161 VSS234 F19 AH27 PAD T3
AT25 VSS4 VSS84 AJ10 T33 VSS162 VSS235 E30 AK28 VCC_DIE_SENSE AH26
AT22 VSS5 VSS85 AJ7 T32 VSS163 VSS236 E27 AK29 CFG[0] VSS_DIE_SENSE CFG2
AT19 VSS6 VSS86 AJ4 T31 VSS164 VSS237 E24 CFG2 AL26 CFG[1]
VSS7 VSS87 VSS165 VSS238 CFG[2]

1
AT16 AJ3 T30 E21 AL27
AT13 VSS8 VSS88 AJ2 T29 VSS166 VSS239 E18 CFG4 AK26 CFG[3] L7 RC79
AT10 VSS9 VSS89 AJ1 T28 VSS167 VSS240 E15 CFG5 AL29 CFG[4] RSVD28 AG7 1K_0402_1%
AT7 VSS10 VSS90 AH35 T27 VSS168 VSS241 E13 CFG6 AL30 CFG[5] RSVD29 AE7 @
AT4 VSS11 VSS91 AH34 T26 VSS169 VSS242 E10 CFG7 AM31 CFG[6] RSVD30 AK2
D D

2
AT3 VSS12 VSS92 AH32 P9 VSS170 VSS243 E9 AM32 CFG[7] RSVD31
AR25 VSS13 VSS93 AH30 P8 VSS171 VSS244 E8 AM30 CFG[8] W8

CFG
AR22 VSS14 VSS94 AH29 P6 VSS172 VSS245 E7 T14 PAD CFG10 AM28 CFG[9] RSVD32
AR19 VSS15 VSS95 AH28 P5 VSS173 VSS246 E6 T20 PAD CFG11 AM26 CFG[10]
AR16 VSS16 VSS96 AH25 P3 VSS174 VSS247 E5 T23 PAD CFG12 AN28 CFG[11] AT26
AR13 VSS17 VSS98 AH22 P2 VSS175 VSS248 E4 T18 PAD CFG13 AN31 CFG[12] RSVD33 AM33
AR10 VSS18 VSS99 AH19 N35 VSS176 VSS249 E3 T22 PAD CFG14 AN26 CFG[13] RSVD34 AJ27
VSS19 VSS100 VSS177 VSS250 CFG[14] RSVD35 PEG Static Lane Reversal - CFG2 is for the 16x
AR7 AH16 N34 E2 T21 PAD CFG15 AM27
AR4 VSS20 VSS101 AH7 N33 VSS178 VSS251 E1 T24 PAD CFG16 AK31 CFG[15]
AR2 VSS21 VSS102 AH4 N32 VSS179 VSS252 D35 T25 PAD CFG17 AN29 CFG[16]
1: Normal Operation; Lane # definition matches
AP34
AP31
VSS22
VSS23
VSS24
VSS103
VSS104
VSS105
AG9
AG8
N31
N30
VSS180
VSS181
VSS182
VSS253
VSS254
VSS255
D32
D29
CFG[17]
CFG2
* socket pin map definition
AP28 AG4 N29 D26 T8
AP25 VSS25 VSS106 AF6 N28 VSS183 VSS256 D20 RSVD37 J16
VSS26 VSS107 VSS184 VSS257 RSVD38 0:Lane Reversed
AP22 AF5 N27 D17 AJ31 H16
AP19 VSS27 VSS108 AF3 N26 VSS185 VSS258 C34 AH31 VAXG_VAL_SENSE RSVD39 G16
AP16 VSS28 VSS109 AF2 M34 VSS186 VSS259 C31 AJ33 VSSAXG_VAL_SENSE RSVD40 CFG4
AP13 VSS29 VSS110 AE35 L33 VSS187 VSS260 C28 AH33 VCC_VAL_SENSE
VSS30 VSS111 VSS188 VSS261 VSS_VAL_SENSE

1
AP10 AE34 L30 C27
AP7 VSS31 VSS112 AE33 L27 VSS189 VSS262 C25 RC82
AP4 VSS32 VSS113 AE32 L9 VSS190 VSS263 C23 AJ26 AR35 1K_0402_1%
AP1 VSS33 VSS114 AE31 L8 VSS191 VSS264 C10 RSVD5 RSVD_NCTF1 AT34 IEDP@
VSS34 VSS115 VSS192 VSS265 RSVD_NCTF2

RESERVED
AN30 AE30 L6 C1 AT33

2
AN27 VSS35 VSS116 AE29 L5 VSS193 VSS266 B22 RSVD_NCTF3 AP35
AN25 VSS36 VSS117 AE28 L4 VSS194 VSS267 B19 RSVD_NCTF4 AR34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD_NCTF5

AN16 AE9 L1 B13 F25


AN13 VSS40 VSS121 AD7 K35 VSS198 VSS271 B11 F24 RSVD8
AN10 VSS41 VSS122 AC9 K32 VSS199 VSS272 B9 F23 RSVD9
VSS42 VSS123 VSS200 VSS273 RSVD10 Embedded Display Port Presence Strap
AN7 AC8 K29 B8 D24 B34
AN4 VSS43 VSS124 AC6 K26 VSS201 VSS274 B7 G25 RSVD11 RSVD_NCTF6 A33
AM29 VSS44 VSS125 AC5 J34 VSS202 VSS275 B5 G24 RSVD12 RSVD_NCTF7 A34 1 : Disabled; No Physical Display Port
*
C C
AM25 VSS45 VSS126 AC3 J31 VSS203 VSS276 B3 E23 RSVD13 RSVD_NCTF8 B35
AM22 VSS46 VSS127 AC2 H33 VSS204 VSS277 B2 D23 RSVD14 RSVD_NCTF9 C35 attached to Embedded Display Port
AM19 VSS47 VSS128 AB35 H30 VSS205 VSS278 A35 C30 RSVD15 RSVD_NCTF10
VSS48 VSS129 VSS206 VSS279 RSVD16 CFG4
AM16 AB34 H27 A32 A31 0 : Enabled; An external Display Port device is
AM13 VSS49 VSS130 AB33 H24 VSS207 VSS280 A29 B30 RSVD17
AM10 VSS50 VSS131 AB32 H21 VSS208 VSS281 A26 B29 RSVD18 connected to the Embedded Display Port
AM7 VSS51 VSS132 AB31 H18 VSS209 VSS282 A23 D30 RSVD19 AJ32
AM4 VSS52 VSS133 AB30 H15 VSS210 VSS283 A20 B31 RSVD20 RSVD51 AK32
AM3 VSS53 VSS134 AB29 H13 VSS211 VSS284 A3 A30 RSVD21 RSVD52
AM2 VSS54 VSS135 AB28 H10 VSS212 VSS285 C29 RSVD22
AM1 VSS55 VSS136 AB27 H9 VSS213 RSVD23
AL34 VSS56 VSS137 AB26 H8 VSS214 AN35
AL31 VSS57 VSS138 Y9 H7 VSS215 J20 BCLK_ITP AM35 CFG6
AL28 VSS58 VSS139 Y8 H6 VSS216 B18 RSVD24 BCLK_ITP#
AL25 VSS59 VSS140 Y6 H5 VSS217 RSVD25 CFG5
AL22 VSS60 VSS141 Y5 H4 VSS218

1
AL19 VSS61 VSS142 Y3 H3 VSS219
AL16 VSS62 VSS143 Y2 H2 VSS220 J15 AT2 RC83 RC84
AL13 VSS63 VSS144 W35 H1 VSS221 RSVD27 RSVD_NCTF11 AT1 1K_0402_1% 1K_0402_1%
AL10 VSS64 VSS145 W34 G35 VSS222 RSVD_NCTF12 AR1 @ @
AL7 VSS65 VSS146 W33 G32 VSS223 RSVD_NCTF13

2
AL4 VSS66 VSS147 W32 G29 VSS224
AL2 VSS67 VSS148 W31 G26 VSS225
AK33 VSS68 VSS149 W30 G23 VSS226 B1 PAD T64
AK30 VSS69 VSS150 W29 G20 VSS227 KEY
AK27 VSS70 VSS151 W28 G17 VSS228
AK25 VSS71 VSS152 W27 G11 VSS229
AK22 VSS72 VSS153 W26 F34 VSS230
AK19 VSS73 VSS154 U9 F31 VSS231
AK16 VSS74 VSS155 U8 F29 VSS232 TYCO_2013620-2_IVY BRIDGE
VSS75 VSS156 VSS233
PCIE Port Bifurcation Straps
AK13 U6
AK10 VSS76 VSS157 U5
VSS77 VSS158 Conn@
AK7 U3 11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: x8, x8 - Device 1 function 1 enabled ; function 2
B B
AK4 VSS78 VSS159 U2
AJ25 VSS79 VSS160
VSS80
disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function
TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Conn@ Conn@

CFG7

1
RC85
1K_0402_1%
@

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB


de assertion
CFG7
0: PEG Wait for BIOS for training
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_GND/RSVD/CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V

1
JDDR3L
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_A_D4
DDR_A_D5
Standard Type DDR_A_DQS[0..7] <7>
DDR_A_D1 7 DQ0 DQ5 8
1 DQ1 VSS3 DDR_A_DQS#[0..7] <7>
CD1 9 10 DDR_A_DQS#0
11 VSS4 DQS#0 12 DDR_A_DQS0
DM0 DQS0 DDR_A_D[0..63] <7>
0.1U_0402_10V7K
13 14
2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DQ2 DQ6 DDR_A_MA[0..15] <7>
DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20
D DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 D
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30
Close to JDDR3L.1 31 DQS1 RESET# 32 SM_DRAMRST# <12,7>
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3 +1.5V
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DQ26 DQ30

1
DDR_A_D27 69 70 DDR_A_D31
71 DQ27 DQ31 72 RD1
VSS25 VSS26 1K_0402_1%

2
73 74
<7> DDRA_CKE0 75 CKE0 CKE1 76 DDRA_CKE1 <7>
VDD1 VDD2 +VREF_DQA
77 78 DDR_A_MA15
C 79 NC1 A15 80 DDR_A_MA14 C
<7> DDR_A_BS2 BA2 A14

1
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11 RD2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 1K_0402_1%
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6

2
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<7> DDRA_CLK0 103 CK0 CK1 104 DDRA_CLK1 <7>
<7> DDRA_CLK0# 105 CK0# CK1# 106 DDRA_CLK1# <7>
DDR_A_MA10 107 VDD11 VDD12 108 +1.5V
109 A10/AP BA1 110 DDR_A_BS1 <7>
<7> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <7>
VDD13 VDD14

1
113 114
<7> DDR_A_WE# 115 WE# S0# 116 DDRA_SCS0# <7>
RD6
<7> DDR_A_CAS# 117 CAS# ODT0 118 DDRA_ODT0 <7>
1K_0402_1%
DDR_A_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDRA_ODT1 <7>

2
<7> DDRA_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAA
127 NCTEST VREF_CA 128
VSS27 VSS28

1
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD7
133 DQ33 DQ37 134 1K_0402_1%
DDR_A_DQS#4 135 VSS29 VSS30 136
DDR_A_DQS4 137 DQS#4 DM4 138 1

2
139 DQS4 VSS31 140 DDR_A_D38 CD16
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
DQ34 DQ39
0.1U_0402_10V7K

B DDR_A_D35 143 144 B


145 DQ35 VSS33 146 DDR_A_D44 2
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
161 DQ43 DQ47 162
close to JDDR3L.126
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 +1.5V +1.5V +0.75VS
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55 CD8 1 2 10U_0603_6.3V6M CD20 1 2 0.1U_0402_10V7K CD24 2 1 1U_0402_6.3V6K
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60 CD9 1 2 10U_0603_6.3V6M CD17 1 2 0.1U_0402_10V7K CD21 2 1 1U_0402_6.3V6K
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184 CD10 1 2 10U_0603_6.3V6M CD18 1 2 0.1U_0402_10V7K
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7 CD11 1 2 10U_0603_6.3V6M CD19 1 2 0.1U_0402_10V7K
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62 CD12 1 2 10U_0603_6.3V6M
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196 CD13 1 2 10U_0603_6.3V6M
197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS 201 VDDSPD SDA 202 PM_SMBDATA <12,26,35,42>
203 SA1 SCL 204 PM_SMBCLK <12,26,35,42>
1 +0.75VS VTT1 VTT2 +0.75VS
A 205 206 A
CD26 G1 G2
2 LCN_DAN06-K4406-0102
Conn@

0.1U_0402_10V7K

SPD setting (SA0, SA1) Security Classification Compal Secret Data Compal Electronics, Inc.
PU/PD by Channel A/B Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
->Channel A 00
->Channel B 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 11 of 56
5 4 3 2 1
A B C D E

+1.5V +1.5V

1
JDDR3H
2
DDR3 SO-DIMM B
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_B_D4
DDR_B_D5
Standard Type
DDR_B_D1 7 DQ0 DQ5 8
CD27 9 DQ1 VSS3 10 DDR_B_DQS#0
1 VSS4 DQS#0
11 12 DDR_B_DQS0
13 DM0 DQS0 14
VSS5 VSS6
0.1U_0402_10V7K
DDR_B_D2 15 16 DDR_B_D6
2 DQ2 DQ6 DDR_B_DQS#[0..7] <7>
DDR_B_D3 17 18 DDR_B_D7
1 19 DQ3 DQ7 20 1
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12 DDR_B_DQS[0..7] <7>
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ9 DQ13 DDR_B_D[0..63] <7>
25 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DQS#1 DM1 DDR_B_MA[0..15] <7>
DDR_B_DQS1 29 30
31 DQS1 RESET# 32 SM_DRAMRST# <11,7>
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
Close to JDDR3H.1 DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29 +1.5V
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
VSS22 DQS#3

1
63 64 DDR_B_DQS3
65 DM3 DQS3 66 RD10
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30 1K_0402_1%
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72

2
VSS25 VSS26

+VREF_DQB
73 74
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>

1
75 76
2 77 VDD1 VDD2 78 DDR_B_MA15 RD11 2
79 NC1 A15 80 DDR_B_MA14 1K_0402_1%
<7> DDR_B_BS2 81 BA2 A14 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11

2
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
101 VDD9 VDD10 102
<7> DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 <7>
<7> DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# <7>
DDR_B_MA10 107 VDD11 VDD12 108 +1.5V
109 A10/AP BA1 110 DDR_B_BS1 <7>
<7> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <7>
VDD13 VDD14

1
113 114
<7> DDR_B_WE# 115 WE# S0# 116 DDRB_SCS0# <7>
RD12
<7> DDR_B_CAS# 117 CAS# ODT0 118 DDRB_ODT0 <7>
1K_0402_1%
DDR_B_MA13 119 VDD15 VDD16 120
121 A13 ODT1 122 DDRB_ODT1 <7>

2
<7> DDRB_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAB
127 NCTEST VREF_CA 128
VSS27 VSS28

1
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37 RD13
133 DQ33 DQ37 134 CD47 1K_0402_1%
VSS29 VSS30 1
DDR_B_DQS#4 135 136
DDR_B_DQS4 137 DQS#4 DM4 138

2
DQS4 VSS31
0.1U_0402_10V7K

139 140 DDR_B_D38


3 DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 3
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
Close to JDDR3H.126 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168 +1.5V +1.5V +0.75VS
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172 CD31 1 2 47U_0805_6.3V6M
173 DQS6 VSS43 174 DDR_B_D54 CD33 1 2 0.1U_0402_10V7K CD45 2 1 1U_0402_6.3V6K
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55 CD41 1 2 10U_0603_6.3V6M
DDR_B_D51 177 DQ50 DQ55 178 CD29 1 2 0.1U_0402_10V7K CD42 2 1 1U_0402_6.3V6K
179 DQ51 VSS45 180 DDR_B_D60 CD36 1 2 10U_0603_6.3V6M
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61 CD30 1 2 0.1U_0402_10V7K
DDR_B_D57 183 DQ56 DQ61 184 CD37 1 2 10U_0603_6.3V6M
185 DQ57 VSS47 186 DDR_B_DQS#7 CD32 1 2 0.1U_0402_10V7K
187 VSS48 DQS#7 188 DDR_B_DQS7 CD38 1 2 10U_0603_6.3V6M
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 CD39 1 2 10U_0603_6.3V6M
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196 CD40 1 2 10U_0603_6.3V6M
197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS 2 1 201 VDDSPD SDA 202 PM_SMBDATA <11,26,35,42>
203 SA1 SCL 204 PM_SMBCLK <11,26,35,42>
1 RD15 10K_0402_5% +0.75VS +0.75VS
4 VTT1 VTT2 4
205 206
CD49 G1 G2
2 LCN_DAN06-K4806-0102
0.1U_0402_10V7K Conn@

SPD setting (SA0, SA1) Security Classification Compal Secret Data Compal Electronics, Inc.
PU/PD by Channel A/B Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
->Channel A 00
->Channel B 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 12 of 56
A B C D E
A B C D E

UV1A

Part 1 of 6 DV1
PCIE_GTX_C_CRX_P[0..3] PCIE_CTX_C_GRX_P0 AG6 C6 FB_CLAMP_MON 2 1
<6> PCIE_GTX_C_CRX_P[0..3] AG7 PEX_RX0 GPIO0 B2 FB_CLAMP <14,17,41> +3VS_DGPU
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1 AF7 PEX_RX0_N GPIO1 D6 +3VS_DGPU
RB751V40_SC76-2

2
PEX_RX1 GPIO2

G
PCIE_GTX_C_CRX_N[0..3] PCIE_CTX_C_GRX_N1 AE7 C7 OPT@ RPV1
<6> PCIE_GTX_C_CRX_N[0..3] PCIE_CTX_C_GRX_P2 AE9 PEX_RX1_N GPIO3 F9 GPS_DOWN# 1 8
PEX_RX2 GPIO4 QV8
PCIE_CTX_C_GRX_N2 AF9 A3 GPU_EVENT 2 7
PEX_RX2_N GPIO5 N14PGV2@
PCIE_CTX_C_GRX_P[0..3] PCIE_CTX_C_GRX_P3 AG9 A4 FB_CLAMP_REQ# 3 1 XTAL_OUTBUFF 3 6
<6> PCIE_CTX_C_GRX_P[0..3] CLK_REQ_GC6# <41>
PCIE_CTX_C_GRX_N3 AG10 PEX_RX3 GPIO6 B6 For GC6 XTAL_SSIN 4 5

D
S
AF10 PEX_RX3_N GPIO7 A6 OVERT#_VGA
PEX_RX4 GPIO8 2N7002KW_SOT323-3
PCIE_CTX_C_GRX_N[0..3] AE10 F8 GPU_EVENT 10K_8P4R_5%
<6> PCIE_CTX_C_GRX_N[0..3] AE12 PEX_RX4_N GPIO9 C5 OPT@
1 AF12 PEX_RX5 GPIO10 E7 DGPU_VID 1
AG12 PEX_RX5_N GPIO11 D7 GPS_DOWN# DGPU_VID <54>
RPV2
AG13 PEX_RX6 GPIO12 B4 PSI GPS_DOWN# <41> VGA_EDID_CLK 1 8

GPIO
AF13 PEX_RX6_N GPIO13 B3 PSI <54> 2 7
VGA_EDID_DATA
AE13 PEX_RX7 GPIO14 C3 SMB_CLK_GPU 3 6
AE15 PEX_RX7_N GPIO15 D5 SMB_DATA_GPU 4 5
AF15 NC GPIO16 D4
AG15 NC GPIO17 C2 2.2K_8P4R_5%
AG16 NC GPIO18 F7 OPT@
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4 RPV3
AE18 NC GPIO21 VGA_CRT_CLK 1 8
AF18 NC AB6 VGA_CRT_DATA 2 7
AG18 NC NC HDCP_SDA 3 6
AG19 NC HDCP_SCL 4 5
AF19 NC
AE19 NC 2.2K_8P4R_5%
AE21 NC AG3 OPT@
AF21 NC DACA_RED AF4
AG21 NC DACA_GREEN AF3 RPV12
AG22 NC DACA_BLUE FB_CLAMP 1 8
NC FB_CLAMP_REQ# 2 7
FB_CLAMP_MON 3 6
PCIE_GTX_C_CRX_P0 CV1 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_P0 AC9 AE3 OVERT#_VGA 4 5
PEX_TX0 DACA_HSYNC

DACs
PCIE_GTX_C_CRX_N0 CV2 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N0 AB9 AE4
PCIE_GTX_C_CRX_P1 CV3 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_P1 AB10 PEX_TX0_N DACA_VSYNC 10K_8P4R_5%
PCIE_GTX_C_CRX_N1 CV4 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N1 AC10 PEX_TX1 OPT@
PCIE_GTX_C_CRX_P2 1 2 PCIE_GTX_CRX_P2 AD11 PEX_TX1_N

PCI EXPRESS
CV5 OPT@ 0.22U_0402_16V7K
PCIE_GTX_C_CRX_N2 CV6 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N2 AC11 PEX_TX2 W5 RPV13
PCIE_GTX_C_CRX_P3 1 2 PCIE_GTX_CRX_P3 AC12 PEX_TX2_N 120mA DACA_VDD AE2 CLK_REQ_GC6# 1 8
CV7 OPT@ 0.22U_0402_16V7K +3VS
PCIE_GTX_C_CRX_N3 CV8 1 2 OPT@ 0.22U_0402_16V7K PCIE_GTX_CRX_N3 AB12 PEX_TX3 DACA_VREF AF2 2 7
PEX_TX3_N DACA_RSET <15> JTAG_TRST
AB13 3 6
2 PEX_TX4 <15> TESTMODE 2
AC13 CLK_REQ_GPU# 4 5
AD14 PEX_TX4_N
AC14 PEX_TX5 10K_8P4R_5%
AC15 PEX_TX5_N OPT@
AB15 PEX_TX6
AB16 PEX_TX6_N B7 VGA_CRT_CLK
AC16 PEX_TX7 I2CA_SCL A7 VGA_CRT_DATA
AD17 PEX_TX7_N I2CA_SDA
AC17 NC C9 HDCP_SCL
AC18 NC I2CB_SCL C8 HDCP_SDA
NC I2CB_SDA

I2C
AB18
AB19 NC A9 VGA_EDID_CLK Internal Thermal Sensor
AC19 NC I2CC_SCL B9 VGA_EDID_DATA
AD20 NC I2CC_SDA +3VS_DGPU
AC20 NC D9 SMB_CLK_GPU
AC21 NC I2CS_SCL D8 SMB_DATA_GPU
AB21 NC I2CS_SDA
AD23 NC
AE23 NC
NC

5
AF24 OPT@
AE24 NC L6 +PLLVDD QV1B
AG24 NC 52mA CORE_PLLVDD M6 +1.05VS_DGPU SMB_CLK_GPU 4 3
LV1
AG25 NC SP_PLLVDD EC_SMB_CK2 <26,34,41>
71mA BLM18PG181SN1D_2P
NC

2
N6 +GPU_PLLVDD 1 2 OPT@ 2N7002DW-T/R7_SOT363-6
VID_PLLVDD

22U_0805_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
41mA OPT@ QV1A

CV9

CV11

CV12
CV10

CV13
1 1 1 1 1 SMB_DATA_GPU 1 6
AE8 EC_SMB_DA2 <26,34,41>
CLK_PCIE_VGA
<26> CLK_PCIE_VGA PEX_REFCLK
CLK_PCIE_VGA# AD8 OPT@ 2N7002DW-T/R7_SOT363-6
<26> CLK_PCIE_VGA# PEX_REFCLK_N
CLK_REQ_GPU# AC6 OPT@
PEX_CLKREQ_N 2 2 2 2 2
1 @ 2 PEX_TSTCLK_OUT AF22
CLK

RV4 200_0402_1% PEX_TSTCLK_OUT# AE22 PEX_TSTCLK_OUT C11 XTALIN


3 PEX_TSTCLK_OUT_N XTAL_IN B10 XTAL_OUT OPT@ OPT@ OPT@ 3
XTAL_OUT
AC7 A10 XTAL_SSIN CV42, CV43 under GPU
<29> PLTRST_VGA# PEX_RST_N XTAL_SSIN
AF25 C10 XTAL_OUTBUFF
PEX_TERMP XTAL_OUTBUFF close to ball : AE8,AD7
2

RV5 N14P-GV2-S-A2_FCBGA595
2.49K_0402_1% N14PGV2R3@
OPT@
1

+1.05VS_DGPU

LV2 OPT@

10U_0603_6.3V6M
+PLLVDD 1 2

OPT@ CV16
0.1U_0402_10V7K
1 2 XTALIN FBMA-L11-160808300LMA25T_2P 1
<35> VGA_X1

22U_0805_6.3V6M
OPT@ CV14

OPT@ CV15
RV8 0_0402_5% 1 1
GCLK@
under GPU
1 2
NOGCLK@ RV7 @EMI@
close to AD8 2 2
<26> CLK_REQ_VGA#
10_0402_5%
YV1 27MHZ_16PF
2

XTALIN 1 3 XTAL_OUT 1
1 3
6

CV113 @EMI@
QV2A GND GND 10P_0402_50V8J
1 2 4 1 2
2 CV17 CV18
+3VS_DGPU
2N7002DW-T/R7_SOT363-6 18P_0402_50V8J 18P_0402_50V8J
OPT@ NOGCLK@
NOGCLK@ for EMI
1

2 2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title
VGA_N14x PEG & DAC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 13 of 56
A B C D E
A

VRAM Interface Place close to the first T point

MDA[15..0]
<18,20> MDA[15..0] +VRAM_1.5VS
UV1B
MDA[31..16]
<18,20> MDA[31..16]
CMDA12
MDA[47..32] CMDA14
<19,21> MDA[47..32]
Part 2 of 6 CMDA15
MDA[63..48] CMDA[30..0] <18,19,20,21> CMDA7
<19,21> MDA[63..48] MDA0 E18 C27 CMDA0
MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1
MDA2 E16 FBA_D01 FBA_CMD1 E24 CMDA2

10

10
FBA_D02 FBA_CMD2

9
8
7
6

9
8
7
6
MDA3 F17 F24 CMDA3
MDA4 D20 FBA_D03 FBA_CMD3 D27 CMDA4 RPV4 RPV5
MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5
FBA_D05 FBA_CMD5 100_1206_10P8R_5% 100_1206_10P8R_5%
MDA6 F20 F25 CMDA6
MDA7 E21 FBA_D06 FBA_CMD6 F26 CMDA7 OPT@ OPT@
MDA8 E15 FBA_D07 FBA_CMD7 F23 CMDA8
MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10

1
2
3
4
5

1
2
3
4
5
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
MDA13 B13 FBA_D12 FBA_CMD12 G25 CMDA13 CMDA11
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 CMDA4
MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 CMDA5
MDA16 B15 FBA_D15 FBA_CMD15 M24 CMDA16 CMDA6
MDA17 C16 FBA_D16 FBA_CMD16 M23 CMDA17
MDA18 A13 FBA_D17 FBA_CMD17 K24 CMDA18
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21 +VRAM_1.5VS
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 CMDA22
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CMDA9
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 CMDA21
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26 CMDA24
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28
MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29

10

10
FBA_D29 FBA_CMD29

9
8
7
6

9
8
7
6
MDA30 C20 J27 CMDA30
MDA31 C21 FBA_D30 FBA_CMD30 J26 RPV6 RPV7
MDA32 R22 FBA_D31 FBA_CMD31
FBA_D32 DQMA[3..0] <18,20> 100_1206_10P8R_5% 100_1206_10P8R_5%
MDA33 R24 D19 DQMA0

INTERFACE A
MDA34 T22 FBA_D33 FBA_DQM0 D14 DQMA1 OPT@ OPT@
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3
N26 FBA_D36 FBA_DQM3 P24 DQMA[7..4] <19,21>
MDA37 DQMA4

MEMORY

1
2
3
4
5

1
2
3
4
5
MDA38 N23 FBA_D37 FBA_DQM4 W24 DQMA5
MDA39 N24 FBA_D38 FBA_DQM5 AA25 DQMA6
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7 CMDA23
MDA41 V22 FBA_D40 FBA_DQM7 CMDA13
T23 FBA_D41 F19 DQSA#[3..0] <18,20>
MDA42 DQSA#0 CMDA8
MDA43 U22 FBA_D42 FBA_DQS_RN0 C14 DQSA#1 CMDA10
MDA44 Y24 FBA_D43 FBA_DQS_RN1 A16 DQSA#2
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3
Y22 FBA_D45 FBA_DQS_RN3 P25 DQSA#[7..4] <19,21>
1 MDA46 DQSA#4 1

MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5


MDA48 AD27 FBA_D47 FBA_DQS_RN5 AB27 DQSA#6
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7 +VRAM_1.5VS
MDA50 AD26 FBA_D49 FBA_DQS_RN7
AC25 FBA_D50 E19 DQSA[3..0] <18,20> RPV9
MDA51 DQSA0 RPV8
MDA52 AA27 FBA_D51 FBA_DQS_WP0 C15 DQSA1 8 1 CMDA26 CMDA28 1 8
MDA53 AA26 FBA_D52 FBA_DQS_WP1 B16 DQSA2 7 2 CMDA25 CMDA27 2 7
30ohms (ESR=0.01) FBA_D53 FBA_DQS_WP2
MDA54 W26 B22 DQSA3 6 3 CMDA27 CMDA25 3 6
MDA55 Y25 FBA_D54 FBA_DQS_WP3 R25 DQSA4 DQSA[7..4] <19,21> 5 4 CMDA28 CMDA26 4 5
+1.05VS_DGPU MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 DQSA5
Close to H22 Close to P22 FBA_D56 FBA_DQS_WP5
LV3 OPT@ MDA57 T25 AB26 DQSA6 100_0804_8P4R_5% 100_0804_8P4R_5%
1 2 +FB_PLLAVDD MDA58 N27 FBA_D57 FBA_DQS_WP6 T26 DQSA7 OPT@ OPT@
FBMA-L11-160808300LMA25T_2P MDA59 R27 FBA_D58 FBA_DQS_WP7 2 1 CMDA29 2 1
FBA_D59
CV20

CV22

CV114
22U_0805_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV21

Place close to BGA MDA60 V26 RV10 100_0402_5% RV11 100_0402_5%


MDA61 V27 FBA_D60 OPT@ OPT@
1 2 1 1 FBA_D61
MDA62 W27 2 1 CMDA30 2 1
MDA63 W25 FBA_D62 RV12 100_0402_5% RV13 100_0402_5%
FBA_D63
OPT@

OPT@

OPT@

D24 OPT@ OPT@


2 1 2 2 FBA_CLK0 CLKA0 <18,20>
OPT@

F16 62mA D25


FB_PLLAVDD_1 FBA_CLK0_N CLKA0# <18,20>
+FB_PLLAVDD P22 62mA
FB_PLLAVDD_2 N22
FBA_CLK1 CLKA1 <19,21>
D23 M22
FB_VREF_PROBE FBA_CLK1_N CLKA1# <19,21>
Near GPU Close to F16
D18
H22 FBA_WCK01 C18
FB_DLLAVDD 35mA FBA_WCK01_N D17
F3 FBA_WCK23 D16
<13,17,41> FB_CLAMP FB_CLAMP FBA_WCK23_N Command Bit Default Pull-down
T24
FBA_WCK45 U24 ODTx 10k
TV1 PAD F22 FBA_WCK45_N V24
TV2 PAD J22 FBA_DEBUG0 FBA_WCK67 V25 DDR3 CKEx 10k
FBA_DEBUG1 FBA_WCK67_N
RST 10k
CS* No Termination

N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
CMDA16 RV36 1 OPT@ 2 10K_0402_5%
CMDA19 RV37 1 OPT@ 2 10K_0402_5%
CMDA3 RV38 1 OPT@ 2 10K_0402_5%
CMDA0 RV40 1 OPT@ 2 10K_0402_5%
CMDA20 RV15 1 OPT@ 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N14x VRAM Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 14 of 56
A
5 4 3 2 1

BINARY STRAPS (for N14M-GL) MULTI LEVEL STRAPS (for N14P-GV2)

Physical Logical Logical Logical Logical


Strap Pin Strap Mapping Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0

ROM_SCLK SMB_ALT_ADDR PD 10k ROM_SO +3VS_DGPU FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE


UV1C
PU 10k if VBIOS ROM exists
Part 3 of 6 F11 ROM_SI SUB_VENDOR PD 10k if no VBIOS ROM
AC3 NC AD10 ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR PCI_DEVID[5] PEX_PLLEN_TERM
AC4 IFPA_TXC NC AD7
Y4 IFPA_TXC_N NC B19
IFPA_TXD0 NC ROM_SO VGA_DEVICE PD 10k (no display)
Y3 V5 ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
AA3 IFPA_TXD0_N NC V6
D IFPA_TXD1 NC STRAP0 RAMCFG[0] D
AA2 G1 STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
AB1 IFPA_TXD1_N NC G2
IFPA_TXD2 NC STRAP1 RAMCFG[1]

NC
AA1
IFPA_TXD2_N NC
G3 Refer to RVL STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
AA4 G4 STRAP2 RAMCFG[2]
AA5 IFPA_TXD3 NC G5
IFPA_TXD3_N NC G6 STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
NC STRAP3 RAMCFG[3]
G7
AB5 NC V1 STRAP3 +3VS_DGPU SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
IFPB_TXC NC STRAP4 PCIE_MAX_SPEED PD 10k
AB4 V2
AB3 IFPB_TXC_N NC W1 STRAP4 +3VS_DGPU RESERVED PCIE_SPEED_CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V
AB2 IFPB_TXD4 NC W2
AD3 IFPB_TXD4_N NC W3
AD2 IFPB_TXD5 NC W4
IFPB_TXD5_N NC Pull-up to +3VS
AE1 SKU Device ID biit5 to bit0 Resistor Values Pull-down to Gnd
AD1 IFPB_TXD6 _DGPU
AD4 IFPB_TXD6_N
IFPB_TXD7
OPT@ 5K 1000 0000
AD5 D11 RV16 1 2 10K_0402_5% N14P-GV2 0x1292 010010
IFPB_TXD7_N BUFRST_N
10K 1001 0001
D10
T2 NC
IFPC_L0 N14M-GL 0x1140 000000 15K 1010 0010
T3 E9
T1 IFPC_L0_N NC
IFPC_L1 20K 1011 0011
R1 E10
R2 IFPC_L1_N NC
25K 1100 0100
GENERAL

IFPC_L2
LVDS/TMDS

R3 F10
N2 IFPC_L2_N NC
IFPC_L3 30K 1101 0101
N3
IFPC_L3_N D1 STRAP0
STRAP0 35K 1110 0110
D2 STRAP1
V3 STRAP1 E4 STRAP2
IFPD_L0 STRAP2 45K 1111 0111
V4 E3 STRAP3
U3 IFPD_L0_N STRAP3 D3 STRAP4
IFPD_L1 STRAP4 MULTI LEVEL STRAPS
C U4 C1 +3VS_DGPU C
T4 IFPD_L1_N NC +3VS_DGPU
T5 IFPD_L2 N14PGV2@
R4 IFPD_L2_N F6 MULTI_STRAP_REF0_GND 1 2
IFPD_L3 MULTI_STRAP_REF0_GND

@ 1
1

@ 1

@ 1

1
10K_0402_1%

10K_0402_1%

10K_0402_1%
45.3K_0402_1%

4.99K_0402_1%
R5 F4 RV17 40.2K_0402_1%
IFPD_L3_N NC

@ 1

1
N14PGV2@

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
F5

@
NC

N14PGV2@

N14PGV2@
N1 +VGA_CORE
NC

RV19
RV18

RV20

RV21

RV22
M1

2
2

2
NC

RV23

RV24

RV25
M2 F12

2
M3 NC THERMDP STRAP0
NC
2

K2 E12 STRAP1 STRAP3 ROM_SI


K3 NC THERMDN RV26 STRAP2 STRAP4 ROM_SO
K1 NC 100_0402_1% ROM_SCLK
J1 NC OPT@
NC

@ 1

1
1

1
4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%
45.3K_0402_1%
RV31
1

1
1

1
15K_0402_1%

N14PGV2@

N14PGV2@
N14PGV2@

N14PGV2@

10K_0402_1%
10K_0402_1%

10K_0402_1%
N14MGL@
N14MGL@

N14MGL@
M4 F2 VGA_VCC_SENSE
M5 NC VDD_SENSE VGA_VCC_SENSE <54>
NC 10K_0402_1%

RV27

RV30

RV31
RV28

RV29
L3 trace width: 16mils

2
2

2
NC N14MGL@

RV33
RV32

RV34
L4
differential voltage sensing.

2
2

2
K4 NC
NC
differential signal routing.
K5
J4 NC F1 VGA_VSS_SENSE
NC GND_SENSE VGA_VSS_SENSE <54> For X76 (N14M-GL) For X76 (N14P-GV2)

OPT@
J5 2 1
N4 NC RV35
N5 IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
TEST 100_0402_1% GPU FB Memory gDDR3 ROM_SI GPU FB Memory gDDR3 STRAP[3:0]
B P3 AD9 B
P4 IFPD_AUX_I2CX_SCL TESTMODE AE5 JTAG_TCK TESTMODE <13>
IFPD_AUX_I2CX_SDA_N JTAG_TCK PAD TV3 900MHz K4W2G1646E-BC11 900MHz K4W2G1646E-BC11
AE6 JTAG_TDI Samsung PD 45.3K Samsung 0101
JTAG_TDI PAD TV4
AF6 JTAG_TDO 1 1
JTAG_TDO PAD TV5
J2 AD6 JTAG_TMS 1GHz K4W2G1646E-BC1A 1GHz K4W2G1646E-BC1A
IFPE_AUX_I2CY_SCL JTAG_TMS PAD TV6 2 2
J3 AG4
IFPE_AUX_I2CY_SDA_N JTAG_TRST_N JTAG_TRST <13>
8 8
M Hynix 900MHz H5TQ2G63DFR-11C M Hynix 900MHz H5TQ2G63DFR-11C
H3 PD 34.8K 0110
H4 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N SERIAL 1GHz H5TQ2G63DFR-N0C 1GHz H5TQ2G63DFR-N0C
D12 x x
ROM_CS_N B12 ROM_SI 1 1
ROM_SI A12 ROM_SO
ROM_SO C12 ROM_SCLK
6 6
ROM_SCLK Micron 900MHz MT41K128M16JT-107G PD 30K Micron 900MHz MT41K128M16JT-107G 0001

N14P-GV2 N14M-GL
N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
Samsung 900MHz K4W4G1646B-HC11 PD 20K Samsung 900MHz K4W4G1646B-HC11 1011
2 2
5 5
6 6
M Micron 900MHz MT41K256M16HA-107G PD 10K M Micron 900MHz MT41K256M16HA-107G 1101
x x
1 1
A 6 6 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x LVDS&TMDS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 15 of 56
5 4 3 2 1
5 4 3 2 1

midway between GPU


Under GPU Near GPU and Power supply +1.05VS_DGPU

+VRAM_1.5VS

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
Under GPU UV1D

OPT@ CV26

OPT@ CV23

OPT@ CV27

OPT@ CV28

OPT@ CV29

OPT@ CV30

OPT@ CV31
1 1 1 1 1 1 1
3500 mA Part 4 of 6 2000 mA
B26 AA10
D FBVDDQ_01 PEX_IOVDDQ_1 D

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K
C25 AA12

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_02 PEX_IOVDDQ_2 2 2 2 2 2 2 2

OPT@ CV32

OPT@ CV24

OPT@ CV33

OPT@ CV34

OPT@ CV25

OPT@ CV35
1 1 1 1 1 1 E23 AA13
E26 FBVDDQ_03 PEX_IOVDDQ_3 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19
2 2 2 2 2 2 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21 +1.05VS_DGPU
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
FBVDDQ_10 PEX_IOVDDQ_10

10U_0603_6.3V6M
10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
G18 AD24

4.7U_0603_6.3V6K
FBVDDQ_11 PEX_IOVDDQ_11

OPT@ CV40
OPT@ CV36

OPT@ CV37

OPT@ CV38

OPT@ CV39

OPT@ CV41

OPT@ CV42
G19 AE25 1 1 1 1 1 1 1
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26
Near GPU FBVDDQ_13 PEX_IOVDDQ_13
G21 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
FBVDDQ_15 2 2 2 2 2 2 2

22U_0805_6.3V6M

10U_0603_6.3V6M
H26
FBVDDQ_16

OPT@ CV43

OPT@ CV44
1 1 J21 AA22
K21 FBVDDQ_17 PEX_IOVDD_1 AB23
L22 FBVDDQ_18 PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25

POWER
2 2 L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27 +3VS_DGPU
N21 FBVDDQ_22 PEX_IOVDD_6
FBVDDQ_23
Under GPU Near GPU
R21
FBVDDQ_24

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
0.1U_0402_10V7K
T21

4.7U_0603_6.3V6K
FBVDDQ_25

OPT@ CV45

OPT@ CV47

OPT@ CV48
OPT@ CV46

OPT@ CV49
V21 1 1 1 1 1
W21 FBVDDQ_26
FBVDDQ_27 G10
VDD33_1 G12
VDD33_2 G8 2 2 2 2 2
VDD33_3 G9
VDD33_4

C V7 Near Ball C
W7 IFPAB_PLLVDD_1
AA6 IFPAB_PLLVDD_2
W6 IFPAB_RSET D22 +FB_CAL_PD_VDDQ 1 2
IFPA_IOVDD FB_CAL_PD_VDDQ +VRAM_1.5VS
Y6 40.2_0402_1% RV39
IFPB_IOVDD OPT@
C24 FB_CAL_PU_GND 2 1
FB_CAL_PU_GND 42.2_0402_1% RV41
OPT@
M7 B25 FB_CAL_TERM_GND 2 1
N7 IFPC_PLLVDD_1 FB_CAL_TERM_GND 51.1_0402_1% RV42
T6 IFPC_PLLVDD_2 OPT@
P6 IFPC_RSET
IFPC_IOVDD

T7 Under GPU
R7 IFPD_PLLVDD_2 +3VS_DGPU
Close to AH12/AG12
U6 IFPD_PLLVDD_1
Near GPU
R6 IFPD_RSET AA8
IFPD_IOVDD PEX_PLL_HVDD_1

0.1U_0402_10V7K
0.1U_0402_10V7K
AA9

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
PEX_PLL_HVDD_2

OPT@ CV51

OPT@ CV53
OPT@ CV50

OPT@ CV52
1 1 1 1
AB8
PEX_SVDD_3V3

J7 +1.05VS_DGPU 2 2 2 2
K7 NC LV4
K6 NC 120mA AA14 +PEX_PLLVDD 2 1
NC PEX_PLLVDD_1

0.1U_0402_10V7K

1U_0402_6.3V6K
H6 AA15

4.7U_0603_6.3V6K
BLM18PG121SN1D_0603
NC PEX_PLLVDD_2 N14MGL@

OPT@ CV54

OPT@ CV55

OPT@ CV56
J6 1 1 1
NC
RV1
B 2 1 B
2 2 2 0_0603_5%
N14PGV2@

N14P-GV2-S-A2_FCBGA595
N14PGV2R3@
Under GPU Near GPU

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 16 of 56
5 4 3 2 1
5 4 3 2 1

+1.05VS_VCCP to +1.05VS_DGPU
UV1E +VGA_CORE UV1F +VGA_CORE

A2 Part 5 of 6 K11 Part 6 of 6


A26 GND_001 GND_057 K13
AB11 GND_002 GND_058 K15 K10 V18 +1.05VS_VCCP +5VALW
AB14 GND_003 GND_059 K17 K12 VDD_001 VDD_041 V16
AB17 GND_004 GND_060 L10 K14 VDD_002 VDD_040 V14 +1.05VS_DGPU
GND_005 GND_061 VDD_003 VDD_039

1
AB20 L12 K16 V12 Vgs=4.5V,Id=6.5A,Rds<22mohm
AB24 GND_006 GND_062 L14 K18 VDD_004 VDD_038 V10 RV43
GND_007 GND_063 VDD_005 VDD_037

2
D AC2 L16 L11 U17 270K_0402_5% D
GND_008 GND_064 VDD_006 VDD_036

POWER
AC22 L18 L13 U15 OPT@ QV3 OPT@ RV44
GND_009 GND_065 VDD_007 VDD_035

1
AC26 L2 L15 U13 D OPT@ 22_0805_5%

2
AC5 GND_010 GND_066 L23 L17 VDD_008 VDD_034 U11 2
AC8 GND_011 GND_067 L25 M10 VDD_009 VDD_033 T18 AO3416_SOT23-3 G

1
AD12 GND_012 GND_068 L5 M12 VDD_010 VDD_032 T16 S 1

3
GND_013 GND_069 VDD_011 VDD_031

0.01U_0402_25V7K
AD13 M11 M14 T14
GND_014 GND_070 VDD_012 VDD_030

3
AD15 M13 M16 T12 CV57 OPT@
AD16 GND_015 GND_071 M15 M18 VDD_013 VDD_029 T10 OPT@ QV4A OPT@
AD18 GND_016 GND_072 M17 N11 VDD_014 VDD_028 R17 2 QV4B
AD19 GND_017 GND_073 N10 N13 VDD_015 VDD_027 R15 2 VGA_PWROK# 5
AD21 GND_018 GND_074 N12 N15 VDD_016 VDD_026 R13 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
GND_019 GND_075 VDD_017 VDD_025 +1.05VS_DGPU
AD22 N14 N17 R11

4
AE11 GND_020 GND_076 N16 P10 VDD_018 VDD_024 P18
AE14 GND_021 GND_077 N18 P12 VDD_019 VDD_023 P16 +5VALW
AE17 GND_022 GND_078 P11 VDD_020 VDD_022 P14
AE20 GND_023 GND_079 P13 VDD_021 1 2
AF1 GND_024 GND_080 P15 100K_0402_5% RV45
AF11 GND_025 GND_081 P17
GND
GND_026 GND_082 OPT@

6
AF14 P2 QV5A D
AF17 GND_027 GND_083 P23 VGA_PWROK 2
AF20 GND_028 GND_084 P26 G
AF23 GND_029 GND_085 P5 2N7002KDWH_SOT363-6
AF5 GND_030 GND_086 R10 OPT@ S

1
AF8 GND_031 GND_087 R12
AG2 GND_032 GND_088 R14
AG26 GND_033 GND_089 R16 N14P-GV2-S-A2_FCBGA595
B1 GND_034 GND_090 R18 N14PGV2R3@
B11 GND_035 GND_091 T11
B14 GND_036 GND_092 T13
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
C B23
B27
GND_039
GND_040
GND_095
GND_096
U10
U12
+1.5V to +VRAM_1.5VS C

B5 GND_041 GND_097 U14


B8 GND_042 GND_098 U16 +1.5V +VRAM_1.5VS
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047
GND_048
GND_103
GND_104
U5 For GC6 +3VS QV6 OPT@ Vgs=10V,Id=14.5A,Rds=6mohm

2
E22 V11 8 1
E25 GND_049 GND_105 V13 7 D S 2 RV46
E5 GND_050 GND_106 V15 6 D S 3 470_0805_5%
E8 GND_051 GND_107 V17 5 D S 4 OPT@ OPT@
H2 GND_052 GND_108 Y2 D G RV47

1
H23 GND_053 GND_109 Y23 FDS6676AS_SO8 VRAM_1.5VS_GATE 1 2
GND_054 GND_110 B+
H25 Y26 1 1 180K_0402_5%
GND_055 GND_111

1
5

3
0.01U_0402_25V7K
H5 Y5

4.7U_0603_6.3V6K
UV2 N14PGV2@
GND_056 GND_112 2 CV59 CV60 RV48 QV7A

G Vcc
<13,14,41> FB_CLAMP B 4 1.5V_PWR_EN OPT@ OPT@ OPT@ 820K_0402_5% QV7B
1 Y 2 2 2 1.5V_PWR_EN# 5 2N7002DW-T/R7_SOT363-6
<30,54> VGA_PWROK A 2N7002DW-T/R7_SOT363-6 OPT@

2
AA7 NC7SZ32P5X_SC70-5 OPT@

4
GND AB7 +5VALW
GND
1 2
1 2 100K_0402_5% RV49
RV50 0_0402_5% OPT@
N14P-GV2-S-A2_FCBGA595 N14MGL@

3
N14PGV2R3@ QV5B D
1.5V_PWR_EN 5
G
2N7002KDWH_SOT363-6
B OPT@ S B

4
+3VS to +3VS_DGPU
+3VS
+3VS_DGPU +VGA_CORE +3VS
2

2
RV51 RV52 2 Vgs=-4.5V,Id=3A,Rds<97mohm
470_0805_5% 470_0805_5% RV53 CV61
OPT@ OPT@ OPT@ 10K_0402_5% 0.1U_0402_10V7K
OPT@
3 1

3 1
1

3
S
RV54 QV11
G
DGPU_PWR_EN# 1 2 2 OPT@
QV9B QV2B
2N7002DW-T/R7_SOT363-6 5 DGPU_PWR_EN# 5 2N7002DW-T/R7_SOT363-6 33K_0402_5% 2 AO3413_SOT23 D

1
6
OPT@ OPT@ OPT@
QV9A CV62 +3VS_DGPU
4

OPT@ 0.01U_0402_25V7K
2 1
<29> DGPU_PWR_EN
2N7002DW-T/R7_SOT363-6
OPT@

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x POWER & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 17 of 56
5 4 3 2 1
5 4 3 2 1

RANK 0 [31...0] Rank 0 Rank 1


Mode E
VRAM DDR3 Chips Address
CMD0
0..31
ODT
32..63 0..31
ODT
32..63

CMD1 CS1#
CMD2 CS0#
CMD3 CKE CKE
DQSA[3..0]
<14,20> DQSA[3..0]
CMD4 A9 A9 A11 A11
D DQSA#[3..0] D
<14,20> DQSA#[3..0]
CMD5 A6 A6 A7 A7
DQMA[3..0] UV3 @ UV4 @
<14,20> DQMA[3..0]
CMD6 A3 A3 BA1 BA1
MDA[31..0] +MEM_VREF_CA0 M8 E3 MDA9 +MEM_VREF_CA0 M8 E3 MDA6
<14,20> MDA[31..0] +MEM_VREF_DQ0 H1 VREFCA DQL0 F7 MDA12 +MEM_VREF_DQ0 H1 VREFCA DQL0 F7 MDA1
VREFDQ DQL1 VREFDQ DQL1 CMD7 A0 A0 A12 A12
CMDA[30..0] F2 MDA8 F2 MDA5
4,19,20,21> CMDA[30..0] CMDA7 N3 DQL2 F8 MDA15 CMDA7 N3 DQL2 F8 MDA0 Group0
A0 DQL3 A0 DQL3 CMD8 A8 A8 A8 A8
CMDA10 P7 H3 MDA13 Group1 CMDA10 P7 H3 MDA4
CMDA24 P3 A1 DQL4 H8 MDA11 CMDA24 P3 A1 DQL4 H8 MDA2
A2 DQL5 A2 DQL5 CMD9 A12 A12 A0 A0
CMDA6 N2 G2 MDA10 CMDA6 N2 G2 MDA7
CMDA22 P8 A3 DQL6 H7 MDA14 CMDA22 P8 A3 DQL6 H7 MDA3
A4 DQL7 A4 DQL7 CMD10 A1 A1 A2 A2
CMDA26 P2 CMDA26 P2
+VRAM_1.5VS CMDA5 R8 A5 CMDA5 R8 A5
A6 A6 CMD11 RAS# RAS# RAS# RAS#
CMDA21 R2 D7 MDA18 CMDA21 R2 D7 MDA30
CMDA8 T8 A7 DQU0 C3 MDA22 CMDA8 T8 A7 DQU0 C3 MDA26
A8 DQU1 A8 DQU1 CMD12 A13 A13 A14 A14
1

CMDA4 R3 C8 MDA16 CMDA4 R3 C8 MDA29


CMDA25 L7 A9 DQU2 C2 MDA23 CMDA25 L7 A9 DQU2 C2 MDA24 Group3
RV55
A10/AP DQU3 A10/AP DQU3 CMD13 BA1 BA1 A3 A3
1K_0402_1% CMDA23 R7 A7 MDA17 Group2 CMDA23 R7 A7 MDA28
CMDA9 N7 A11 DQU4 A2 MDA20 CMDA9 N7 A11 DQU4 A2 MDA27
OPT@
A12 DQU5 A12 DQU5 CMD14 A14 A14 A13 A13
CMDA12 T3 B8 MDA19 CMDA12 T3 B8 MDA31
2

+MEM_VREF_CA0 CMDA14 T7 A13 DQU6 A3 MDA21 CMDA14 T7 A13 DQU6 A3 MDA25


+MEM_VREF_CA0 A14 DQU7 A14 DQU7 CMD15 CAS# CAS# CAS# CAS#
M7 M7
A15/BA3 A15/BA3
1

+VRAM_1.5VS +VRAM_1.5VS CMD16 ODT ODT


1
RV56 CV63
1K_0402_1% 0.01U_0402_25V7K CMDA29 M2 B2 CMDA29 M2 B2 CMD17 CS1#
OPT@ OPT@ CMDA13 N8 BA0 VDD D9 CMDA13 N8 BA0 VDD D9
2 CMDA27 M3 BA1 VDD G7 CMDA27 M3 BA1 VDD G7 CMD18 CS0#
2

BA2 VDD K2 BA2 VDD K2


VDD K8 VDD K8
VDD VDD CMD19 CKE CKE
N1 N1
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9
C CK VDD CK VDD CMD20 RST RST RST RST C
CLKA0# K7 R1 CLKA0# K7 R1
CMDA3 K9 CK VDD R9 CMDA3 K9 CK VDD R9
+VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
CMD21 A7 A7 A6 A6
CMD22 A4 A4 A5 A5
CMDA0 K1 A1 CMDA0 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
1

CMDA2 L2 A8 CMDA2 L2 A8 CMD23 A11 A11 A9 A9


RV57 CMDA11 J3 CS/CS0 VDDQ C1 CMDA11 J3 CS/CS0 VDDQ C1
CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
1K_0402_1%
CAS VDDQ CAS VDDQ CMD24 A2 A2 A1 A1
OPT@ CMDA28 L3 D2 CMDA28 L3 D2
WE VDDQ E9 WE VDDQ E9
310mAVDDQ CMD25 A10 A10 WE# WE#
2

+MEM_VREF_DQ0 F1 VDDQ F1
+MEM_VREF_DQ0
DQSA1 F3 VDDQ H2 DQSA0 F3
310mAVDDQ H2
DQSL VDDQ DQSL VDDQ CMD26 A5 A5 A4 A4
1

1 DQSA2 C7 H9 DQSA3 C7 H9
DQSU VDDQ DQSU VDDQ
RV58 CV64 CMD27 BA2 BA2
1K_0402_1% 0.01U_0402_25V7K
OPT@ OPT@ DQMA1 E7 A9 DQMA0 E7 A9 CMD28 WE# WE# A10 A10
2 DQMA2 D3 DML VSS B3 DQMA3 D3 DML VSS B3
2

DMU VSS E1 DMU VSS E1


VSS VSS CMD29 BA0 BA0 BA0 BA0
G8 G8
DQSA#1 G3 VSS J2 DQSA#0 G3 VSS J2
DQSL VSS DQSL VSS CMD30 BA2 BA2
DQSA#2 B7 J8 DQSA#3 B7 J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
CMDA20 T2 VSS P9 CMDA20 T2 VSS P9
RESET VSS T1 RESET VSS T1
ZQ0 L8 VSS T9 ZQ1 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
OPT@ J1 B1 OPT@ J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV60 RV61 Place close to the first T point
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
B L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8 B
2

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8 <14,20> CLKA0
VSSQ VSSQ

1
F9 F9
VSSQ G1 VSSQ G1 OPT@
VSSQ G9 VSSQ G9 RV63
VSSQ VSSQ 160_0402_1%
96-BALL 96-BALL

2
SDRAM DDR3 SDRAM DDR3
<14,20> CLKA0#
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

Place close to RANK0 VRAM

+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS

22U_0805_6.3V6M
0.1U_0402_10V7K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPT@ CV75

OPT@ CV77
OPT@ CV67

OPT@ CV68

OPT@ CV70

OPT@ CV71

OPT@ CV73

OPT@ CV74

OPT@ CV76

OPT@ CV78

OPT@ CV79

OPT@ CV80

OPT@ CV83

OPT@ CV84

OPT@ CV85

OPT@ CV86

OPT@ CV87
OPT@ CV69

OPT@ CV72

OPT@ CV81

OPT@ CV82
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x VRAM RANK 0L
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 18 of 56
5 4 3 2 1
5 4 3 2 1

RANK 0 [63...32] Rank 0 Rank 1


Mode E
VRAM DDR3 Chips Address
CMD0
0..31
ODT
32..63 0..31
ODT
32..63

CMD1 CS1#
CMD2 CS0#
DQSA[7..4] CMD3 CKE CKE
<14,21> DQSA[7..4]
DQSA#[7..4] CMD4 A9 A9 A11 A11
D <14,21> DQSA#[7..4] D
DQMA[7..4] UV5 @ UV6 @ CMD5 A6 A6 A7 A7
<14,21> DQMA[7..4]
MDA[63..32] +MEM_VREF_CA1 M8 E3 MDA35 +MEM_VREF_CA1 M8 E3 MDA45 CMD6 A3 A3 BA1 BA1
<14,21> MDA[63..32] +MEM_VREF_DQ1 H1 VREFCA DQL0 F7 MDA37 +MEM_VREF_DQ1 H1 VREFCA DQL0 F7 MDA41
CMDA[30..0] VREFDQ DQL1 F2 MDA32 VREFDQ DQL1 F2 MDA46
<14,18,20,21> CMDA[30..0] DQL2 DQL2 CMD7 A0 A0 A12 A12
CMDA7 N3 F8 MDA36 CMDA7 N3 F8 MDA40
CMDA10 P7 A0 DQL3 H3 MDA33 Group4 CMDA10 P7 A0 DQL3 H3 MDA44 Group5
A1 DQL4 A1 DQL4 CMD8 A8 A8 A8 A8
CMDA24 P3 H8 MDA38 CMDA24 P3 H8 MDA43
CMDA6 N2 A2 DQL5 G2 MDA34 CMDA6 N2 A2 DQL5 G2 MDA47
A3 DQL6 A3 DQL6 CMD9 A12 A12 A0 A0
CMDA22 P8 H7 MDA39 CMDA22 P8 H7 MDA42
CMDA26 P2 A4 DQL7 CMDA26 P2 A4 DQL7
A5 A5 CMD10 A1 A1 A2 A2
CMDA5 R8 CMDA5 R8
+VRAM_1.5VS CMDA21 R2 A6 D7 MDA58 CMDA21 R2 A6 D7 MDA54
A7 DQU0 A7 DQU0 CMD11 RAS# RAS# RAS# RAS#
CMDA8 T8 C3 MDA62 CMDA8 T8 C3 MDA50
CMDA4 R3 A8 DQU1 C8 MDA56 CMDA4 R3 A8 DQU1 C8 MDA55
A9 DQU2 A9 DQU2 CMD12 A13 A13 A14 A14
1

CMDA25 L7 C2 MDA63 CMDA25 L7 C2 MDA48


CMDA23 R7 A10/AP DQU3 A7 MDA57 Group7 CMDA23 R7 A10/AP DQU3 A7 MDA53 Group6
RV59
A11 DQU4 A11 DQU4 CMD13 BA1 BA1 A3 A3
1K_0402_1% CMDA9 N7 A2 MDA61 CMDA9 N7 A2 MDA51
CMDA12 T3 A12 DQU5 B8 MDA59 CMDA12 T3 A12 DQU5 B8 MDA52
OPT@
A13 DQU6 A13 DQU6 CMD14 A14 A14 A13 A13
CMDA14 T7 A3 MDA60 CMDA14 T7 A3 MDA49
2

+MEM_VREF_CA1 M7 A14 DQU7 M7 A14 DQU7


+MEM_VREF_CA1 A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD15 CAS# CAS# CAS# CAS#
1

1 CMD16 ODT ODT


RV62 CV65 CMDA29 M2 B2 CMDA29 M2 B2
CMDA13 N8 BA0 VDD D9 CMDA13 N8 BA0 VDD D9
1K_0402_1% 0.01U_0402_25V7K
BA1 VDD BA1 VDD CMD17 CS1#
OPT@ OPT@ CMDA27 M3 G7 CMDA27 M3 G7
2 BA2 VDD K2 BA2 VDD K2 CMD18 CS0#
2

VDD K8 VDD K8
VDD N1 VDD N1
VDD VDD CMD19 CKE CKE
CLKA1 J7 N9 CLKA1 J7 N9
CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
C CK VDD CK VDD CMD20 RST RST RST RST C
CMDA19 K9 R9 CMDA19 K9 R9
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
+VRAM_1.5VS
CMD21 A7 A7 A6 A6
CMDA16 K1 A1 CMDA16 K1 A1 CMD22 A4 A4 A5 A5
CMDA18 L2 ODT/ODT0 VDDQ A8 CMDA18 L2 ODT/ODT0 VDDQ A8
CS/CS0 VDDQ CS/CS0 VDDQ
1

CMDA11 J3 C1 CMDA11 J3 C1 CMD23 A11 A11 A9 A9


RV64 CMDA15 K3 RAS VDDQ C9 CMDA15 K3 RAS VDDQ C9
CMDA28 L3 CAS VDDQ D2 CMDA28 L3 CAS VDDQ D2
1K_0402_1%
WE VDDQ WE VDDQ CMD24 A2 A2 A1 A1
OPT@ 310mAVDDQ E9 310mAVDDQ E9
F1 F1 CMD25 A10 A10 WE# WE#
2

+MEM_VREF_DQ1 DQSA4 F3 VDDQ H2 DQSA5 F3 VDDQ H2


+MEM_VREF_DQ1 DQSL VDDQ DQSL VDDQ
DQSA7 C7 H9 DQSA6 C7 H9 CMD26 A5 A5 A4 A4
DQSU VDDQ DQSU VDDQ
1

1
RV65 CV66 CMD27 BA2 BA2
1K_0402_1% 0.01U_0402_25V7K DQMA4 E7 A9 DQMA5 E7 A9
DQMA7 D3 DML VSS B3 DQMA6 D3 DML VSS B3
OPT@
2
OPT@
DMU VSS DMU VSS CMD28 WE# WE# A10 A10
E1 E1
2

VSS G8 VSS G8
VSS VSS CMD29 BA0 BA0 BA0 BA0
DQSA#4 G3 J2 DQSA#5 G3 J2
DQSA#7 B7 DQSL VSS J8 DQSA#6 B7 DQSL VSS J8
DQSU VSS DQSU VSS CMD30 BA2 BA2
M1 M1
VSS M9 VSS M9
VSS P1 VSS P1
CMDA20 T2 VSS P9 CMDA20 T2 VSS P9
RESET VSS T1 RESET VSS T1
ZQ2 L8 VSS T9 ZQ3 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
OPT@
OPT@ J1 B1 RV72 J1 B1
L1 NC/ODT1 VSSQ B9 L1 NC/ODT1 VSSQ B9
RV71
NC/CS1 VSSQ
243_0402_1%
NC/CS1 VSSQ
Place close to the first T point
243_0402_1% J9 D1 J9 D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
2

2
B NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 B
VSSQ E8 VSSQ E8 <14,21> CLKA1
VSSQ VSSQ

1
F9 F9
VSSQ G1 VSSQ G1 OPT@
VSSQ G9 VSSQ G9 RV74
VSSQ VSSQ 160_0402_1%
96-BALL 96-BALL

2
SDRAM DDR3 SDRAM DDR3
<14,21> CLKA1#
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

Place close to RANK1 VRAM

+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS

22U_0805_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
0.1U_0402_10V7K

0.1U_0402_10V7K
OPT@ CV109
OPT@ CV100

OPT@ CV101

OPT@ CV103

OPT@ CV104

OPT@ CV105

OPT@ CV106

OPT@ CV108

OPT@ CV111

DRANK@ CV112
OPT@ CV102

OPT@ CV107

OPT@ CV110
OPT@ CV93
OPT@ CV92

OPT@ CV95

OPT@ CV97

OPT@ CV98

OPT@ CV99
OPT@ CV94

OPT@ CV96
1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x VRAM RANK 0H
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 19 of 56
5 4 3 2 1
5 4 3 2 1

RANK 1 [31...0] Rank 0 Rank 1


Mode E
VRAM DDR3 Chips Address
CMD0
0..31
ODT
32..63 0..31
ODT
32..63

CMD1 CS1#
CMD2 CS0#
CMD3 CKE CKE
DQSA[3..0]
<14,18> DQSA[3..0]
CMD4 A9 A9 A11 A11
D DQSA#[3..0] D
<14,18> DQSA#[3..0]
CMD5 A6 A6 A7 A7
DQMA[3..0]
<14,18> DQMA[3..0]
CMD6 A3 A3 BA1 BA1
MDA[31..0]
<14,18> MDA[31..0]
DRANK@ CMD7 A0 A0 A12 A12
CMDA[30..0] 0.01U_0402_25V7K
<14,18,19,21> CMDA[30..0] 2 1 UV7 @ UV8 @ CMD8 A8 A8 A8 A8
CV88
M8 E3 MDA12 M8 E3 MDA1 CMD9 A12 A12 A0 A0
+MEM_VREF_CA0 +MEM_VREF_CA0
H1 VREFCA DQL0 F7 MDA9 H1 VREFCA DQL0 F7 MDA6
+MEM_VREF_DQ0 VREFDQ DQL1 +MEM_VREF_DQ0 VREFDQ DQL1
F2 MDA15 F2 MDA0 CMD10 A1 A1 A2 A2
CMDA9 N3 DQL2 F8 MDA8 CMDA9 N3 DQL2 F8 MDA5
1
CMDA24 P7 A0 DQL3 H3 MDA14 Group1 CV89 CMDA24 P7 A0 DQL3 H3 MDA3 Group0 CMD11 RAS# RAS# RAS# RAS#
CMDA10 P3 A1 DQL4 H8 MDA10 0.01U_0402_25V7K CMDA10 P3 A1 DQL4 H8 MDA7
CMDA13 N2 A2 DQL5 G2 MDA11 DRANK@ CMDA13 N2 A2 DQL5 G2 MDA2 CMD12 A13 A13 A14 A14
CMDA26 P8 A3 DQL6 H7 MDA13 2 CMDA26 P8 A3 DQL6 H7 MDA4
CMDA22 P2 A4 DQL7 CMDA22 P2 A4 DQL7
CMD13 BA1 BA1 A3 A3
CMDA21 R8 A5 CMDA21 R8 A5
CMDA5 R2 A6 D7 MDA22 CMDA5 R2 A6 D7 MDA26 CMD14 A14 A14 A13 A13
CMDA8 T8 A7 DQU0 C3 MDA18 CMDA8 T8 A7 DQU0 C3 MDA30
CMDA23 R3 A8 DQU1 C8 MDA23 CMDA23 R3 A8 DQU1 C8 MDA24
DQU2 CMD15 CAS# CAS# CAS# CAS#
CMDA28 L7 A9 DQU2 C2 MDA16 CMDA28 L7 A9 C2 MDA29
CMDA4 R7 A10/AP DQU3 A7 MDA21 Group2 CMDA4 R7 A10/AP DQU3 A7 MDA25 Group3
DQU4 CMD16 ODT ODT
CMDA7 N7 A11 DQU4 A2 MDA19 CMDA7 N7 A11 A2 MDA31
CMDA14 T3 A12 DQU5 B8 MDA20 CMDA14 T3 A12 DQU5 B8 MDA27 CMD17 CS1#
CMDA12 T7 A13 DQU6 A3 MDA17 CMDA12 T7 A13 DQU6 A3 MDA28
M7 A14 DQU7 M7 A14 DQU7
CMD18 CS0#
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD19 CKE CKE
CMDA29 M2 B2 CMDA29 M2 B2
CMDA6 N8 BA0 VDD D9 CMDA6 N8 BA0 VDD D9
C BA1 VDD BA1 VDD CMD20 RST RST RST RST C
CMDA30 M3 G7 CMDA30 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD CMD21 A7 A7 A6 A6
K8 K8
VDD N1 VDD N1
VDD VDD CMD22 A4 A4 A5 A5
J7 N9 CLKA0 J7 N9
<14,18> CLKA0 K7 CK VDD R1 CLKA0# K7 CK VDD R1
<14,18> CLKA0# CK VDD CK VDD CMD23 A11 A11 A9 A9
CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CMD24 A2 A2 A1 A1
CMDA0 K1 A1 CMDA0 K1 A1 CMD25 A10 A10 WE# WE#
CMDA1 L2 ODT/ODT0 VDDQ A8 CMDA1 L2 ODT/ODT0 VDDQ A8
CMDA11 J3 CS/CS0 VDDQ C1 CMDA11 J3 CS/CS0 VDDQ C1
RAS VDDQ RAS VDDQ CMD26 A5 A5 A4 A4
CMDA15 K3 C9 CMDA15 K3 C9
CMDA25 L3 CAS VDDQ D2 CMDA25 L3 CAS VDDQ D2
WE VDDQ WE VDDQ CMD27 BA2 BA2
E9 E9
310mAVDDQ F1
310mAVDDQ F1
VDDQ VDDQ CMD28 WE# WE# A10 A10
DQSA1 F3 H2 DQSA0 F3 H2
DQSA2 C7 DQSL VDDQ H9 DQSA3 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ CMD29 BA0 BA0 BA0 BA0
CMD30 BA2 BA2
DQMA1 E7 A9 DQMA0 E7 A9
DQMA2 D3 DML VSS B3 DQMA3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
DQSA#1 G3 VSS J2 DQSA#0 G3 VSS J2
DQSA#2 B7 DQSL VSS J8 DQSA#3 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
CMDA20 T2 VSS P9 CMDA20 T2 VSS P9
RESET VSS T1 RESET VSS T1
ZQ4 L8 VSS T9 ZQ5 L8 VSS T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B

1
1

J1 B1 J1 B1
L1 NC/ODT1 VSSQ B9 RV78 L1 NC/ODT1 VSSQ B9
RV77 J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8

2
NCZQ1 VSSQ E2 DRANK@ NCZQ1 VSSQ E2
2

DRANK@ VSSQ E8 VSSQ E8


VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x VRAM RANK 1L
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 20 of 56
5 4 3 2 1
5 4 3 2 1

Rank 0 Rank 1
RANK 1 [63...32] Mode E
0..31 32..63 0..31 32..63
Address

VRAM DDR3 Chips CMD0


CMD1
ODT ODT
CS1#
CMD2 CS0#
CMD3 CKE CKE
DQSA[7..4]
<14,19> DQSA[7..4]
CMD4 A9 A9 A11 A11
DQSA#[7..4]
D <14,19> DQSA#[7..4] D
CMD5 A6 A6 A7 A7
DQMA[7..4]
<14,19> DQMA[7..4]
CMD6 A3 A3 BA1 BA1
MDA[63..32]
<14,19> MDA[63..32]
CMD7 A0 A0 A12 A12
CMDA[30..0]
4,18,19,20> CMDA[30..0]
DRANK@ CMD8 A8 A8 A8 A8
0.01U_0402_25V7K
2 1 UV9 @ UV10 @ CMD9 A12 A12 A0 A0
CV90
M8 E3 MDA37 M8 E3 MDA41 CMD10 A1 A1 A2 A2
+MEM_VREF_CA1 +MEM_VREF_CA1
H1 VREFCA DQL0 F7 MDA35 H1 VREFCA DQL0 F7 MDA45
+MEM_VREF_DQ1 VREFDQ DQL1 +MEM_VREF_DQ1 VREFDQ DQL1
F2 MDA36 F2 MDA40 CMD11 RAS# RAS# RAS# RAS#
CMDA9 N3 DQL2 F8 MDA32 CMDA9 N3 DQL2 F8 MDA46
1
CMDA24 P7 A0 DQL3 H3 MDA39 Group4 CV91 CMDA24 P7 A0 DQL3 H3 MDA42 Group5 CMD12 A13 A13 A14 A14
CMDA10 P3 A1 DQL4 H8 MDA34 0.01U_0402_25V7K CMDA10 P3 A1 DQL4 H8 MDA47
CMDA13 N2 A2 DQL5 G2 MDA38 DRANK@ CMDA13 N2 A2 DQL5 G2 MDA43 CMD13 BA1 BA1 A3 A3
CMDA26 P8 A3 DQL6 H7 MDA33 2 CMDA26 P8 A3 DQL6 H7 MDA44
CMDA22 P2 A4 DQL7 CMDA22 P2 A4 DQL7
CMD14 A14 A14 A13 A13
CMDA21 R8 A5 CMDA21 R8 A5
CMDA5 R2 A6 D7 MDA62 CMDA5 R2 A6 D7 MDA50 CMD15 CAS# CAS# CAS# CAS#
CMDA8 T8 A7 DQU0 C3 MDA58 CMDA8 T8 A7 DQU0 C3 MDA54
CMDA23 R3 A8 DQU1 C8 MDA63 CMDA23 R3 A8 DQU1 C8 MDA48 CMD16 ODT ODT
CMDA28 L7 A9 DQU2 C2 MDA56 CMDA28 L7 A9 DQU2 C2 MDA55
CMDA4 R7 A10/AP DQU3 A7 MDA60 Group7 CMDA4 R7 A10/AP DQU3 A7 MDA49 Group6 CMD17 CS1#
CMDA7 N7 A11 DQU4 A2 MDA59 CMDA7 N7 A11 DQU4 A2 MDA52
CMDA14 T3 A12 DQU5 B8 MDA61 CMDA14 T3 A12 DQU5 B8 MDA51 CMD18 CS0#
CMDA12 T7 A13 DQU6 A3 MDA57 CMDA12 T7 A13 DQU6 A3 MDA53
M7 A14 DQU7 M7 A14 DQU7
CMD19 CKE CKE
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD20 RST RST RST RST
CMDA29 M2 B2 CMDA29 M2 B2
C CMDA6 N8 BA0 VDD D9 CMDA6 N8 BA0 VDD D9 C
BA1 VDD BA1 VDD CMD21 A7 A7 A6 A6
CMDA30 M3 G7 CMDA30 M3 G7
BA2 VDD K2 BA2 VDD K2
VDD VDD CMD22 A4 A4 A5 A5
K8 K8
VDD N1 VDD N1
VDD VDD CMD23 A11 A11 A9 A9
J7 N9 CLKA1 J7 N9
<14,19> CLKA1 K7 CK VDD R1 CLKA1# K7 CK VDD R1
<14,19> CLKA1# CK VDD CK VDD CMD24 A2 A2 A1 A1
CMDA19 K9 R9 CMDA19 K9 R9
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CMD25 A10 A10 WE# WE#
CMDA16 K1 A1 CMDA16 K1 A1 CMD26 A5 A5 A4 A4
CMDA17 L2 ODT/ODT0 VDDQ A8 CMDA17 L2 ODT/ODT0 VDDQ A8
CMDA11 J3 CS/CS0 VDDQ C1 CMDA11 J3 CS/CS0 VDDQ C1
RAS VDDQ RAS VDDQ CMD27 BA2 BA2
CMDA15 K3 C9 CMDA15 K3 C9
CMDA25 L3 CAS VDDQ D2 CMDA25 L3 CAS VDDQ D2
WE VDDQ WE VDDQ CMD28 WE# WE# A10 A10
310mAVDDQ E9 E9
F1 VDDQ F1
VDDQ 310mAVDDQ CMD29 BA0 BA0 BA0 BA0
DQSA4 F3 H2 DQSA5 F3 H2
DQSA7 C7 DQSL VDDQ H9 DQSA6 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ CMD30 BA2 BA2

DQMA4 E7 A9 DQMA5 E7 A9
DQMA7 D3 DML VSS B3 DQMA6 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
DQSA#4 G3 VSS J2 DQSA#5 G3 VSS J2
DQSA#7 B7 DQSL VSS J8 DQSA#6 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
CMDA20 T2 VSS P9 CMDA20 T2 VSS P9
RESET VSS T1 RESET VSS T1
B ZQ6 L8 VSS T9 ZQ7 L8 VSS T9 B
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1
RV79 L1 NC/ODT1 VSSQ B9 RV80 L1 NC/ODT1 VSSQ B9
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
DRANK@ L9 NC/CE1 VSSQ D8 DRANK@ L9 NC/CE1 VSSQ D8
2

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_N14x VRAM RANK 1H
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 11, 2013 Sheet 21 of 56
5 4 3 2 1
A B C D E

For eDP Panel LCD POWER CIRCUIT


CAM_EMI@ eDP&LVDS both 3V power rail
USB20_N11_R 1 2 USB20_N11 <29>
1 2
+3VS
IEDP@ USB20_P11_R 4 3 USB20_P11 <29>
C890 1 20.1U_0402_10V7K LVDS_EDID_CLK 4 3 +LCD_VDD
<6> H_EDP_AUXP
IEDP@
W=60mils W=60mils
L55 WCM-2012-900T_0805 U16
C891 1 20.1U_0402_10V7K LVDS_EDID_DATA 1.5A 1 +LCD_VDD_OUT 1 Rshort@ 2 I rush=1.5A
<6> H_EDP_AUXN VOUT
IEDP@ Reserve for EMI request 5 R106 0_0805_5%
1 C912 1 20.1U_0402_10V7K LVDS_TXOUT0+ VIN 1
<6> H_EDP_TXP0
IEDP@ 2
C913 1 20.1U_0402_10V7K LVDS_TXOUT0- +LCD_VDD_SS 4 GND
<6> H_EDP_TXN0 SS
IEDP@
C914 1 20.1U_0402_10V7K LVDS_TXOUT1+ 1 2 3
<6> H_EDP_TXP1 EN
IEDP@ R267 0_0402_5%

1
C915 1 20.1U_0402_10V7K LVDS_TXOUT1- @TOUCH_EMI@ APL3512ABI-TRG_SOT23-5
<6> H_EDP_TXN1
C7
TOUCH_EMI@ 0.015U_0402_50V7K

2
USB20_P8_R 1 2 USB20_P8 <29>
1 2
<28> LCD_ENVDD

2
USB20_N8_R 4 3 USB20_N8 <29>
4 3 R112
L57 WCM-2012-900T_0805 100K_0402_5%

1 2

1
R266 0_0402_5%
@TOUCH_EMI@

Reserve for EMI request

For LVDS 1ch Panel LVDS colay eDP cable


1 LVDS@ 2 LVDS_TXOUT0+
<28> LCD_TXOUT0+
R262 0_0402_5%
2 1 LVDS@ 2 LVDS_TXOUT0- 2
<28> LCD_TXOUT0-
R263 0_0402_5%
1 LVDS@ 2 LVDS_TXOUT1+ +5VS
<28> LCD_TXOUT1+
R265 0_0402_5%
1 LVDS@ 2 LVDS_TXOUT1- JLVDS
<28> LCD_TXOUT1-
R264 0_0402_5% 1 +5VS_LVDS_TOUCH 1 Rshort@ 2 20mils
<28> LCD_TXOUT2+
LCD_TXOUT2+ pin1-4 Touch function for panel 1 2 USB20_N8_R R390 0_0603_5%
2 3 USB20_P8_R
LCD_TXOUT2- 3 4 BKOFF#
<28> LCD_TXOUT2- 4 5 INT_MIC_DATA
LCD_TXCLK+ 5 6 INT_MIC_CLK INT_MIC_DATA <39>
<28> LCD_TXCLK+ pin5-10 For Webcam with single or dual MIC 6 7 INT_MIC_CLK <39>
LCD_TXCLK- 7 8 USB20_P11_R +3VS
<28> LCD_TXCLK- 8 9 USB20_N11_R
1 LVDS@ 2 LVDS_EDID_CLK 9 10 +3VS_LVDS_CAM 1 Rshort@ 2
<28> LCD_EDID_CLK 10 20mils
R300 0_0402_5% 11 +LCD_VDD R389 0_0603_5%
1 LVDS@ 2 LVDS_EDID_DATA 11 12 +3VS
<28> LCD_EDID_DATA pin11-30 For LVDS or EDP panel 12 +LCD_VDD Irush=1.5A 60mils
R299 0_0402_5% 13 +3VS
13 14 LVDS_EDID_CLK
14 15 LVDS_EDID_DATA
15 16 LVDS_TXOUT0-
16 17 LVDS_TXOUT0+
17 18 LVDS_TXOUT1-
18 19 LVDS_TXOUT1+
19 20 LCD_TXOUT2-
20 21 LCD_TXOUT2+
21 22
22 23 LCD_TXCLK-
23 24 LCD_TXCLK+
24 25
25 26 LED_PWM CPU_EDP_HPD <6>
26 27 BKOFF#_R
3 27 28 3
28 29
29 30
30 +LCD_INV Irush=1.5A 60mils
31
GND 32
GND 33
GND 34
GND 35
GND B+
Irush=1.5A 60mils
Conn@ +LCD_INV
L2
Reserve for eDP panel potential issue 2 1
FBMA-L11-201209-221LMA30T_0805
+3VS EMI@

IEDP@1 2 IEDP@
5

R103 0_0402_5% U17 LED_PWM 1 2


PCH_PWM <28>
1 RB751V40_SC76-2 D17
P

BKOFF#_R 1 2 4 IN1 EC_ENBKL <28,41>


D15 RB751V40_SC76-2 O 2
IN2 BKOFF# <41>
G

1
LVDS@
1

R131
3

R113 SN74AHC1G08DCKR_SC70-5 47K_0402_5%


10K_0402_5%

2
2

1 2
R147 0_0402_5%
4 LVDS@ 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/12/07 Deciphered Date 2013/12/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VFKAA
Date: Monday, March 11, 2013 Sheet 22 of 56
A B C D E
A B C D E

CRT CONNECTOR
1 1

T65, T66: for ATE


L3 1 2 NBQ100505T-800Y_0402 CRT_R_L JCRT
<28> UMA_CRT_R
CRT_EMI@ 6
L4 1 2 NBQ100505T-800Y_0402 CRT_G_L 11
<28> UMA_CRT_G T65 PAD
CRT_EMI@ CRT_R_L 1
L5 1 2 NBQ100505T-800Y_0402 CRT_B_L 7
<28> UMA_CRT_B
CRT_EMI@ CRT_DDC_DAT 12
CRT_G_L 2
CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ 8
HSYNC 13

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
R138 R139 R140 CRT_B_L 3

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 9
+HDMI_5V_OUT

1
VSYNC 14 16
G
C238 C239 C240 C241 C242 C243 4 17
T66 PAD G
10
2 2 2 2 2 2 CRT_DDC_CLK 15
USE HDMI POWER 5

2
C-H_13-12201513CP
Conn@

2 2

CRT@
U49 +HDMI_5V_OUT
1 8 1 2
+HDMI_5V_OUT VCC_SYNC BYP C15 0.22U_0402_16V7K

2 3 CRT_R_L
+3VS VCC_VIDEO