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By ALEJANDRO MONTENEGRO LEÓN
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2005
Copyright 2005 by Alejandro Montenegro León
To my brother
ACKNOWLEDGMENTS I would like to first express my gratitude to Charles Edwards, the principle engineer at S&C Electric Co. (Chicago, IL) for his patience and the knowledge he shared throughout the project. I would also like to acknowledge Kenneth Mattern (manager at S&C Electric Co., Power Quality Division) for his constant encouragement and confidence in my ability. I am grateful to S&C Electric Company in general for all of their contribution and concern. Additionally, I would like to thank Alexander Domijan (my supervisory committee chair) for his funding during my graduate studies. My gratitude also goes to my supervisory committee (Dr. Ngo, Dr. Arroyo, and Dr. Goswami) for all of their time and effort. I would furthermore like to acknowledge my family in Spain, for supporting me and believing in me throughout my stay in the United States. I would finally like to express my love and gratitude to my girlfriend, Andrea Victoriano, for her help with the proofreading and for always being the shoulder I could lean on throughout the project
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TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................................................................................. iv LIST OF TABLES........................................................................................................... viii LIST OF FIGURES ........................................................................................................... ix ABSTRACT.................................................................................................................... xvii CHAPTER 1 INTRODUCTION ........................................................................................................1 WindEnergy Outlook ..................................................................................................1 Electrical Issues ............................................................................................................3 Solutions to WindPower Fluctuations.........................................................................9 State of the Art..............................................................................................................9 Objective.....................................................................................................................11 2 SYSTEM DESIGN.....................................................................................................14 Introduction.................................................................................................................14 Control Scheme ..........................................................................................................14 Positive Sequence Calculation ............................................................................14 Real Power Calculation Using dq Components ..................................................20 Phase Locked Loop .............................................................................................21 Control Algorithm Design...................................................................................26 Inner regulators ............................................................................................27 Outer regulators............................................................................................35 PerUnit System Model ..............................................................................................56 Inverter OutputFilter Design ..............................................................................56 Harmonic content .........................................................................................57 Switching frequency.....................................................................................60 Passive filter design......................................................................................61 Passive filter damping ..................................................................................65 DirectCurrent Link Capacitor Design ................................................................68 Energy Storage Design ........................................................................................69 Chopper Inductor Design ....................................................................................71 PerUnit System Model Summary.......................................................................72 Simulated Model.........................................................................................................73 v
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SYSTEM DESCRIPTION..........................................................................................78 System Overview........................................................................................................78 Electrical Network Model...........................................................................................80 Synchronous Machine .........................................................................................80 Voltage regulation ...............................................................................................81 Prime Mover........................................................................................................81 Synchronous Machine Control Algorithm ..........................................................83 WindFarm Model ......................................................................................................87 WindFarm Control Algorithm............................................................................90 WindFarm PowerFactor Correction..................................................................90 WindFarm SoftStart System .............................................................................94 Power Stabilizer..........................................................................................................97 PowerStabilizer Hardware Description..............................................................97 Interface board..............................................................................................99 Digital signal processor..............................................................................105 Fieldprogrammable gate array ..................................................................106 Intelligent power module ...........................................................................107 Isolation interface circuit............................................................................108 Power Stabilizer Software Description .............................................................108 Description of DSP program ......................................................................109 FPGA program description ........................................................................114
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SYSTEM PERFORMANCE ....................................................................................121 System Data ..............................................................................................................121 Power Stabilizer Transient Response .......................................................................121 DirectCurrent Link Voltage Control ................................................................121 Reactive Current Control...................................................................................123 Passive Filter Performance .......................................................................................126 Voltage Regulation ...................................................................................................127 System Losses...........................................................................................................128 Power Limiter Results ..............................................................................................130 Power Limiter 1 (High Pass Filter) ...................................................................131 Power Limiter 1 (Adaptive High Pass Filter)....................................................136 Power Limiter 2.................................................................................................138 Power Limiters Comparison Study...........................................................................145
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SUMMARY..............................................................................................................148 Conclusions...............................................................................................................148 Further Work ............................................................................................................150
APPENDIX A B MATHEMATICAL TRANSFORMATIONS..........................................................151 MATLAB CODES ...................................................................................................158 vi
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POWER STABILIZER CONTROL MODULES ....................................................168
LIST OF REFERENCES.................................................................................................172 BIOGRAPHICAL SKETCH ...........................................................................................176
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LIST OF TABLES Table 11 12 13 14 15 21 22 23 24 25 26 27 28 29 31 32 33 41 A1 C1 page Technical specifications of IEC and IEEE ................................................................4 Windfarm outputpower requirements.....................................................................8 Largescale windpower outputleveling projects...................................................10 Conceptual windpower filtering projects...............................................................12 Basic system configurations....................................................................................13 Outer regulator assignation .....................................................................................35 Rateofchange limits or PPA for a 10 MW wind farm ..........................................47 Generalized Harmonics of linetoline voltage .......................................................59 L filter vs. LCL filter...............................................................................................61 LCL filter design .....................................................................................................64 LCL equivalent impedance with damping resistance .............................................65 Perunit system........................................................................................................65 Perunit system parameters .....................................................................................73 Designed system results and simulated system results comparison........................76 Synchronous machine output voltage profile at rated speed...................................82 Alternatives for the power stabilizer controller.....................................................106 FPGA code words .................................................................................................120 System parameters.................................................................................................122 Mathematical transformations summary ...............................................................157 Control Modules....................................................................................................168
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LIST OF FIGURES Figure 11 12 13 14 15 16 21 22 23 24 25 26 27 28 29 page Windpower output for two wind farms during one month. .....................................5 Power fluctuation comparison...................................................................................6 Typical power curve of a wind turbine. ....................................................................6 Windfarm output power vs system frequency. ........................................................7 Control strategies along the power curve ..................................................................8 Windfarm generation buffering concept ................................................................13 Unbalanced system..................................................................................................15 Space vector trajectory of an unbalanced system in the dqo plane ......................16 Space vector trajectory projection over the dq plane.............................................16 Direct and quadrature components of an unbalanced system .................................17 Representation of an unbalanced system in the frequency domain.........................17 Positivesequence extraction algorithm ..................................................................19 Voltage waveforms for an unbalanced fault event..................................................19 Response of the positivesequence extraction algorithm ........................................20 Distortion of phase angle due to a negative sequence component ..........................22
210 PLL diagram............................................................................................................23 211 PLL simplified model..............................................................................................24 212 PLL system step response .......................................................................................25 213 Root locus for two different regulator gains ...........................................................25 214 PLL system response to an unbalanced system condition ......................................26
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215 PLL system response to a frequency excursion ......................................................26 216 System description ..................................................................................................27 217 Simplified system model .........................................................................................28 218 Electrical representation of the dq components ......................................................30 219 System model block diagram ..................................................................................30 220 Inverter current regulatorsystem model block diagram .........................................31 221 Inverter current regulatorsystem model simplified block diagram........................32 222 Simplified current control diagram .........................................................................32 223 Current regulator step response...............................................................................33 224 Chopper equivalent system .....................................................................................34 225 Chopper current controller ......................................................................................35 226 Powers' definition....................................................................................................36 227 System model ..........................................................................................................37 228 DC link equivalent system block diagram ..............................................................37 229 DC link simplified system block diagram...............................................................38 230 DC link voltage regulator step response .................................................................38 231 Simplified system model .........................................................................................40 232 Source impedance voltage drop ..............................................................................41 233 Transfer functions of inverter’s quadrature current component..............................42 234 Transfer functions of inverter’s direct current component......................................42 235 Voltage regulator system block diagram.................................................................44 236 Positive sequence extraction algorithm equivalent system .....................................44 2 37 Voltage regulator detailed block diagram ...............................................................45 2 38 Voltage regulator simplified control diagram .........................................................45 2 39 System response to a 5% change in voltage reference............................................45
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240 Adaptive control scheme .........................................................................................46 241 Power Regulator general control scheme................................................................47 242 Power limiter 1. Control block diagram..................................................................48 243 Power limiter 1. Performance using different cutoff frequencies (unlimited power and energy) ....................................................................................................49 244 Power limiter 1. Performance using different cutoff frequencies (Pinverter=1.0 MW and Einverter=±8.5 MJ) .......................................................................................49 245 Power limiter 2. Limiters details .............................................................................50 246 Power limiter 2. Control block diagram..................................................................51 247 Power limiter 2. Compensation performance.........................................................51 248 Power limiter 2. Inverter response for a sampling time of 2 seconds .....................52 249 Power limiter 2. Inverter response for different power ratings. Sampling time 2 seconds .....................................................................................................................53 250 Power limiter 2. Inverter response for different ESS sizes. Sampling time 2 seconds .....................................................................................................................53 251 Power limiter 3. Control block diagram..................................................................54 252 Power limiter 3. Compensation performance.........................................................55 253 Power limiter 3. Inverter response for a sampling time of 2 seconds .....................55 254 Inverter topology ......................................................................................................57 255 Linetoline and linetoneutral voltage of a three phase inverter...........................57 256 RMS Linetoline voltage harmonic spectrum........................................................58 257 Static Synchronous Generator diagram...................................................................59 258 LCL filter topology .................................................................................................61 259 LCL equivalent block diagram................................................................................62 260 Single phase equivalent filter model at the fundamental frequency .......................62 261 Single phase equivalent filter model at the hth harmonic ........................................63 262 LCL equivalent impedance with damping resistance .............................................66
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263 Single phase harmonic generator equivalent circuits ..............................................66 264 LCL gain frequency response .................................................................................67 265 Inverter frequency analysis .....................................................................................67 266 Capacitor Voltage vs. Energy Storage ....................................................................70 267 ESSChopper topology............................................................................................71 268 Equivalent circuit for maximum current ripple calculation ....................................72 269 System overview .....................................................................................................74 270 Perunit electric system model ................................................................................74 271 Power Stabilizer Control Scheme ...........................................................................75 31 32 33 34 35 36 37 38 39 Equivalent system model ........................................................................................79 DC genset...............................................................................................................83 Two single quadrant chopper circuit .......................................................................83 Synchronous generator control system ...................................................................84 Frequency deviation ................................................................................................85 DCGEN set control scheme ...................................................................................85 System frequency response for Δf=1Hz ................................................................86 Frequency control equivalent system ......................................................................87 Equivalent model frequency response for Δf=  0.01666 pu ..................................88
310 Dynamic model used for transient studies ..............................................................88 311 Static model used for steadystate studies...............................................................88 312 Windfarm model ....................................................................................................89 313 Windfarm controller...............................................................................................90 314 Windfarm power regulator & current regulator step response (ΔP=100%) ..........91 315 Induction generator PQ curve .................................................................................92 316 Windfarm PF correction capacitor bank ................................................................93
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317 PF correction capacitor bank current waveforms....................................................93 318 Capacitor bank impedance frequency scan .............................................................94 319 Machine control scheme operating states................................................................95 320 Electric power system startup ................................................................................96 321 Detail of the transition from startup mode to run mode.........................................96 322 Power Stabilizer system overview ..........................................................................97 323 Interface board overview.......................................................................................100 324 AC voltage scaling circuit (input [1000+1000V], output [0 +3V]) .....................101 325 DC voltage scaling circuit (input [0 +1000V], output [0 +3V]) ...........................101 326 CT current scaling circuit (input [5 +5A], output [0 +3V]).................................101 327 LEM current scaling circuit (input [0.36 +0.36A], output [0 +3V])....................101 328 Power supplies’ voltage monitoring......................................................................102 329 System’s critical signals during turn on ................................................................103 330 System’s critical signals during turn off ...............................................................103 331 Darlington drivers .................................................................................................104 332 IPM status signals interface circuitry ...................................................................104
333 DAC circuit ...........................................................................................................105 334 DSP builtin PWM output performance vs. FPGA ...............................................107 335 IMP power circuit configuration ...........................................................................108 336 Isolated interface board .........................................................................................109 338 Power stabilizer control algorithm sampling rates ................................................110 337 Interconnections between the different subsystems of the power stabilizer........111 339 Power stabilizer control stages..............................................................................113 3 40 Power stabilizer startup sequence ........................................................................113 341 FPGA system overview.........................................................................................116
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342 Up/Down counter. .................................................................................................117 343 PWM generator .....................................................................................................117 344 One phase deadtime generator detailed diagram .................................................119 345 Deadtime generator’s waveforms ........................................................................119 346 Watchdog logic .....................................................................................................120 41 42 43 44 45 46 47 48 49 DC link voltage response for different Kp gains...................................................121 DC link voltage response for different Ki gains ...................................................122 Iqref command step change from 0.5 to 0.5 A per unit. Integral gain effect ........123 Iqref command step change from 0.5 to 0.5 A per unit. Proportional gain effect.......................................................................................................................124 Iq current regulator output for different Kp ..........................................................124 Iqref command step change from 0.5 to 0.5 and back to 0.5 A per unit ............124 Power stabilizer harmonic injection response for Ki=18 and Kp=1 .....................125 Current regulator frequency response ...................................................................126 Frontend inverter current waveform ....................................................................126
410 Frequency spectrum of the LCL currents..............................................................127 411 Simplified system description ...............................................................................127 412 Power stabilizer voltage regulation performance..................................................128 413 Energy storage charge/discharge cycle .................................................................129 414 Control scheme with a losses compensation term.................................................129 415 Power stabilizer equivalent system .......................................................................130 416 Windpower conditions under study .....................................................................130 417 Measured and modeled high pass filter results for Kc=0.0064 W/J, fcut_off=0.005 Hz ......................................................................................................132 419 Measured high pass filter performance for different cutoff frequencies. System parameters Kc=0.0064 W/J.....................................................................................134
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420 Modeled high pass filter performance for different cutoff frequencies. System parameters Kc=0.0064 W/J.....................................................................................135 421 Measured high pass filter performance for different energy storage sizes. System parameters, Kc=0.0064 W/J, fcutoff=0.005 Hz. ..........................................135 422 Cutoff frequency trajectory of the adaptive high pass filter for a given energy deviation .................................................................................................................136 423 Measured adaptive high pass filter performance for different Kf’s. System parameters, Kc=0.0064 W/J, fcutofforigin=0.005 Hz.................................................137 424 Measured adaptive high pass filter performance for different energy storage sizes. .......................................................................................................................137 425 Multiple sampling concept. ...................................................................................139 426. Measured and modeled power limiter 2 results for Kc=0.0064, RR=2 MW/minute, A=0.3 MW/minute, I=1MW/2 seconds fcutoff=0.005 Hz. ................140 427 Measured power indexes activity. System parameters: Kc=0.0064 W/J, RR=2 MW/minute, A=0.3 MW/minute, I=1 MW/2 seconds, and fs=10Hz.....................141 428 Measured power limiter 2 response to different Kc . System parameters: RR=2 MW/minute, A=0.3 MW/minute, I=1MW/2 seconds, and fs=10Hz......................142 429 Measured power limiter 2 response to different ramp rate limits. ........................142 430 Measured power limiter 2 response to different average power fluctuation limits.......................................................................................................................143 431 Effect of linear interpolation on the average power fluctuation index activity. The sampling time of the original windpower data is 2 seconds ..........................144 432 Measured power limiter 2 response to different instantaneous power fluctuation limits.......................................................................................................................144 433 Measured power limiter 2 response to different sampling frequencies.................145 434 Measured synchronous machine output power for the different power limiter control schemes ......................................................................................................146 435 Measured synchronous machine output power for the different power limiter control schemes. .....................................................................................................147 436 Frequency regulator output for the different power limiters.................................147 A1 Relationships among dsqs, and abc axes .............................................................153
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A2 Stationary dsqs components in the time domain .....................................................153 A 3 Relationship among dsqs and drqr axes ...............................................................154 A4 A5 Direct and quadrature components........................................................................155 Time domain representation of abc and dq components .....................................156
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy ADVANCED POWER ELECTRONIC FOR WINDPOWER GENERATION BUFFERING By Alejandro Montenegro León May 2005 Chair: Alexander Domijan, Jr Major Department: Electrical and Computer Engineering As the cost of installing and operating wind generators has dropped, and the cost of conventional fossilfuelbased generation has risen, the economics and political desirability of more windbased energy production has increased. High windpower penetration levels are thus expected to augment in the near future raising the need for additional spinning reserve to counteract the effects of wind variations. This solution is technologically viable, but it has high associated costs. Our study presents a different solution to shortterm windpower variability, using advanced power electronic devices combined with energystorage systems. New control schemes (designed to filter power swings with a minimum of energy) were designed, modeled and verified through experimental tests. We also determined the procedure to extract the corresponding perunit model parameters for simulations and test purposes.
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We first reviewed DQ transformations with emphasis on modeling of the system and control algorithm. System components were then designed using criteria similar to those used to design mediumvoltage power products. We tested a proofofconcept for performance of the power converter in a scaleddown isolated system using real windpower data. Tests were conducted under realistic system conditions of windpenetration level and energystorage levels, to better characterized the impacts and benefits of the Power Stabilizer. We described the scaleddown isolated electric power system used in the testing. We also analyzed the performance of the windfarm model and the synchronous machine’s governor to gain an insight into the model system’s limitations. Simulation results carried out in Mathematical Laboratory (MATLAB) and Power Systems Computer Aided Design (PSCAD) were compared to experimental data to verify the performance of the power converter under different system conditions and algorithms. Power limiters were also contrasted and evaluated for frequency deviations and attenuated power fluctuations. In summary we can say that, among all the power limiters considered in our study, the adaptive high pass filter presented the best performance in terms of system robustness and effectiveness.
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CHAPTER 1 INTRODUCTION WindEnergy Outlook Wind power has been used for at least 3000 years, mainly for milling grain, pumping water, or driving various types of machines. However, the first attempt to use wind turbines for producing electricity date back to the 19th century. In 1891, Poul La Cour in Demark built an experimental wind turbine driving a dynamo. The oil crisis of the 1970s revived interest in wind turbines. Nowadays, the power is the fastest growing source of energy in the world and its growth rates have exceeded 30% annually over the past decade [1]. Cumulative global windenergy generating capacity approached 40,000 MW by the end of 2003 [2][3]. The main drivers for developing of the wind industry in the United States are • Federal Renewable Energy Policies, particularly the Production Tax Credit (PTC) that provides a 1.5 cent per kilowatthour credit for electricity produced from a wind farm during the first 10 years of operation. This wind energy PTC expired December 31, 2003 but will be reinstated through 2005 as part of a major tax package (H.R. 1308). Statelevel renewable energy initiatives, such as the Renewable Portfolio Standard, or green pricing. The Database of State Incentive for Renewable Energy [4] gives more information on incentives. These government initiatives, together with technological advances, plus the need for a new source of energy capable of meeting the world’s growing power demand and the rising prices of conventional fossil fuelbased generation, make the wind power one of the most promising industries in the future.
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2 According to the European Wind Energy Association and Greenpeace, no barriers exist for wind to provide 12% of the world’s electricity by 2020. The American Wind Energy Association forecasts that wind power will provide 6% of the US’s electricity by 2020 if the wind industry maintains an annual growth rate of 18%. The positive effects of using such types of renewable resources are well known. However, windpower plants, like all other energy technology, have some drawbacks that should be mentioned. These problems can be divided into major groups: environmental issues and interconnection issues. Environmental issues. Most significant among these are the following: • Sound from turbines: Some wind turbines built in the early 1980s were very noisy. However, manufactures have been working on making the turbines quieter. Today, an operating wind farm at a distance of 750 to 1,000 feet is no noisier than a moderately quiet room. Research in aeroacoustics is still being carried out to further reduce noise from wind on the blades. Bird death: Wind turbines are often mentioned as a risk to birds, and several international tests have been performed. The general conclusion is that birds are seldom bothered by wind turbines. Studies show that for example, overhead power pole lines are far more hazardous for birds than wind turbines [2]. Windtower shadow effect: Wind turbines, like other tall structures cast a shadow on the neighboring area when the sun is visible. It may be irritating if the rotor blades chop the sunlight, causing a flickering effect while the rotor is in motion, especially when the sun is low in the sky. Interconnection issues. Connecting wind turbine to operate in parallel with the electric power system influences the system operating point (load flow, nodal voltages, power losses, etc). These changes in the electric power system state bring up new systemintegration issues that system operators and power quality engineers must take into account. These interconnection issues can be divided into operational issues and electrical issues. • Operational Issues: These include unit commitment and spinning reserve.
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3 − The unit commitment problem is to schedule specific or available generators (on or off) on the utility system to meet the required loads at a minimum cost, subject to system constraints. The most conservative approach to unit commitment and economic dispatch is to discount any contribution from interconnected wind resources because of wind variability. − Operating reserve is further defined to be a spinning or non spinning reserve. Any probable load or generation variations that cannot be forecasted, such as wind power, have to be considered when determining the amount of operating reserve to carry out. • Electrical issues: These factors are considered in the next section. Electrical Issues Windturbine generatorsystem operation has some negative influence on power systems. This influence on the electric power system depends on wind variations and on windturbine technology. Impacts on the electric power system can be grouped as follows: • • • Power quality: Voltage variations, flicker, harmonics, powerflow variations Voltage and angle stability Protection and control The IEEE 1547 [5] and the IEC 6140021 [6] standards are the bases to evaluating the impact of such windturbine generation systems on the electric power system. According to the IEEE 1547 [5, page 2] abstract, This standard focuses on the technical specifications for, and testing of, the interconnection itself. It provides requirements relevant to the performance, operation, testing, safety considerations, and maintenance of the interconnection. It includes general requirements, response to abnormal conditions, power quality, islanding, and test specifications and requirements for design, production, installation evaluation, commissioning, and periodic tests. The stated requirements are universally needed for interconnection of distributed resources (DR), including synchronous machines, induction machines, or power inverters/converters and will be sufficient for most installations. The criteria and requirements are applicable to all DR technologies, with aggregate capacity of 10 MVA or less at the point of common coupling, interconnected to electric power systems at typical primary and/or secondary distribution voltages.
4 According to the IEC 6140021 [6, page 9] abstract, The purpose of this part of IEC 61400 is to provide a uniform methodology that will ensure consistency and accuracy in the measurement and assessment of power quality characteristics of grid connected wind turbines (WTs). In this respect the term power quality includes those electric characteristics of the WT that influence the voltage quality of the grid to which the WT is connected. This standard provides recommendations for preparing the measurements and assessment of power quality characteristics of grid connected WTs. Table 11 shows technical specifications for interconnection and power assessment covered in both standards. Table 11. Technical specifications of IEC and IEEE Interconnection system Power quality assessment response to excursions IEEE Voltage Frequency IEC Voltage Voltage fluctuations: Frequency Continuous operation Switching operation Harmonics As shown in Table 11, both standards overlooked one of the most significant characteristics of wind farms: its variability (i.e., power fluctuations) [7], the most important ones being • • • Gusty wind variations having a spectrum of frequencies from 110 Hz. Shadow effect having a spectrum of frequencies from 12 Hz and producing torque variations up to 30%. Complex oscillations of the turbine tower, rotor shaft, gear box, and blades with spectrum frequencies from 2100 Hz, and creating torque variations up to 10%. Figure 11 shows actual output power data collected by NREL from two large windpower plants in the United States. The small wind farm has a capacity of about 35 MW, and the large one has a capacity of 150 MW.
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Figure 11. Windpower output for two wind farms during one month (May 2003). A) Nominal capacity 35 MW. B) Nominal capacity 150 MW. Even though the technology used in constructing the small wind farm is more than a decade older than the large one, power fluctuations keep being an issue. Figure 12 is a closeup of Figure 11 and shows the magnitude of these power fluctuations. Wind turbine manufactures usually provide power curves (Figure 13) to developers to determine the amount of power that will be transferred into the grid for a single turbine, given the wind speed. However, those figures represent only the mean values, since a series of stochastic values cannot be controlled, and create additional power fluctuations. Windoutput power fluctuations can have different effects on the electric power system, but the most significant ones are voltage variation and frequency variation in small or isolated systems.
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Figure 12. Power fluctuation comparison. A) Nominal capacity 35 MW. B) Nominal capacity 150 MW.
Figure 13. Typical power curve of a wind turbine. As the power fluctuates, the reactive power required by the turbines changes as well, and therefore voltage variations are expected, especially when the wind farm is
7 located at weak points in the system. To compensate for such voltage variations and keep the voltage close to its rated value, several solutions are available: simple capacitor banks, static voltage compensator (SVC), or static compensators (STATCOM). A different approach must be taken for frequency variations due to power fluctuations. Normally, wind farms connected to big systems do not present a major problem in terms of frequency variations, because of the stiffness of the system. However, with small or isolated systems that contain slow or no automatic generation controls, a mismatch between generated and absorbed power can significantly affect system frequency unless spinning reserves are significant. Figure 14 shows the effect of windpower fluctuation on an isolated system with a wind penetration level of 1%. To counter these negative effects, countries and small isolated systems with high windpenetration factors developed special purchase power agreement (PPA) requirements or indexes for windfarm developers (Table 12).
Figure 14. Windfarm output power vs system frequency.
8 Table 12. Windfarm outputpower requirements Ramp Rate dP/dt Netherlands <12 MW per min Denmark <0.1·Pnom per min Hawaii Germany Scotland <2 MW per min <0.1·Pnom per min No limit for Pnom<15 MW/min Pnom/15 for Pnom=[15150] MW/min 10 MW for Pnom>150 MW per min 1 MW change per 2 sec scan Instantaneous Average (max variation) <0.05 Pnom per 60 sec period <0.3MW per 60 sec period
These power requirements guarantee minimum impact on system voltage and frequency control. However, today’s wind farms have limited capacity to reduce the rate of change of power, especially the down ramp rate. At high wind speeds (above the rated wind speed), active and stalled pitch controls, among other strategies, can help keep the output power under control. However, modern wind turbines are designed to obtain as much power as possible at low wind speeds (Figure 15), making them very vulnerable to wind variations.
Figure 15. Control strategies along the power curve
9 Solutions to WindPower Fluctuations To reduce the effects of windpower variations and meet the PPA requirements for electric utilities, two solutions can be considered: • • Higher spinning reserves Wind farm buffer Increasing spinning reserves is a costly solution. A better approach would be to use an energystorage system that could deliver the required power when needed. Work has been done in developing largescale energy storage systems that have overcome these issues by absorbing undesirable power fluctuations and providing firm, dependable peaking capacity [8]. However, a less costly solution should be explored based exclusively on powerfluctuation indexes (such as ramp rate indexes or instantaneous fluctuation indexes). State of the Art Storing wind power is not a new concept; in fact, back in 1900, the father of the modern wind turbine, Poul La Cour, tackled for the first time the problem of energy storage. He used the electricity from the wind turbines for electrolysis and to store energy in the form of hydrogen. However, with time, system requirements, energy storage systems, and wind turbine ratings have changed. Nowadays, the average wind turbine installed is around 1 MW, according to the European Wind Energy Association, and windpower farms usually consists of ten to several tens of windturbine generators of rated power up to 2 MW. Thus, the amount of energy storage needed to stabilize the power output change in the short term has increased. Table 13 shows some recent projects dealing with output leveling of windenergy conversion.
Table 13. Largescale windpower outputleveling projects Project name Subaru Project [9]. Tomamae windpower station. Wind farm size 1.65 MW *16 (Vestas). 1.5 MW * 5 (Enercon). Energy storage system Vanadium–Redox Flow Battery PVRB nominal =4.000kW EVRB=6.000kWh S inverter=6.000kVA Vanadium–Redox Flow Battery Active power reference control scheme Moving Average of wind farm output determined as Pbattery=Pwind average (tΔt)Pwind(t) (for Δt=8 seconds to 8 hours) Isochronous frequency mode over the VRB power range. Speed droop characteristic during instantaneous and shortterm load (>± 200 kW).
Total Capacity 30.6 MW King Island [10]. Energy 250 kW*3 storage system provided 850 kW*2 by Pinnacle VRB Total Capacity 2.45 MW Oki project by Fuji Electric 600 kW *3 Total Capacity 1.8 MW
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PVRB nominal=200kW PVRB shortterm ( 5 minutes)=300kW PVRB shortterm (10 seconds)=400kW EVRB =1100kWh Flywheel Power ramp rate limiting E flywheel = 100 kW  90 sec P inverter flywheel side= 110kVA P inverter power system side= 150kVA
11 However, smallscale concepts and technical/economic feasibility studies have been proposed (Table 14). Each of these projects has a different objective (frequency control, power smoothing, load leveling, etc.). However, they all end up using one of the topologies and energystorage systems shown in Table 15, where the flywheel or capacitors may be replaced by some other energystorage medium. Tables 13 and 14 show that the amount of energy needed for windpower balancing using current technology and current pricing is so significant, that a more flexible and integrated approach is needed. Our study focused on developing new power smoothing control algorithms. The new integrated approach used a shuntconnected voltagesource converter with added storage included on the DC link bus. The system can • • • Exchange active power with the system. Regulate voltage at the point of common coupling Increase power quality and system stability Objective Our purpose was to develop, simulate, and implement a proofofconcept prototype advancedpower electronic device capable of controlling and smoothing the power fluctuations of a wind farm using an optimal amount of energy. The windpower generation buffering concept is shown in Figure 16. The Power Stabilizer was designed to store excess power during periods of increased windpower generation and release stored energy during periods of decreased generation due to wind fluctuations. We tested the performance of the advanced electronic device on • • • • DCsynchronous machine set Passive load DCasynchronous machine set Windfarm buffer or also called Power Stabilizer
Table 14. Conceptual windpower filtering projects Wind farm size Energy storage system 20 MW Zincbromide battery PZBB nominal (charge) =750kW PZBB nominal (discharge)=1500kW EZBB =1500 kWh Superconducting magnetic energy storage (SMES) Electric double layer capacitor P ECS =100 kW E ECS =1.1 kWh Redoxflow battery (Regenesys ) E=62004 MWh P=255MW Flywheel E flywheel= 12MJ P drive=45kW Lead Acid Battery E battery=35kWh P converter=50kVA
Maximum power oscillation 2.5 MW 300kW
Active power reference control scheme Limiting instantaneous power fluctuations based on a 2 seconds interval ΔPinstantaneous (Δt=2 seconds) = ±1.3 MW Average power levels over a 2 hour window Paverage(t Δt=2hours)= ±200 kW Active power reference is chosen to control system frequency ESS active power reference is determined by detection power oscillation components using a high pass filter Power balancing
Comments Technical and economical feasibility evaluation [11] Simulation study [12] Simulation study [13] 12
6GW
Feasibility study [14]
45KW 55kW
The active power demand is extracted via a 2nd Practical results [15][16] order Butterworth high pass filter, with a 5mHz bandwidth Power smoothing Practical results [17]
13
10800 10600 10400 10200 Power (W) Wind Power Output
10800 10600 10400 10200 Power (W) 10000 9800 9600 9400 9200 9000 8800
Wind Power Output
Wind power + Wind farm buffer Power
10000 9800 9600 9400
V47 VRCC Vestas
9200 9000 8800 0 20 40 60 Time (s) 80 100 120
0
20
40
60 Time (s)
80
100
120
L1 L2 L3
A B C #2 0.69
? #1 12.47
A B C
A B C #2 12.47
? #1 69.0
A B C
WIND FARM
600 400 200 0 Power (W) 200 400 600 800 1000
A B C #1 12.47 ? #2 0.48 A B C NAS VnaS NBS VnbS NCS VncS 4 2 g4 2 g6 6 2 g2 2 2 gc2 5 1.0 300.0 2 g1 2 g3 2 g5 dcCur 1 3 5 5 2 gc1
Power Stabilier Power Output
INVERTER
Chopper Reactor
1.0
Energy Storage Capacitor
0
20
40
60 Time (s)
80
100
120
Figure 16. Windfarm generation buffering concept Table 15. Basic system configurations Voltage source inverter ESS connected at the DC link side [19][21][24]
Wind Turbine Voltage Source Inverter
DC link
Electric System
Synchronous Machine
ESS (flywheel)
ESS connected at the AC side [18][20][22][23][25]
Wind Turbine Electric System
System configuration
Induction Machine DC link
Voltage Source Inverter
ESS (flywheel)
Current source inverter (shunt connected) [13]
Wind Turbine Electric System
Induction Machine
Chopper (DC/DC converter)
ECS
Current Source Inverter
ESS (capacitors)
Available options [26] • Compressed air energy storage • Battery storage Energy storage system • Electrochemical flow cell systems • Fuel cell/electrolyser/hydrogen systems • Kinetic energy (flywheel) storage • Pumping water
CHAPTER 2 SYSTEM DESIGN Introduction One of the most difficult tasks when designing a control algorithm for a power electronic converter is to calculate the regulators’ gains. Determination of the controllers’ parameters is based on the electric power system they are connected to, and also on the power electronic converter topology. This chapter details the design of the different regulators involved in the control of the Power Stabilizer and also the design of the different components that define its topology. The system design was carried out per unit, so results can be extrapolated to any system size, to facilitate implementation of the control scheme in a fixedpoint digital signal processor. The system design was also compared to simulation results to assure the correctness of the design methodology used Control Scheme Positive Sequence Calculation Threephase systems are not always balanced, especially during fault conditions, and it is expected to have positive, negative and even zero sequence components. However, for voltage regulation purposes, only the positive sequence component is of importance. Before going into detail on the positive extraction algorithm description, we will explain first where the transformations given in Appendix A fail in coupling the different symmetrical components. Consider the following set of phasors
14
15
Va = 0.5∠ 0° Vb = 1.0 ∠ −120° Vc = 1.0 ∠ −240° Figure 21 shows the time domain representation of this threephase unbalanced system. (21)
Figure 21. Unbalanced system If we now calculate the symmetrical components of this unbalanced system, we obtain V1 = 0.833∠ 0° V2 = 0.167 ∠180° V0 = 0.167 ∠180° The symmetrical components transformation is a good tool to determine the type of distortion or asymmetry the system has. However, it has the drawback of having to use phasors as input instead of time domain signals. Therefore a different transformation was needed in order to extract the positive sequence component out of the rotating space vector. Figure 22 shows the trajectory followed by the rotating space vector of the unbalanced system in the dqo plane using Clarke’s transformation. This trajectory is (22)
16 clearly distorted from the ideal one, and the space vector no longer follows a circular path (Figure 23).
Figure 22. Space vector trajectory of an unbalanced system in the dqo plane
Figure 23. Space vector trajectory projection over the dq plane Figure 24 shows the Vdr and Vqr components (Park’s transformation) of the unbalanced system in the time domain for δ = 0°.
17
Figure 24. Direct and quadrature components of an unbalanced system It is clear that the Vdr component is not constant any more, and it contains a 2nd harmonic due to the negative sequence. This effect can also be explained in the frequency domain as shown in Figure 25. The rotating reference frame aligns with the fundamental frequency, w=2πf, and therefore • • • a negative sequence (w) appears as a 2nd harmonic a dc component appears as a 1st harmonic a positive sequence (w) has a constant value.
abc axis drqr axis
0.833
0.167
w
dc
w
w
2w
w
dc
Figure 25. Representation of an unbalanced system in the frequency domain
18 Thus, it can be concluded that Clarke’s and Park’s transformations do not provide suitable components that can be used in a voltage regulation control algorithm. It is therefore necessary then to redefine the transformations in order to extract the desired components. Assuming the threephase electric system has positive and negative sequence components
Va = V p ⋅ cos( wt ) + Vn ⋅ cos(− wt ) Vb = V p ⋅ cos( wt − 2π 2π ) + Vn ⋅ cos(− wt + ) 3 3 4π 4π Vc = V p ⋅ cos( wt − ) + Vn ⋅ cos(− wt + ) 3 3
(23)
Clarke’s transformation can be used to obtain
Vds = V p ⋅ cos( wt ) + Vn ⋅ cos( wt ) = Vds+ + Vds− Vqs =V p ⋅ sin( wt ) − Vn ⋅ sin( wt ) = Vqs+ + Vqs−
(24)
where Vds+ and Vqs+ are the dq components of the positive sequence, while Vds− and Vqs− are the dq components of the negative sequence. If we now assume that the symmetrical components remained constant for at least a quarter of cycle, the equations can be rewritten as
Vds + (t ) = Vqs + (t ) =
1 ⎛ ⎛ π ⎞⎞ ⋅ ⎜ Vds (t ) − Vqs ⎜ t − ⎟ ⎟ ⎜ ⎟ 2 ⎝ ⎝ 2 ⎠⎠ ⎞ 1 ⎛ ⎛ π⎞ ⋅ ⎜ Vds ⎜ t − ⎟ + Vqs (t )⎟ ⎜ ⎟ 2 ⎝ ⎝ 2⎠ ⎠
1 ⎛ ⎛ π ⎞⎞ Vds − (t ) = ⋅ ⎜ Vds (t ) + Vqs ⎜ t − ⎟ ⎟ ⎜ ⎟ 2 ⎝ ⎝ 2 ⎠⎠ Vqs − (t ) = ⎞ 1 ⎛ ⎛ π⎞ ⋅ ⎜ Vds ⎜ t − ⎟ − Vqs (t )⎟ ⎜ ⎟ 2 ⎝ ⎝ 2⎠ ⎠
(25)
19 These components can now be transformed using the rotating reference frame in order to obtain the positive sequence component. Figure 26 shows the block diagram of the algorithm used to extract the positivesequence component. The same concept could be used if the negative sequence magnitude is needed.
θ
Va Vb Vc
abd dsqs
Vds Vqs _+
Delay (1/f/4) 0.5
Vdr dsqs drqr Vds+ Vqs+ Vqr
dsqs drqr
Vdr+ Vqr+
x x
Sliding window filter
+
Delay (1/f/4)
+ +
+
magnitude positive sequence
V
Filter
+
0.5
θ
Figure 26. Positivesequence extraction algorithm Figure 28 shows the algorithm performance when an unbalanced fault condition takes place at t=0.02 sec (Figure 27). The data used for this example is given by Equation 22.
Figure 27. Voltage waveforms for an unbalanced fault event
20
A
B
Figure 28. Response of the positivesequence extraction algorithm. A) Positive sequence using ½ and 1 cycle filters. B) Positive sequence using Vdr with 1 cycle filter The meaning of the different plotted variables is the following: • Vpositivesequence magnitude is the output of the positivesequence extraction algorithm. As expected, its time response is only one quarter of a cycle. However, the transient response is very abrupt an uneven. Vpositivesequence magnitude (1/2 cycle filter) is the filtered signal of Vpositivesequence magnitude using a half cycle sliding window filter. Vpositivesequence magnitude (1 cycle filter) is the filtered signal of Vpositivesequence magnitude using a onecycle sliding window filter. Its transient response is the slowest but at the same time the smoothest among the three signals. Vdr filtered is the filtered signal of Vdr . The one cycle sliding window filter (also called moving average) rejects all harmonics. Therefore there is no need to use the Vds+ and Vqs+ calculator to extract the positive sequence. However its transient response is not as smooth as the Vpositivesequence magnitude (1 cycle filter) one.
• •
•
Real Power Calculation Using dq Components
As shown in Appendix A Park’s transformation matrix is not unitary ( Tdqo ≠ Tdqo
[ ] [ ]
t
−1
) and therefore is not power invariant.
The total instantaneous power in abc quantities can be transformed into qdo quantities as shown in Equation 26.
21 This relationship between dqo quantities and the instantaneous power is later used in the control system to determine the amount of directcurrent component ( I dr ) needed to meet the power fluctuation requirements.
⎡Va ⎤ = Va ⋅ I a + Vb ⋅ I b + Vc ⋅ I c = ⎢Vb ⎥ ⎢ ⎥ ⎢Vc ⎥ ⎣ ⎦ ⎡ ⎢ = ⎢ Tdqo ⎢ ⎣ = Vdr
t
Pabc
⎡I a ⎤ ⋅ ⎢I b ⎥ ⎢ ⎥ ⎢I c ⎥ ⎣ ⎦
[ ]
⎡Vdr ⎤ ⎤ ⎥ −1 ⎢ ⋅ ⎢Vqr ⎥ ⎥ ⎥ ⎢ Vo ⎥ ⎥ ⎣ ⎦⎦
t
⎡ ⎢ ⋅ ⎢ Tdqo ⎢ ⎣
[ ]
−1 t
−1
⎡ I dr ⎤ ⎤ ⎢I ⎥⎥ ⋅ ⎢ qr ⎥ ⎥ ⎢ I o ⎥⎥ ⎣ ⎦⎦
−1 dqo
[
Vqr
Vo ⋅ Tdqo ⎡3 ⎢2 ⎢ Vo ⋅ ⎢ 0 ⎢ ⎢0 ⎢ ⎣
] [[ ] ] ⋅ [T ]
0
⎡ I dr ⎤ ⋅ ⎢ I qr ⎥ ⎢ ⎥ ⎢ Io ⎥ ⎣ ⎦
⎤ 0⎥ I ⎥ ⎡ dr ⎤ 3 ⎢I ⎥ = Vdr Vqr 0 ⎥ ⋅ ⎢ qr ⎥ 2 ⎥ 1⎥ ⎢ Io ⎥ ⎣ ⎦ 0 ⎥ 3⎦ 3 1 = ⋅ (Vdr ⋅ I dr + Vqr ⋅ I qr ) + ⋅ Vo ⋅ I o 2 3
[
]
(26)
Phase Locked Loop
The phase angle of the utility voltage (Ө) is of vital importance for the operation of most of the advanced power electronic devices connected to the electric utility, since it has a direct effect on their control algorithms. A simple and fast method to obtain the phase angle of the utility voltage is to use Clarke’s transformation as shown in Equation 27.
1 ⎡ X ds ⎤ 2 ⎢1 − 2 ⎡ ⎢X ⎥ = ⎢ 3 ⎣ qs ⎦ 3 ⎢0 ⎢ ⎣ 2
1 ⎤ ⎡X ⎤ a 2 ⎥ ⋅⎢X ⎥ ⎥ 3⎥ ⎢ b⎥ − ⎢X ⎥ 2 ⎥ ⎣ c⎦ ⎦ −
⇒
θ = arctan⎜ ⎜
⎛ X qs ⎝ X ds
⎞ ⎟ ⎟ ⎠
(27)
22 However, this approach is not robust since it is very sensitive to system disturbances. The phase angle Ө distorts as the utility’s voltage becomes affected by different power quality events, such as voltage unbalance, voltage sags, frequency variations, etc. Figure 29 shows the voltage’s phase angle under unbalanced conditions using Equation 27. The angle distortion is due to the negative sequence component of the unbalanced threephase system.
Figure 29. Distortion of phase angle due to a negative sequence component In order to lock the phase angle of the utility voltage in a robust way, a phase locked loop (PLL) was used. Assuming a balanced three phase system, the control model of the PLL was obtained using Park’s transformation as shown in Equation 28.
⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡Va ⎤ ⎡Vdr ⎤ ⎢V ⎥ = 2 ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢V ⎥ = ⎥ ⎢ b⎥ ⎢ qr ⎥ 3 ⎢ ⎢ 1 ⎥ ⎢V ⎥ 1 1 ⎢ Vo ⎥ ⎣ ⎦ 2 2 2 ⎣ ⎦ ⎣ c⎦ ⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡ V ⋅ cos( wt ) ⎤ ⎥ 2⎢ = ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢V ⋅ cos( wt − 120°) ⎥ ⎥ ⎢ 3⎢ 1 ⎥ ⎢V ⋅ cos( wt − 240°)⎥ 1 1 ⎦ 2 2 2 ⎣ ⎦ ⎣
(28)
23 Where Ө* is the PLL phase angle output, Ө is the utility’s phase angle, and w = dθ Thus, if Ө(t=0)=0, we can substitute wt for Ө(t) and obtain .
dt
⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡ V ⋅ cos(θ ) ⎤ ⎡Vdr ⎤ 2⎢ ⎢V ⎥ = − sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢V ⋅ cos(θ − 120°) ⎥ (29) ⎥ ⎢ ⎥ ⎢ qr ⎥ 3 ⎢ ⎥ ⎢V ⋅ cos(θ − 240°)⎥ ⎢ 1 1 1 ⎢ Vo ⎥ ⎦ ⎣ ⎦ 2 2 2 ⎦ ⎣ ⎣ Using trigonometric identities, Equation 29 results in ⎡cos(θ * − θ )⎤ ⎡Vdr ⎤ ⎡cos(Δθ )⎤ ⎢V ⎥ = V ⋅ ⎢ sin(θ * − θ ) ⎥ = V ⋅ ⎢ sin(Δθ ) ⎥ ⎢ ⎥ ⎢ qr ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ Vo ⎥ ⎢ 0 ⎥ 0 ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
(210)
Where ΔӨ is the error between the utility angle and the PLL output. If the ΔӨ is set to zero, Vdr=V and Vqr=0. Therefore, it is possible to lock the utility angle by regulating Vqr to zero without needing any information regarding the magnitude of the utility voltage. Figure 210 shows the details of the PLL algorithm used in our study. The limits of the controller integrator and the limiter were ±30 rad/sec. Thus, the PLL was able to track the system frequency as long as this was within 2π60±30 rad/sec or 55 to 65 Hz range. To use linear control techniques for the design and tuning of PLL controller, it was assumed that: • • • For small values of ΔӨ, the term sin (ΔӨ) behaved linearly, i.e., sin(ΔӨ) ≈ ΔӨ. Wref was assumed to be a constant perturbation. Limiters behave linearly for small control actions, and therefore can be removed.
θ
Va Vb Vc
abd dsqs
Vds Vqs
dsqs drqr
Vdr Vqr Ki
Kp
1 s
30
30
+ +
30
+
30
+
1 s
W ref=2πf
Figure 210. PLL diagram
24 Figure 211 shows the PLL control loop after eliminating the nonlineal terms.
PLL controller θ
+ 
Δθ Ki
Kp
1 s
Plant transfer Function
+ +
θ∗
Control action
1 s
θ∗
Figure 211. PLL simplified model The closed loop transfer function of Figure 211 determines the dynamic characteristics and stability of the system, and can be expressed as
H=
K ps + KI θ* = 2 θ s + K ps + KI
(211)
The control system (Kp and Ki) was designed to satisfy two performance objectives
• •
< 10% overshoot Settling time inside the 2% band error lower than 2 secs The criterion to select the settling time was a tradeoff between high distortion
rejection and tracking of normal system frequency variations. The PLL closed loop transfer function was compared to a standard second order transfer function to determine the regulator’s gains. The obtained values were
ζ = 0.7 ( for 5% overshoot )
t s = 2 sec
⎛ 4 ⎞ ⎛ 4 ⎞ KI = ω = ⎜ ⎟ ⎝ ⎜ ζ ⋅ t ⎟ = ⎜ 0.7 ⋅ 2 ⎟ = 8.1 ⎠ s ⎠ ⎝ K p = 2 ⋅ ζ ⋅ ω n = 2 ⋅ 0.7 ⋅ 2.85 = 4
2 n
2
2
Figure 212 shows the system’s closedloop step response for two different PI regulators.
25 The originally designed regulator did not meet the system requirements due to the effect of the zero introduced by the PLL regulator. This additional zero increased the overshoot, but it had very little influence on the settling time. Thus, it was necessary to tune the original regulator gains in order to meet the system requirements.
Figure 212. PLL system step response Figure 213 shows the root locus of the singleinput single output PLL system for the two regulators.
Figure 213. Root locus for two different regulator gains
26 Figures 214 and 215 show the PLL system response to a negative sequence condition (V2=16.6%) and a system frequency excursion (w=2π60+30 rad/sec).
Figure 214. PLL system response to an unbalanced system condition
A
B
Figure 215. PLL system response to a frequency excursion. A) Angle. B) PLL error.
Control Algorithm Design
Park’s transformation was used to model the system’s equations to facilitate the design of the control system. The usage of a rotating reference frame had the following advantages:
•
Improvement of the steadystate performance of the current controllers: Sinusoidal signals were transformed into dc components, and accordingly it is possible to achieve small signal errors. High bandwidth current controllers: Feedback signals and reference signals were not sinusoidal, but dc.
•
27
•
Decoupling of active and reactive power: This was very useful when trying to control voltage at the point of coupling while meeting the system requirements in terms of power fluctuations.
Figure 216 shows the overall system topology as well as the sign notation that was used in the control system design. In general, power flowing out of the inverter will be considered to be positive. The objective was to smooth out windpower fluctuations using the power stabilizer as a buffer. The energystorage voltage was expected to change in order to accommodate for those changes in wind power.
WIND FARM UTILITY SYSTEM Transformer equivalent impedance Inverter DC link bus Chopper
Xsource Iwind Vpcc Lxfrm Cf Vf Lf Iinv Vinv Vdc Cdc Ichopper Vchopper Vstorage
ESS Filter
P+
Figure 216. System description
Inner regulators Inverter system model. For the following set of equations, it was assumed that the
inverter behaved as an ideal controllable voltage source, neglecting the effects of the current harmonics. System’s nonlinearities, such as saturation or deadtime effects were taken into consideration later on in the design. The capacitor filter was neglected in the analysis, since the filter current represented a small portion of the inverter’s current. The system can then be represented as shown in Figure 217.
28
Vpcc a Vpcc b Vpcc c
R R R
L L L
Iinv a Iinv b Iinv c
Vinv a Vinv b Vinv c
C
VDC LINK
Figure 217. Simplified system model The system equations for the simplified model are
⎡Vinva ⎤ ⎡ I inva ⎤ ⎡ I inva ⎤ ⎡V pcca ⎤ ⎢V ⎥ = R ⋅ ⎢ I ⎥ + L ⋅ d ⎢ I ⎥ + ⎢V ⎥ invb ⎥ ⎢ pcca ⎥ ⎢ invb ⎥ ⎢ invb ⎥ dt ⎢ ⎢Vinvc ⎥ ⎢ I invc ⎥ ⎢ I invc ⎥ ⎢V pcca ⎥ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
Applying Park’s transformation we get
(212)
[T ]
dqo
−1
⎡Vinv dr ⎤ ⎢ ⎥ ⎢Vinv qr ⎥ = R Tdqo ⎢Vinv o ⎥ ⎣ ⎦
[ ]
−1
⎧ ⎡ I inv dr ⎤ d ⎪ ⎢ ⎥ ⎢ I inv qr ⎥ + L dt ⎨ Tdqo ⎪ ⎢ I inv o ⎥ ⎣ ⎦ ⎩
[ ]
−1
⎡ I inv dr ⎤ ⎫ ⎢ ⎥⎪ ⎢ I inv qr ⎥ ⎬ + Tdqo ⎢ I inv o ⎥ ⎪ ⎣ ⎦⎭
[ ]
−1
⎡V pcc dr ⎤ ⎢ ⎥ ⎢V pcc qr ⎥ ⎢ V pcc o ⎥ ⎣ ⎦
(213)
⎧ ⎡Vpccdr ⎤ ⎡Vinvdr ⎤ ⎡Iinvdr ⎤ ⎡Iinvdr ⎤⎫ d⎪ ⎥ ⎢ ⎥ ⎥ ⎥⎪ −1 ⎢ −1 ⎢ −1 ⎢ ⎢Vinvqr ⎥ = Tdqo ⋅ R ⋅ Tdqo ⋅ ⎢Iinvqr ⎥ + Tdqo ⋅ L ⋅ dt ⎨ Tdqo ⋅ ⎢Iinvqr ⎥⎬ + Tdqo ⋅ Tdqo ⋅ ⎢Vpccqr ⎥ (214) ⎪ ⎢Vpcco ⎥ ⎢Vinvo ⎥ ⎢ Iinvo ⎥ ⎢ Iinvo ⎥⎪ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦⎭ ⎩
[ ] [ ]
[ ]
[ ]
[ ][ ]
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ ⎢ ⎥ ⎢ ⎥ ⎢Vinv qr ⎥ = R ⋅ ⎢ I inv qr ⎥ + L ⋅ Tdqo ⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎣ ⎦ ⎣ ⎦
[ ] [ ]
⎧ ⎪ d Tdqo ⋅⎨ ⎪ dt ⎩
−1
⎡ I inv dr ⎤ ⎢ ⎥ ⋅ ⎢ I inv qr ⎥ + Tdqo ⎢ I inv o ⎥ ⎣ ⎦
[ ]
−1
⎡ I inv dr ⎤ ⎫ ⎡V pcc dr ⎤ d⎢ ⎥ ⎥⎪ ⎢ ⋅ ⎢ I inv qr ⎥ ⎬ + ⎢V pcc qr ⎥ (215) dt ⎢ I inv o ⎥ ⎪ ⎢ V pcc o ⎥ ⎦ ⎣ ⎦⎭ ⎣
⎡Vinvdr ⎤ ⎡Iinvdr ⎤ ⎤ ⎡Iinvdr ⎤ ⎡Vpccdr ⎤ −1 ⎡I d Tdqo ⎢ invdr ⎥ ⎢ ⎥ ⎢ ⎥ ⎥ ⎢ ⎥ −1 d ⎢ ⎢Vinvqr ⎥ = R ⋅ ⎢Iinvqr ⎥ + L ⋅ Tdqo ⋅ dt ⋅ ⎢Iinvqr ⎥ + L ⋅ Tdqo ⋅ Tdqo ⋅ dt ⎢Iinvqr ⎥ + ⎢Vpccqr ⎥ (216) ⎢Vinvo ⎥ ⎢ Iinvo ⎥ ⎢ Iinvo ⎥ ⎢ Iinvo ⎥ ⎢Vpcco ⎥ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
[ ] [ ]
[ ][ ]
29
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ d Tdqo ⎢ ⎥ ⎢ ⎥ Vinv qr ⎥ = R ⋅ ⎢ I inv qr ⎥ + L ⋅ Tdqo ⋅ ⎢ dt ⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎣ ⎦ ⎣ ⎦
Where
d Tdqo dt
[ ] [ ]
−1
⎡ I inv dr ⎤ ⎡ I inv dr ⎤ ⎡V pcc dr ⎤ d ⎢ ⎢ ⎥ ⎥ ⎢ ⎥ ⋅ ⎢ I inv qr ⎥ + L ⋅ ⎢ I inv qr ⎥ + ⎢V pcc qr ⎥ dt ⎢ I inv o ⎥ ⎢ I inv o ⎥ ⎢ V pcc o ⎥ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
(217)
[ ]
−1
− sin(θ ) − cos(θ ) 1⎤ ⎡ − sin(θ ) 0⎤ ⎡ cos(θ ) d ⎢ ⎥ = ⎢ − sin(θ − 120°) − cos(θ − 120°) 0⎥ ⋅ dθ = ⎢ cos(θ − 120°) − sin(θ − 120°) 1⎥ ⎢ ⎥ dt dt ⎢cos(θ − 240°) − sin(θ − 240°) 1⎥ ⎢− sin(θ − 240°) − cos(θ − 240°) 0⎥ ⎣ ⎦ ⎣ ⎦
(218)
ω=
dθ dt
It can be shown that
[T ]⋅ d [Tdt ]
dqo dqo
−1
=
⎡ cos(θ * ) cos(θ * − 120°) cos(θ * − 240°) ⎤ ⎡ − sin(θ ) 0⎤ (219) − cos(θ ) ⎢ ⎥ ⎢ 2 = ⋅ ω ⋅ ⎢− sin(θ * ) − sin(θ * − 120°) − sin(θ * − 240°)⎥ ⋅ ⎢ − sin(θ − 120°) − cos(θ − 120°) 0⎥ ⎥ 3 ⎢ 1 ⎥ ⎢− sin(θ − 240°) − cos(θ − 240°) 0⎥ 1 1 ⎦ ⎣ 2 2 2 ⎣ ⎦ ⎡0 − 1 0 ⎤ ⎡ 0 − ω 0 ⎤ = ω ⋅ ⎢1 0 0⎥ = ⎢ω 0 0⎥ ⎥ ⎥ ⎢ ⎢ ⎢0 0 0 ⎥ ⎢ 0 0 0⎥ ⎦ ⎦ ⎣ ⎣
Thus, the equations for the simplified model in the dq plane are
⎡Vinv dr ⎤ ⎡ I inv dr ⎤ ⎡0 ⎢ ⎥ ⎢ ⎥ ⎢ ⎢Vinv qr ⎥ = R ⋅ ⎢ I inv qr ⎥ + L ⋅ ⎢ω ⎢Vinv o ⎥ ⎢ I inv o ⎥ ⎢0 ⎣ ⎣ ⎦ ⎣ ⎦ −ω 0 0 ⎡ I inv dr ⎤ ⎡V pcc dr ⎤ 0⎤ ⎡ I inv dr ⎤ d ⎢ ⎥ ⎥ ⎢ ⎥ ⎥ ⋅ ⎢I 0⎥ ⎢ inv qr ⎥ + L ⋅ ⎢ I inv qr ⎥ + ⎢V pcc qr ⎥ dt ⎢ I inv o ⎥ ⎢ V pcc o ⎥ 0⎥ ⎢ I inv o ⎥ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
(220)
The zerosequence component can be removed, since the system is a threephase threewire inverter with the DC link bus isolated from the AC side (the DC link midpoint will not be tapped to neutral). Removing the zero sequence we obtain Vinv dr = R ⋅ I inv dr + L ⋅ Vinv qr = R ⋅ I inv qr + L ⋅ dI inv dr dt dI inv qr dt + V pcc dr − L ⋅ ω ⋅ I inv qr (221) + V pcc qr + L ⋅ ω ⋅ I inv dr
30 Equation 221 can be represented as a coupled electrical system as shown in Figure 218.
R Vpcc dr
L
Iinv dr LωIinv qr Vinv dr
A
R Vpcc qr
L
Iinv qr LωIinv dr Vinv qr
B
Figure 218. Electrical representation of the dq components. A) Direct circuit. B) Quadrature circuit. Using Laplace’s transformation we can rewrite the equations as Equation 222.
Vinv qr ( s) = (R + Ls ) ⋅ I inv qr ( s ) + V pcc qr ( s) + L ⋅ ω ⋅ I inv dr ( s) Vinv dr ( s) = (R + Ls ) ⋅ I inv dr ( s ) + V pcc dr ( s) − L ⋅ ω ⋅ I inv qr ( s)
(222)
Thus, the block diagram of the system is represented in Figure 219.
Vinv dr
+ +
1 R + Ls
Iinv dr
Vpcc dr
ωL ωL
Vinv qr
+ 

1 R + Ls
Iinv qr
Vpcc qr
Figure 219. System model block diagram
31 The inverter’s critical control variable was the inverter’s current. This was due to the fact the outer control loops, such voltage regulators, power regulators, etc, were based on the inner current regulators. That was why the current controllers were designed to meet two basic requirements, which were high accuracy and high bandwidth. The inverter’s terminalvoltage needed to generate the desired inverter current can be determined as Vinv dr = R ⋅ I inv dr + L ⋅ Vinv qr = R ⋅ I inv qr + L ⋅ dI inv dr dt dI inv qr dt + V pcc dr − L ⋅ ω ⋅ I inv qr = ΔVdropdr + V pcc dr − L ⋅ ω ⋅ I inv qr + V pcc qr + L ⋅ ω ⋅ I inv dr = ΔVdropqr + V pcc qr + L ⋅ ω ⋅ I inv dr
(223)
The voltage drop due to the filter inductance was compensated using a PI controller. Figure 220 shows the inveter’s current controller implementation for the system given in Equation 223.
ˆ V pcc dr
Iinv dr ref
ˆˆ ωL
Vinv dr
+ Ki
Kp
1 s
+
ΔVdrop dr
+ 
+ +
+
+
1 R + Ls
Iinv dr
Iinv dr
Vpcc dr
ωL ωL
Iinv qr ref
+ Ki
Kp
+
ΔVdrop qr
+
+
Vinv qr
+ 

1 s
+
+ ˆ V pcc qr
ˆˆ ωL
1 R + Ls
Iinv qr
Iinv qr
Vpcc qr
CURRENT REGULATORS
SYSTEM MODEL
Figure 220. Inverter current regulatorsystem model block diagram The character ^ over a constant or variable indicates that the quantity is estimated, and therefore subject to measurement errors.
32 To design the current regulator gains, crosscoupling factors were assumed to cancel each other out. Under these conditions, the simplified current regulator block diagram is shown in Figure 221.
Iinv dr ref
+ Ki
Kp
1 s
+
+
1 R + Ls
Iinv dr
Iinv dr
Iinv qr ref
+ Ki
Kp
+
1 s
+
1 R + Ls
Iinv qr
Iinv qr
CURRENT REGULATORS
SYSTEM MODEL
Figure 221. Inverter current regulatorsystem model simplified block diagram Figure 221 shows that: • • • The system behaves linearly, and therefore linear control techniques can be used to determine the regulators’ gains. Both regulators are identical. Only an estimation of L and R (filter inductance + transformer equivalent impedance) are needed to design the current regulator. Given the filter/transformer characteristics in p.u., the closedloop transfer function of Figure 222 is shown in Equation 224.
Iref
+ Ki
Kp
1 s
+
Control Action
+
1 R + Ls
I
Figure 222. Simplified current control diagram
33 I I ref K p ⋅ s + KI
H (s) =
=
Ls 2 + (R + K p )s + K I
(224)
Using the following system data, the transfer function is given in Equation 225. • X=Xtransfomer+Xfilter=5%+10% = 0.15 Ω → L= 400 µH • X/R=10 → R=0.015 Ω Note: More on the system parameters can be found in the perunit mode section. H (s) = 0.0004s + (0.015 + K p )s + K I
2
K p ⋅ s + KI
(225)
The Figure 223 shows the system step response for two different current regulator gains.
Figure 223. Current regulator step response Even though the current regulator with the highest gains had a faster settling time, the control action required to obtain such a response doubled the regulator with the lowest gains. To avoid possible system saturations the control action was kept below 1 pu. The best PI controller performance was achieved when the plant’s dominant pole was cancelled by the controller (Equation 226). Thus, the zero at  K I was assigned to
Kp
the time constant of the plant, which was, K I = R .
Kp L
34
⎛ K ⎞ K p ⋅⎜ s + I ⎟ ⎜ Kp ⎟ K ⎝ ⎠ PI = K p + I = s s
(226)
The synthesis was done by selecting the integral time constant of the PI equal to that of the load. For our study the selected values were
R = 37.5 L K p =1 KI =
Chopper system model. The analysis of the chopper system was less complex than
the inverter one, since no transformations were involved. Again, it was assumed that the chopper behaved as an ideal controllable voltage source and therefore the effects of the current harmonics were neglected.
Ichopper V chopper
Figure 224. Chopper equivalent system The system equations for the chopper equivalent circuit (Figure 224) are given in Equaion 227.
Vstorage = L ⋅ dI chopper dt + Vchopper dI chopper dt
V storage
(227)
Vchopper = Vstorage − L ⋅
The chopper’s terminals voltage needed to generate the desired chopper current can be determined as
Vchopper = Vstorage − ΔVdrop
(228)
35 The voltage drop due to the chopper inductance was compensated using a simple P controller. The gain of the controller was found by converting the continuous system into discrete time system as shown in Equation 229.
Vchopper = Vstorage − L ⋅
ΔI chopper
dt
= Vstorage − L ⋅
( I chopperref − I chopper )
dt
Vchopper = Vstorage − K L ⋅ ΔI chopper
L where K L = Δt
(229)
Where KL is the regulator’s gain and Δt is half of the sampling time period. Figure 225 shows the implementation of the chopper’s current regulator.
Ichopper ref
+ Ichopper
KL
+ Vstorage
Vchopper
Figure 225. Chopper current controller
Outer regulators
There were a total of three controllable currents, which consisted of Ichopper_ref, Iinvdr_ref, and Iinvqr_ref.. However, there were four variables that needed to be controlled, which were voltage at the dc link bus, voltage at the point of common coupling, voltage at the energy storage system, and wind farm power fluctuation. Table 21 shows how these variables were assigned to the respective current regulators. Table 21. Outer regulator assignation Inner current Variable to be Comments regulator controlled Iinv dr ref Vstorage, PΔwind The direct current component will be responsible for controlling the state of charge of the ESS and for smoothing the wind farm output power Iinv qr ref Vpcc The quadrature current component will be deployed for voltage regulation purposes Ichopper ref Vdc link The chopper current will regulate the DC link bus voltage.
36
DC link Voltage regulator. The DC link bus was the bridge between the energy
storage system (chopper) and the inverter. Therefore, it was a critical variable in the overall system. Poor DC voltage regulation could bring the system down, since the inverter and chopper would not be able to meet their respective voltage requirements. The DC link system can be modeled as shown in Figure 226.
Vpcc a Vpcc b Vpcc c
R R R
L L L
Iinv a Iinv b Iinv c
Vinv a Vinv b Vinv c
VDC LINK Cdclink
Lchopper
Ichopper
Cstorage
Vstorage
Pout
Plosses
Pdc link
Plosses
Pchopper
P+
Figure 226. Powers' definition Using the energy balance theorem we can write
Pchopper = Pdc link + Plosses + Pinvout Pdc link ≈ I chopper ⋅ Vstorage − Pinvout − Plosses ( filter , inverter...)
(230)
Assuming Plosses ≈ 0 , we have
d (Vdc link ) 1 ⋅ C dc link ⋅ ≈ I chopper ⋅ Vstorage − Pinvout 2 dt Linearizing Equation 231 around the nominal point of the energystorage voltage (Vstorage), we can rewrite the equations as 1 2 ⋅ C dc link ⋅ (Vdc link )( s) ⋅ s ≈ I chopper ( s ) ⋅ Vstorage − Pinvout ( s ) 2 2 ⋅Vstorage ⎛ P ( s) ⎞ 2 ⋅ ⎜ I chopper ( s ) − out ⎟ Vdc link ( s ) = C dc link ⎜ Vstorage ⎟ ⎝ ⎠ Figure 227 shows the block diagram of the system model.
2
(231)
(232)
37
Pout Vstorage
I chopper
+ +
2 ⋅Vstorage Cdc link ⋅ s
2 Vdc link
Figure 227. System model Considering Pinvout as a disturbance, the transfer function of the system is
2 d (Vdc ) 1 1 2 ⋅ C dc ⋅ ≈ I chopper ⋅ Vstorage ⇒ ⋅ C dc ⋅ (Vdc )( s ) ⋅ s ≈ I chopper ( s ) ⋅ Vstorage dt 2 2 2 2 ⋅Vstorage Vdc ( s ) = I chopper ( s ) C dc ⋅ s
(233)
The system model and the DC link voltage regulator can be represented in the form of a block diagram as shown in Figure 228.
ˆ Pout ˆ Vstorage
2 Vdc link ref
Pout Vstorage
I chopper
+ Ki
Kp
1 s
+
+ +
+
2 ⋅Vstorage Cdc link ⋅ s
2 Vdc link
+
DC LINK VOLTAGE REGULATOR
SYSTEM MODEL
Figure 228. DC link equivalent system block diagram Under ideal conditions the terms
Pout Vstorage
cancel each other out, resulting in a
simplified block diagram (Figure 229).
38
2 Vdc link ref
+ Ki
Kp
1 s
+
2 ⋅Vstorage
Cdc link ⋅ s
2 Vdc link
+
DC LINK VOLTAGE REGULATOR
SYSTEM MODEL
Figure 229. DC link simplified system block diagram The closedloop transfer function of the simplified DC link system is:
H (s ) =
2 ⋅ Vstorage ⋅ (K p s + K I )
C dc link s 2 + 2 ⋅ Vstorage ⋅ K p s + K I ⋅ 2 ⋅ Vstorage
(234)
Figure 230 shows the system step response for two different regulator gains, using the following system data: • • Cdc link =15700µF Vstorage nominal =1.533 p.u.
Figure 230. DC link voltage regulator step response To avoid a possible saturation of the DC link voltage regulator, the controller with lower gains was chosen. In this case, the control action was the chopper current, and it was designed to always be below 1.pu.
39
Point of common coupling voltage regulator. The voltage support capability of
the inverter depended on the available line impedance back to the utility source voltage, and its dynamics response was directly affected by the line parameters. The regulation of the voltage at the point of common coupling was accomplished by changing the amount of reactive current generated / absorbed (Iinv qr) by the inverter. It was also possible to improve the voltage regulation controlling the real current component. However, as it will be shown, the voltage regulation range was significantly reduced. The system model used in our study (Figure 231) was a simplified version of the actual system. It consisted of the source (modeled as an infinite bus with a series impedance), and the inverter (modeled as a controllable current source). System nonliberalities, such as switching of the semiconductor devices, transformer saturation, etc, were neglected. The system of the equations for Figure 231 is ⎡ I inv a ⎤ ⎡Vsource a ⎤ ⎡ I inv a ⎤ ⎡V pcc a ⎤ d ⎢ ⎥ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎢V pcc b ⎥ = Rsource ⋅ ⎢ I inv b ⎥ + Lsource ⋅ dt ⎢ I inv b ⎥ + ⎢Vsource b ⎥ ⎢ I inv c ⎥ ⎢Vsource c ⎥ ⎢ I inv c ⎥ ⎢V pcc c ⎥ ⎦ ⎦ ⎣ ⎣ ⎦ ⎣ ⎦ ⎣
(235)
Applying Park’s transformation and removing the zerosequence component, it can be shown that V pcc dr = Rsource ⋅ I inv dr + Lsource ⋅ V pcc qr = Rsource ⋅ I inv qr + Lsource ⋅ dI inv dr dt dI inv qr dt + Vsource dr − Lsource ⋅ ω ⋅ I inv qr (236) + Vsource qr + Lsource ⋅ ω ⋅ I inv dr
40
EQUIVALENT SYSTEM MODEL
V source a Rsource Lsource V source b Rsource Lsource Vsource c Rsource Lsource Iinv a Vpcc a Iinv b Vpcc b Iinv c Vpcc c
Vpcc a Vpcc b Vpcc c
R R R
L L L
Iinv a Iinv b Iinv c
Vinv a Vinv b Vinv c
C
Figure 231. Simplified system model Using Laplace’s transformation and reorganizing the terms, we obtain the transfer functions shown in Equation 237
sI inv dr ( s) = −
Rsource 1 ⋅ I inv dr ( s) + w ⋅ I inv qr ( s ) + ⋅ (V pcc dr ( s ) − Vsource dr ( s) ) Lsource Lsource
R 1 sI inv qr ( s) = − source ⋅ I inv qr ( s) − w ⋅ I inv dr ( s) + ⋅ (V pcc qr ( s) − Vsource qr ( s) ) Lsource Lsource
⋅ (V pcc dr ( s) − Vsource dr ( s ) ) Lsource I inv dr ( s ) = ⎛ ⎞ R ⎜ s + source ⎟ ⎜ Lsource ⎟ ⎝ ⎠ 1 − w ⋅ I inv dr ( s) + ⋅ (V pcc qr ( s) − Vsource qr ( s) ) Lsource I inv qr ( s) = ⎛ ⎞ R ⎜ s + source ⎟ ⎜ Lsource ⎟ ⎝ ⎠ w ⋅ I inv qr ( s ) + 1
(237)
(238)
41 Defining the voltage drop, ΔV, as the voltage across the source impedance (Figure 232), it was possible to find the amount of current needed to obtain the desired voltage drop (Equation 238).
ΔV
V source a Rsource Lsource V source b Rsource Lsource Vsource c Rsource Lsource Iinv a Vpcc a Iinv b Vpcc b Iinv c Vpcc c
Figure 232. Source impedance voltage drop I inv dr ( s) = Lsource ⋅ ΔVdr ( s ) ⎛ Rsource ⎞ w2 ⎛ Rsource ⎞ ⎜s + ⎟+ ⎜s + ⎟ + w2 ⎜ ⎜ Lsource ⎟ ⎛ Lsource ⎟ ⎝ ⎠ ⎜ s + Rsource ⎞ ⎝ ⎠ ⎟ ⎜ Lsource ⎟ ⎝ ⎠ (239) −w 1 Lsource Lsource I inv qr ( s) = ⋅ ΔVdr ( s ) + ⋅ ΔVqr ( s ) 2 ⎛ Rsource ⎞ w2 ⎛ Rsource ⎞ ⎜s + ⎟+ ⎜s + ⎟ + w2 ⎜ ⎜ Lsource ⎟ ⎛ Lsource ⎟ ⎝ ⎠ ⎜ s + Rsource ⎞ ⎝ ⎠ ⎟ ⎜ Lsource ⎟ ⎝ ⎠ Lsource
2
w
1
⋅ ΔVqr ( s) +
The Bode plots of the Equation 239 for a system with a source impedance of 10%, and X/R=10 are shown in Figure 233 and Figure 234. Even thought the Bode plots of I inv dr and I inv qr look very similar, the effect on the amount of voltage drop for a given source impedance were significantly different. There are two ways of controlling the amount of voltage drop at the source impedance; regulating ΔVqr ( s ) and/or ΔVdr ( s ) . However, in order to increase system
stability and gain robustness, the phase shift between the utility voltage and the voltage at
42 the point of common coupling must be as small as possible. Therefore, it was preferable to regulate Vpcc by controlling ΔVdr ( s ) exclusively.
I inv qr ( s ) ΔVdr ( s )
I inv qr ( s ) ΔVqr ( s )
Figure 233. Transfer functions of inverter’s quadrature current component
I inv dr ( s) ΔVqr ( s)
I inv dr ( s ) ΔVdr ( s )
Figure 234. Transfer functions of inverter’s direct current component Comparing Figure 233 to Figure 234, it is clear that, in the low frequency range, the cross coupling between I inv qr and ΔVdr is much greater than the direct gain between
43
I inv dr and ΔVdr . This means that the voltage can be regulated by controlling only the
quadrature current. Thus, for instance, the steadystate bus voltage of a system with a source impedance of 10%, and X/R=10 in terms of I inv dr and I inv qr is 0=−
Rsource 1 ⋅ I inv dr ( s) + w ⋅ I inv qr ( s) + ⋅ (V pcc dr ( s) − Vsource dr ( s) ) Lsource Lsource
R 1 0 = − source ⋅ I inv qr ( s) − w ⋅ I inv dr ( s) + ⋅ (V pcc qr ( s) − Vsource qr ( s) ) Lsource Lsource
For I inv dr = 0 ,
V pcc = V pcc dr + V pcc dr =
2 2
(240)
(V
source dr
− wLsource I inv qr ) + (Vsource qr + Rsource I inv qr ) (241)
2 2
For I inv qr = 0 ,
V pcc = V pcc dr + V pcc dr =
2 2
(V
source dr
+ Rsource I inv dr ) + (Vsource qr + wLsource I inv dr ) (242)
2 2
If I inv qr = −1 pu (capacitive), Vsource dr = 1 pu , Vsource qr = 0 pu , X source = 0.1Ω, and X source Rsource = 10 , then V pcc = 1.1 pu .
The amount of I inv dr needed to obtained the same voltage would be
V pcc = 1.1 =
(V
source dr
+ Rsource I inv dr ) + (Vsource qr + wLsource I inv dr )
2
2
⇒ I inv dr = 3.67 pu
This proves that for a system where the ratio X/R>1, the PCC bus voltage can be regulated in an efficient way by injecting only quadrature current. The design of the voltage regulator requires the knowledge of the source impedance. However, this impedance varies with time and on online estimation can be very complex if transient situations are present in the system.
44 For steadystate conditions the transfer function between ΔV and I inv qr can be reduced to just the source impedance of value Xsource=wLsource. Therefore, the control block diagram of the voltage regulator can be interpreted as shown in Figure 235.
Vsource dr V pcc ref
positive sequence
+ Ki
Kp
1 s
POSITIVE SEQUENCE EXTRACTION
+ +
I inv dr ref
CURRENT CONTROLLER
I inv dr
SOURCE IMPEDANCE
ΔVdr +
+
V pcc
VOLTAGE REGULATOR
SYSTEM MODEL
Figure 235. Voltage regulator system block diagram The current controller is represented as a second order transfer function in Equation 243. H current regulator ( s) =
0.0004 s + (0.015 + K p current
2
K p current
regulator
⋅ s + K I current regulator
regulator
)⋅ s + K
(243)
I current regulator
For Kp=1 and Ki=36 the current controller transfer function is
H current regulator ( s ) = I inv I inv ref
=
s + 36 0.0004 s + 1.015s + 36
2
The positive sequence extraction transfer function can be modeled in continuous time as shown in Figure 236.
Integrator
V pcc
+ Td Transport delay
1 Td s
V pcc
positive sequence
Figure 236. Positive sequence extraction algorithm equivalent system
45 For the simplified voltage regulator system, there was not need for any transformation. Only the modeling of the positive sequence 1 cycle sliding window filter (Td=16.666msec) was required (Figure 2 37).
V pcc ref
positive sequence
+ Ki
Kp
1 s
+ +
I inv dr ref
s + 36 0.0004s 2 + 1.015s + 36
I inv dr
wLsource
ΔVdr +
+
Vsource dr
V pcc
1 Td s
+ Td
VOLTAGE REGULATOR
SYSTEM MODEL
Figure 2 37. Voltage regulator detailed block diagram The system was further simplified assuming that the current regulator time response was much faster than voltage regulator time response (Figure 2 38).
V pcc ref
positive sequence
+ Ki
Kp
1 s
+
I inv dr ref
1
I inv dr
wLsource
ΔVdr +
+
Vsource dr
V pcc
+
1 Td s
+ Td
VOLTAGE REGULATOR
SYSTEM MODEL
Figure 2 38. Voltage regulator simplified control diagram Figure 2 39 shows the system step response for a given voltage regulator under different system conditions.
A
B
Figure 2 39. System response to a 5% change in voltage reference for Kp=2 Ki=250. A) With saturation. B) Without saturation
46 The settling time was a function of the system impedance, and therefore it was not possible to predict the system response without knowing the source impedance. One solution was to use an adaptive parameter tuner capable of adjusting the regulator gains according to the identified plant dynamics. The block diagram of the adaptive control scheme is shown in Figure 240.
Adaptive Parameter Tuner
V pcc ref
positive sequence
+ Ki
Kp
1 s
+
+
I inv dr ref
PLANT
V pcc
1 Td s
+ Td
Figure 240. Adaptive control scheme However, due to the difficulty in distinguishing between changes in the system impedance, load variations, and utility voltage, a simpler but robust solution was adopted. It consisted of a classic PI regulator, with gains that were tuned in the field. The drawback was a slower response that could occur for any given condition.
Power regulator. The power regulator required to control the power fluctuations of
a wind farm was the most complicated control scheme among all the described so far. It involved nonlinear algorithms which made the system very sensitive to instabilities due to non forecasted conditions. The basic idea behind the power regulator was to determine the amount of the real power required by the inverter in order to meet the utility’s power fluctuation limits. A generic power regulator control scheme is shown in Figure 241.
47
Iwinda Vpcca Iwindb Vpccb Iwindc Vpccc
X
Ramp Rate Average
Inst
V storage
Centering algorithm
X
+ + +
Wind Power
Limiters
X
+ +
PowerInverter Reference
ESA required power
+
Allowedcenteringpower
Figure 241. Power Regulator general control scheme First the wind farm power was calculated and the compared to rateof change limits (Table 22). If limits were exceeded, the difference would be compensated by the inverter. The centering algorithm was a control scheme used to hold the energy storage near its nominal value, to be ready for the next supply or absorption cycle. If the wind farm power was causing the limiters to activate, this centering action would not take place. That way a higher priority was given to the power limiters. Table 22. Rateofchange limits or PPA for a 10 MW wind farm Parameter Value Instantaneous 1 MW change per 2 second scan Sub minute average average of 0.3MW change per 2 second scan for any 60 second period Ramp rate 2 MW per minute up, and down when operationally possible The first proposed control scheme of the power limiter consisted of a high pass (HP) filter which canceled the high frequency power fluctuations independently of the rateofchange limits. Figure 242 shows the HP filter control block diagram. A small bias power was added to assure the charging of the energy storage system. This approach had three major drawbacks:
48
• • •
Rateofchange limits might not meet unless inverter’s power and energy requirements were increased. Optimal cutoff frequency design was unknown. Inverter duty cycle was higher than the next approaches.
Wind Farm Output High Pass Filter Storage Nominal State of Charge + Centering Charge/ Discharge Constant + + Centering + Inverter Power
Storage (integrator)
+
Figure 242. Power limiter 1. Control block diagram Wind farm power data records were used to test the power limiter control scheme under different system conditions. Figure 243 and Figure 244 show the inverter requirements as well as the system performance for different cutoff frequencies. Note: Inverter size requirements cannot be extrapolated from the 15 minutes simulation. A more detailed study must be performed using long windpower data records (perhaps years). It was also not cost effective to correct every possible scenario. Therefore, the number of times and/or amount that the wind farm may exceed the power index limits, with a Power Stabilizer installed, needs to be determined, when traded off against inverter and storage ratings. The main advantages of the HP power limiter were its simplicity and its stability under unexpected power fluctuations. The control scheme was implemented in MATLAB in order to test the power limiter performance under different system conditions. Appendix B gives more information on the MATLAB code.
49
A
B
C
Figure 243. Power limiter 1. Performance using different cutoff frequencies (unlimited power and energy). A) Power to utility. B) Powerstabilizer output power. C) Power stabilizer’s energy storage.
A
B
C
Figure 244. Power limiter 1. Performance using different cutoff frequencies (Pinverter=1.0 MW and Einverter=±8.5 MJ). A) Power to utility. B) Powerstabilizer output power. C) Power stabilizer’s energy storage.
50 The second proposed control scheme of the power limiter consisted of a power limiter with the three rateofchange limiters in cascade (Figure 245). The ramp limit was first applied, followed by the sub minute limit, and finally the scantoscan limit.
Input
R +R +S
S
ScantoScan Limiter Subminute Limit Calculator
Output
R
S
Ramp Limit Calculator
Figure 245. Power limiter 2. Limiters details As mentioned earlier, the “centering” of the energy storage energy was needed so that it could supply or absorb power from its nominal state. Therefore this energy must be taken into account when calculating the rateofchange limits, since it was real power being interchanged with the system. Thus, the power limiter control scheme had two limiters in parallel (Figure 246); one limiter acted upon the wind farm output only, another limiter acted on the wind farm power plus the desired centering power. If the inverter were big enough to supply or absorb the excess power and energy from the wind farm, the power limiter would keep the power within that allowed by the rateof change limits. The problem occurred when the power or energy storage is beyond the rating of the inverter, since the history of what is actually delivered to the utility could be wrong. Thus, a saturation limiter was needed in order to adjust the buffer input data. The control scheme was implemented in MATLAB in order to test the power limiter performance under different system conditions. Appendix B gives mode information on the MATLAB code.
51
Desired Power (Wind+Storage Centering) + Previous scans (BUFFER)
+
+
Limiter
Last thing to be updated/evaluated
+ + + + 
Wind Farm Output
Desired Centering
Limiter Storage Nominal Centering Charge/ Discharge Constant + State of  Charge + + + + + ESA Required Supply/Absorb + Centering Power Allowed
+
+

1 PU
Inverter Power
1 PU
Power Limiter
Figure 246. Power limiter 2. Control block diagram Wind farm power data stored on a 2 second basis was used to test and size the power limiter control scheme under different scenarios. The following figure shows the system performance for a period of 15 minutes.
Zoom in
Figure 247. Power limiter 2. Compensation performance
52 The inverter power and energy required to meet the rateofchange limits for the 15 minute simulation is shown in Figure 248.
A
B
Figure 248. Power limiter 2. Inverter response for a sampling time of 2 seconds. A) Powerstabilizer output power. B) Power stabilizer’s energy storage. To test the stability of the control algorithm, saturation effects were taken into account. Figure 249 and 250 show the system performance for different underrated inverters. Rateofchange limits were not met, but the system was stable. It is very difficult anticipate all of the types of misbehavior that might occur in the system, and that there could be unusual power fluctuations from the wind farm could get the inverter into a mode where it would continue to swing the power around in an undesirable manner. Therefore it was recommended to include some type of “misbehavior detector” in the power limiter control scheme to protect the inverter and the system.
53
A
B
Figure 249. Power limiter 2. Inverter response for different power ratings. Sampling time 2 seconds .A) Powerstabilizer output power. B) Power stabilizer’s energy storage.
Zoom in
A
B
Figure 250. Power limiter 2. Inverter response for different ESS sizes. Sampling time 2 seconds. A) Powerstabilizer output power. B) Power stabilizer’s energy storage.
54 The third control scheme considered for the power limiter consisted of a power limiter with the three rateofchange limiters in parallel (Figure 251). The limiter’s input was the power out to the utility instead of the wind power, plus the centering power, for a more accurate control of the power fluctuations seen by the utility. Each limiter determined the maximum and minimum amount of power allowed changing per scan. Then the absolute maximum and minimum were calculated in order to establish the centering power limits and the required power from the inverter.
Wind Farm Output + Power to Utility + Storage (Joules or Volts) Upper Centering Limit
+
Inverter 1
Upper
Ramp Limiter
Upper Lower

+ + Inverter Power Before Centering + + +
Total Inverter Power
Min
Upper
Subminute Limiter
Lower
These should not have a simulataneous nonzero output + +
+
+ + 1
Upper
ScantoScan Limiter
Max
Lower
Lower

Storage Setpoint
Lower Centering Limit 1
Centering Power
lower
upper upper
+ +
Kcenter or other controller
lower
Figure 251. Power limiter 3. Control block diagram Figure 252 shows the response of the power limiter 2 using the same windpower data records used previously. It can be concluded from Figure 247 and Figure 252 that both power limiters have the same response under normal conditions.
55
Figure 252. Power limiter 3. Compensation performance
A
B
Figure 253. Power limiter 3. Inverter response for a sampling time of 2 seconds. A) Powerstabilizer output power. B) Power stabilizer’s energy storage.
56
PerUnit System Model
The reasons why to convert system variables into per unit are:
• • •
System easily scalable Facilitate fixed point operations Power system components can be treated uniformly no matter what voltage level The two variables selected as based values are
Vbase = V max I base = I max
line − neutral line
= 1 pu (V )
= 1 pu ( A)
Thus, the rest of variables can be calculated as
• •
Base Impedance: Z base = Base Power (3 phase):
Pbase = Pinverter rate
power
VRMS
line neutral
I RMS line
=
Vbase = 1Ω I base
Vbase I base ⋅ = 1 .5 W 2 2
= 3 ⋅ V RMS line neutral ⋅ I RMS line = 3 ⋅
Inverter OutputFilter Design
The purpose of inverter filter was to attenuate the high frequency switching harmonics produced by the inverter in order to avoid disturbing other EMI sensitive equipment on the grid. Its optimal design is very complex and it involves coupled design constraints and nonlinear equations. The inverter topology for which the filter would be designed was a 6pulse 3wire inverter, without DC bus midpoint tapped to neutral (Figure 254), where power semiconductors were considered as ideal switches.
57
Iinv a Iinv b Iinv c
Vinv a Vinv b Vinv c
C
Figure 254.Inverter topology
Harmonic content
The typical linetoneutral and linetoline voltage of a three phase inverter using a PWM strategy is shown in Figure 255.
A
B
Figure 255. Linetoline and linetoneutral voltage of a three phase inverter Figure 256 shows the harmonic spectrum of the linetoline voltage under the following conditions:
• • •
fsw = 4860 Hz f1=60 Hz Frequency Modulation, m f =
switching frequency f = sw = 81 fundamental frequency f1
• • • •
Vdc = 2.04 pu Vsource max linetoneutral = 1 pu Peak amplitude of the control signal = Amplitude of the triangular signal = 1 Vmax desired Vdc _ link 2
58 • Amplitude modulation, ma = peak amplitude of the control signal =1 amplitude of the triangular signal
Figure 256. RMS Linetoline voltage harmonic spectrum The main harmonic components of the linetoline output voltage were calculated using the tabulated table in [28] as Vinverter
rms l −l
(h ) = Vdc ⋅ K
(244)
K values for the different harmonics can be found in Table 23. The frontend inverter was designed to behave as a static synchronous generator (SSG) capable of producing a set of adjustable voltages, which may be coupled to an ac power system to exchange independently controllable real and reactive power. This was accomplished by the usage of a synchronous inductor which linked the inverter output to the ac supply side (Figure 257).
59 Table 23. Generalized Harmonics of linetoline voltage for a large and odd mf that is a multiple of 3 K (Generalized Harmonics of Vrms ll) ma h 0.2 0.4 0.6 0.8 1 1 0.122 0.245 0.367 0.490 0.612 mf ± 2 0.010 0.037 0.080 0.135 0.195 mf ± 4 0.005 0.011 2mf ± 1 0.116 0.200 0.227 0.192 0.111 2mf ± 5 0.008 0.020 3mf ± 2 0.027 0.085 0.124 0.108 0.038 3mf ± 4 0.007 0.029 0.064 0.096 4mf ± 1 0.100 0.096 0.005 0.064 0.042 4mf ± 5 0.021 0.051 0.073 4mf ± 7 0.010 0.030
synchronous Inductor
Vsource
Inverter
L I
Vinv
SSG
Figure 257. Static Synchronous Generator diagram Thus, the inverter voltage harmonics would generate current harmonics, which amplitude would not only be a function of the inverter’s mf and ma, but the synchronous inductor as well. The inverter current harmonics can be calculated as: • For h=1 (fundamental frequency): Vinverter rms l −l − Vsource rms l −l 1 I rms (h ) = ⋅ 2πf1 ⋅ h ⋅ L 3 For h>1 (assuming no harmonics are present in the utility bus voltage): Vinverter rms l −l (h) V ⋅K 1 1 I rms (h ) = ⋅ ⋅ = dc 2πf1 ⋅ h ⋅ L 3 3 2πf1 ⋅ h ⋅ L
(245)
•
(246)
Where f1 is the fundamental frequency.
60 The inverter current harmonics must be attenuated in order to avoid interference with communication circuits and other types of equipment, the increase of system losses, resonance conditions, and malfunction of power electronic devices. The IEEE 519 Standard [29] is a recommended practice to be used for guidance in the design of power systems with nonlinear loads and therefore should be taken into account on the design of the switching ripple filter. The worst case scenario is for general distribution systems (120V through 69000V) with a TDD < 5% for current harmonics below the 50th. TDD is the total demand distortion and is defined as
TDD(%) =
∑I
h=2
50
2 h
IL
⋅100
(247)
The maximum demand load, which is IL, can be estimated from data used to size the inverter isolation transformer.
Switching frequency
The selection of the switching frequency was based on the recommendations given by [28], which stated that:
• • • •
Because of the relative ease in filtering harmonic voltages at high frequencies, it is always desirable to use as high a switching frequency as possible. In most applications, the switching frequency is selected to be either less than 6 kHz or greater than 20 kHz to be above the audible range. In order to avoid subharmonics, synchronous PWM must be used. Synchronous PWM requires that mf be an integer. In the 3wire threephase inverters, only the harmonics in the linetoline voltage are of concern, and only the odd harmonics exit as sidebands, centered around mf and its multiples, provided mf is odd. If mf is chosen to be an odd multiple of 3 the most dominant harmonics in the linetoline voltage (even harmonics of mf) will be cancelled out.
•
61
•
For high power applications (kVA) where switching losses play a major role in the overall system design, the switching frequency is usually selected between 3 kHz and 5 kHz. Taking all these elements into consideration, the optimal switching frequency
selected for the inverter and for the chopper was f sw = f1 ⋅ m f = 60 ⋅ 81 = 4860 Hz
Passive filter design
The switching ripple filter topology selected for the inverter filter was based on a LCL network as shown in Figure 258.
Isolation transformer equivalent impedance Filter or synchronous Inductor
Inverter
Vsource Igrid
Lt Cf
Filter capacitor
Lf Iinverter
Vinv
LCL switching ripple filter
Figure 258. LCL filter topology The main advantages of the LCL filter compare to the L filter are summarized in Table 24. Table 24. L filter vs. LCL filter Characteristics L filter Control method Hysteresis controllers Attenuation above resonance frequency I grid ( s) 20dB ( first order system) LCL filter Fixed switching frequency control methods 60 dB (third order system)
Vinverter ( s ) Total line filter inductance for a given grid current ripple magnitude
High line inductance, and therefore poor transient performance
Low line inductance, and fast transient performance
62 The LCL inverter filter equations are the following:
Vinverter − Vc f = L f ⋅ Vc f − Vsource = Lt ⋅ I inverter − I grid dI inverter dt dI grid
dt dVc f = Cf ⋅ dt
(248)
Applying Laplace’s transform, the LCL inverter filter can be modeled as shown in Figure 259.
Figure 259. LCL equivalent block diagram The inverter filter was divided into two different equivalent filter models based on the frequency under study. Thus, we have:
Equivalent filter circuit configuration at fundamental frequency. Under these
conditions the inverter was considered as an ideal sinusoidal voltage source. This was the lineal inverter model valid for the design of the system controllers. Figure 260 shows the filter equivalent system at fundamental frequency.
Vsource (f1)
Lt Cf
Lf
Vinv (f1) Iinverter (f1)
Igrid (f1)
Figure 260. Single phase equivalent filter model at the fundamental frequency
63
Equivalent filter circuit configuration for the h harmonic (for h>1). At high
frequencies the converter was considered to be a harmonic generator, while the grid can be considered shortcircuited.
Lt
Vsource (hf1)= 0
Lf Cf
Vinv (hf1) I inverter (hf1)
I grid (hf1)
Figure 261. Single phase equivalent filter model at the hth harmonic Thus, the current ripple attenuation, passing from the inverter side to the grid side can be calculated as
I grid
rms
( s)
l −n
Vinverter rms I inveter
( s)
=
1 s ⋅ Lt ⋅ C f ⋅ L f + s ⋅ ( Lt + L f )
3
rms
( s) ( s)
Vinverter rms I grid I inverter
=
s 2 ⋅ C f ⋅ Lt + 1 s 3 ⋅ Lt ⋅ C f ⋅ L f + s ⋅ ( Lt + L f )
(249)
l −n
rms
( s) (s)
=
rms
1 s ⋅ C f ⋅ Lt + 1
2
There are different ways of designing the LCL inverter filter, as well as different specifications or constrains. Table 25 is a summary of the most common parameter used to design the inverter filter. It can be inferred from Table 25 that there is no a unique approach or limit when designing the LCL filter. The LCL parameters selected for the inverter filter design are
X L f = 10% ⇒ L f = 265.25 μH X C f = 3333.33% ⇒ C f = 79.577 μF X Lt = 5% ⇒ Lt = 132.62μH ( typical transformer equivalent impedance)
Table 25. LCL filter design Parameter Description Equations Current Maximum Peak to Peak For ma ≤ 1 ⎡ ripple value Note: Maximum current ripple at Vsource(t)=0 differs from Vsource(t)=Vmax Most significant harmonic components
⎢Vsource ΔI ripple max = Max ⎢ ⎢ ⎢ ⎣
max
⎤ ⎛ m ⎞ ⋅ ⎜1 − a ⎟ ⋅ 2 Vdc ⋅ 3 ⋅ ma ⎥ 2⎠ ⎝ ⎥ , 3 4 ⋅ Lf ⋅ fsw 4 ⋅ Lf ⋅ fsw ⎥ ⎥ ⎦
l −n
Limits Peak to Peak value: • 15%25% of rated current [35] • 31% of rated current [32]
For ma ≈1
ΔI inverter ripple max ≈ Vdc 7 ⋅ L f ⋅ f sw
For ma ≈1
1 I inverter rms (h = m f ± 2 ) ≈ ⋅ 0. 2 ⋅ 2πf1 ⋅ h ⋅ L f 3 Vdc
Attenuation Laplace domain of harmonic Frequency domain content Voltage drop across the filter during normal operation
I grid rms ( s) I inverter
I inverter
rms
( s)
=
1 s ⋅ C f ⋅ Lt + 1
2
Most significant harmonic component (mf±2) • 10% of rated current [30] • 1.6% of rated current [31] • 0.2 attenuation [30] • 0.5 attenuation [32]
64
I grid rms (h = m f − 2)
rms
(h = m
f
− 2)
=
Z C f ( f1 ⋅ h ) + Z Lt ( f1 ⋅ h )
Z C f ( f1 ⋅ h )
ΔVmax L f = I inverter max ⋅ 2πf1 ⋅ L f
Filter resonant frequency Filter capacitor reactive power
f resonant =
1 2π C f ⋅ (Lt // L f
)
Cf =
1 QC f (%) ⋅ Pinveter rated power ⋅ 2 100 3 ⋅ 2 ⋅ π ⋅ f 1 ⋅ V source rms l − n
Total value of inductance should be lower than 10% to limit the voltage drop and the dc link voltage[30],[33] • 1.7% on the inverter kVA base [34] Resonance frequency between 10 times the line frequency and half of the switching frequency[30][33] QCf: • <5%[30][33][34] • 15% [35]
•
65 The electrical characteristics of the LCL filter for the system parameters given Table 27 in are summarized in Table 26. Table 26. LCL equivalent impedance with damping resistance Parameter Current ripple (peak to peak) Current ripple (most significant harmonic) Harmonic attenuation Max Voltage drop Filter resonant frequency Filter capacitor reactive power Equation
ΔI inverter current ripple max ≈ Vdc 7 ⋅ L f ⋅ f sw
Stiff system 0.2264 pu (App) 0.00003 pu (Arms) 18.5 dB 0.1 pu (Volts) 1897 Hz 3.0% VAr ( I C f MAX = 0.03 pu )
V 1 I inverter rms ( f sw − 2 ⋅ f1 ) ≈ dc ⋅ 0.2 ⋅ 2π ( f sw − 2 ⋅ f1 ) ⋅ L f 3
ZC f ( f sw − 2 ⋅ f1 ) I grid rms ( f sw − 2 ⋅ f1 ) = I inverter rms ( f sw − 2 ⋅ f1 ) ZC f ( f sw − 2 ⋅ f1 ) + Z Lt ( f sw − 2 ⋅ f1 )
ΔVmax L f = I inverter max ⋅ 2π ⋅ f1 ⋅ L f
f resonant = 1 2π C f ⋅ ( Lt // L f )
2 C f ⋅ 3 ⋅ 2 ⋅ π ⋅ f1 ⋅ Vsource rms l −n ⋅ 100 Pinveter rated power
QC f (%) =
Table 27. Perunit system Variable VMAX line− neutral VRMS line−line VRMS line−neutral I MAX inverter nominal I RMS inverter nominal Z base Pinverter Vdc
Passive filter damping
Per unit 1.0 1.22474 0.70677 1.0 0.70711 1.0 1.5 2.0412
To determine the system stability, the LCL inverter filter damping resistances must be taken into account when calculating the system attenuation at resonance frequency. The system resistors are given in Figure 262.
66
Vsource
Rt Rt Rt Lt Lt Lt Cf Cf Cf Lf Lf Lf Rf Rf Rf
Vinveter
Figure 262. LCL equivalent impedance with damping resistance Using a X/R=10 for all inductors, the damping resistances of the LCL filter are
X L f = 10% ⇒ X Lt = 5% ⇒ X Lf Rf = 10 ⇒ R f = 0.01Ω
X Lt Rt
= 10 ⇒ Rt = 0.005Ω
The LCL inverter filter could resonate due to harmonics generated either from the source or from the inverter. The two equivalent circuits are
Rt Lt
Vcapacitor
Cf
Lf
Rf
Vinveter
Vsource
Rt
Lt
Vcapacitor
Cf
Lf
Rf
A Figure 263. Single phase harmonic generator equivalent circuits. A) Inverter as a harmonic generator. B) Source as a harmonic generator Thus, the
Vcapacitor Vinverter
B
Vcapacitor V
transfer functions are given in Equations 250 and 251: (250)
= 1 + Z Lf
1 ⎛ 1 1 ⎞ ⎟ ⋅⎜ + ⎜ ZC Z Lt ⎟ ⎝ f ⎠
1
Vcapacitor Vsource
=
(251)
⎞ ⎟ ⎟ ⎠
⎛ 1 1 + 1 + Z Lt ⋅ ⎜ ⎜ ZC Z Lf ⎝ f
67 The Bode frequency response of both models is given in Figure 264.
Figure 264. LCL gain frequency response It can be deduced from Figure 264 that there is a significant gain at the resonance frequency (small system damping resistance), and therefore harmonics close to this frequency could be amplified by the LCL filter. From the inverter point of view there are two sources of disturbances: 1. 2. Voltage harmonics due to the PWM Disturbances amplified by the current regulator
Figure 265. Inverter frequency analysis
68 Figure 265 shows the current regulator frequency response, the filter frequency response, and the inverter linetoneutral harmonic spectrum. It can be inferred from Figure 265 that the current regulator attenuates any signal with a frequency > 400Hz (cutoff frequency), and the inverter voltage harmonics do not make the LCL filter resonate. From the point of view of the voltage source there are two sources of disturbances: • • Large infrequent transient, such as capacitor bank switching. This type of disturbance may ring the filter, but it will damp out in a few cycles. System harmonics. A detail study of the system it is required to determine if it is likely.
DirectCurrent Link Capacitor Design
The DC link bus voltage had the following constrains: • • • IPM Max voltage 1200V. Line to line voltage 480 V. This would allow the use standard isolation transformers Minimum DC link voltage = 1.1 ⋅ Vmax line −to −line = 1.1 ⋅ 480 ⋅ 2 = 750 V . Minimum voltage to guarantee system controllability. • IPM trip level = 900V. Capacitor switching voltage transients tend to raise the DC link voltage and could damage the IGBT’s. A trip level of 900 V allows ridingthrough the majority of the capacitor switching transients. Low DClink voltage was desirable in order to reduce the switching losses. Given these system restrictions the selected DClink voltage was 800V. In per unit V dc −link = 800 ⎛ 480 ⋅ 2 ⎞ ⎟ ⎜ ⎜ 3 ⎟ ⎠ ⎝ = 2.0412 pu
•
The dimensioning of the DC link capacitor was determined by the following constrains:
69 • • • • Maximum permissible current stress for a required working life (current ripple) Existence of any zero sequence component System controllability ( avoid large gains) Max ripple voltage 10% For a traditional STATCOM configuration, the DClink capacitor is necessary for an unbalanced system operation and harmonic absorption. For a configuration with energy storage, the DC link capacitor main function is to reduce the DC current ripple from/into the ESS and therefore a smaller DClink capacitor could be used. The time constant selected for our study was the DClink capacitor in perunit model is DC − link Energy = 21.5 msec . Thus, Inverter Power
DC  link Energy pu DC  link Energy = 22 m sec = Pinverter pu Inverter Power DC  link Energy pu 1.5W
⇒ DC  link Energy pu = 0.033J 1 2 ⋅ C dc −link ⋅ Vdc −link ⇒ C dc −link ≈ 15700 μ F 2
DC  link Energy pu =
Energy Storage Design
The Energy Storage System (ESS) design parameters were • The voltage at the energy storage system (ESS) was designed to vary from 95% to 0.95*50% of the DC link voltage.
Total Energy in the ESS = 20.45 sec Inverter Power
•
Note: More on the design and size of the Power Stabilizer energy storage system can be found in [36]. The center voltage of the ESS can be calculated as
70
1 1 2 2 2 2 ⋅ Cstorage ⋅ Vstorage max − Vstorage center = ⋅ Cstorage ⋅ Vstorage center − Vstorage min 2 2 (252) 1 2 2 Vstorage center = ⋅ Vstorage max + Vstorage min 2
(
)
(
)
(
)
Thus, for a system with a Vdc nominal = 2.0412 pu , the ESS nominal voltage was
Vstorage max = 0.95 ⋅ 2.0412 = 1.9391 pu Vstorage min = 0.95 ⋅ 0.50 ⋅ 2.0412 = 0.9695 pu Vstorage center = 5 1 2 2 ⋅ Vstorage max + Vstorage min = 1.9391 ⋅ = 1.533 pu 8 2
(
)
Figure 266 shows the relationship between the capacitor voltage and the energy storage. The capacitance of the ESS in perunit can be calculated from the time constant
Total Energy in the ESS as Inverter Power
Max Energy pu Max Energy = 20.45 sec = ⇒ Max Energy pu = 30.67 J Power Pinverter pu Max Energy pu = 1 2 ⋅ Cstorage ⋅ Vstorage 2
max
⇒ Cstorage = 16.31 F
Figure 266. Capacitor Voltage vs. Energy Storage
71
Chopper Inductor Design
The purpose of chopper inductor was to reduce the current ripple produced by the chopper in order to guarantee the ESS working life (Figure 267). The current ripple current selected for this application was 30%. Under this condition the chopper inductance in per unit is calculated as shown in Equation 253. ΔVchopper = Lchopper ⋅ dI chopper dt , where ΔVchopper = Vdc −link − V storage (253)
Vdclink
Cdclink
Ichopper
Lchopper
Cstorage
Vstorage
Figure 267. ESSChopper topology In the worst case scenario the DClink voltage is at its nominal value, while the voltage at the ESS is at its minimum. Thus, the maximum voltage drop across the chopper inductor is
Δ Vchopper
max
= Vdc − link nominal − Vstorage min = 2.0412 − 0.9695 = 1.0717 pu
Discretization of the chopper inductor voltage drop differential equation yields the Equation 254. ΔVchopper = Lchopper ⋅ ΔI chopper Δt 1 1 ⋅ as shown in Figure 268. 2 f sw (254)
Where ΔI chopper is the ripple current, and Δt =
72
Tsw Triangular waveform
Time Δt
Ichopper
ΔIchopper
Lchopper
Time Vdclink=2.0412 pu
Cdclink
ΔIchopper
Lchopper Cstorage
Vstorage=0.9695 pu
Figure 268. Equivalent circuit for maximum current ripple calculation Thus, the chopper inductor in per unit is:
⎫ ⎪ Lchopper = = ⎪ ΔI chopper ΔI chopper ⎪ ⎪ ⎪ ⎪ ΔI chopper = 0.03 ⋅ I chopper rated (30% ripple) ⎬ ⎪ ⎪ ⎪ Pinverter nominal 1.5W I chopper rated = = = 0.7352 pu ( A)⎪ Vdclink 2.0412 ⎪ ⎪ ⎭ ΔVchopper max ⋅ Δt 1.0717 ⋅ 1 2 ⋅ 4860
Lchopper = 500 μH
PerUnit System Model Summary
Table 28 is a summary of the perunit system parameters used in the control and modeling of the system.
73 Table 28. Perunit system parameters Variable Perunit Model 1.0V VMAX line− neutral VRMS line−line VRMS line− neutral I MAX inverter nominal I RMS inverter nominal Z base Pinverter Vdc no min al Vstorage center C dc link C storage Lchopper Rchopper Lf Rf Cf Lt Rt 1.22474V 0.70677V 1.0A 0.70711A 1.0Ω 1.5W 2.0412V 1.533V 15700 µF 16.31F 500.0µH 0.018849Ω 265.25µH 0.01Ω 79.57 µF 132.63µH 0.05Ω
Simulated Model
Specs
21.5 msec time constant 20.45 sec time constant (at maximum ESS voltage) 30% current ripple X/R=10 10% Impedance X/R=10 3% VArs (3333.3% Impedance) 5% Impedance X/R=10
Power Systems Computer Aided Design (PSCAD) was used for the modeling and simulation of the power stabilizer. The PSCAD model was based on the perunit system, so that the system performance could be compared to any given unit size. Figure 269 shows the main components of the system. The PSCAD model can be divided into two main subsystems; the electric system (Figure 270) and the control algorithm (Figure 271).
74 The majority of components used in the modeling were part of the PSCAD library. Only the power limiter 2 had to be implemented in FORTRAN and linked to PSCAD given the complexity of its design.
UTILITY SYSTEM
Xsource Iwind Vpcc WIND FARM Lxfrm Cf LCL Vf Lf Iinv Vinv INVERTER Vdc Cdc
Chopper Ichopper Vchopper ESS Vstorage
Figure 269. System overview
1 V Vutility A B C Vpccc 0.00013262911 0.005 Vfc R=0 Vpcca Vpccb 0.00013262911 0.005 0.00013262911 0.005 Vfa Vfb Iinva Iinvb Iinvc 0.01 0.00026525 0.01 0.00026525 0.01 0.00026525 Vpwma Vpwmb Vpwmc 4 2 g4 2 g6 2 g1 2 g3
3 2 g5
5 2 gch1
5
15700.0
+
V_dc
0.0005 0.018849 Vstorage 6 2 g2 2 2 gch2 2 16310000.0
LCL filter
Inverter
DC link bus
Chopper
Figure 270. Perunit electric system model Table 29 shows the model performance as well as the designed specifications for comparison. It can be observed that designed and simulated system closely agree.
+
79.57
79.57
79.57
Kp
1 s
1pu
+ +
1 pu
1pu
Ki
1pu
PI regulator
Iwinda V pcca Iwindb V pccb Iwindc V pccc
X
RampRate Av erage
Inst
Vstorage
Centering algorithm
X
+ + +
Wind Power
Pinv erter ref erence updated every0.1seconds
V pcc_offset
Klimit
Limiters
X
+ +
PowerInverter Reference
ESA required power
+
Allowedcenteringpower
40 kHz
Idrinv Idref +
V pcc_offset
Current Limiter
Vdf wLIqinv + + V dinv
2 2 Vdqinv = Vdinv + Vqinv
+
Constant angle Max Magnitude
V apu + + + Vflata + + + PWM Vb PWM Vc 
1.5pu
Idref Vdr
PI regulator
1.5 pu
V dqinv
0
V dqinv_limited
Vdinv_limited =
Vdqinv_limited 1+ K
2 dqinv
Vdinv _limited Vqinv _limited
iPark V1
PWMVa
Power Limiter
V pcc ref
+ 
Ki
1 s
M
Kp
M
M
+ +
M M
Iqref + Iqr inv
K dqinv =
PI regulator
Vqinv Vdinv
K dqinv
+ + V qf + wLIdinv
Vqinv
Vqinv_limited = K dqinv ⋅Vdinv_limited
Vdsinv drqr dsqs Vqsinv
sin(theta) cos(theta)
iClark V1
ds qs abc
V bpu V c pu
Vpccpositivesequence
M
Voltage regulator
V dc
(formodulationindex calculation)
Vflatb + 2 Vflatc
+ +
V flat
Current regulator
Limiters & Transformations Flattop
To current regulator
Rotating Reference Frame transformation & positive sequence calculation
V pcca V pccb V pccc
Clark V1
75
abc ds qs Vos
Vds V qs Vds V qs
PLL
PLL (2 sec time constant) Theta sin(theta) cos(theta)
Park V1
Vds Vqs Vqs
Delay (t1/f /4) Delay (t1/f /4)
Iinva Iinvb Iinvc Vdr Vqr
To current regulator
Clark I1
abc ds qs Ios
Ids Iqs
Park I1
ds qs dr qr
sin(theta) cos(theta)
Idrinv Iqr inv
dsqs dr qr
Vds + 
sin(theta) cos(theta) 0.5
Vds positivesequence Vqspositivesequence
Park V1
positivesequence
0.5
sin(theta) cos(theta)
Iinva Vfa Iinvb Vfb Iinvc Vfc
V 2dcref
X
V2dc + +
+ 
PI regulator
X
Inv erter Power
+ +
Ichopperref + Ichopper
KL
+ Vstorage
Vchopper
Vdc _link
Vchopper_limited
Vchopperpu + Vdc PWMchopper
Vdc _link
X
Vstorage
(formodulationindex calculation)
Chopper Control Scheme
Figure 271. Power Stabilizer Control Scheme
X
+ +
ds qs dr qr
V drpositivesequence Vqrpositivesequence
X
+ +
Slidingwindowfilter (1cycle)
Filter
V pcc positivesequence
To PCC voltage regulator
76 Table 29. Designed system results and simulated system results comparison. System conditions: V dc link =2.04 pu, V source max =1 pu, stiff system Parameter Model response Design system/Comments ⎤ ⎡ ⎛ m ⎞ V Inverter ⋅ ⎜1 − ⎟⋅2 ⋅ 3⋅m ⎥ ⎢V 2 ⎠ ⎝ 3 ⎥ , ΔI = Max⎢ current 4⋅ L ⋅ f 4⋅ L ⋅ f ⎥ ⎢ ⎥ ⎢ ⎦ ⎣ ripple
source max l − n a dc a inverter ripple max f sw f sw
ΔI inverter ripple max = Max(0.198, 0.2241) = 0.2241 pu ( App)
I inverter I inverter
rms
(h = m (h = m
f
± 2) ≈
rms
f
± 2 ) ≈ 0.02986 pu ( A rms)
Vdc 1 ⋅ 0.2 ⋅ 2πf1 ⋅ h ⋅ L f 3
Harmonic attenuati on
Z C ( f sw − 2 ⋅ f1 ) = ( f sw − 2 ⋅ f1 ) Z C ( f sw − 2 ⋅ f1 ) + Z L ( f sw − 2 ⋅ f1 ) I grid rms ( f sw − 2 ⋅ f1 ) = −18.5bB I inverter rms ( f sw − 2 ⋅ f1 ) I grid rms ( f sw − 2 ⋅ f1 ) = 0.1188 ⋅ 0.02986 = 0.0035 pu ( A rms) I grid rms ( f sw − 2 ⋅ f1 )
rms
f
I inverter
f
t
Current regulator step response
Iqref step change [1 1] (from capacitive to inductive) No PCC voltage regulator Stiff system Limiters: Vmax=1.15, Vflat=1
Dc link step response
Vdc ref step change [2.0412 2.3] Stiff system
77 Table 29. Continued Parameter Model response Voltage regulation
Design system/Comments Vpcc ref step change [1.0 1.05] Variable line impedance: [1% 2% 4% 5% 10% 20% ]
Current regulator bandwidth
Iqref =0.2sin (wt) Idref =Iess+0.2cos (wt) f=[120 300 420 540 660 1020]Hz Vdclink=2.0412pu (V) Vsouce max ln=1 pu (V) Stiff system Cutoff frequency ≈ 400 Hz
Power filtering
Power limiter 2 simulation results for a sampling time of 2 seconds
CHAPTER 3 SYSTEM DESCRIPTION
System Overview
The performance of the power advanced electronic device was tested in a test bench based on: • • • • DC motor  synchronous machine set Passive load DC motor  asynchronous machine set Wind farm buffer The basic idea was to reproduce the basic electrical components of a small isolated system in order to asses the benefits of smoothing windpower fluctuations. Figure 31 shows this main idea.
Bulk generation. The system model’s bulk generation was represented with a
single synchronous machine, which the main function was to control the system frequency and voltage.
Load. The power system’s load composition was strongly dependent on the time of
day, month, and season, but also on weather. A typical load profile was studied in [37], and can have the following approximate composition: • • • Induction motors, 60 per cent Synchronous motors, 20 per cent Other ingredients (passive load, electronics...), 20 per cent
78
79
Wind Farm m odel
DCM otor Asynchronous Generator
3 phas e four w ire s y s tem Vphas ephas e=480 V
Electric Network Model
1 st QU AD R AN T CHOPPER
Tachometer (w>1800 rpm)
Line Impedance Z=5%,X/R=100
PF caps
3 phas e four w ire s y s tem Vphas ephas e=480 V
LOAD
180 Vdc +
C ontrol signal
P=4.5kW
3 phas e four w ire s y s tem Vphas ephas e=480 V
Gate D riv er
Vr ated field ?? DC volts = Fixed Magnetic field ?? Power=?? PFcorrec tion
1 st QU AD R AN T CHOPPER 3 phase input V ll =240 V 180 Vdc +
DC M otor
Tachometer (w>1800 rpm )
C ontrolsignal
Synchronous Machine
V rated field ?? DCvol ts = Fixed Magnetic fi eld ?? Power=??
Gate D riv er
SE350 Voltage R egulator (1% v oltage regulation)
3 phase input V ll =240 V GM1 GM4
Va,Vb,Vc PC C
LOAD 1
C hoke InductorFilter
5%base on Power Stabilizerrated Power and Voltage
Va,Vb,Vc Filter
LOAD 4
10% bas e on Power Stabi lizerrated Power and Voltage
1 g1 N AS VnaS N BS VnbS N CS 2 g3 2
3 g5 2
5 2 gc1
5
300.0
Vdc link
C hopper R eac tor 1.0 1.0
GM2 LOAD 2 GM3
3% bas e on Power Stabilizerrated Power and Voltage
Ia,Ib,Ic IN V
Vnc S 4 g4 2 g6 2 6 g2 2 2 2 gc2 5
Energy Storage C apac itor
LOAD 6
LOAD 5
Power Stabilizer
LOAD 3 GM5
IM1
Figure 31. Equivalent system model Dynamic loads usually consume between 60 to 70 % of the total power system energy. However, their dynamics are of special importance for voltage stability studies due to their reactive power requirements. Thus, since only real power fluctuations were of interest in our study, the system’s load was reduced to a one threephase passive load.
Renewable Resources. Renewable resources are growing faster than traditional
energy sources, with the fastest growth being in wind and solar energy. It is expected that in the near future, they will play a significant role in the generation mix. The system’s renewable resources were modeled using a single induction generator that would represent 15% of the system capacity. This number was very conservative compared to other grids such as Western Denmark with a penetration level of 63% of peak load and the Island of Crete, where wind power has a penetration level close to 40%.
80
Power Quality Devices. Because of wind power’s high penetration factor in the
near future, new advanced power electronic devices as well as grid operation procedures have to emerge to minimize the impact of nondispatchable wind power. In modeling the system, only a proof of concept wind farm buffer was considered to study different control schemes that could reduce windpower fluctuations.
Electrical Network Model Synchronous Machine
The first requirement of a reliable service is to have the synchronous generators with adequate capacity to meet the load demand. Any unbalance between the generation and load initiates a transient that causes the synchronous machine to accelerate or decelerate due to the appearance of net torques on the rotor. It can be shown that the interconnection of j finite machines with inertia constants Mj can be reduced to a single finite machine with inertia H, where H can be calculated as shown in Equation 31.
H=
1 1 1 1 + + ... + H1 H 2 Hj
(31)
The synchronous machine selected for modeling the electrical system is a threephase, brushless, self excited, externally regulated, AC generator. The ratings of the synchronous machine were • • • Rated Power 7.0 kW intermittent, 5.4 kW Continuous Rated Voltage 240/480 3ph 60 Hz Rated Speed 1800 rpm
81 The system voltage selected for the model is 480V; therefore the synchronous machine’s coils were connected in a high series Y configuration.
Voltage regulation
Load voltage regulation was mainly carried out by the generator’s exciter using an external voltage regulator. The automatic voltage regulator received both its input power and voltage sensing from the generator’s output terminals. The DC output voltage of the exciter field required to maintain constant the generator’s terminal voltage was automatically changed by the voltage regulator, which had a voltage regulation accuracy of 1%. The voltage regulator set point was 480V, line to line. Due to synchronous machine imperfections and asymmetries, output voltage was not an ideal sinusoidal waveform, as shown in Table 31. The most significant distortions were the second, third, fourth, and fifth harmonics, with an unbalance of approximately 1%. Such types of distortions were not very common in electric systems and may have an impact on the control system. Simple sliding windows were used to filter/reduce their impact.
Prime Mover
The prime movers of large generators are principally hydraulic turbines, steam turbines, and combustion turbines. In our model the prime mover that was used to produce the mechanical torque was a DC machine with the following specs: • • • • Rated Power: 7.5 HP Armature Voltage 240 V dc Field Voltage 150 V dc Rated Speed 1750 rpm
82 Both machines were connected in cascade through their shaft, so power could be transferred from one machine to another. Figure 32 shows the system configuration as well as the variables used in the control. Table 31. Synchronous machine output voltage profile at rated speed Synchronous Machine Voltage Synchronous Machine Voltage Features profile for unloaded condition profile for unloaded condition Waveform
FFT
Unbalance
A single quadrant chopper was used for speed control of the DC machine. Chopper circuit specs are shown in Figure 33. Note: Figure 33 shows that the DC power supply was used by the two choppers required in the model. One was for the prime mover of the synchronous machine, and the other one a different DC machine that would represent wind speed variations.
83
DC Motor 7.5hp
Encoder (w>1800 rpm) Single quadrant chopper
Encoder
Synchronous Generator 7hp
3 phase four wire system Vphasephase=480 V
Electric system
Istator generator
SE350 Voltage Regulator (1% voltage regulation) W rotor2 single phase input Vln=120 V Electrical field constant=7.6 Ripple period
Pout, Qout (V and I)
Ia, Ib generator
Vab, Vbc generator
Interface Board (signal conditioning and filtering) (Output Range 0v to 3v) (cutoff frequency=100kHz)
TO DSP
Figure 32. DC genset
R⋅2 = 300 sec ⎛ 50 ⎞ − ln⎜ ⎟ ⋅ Cfilter ⎝ 750 ⎠
BDD6 U 160 N 16 480 Volts LL RMS
C=2200uF 450V C=2200uF 450V C=2200uF 450V
Prime mover for synchronous machine
Prime mover for induction machine
Contactor
R 15kΩ 12 W
DC machine 1
DC machine 2
670 V
Vdc
source
Fuses Rlimit Lchoke FWH100 100Ω 0.83mH 100W Irms=44Ams
R 15kΩ 12 W C=2200uF C=2200uF 450V 450V C=2200uF 450V
Cfilter 3.3 mF 900 Volts
CHOPPER1
CHOPPER2
Figure 33. Two single quadrant chopper circuit
Synchronous Machine Control Algorithm
The control of a synchronous machine is based on three separate control systems: • • The excitation system or voltage regulator that controls the synchronous machine’s terminal voltage. The governor that controls the mechanical power monitoring the shaft’s speed.
84 • The supervisory controller which sends signals to each generator in the system to meet the load demand.
Excitation system
Vt
Rectifier
Boiler
Vreference
+
Excitation system
Vfield
Governor
Control Center Pelectrical Set points Boiler Control
Vfield Servomotors and Actuators Steam turbine Pmechanical
+
+
Pelectrical
Speed
Speed
Pelectrical
Machine Dynamics
Speed Generator
Vt Pelectrical
Electrical Network
Figure 34. Synchronous generator control system Figure 34 shows a generic block diagram of the different control systems required for the control of one generator. In our smallscale model, only the governor and the excitation were considered, since the master controller was designed to be quite slow, which is usually not involved in the mechanical dynamics of the shaft. The accurate modeling of the system’s frequency control requires the knowledge of a series of parameters that most of the times are impracticable to get. The frequency’s response after a disturbance depends on: • • • • System inertia, H Network power frequency characteristic, D Speed governor’s transfer function Load shedding scheme Equation 32 represents the frequency deviation response of a system with inertia H, and load frequency dependency D. Figure 35 shows the system frequency response for different H and D, for a 50% load step change (ΔP).
85 w dw = n ⋅ ΔP − D ⋅ Δw dt 2 ⋅ H
(32)
These two factors, H and D, dominate the system frequency deviation during the initial seconds following a power perturbation, since large time constants are involved in the control of the system frequency. Such parameters are usually very difficult to determine or estimate due to the system’s nonlinearity. If all these factors were known, it could be possible to implement a control scheme that could represent the system’s frequency response. Figure 36 shows a control scheme for a synchronous machine when system frequency response parameters are known.
Figure 35. Frequency deviation
Ia, Ib generator Vab, Vbc generator 5 channels I chopper generator
A/D inputs Ia, Ib generator Vab, Vbc generator Frequency and Power calculation f grid f ref

+
+ +
PI controller Transient Droop Droop (4%)
ServoValve System model
Δc gate position
Turbine system model
ΔP 
Pout2 +
W rotor2 Pref2
Torque calculation
Ichopper generator Tref2
Stator Current Calculation 1/k
Vdc source
I stator ref2 +
PI controller PWM
4860Hz
Figure 36. DCGEN set control scheme
86 This control algorithm was further simplified, and a single frequency control regulator was implemented to tightly control the system frequency. Figure 37 shows the synchronous machine frequency response to a step change of 1 Hz in the reference for two different gains with a 90% system load (4.5kW out of 5kW). The frequency regulator’s transfer function and gains were adjusted to simulate any other system frequency deviation response. The only limitations were the DC motor maximum electrical specs, which should not be exceeded in order to avoid possible controlaction saturations and system damage.
Figure 37. System frequency response for Δf=1Hz From Figure 37, it is also possible to identify the DCgen set transfer function, adjusting the system response to a second order equation. Such parameters were valid for a particular point of operation, and should be recalculated every time the system changes. Nevertheless, their knowledge helped in the tuning of the frequency regulator, even with approximated coefficients. Thus, with 90% load, the system DCGen set transfer function was estimated to be:
87 w( s) Varmature
in pu 2 K ⋅ω n 3.0 ⋅ 225 = 2 = 2 2 s + 2 ⋅ ζ ⋅ ω n ⋅ s + ω n s + 33 ⋅ s + 225 cycle chopper ( s )
H ( s) =
( s)
=
w( s)
d duty
Thus, it possible to represent the DCGen set frequency control scheme as shown in Figure 38.
Δw ref + Ki Kp + s
Δduty cycle
3.0 ⋅
225 s 2 + 33 ⋅ s + 225
Δw
Figure 38. Frequency control equivalent system Figure 39 shows the equivalent system response to a step change of 1Hz/60Hz=0.01666pu for two different gains. As expected, the system’s behavior was similar to the model, and it was used in the design of the frequency regulator.
Wind Farm Model
There are countless studies, books and reports on the modeling of wind turbines and wind farms. Among them, transient studies, such as flicker assessment, harmonics impact, fault ridethrough, etc, have become one of the most popular ones. Nevertheless, there are long term studies, such as voltage stability, protection and control, and powerflow variations that, even though they do not require a detailed system representation, are of vital importance for the overall electric system stability. Transient and long term studies require different approaches when modeling the wind turbines, mainly due to the different time constants involved in the different analysis. Figure 310 and 311 illustrate the different basic structures of a wind turbine for the different types of analysis.
88
Figure 39. Equivalent model frequency response for Δf=  0.01666 pu
Pitch control wwind
β = pitch angle
1 ⎛ ⎞ −c6 ⋅ c p (λ , β ) = c1 ⋅ ⎜ c2 ⋅ − c3 ⋅ β − c4 ⋅ β x − c5 ⎟ ⋅ e Δ Δ ⎝ ⎠ 1 1 0.035 w⋅ R = − ;λ= Δ λ + 0.08 ⋅ β 1 + β 3 v v
1
wwind wwind Blade transients Mechanical transients Tw
wgenerator Tg Generator Pg Converter (optional) Grid
Pwind
1 = ⋅ ρ ⋅ A ⋅ v3 2
Pwind wheel = c p (λ , β ) ⋅ Pwind
dw J⋅ = Tw − Tg − D ⋅ w dt
Drive train Model
Wind Power
Wind Wheel Power
Converter (optional)
Generator controller
Figure 310. Dynamic model used for transient studies [38]
Rs' + Rr
j ( X s' + X r )
P = f (wind )
− jX c
jX m
Figure 311. Static model used for steadystate studies [39] According to an extensive research study undertaken by the National Renewable Energy Laboratory (NREL) on the shortterm power fluctuation of large windpower plants, the persistence of the wind and the output of the windpower plant are very strong
89 within one second time step. In other words, the likelihood of wind power changing from one level Pi to another level Pj=Pi*( ± 1.1) at the next second is very small (<1.5%) [40][41]. Therefore, since only power fluctuations were of interest for our study, no fast wind turbine dynamics were incorporated into the system model or system control. The proposed windfarm equivalent model is shown in Figure 312. A 7.5 HP DC motor acted as a prime mover and its control was designed to assure that a 5 HP induction generator followed a given power fluctuation profile.
DC Motor 7.5hp
Encoder (w>1800 rpm) Single quadrant chopper
Encoder
Asynchronous Generator 5hp
3 phase four wire system Vphasephase=480 V
GRID
PF caps
Ichopper wind farm real time data transfer wind power data DC machine controller Power reference
W rotor1
Vrated field= 150 DC volts Irated=1.15 Amps Lfield=6.76 H Rfield=107 Ω τ=0.063 secs
PF correction
Pout, Qout (V and I)
Ia, Ib wind farm Vab, Vbc wind farm
DSP TI F2812
single phase input Vln=120 V Electrical field constant=7.6 Ripple period
Data logging
Supervisory system
Interface Board (signal conditioning and filtering) (Output Range 0v to 3v) (cutoff frequency=100kHz)
Figure 312. Windfarm model Actual windpower output data from a windpower plant in Hawaii was used for the analysis of the system performance. Before the data was incorporated into the control algorithm as reference values, they were scaled down according to the system needs and penetration factors wanted. For instance, a 10 MW rated power wind farm that represents 15% of the system total capacity would have to be scaled down as
Model system capacity = 5 kW Wind farm penetration level = 15% ( or 750 W) Actual wind power output data ( MW) Induction Machine Reference Power = ⋅ 0.15 10 MW
90 The goal was to be able to reproduce any kind of power variation (or wind profile) typical of wind farms, and its impact on the electric power system.
WindFarm Control Algorithm
To generate the required windpower fluctuations, the following control algorithm was implemented in a DSP.
I chopper Ia, Ib wind farm Va, Vb,Vc wind farm
6 channels
A/D inputs
Vdc power
supply
Pwind farm Pwind ref + 
K derivative
s 1 + sT
+ +
Ichopper I chopper ref +
PI controller PWM TO CHOPPER
PI controller
4860Hz
Power regulator
Current regulator
Figure 313. Windfarm controller A derivative control action was added to the PI controller to allow for a fast time response. Figure 314 shows the windfarm model time response to a 750W step change (from 0% to full load). It can be deduced from the current chopper reference curve that the power regulator’s derivative control action was of vital importance in the damping of the output power ( P wind farm). The system time constant was around 0.25 seconds, allowing for changes in power references every second.
WindFarm PowerFactor Correction
When an asynchronous machine is acting as a generator, excitation currents needed to create the field excitation are drawn from the electric power system it is connected to.
91 Asynchronous generators are usually equipped with a power factor correction system for phase compensation of individual machines and/or to regulate voltage at the point of interconnection.
A
B
Figure 314. Windfarm power regulator & current regulator step response (ΔP=100%). A) Current regulator output. B) Power regulator output. Figure 315 shows the PQ curve of the induction generator used for the modeling of the wind farm. It can be inferred from Figure 315 that • • As the power generated increases so does the reactive power drawn from the system. The PQ curve is strongly biased. Usually, only the nonload reactive power consumed by the asynchronous generator is compensated by means of capacitor banks. However, the wind farm manufacturers also offer the possibility of 100% compensation using different capacitor
92 bank steps. The largest capacitor bank is always switched on first, once the generator has been cutin.
Figure 315. Induction generator PQ curve In order to reduce the amount of reactive current drawn from the electric power system, a power factor correction capacitor bank was connected in shunt with the induction machine. The windfarm power factor was not corrected 100% to avoid possible selfexcitation conditions during unwanted island mode operations. The amount of required capacitance required to compensate for a given reactive power is given by Equation 33. C= Q3 phase
2 3 ⋅ 2 ⋅ π ⋅ f ⋅ Vl −n
(33)
Thus, a C ≈ 15 uF capacitor (per phase) was required to compensate for Q=1300Var, which meant a reduction of approximately 70% in reactive current at the nonload operation point. Figure 316 shows the location and configuration of the PF capacitor bank.
93 Figure 317 shows the power factor correction capacitor bank effect on the windfarm output current for the nonload condition. It can be concluded that • • The required reactive current drawn from the electric power system was significantly reduced. Capacitor current created undesired harmonic components that had an impact on the total output windfarm current.
GRID
15 uF 280 V 15 uF 280 V 15 uF 280 V
Single quadrant chopper
Encoder
DC Motor 7.5hp
Asynchronous Generator 5hp
PF correction
Figure 316. Windfarm PF correction capacitor bank A closer look at the capacitor harmonic current content revealed that the capacitor impedance did not decrease linearly with the frequency. Figure 318 shows the capacitor impedance at different frequencies.
A
B
C
D
Figure 317. PF correction capacitor bank current waveforms. A) Synchronous machine voltage. B) Capacitor bank current. C) Induction machine current. D) Wind farm current.
94
Figure 318. Capacitor bank impedance frequency scan Capacitor current distortion was mainly due to its nonlinear behavior at different frequencies. Thus, synchronous machine voltage harmonics content, in particular 2nd, 3rd, 4th, and 5th harmonics, would exaggerate this nonlinearity, making it more visible.
WindFarm SoftStart System
Wind turbines use softstart systems to smooth the connection and disconnection of the generator to the electric power system. It helps minimize high changes of voltage and current in the grid, while protecting the mechanical parts of the wind turbine against high torque forces present during the startup and shutdown. In the majority of cases, thyristors are used as softstarters, and these are bypasses electromechanically, once the wind turbine has been started to avoid semiconductor losses. Induction machines’ inrush current can sometimes reach values up to eight times their nominal current, causing protection systems to disconnect the machine from the power grid. The same type of inrush currents was present in our model during the startup of the induction generator. In order to avoid this inrush current, the induction generator was brought online at the same time the synchronous machine was brought up to the rated speed (1800 rpm). Figure 319 shows a flow chart describing the procedure
95 followed to bring the entire system to nominal values, avoiding any unwanted inrush current or transient. The system operated in various modes, some of them stationary, and some of them temporary. The control sequence was the following: 1. The duty cycle of the synchronous machine’s prime mover was increased linearly, so that synchronous machine’s V/F ratio was kept as constant as possible (except when the voltage regulator took control over the excitation field). A speed regulator controlled the duty cycle of the induction machine’s prime mover in order to track the synchronous machine’s speed during the rampup stage. Thus, the induction machine’s inrush current was minimized. Once both machines were closer to their nominal speed (1800 rpm), the control system smoothly changed the mode of operation, where the synchronous machine’s speed and induction machine’s output power were tightly controlled.
Reset Mode Actions  Disable Chopper PWM1  Disable Chopper PWM2  Initialize regulators
2.
3.
No
Actions  Disable all control actions
Chopper DC power supply OK?
Actions  Clear errors  Enable Chopper PWM1  Enable Chopper PWM2
Yes
Stop Mode Startup Mode
Actions  Rampup duty cycle of synchronous machine's primer mover  Enable speed regulator of induction machine's primer move ( speed reference induction machine equals synchronous machine actual speed)
IM speed<90% rated speed ? & SM speed>99% rated speed?
Chopper DC power supply OK?
No
No
IM speed>90% rated speed ? & SM speed>99% rated speed?
Yes
Run Mode Actions  Frequency regulation  Power regulation
Yes
SM speed>120% rated speed?
No
Figure 319. Machine control scheme operating states
96 Figure 320 shows the system’s performance during the startup sequence. As expected, the induction machine’s inrush current during the starting stage was also insignificant. Figure 321 shows a detail of the transient of the induction machine speed during the transition between “startup” mode and “run” mode.
A
B
C
D
E
Figure 320. Electric power system startup. A) Machines’ dutycycle. B) Machines’ speeds. C) Automatic voltage regulator output. D) Synchronous machine output voltage. E) Windfarm current.
Figure 321. Detail of the transition from startup mode to run mode
97
Power Stabilizer PowerStabilizer Hardware Description
The main components that form part of the windfarm buffer were: • • • • • Interface board Digital Signal Processor (DSP) Field Programmable Gate Array (FPGA) Intelligent Power Module (IPM) Gate Drive board (isolated interface circuit) All these components were linked to each other one way or another, and their designs were very interrelated. The major difficulty found when designing and implementing the Power Stabilizer system was the electrical noise. Sharp edge digital signals in close proximity to high switching frequency power semiconductors at high voltage levels required special care in order to make them work in “harmony”. Figure 322 shows the overall power stabilizer system as well as all the major links between all key components.
Iwind
GRID
Va, Vb, Vc PCC
Choke Inductor Filter
10% base on Power Stabilizer rated Power and Voltage
1 2 g1 2 g3 3 2 g5 5 2 gc1 5
5% base on Power Stabilizer rated Power and Voltage
Va, Vb, Vc Filter
Vdc link
Chopper Reactor
3% base on Power Stabilizer rated Power and Voltage Ia, Ib, Ic INV
2 g4
Ichopper
4 2 g6
6 2 g2
2 2 gc2
5
Energy Storage Capacitor
Vstorage
g1
g2
g3
g4
g5
g6
gc1
gc2
Va, Vb, Vc PCC
Va, Vb, Vc Filter
Ia, Ib, Ic INV
Vdc link
Ichopper
Vstorage
Ia, Ib, Ic wind farm
GATE DRIVE BOARD
INTERFACE BOARD
Va, Vb, Vc PCC 3 channels Va, Vb, Vc Filter Ia, Ib, Ic INV Vdc link Ichopper Vstorage Ia, Ib, Ic wind farm 3 channels
signal conditioning and filtering Output Range 0v to 3v
3 channels 3 channels
1 channel
1 channel
1 channel
Error signals Data Bus (PWM & Watch Dog)
g1
g2
g3
g4
g5
g6
gc1
gc2
A/D 16 inputs (12 bit)
FPGA
DSP
Digital Outputs PWM generation System diagnosis Address
Power Stabilizer control algorithm
Reset Synchronization signal
Figure 322. Power Stabilizer system overview
98 The following sequence shows how the power stabilizer’s control scheme functions: 1. 2. Signals from the electric system were scaled down by the interface board to the appropriated levels before these were sent to the DSP’s A/D converter. To synchronize the PWMtriangular waveform and the DSP’s interrupt service routine frequency that executed the main control algorithm, the FPGA’s clock signal was used as the main time base. Thus, every 25.72 µs (or eight times the PWM switching frequency) the FPGA sent a signal to the DSP to initialize the execution of the main control algorithm. The DSP processed the input signals and determined the control actions required to meet particular system’s specifications. Once control actions were calculated by the DSP, these were sent to the FPGA in the form of clock cycles. The FPGA then compared these signals to a “digital” triangular waveform (an up/down counter) in order to generate the PWM signals. PWM signals were then passed through a digital deadtime generator to avoid possible shootthrough currents that could damage the IPMs. PWM signals were then sent to the interface board, where the appropriate scaling was carried out before these were sent to the gate drive board. Once the PWM signals reached the gate drive board, these were isolated from the high power side in order to avoid noise problems. IPMs executed the desired control actions. Other signals that were involved in our design and were not shown in the overall diagram are •
Protection signals:Trip signals due to overcurrent, and overvoltage conditions were present in the interface board and they were provided for the safe operation of the system. These signals, when active, disabled the PWM control actions without the intervention of the DSP. The reason for such highspeed response was that the DSPs interrupt latency could not protect hardware when responding to overcurrent through interrupt service routine software. WatchDog: The FPGA also contained a special error signal called “WatchDog”. It basically provided a safeguard against DSP crashes by automatically disabling PWM control actions if it was not serviced by the DSP at regular intervals. Data acquisition signals: To tune and improve system performance a data acquisition system to monitor system variables was required. Thus, the interface
3.
4. 5. 6. 7.
•
•
99 board was equipped with two D/A converters that in real time could show the DSP’s internal variables. Up to 8 different variables were sampled in real time. •
Data acquisition system: A secondary data acquisition system was also available through the DSP’s JTAG controller interface with a refreshing time limited to 100 ms (close to 4000 times slower than the DAC system).
Interface board
The interface board’s main function was signaling conditioning while providing trip signals due to overcurrent and/or overvoltage conditions. Figure 323 shows an overview of the different functions implemented in the interface board. These functions were • • • • • Signals scaling (voltage and current) Trip signals conditioning Power supply voltage monitoring FPGAGate drive board interface (input and output signals) D/A circuit
Signals scaling. The electric power signals had to be scaled down before their
conversion into digital. The DSP ADC data sheet specified that the input range voltage was from 0.0 V to 3.0 V. Therefore, a signal conditioning circuit was designed to bring down voltages within ±1000 V range. Figures 324, 325, 326, and 327 show the circuit topologies used in the scaling of the different voltages and currents present in the system. Voltage at the DC link bus, voltage at the energy storage energy bus, and power stabilizer currents were the only inputs with trip signals. Moreover, only the DC link voltage’s scaling & trip circuitry was duplicated, with the purpose of avoiding system damage due to the loss of one of the instrumentation amplifiers. The DC link voltage would tend to rise without control, if the system used to measure its value failed.
100
J1 PHOENIX 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J3 PHOENIX 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VPCCC VPCCN V_DC_LINK_P1 V_DC_LINK_N1 V_DC_LINK_P2 V_DC_LINK_N2 VSTORAGEP VSTORAGEN VEXTRAP VEXTRAN AREA1 VFILTER, VPCC,VDCLINK, VSTORAGE VFILTERAOUT VFILTERBOUT VFILTERCOUT VPCCAOUT VPCCBOUT VPCCCOUT V_DC_LINK1 V_DC_LINK2 VSTORAGE GND VFILTERA VFILTERN VFILTERB VEXTRA_ERROR VFILTERN DC_LINK_ERROR1 VFILTERC VFILTERN VPCCA VPCCN VPCCB VPCCN VEXTRA J4 1 2 PHOENIX 2 DC_LINK_ERROR2 VSTORAGE_ERROR
+15V +5V +3.3V GND 15V J5 PHOENIX 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J7 PHOENIX 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IESACP IESACN ICHOPPERP ICHOPPERN AREA2 IWIND,IESA, ICHOPPER IWINDAP IWINDAN IWINDBP IWINDBN IWINDCP IWINDCN IESAAP IESAAN IWINDA IESABP IWINDB IESABN IWINDC IESAA IESAB IESAC ICHOPPER GND J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
IESAA_ERROR_P IESAA_ERROR_N IESAB_ERROR_P IESAB_ERROR_N IESAC_ERROR_P IESAC_ERROR_N +15V +5V +3.3V GND 15V ICHOPPER_ERROR_P ICHOPPER_ERROR_N
J10 PHOENIX 10 1 2 3 4 5 6 7 8 9 10 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20 J9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 A0 A1 LS MS CS1 CS2 GND +24V +15V +5V +3.3V GND 15V UV+24V UV+15V UV+5V UV+3.3V UV15V GND +15V OK
AREA5 UV
J8 PHOENIX 20 D/A OUTPUT1 D/A OUTPUT2 AREA 3 D/A D/A OUTPUT3 D/A OUTPUT4 D/A OUTPUT5 D/A OUTPUT6 D/A OUTPUT7 D/A OUTPUT8 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+15V +5V GND 15V
J13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
PWM_UP SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 10 J11 1 2 3 4 5 6 7 8 9 10 PWM_UN PWM_VP PWM_VN PWM_WP PWM_WN PWM_CP PWM_CN GND AREA4 PWM BUFFER
UP1A UP2A VP1A VP2A WP1A WP2A UN1A UN2A VP1A VN2A WN1A WN2A UP1B UP2B VP1B VP2B WP1B WP2B UN1B UN2B VN1B VN2B WN1B WN2B GND +15V OK
J12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20
SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20 J14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+3.3V GND U_FOSA V_FOSA W_FOSA AREA6 A IPM ERROR A
U_FOSERRORA V_FOSERRORA W_FOSERRORA
FOSA
FOSERRORA GND +15V OK SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 10 J16 1 2 3 4 5 6 7 8 9 10
+3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J15 SHROUDED LATCH HEADER FOR RIBBON CABLE STRAIGHT PIN 20 GND U_FOSB V_FOSB W_FOSB AREA6 B IPM ERROR B U_FOSERRORB V_FOSERRORB W_FOSERRORB
FOSB
FOSERRORB GND +15V OK
Figure 323. Interface board overview
101
+15V +10V CLAMP VOLTAGE R1 VFILTERA R2 4.99k 0.6W 1% 1M 3/4W
5V TO +5V RANGE C2 0.001uF 50V 10% 7 U1 3 + 1 R1 8 R2 2 C3 0.001uF 50V 10% 4 5
C1 0.1uF 50V 10%
D1 1N914B R3 D2 1N5817 2.8k 1/4W 1%
6 0 TO +10V RANGE
0 TO +3V RANGE R4 1.2 k 0.4W 1%
VFILTERAOUT
R6 4.99k 0.6W 1% R5 VFILTERN 1M 3/4W
AD620 +5V
C5 0.1uF 50V 10% 15V
Figure 324. AC voltage scaling circuit (input [1000+1000V], output [0 +3V])
+3.3V +10V CLAMP VOLTAGE 16 0 TO +10V RANGE, 9V TRIP (DC LINK TRIP VOLTAGE =900 V) R40 V_DC_LINK_P1 R41 10K 1/4W 1% C27 0.001uF 50V 10% 3 1 8 2 R43 10K 1/4W 1% R42 V_DC_LINK_N1 C29 0.1uF 50V 10% 15V 1M 3/4W C28 0.001uF 50V 10% C26 0.1uF 50V 10% U7 6 D14 1N5817 AD620 4 5 D13 1N914B +TRIP LEVEL VOLTAGE 7 + 6 12 LM239 7 C36 0.1uF 50V 10% U9A 1 1 1M 3/4W +15V +15V +3.3V RP1A 1.0k 14 7 3 C34 0.1uF 50V 10% 12 U10F 74AHC14
+ R1 R2 
13
DC_LINK_ERROR1
R46 V_DC_LINK1 0 TO +3V RANGE, 2.7V TRIP (DC LINK TRIP VOLTAGE =900 V) 2.8k 1/4W 1% R47 1.2 k 0.4W 1%
Figure 325. DC voltage scaling circuit (input [0 +1000V], output [0 +3V])
+15V +10V CLAMP CURRENT R79 1.0k 1/4W 1% TP1 IWINDAP TP2 IWINDAN T1 PIN1 PIN3 PIN2 AC1005 1 3 2
R84 100 1/4W
C49 0.001uF 50V 10%
R80 5.49k 1%
U15 3 + 1 R1 GAIN 10 8 R2 2 4 5
7
0.5V TO 0.5V RANGE
C48 0.1uF 50V 10% 0 TO +10V RANGE 6
D27 1N914B R85 D28 1N5817 2.8k 1/4W 1%
0 TO +3V RANGE R86 1.2 k 0.4W 1%
IWINDA
AD620 +5V
C51 0.1uF 50V 10% 15V
Figure 326. CT current scaling circuit (input [5 +5A], output [0 +3V])
+15V +3.3V +3.3V LEM1 IESAAP IESAAN M LA 25NP/SP14 R98 137 0.6W 1% C59 0.001uF 50V 10% 7 3 + 1 R1 8 R2 2 4 5 U19 6 D34 1N5817 AD620 TRIP LEVEL CURRENT +5V 5 4 + 12 LM239 R101 IESAA 0 TO +3V RANGE, 0.3V AND 2.7V TRIP 2.8k 1/4W 1% R102 1.2 k 0.4W 1% +15V 15V R97 1.0k 1/4W 1% +15V 3 0 TO +10V RANGE, 1V & 9V TRIP C58 0.1uF 50V 10% +10V CLAMP CURRENT +TRIP LEVEL CURRENT 7 + 6 12 LM239 U20A 1 5 C61 0.1uF 50V 10% 16 RP1E 1.0k
D33 1N914B
3 16
14
C62 0.1uF 50V 10% 4 U21B 74AHC14
IESAA_ERROR_P
RP1F 1.0k 3 U20B 2
6
5
7
6 U21C 74AHC14
IESAA_ERROR_N
C60 0.1uF 50V 10% 15V
Figure 327. LEM current scaling circuit (input [0.36 +0.36A], output [0 +3V])
Power supply monitoring. During the startup and shutdown of the system, it was
very important to have complete control in order to avoid possible unwanted turnon of the power semiconductors. Moreover, if one of the power supplies would fail during
102 normal operation of the power stabilizer, a shut down of the IGBT gating was required in order to protect the rest of the system. Figure 328 shows the power supplies’ voltage monitoring circuitry used in the interface board.
+5V +15V +24V C46 0.1uF 50V 10% U14 1 2 3 4 5 6 7 8 R76 1.24k 1/4 W 1% VREF IN1 IN2 IN3+ IN3IN4+ IN4DIN VDD MS OUT1 OUT2 OUT3 OUT4 DOUT GND MAX8214 U10B 3 R81 1.24k 1/4 W 1% U10C 5 15V 74AHC14 6 UV15V +15V 4 UV+24V 16 15 14 13 12 11 10 9 R63 10k 1/4W 1% R65 10k 1/4W 1% R69 10k 1/4W 1% 14 U10A 2 UV+15V C40 0.1uF 50V 10% +3.3V +3.3V
R66 13k 1/4W 1%
R70 21.5k 1/4W 1%
1
R64 1.24k 1/4 W 1%
R72 1.24k 1/4 W 1%
74AHC14
7
74AHC14
D19
1N914B K Z4 1N914B D22 A 1N755A D21
R62 10k 1/4W 1%
Q2 +5V +5V +3.3V +3.3V 1N914B K D23 IRF4905/TO
Z2 R73 3.48k 1/4W 1% R78 1.87k 1/4W 1% U16 1 2 3 4 5 6 7 8 VREF IN1 IN2 IN3+ IN3IN4+ IN4DIN VDD MS OUT1 OUT2 OUT3 OUT4 DOUT GND MAX8214 U10E 11 10 UV+3.3V 16 15 14 13 12 11 10 9 U10D 9 8 UV+5V Q1 2N7000 A C50 0.1uF 50V 10% R82 10k 1/4W 1% R77 10k 1/4W 1% 1N914B R75 10k 1/4W 1% 1N755A A K Z3 1N967B
+15V OK
R71 1.0k 1/4W 1%
R74 1.24k 1/4 W 1%
R83 1.24k 1/4 W 1%
74AHC14
74AHC14 D25
1N914B D26
1N914B
Figure 328. Power supplies’ voltage monitoring Only when the power supplies were OK a 15 V source (labeled “+15V OK”) was switched on, allowing the Darlington drivers of the FPGA to control the optocouples (fault and control signals) of the IPM’s gate drive. Figure 329 shows the system’s critical signals during powerup. It can be inferred that the voltage monitoring circuit ( +15 Volts OK signal ) was a critical element to assure that no PWM signals reached the gate drive until all the voltages were stable. Figure 330 shows the system’s critical signals during shutdown. In this case no glitches were present. However the voltage monitoring circuitry provided a clean system shutdown, avoiding possible system malfunctions.
103
A
B
C
D
Figure 329. System’s critical signals during turn on. A) AC side. B) 15 volts signal. C) FPGA’s PWM phase A. D) FPGA voltage supply.
A
B
C
D
Figure 330. System’s critical signals during turn off. A) AC side. B) 15 volts signal. C) FPGA’s PWM phase A. D) FPGA voltage supply.
FPGAGate drive board interface. Gate drive board faults and on/off control
signals were transferred to and from the system controller (FPGA) using optocouplers, so high and low side control signals could be referred to a common logic level. In our application board, Darlington transistors (Figure 331) were used to drive the diode side of the optocouplers.
104
+15V OK UP1A UP2A VP1A VP2A WP1A WP2A U31 PWM_UP PWM_UN PWM_VP PWM_VN PWM_WP PWM_WN 1 2 3 4 5 6 7 9 IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM MC1413 UP1B UP2B U32 PWM_CP PWM_CN 1 2 3 4 5 6 7 9 Z6 1N967B A IN1 IN2 IN3 IN4 IN5 IN6 IN7 COM MC1413 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 16 15 14 13 12 11 10 VP1B VP2B WP1B WP2B UN1B UN2B VN1B VN2B WN1B WN2B OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 16 15 14 13 12 11 10 UN1A UN2A VP1A VN2A WN1A WN2A
FROM FPGA
TO GATE DRIVE BOARD (isolated interface board)
Figure 331. Darlington drivers Status signals from the IPM, once isolated by the gate drive board, are scaled down in order to be processes by the FPGA (Figure 332).
+15V OK +3.3V
K
C41 0.1uF 50V 10% R120 5.5k 1/4W 1% 14 R128 30k 1/4W 1% U_FOSA C88 0.001uF 50V 10% R121 5.5k 1/4W 1% R129 30k 1/4W 1% V_FOSA C89 0.001uF 50V 10% R122 5.5k 1/4W 1% R130 30k 1/4W 1% W_FOSA C90 0.001uF 50V 10% R123 5.5k 1/4W 1% R131 30k 1/4W 1% FOSA C91 0.001uF 50V 10% R139 10k 1/4W 1% 74AHC14 9 R138 10k 1/4W 1% 74AHC14 U33D 8 FOSERRORA 5 R137 10k 1/4W 1% 74AHC14 U33C 6 W_FOSERRORA U33B 3 4 V_FOSERRORA R136 10k 1/4W 1% 74AHC14 7 1 U33A 2 U_FOSERRORA
FROM GATE DRIVE BOARD (isolated interface board)
TO FPGA
Figure 332. IPM status signals interface circuitry
D/A circuit. Real time system diagnostics could be carried out by the usage of D/A
converters controlled by the DSP. The goal was to be able to identify potential problems and to evaluate system performance. Thus, every time the DSP executed the control algorithm, the DACs were updated with new values from the DSP. The number of DACchannels available was 8, and the range of output voltage was programmable from the DSP, having a maximum of ±10V. Figure 333 shows the circuit used for the control of the DAC.
105
+5V 15V +15V
C78 0.1uF 50V 10%
C76 0.1uF 50V 10%
C82 0.1uF 50V 10%
42
6
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
28 29 30 31 32 33 35 36 37 38 39 40
5
VEE
VLL
VCC
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
RFA VOA RFB VOB RFC VOC
7 8 10 9 12 13 15 14 D/A OUTPUT4 D/A OUTPUT3 D/A OUTPUT2 D/A OUTPUT1
A0 A1
19 20 23 24 25 2 27 18 +5V +5V 1 26
U27 AD664 (44 pin) DS0 DS1 QS0 QS1 QS2 LS MS CS RD TR RST
RFD VOD
LS\ MS\ CS1
DGND 21 GND
R118 10k 1/4W 1%
22
11
4
AGND
VREF
GND +15V C80 0.1uF 50V 10% 2 C83 0.1uF 50V 10% 8 5 U29 +VIN NOISE TRIM AD587JN VOUT GND 6 C84 1uF 50V 10%
4
+5V
15V
+15V
C79 0.1uF 50V 10%
C77 0.1uF 50V 10%
C85 0.1uF 50V 10%
42
6
28 29 30 31 32 33 35 36 37 38 39 40
5
VEE
VLL
VCC
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
RFA VOA RFB VOB RFC VOC
7 8 10 9 12 13 15 14 D/A OUTPUT8 D/A OUTPUT7 D/A OUTPUT6 D/A OUTPUT5
19 20 23 24 25 2 27 18 +5V +5V 1 26
U28 AD664 (44 pin) DS0 DS1 QS0 QS1 QS2 LS MS CS RD TR RST
RFD VOD
CS2
DGND 21
R119 10k 1/4W 1%
22
11
+15V C81 0.1uF 50V 10% 2 C86 0.1uF 50V 10% 8 5 U30 +VIN NOISE TRIM AD587JN VOUT GND 6 C87 1uF 50V 10%
Figure 333. DAC circuit
Digital signal processor
The controller selected for this application was the DSP F2812 from Texas Instruments. The main features of the DSP development board are: • TMS320F2812 Digital Signal Processor operating at 150 MHz − 32Bit CPU − 18 K on chip RAM − 12Bit ADC, 16 Channels − 56 Individually Programmable, Multiplexed GPIO Pins
4
4
AGND
VREF
106 • • • • 128 K on chip FLASH ROM 64 K words on board RAM Expansion Connectors Onboard IEEE 1149.1 JTAG controller Different alternatives were evaluated for the control of the power stabilizer. However, mainly due to cost reasons and processing speed, the DSP F2812 was the chosen option for this type of application. The alternatives under consideration are summarized in Table 32. Table 32. Alternatives for the power stabilizer controller Controller Price Comments Matlab Real Time Workshop $7,500.00 Maximum speed: 10 kHz Matlab RealTime Windows Target $2,000.00 RealTime Linux Freeware Long learning curve to be proficient at it. National Instruments : NI PXI8186 RealTime $4495.00 Data acquisition system (42 kHz single PI loop) + LabView Realwith onboard processor Time Microstar Laboratories: DAP5400a $4000.00 Data acquisition system with onboard processor Texas Instruments TMS320C2812 DSP $300.00 development kit
Fieldprogrammable gate array
A Field Programmable Gate Array or FPGA is an integrated circuit that can be programmed, and it is specially designed for prototyping integrated circuit designs. In this application the FPGA developed two basic tasks: • • PWM generation ( “digital” triangular waveform, circuit comparator, and deadtime generator) Error signals’ processing Despite the fact that the DSP F2812 was capable of generating up to 10 independent PWM outputs, signals were allowed to change only twice per cycle. Figure 334 explains this limitation in the builtin PWM circuit.
107 As it will be elucidated later, a PWM generator was implemented in the FPGA, so that the system’s response was improved by allowing multiple changes within a cycle. Moreover, simple logic was included in the PWM generator so deadtime and error signals could be taken into account before PWM signals were sent to the gate drive board. The basic features of the development board used with the FPGA are • • • • • • • Actel APA075 ProASIC Plus FPGA Maximum System Gates 75000 Embedded RAM bits 27*1024 Maximum user I/O 158 On board clock oscillator ( 40 Mhz) Eight LED’s Four switches
Timer value (counts) Step change Triangular waveform
Signal
Time TMX320F2812 PWM output Missed pulse
Desired PWM output (FPGA output)
Figure 334. DSP builtin PWM output performance vs. FPGA
Intelligent power module
The Intelligent Power Module or IPM is an isolated base module, composed of several IGBTs and designed to reduce the system’s development time, thanks to its builtin gate drive circuit. The IPM module selected for this application was the PM50RSA120 IPM from Powerex. Its main features were • Gate Drive Circuit
108 • • • • • Protection Logic: short circuit, over current, over temperature, under voltage Maximum collectoremitter voltage 1200 V Collector Current 50 Amps Maximum PWM input frequency 20 kHz Minimum deadtime 3.0 µs Figure 335 shows the power circuit configuration of the PM50RSA120. The brake section (B) of the IPM was not used in the implementation of the power stabilizer.
P
W B U V
N
Figure 335. IMP power circuit configuration
Isolation interface circuit
One of the critical components in the design of the power stabilizer was the interface circuit between the IPM and the low side control signals. Even though the IPM had a builtin gate drive, there were still some interface circuit requirements that had to be satisfied in order to avoid noise problems. The isolation interface required was provided by optocouplers, which would be driven by the Darlingtons transistors of the interface board. Figure 336 shows the isolated interface circuit used for the IPM.
Power Stabilizer Software Description
The software tools used in the programming of the FPGA and the DSP are Actel Libero Gold Integrated Design Environment (IDE) and Texas Instruments Code Composer Studio (CCS). Different C code generation tools were considered in order to reduce system development time and to increase flexibility and readability in the design. The different
109 alternatives evaluated were VisSim/Embedded Controls Developer from Visual Solutions and Matlab embedded target for TI C2000 toolbox. However, neither one of them offered the flexibility, readability and efficiency needed for this type of application.
U61 4 5 6 +20V_IN +20V_IN +20V_IN +15V_3 J17 1 2 VOLTAGE SUPPLY 20 V F P_20V N_20V C19 330uF COM_3 12 11 +15V_4 COM_4 14 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CONN 20 F GND U_F0S V_F0S W_F0S BRC F0S +20V
+15V_2 COM_2 1 2 3 COM_IN COM_IN COM_IN COM_1 M5714001 +15V_1
10 9
TO INTERFACE BOARD (status signals)
8 7
J18 UP1 UP2 VP1 VP2 WP1 WP2 UN1 UN2 VN1 VN2 WN1 WN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CONN 20 F SU 3 4 1 R43 ??? 2 3 4
U62 NC1 20 KOhms ANODE CATHODE NC4 HCNW4506 U64 1 R45 ??? 2 ANODE CATHODE NC4 HCNW4506 U66 1 R47 ??? 2 3 4 NC1 20 KOhms ANODE CATHODE NC4 HCNW4506 U68 1 R49 ??? 2 3 4 NC1 20 KOhms ANODE CATHODE NC4 HCNW4506 R51 1.5 K 2 U70 1 R52 1.5k 2 3 4 NC1 20 KOhms ANODE CATHODE NC4 HCNW4506 U71 8 U72 1 R54 ??? 2 3 4 NC1 20 KOhms ANODE CATHODE NC4 HCNW4506 SHIELD VL VO GND VCC 8 7 6 5 C35 0.1uF C36 10uF R55 10k W_N C34 0.1uF 7 6 5 VCC 20 KOhms VL VO GND HCNW4506 SHIELD ANODE CATHODE NC4 NC1 1 2 3 4 V_N1 F0 SHIELD VL VO GND VCC 8 7 6 5 C32 0.1uF C33 10uF R53 10k V_N 3 4 ANODE CATHODE NC4 HCNW4506 SHIELD SHIELD VL VO GND VCC 8 7 6 5 C29 0.1uF C30 10uF R50 10k V_NC 1 U69 NC1 20 KOhms VL VO GND VCC 8 7 6 5 V_N1 BR C31 0.1uF V_NC V_N1 U_N HCNW4506 C28 0.1uF SHIELD VL VO GND VCC 8 7 6 5 C26 0.1uF C27 10uF R48 10k V_WPC V_WP1 W_P C25 0.1uF SHIELD NC1 20 KOhms VL VO GND VCC 8 7 6 5 C23 0.1uF C24 10uF R46 10k V_VPC V_VP1 V_P 8 7 6 5 SHIELD VL VO GND VCC 8 7 6 5 C20 0.1uF C21 10uF R44 10k V_UPC C22 0.1uF V_UP1 U_P 8 7 6 5 U63 VCC 20 KOhms VL VO GND HCNW4506 SHIELD ANODE CATHODE NC4 NC1 1 2 3 4 V_UP1 U_F0
RU
U65 VCC 20 KOhms VL VO GND HCNW4506 SHIELD ANODE CATHODE NC4 NC1 1 2 3 4 V_VP1 V_F0
FROM INTERFACE BOARD (control signals)
TU
U67 8 7 6 5 VCC 20 KOhms VL VO GND SHIELD ANODE CATHODE NC4 NC1 1 2 3 4 V_WP1 W_F0
RL
SL
TL
Figure 336. Isolated interface board Figure 338 shows the name of the variables used in the programming of the DSP and FPGA, and also the different links between the different subsystems.
Description of DSP program
The programming of the DSP power stabilizer control and communications was probably the most complex one in our entire project, since it required the knowledge not only of the control algorithm, but of the system configuration as well. To increase the readability of the code, a series of object oriented modules were created in C. The majority of the modules were generated using the IQmath, a quasi floating point toolset, from Texas Instruments [42], with the intention of increasing the
110 control algorithms’ accuracy. A detailed description of the main modules used in the implementation of the control scheme can be found in Appendix C. The power stabilizer control algorithm was split in main blocks according to the time constants involved. These two blocks were the “power limiters control loop”, and the “current controller loops”. Figure 337 explains how the control algorithm was divided into two sections and the components that were included in each one. On the one hand, power fluctuations due to changes in wind speed were not expected to have significant changes within time intervals smaller than 100 milliseconds. Thus, a control loop with a sampling frequency equal 10 Hz was used to determine the amount of power required to filter out windfarm power variations. On the other hand, since the inverter performance was based on how accurately the system current was controlled, inner current loops had a faster sampling rate. The splitting up of the control scheme into two main loops released some time out of the DSP, and reduced the amount of data needed to be stored.
Iwinda Vpcca Iwindb Vpccb Iwindc Vpccc
X
Ramp Rate Average Inst
Vstorage
Centering algorithm
X
+ + +
Wind Power
Limiters
10Hz
Vpcc_offset
X
+ +
PowerInverter Reference
ESA required power
Klimit
+
Allowedcenteringpower
38880 Hz
1.5 pu
Idrinv Idref +
Vpcc_offset
Current Limiter
Vdf wLIqinv +
PI regulator
+ Vdinv
Vdqinv = V
2 dinv
Vapu
Idref Vdr Vpcc ref + Ki
1 s
+

Constant angle Max Magnitude
1.5pu
+V
2 qinv
Vdqinv
0
V dqinv_limited
Vdinv_limited =
Vdqinv_lim ited
2 1 + K dqinv
V dinv _limited V qinv _limited
+ + + V flata
+ + + 
iPark V1
PWMVa PWMVb PWMVc 
M
Kp
M
M
+ +
M M
Iqref + Iqr inv
K dqinv =
PI regulator
Vqinv Vdinv
drqr ds qs
K dqinv
Vpcc positivesequence
M
+ + Vqf
Vqinv + wLIdinv
Vqinv_limited = K dqinv ⋅Vdinv_limited
V ds inv d q s s Vqs inv abc
iClark V1
V bpu V c pu
sin(theta) cos(theta)
d c (formodulationindex calculation)
V
Vflatb + 2 Vflatc
+ +
Vflat
Iinva Iinvb Iinvc
Clark I1
abc dsqs Ios
Ids Iqs
Park I1
dsqs dr qr
sin(theta) cos(theta)
Idrinv Iqr inv
To current regulator
V pcca V pccb V pccc
Clark V1
abc ds qs Vos
Vds V qs V ds Vqs
PLL
PLL (2 sec time constant) Theta sin(theta) cos(theta)
Park V1
Vds V qs Vqs
Delay (t1/f /4) Delay (t1/f /4)
dsqs dr qr
Vdr V qr
To current regulator
Vds + 
sin(theta) cos(theta) 0.5
Vds positivesequence Vqs positivesequence
Park V1
positivesequence
0.5
sin(theta) cos(theta)
Iinva V fa Iinvb V fb Iinvc V fc
V2dcref
X
V2dc + +
+ 
PI regulator
X
Inv erter Power
+ +
Ichopperref + Ichopper
KL
+ Vstorage
Vchopper
Vdc_link
Vdc_link
Vchopper_limited
V chopperpu + PWMchopper
X
V storage
d c (formodulationindex calculation)
V
Figure 337. Power stabilizer control algorithm sampling rates
X
+ +
ds qs dr qr
Vdrpositivesequence Vqrpositivesequence
X
+ +
Slidingwindowfilter (1cycle)
Filter
Vpcc positivesequence
To PCC voltage regulator
WF1
WIND FARM Phase C Phase B 2 1 Phase A 3
IWINDAP IWINDAN IWINDBP IWINDBN IWINDCP IWINDCN
D/A OUTPUT1 GND D/A OUTPUT2 GND D/A OUTPUT3 GND D/A OUTPUT4 GND D/A OUTPUT5 GND D/A OUTPUT6 GND D/A OUTPUT7 GND D/A OUTPUT8 GND
GPIO WR WR VPCCN VPCCB VPCCN A0 A1 A2 LDAC VPCCC VPCCN GND A0 A1 A2 LDAC GND VPCCA VFILTERA VFILTERN VFILTERB VFILTERN IWINDA IWINDA IWINDB IWINDC VPCCA VPCCB VPCCC VFILTERA VFILTERB VFILTERC IESAA IESAB IESAC V_DC_LINK1 V_DC_LINK2 ICHOPPER VSTORAGE GND IESAAP IESAAN IESABP IESABN IESACP IESACN VFILTERN IWINDB IWINDC VPCCA VPCCB VPCCC VFILTERA VFILTERB VFILTERC IESAA IESAB IESAC V_DC_LINK1 V_DC_LINK2 ICHOPPER VSTORAGE GND A/D UP1A UP2A VP1A VP2A WP1A WP2A UN1A UN2A VN1A VN2A WN1A WN2A BRCA U_F0SA V_F0SA W_F0SA F0SA +20V GND VFILTERC
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
1
1
L6 TRAFO EQUIVALENT 5% 1 2
L3 TRAFO EQUIVALENT 5% 2 C1 C FILTER 10%
L1 TRAFO EQUIVALENT 5% 2
DSP DSP Development Board UP1 UP2 VP1 VP2 WP1 WP2 UN1 UN2 VN1 VN2 WN1 WN2 BRC U_F0S V_F0S W_F0S F0S +20V GND MEASUREMENT
C3 C FILTER 10% 1
1
C5 C FILTER 10%
L7 L FILTER 10% 1 2
L4 L FILTER 10% 2
L2 L FILTER 10% 2 IPM1 IPM 1
PWM_A0 PWM_A1
PWM_LATCH PWM_D0 PWM_D1 PWM_D2 PWM_D3 PWM_D4 PWM_D5 PWM_D6 PWM_D7 PWM_D8 PWM_D9 PWM_D10 PWM_D11 PWM_WR
RESET
SF STOP RESET PWM_A0 PWM_A1 SF STOP PWM_WR PWM_D0 PWM_D1 PWM_D2 PWM_D3 PWM_D4 PWM_D5 PWM_D6 PWM_D7 PWM_D8 PWM_D9 PWM_D10 PWM_D11 PWM_LATCH
GND GND VDD HW STOP S1 PWM_UP PWM_UN PWM_VP PWM_VN PWM_WP PWM_WN PWM_CP PWM_CN GND
IPM INTERFACE A IPM interface board A
Measurement & Interface board
V_UPC U_F0 U_P V_UP1 V_VPC V_F0 V_P V_VP1 V_WPC W_F0 W_P V_WP1 V_NC V_N1 BR U_N V_N W_N F_0
PWM_UP PWM_UN PWM_VP PWM_VN PWM_WP PWM_WN PWM_CP PWM_CN GND UP1B UP2B VP1B VP2B WP1B WP2B UV +24V UV +15V UV +5V UV +3.3V UV 15V DC_LINK_ERROR1 DC_LINK_ERROR2 VSTORAGE_ERROR IESAA_ERROR_P IESAA_ERROR_N IESAB_ERROR_P IESAB_ERROR_N IESAC_ERROR_P IESAC_ERROR_N ICHOPPER_ERROR_P ICHOPPER_ERROR_N U_FOSERRORA V_FOSERRORA W_FOSERRORA FOSERRORA U_FOSERRORB V_FOSERRORB W_FOSERRORB FOSERRORB GND UV +24V UV +15V UV +5V UV +3.3V UV 15V DC_LINK_ERROR1 DC_LINK_ERROR2 VSTORAGE_ERROR IESAA_ERROR_P IESAA_ERROR_N IESAB_ERROR_P IESAB_ERROR_N IESAC_ERROR_P IESAC_ERROR_N ICHOPPER_ERROR_P ICHOPPER_ERROR_N U_FOSERRORA V_FOSERRORA W_FOSERRORA FOSERRORA U_FOSERRORB V_FOSERRORB W_FOSERRORB GND 15V FOSERRORB GND +3.3V +5V VSTORAGEN VSTORAGEP +15V +24V C4 C STORAGE ICHOPPERP ICHOPPERN UN1B UN2B VN1B VN2B WN1B WN2B BRCB U_F0SB V_F0SB W_F0SB FOSB +20V GND UP1 UP2 VP1 VP2 WP1 WP2 UN1 UN2 VN1 VN2 WN1 WN2 BRC U_F0S V_F0S W_F0S F0S +20V GND 1 L5 L CHOPPER 2 IPM INTERFACE B IPM interface board B FPGA FPGA Develpment Board V_UPC U_F0 U_P V_UP1 V_VPC V_F0 V_P V_VP1 V_WPC W_F0 W_P V_WP1 V_NC V_N1 BR U_N V_N W_N F_0 V_DC_LINK_P1 V_DC_LINK_P2 V_DC_LINK_N1 V_DC_LINK_N2 C2 C DC LINK
HW STOP BUTTON
IPM2 IPM 2
111
Figure 338. Interconnections between the different subsystems of the power stabilizer
+5V 15V GND POWER SUPPLY +15V +24V +3.3V PWR1 GND
112 As stated in the previous chapter, the switching frequency selected for the power stabilizer was 4860 Hz. However, the inner loop regulators had a sampling frequency that was 8 times the PWM frequency. The goal was to reduce inverter time responses to system transients, increasing the power stabilizer’s bandwidth. This technique is called resampled uniform PWM [43], and is a digital approximation to the naturally sampled PWM technique. A flow chart illustrating the different stages the power stabilizer undergoes is shown in Figure 339. The time base used for the power stabilizer control algorithm was based on the FPGA synchronization signal that would force the DSP to run at 38,880 Hz. During the startup of the machine, the frontend inverter of the power stabilizer acted as a three phase rectifier, charging the DC link capacitor bank. Once the simulated electric network was running at rated frequency and voltage, the chopper of the power stabilizer would charge the energy storage system to 90% its nominal value. Then the control system would reverse the power through the chopper, so the DC link voltage could be charged to its nominal value. Once both systems, the DC link bus and the ESS, were within a reasonable range and close to their nominal values, the power stabilizer switched to normal mode, where power could flow in both directions. Figure 3 40 shows the power interchange between the electric power system and the power stabilizer, during the different stages.
113
Modules Initialization
Data acquisition
A/D offsets calculation
Watchdog reset
Data convertion A/D offsets calculation
Overcurrent protection
Power Limiter control scheme
Operation Mode Wait mode
Vdc_link>590V?
Yes No
Background control loop (f=10 Hz)
Yes
Charging Energy Storage
No
Vdc_link>590V?
No
105%<Energy>90% ?
Yes Yes
Charging DC link
No
Vdc_link>590V?
No
DC Energy>95% ?
Yes
FPGA synchronization signal (f=38880 Hz)
Run mode
Foreground control loop (f=38880 Hz)
Figure 339. Power stabilizer control stages
DC link charge during machines startup sequence STAGE 1
ESS is charge to 90% of its nominal value STAGE 2
STAGE 3
DC link is charged to 800Volts
STAGE 4
Normal operation
Figure 3 40. Power stabilizer startup sequence
114 During the Power stabilizer’s normal operation, several tasks, besides the control algorithm, had to be carried out. These actions were • • • • Update control actions Update data logging for PCDSP communications Refresh DAC Update FPGA PWM signals
FPGA program description
All the main system components ended up using part of the FPGA for different purposes. However, the main functions were for PWM and error generation. The FPGA code was split into two independent systems, one for the control of the different machines and the other for the control of the power stabilizer. Figure 341 shows the main modules implemented in the FPGA (the software tool used for the programming is ViewDraw from Actel ). Among all these modules, only three were of vital importance for the proper performance of the system. The main modules were • • • PWM generator and the DSP synchronization Dead time generator Watchdog logic
PWM generator and DSP synchronization. The basic idea consists of using an
up/down counter as a triangular waveform generator, so the up/down counts can be compared to voltage demand for phase a, phase b, phase c, and the chopper. The PWM triangle count used a counter that was one more bit than the up/down triangular count would require. For instance, for an up count of 01023, and a down count of 10230, instead of using a 10 bits counter, the one used for this approach would be 11 bits (N bits). The higher order Nth bit was used to invert the lower order N1 bits when it was high (Figure 342). Only the lower order N1 bits were used in the triangle
115 comparator, since a 10bit word was sent from the DSP to the FPGA, containing information on the voltage commands. The format of the word sent from the DSP to the FPGA required a small code manipulation, before it was actually compared to the up/down triangle. Since the DSP voltage commands were represented by signed integers, a flip of the highest order bit was all that was need to convert a signal from signed 1.x to unsigned integer. For instance, a (10bits) #0000000000 would be converted into #1000000000, which is about half of the count range. B#1000000000 would convert to B#0000000000, the minimum, and B#0111111111, would be B#1111111111, the maximum. As far as the maximum value that could be sent to the FPGA, there were a couple of remarks; it was possible to send values that ranged between the minimum and maximum triangle count. However, this presented the following problem; when the values were B#0000000000 >= B#0000000000, the output was high, and when it was B#1111111111 >= B#1111111111, the output was also high. This gave a high bias to the output for an average around zero. This effect was canceled out by the fact the number range was one count larger in the negative direction. The other problem was that as very narrow notches were being generated, the underlap circuitry that prevented shootthroughs did a poor job of reproducing them. The device in the pole with the high duty cycle continued to switch until the notch disappeared. Suddenly, the underlap circuit was not required to do anything, and the voltage took a small jump in the direction of the high duty cycle switch. The low duty cycle switch stopped conducting when the notch time got to be shorter than the underlap time. The deadtime presented a problem in that the current defined what the voltage ended up being during this time. However, when the low
116 dutycycle switch stopped coming on, the problem become worse. One way to reduce both of these effects was not to send a value that would stop the low duty cycle IGBT from switching. This value was approximately defined as:
Maximum output voltage = 1 − 2 ⋅ dead − time ⋅ modulation frequency Thus, if the deadtime is 2 µsec, the maximum value that can be sent to the FPGA is 0.96 pu.
Figure 341. FPGA system overview
117
A
B
Figure 342. Up/Down counter. A). Digital triangular waveform. B).Detail of the countfold effect. The output of the comparators (A>=B) were cleaned up by the D flipflops at the outputs since the comparator outputs could transiently glitch as the logic settled, after a rising clockedge. These PWM state signals were then sent to deadtime generators as shown in Figure 343.
f output=10 Mhz
finput=40 Mhz
DSP synchronization signal
Deadtime generator
PWM generator
Figure 343. PWM generator
118 The DSP synchronization pulse was a latched (and one clock delayed) signal and generated 8 times per PWM cycle (4860Hz). It was true one clock cycle after any count, when the least significant 8 bits were low. Therefore, the DSP control loop ran at a frequency of 38,880Hz Note: Due to clock limitations, the actual PWM frequency was 10MHz/211 = 4882.8 Hz, and the DSP control loop frequency was 10 MHz/28 =39063 Hz. These values were only 0.47% off compared to the designed values.
Deadtime generator. The deadtime generator ensured that no shootthrough
conditions were given in the IPM module. The IPM minimum deadtime was 3µsec, consequently a 4µsec deadtime was used in order to guarantee system performance during switching conditions. Figure 344 shows how the deadtime generator was implemented in the FPGA. Two counters were turned on/off according to the PWM input signal. Their output signals (counts) were then compared to a constant (number of counts). In this case the constant selected was 40. Thus, the delaytime was: dead − time = constant 40 = = 4μ sec clock frequency 10Mhz
PWM output signals were then enabled or disabled based on a trip signal that included information about all the possible flags/errors in the system. Figure 345 shows the FPGA deadtime performance for phase A of the frontend inverter.
119
PWM upper IGBT
PWM
PWM lower IGBT
CLOCKSIGNAL ERRORSIGNAL
Figure 344. One phase deadtime generator detailed diagram
Figure 345. Deadtime generator’s waveforms
Watchdog logic. The F2812 DSP has a builtin watchdog timer that provides a
safeguard against CPU crashes by automatically initiating a reset if not serviced by the CPU at regular intervals. This is a very useful tool for applications where the PWM signals are generated from the DSP, since any CPU reset will put the PWM outputs to a high impedance state, which should turn off the power converter. However, for our application, the PWM generation was carried out by the FPGA, and therefore a builtin watchdog timer had to be implemented. Figure 346 shows the logic used to realize the watchdog timer that mimicked the one implemented in the DSP.
120
Watchdog counter
29 different error signals
Figure 346. Watchdog logic The Watchdog timer was a 9bit counter that generated an error signal (terminal count) after 2 9
10 Mhz = 51 . 2 μ sec
, if not serviced by the DSP. The way the DSP attended
the watchdog timer was by sending a specific word to the FPGA. The following table explains meaning of the different words used for the control of the watchdog timer, and also the reset signals. Table 33. FPGA code words Value written Objective into the data bus Reset error signals 0x055 Watchdog reset Frontend inverter and Chopper turn off signal Inverter turnon signal Chopper turnon signal 0x0AA 0x0EE 0x088 0x033
Description This value will clear all the flipflops used to latch error signals This value will reset the watchdog timer This value will disable both, the inverter and the chopper of the power stabilizer This value will enable the inverter part of the power stabilizer This value will enable the chopper part of the power stabilizer
Note: It is assumed that a DSP general purpose I/O pin was assigned to latch the FPGA data input. The latched value was cleared by the “DSP synchronization” signal; so that no values were held in the latch for more than one DSP control loop cycle. In this application the GPIO had the name of DSP_WD.
CHAPTER 4 SYSTEM PERFORMANCE
System Data
Table 41 summarizes the system parameters used in the modeling of the power stabilizer system. A comparison with the ideal values based on the perunit designed system is also included. These differences caused a small deviation from the ideal system. However, the overall system performance was not significantly decreased.
Power Stabilizer Transient Response
The following sections illustrate the power stabilizer response due to stepchanges in the different values. System performance was analyzed under various scenarios.
DirectCurrent Link Voltage Control
One of the key variables in the overall system performance was the voltage at the DC link bus, since PWM control actions were based on it. Thus, its value had to be tightly controlled. Figure 41 and Figure 42 show the DC link voltage responses to a stepchange in the voltage reference for different regulator gains.
Figure 41. DC link voltage response for different Kp gains 121
122 Table 41. System parameters Variable DC link time constant (sec) ESS time constant (sec) ( @ Vess max) Chopper current ripple (pu) PWM (Hz) X/R Xfilter (pu) Xtrafo (pu) Cfilter size (Vars pu) Vmax lineneutral I max inverter nominal Vdc nominal Vrms lineneutral Irms inverter nominal Zbase (Ω) Pinverter Vstorage max Vstorage min Vstorage center Cdc link (mF) Cstorage (F) Lchopper (mH) Rchopper (Ω) Lf (mH) Rf (Ω) Cf (uF) Lt (mH) Rt (Ω) Kp current regulator Ki current regulator (R/L) Kc (charge/discharge constant)(Watts/Joules) 1/2*Cstorage (pu) K=1/2*Cstorage (pu) * Kc (Watts/Volts2) Perunit model 0.022 20.45 0.3 4860 10 0.1 0.06 0.03 1 1 2.04 0.71 0.71 1 1.5 1.94 0.97 1.53 16 16.323 0.5 0.019 0.265 0.01 79.58 0.159 0.006 1 37.7 0.0064 8.16 0.052 Ideal model 0.022 20.45 0.3 4860 10 0.1 0.06 0.03 391.92 0.256 800 277.13 0.18 1536 150 760 380 600.83 0.0103 0.0106 768.18 28.96 407.44 15.36 0.052 244.46 9.22 1 37.7 0.00647 8.16 0.052 Real model 0.032 22.23 0.34 4860 18 0.103 0.074 0.029 391.92 0.256 800 277.13 0.18 1536 150 760 380 600.83 0.015 0.0116 660 14.6 420 8.2 0.050 300 7.00 1 18 0.00647 8.86 0.057
Figure 42. DC link voltage response for different Ki gains
123 It can be inferred from Figures 41 and 42 that the DC link voltage regulator was very robust, and that large changes in the regulator’s gain would not affect the system performance. In general, higher proportional gains improved DC link voltage settling time, without causing any system overshoot as in the case of high integral gains. However, higher gains caused control actions to saturate and could have originated instabilities.
Reactive Current Control
The core of the Power stabilizer was the inner current regulators. Their performance determined the overall system response. The current regulators’ robustness is shown in Figure 43 and Figure 44. As expected, the increase in the integral and/or proportional gains had no major impact on the current response. This was due to the saturation of control actions, as seen in Figure 45. The original current regulator gains were designed to avoid possible saturation situations due to a step change in the error of 1 pu. Figure 46 shows the Power stabilizer current waveform during a multiple stepchange in the reactive current reference.
A
B
C Figure 43. Iqref command step change from 0.5 to 0.5 A per unit. Integral gain effect. A) Inverter’s reference output voltage. B) Inverter current. C) Inverter’s Iq.
124
Figure 44. Iqref command step change from 0.5 to 0.5 A per unit. Proportional gain effect
Figure 45. Iq current regulator output for different Kp
A
B
C
Figure 46. Iqref command step change from 0.5 to 0.5 and back to 0.5 A per unit. A) Inverter’s reference output voltage. B) Inverter current. C) Inverter’s Iq.
125 The current control loop bandwidth was also tested and compared to the ideal system. A variable frequency sinusoidal waveform was introduced into the control loop references (Iqref and Idref) to study the reduction in amplitude as the frequency of the input signal increased. The signal references can be defined as
I d ref = I max ⋅ cos((h − 1) ⋅ wt ) I q ref = I max ⋅ sin((h − 1) ⋅ wt ) w = 2 ⋅ π ⋅ 60
Where h is the desired harmonic. For this test the amplitude selected for the signal amplitude was 0.5 Amps per unit. Figure 47 shows the different current output amplitudes for the different harmonics.
Figure 47. Power stabilizer harmonic injection response for Ki=18 and Kp=1 The bandwidth of the current regulators could then be compared to the ideal system as shown in Figure 48. As expected the bandwidth of the real system was lower than the ideal one due to the increase in the amount of system impedance. However, this reduction
126 in bandwidth did not have any impact in the system performance, since no harmonic compensation was required.
Figure 48. Current regulator frequency response
Passive Filter Performance
LCL filter design was also tested and compared to the ideal attenuation gain. Figure 49 shows the current waveforms before and after the LCL filter.
Figure 49. Frontend inverter current waveform The peak to peak ripple current was 0.06 A, and it was very similar to the expected value: 0.0572 A (0.2214pu*0.22515A=0.0572A).
127 Figure 410 shows the frequency spectrum of Figure 49. It can be deduced that the filter attenuation gain was 19 dB.
Figure 410. Frequency spectrum of the LCL currents
Voltage Regulation
The Power stabilizer did not just have the capacity of filtering power variations, but voltage fluctuations as well. By controlling the amount of reactive current injected into the system, it was possible to modify the voltage profile at the windfarm terminals. Figure 411 shows a simplified diagram of the different impedances that played a significant role in the voltage regulation scheme.
1% from the Power Stabilizer point of view 17.67% from thePower Stabilizer point of view
Vsource
V=480V
L=44mH
5.4% from the Wind farm point of view
Vpcc Lf = 720mH
Ipower stabilizer
Vinveter
P=150W
Main Load
Vwind
P=750W
Figure 411. Simplified system description
128 If Vsource is considered to be stiff, the maximum increment in voltage at the point of common coupling for a 150 W rated Power Stabilizer is ΔV = Vsource − V pcc = X line ⋅ I inverter rated rms ⋅ 2 = 0.044 ⋅ 60 ⋅ 2 ⋅ π ⋅ 0.25515 ⋅ 2 = 5.98 V 2
Figure 412 shows the voltage at the point of common coupling when the Power Stabilizer went from full inductive to full capacitive and back to full inductive. It can be deduced from the previous calculation, that for the given power rating, the voltage regulation capabilities of the Power Stabilizer were modest (±0.77%).
A
B
Figure 412. Power stabilizer voltage regulation performance. A) Voltage at the point of common coupling. B) Inverter Iq component.
System Losses
Due to the size of the equipment, system losses were expected to be a significant proportion of the power ratings, compared to a fullsize system. In particular, for the Power Stabilizer, the main losses were:
129 • • • • • Conduction losses Switching losses I2R Core losses Capacitor leakage current Because of these losses there was an expected asymmetric charge/discharge cycle of the energy storage system. Figure 413 shows this effect. To compensate for these losses the Power Stabilizer was biased such that no control action from the energy storage regulator was needed. Figure 414 shows the compensation term in the overall control algorithm.
A
B
C
Figure 413. Energy storage charge/discharge cycle. A) Chopper output power. B). Energy storage voltage and current. C) ESS’s energy.
Losses _ + Idref
Current Regulators
Power Limiter ESS Voltage regulator
Vd Vq
Limters and Transformations PWM
PCC Voltage regulator
Iqref
Figure 414. Control scheme with a losses compensation term
130 The effect of introducing a loss compensation term in the control algorithm had the same effect as modeling the Power Stabilizer as a nostatic inverter/chopper in parallel to a resistive load (Figure 415). The losses were estimated to be around 20Watts for the nonload condition.
Power Stabilizer
Synchronous Machine Losses=20Watts Line Impendace Filter Wind Farm
Main Load 4.5 KW
Figure 415. Power stabilizer equivalent system
Power Limiter Results
When trying to compensate for power fluctuation, two different approaches were considered, tested, and compared in detail. The windpower data used for the comparison was 15 minutes of data from a wind farm on the big island of Hawaii. The frequency scan of the data was 15 minutes, and it corresponded to high wind conditions. The wind farm consisted of 37 Mitsubishi 250 kW wind turbines, with a total capacity close to 10 MW (Figure 416).
Figure 416. Windpower conditions under study
131 The time response of the induction machine’s power controller was low enough to be able to reproduce the changes in power using step variations. However, this type of behavior was unrealistic and therefore a linear interpolation was used between the two consecutive scans.
Power Limiter 1 (High Pass Filter)
The transfer function of the high pass (HP) filter used in the design of the first power limiter is shown in Equation 41.
H (s) = s 2 ⋅ π ⋅ f cut −off + s
(41)
The only parameter that needed to be determined according to the system requirements was the cutoff frequency. Figure 417 shows the Power Stabilizer response to windpower fluctuation using a HP filter with a cut off frequency of 0.005Hz. It can be concluded from Figure 417 that the Power Stabilizer had a very good performance smoothing windpower fluctuation as long there was enough energy storage available. However, such a control scheme generated abrupt changes in power when the power converter reached the energy limits. These types of situations should be avoided, since the step changes in power could be even higher than the ones naturally produced by the windfarm output power. Figure 418 is a zoom of the exact moment where the Power Stabilizer ran out of energy. When the Power Stabilizer reached the minimum energy limit, the power delivered to the utility did not only drop down to what the wind farm was producing, but it overshot due to the energy absorbed by the Power Stabilizer (also called centering power). That power was designed to be small in magnitude (proportional to the charge discharge constant Kc), but still had a negative impact on the system.
132
A
B
C
Figure 417. Measured and modeled high pass filter results for Kc=0.0064 W/J, fcut_off=0.005 Hz. A) Power to utility. B) Power stabilizer output power. C) Power stabilizer energy level
133
A
B
C
Figure 418. Measured and modeled high pass filter results for Kc=0.0064 W/J, fcut_off=0.005 Hz (zoom in). A) Power to utility. B) Power stabilizer output power. C) Power stabilizer energy level
134 In order to circumvent such types of situations we considered three different approaches: • Increased the cutoff frequency, so the Power Stabilizer only compensated for higher frequency power fluctuations. Figure 419 shows the system response to different cutoff frequencies. Figure 420 confirms the results by using the Matlab model. It was clear that only high cutoff frequencies could help the system from reaching the energy limits. The drawback of higher cutoff frequencies was obvious; less power smoothing effect. Increased the size of the energy storage, so the system could face larger power fluctuations for a given cutoff frequency. Figure 421 shows a comparison between a system with nominal energy and a system with an extra 66% of energy. Even with an increase of more than half in energy the power converter was unable to compensate for large swings in wind power without running out of energy. Adaptive high pass filter. The idea behind this control strategy was to vary the cutoff frequency according to the status of the energy storage. The closer the Power Stabilizer energy storage system was to the nominal value, the more filter was allowed (Figure 422).
•
•
A
B
C
Figure 419. Measured high pass filter performance for different cutoff frequencies. System parameters Kc=0.0064 W/J. A) Power to utility. B). Power stabilizer output power. C) Power stabilizer energy level
135
A
B
C
Figure 420. Modeled high pass filter performance for different cutoff frequencies. System parameters Kc=0.0064 W/J. A) Power to utility. B). Power stabilizer output power. C) Power stabilizer energy level
A
B
C
Figure 421. Measured high pass filter performance for different energy storage sizes. System parameters, Kc=0.0064 W/J, fcutoff=0.005 Hz. A) Power to utility. B). Power stabilizer output power. C) Power stabilizer energy level
136
f
cutoff
f
cutoff_origin
Energy
Energy nominal value
Figure 422. Cutoff frequency trajectory of the adaptive high pass filter for a given energy deviation
Power Limiter 1 (Adaptive High Pass Filter)
The adaptive high pass filter control scheme was designed to avoid saturation situations, yet allowing power fluctuation smoothing. In the adaptive filter control algorithm the number of parameters that needed to be optimized were two; fcut_off_rigin and the slope of the variable cutoff frequency. Equation 42 shows the relationship between energy deviation and cutoff frequency used for the adaptive high pass filter.
f cut −off = f cut −off −origin + K f ⋅ ΔE
(42)
Figure 423 shows the real system response for different Kf. The fcut_off_origin was kept constant to 0.005 Hz. It can be concluded from Figure 423 that when high pass filter parameters were optimized the system could ride through large windpower fluctuation without reaching the energy limits. Figure 424 shows the adaptive high pass filter response using an extra 66% of energy. Measured results were compared to the one obtained using nominal energy capacity. System parameters were: Kf=0.0059 Hz/J, Kc=0.0064 W/J, and a frequency of fcut_off_origin=0.005 Hz.
137
A
B
Figure 423. Measured adaptive high pass filter performance for different Kf’s. System parameters, Kc=0.0064 W/J, fcutofforigin=0.005 Hz. A) Power to utility. B) Power stabilizer energy level
A
B
Figure 424. Measured adaptive high pass filter performance for different energy storage sizes. System parameters, Kf=0.0059 Hz/J, Kc=0.0064 W/J, fcut_off_origin=0.005 Hz. A) Power to utility. B) Power stabilizer energy level
138 This approach seemed to work fairly well. However, it lacked applicability. Electric power systems can be disturbed by large power swings, while small power unbalances can be compensated without significant burden. Therefore large power fluctuations should be tackled first, rather than the small ones due to its impact on the system. Thus, there was a need for a better control algorithm that exclusively targeted and compensated for large power variations, while avoiding compensation of less significant events. The goal was to settle down the control actions given by the synchronous machine regulator, so less stress was caused to the synchronous generator.
Power Limiter 2
This approach targeted specific indexes and therefore was more prompt to compensate for large power fluctuation rather than low profile power changes. The indexes considered in our study were the ones used by HECO (Hawaiian Electric Company, Inc.), which were based on a twosecond scan sampling time. The indexes for a 10 MW wind farm were: • Ramp Rate Power Fluctuation: RR = MWs −30 − MWs =2 MW/minute where RR= Ramp Rate, may be calculated once every scan MWs30= The instantaneous MW analog value 30 scans (60s) prior the present scan. MWs = The instantaneous MW analog value for the present scan Instantaneous Power Fluctuation: I = MWs −1 − MWs =0.3 MW/2 sec where I= Instantaneous Power Change, calculated once every scan MWs1 = The instantaneous MW analog value for the previous scan (2 seconds ago) MWs = The instantaneous MW analog value for the present scan • Subminute Average Power Fluctuation: A1 =
•
∑ MW
s =1
30
s −1
− MWs
30
=1 MW/minute
where Al= Subminute Average, calculated once every 30 scans MWs1 = The instantaneous MW analog value for the previous scan MWs= The instantaneous MW analog value for the present scan
139 These numbers had to be scaled down according to the size of the wind farm model. Thus, the actual power indexes considered in the model were: • • • RR=(2/10)*750=150 Watts/minute A=(0.3/10)*750=22.5 Watts/minute I=(1/10)*750=75 Watts/2seconds Note: 750 Watts is the windfarm model rated power. Even though indexes were based on 2second scans, the power limiter control scheme calculated such indexes several times per second, using a multiplesampling control algorithm. Figure 425 illustrates how these indexes, based on 2second scans, could be estimated more than once every two seconds. This allowed for higher refreshing times for the inverter power reference, so that a faster and a more accurate response to wind fluctuations were achieved. Figure 426 demonstrates that the power limiter injected energy when it was really needed. Moreover, the control system only released the necessary amount of energy to meet the indexes, so not all the energy was consumed during the large power fluctuation. It was also evident that since system losses were not corrected 100%, the power converter drew some extra power from the system to compensate for the losses. In the simulation results, only static losses (or losses independent from the inverter current) were considered.
Wind Farm Power
2 seconds 0.5 seconds
2 second scan 2 second sampling rate 2 second scan 0.5 second sampling rate
A1
A2
Figure 425. Multiple sampling concept. For this example a 0.5 second sampling time was assumed
140
A
B
C
Figure 426. Measured and modeled power limiter 2 results for Kc=0.0064, RR=2 MW/minute, A=0.3 MW/minute, I=1MW/2 seconds fcutoff=0.005 Hz. A) Power to Utility. B) Power stabilizer output power. C) Power stabilizer energy level. The activity of the power indexes during the 15 minute period are shown in Figure 427. As expected the power limiter does a very good job trying to keep the power fluctuation indexes within the limits. A significant number of variables could have made the power limiter behave differently. However, only a few of them were considered for our sensibility study: • • • Kc (charge and discharge constant). Nominal value Kc=0.0062 Watts/Joule Power limiter sampling frequency. Nominal value 10 Hz Power indexes. Nominal values RR=2 MW/minute, A=0.3 MW/minute, I=1 MW/2 seconds
141
A
B
C
D
Figure 427. Measured power indexes activity. System parameters: Kc=0.0064 W/J, RR=2 MW/minute, A=0.3 MW/minute, I=1 MW/2 seconds, and fs=10Hz. A) Power stabilizer output power. B) Average power fluctuation. C) Ramp rate power change. D) Instantaneous power fluctuation. Figure 428 shows the effect of increasing the charge/discharge constant. When doing this, there was no impact on the indexes’ activity. However, large charge/discharge constants could have caused the activation of the power indexes, since there was power absorbed (charge) or delivered (discharge) from or to the electric power system. Figure 429 shows the effect of decreasing the ramp rate limits, making them stricter. For this type of windpower fluctuation, the ramp rate activity was the most important one, so that tighter limits could have made the Power Stabilizer reach the energy limits. In general, a ramp rate limit of 1 MW/minute generated a good system response in terms of power fluctuation magnitude and energy capacity required. Lower ramp rate limits would have required larger energy capacity, making the Power Stabilizer a noncost effective solution.
142
A
B
Figure 428. Measured power limiter 2 response to different Kc . System parameters: RR=2 MW/minute, A=0.3 MW/minute, I=1MW/2 seconds, and fs=10Hz. A) Power stabilizer output power. B) Power stabilizer energy level.
A
B
C
Figure 429. Measured power limiter 2 response to different ramp rate limits. System parameters: Kc=0.0064 W/J, A=0.3 MW/minute, I=1 MW/2 seconds, and fs=10 Hz. A) Power to Utility. B) Power stabilizer output power. C) Power stabilizer energy level.
143 Figure 430 shows the effect of decreasing the average power fluctuation limit. In this case the tighter the average power limit was, the worse the response obtained became. The reason for such unusual conduct was found in the way the induction power reference was obtained. Windpower reference was linearly interpolated between two consecutive data samples. Thus, a control scheme using a multisampling strategy (more than one sample per real data samples) perceived an average power fluctuation from the original one. Figure 431 shows the average power fluctuation for different sampling rates. This effect made it almost impossible to judge the pros and cons of different average power fluctuation limits.
A
B
C
Figure 430. Measured power limiter 2 response to different average power fluctuation limits. System parameters: Kc=0.0064 W/J, RR=2 MW/minute, I=1 MW/2 seconds, and fs=10 Hz. A) Power to Utility. B) Power stabilizer output power. C) Power stabilizer energy level.
144
Average power fluctuation (MW/minute)
A
Time (secs)
Average power fluctuation (MW/minute)
Zoom in
Time (secs)
B
Figure 431. Effect of linear interpolation on the average power fluctuation index activity. The sampling time of the original windpower data is 2 seconds. A) Average index. B) Average index zoom in. Figure 432 shows the effect of reducing the instantaneous power fluctuation limit. In general, the system responded fairly well to such limits. However, a special precaution had to be taken when reducing such an index, since it could have caused the power converter to continuously compensate, even for small power variations.
A
B
C Figure 432. Measured power limiter 2 response to different instantaneous power fluctuation limits. System parameters: Kc=0.0064 W/J, RR=2 MW/minute, A=0.3 MW/minute, and fs=10 Hz. A) Power to Utility. B) Power stabilizer output power. C) Power stabilizer energy level.
145 Figure 433 shows the effects of decreasing the sampling frequency (or refreshing frequency) of the power limiter. In general, lower sampling frequencies did not have a major impact on the Power Stabilizer energy. The advantage of using high sampling frequencies was the fact that power indexes were tracked with exactitude, allowing for a more accurate way of assuring the power fluctuations fell within the specified limits.
A
B
C Figure 433. Measured power limiter 2 response to different sampling frequencies. System parameters: Kc=0.0128 W/J, RR=2 MW/minute, A=0.3 MW/minute, and I=1 MW/2 seconds. A) Power to Utility. B) Power stabilizer output power. C) Power stabilizer energy level.
Power Limiters Comparison Study
In determining which of the power limiters had a more desirable impact on the electric power system, one should pay attention to the system’s frequency. In our case, since the frequency regulator of the synchronous machine was tuned to instantaneously compensate for frequency deviations, no frequency variations were expected. Therefore, the only good indicator available to determine the impact of the different power limiters was the control action given by the frequency regulator.
146 Wind farm power fluctuations tended to change the frequency regulator output due to an unbalance in power. Thus, control actions had the tendency to displace up and down from an average value based on the mismatch between mechanical and electrical power (Figure 434).
Figure 434. Measured synchronous machine output power for the different power limiter control schemes It can be concluded from Figure 435 that both, the high pass filter and the adaptive filter had good response filtering “small” power fluctuation. However, when the Power Stabilizer capacity to absorb or supply energy was needed the most, no capacity was available. Only the power limiter 2 and the adaptive HP filter, with 66% of extra energy, were capable of injecting some energy to shaveoff the surge in power. Figure 436 shows the frequency regulator response for the different power limiters. This graph was a consequence of Figure 435 one, and gives a better picture of the benefits of each one of the different power limiters.
147
Figure 435. Measured synchronous machine output power for the different power limiter control schemes. Zoom in of the largest power swing
A
B
C
D
Figure 436. Frequency regulator output for the different power limiters. A) HP filter. B) Adaptive HP filter. C) Adaptive HP filter with 66% extra energy. D) Power Limier 2 In conclusion, we cannot say that there is a better or worse power control scheme, since each one of the different power limiters can serve different purposes.
CHAPTER 5 SUMMARY
Conclusions
The purpose of our study was to develop an electronic power converter capable of compensating power fluctuations typical of wind farms. The proofofconcept converter was designed using similar techniques utilized in the design of medium voltage power quality products. The system design involved the mathematical description of the different equations implicated in the design of the diverse regulators. Special attention was paid to the current controllers, for being the foundation upon which the rest of the system relies on, and to the development of new control algorithms capable of minimizing power fluctuation while optimizing the usage of the energy storage system. Two different power limiter control schemes have been proposed and described in detail. A testbench was developed to mimic a future scenario of an isolated power system. Tests have been conducted under realistic modeled system conditions, in terms of wind penetration factor, and costeffective amount of energy storage. The main conclusions of the tests carried out were: • • The shunt connected voltage source converter has shown to be an excellent approach in terms of speed and flexibility, and power fluctuation smoothing. Two main alternatives for compensating windpower fluctuations using small amounts of energy; power limiters that target low profile power fluctuations and power limiters that compensate according to predefined power fluctuation indexes were studied. These alternatives are usually designed to compensate for large power swings.
148
149 • • High pass filters are not appropriate for power filter functions, due to their lack of continuousness when running out energy. Adaptive high pass filters have shown to be a much better alternative to high pass filters. However, behaviors similar to the simple high pass filter might occur if incorrect adaptive laws are considered. Power limiters that target specific power fluctuation indexes have a lower dutycycle than the high pass filter approach and only compensate for larger power fluctuations. Ramprate indexes are a good alternative to adaptive high pass filters. Instantaneous power fluctuation indexes do no have as much significance as the ramprate indexes Average power fluctuation indexes are highly nonlinear, and might create unwanted misbehaviors that are difficult to predict. Both types of power limiters have shown to be beneficial for the reduction in the control actions of the synchronous machine’s governor. Thus, reducing the stress of the generator during power fluctuations. In summary, among the different power limiter regulators considered in this dissertation, the adaptive high pass filter has been shown as the most robust and reliable when designed correctly. It forces the power converter and the energy storage system to work continuously, getting the maximum effectiveness out the system. It even helps the system ride through large power variations in a moderate way. A drawback for this approach is the wear of the energystorage system, due to high duty cycles. The power limiter based on power fluctuation indexes serves as a very specific solution to a specific problem or need. Its low dutycycle profile in terms of real power allows for better voltage regulation or voltage flicker reduction (using reactive power), in cases where system impedance is relatively large.
•
• • • •
150
Further Work
There is still a lot of work to be done in the area of smoothing real power fluctuations using various types of energy storage systems. The following is a summary of the different subjects that merit additional research: • • • New control algorithms. For instance, new nonlinear adaptive laws or a combination of different power limiters based on energy levels Evaluation of the benefits of real power smoothing. Evaluation of new energy storage systems Our research work has focused entirely on power fluctuations generated by wind farms. However, the same concept can be applied to other producers of realpower fluctuations, such as the continuous switching of large loads, or new nondispatchable distributed resources (wave, solar, etc)
APPENDIX A MATHEMATICAL TRANSFORMATIONS In studying of power systems, mathematical transformations are often used to decouple variables or to help solve of difficult differential equations. The most common and known transformation is the method of symmetrical components developed by Fortescue in 1918 [27]. This method uses a complex transformation to represent an unbalanced system of n phasors into n systems of balanced phasors called symmetrical components of the original phasors. For a threephase system, these symmetrical components are the positive sequence component, the negative sequence component, and a zero sequence component. This relationship can be expressed as
⎡ ⎢ ⎢1 1 ⎤ ⎡Xa ⎤ ⎢ 1 a 2 ⎥ ⋅ ⎢ X b ⎥ = ⋅ ⎢1 ⎥ ⎢ ⎥ 3 ⎢ a ⎥ ⎢Xc ⎥ ⎢ ⎦ ⎣ ⎦ ⎢ ⎢1 ⎢ ⎣ ⎤ ⎥ 1 ⎥ 2⎥ ⎡X ⎤ ⋅ ⎛ j ⋅ 23π ⎞ ⎥ ⎢ a ⎥ ⎜e ⎟ ⋅ Xb ⎜ ⎟ ⎥ ⎢ ⎥ ⎝ ⎠ ⎥ ⎢X ⎥ ⎣ c⎦ 2 ⋅π j⋅ ⎥ 3 e ⎥ ⎥ ⎦
r ⎡X0⎤ ⎡1 1 ⎢r ⎥ 1 ⎢ X 1 ⎥ = ⋅ ⎢1 a ⎢r ⎢ X 2 ⎥ 3 ⎢1 a 2 ⎣ ⎣ ⎦
1 e
j⋅ 2 ⋅π 3
(A1)
⋅ ⎛ j ⋅ 23π ⎜e ⎜ ⎝
⎞ ⎟ ⎟ ⎠
2
Variable X of Equation A1 may be currents, voltages, or fluxes. Written explicitly in terms of real and imaginary components, we have
r ⎛ 1 ⎛ 1 3⎞ 3⎞ ⎟ ⋅ Xb + ⎜− − j ⋅ ⎟⋅ Xc X1 = X a + ⎜ − + j ⋅ ⎜ 2 ⎟ ⎜ 2 2 ⎠ 2 ⎟ ⎝ ⎝ ⎠ r 1 3 (X b − X c ) X 1 = X a − ⋅ (X b + X c ) + j ⋅ 2 2 r ⎛ 1 ⎛ 1 3⎞ 3⎞ ⎟⋅ Xb + ⎜− + j ⋅ ⎟⋅ Xc X 2 = Xa + ⎜− − j ⋅ ⎜ 2 ⎟ ⎜ 2 2 ⎟ 2 ⎠ ⎝ ⎝ ⎠ r 1 3 (X b − X c ) X 2 = X a − ⋅ (X b + X c ) − j ⋅ 2 2
(A2)
151
152
r r It is evident from Equation A2 that space vectors X 1 and X 2 are complex
conjugates of each other. For a balanced threephase system, we have
X a = X m ⋅ cos(wt ) 2π ⎞ ⎛ X b = X m ⋅ cos⎜ wt − ⎟ 3 ⎠ ⎝ 4π ⎞ ⎛ X c = X m ⋅ cos⎜ wt − ⎟ 3 ⎠ ⎝
(A3)
r r Thus, the space vectors X 1 and X 2 can be expressed as
r 1 3 X1 = X a − ⋅ ( X b + X c ) + j ⋅ (X b − X c ) 2 2 3 1 3 = ⋅ X a − (X a + X b + X c ) + j ⋅ ⋅ (X b − X c ) 2 2 2 ⎛ ⎛ 3 3 2π ⎞ 4π ⎞ ⎞ ⎛ ⎜ = ⋅ X m ⋅ cos(wt ) + j ⋅ ⋅ X m ⋅ ⎜ cos⎜ wt − ⎟ − cos⎜ wt − ⎟⎟ 2 2 3 ⎠ 3 ⎠⎟ ⎝ ⎝ ⎝ ⎠ ⎛ 3 3 ⎛ − 2π = ⋅ X m ⋅ cos(wt ) + j ⋅ ⋅ X m ⋅ ⎜ − 2 ⋅ sin (wt ) ⋅ sin ⎜ ⎜ 2 2 ⎝ 3 ⎝ = 3 3 ⋅ X m ⋅ (cos(wt ) + j ⋅ sin (wt )) = ⋅ X m ⋅ e jwt 2 2 ⎞⎞ ⎟⎟ ⎟ ⎠⎠
(A4)
r r * 3 X 2 = X 1 = ⋅ X m ⋅ e − jwt 2
( )
(
)
*
r Defining X = X m ⋅ e jwt = X ds + j ⋅ X qs , the symmetrical transformation matrix
equation can be written as
r r ⎡ X 1 ⎤ 3 ⎡ X ⎤ ⎡1 a ⎢ r ⎥ = ⎢ r *⎥ = ⎢ 2 ⎣ X 2 ⎦ 2 ⎣ X ⎦ ⎣1 a
( )
⎡X a ⎤ a2 ⎤ ⎢ ⎥ ⎥ ⋅ Xb a⎦ ⎢ ⎥ ⎢Xc ⎥ ⎣ ⎦
(A5)
Since (a 2 ) = a , row two can be eliminated without any loss of information (Equation A*
6).
⎡X a ⎤ r 2 2 X = 1 a a ⋅ ⎢Xb ⎥ ⎢ ⎥ 3 ⎢Xc ⎥ ⎣ ⎦
[
]
(A6)
153 Writing the real and imaginary components in two separate rows, and adding the zerosequence component, we obtain the general real transformation (Equation A7).
⎡ 2 ⎤ ⎡ X ds ⎤ ⎢ 1 ℜ(a ) ℜ a ⎥ ⎡ X a ⎤ ⎢ X ⎥ = 2 ⎢ 0 ℑ(a ) ℑ a 2 ⎥ ⋅ ⎢ X ⎥ ⎢ qs ⎥ 3 ⎢ ⎢ b⎥ 1 1 1 ⎥ ⎢X ⎥ ⎢ Xo ⎥ ⎢ ⎥ ⎣ c⎦ ⎣ ⎦ 2 2 ⎦ ⎣2
( ) ( )
⎡ ⎢1 ⎡ X ds ⎤ ⎢ ⎢X ⎥ = 2 ⎢0 qs ⎥ ⎢ 3⎢ ⎢ Xo ⎥ ⎢1 ⎦ ⎣ ⎢2 ⎣
−
1 2 3 2 1 2
1 ⎤ 2 ⎥ ⎡X ⎤ a ⎥ 3⎥ ⎢ ⎥ ⋅ Xb − 2 ⎥ ⎢ ⎥ 1 ⎥ ⎢Xc ⎥ ⎣ ⎦ ⎥ 2 ⎦ −
(A7)
Equation A7 is known as Clark’s transformation, and it transforms a threephase system to an equivalent twophase system. Figure A1 shows the relationships of the different axes. Figure A2 shows the same relationship, but in the time domain.
c axis
a axis
w=0 ω=2 π f w=0
ds axis
X
b axis qs axis
Figure A1. Relationships among dsqs, and abc axes
Figure A2 Stationary dsqs components in the time domain
r As shown by Figure A1, dsqs axes are stationary, while the space vector X
rotates at w=2πf. To achieve high bandwidth in the control algorithm, it is necessary to
154 transform the stationary variables X ds and X qs into X dr and X qr (rotating frame reference).
r We can deduce that an observer moving at the same speed as X will see this space
vector as a constant, unlike the time variant X ds and X qs components of the stationary dsqs axes. Figure A 3 shows the geometrical relationship of the rotating drqr axes with respect to the stationary dsqs axes.
θ
ds axis
w=0
w=2 π f
X
dr axis
w=2 π f
qr axis
qs axis
Figure A 3. Relationship among dsqs and drqr axes This geometrical relationship can be expressed as
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) ⎤ ⎡ X ds ⎤ ⎥ ⎢X ⎥ = ⎢ ⎥⋅⎢ ⎣ qr ⎦ ⎣− sin(θ ) cos(θ )⎦ ⎣ X qs ⎦
(A8)
r The angle Θ is the angle between the d axis of rotating and X stationary dq axes; it is a
function of the angular speed of the rotating drqr axes, that is wt = dθ dt (A9)
Figure A4 shows the decomposition of X ds and X qs into X dr and X qr .
r The angle δ is the angle between the dr axis and space vector X ; it is a constant
vale, and it will depend on the kinds of simplification or formulation best suited to a
155 specific application. The full transformation from stationary reference frame to rotating reference frame, including the zero sequence, is shown in Equation A9.
Xds sin (θ)
Xds θ δ Xds cos (θ) Xqs sin (θ)
ds axis
Xqs cos (θ)
w=2 π f
Xqs
dr axis
qr axis qs axis
Figure A4. Direct and quadrature components
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) 0⎤ ⎡ X ds ⎤ ⎢ X ⎥ = ⎢ − sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ X ⎥ ⎢ qr ⎥ ⎢ ⎥ ⎢ qs ⎥ ⎢ Xo ⎥ ⎢ 0 0 1⎥ ⎢ X o ⎥ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦
w=2 π f
X
(A9)
Figure A5 shows the time domain representation of the three different reference frames, that is abc, dsqs, and drqr, for δ = 0°.
156
Figure A5. Time domain representation of abc and dq components In terms of the original X a , X b , and X c components,
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) 0⎤ ⎡ X ds ⎤ ⎢ X ⎥ = ⎢− sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ X ⎥ ⎢ qr ⎥ ⎢ ⎥ ⎢ qs ⎥ ⎢ Xo ⎥ ⎢ 0 0 1⎥ ⎢ X o ⎥ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ 1 ⎡ ⎢1 − 2 ⎡ cos(θ ) sin (θ ) 0⎤ ⎢ 2 3 = ⎢− sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ 0 ⎥ ⎢ 3⎢ 2 ⎢ 0 0 1⎥ ⎢ 1 1 ⎦ ⎣ ⎢2 2 ⎣
1 ⎤ 2 ⎥ ⎡X ⎤ a ⎥ 3⎥ ⎢ ⎥ ⋅ ⎢Xb ⎥ − 2 ⎥ 1 ⎥ ⎢Xc ⎥ ⎣ ⎦ 2 ⎥ ⎦ −
(A10)
⎡ cos(θ ) cos(θ − 120°) cos(θ − 240°) ⎤ ⎡ X a ⎤ ⎡ X dr ⎤ ⎢ X ⎥ = 2 ⎢− sin (θ ) − sin (θ − 120°) − sin (θ − 240°)⎥ ⋅ ⎢ X ⎥ ⎥ ⎢ b⎥ ⎢ qr ⎥ 3 ⎢ ⎢ 1 ⎥ ⎢X ⎥ 1 1 ⎢ Xo ⎥ ⎣ ⎦ 2 2 2 ⎣ ⎦ ⎣ c⎦
(A11)
In short notation
[X ] = [T ]⋅ [X ]
dqo dqo abc
(A12)
This transformation is called Park’s transformation, and it is wellknown in synchronous machine analysis. The inverse transformation can be shown
1⎤ ⎡ X dr ⎤ − sin (θ ) ⎡ X a ⎤ ⎡ cos(θ ) ⎢ X ⎥ = ⎢ cos(θ − 120°) − sin (θ − 120°) 1⎥ ⋅ ⎢ X ⎥ ⎥ ⎢ qr ⎥ ⎢ b⎥ ⎢ ⎢ X c ⎥ ⎢cos(θ − 240°) − sin (θ − 240°) 1⎥ ⎢ X o ⎥ ⎦ ⎦ ⎣ ⎣ ⎦ ⎣
(A12)
157 As it can be inferred from previous expression, Tdqo ≠ Tdqo
dqo
[ ] [ ]
t
−1
, since the matrix
[T ] is not unitary. Table A1 summarizes all the transformations that used in our study.
Table A1. Mathematical transformations summary Independent variables Matrix Transformations Xa , Xb , Xc 1 1 ⎤ ⎡ ⎢1 − 2 − 2 ⎥ ⎡ X ds ⎤ ⎢ ⎥ ⎡X a ⎤ 3 3⎥ ⎢ ⎥ ⎢X ⎥ = 2 ⎢0 − ⋅ Xb ⎢ qs ⎥ 3 ⎢ 2 2 ⎥ ⎢ ⎥ ⎢ Xo ⎥ ⎢1 1 1 ⎥ ⎢Xc ⎥ ⎣ ⎦ ⎣ ⎦ ⎢2 2 ⎥ 2 ⎦ ⎣ X ds , X qs , X o
⎡ X dr ⎤ ⎡ cos(θ ) sin (θ ) 0⎤ ⎡ X ds ⎤ ⎢ X ⎥ = ⎢− sin (θ ) cos(θ ) 0⎥ ⋅ ⎢ X ⎥ ⎥ ⎢ qs ⎥ ⎢ qr ⎥ ⎢ ⎢ Xo ⎥ ⎢ 0 0 1⎥ ⎢ X o ⎥ ⎦ ⎦ ⎣ ⎦ ⎣ ⎣
2 2 X = X ds + X qs
X ds , X qs
θ = arctan⎜ ⎜
X dr , X qr , X o
⎛ X qs ⎞ ⎟ X ds ⎟ ⎝ ⎠
⎡ X dr ⎤ ⎢X ⎥ = ⎢ qr ⎥ ⎢ Xo ⎥ ⎣ ⎦
⎡ cos(θ ) cos(θ − 120°) cos(θ − 240°) ⎤ ⎡ X a ⎤ ⎥ ⎢ ⎥ 2⎢ ⎢− sin(θ ) − sin(θ − 120°) − sin(θ − 240°)⎥ ⋅ ⎢ X b ⎥ 3⎢ 1 ⎥ ⎢X ⎥ 1 1 2 2 2 ⎣ ⎦ ⎣ c⎦
APPENDIX B MATLAB CODES
Power Limiter 1
The Matlab code for the control algorithm of the high pass filters is listed below along with comments, signified by the % sign %%%%%%%%%% Inverter size %%%%%%%%%%%%%% load data.txt % load wind power files Pwind=data; % input data in MW Ts=1; % Sampling time Erangen =10; % Energy storage positive limit 1e9 =Unlimited Erangep =10; % Energy storage negative limit 1e9 =Unlimited INVL=2; %Inverter power limit  1e9= Unlimited wc=2*pi*0.05; % cutoff frequency %%%%%%%%% Initialization%%%%%%%%%%%%%%%%% nt=length(Pwind); Kc=(0.006427/tolerance); % ESS charge/discharge constant P0=Pwind(1,1); IOUTF=0; IINVRF=0; Pcomp=0; Pcomp_buffer=zeros(1,nt); Pwind_old=P0; Plosses=0.0; %%%%%%%%%% Physical system description %%%%%% Putility=zeros(1,nt); Energy=zeros(1,nt); Inverter=zeros(1,nt); Vstorage=zeros(1,nt); Pinverter=zeros(1,nt); RRcounter=zeros(1,nt); Icounter=zeros(1,nt); OUT_OF_ENERGY=zeros(1,nt); FULL_POWER=zeros(1,nt); %%%%%%%% System model %%%%%%%%%%%%%%%%%% for i=1:nt %%%%%%%%%%%%% Electrical system%%%%%%%%%% if i==1 Energy(i)=0; 158
159 else Energy(i)=Energy(i1)(Inverter(i1)+Plosses)*Ts; end %%%%%%%%%%% HP filter %%%%%%%%%%%%%%%%% Pcomp=(1/(1+Ts*wc))*(Pwind(i)Pwind_old+Pcomp); Pcomp_buffer(i)=Pcomp; Pwind_old=Pwind(i); IINVRF=Pcomp; IOUTF=IINVRF; %%%%%%% Max Power Saturation%%%%%%%%%%%%%%% if IINVRF > INVL IOUTF=INVL; FULL_POWER(i)=1; elseif IINVRF < INVL IOUTF=INVL; FULL_POWER(i)=1; else IOUTF=IINVRF; end %%%%%%%% Stop inverter due to E>Elimit%%%%%%%%%%% if Energy(i)IOUTF*Ts<Erangen IOUTF=(Energy(i)(sign(IOUTF)*Erangen))/Ts; OUT_OF_ENERGY(i+1)=1*sign(IOUTF); Pcomp=0; end if Energy(i)IOUTF*Ts>Erangep IOUTF=(Energy(i)(sign(IOUTF)*Erangep))/Ts; OUT_OF_ENERGY(i+1)=1*sign(IOUTF); Pcomp=0; end if IOUTF > INVL IOUTF=INVL; FULL_POWER(i)=1; elseif IOUTF < INVL IOUTF=INVL; FULL_POWER(i)=1; end %%%%%%%% Update Electrical system %%%%%%% Inverter(i)= IOUTF+Kc*(Energy(i)0); Pinverter(i)=IOUTF; Putility(i)=Pwind(i)+Inverter(i); Vstorage(i)=Kc*(Energy(i)0); end
160
Power Limiter 2
The Matlab code for the control algorithm of the power limiter 2 is listed below along with comments, signified by the % sign %%%%%%%%%%%%%% Limits Inverter size %%%%%%%%%% Ts=2 % Sampling time R=2.0 % Ramp Rate limit 2MW/min (2 sec scan) A=0.3 %Average limit; 0.3MW/min (2 sec scan) II=1.0 %Instantaneous limit 1MW/2 sec; Erange = 1e9 % Energy storage range (MJ) 1e9 =Unlimited INVL=1e9 %Inverter power limit (MW)  1e9= Unlimited %%%%%%%%%%%%%% Data Input%%%%%%%%%%%%%% %load data.txt; ( units MW) Pwind=data; %%%%%%%%%%%%%%% Initialization%%%%%%%%%%%% nt=length(Pwind); N=60/Ts; %samples per minute Kc=1/300; % ESS charge/discharge constant P0=Pwind(1,1); %%%%%%%%%%%%%%%%%% Indexes %%%%%%%%%%% J=N+1; M=0; %%%%%%%%%%%%%% Physical system description %%%%%% Putility=zeros(1,nt); Energy=zeros(1,nt); Inverter=zeros(1,nt); RRcounter=zeros(1,nt); Acounter=zeros(1,nt); Icounter=zeros(1,nt); OUT_OF_ENERGY=zeros(1,nt); FULL_POWER=zeros(1,nt); %%%%%%%%%%%%%%%% Buffers %%%%%%%%%%%%%% IOPF=P0*ones(1,N);% 2 sec scan buffer initialization IAF=zeros(1,N); % Average buffer initialization Average=0; IOUTF=0; ISWF=0; IOWSF=0; IOWF=0; ICPAF=0; IESARF=0; INDPF=0; IAWSF=0; IAWF=0;
161 IINVRF=0; INWS=0; INW=0; %%%%%%%%%%%%%%% System model %%%%%%%%%%%% for i=1:nt %%%%%%%%%%%%% Electrical system %%%%%%%%%%% if i==1 Energy(i)=0; else Energy(i)=Energy(i1)Inverter(i1)*Ts; end INWS=Kc*(Energy(i)0)+Pwind(i); INW=Pwind(i); %%%%%%%%%%%%% Control loop %%%%%%%%%%%%%% J=J1; %%% 1 minute ago index if J<1 J=N; end M=J+1; %%%% 2 seconds ago index if M>N M=1; end %%%%%%%%%%%%% Top Limiter %%%%%%%%%%%%%%% IOWSF=INWS; %%% Ramp Rate if IOWSFIOPF(J) > R IOWSF= IOPF(J)+R; RRcounter(i)=1; elseif IOWSFIOPF(J) < R IOWSF=IOPF(J)R; RRcounter(i)=1; end %%% Average IAWSF=Average+(abs(IOPF(M)IOWSF)IAF(J))/N; if IAWSF > A if IOPF(M)> IOWSF IOWSF=IOPF(M)abs((AAverage)*N+IAF(J)); Acounter(i)=1; end if IOPF(M) < IOWSF IOWSF=IOPF(M)+abs((AAverage)*N+IAF(J)); Acounter(i)=1; end end %%% Instantaneous if IOWSFIOPF(M)> II
162 IOWSF=IOPF(M)+II; Icounter(i)=1; elseif IOWSFIOPF(M)<  II IOWSF=IOPF(M)II; Icounter(i)=1; end %%%%%%%%%%%%% Bottom Limiter %%%%%%%%%%%% IOWF=INW; %%% Ramp Rate if IOWFIOPF(J) > R IOWF= IOPF(J)+R; RRcounter(i)=1; elseif IOWFIOPF(J) < R IOWF=IOPF(J)R; RRcounter(i)=1; end %%% Average IAWF=Average+(abs(IOPF(M)IOWF)IAF(J))/N; if IAWF > A if IOPF(M)> IOWF IOWF=IOPF(M)abs((AAverage)*N+IAF(J)); Acounter(i)=1; end if IOPF(M) < IOWF IOWF=IOPF(M)+abs((AAverage)*N+IAF(J)); Acounter(i)=1; end end %%% Instantaneous if IOWFIOPF(M)> II IOWF=IOPF(M)+II; Icounter(i)=1; elseif IOWFIOPF(M)<  II IOWF=IOPF(M)II; Icounter(i)=1; end %%%%%%%%%%%%%% Inverter Power %%%%%%%%%%%%% ICPAF=IOWSFIOWF; IESARF=IOWF+INW; IINVRF=ICPAFIESARF; %%%%%%%%%%%%%%% Max Power Saturation%%%%%%%%% if IINVRF > INVL IOUTF=INVL; FULL_POWER(i)=1; elseif IINVRF < INVL IOUTF=INVL;
163 FULL_POWER(i)=1; else IOUTF=IINVRF; end %%%%%%%%%%%% Stop inverter due to E>Elimit%%%%%%%% if abs(Energy(i)IOUTF*Ts)>Erange/2 IOUTF=(Energy(i)(sign(IOUTF)*Erange/2))/Ts; OUT_OF_ENERGY(i+1)=1*sign(IOUTF); if IOUTF > INVL IOUTF=INVL; FULL_POWER(i)=1; elseif IOUTF < INVL IOUTF=INVL; FULL_POWER(i)=1; end end %%%%%%%%%% Update buffer data %%%%%%%%%%%%%% INDPF=IINVRFIOUTF; Average=Average+(abs(IOPF(M)(IOWSFINDPF))IAF(J))/N; IAF(J)=abs(IOPF(M)(IOWSFINDPF)); IOPF(J)=IOWSFINDPF; %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%% Electrical system %%%%%%%%%%% Inverter(i)= IOUTF; Putility(i)=Pwind(i)+Inverter(i); end Power Limiter 3 The Matlab code for the control algorithm of the power limiter 3 is listed below along with comments, signified by the % sign %%%%%%%%%%%% Limits Inverter size %%%%%%%% Ts=2 % Sampling time R=2.0 % Ramp Rate limit 2MW/min (2 sec scan) A=0.3 %Average limit; 0.3MW/min (2 sec scan) II=1.0 %Instantaneous limit 1MW/2 sec; Erange = 1e9 % Energy storage range (MJ) 1e9 =Unlimited INVL=1e9 %Inverter power limit  1e9= Unlimited %%%%%%%%%%%%%% Data Input%%%%%%%%% load data.txt; % Data scaled to 10 MW( units MW) Pwind=data; %%%%%%%%%%%%%%% Initialization%%%%%%%%%% nt=length(Pwind); N=60/Ts; %samples per minute Kc=1/300; % ESS charge/discharge constant
164 P0=Pwind(1,1); J=N+1; M=0; %%%%%%%%%%% Physical system description %%%%%% Putility=zeros(1,nt); Energy=zeros(1,nt); Centering=zeros(1,nt); Inverter=zeros(1,nt); Pold=P0*ones(1,N); Avg=zeros(1,N); Abuffer=zeros(1,N); Average=0; ESArp=zeros(1,nt); ESArn=zeros(1,nt); ESAr=zeros(1,nt); UR=zeros(1,nt); LR=zeros(1,nt); UA=zeros(1,nt); LA=zeros(1,nt); UI=zeros(1,nt); LI=zeros(1,nt); UT=zeros(1,nt); LT=zeros(1,nt); UW=zeros(1,nt); LW=zeros(1,nt); UC=zeros(1,nt); LC=zeros(1,nt); I_counter=zeros(1,nt); RR_counter=zeros(1,nt); A_counter=zeros(1,nt); OUT_OF_ENERGY=zeros(1,nt); FULL_POWER=zeros(1,nt); for i=1:nt %%%%%%%%%%%%% Electrical system %%%%% if i==1 Energy(i)=0; else Energy(i)=Energy(i1)Inverter(i1)*Ts; end %%%%%%%%%%%%% Control loop %%%%%%%%%% J=J1; %%% 1 minute ago index if J<1 J=N; end M=J+1; %%%% 2 seconds ago index if M>N
165 M=1; end %%%%% Ramp Rate1%%%%%% UR(i)=Pold(J)+R; LR(i)=Pold(J)R; %%%%% Subminute1%%%%%% UA(i)=Pold(M)+(abs(AAverage)*N+Avg(J)); LA(i)=Pold(M)(abs(AAverage)*N+Avg(J)); %%%%% Instantaneous 1%%%%%% UI(i)=Pold(M)+II; LI(i)=Pold(M)II; %%%%%%%%% Internal variables UT(i)=min([UR(i) UA(i) UI(i)]); LT(i)=max([LR(i) LA(i) LI(i)]); UW(i)=Pwind(i)UT(i); LW(i)=Pwind(i)LT(i); if UW(i)>0 UC(i)=UW(i); else UC(i)=0.0; end if LW(i)<0 LC(i)=LW(i); else LC(i)=0.0; end if UW(i)>0 ESArp(i)=UW(i); if UT(i)==UR(i) RR_counter(i)=1; I_counter(i)=0; A_counter(i)=0; elseif UT(i)==UI(i) I_counter(i)=1; A_counter(i)=0; RR_counter(i)=0; else A_counter(i)=1; I_counter(i)=0; RR_counter(i)=0; end else ESArp(i)=0.0; end if LW(i)<0 ESArn(i)=LW(i);
166 if LT(i)==LR(i) RR_counter(i)=1; I_counter(i)=0; A_counter(i)=0; elseif LT(i)==LI(i) I_counter(i)=1; A_counter(i)=0; RR_counter(i)=0; else A_counter(i)=1; I_counter(i)=0; RR_counter(i)=0; end else ESArn(i)=0.0; end ESAr(i)=ESArp(i)+ESArn(i); Centering(i)=Kc*Energy(i); if Centering(i)>UC(i) Centering(i)=UC(i); end if Centering(i)<LC(i) Centering(i)=LC(i); end Inverter(i)=Centering(i)ESAr(i); %%%%%%%%%%%%%%% Max Power Saturation%%% if Inverter(i) > INVL Inverter(i)=INVL; FULL_POWER(i)=1; elseif Inverter(i) < INVL Inverter(i)=INVL; FULL_POWER(i)=1; end %%%%%%%%%%%% Stop inverter due to E>Elimit%%%% if abs(Energy(i)Inverter(i)*Ts)>Erange/2 Inverter(i)=(Energy(i)(sign(Inverter(i))*Erange/2))/Ts; OUT_OF_ENERGY(i+1)=1*sign(Inverter(i)); if Inverter(i) > INVL Inverter(i)=INVL; FULL_POWER(i)=1; elseif Inverter(i) < INVL Inverter(i)=INVL; FULL_POWER(i)=1; end end Putility(i)=Pwind(i)+Inverter(i);
167 %%%%% Update buffer%%% Average=Average+(abs(Pold(M)Putility(i))Avg(J))/N; Abuffer(i)=Average; Avg(J)=abs(Pold(M)Putility(i)); Pold(J)=Putility(i); end
APPENDIX C POWER STABILIZER CONTROL MODULES The following table is a summary of the main functions used in the programming of the power stabilizer. Table C1. Control Modules File Name C code PLL.h typedef struct { _iq ds; /* Input: Vds */ _iq qs; /* Input: Vqs */ _iq e_pll; /* Variable: Error */ _iq i_pll; /* Variable: Integral output */ _iq p_pll; /*Variable: Proportional output */ _iq pi_pll; /*Variable: PI output */ _iq theta; /* Output: PLL output (theta) */ _iq sin_theta; /* Output: sin(theta)*/ _iq cos_theta; /* Output: cos(theta) */ _iq Kp_pll; /* Parameter: P gain */ _iq Ki_pll; /* Parameter: I gain */ _iq wdt; /* System Frequency */ _iq i_pll_out_max; /* Param: Max Int output */ _iq i_pll_out_min; /* Param: Min Int output */ _iq pi_pll_out_max; /* Param: Max PI output */ _iq pi_pll_out_min; /* Param: Min PI output */ _iq deltat; /* Parameter: Time step */ void (*calc)(); /* Pointer to calc func */ } PLL; typedef PLL *PLL_handle; void PLL_calc(PLL_handle); #include "IQmathLib.h" /* Include header for IQmath */ #include "pll.h" void PLL_calc(PLL *v) { v>e_pll =_IQmpy(_IQcos(v>theta),v>qs)_IQmpy(_IQsin(v>theta),v>ds); v>i_pll = v>i_pll+_IQmpy(v>Ki_pll,v>e_pll); v>i_pll = _IQsat(v>i_pll,v>i_pll_out_max,v>i_pll_out_min); v>p_pll = _IQmpy(v>e_pll,v>Kp_pll); 168
PLL.c
169 Table C1. Continued File Name C code PLL.c v>pi_pll= v>p_pll+v>i_pll; v>pi_pll= _IQsat(v>pi_pll,v>pi_pll_out_max, v>pi_pll_out_min); v>theta= v>theta+_IQmpy(v>deltat,v>pi_pll)+v>wdt; if (v>theta>=_IQ(3.141592654)) v>theta=v>theta_IQ(2*3.141592654); v>sin_theta = _IQsin(v>theta); v>cos_theta = _IQcos(v>theta); } CLARKE.h typedef struct { _iq as; /* Input: phasea variable */ _iq bs; /* Input: phaseb variable */ _iq cs; /* Input: phasec variable */ _iq ds; /* Output: stationary daxis variable*/ _iq qs;/* Output: stationary qaxis variable*/ _iq os;/* Output: stationary oaxis variable*/ void (*calc)(); /* Pointer to calc func */ } CLARKE; #include "IQmathLib.h" /* Include header for IQmath */ #include "clarke.h" /* 1/sqrt(3) = 0.57735026918963 */ void clarke_calc(CLARKE *v) { v>ds =_IQmpy(_IQ(0.666666666),v>as)+_IQmpy(_IQ(0.3333333),(v>bs+v>cs)); v>qs =_IQmpy(_IQ(0.577350269),(v>bsv>cs)); v>os =_IQmpy(_IQ(0.333333333),(v>as+v>bs+v>cs)); } typedef struct { _iq ds; /* Input: stationary daxis */ _iq qs; /* Input: stationary qaxis */ _iq sin_theta; /* Input: cos(theta) */ _iq cos_theta; /* Input: sin(theta) */ _iq dr; /* Output: rotating daxis*/ _iq qr; /* Output: rotating qaxis*/ void (*calc)(); /* Pointer to calc function */ } PARK; typedef PARK *PARK_handle; void park_calc(PARK_handle);
CLARKE.c
PARK.h
170 Table C1. Continued File Name C code PARK.c #include "IQmathLib.h" /* Include header for IQmath*/ #include "park.h" void park_calc(PARK *v) { v>dr = _IQmpy(v>ds,v>cos_theta) + _IQmpy(v>qs,v>sin_theta); v>qr = _IQmpy(v>qs,v>cos_theta)  _IQmpy(v>ds,v>sin_theta); } typedef struct { _iq ds; /* Input: ds variable */ _iq qs; /* Input: qs variable */ _iq as; /* Output: stationary aaxis */ _iq bs; /* Output: stationary baxis */ _iq cs; /* Output: stationary caxis */ void (*calc)(); /* Pointer to calc function */ } ICLARKE; typedef ICLARKE *ICLARKE_handle; void iclarke_calc(ICLARKE_handle); #include "IQmathLib.h" /* Include header for IQmath */ #include "iclarke.h" void iclarke_calc(ICLARKE *v) { v>as = v>ds; v>bs = _IQmpy(_IQ(0.5), v>ds) + _IQmpy(_IQ(0.8660254038),v>qs) ; v>cs = _IQmpy(_IQ(0.5), v>ds) + _IQmpy(_IQ(0.8660254038),v>qs); } IPARK.h typedef struct { _iq ds; /* Output: stationary daxis */ _iq qs; /* Output: stationary qaxis */ _iq sin_theta; /* Input: cos(theta) */ _iq cos_theta; /* Input: sin(theta) */ _iq dr;/* Input: rotating daxis*/ _iq qr;/* Input: rotating qaxis*/ void (*calc)();/* Pointer to calc function */ } IPARK; typedef IPARK *IPARK_handle;
ICLARKE.h
ICLARKE.c
171 Table C1. Continued File Name C code IPARK.c #include "IQmathLib.h" /* Include header for IQmath*/ #include "ipark.h" void ipark_calc(IPARK *v) { v>ds = _IQmpy(v>dr,v>cos_theta)  _IQmpy(v>qr,v>sin_theta); v>qs = _IQmpy(v>qr,v>cos_theta) + _IQmpy(v>dr,v>sin_theta); }
PIANTIWINDUP.h typedef struct { _iq feedback; /* Input: Feedback signal */ _iq e_pi; /* Variable: Error */ _iq i_pi; /* Variable: Integral output*/ _iq p_pi; /* Variable: Proportional output */ _iq pi_pi; /* Variable: PI output */ _iq out; /* Output: PI control action */ _iq ref; /* Parameter: Reference signal */ _iq Kp_pi; /* Parameter: Proportional gain */ _iq Ki_pi; /* Parameter: Integral gain */ _iq i_pi_out_max; /* Parameter: Max Int */ _iq i_pi_out_min; /* Parameter: Min Int */ _iq pi_pi_out_max; /* Parameter: Max PI */ _iq pi_pi_out_min; /* Parameter: Min PI */ void (*calc)(); /* Pointer to calc function */ } PIANTIWINDUP; PIANTIWINDUP.c #include "IQmathLib.h" /* Include header for IQmath*/ #include "PIantiwindup.h" void PIantiwindup_calc(PIANTIWINDUP *v) { v>e_pi = v>refv>feedback; v>i_pi = _IQsat(v>i_pi+_IQmpy(v>Ki_pi,v>e_pi), v>i_pi_out_max,v>i_pi_out_min); v>p_pi = _IQmpy(v>e_pi,v>Kp_pi); v>pi_pi=v>p_pi+v>i_pi; v>out=_IQsat(v>pi_pi,v>pi_pi_out_max,v>pi_pi_out_min); }
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BIOGRAPHICAL SKETCH Alejandro Montenegro obtained his BS degree in Electronic Engineering from the Polytechnic University of Valencia (UPV) in 1995 and his MS in Industrial Engineering from UPV in 2000. He has been a research assistant at the Department of Electrical Engineering (UPV) and is currently a research assistant and a Ph.D. candidate at the University of Florida in the Department of Electrical and Computer Engineering. His field of interest is reliability and power quality of distribution networks using power electronic devices.
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