Ed Dissertation

SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
by
Edward Flanigan
M.S. in Electrical Engineering, Southern Illinois University, 2005
B.S. in Electrical Engineering, Southern Illinois University, 2003
A Dissertation
Submitted in Partial Fulfillment of the Requirements for the
Doctor of Philosophy Degree in Electrical and Computer Engineering
Department of Electrical and Computer Engineering

in the Graduate School
Southern Illinois University Carbondale
May 2, 2009
DISSERTATION APPROVAL
SCALABLE TEST GENERATION FOR PATH DELAY FAULTS
By
EDWARD FLANIGAN
A Dissertation Submitted in Partial
Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in Electrical and Computer Engineering
Approved by:
Dr. Spyros Tragoudas, Chair
Dr. Dimitri Kagaris
Dr. Ning Weng
Dr. Mohammad Seyeh
Dr. Manoj Mohanty
Graduate School
Southern Illinois University Carbondale
May 2, 2009
AN ABSTRACT OF THE DISSERTATION OF
EDWARD FLANIGAN, for the Doctor of Philosophy degree in ELECTRICAL
AND COMPUTER ENGINEERING, presented on 05/02/2009, at Southern Illinois
University Carbondale.
TITLE: Scalable Test Generation for Path Delay Faults
MAJOR PROFESSOR: Dr. Spyros Tragoudas
Modern day IC design has drawn a lot of attention towards the path delay fault
model (PDF) [1], which targets delay defects that affect the timing characteristics
of a circuit. Due to the exponential number of paths in modern circuits a subset
of critical paths are chosen for testing purposes [2]. Path intensive circuits contain
a large number of critical paths whose delays affect the performance of the circuit.
This dissertation presents three techniques to improve test generation for path delay
faults. The first technique presented in this dissertation avoids testing unnecessary
paths by using arithmetic operations. This second technique shows how to compact
many faults into a single test application, thus saving valuable test application time.
The third technique demonstrates how to generate tests under modern day scan
architectures. Experimental results demonstrate the effectiveness of the proposed
techniques.
ii
Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
1 Problem Studied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Identification of Delay Measurable PDFs Using Linear Dependency Rela-
tionships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Previous Work and Rationale . . . . . . . . . . . . . . . . . . . . . 6
2.3 Measurable Path Identification . . . . . . . . . . . . . . . . . . . . 8
2.3.1 Off Input Path Selection . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Advanced Measurement Procedures . . . . . . . . . . . . . . . . . . 18
2.4.1 Off-Input Sub-Path Sensitization . . . . . . . . . . . . . . . 18
2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Function-based ATPG for Path Delay Faults using the Launch-Off-Capture
Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Path Implicit Framework and Rationale . . . . . . . . . . . . . . . . 31
3.3 Launch-off-Capture Test Generation . . . . . . . . . . . . . . . . . . 34
iii
3.3.1 Required Functions . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.2 LOC ATPG Procedure . . . . . . . . . . . . . . . . . . . . . 36
3.3.3 Details on Computing the Partitioned Image Method . . . . 39
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Compact Test Pattern Generation for Path Delay Faults using Implicit Path
Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 Function-Based Compaction . . . . . . . . . . . . . . . . . . . . . . 47
4.3 Zdd-Based Path Selection . . . . . . . . . . . . . . . . . . . . . . . 55
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5 Concluding remarks for the dissertation . . . . . . . . . . . . . . . . . . . 66
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
iv
LIST OF TABLES
2.1 Basis Sizes by Different Methods . . . . . . . . . . . . . . . . . . . . . 22
2.2 Testable Basis Coverage of Critical Paths . . . . . . . . . . . . . . . . 23
2.3 Number of Identified DM-PDFs . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Robust PDF Testability for LOC . . . . . . . . . . . . . . . . . . . . . 41
4.1 Compaction of Robust PDFs in the ISCAS’89 Benchmarks . . . . . . . 58
4.2 Compaction of Non-Robust PDFs ISCAS’89 . . . . . . . . . . . . . . . 61
4.3 Compaction of Robust PDFs ISCAS’85 . . . . . . . . . . . . . . . . . . 62
4.4 Compaction of Non-Robust PDFs ISCAS’85 . . . . . . . . . . . . . . . 62
4.5 Comparison of Robust PDF Compaction with [3]: ISCAS’89 . . . . . . 63
4.6 Comparison of Non-Robust PDF Compaction with [3]: ISCAS’89 . . . 64
4.7 Comparison of Robust PDF Compaction with [3]: ISCAS’85 . . . . . . 64
4.8 Comparison of Non-Robust PDF Compaction with [3]: ISCAS’85 . . . 65
v
LIST OF FIGURES
2.1 Validation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Strong Robust PDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Delay Measurable PDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Validated Off-Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 LOC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 LOC Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 s27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 Compaction of a set of PDFs . . . . . . . . . . . . . . . . . . . . . . . 54
vi
Chapter 1
PROBLEM STUDIED
Modern circuits contain an exponential number of path delay faults (PDFs).
Path delay fault testing requires the application of a vector pair (V1, V2 ) to sensitize
and propagate the PDF throughout the selected path. The application of the two
vector sequence depends on the scan architecture of the design. The two most
popular scan architectures used in the industry are enhanced-scan, and launch-off-
capture (LOC). In the enhanced-scan architecture [4] any vector pair that sensitizes
and propagates the PDF can be applied to the circuit under test. The scan flip-flops
used in this architecture have the ability to store two test patterns instead of one.
This allows the scan and application of any two-vector test without imposing any
scan architecture constraints. The hardware overhead associated with scan flip-flops
prevents the use of the enhanced-scan architecture in industrial applications. LOC
[5, 6] overcomes the limitations of enhanced scan architecture and has thus been
widely adopted in industrial applications. Under the LOC scan architecture the
second vector V2 is the functional response of the first vector.
This dissertation presents test pattern generation techniques that can be ap-
plied to large circuit designs that have an enormous number of paths. Such designs
are very difficult to test and results show the techniques presented in this disserta-
tion improve over existing work. The techniques presented in this dissertation are
applicable to both the traditional enhanced-scan architecture as well as launch-of-
1
capture scan architecture. All of the approaches in this dissertation use functions,
therefore they can all be easily integrated and used together.
A large number of path delay faults are critical [7] and affect the timing char-
acteristics of the circuit, however only a small number of critical PDFs can be tested
because of limited automatic test equipment (ATE) test time. To improve the confi-
dence in circuit timing characterization, this dissertation proposes a technique that
measures a set of basis paths, and then calculates the delay of many other paths
by using the basis set. The launch-off-capture scan architecture has become very
popular in industry because of reduced hardware overhead and increased operating
frequencies. This dissertation proposes a function-based test generation technique
under the LOC scan architecture that identifies and generates tests for all testable
paths. There is a very large number of paths in modern circuits, so many techniques
have tried to increase the number of paths tested with a single test by compacting
test sets. There are several test set compaction techniques that try to increase the
number of tested PDFs without increasing test application time. This dissertation
proposes a compaction technique that outperforms all other compaction techniques
in existing literature.
This dissertation is organized as follows. Chapter 2 presents a path-based
procedure that identifies measurable PDFs by considering the bounded delay model.
Chapter 3 presents a novel function-based test generation technique for path delay
faults (PDFs) under the launch-off-capture (LOC) scan architecture. The function
based technique avoids strenuous backtracking procedures required by traditional
2
techniques. Chapter 4 describes the basic function based compaction approach as
well as an enhancement in test compaction that applies implicit path storage and
selection to guide an automatic test pattern generation (ATPG) tool for compaction.
Chapter 5 concludes this dissertation.
3
Chapter 2
IDENTIFICATION OF DELAY MEASURABLE PDFS USING
LINEAR DEPENDENCY RELATIONSHIPS
2.1 INTRODUCTION
Modern day IC design has drawn a lot of attention towards the path delay fault
model (PDF) [1], which targets delay defects that affect the timing characteristics
of a circuit. Due to the exponential number of paths in modern circuits a subset
of critical paths are chosen for testing purposes [2]. Path intensive circuits contain
a large number of critical paths whose delays affect the performance of the circuit.
The number of critical paths may be too large to test all of them on the Automatic
Test Equipment (ATE).
The work presented in [8, 9] shows how to determine an upper bound on
circuit delay using a small set of basis paths, however the approach is limited by
the number of paths that can be measured. In previous work, strong robustly
sensitizable PDFs are considered measureable, and the testable basis sets ST B formed
by those measurable paths can be small.
This work identifies additional PDFs whose delays can be measured. Such
PDFs are referred to as delay measurable PDFs (DM-PDFs). The DM-PDFs are
used to increase the cardinality of ST B . Increasing the size of the testable basis
set increases the number of PDFs which are linearly dependent on that basis set
and produces a large number of PDFs whose circuit timing characteristics can be
4
determined by considering the enhanced set of DM-PDFs. The circuit timing charac-
teristics of these paths could not be determined by strictly using the strong robustly
testable path set.
It is shown that the proposed work allows basis sets to extend beyond the
limitations of the traditional strong robustly testable basis set while maintaining
the same level of accuracy when determining circuit timing characteristics. Results
show that the presented work produces a significant increase in the number of iden-
tifiable DM-PDFs. All DM-PDFs identified beyond the strong robustly testable set
can be directly applied to obtain improvements when determining circuit timing
characteristics using linear dependency relationships. Improvements such as max-
imizing the size of the testable basis set allows one hundred percent coverage of
all circuit paths. Techniques presented in this chapter often produce one hundred
percent coverage of all paths and always result in high coverage of critical paths
which was not obtainable using previous techniques [8].
The rest of the chapter is organized as follows. Section 2.2 presents necessary
background and previous work. Sections 2.3 and 2.4 present a path-based procedure
that identifies DM-PDFs by considering the bounded delay model. Experimental
results in Section 2.5 demonstrate that the use of DM-PDFs increases the number of
critical paths for which circuit timing characterization can be determined. Section
2.6 concludes the chapter .
5
2.2 PREVIOUS WORK AND RATIONALE
The delay of every PDF in a circuit can be expressed as a linear combination
of a subset of basis paths [8, 9]. The basis path set is the smallest set such that every
PDF can be represented as a linear combination of that set and has been shown to
be linear with respect to the size of the circuit [8]. The basis set contains PDFs that
are all linearly independent and ideally testable. The testable basis set ST B consists
only of the testable PDFs within a basis set whose delays are measurable. The work
in [8] insists on using strong robustly testable PDFs to create the basis set. The
circuit timing characteristics are determined by using a basis set of strong robustly
testable PDFs to calculate the delay of all PDFs which are linearly dependent on
that strong robustly testable basis set. It is desirable to find the largest possible
testable basis set to maximize the number of PDFs whose delays can be calculated
thus eliminating the need to test those PDFs on the ATE.
Strong robustly testable PDFs [10, 11] guarantee the delay measurement for
the path taken on the automatic test equipment (ATE) is the delay of the on input
transition of the path for which test generation was performed. Unlike strong ro-
bustly testable PDFs, delays measured for robust and non-robustly testable PDFs
[12, 13] could unintentionally be the delay of an off input transition because of mask-
ing. A precise delay measurement is obtained by using a binary search with the clock
frequency [8]. A strong robustly testable path requires stable non-controlling values
(SNCV) on all off inputs of the path [10]. The number of strong robustly testable
PDFs is usually limited in size due to the stringent path sensitization criteria. Hence
6
there still remains a significant percentage of PDFs whose timing characteristics
cannot be determined because they are not linearly dependent on the small strong
robustly testable basis set.
To improve circuit timing characterization we propose a methodology to ef-
fectively identify additional PDFs whose delays can be measured. These delay mea-
sureable PDFs (DM-PDFs) exhibit the same important characteristic as a strong
robustly testable PDFs; the delay measurement taken at the output is guaranteed
to be the delay of the path for which test generation was performed. Unlike strong
robustly testable paths, the sensitization criteria for a DM-PDF allows transitions
along the off inputs of the path. However, the off input transitions are restricted to
transitions that guarantee the on-input transition delay propagates to the output of
a gate. Such off input transitions are achieved by sensitizing all off input subpaths
(paths leading into an off input) with the same criteria as PDFs with measurable
delays, such as strong robust PDFs. It is shown that the measurable delay of off in-
put transitions as well as the bounded delay model allow for the delay measurement
of the path under test (on input transition).
In the presented work the bounded delay model [14] is used to overcome defi-
ciencies of the path delay fault model including input pattern sensitivity, coupling
effects, as well as interdie and intradie process variations. Bounded gate delays are
used to address process variation by specifying minimum and maximum delay values
for gates, wires, and interconnects. The bounded delay model also considers noise
related defects such as crosstalk, simultaneous switching and power supply noise. All
7
combinations of delay and process variation are modeled within the minimum and
maximum range of the bounded delay model. Under this model it is assumed that
any delay which appears outside of the bounded delay range are considered gross
delay defects and will be identified by transition delay fault testing. Statistical delay
models [15] using mean and sigma parameters can be used to accurately model pro-
cess variation, crosstalk, and other deep submicron related issues. Bounded delay
values at each gate can be modified to reflect a statistical model to improve the
effectiveness of the proposed approach.
2.3 MEASURABLE PATH IDENTIFICATION
Strong robustly testable paths have a unique property where the delay mea-
sured at the primary output is the delay value of the on input transition for the
tested path. Strong robust PDFs are the most basic type of DM-PDFs because all
off inputs take stable non-controlling values. This section identifies DM-PDFs which
allow off input transitions that do not affect the on-input delay measurement taken
at the primary output. The procedures for identifying such paths place sensitization
restrictions on subpaths leading into off inputs.
All transitions at a gate must be of the same type either rising or falling, and
the transition that appears at the output of a gate must be the on-input transition
for DM-PDF. Two types of PDF sensitization follow that description. Robust sensi-
tization occurs when all transitions at a gate are from CV to NCV. The second type
of sensitization is functional sensitization when all transitions at a gate are from
NCV to CV. Under the bounded delay model there are two conditions which allow
8
for off-input sensitization of a DM-PDFs at a gate.
Condition 1. (Robust DM-PDF Sensitization): The on input is robustly sen-
sitized and the maximum delay of each off input is less than the minimum delay of
the on input. The on input transitioning to non-controlling value occurs later than
all off input transitions.
The on input transition is propagated to the gate output as demonstrated in
Figure 2.1a.
Condition 2. (Functional DM-PDF Sensitization): The on input is func-
tionally sensitized and the maximum delay of the on input is less than the minimum
delay of each off input. The on input transitioning to controlling value occurs before
all off input transitions.
The on input transition is propagated to the gate output as demonstrated in
Figure 2.1b.
In both conditions the delay of the on-input transition is observed at the out-
put of the gate.
(a) Robust Validation (b) Functional Validation

min(on) > max(off) max(on) < min(off)
min max min max min max min max min max min max
off off on on on on on on off off on on
on on
off off
Figure 2.1. Validation Conditions
9
Figures 2.2 and 2.3 show the s27 circuit from the ISCAS’89 benchmark col-
lection. Assume the bounded delay of each gate in the circuit is in the range of 1
and 2 units. This bounded delay value is denoted as (1, 2). Figure 2.2 shows the
strong robustly tested path {1, 8, 17} whose delay can be measured at primary out-
put 17. The measured delay should obey the bounded delay model. It is computed
by adding the bounded delay values of the two gates along the path and is (2, 4). If
the measured delay is greater than 4 a delay defect exists along path {1, 8, 17}. If
the measured delay is less than 2 a manufacturing defect exists along path {1, 8, 17}.
Figure 2.3 shows a PDF {1, 8, 10, 13, 15, 16, 17} that cannot be tested strong
robustly but is a DM-PDF. Applying the test pattern as shown in Figure 2.3, a delay
measurement at primary output 17 could reflect the delay of the falling off-input
transition occurring on node 8 or the falling on-input transition occurring on node
16. This is explained in the following.
Figure 2.3 shows the sensitization and bounded delay values for paths {1, 8, 17}
and {1, 8, 10, 13, 15, 16, 17}. The inputs of the NOR gate driving output 17 has
bounded delay values of (1, 2) (line 8), and (5, 10) (line 16). Transitions on nodes
8 and 16 are from controlling value to non-controlling value, therefore the later of
the two transitions will be measured at output 17. The delay of path {1, 8, 17}
has already been verified by applying a strong robust test for that path. There-
fore the latest transition is (6, 12) because of path {1, 8, 10, 13, 15, 16, 17} has a
bounded delay of (6, 12). Thus the measured delay reflects the delay along path
{1, 8, 10, 13, 15, 16, 17}.
10
1 8 17
0
4
13
6 10 15 16 19
12
1 18
5
2 9
7
11
3
Figure 2.2. Strong Robust PDF
[1,2] [1,2]
1 18
0 17
0 [3,6]
[5,10]
4
13
00
11
6
1 110
0 00
11
15 16 19
[2,4]
1 12 [4,8]
5
0 1
0 18
0
2 1 9
0 1
0
7
11
3
Figure 2.3. Delay Measurable PDF
2.3.1 Off Input Path Selection
Before generating tests for DM-PDFs, the existing set of DM-PDFs is consid-
ered because they can potentially sensitize a sub path leading into an off input of a
target DM-PDF. The set of known delay measurable PDFs is denoted as SDM . The
set initially is the set of strong robustly testable PDFs. A DM-PDF restricts all off
inputs to either a stable non-controlling value or a transition that is sensitized using
one of the PDFs from the pre-existing measurable set SDM . Target paths are a set
of user defined paths that are candidates to be identified as DM-PDFs. The target
11
paths selected for test generation will be determined by problem formulated use of
the DM-PDFs. In the case of forming a testable basis [9], linearly independent paths
should be selected.
The test generation procedure begins by assuming all off inputs of the target
DM-PDF take stable non-controlling values. To guarantee the delay of the on input
transition is measured at the primary output, the delay of the target PDF is calcu-
lated using the bounded delay model. Any measurable PDF within the set SDM that
violates Condition 1 or Condition 2 is removed from consideration for sensitizing an
off input transition. What remains is the set of PDFs which can be sensitized with
delay measurable criteria up to an off input of the target path without affecting the
delay measurement of the target path.
From the remaining set of PDFs in SDM we determine the appropriate set of
PDFs which will be taken into consideration for validating each individual off-input
along the target path. Each individual off input will have a set of paths that can
sensitize the DM-PDF; those paths are stored in an off input set Vof f . The set of
delay measurable PDFs from SDM that meet the timing constraints mentioned in
Condition 1 or Condition 2 are added to the off-input measurable transition set Vof f
only if the path has the same identical sub path as the target path starting from the
output of the off-input gate and ending at the primary output. The identification
of the paths which coincide with the on-input sub-path can be done efficiently using
zero suppressed binary decision diagrams (ZBDDs) [16, 17].
Any off input transition occurring along an off input of a DM-PDF must obey
12
the conditions stated in Definition 1.
Definition 1. For a single off input i of the target path, Vof f (i) i is the set of all
paths which are contained in SDM and obey the following selection criteria:
1. The measured delay of the candidate path taken from SDM must obey either
Condition 1 or Condition 2.
2. The delay measurable sensitization of the off input path must be maintained
up to the point where the off input and the target path converge.
3. The sub path of the candidate Vof f path must follow the same identical sub
path as the target path beginning with the output of the gate for which the
off input connects.
Theorem 2. Any DM-PDF has a measurable delay if all off-inputs along that DM-
PDF are sensitized by any path in the respective Vof f set as defined in Definition 1,
or a stable non-controlling value.
The proof of theorem 2 is presented below with a induction argument on the number
of gates along the DM-PDF. The base case for induction shows the PDF delay is
measurable through the first gate of the DM-PDF.
Proof. Any off-input which has a stable non-controlling value does not affect the
propagating on-input transition. Considering a single two-input gate along a DM-
PDF, the delay measured at the primary output is determined by either the transi-
tion occurring on the on-input or the transition occurring on the off-input. The off
13
input sub path follows the same identical sub path as the on-input path beginning
with the output of the gate for which the off input connects. This means that under
the PDF model, the identical sub path has the same delay for both the on-input
path and the off-input path. Therefore under robust (functional) sensitization the
measured output response is the one which has the latest (fastest) transition among
all transitioning inputs of the gate along the DM-PDF.
The delay of all paths ∈ Vof f (i) are measurable because they are also elements
of SDM . The paths in Vof f have known delay values and they obey the bounded
delay model; if they do not obey the bounded delay model a defect is present in the
circuit. To be elements of Vof f the paths must obey Condition 1 or Condition 2. The
on-input transition is always measurable at the output of a gate because bounded
delay values are satisfied for all off-input transitions, and all off-input transitions
occur before (after) the on-input transition under robust (functional) sensitization.
If a delay is measured and is not within the bounded delay of the on-input path
a defect exists. The argument above holds for any number of off-inputs because
all paths transitioning through those off inputs must be elements of Vof f , and have
measurable delays that obey the bounded delay values.
Assume that the PDF is delay measurable through k gates. The PDF is delay
measurable through k + 1 gates. The arguments made above are applied on gate
k + 1. All off inputs have a measurable delay value. Considering robust(functional)
sensitization, the bounded delay values of all transitioning sub paths leading into
off-inputs of gate k + 1 have a minimum (maximum) delay bound greater (less) than
14
the maximum (minimum) delay bound of the on input path. The delay measured
at the output of gate k + 1 is the delay of the on-input transition unless the delay
lies outside the bounded delay values of the on-input path. A defect exists if the
measured delay is not within the delay bounds of the on-input path, and Theorem
2 has been proven for any number of gates with any number of off inputs.
The formal procedure for finding the set of paths that can be used to sensitize
a transition on the off-inputs of a DM-PDF p is given in Algorithm 1. The identifica-
tion of paths utilizes efficient ZBDD set operations such as union, and intersection.
Procedure Sub path(o, p) finds all paths v such that each path in v is a measurable
path passing through off-input o and follows along same sub-path as the target path
p from o to the primary output.
Algorithm 1 Find off input paths Vof f

1: for all off inputs o along path p do
2: Vof f (o) = (empty path set)

3: v = Subpath(o, p)
4: for all paths t ∈ v do
5: if Condition 1 or Condition 2 then
6: Vof f (o) = Vof f (o) ∪ t
7: end if
8: end for
9: end for
To illustrate the procedure consider the previous example described by Fig-
ures 2.2 and 2.3. Definition 1 states that {1, 8, 17} can be used to gener-
15
ate an off-input transition for PDF {1, 8, 10, 13, 15, 16, 17}. Theorem 2 classifies
{1, 8, 10, 13, 15, 16, 17} as a DM-PDF under the sensitization conditions described
for Figure 2.3. The falling off-input transition on node 8 has a maximum delay of
2 which is less than the minimum on-input transition delay of line 16, which has
a minimum delay of 5. The delay measured at the primary output is the delay of
path {1, 8, 10, 13, 15, 16, 17} which is (6, 12).
2.3.2 Test Generation
Once the off-input sensitization path sets Vof f are determined, function based
automatic test pattern generation [18, 19, 10, 7] is used to determine a delay mea-
surable test for the target PDF. During the test generation phase all off inputs
along the target path are restricted to either a stable non-controlling value [10, 18]
or a off input transition which is sensitized using one of the paths from the existing
measurable path set contained in Vof f . A delay measurable test for a PDF is the
conjunction of the set of off-input functions that either hold the off-input at a stable
non-controlling value or produce a transition that obeys Definition 1. Procedures
to derive off-input stability functions have been presented in [8, 10].
When forming a test function for a delay measurable off-input transition, it is
important that the off-input sub-path taken from Vof f (starting at a primary input
and ending at the off input of the target path) is sensitized using the same measur-
able sensitization criteria for which the delay measurement for that paths was taken.
Any path within Vof f can be sensitized in this manner because all of the paths in
Vof f obey the selection criteria as stated in Definition 1.
16
Algorithm 2 generateTest(i)
1: test = 0
2: for all paths m ∈ Vof f (i) do
3: test = test + DM-Test(m, i)

4: end for
5: return test
Enforcing the off input sensitization criteria, the test function for a particular
off input is the disjunction of all delay measurable tests sensitizing the sub-paths
of Vof f along with the stable non-controlling value (SNCV) for that respective off
input. The measurable sensitization of the off input must be maintained only up to
the point where the off input and the targeted path converge. Algorithm 2 describes
the procedure generateTest(i) which generate a test function for a single off input i
of a target DM-PDF. Procedure DM-Test(m, i) produces a delay measurable test
for sub-path m starting at a primary input and ending at gate input i. Algorithm
3 effectively uses Algorithm 2 to generate a delay measurable test target PDF p.
Procedure SNCV(i) generates a stable non-controlling value at input i.
Algorithm 3 Find DM-PDF test

1: test = 1
2: for all gates g along path p do
3: for all off inputs i of g do

4: test = test * ( generateTest(i) + SNCV(i))
5: end for
6: end for
17
2.4 ADVANCED MEASUREMENT PROCEDURES
This section presents an extension for identifying DM-PDFs that were not
identified in Section 2.3. In Section 2.3 the sub paths within Vof f were sensitized
with stable non-controlling values up to the off input of the target path. The valida-
tion sensitization conditions will now be extended to allow delay measurable PDF
sensitization of the sub paths within Vof f by applying the arguments in Section 2.3
to the off-input sub paths. In other words, the technique will sensitize the off in-
put sub-paths using other DM-PDFs as long as the propagating transition reaching
the off-input obeys the off-input sensitization requirements described in Lemma 2.
Also the number of DM-PDFs can be increased by using newly identified DM-PDFs
to sensitize off-input transition for other target paths. These techniques effectively
increases the size of set Vof f , which in turn improves the chances for DM-PDF
sensitization of the on input transition.
2.4.1 Off-Input Sub-Path Sensitization
Any off-input sub-path ∈ Vof f which leads into an off input of a target path
can also be delay measured sensitized based on Lemma 2. Assume PDF p is an
element of Vof f and has the longest (shortest) delay of all paths in Vof f . Definition
1 states that the delay of path p is less than (greater than) the delay of the target
path. Based on this information we can treat the sub-path of p as an artificial
on-input path starting the sub-path at a primary input and ending at the off-input
of the target path. From here our task is to find a test function that sensitizes the
sub-path as a DM-PDF to ensure the off-input of the target path has a measurable
18
(known) delay that sensitizes the target path as stated in Lemma 2. This test can
be generated by applying Algorithm 3 on the sub-path of p starting from a primary
input and ending at the off-input of the target path.
Based on Definition 1 all paths within Vof f can be used to sensitize the off-
input transitions along the artificial on-input sub-path p which starts at a primary
input and ends at the off-input of the target path. Performing this type of sub-path
sensitization increases the possibilities for generating a DM-PDF because for a given
off input, any combination of one or more DM-PDFs through that off input path set
Vof f can be used to produce a measurable off input transition for the target path.
An example of off-input sub-path sensitization is described by considering
Figure 2.4. Suppose On-Path is the target path for a delay measurable test and it
has a single-off input at the point where On-Path and Off-Path 2 converge. Assume
Off-Path 1 and Off-Path 2 are both elements of Vof f and Off-Path 2 is path p as
described above in the off-input sub-path sensitization. Lemma 2 states to sensitize
On-Path as a DM-PDF, Off-Path 2 must be sensitized with a measurable delay up
to the point where On-Path and Off-Path 2 converge. Assume that sensitization
requirements do not allow stable non-controlling values on all off-inputs along Off-
Path 2 while simultaneously sensitizing On-Path with a delay measurable test
The off-input sub-path sensitization principle can be applied to the off inputs
along Off-Path 2. A pattern may exist that can delay measurably sensitize On-Path
by allowing a delay measurable transition at the point where On-Path and Off-Path
2 converge. That pattern may require a transition at the point where Off-Path 1 and
19
Off-Path 2 converge. In that case off-input sub-path sensitization uses a delay mea-
surable off input transition on Off-Path 1 to sensitize a delay measurable off-input
transition on Off-Path 2, that in turn allows the delay measurable sensitization of
On-Path. Off-input sub-path sensitization gives the test pattern generator greater
flexibility for finding a test for a DM-PDF.
On−Path Off−Path 1 Off−Path 2
Figure 2.4. Validated Off-Input Path
A second extension to the method allows for an increase in the size of the set
Vof f by reusing DM-PDFs. This is accomplished by adding any DM-PDF to the set
SDM and then placing those paths into any eligible off input Vof f set. Adding DM-
PDFs to Vof f allows us to use the newly added paths to help sensitized other paths.
Test generation can be performed again on any PDF which has a new DM-PDF
added to any of its off-input sets Vof f .
Techniques for identifying DM-PDFs can be extended beyond the procedures
presented previously in Sections 2.3 and 2.4. The major limitation in generating a
test for a DM-PDF is the number of off-inputs that require a stable non-controlling
value and the cardinality of Vof f at each off-input. The cardinality of Vof f can
20
be drastically increased by adding any PDF that is linearly dependent on SDM .
These linearly dependent paths can be safely added because the delay value can
be calculated using linear dependency relationships [8, 9]. The impressive results
shown in Section 2.5 are a result of increasing the cardinality of Vof f by adding the
paths which are linearly dependent on SDM .
The delay values for the paths in SDM are measured using a binary search with
the clock frequency [8]. A small offset value can be appropriately added or subtracted
to each linear dependency calculation to ensure that measurement inaccuracies do
not conflict with Conditions 1 and 2 from Section 2.3.
Under the proper delay model any off-input transition that obeys Definition
1 can be used to measurably sensitize the on-input transition. The bounded delay
sensitization conditions assume the bounded delay model is accurate and an accurate
delay defect variation parameter can be introduced if desired. The defect parameter
should model the largest delay defect along any path. Using these delay assumptions,
the sensitization conditions presented in Section 2.3 can be adjusted to take into
consideration the maximum defect parameter, and any path that obeys Definition 1
can be used in the set Vof f . The conditions in Definition 1 ensure that the measured
response for the target path lies outside of the delay value range for all off input
paths. If a measured delay does not conform to the bounded delay values a delay
defect is identified and the procedure should not use that PDF should not be added
to any Vof f set.
The advanced DM-PDF identification procedures increase in the number of
21
DM-PDFs significantly. The large number of DM-PDFs allows very large testable
basis sets, which results in a large percentage of critical path whose circuit timing
characteristics can be determined by using linear dependency relationships.
2.5 EXPERIMENTAL RESULTS
The proposed approach was implemented in C++ and run on a 900 MHz Sun
Blade 1000 workstation. Experimental results were performed on the ISCAS’85 and
ISCAS’89 benchmarks, and are summarized in three Tables (Tables 2.1, 2.2, and
2.3). The first column in each of these tables indicates the name of each benchmark.
Aux Strong Advanced
Bench Size Rob [8] DM-PDF DM-PDF
c880 744 744 744 744
c1908 1284 1184 1187 1284
c2670 2352 1556 1626 2134
c5315 5486 3838 3853 4254
c7552 5948 3958 4030 5028
s400 370 340 346 370
s444 396 306 310 396
s641 404 398 398 404
s713 480 242 242 480
s832 1012 962 981 1012
s1196 1024 948 962 1024
s1238 1676 948 969 1123
s1269 1384 976 1000 1050
s1423 1172 1082 1123 1167
s3271 2510 2330 2340 2510
s5378 3292 3156 3172 3258
s9234 5248 3296 3441 5248
s13207 8008 5658 5892 7658
s38417 23182 20118 20297 21859
Table 2.1. Basis Sizes by Different Methods
A function based test pattern generator [7] is used to determine testable paths
22
Crit Strong-Rob % DM % Adv. %
Bench Paths [8] LD PDFs LD DM-PDFs LD
c880 45,102 45,102 100 % 45,102 100 % 45,102 100 %
c1908 58,406 58,406 100 % 58,406 100 % 58,406 100 %
c2670 99,072 0 0% 0 0% 63,406 64 %
c5315 89,329 0 0% 0 0% 67,890 76 %
c7552 49,254 0 0% 0 0% 33,492 68 %
s641 3,444 3,284 95 % 3,284 95 % 3,444 100 %
s1196 6,196 5,764 93 % 5,983 96 % 6,196 100 %
s1238 7,116 5,080 71 % 5,681 79 % 7,043 99 %
s1269 35,280 16,800 48 % 23,520 67 % 35,280 100 %
s1423 35,166 19,386 55 % 29,106 83 % 33,816 96 %
s3271 48,927 15,167 31 % 17,614 36 % 48,927 100 %
s5378 63,263 33,529 53 % 41,121 65 % 57,569 91 %
s9234 72,192 38,261 53 % 41,871 58 % 72,192 100 %
s13207 86,936 24,342 28 % 29,558 34 % 79,112 91 %
s38417 1,243,527 572,022 46 % 634,199 51 % 1,156,480 93 %
Table 2.2. Testable Basis Coverage of Critical Paths
and the techniques from [9] are used to identify linear dependency relationships for
critical paths. Critical paths are identified by using the techniques in [7].
An auxiliary basis set [9] 1 is a basis set that has reached the maximum possible
cardinality and this size will be used as a reference for comparing cardinality of
testable basis sets. The maximum possible size of the basis set is the size of the
auxiliary set [9] which is listed in column 2 of Table 2.1. Column 3 of Table 2.1 shows
the size of the testable basis considering only strong robustly testable PDFs. The
size of ST B consisting of both strong robust PDFs and DM-PDFs is listed in column
4 of Table 2.1. Column 5 of Table 2.1 represents the size of ST B consisting of strong
robust, DM-PDFs, and advanced DM-PDFs is listed in. The DM-PDFs are identified
using the techniques described in Section 2.3, and the advanced DM-PDFs use the
1
An auxiliary basis set [9] is a basis set with maximum cardinality, and every single PDF in
the circuit is linearly dependent on this set.
23
techniques described in Section 2.4. Table 2.1 demonstrates the increase in the size
of the testable basis set when DM-PDFs, and advanced DM-PDFs are considered.
The size of the basis set increases for every circuit when DM-PDF techniques
are utilized, and comes very close to the size of the auxiliary set for almost all bench-
marks, which isn’t the case for the basis set consisting only of strong robustly tested
PDFs. Bold entries in Table 2.1 indicate testable basis sets which have cardinality
equal to the circuit auxiliary set size. Bold entries indicate circuits for which linear
dependencies can be used to determine the circuit timing characteristics of every
PDF in the circuit because every PDF in the circuit is linearly dependent on the
testable basis set. Over 50% of the circuits listed in Table 2.1 reach a maximum
testable basis set by using the advanced DM-PDF techniques whereas only one cir-
cuit (C880) reaches a maximum basis set size when strong robustly testable PDFs
are considered.
Once the basis sets are found, the circuit timing characteristics of critical paths
are determined by using the testable basis sets listed in Table 2.1. The critical path
coverage of the testable basis sets shown in Table 2.1 are listed in Table 2.2. The
number of critical paths is listed in column 2 of Table 2.2. The total number of
critical paths which are linearly dependent on the strong robust testable basis sets
is listed in column 3 and the percent of critical paths linearly dependent on that
basis set is listed in column 4. The total number of critical paths which are linearly
dependent on the DM-PDF and advanced DM-PDF basis sets are listed in columns
5 and 7 respectively. The corresponding percentages of linearly dependent critical
24
paths are listed in columns 6 and 8.
The results in Table 2.2 show a large percentage of critical paths whose circuit
timing characteristics can be determined by utilizing the procedures presented in
this chapter. Table 2.2 shows that the number of critical paths which are linearly
dependent on the enhanced testable basis set can be over two times the number of
critical paths linearly dependent on the strong robustly testable basis set [8]. For
some benchmarks zero critical paths are covered using the strong robust basis set,
however the percent of critical paths covered increases to over 64 percent for all
benchmarks, and in most cases covers one hundred percent of critical paths when
the techniques from this chapter are applied.

Strong Percent Advanced Percent
Benchmark Robust DM-PDF Increase DM-PDF Increase
c880 15102 16030 6.1 17249 14.2
c1908 25338 27611 9.0 40895 61.4
c2670 14388 16121 12.0 45189 214.1
c5315 77468 78587 1.4 125576 62.1
c7552 73148 75182 2.8 104643 43.1
s641 1540 1984 28.8 3010 95.5
s1196 3088 3370 9.1 4339 40.5
s1238 2852 3171 11.2 4498 57.7
s1269 6694 10116 51.1 45019 572.5
s1423 24458 34145 39.6 58522 139.3
s3271 7190 7642 6.3 21843 203.8
s5378 17106 18423 7.7 24046 40.6
s9234 14696 16387 11.5 489708 3232.3
s13207 19868 21040 5.9 27517 38.5
s38417 390900 401454 2.7 487452 24.7
Table 2.3. Number of Identified DM-PDFs
Table 2.3 shows the total number of identified DM-PDFs alongside the percent
increase when compared to traditional strong robustly testable PDFs. Column 2 of
25
Table 2.3 shows the number of strong robustly testable paths and column 3 shows
the number of DM-PDFs obtained using the test generation based on the algorithms
presented in Section 2.3. Column 5 represents the number of DM-PDFs identified
using the advanced techniques described in Section 2.4. Columns 4 and 6 represent
the respective percentage increases in the number of strong robustly testable paths
when comparing columns 3 and 5 with column 2. The percent increase from DM-
PDFs (column 4) to the advanced DM-PDFs (column 6) is tremendous and shows the
techniques presented in this chapter drastically increase the number of identifiable
delay measurable PDFs when compared to previous work [11].
Test generation and ATE test application is only performed on the linearly
independent strong robustly testable paths. The cardinality of those basis set sizes
(shown in column 4, Table 2.1) is significantly smaller than the number of DM-PDFs
(column 5, Table 2.3).
The results in Tables 2.1, 2.2, and 2.3 show that the presented methods in-
crease the number of DM-PDFs significantly. The listed benchmarks display a good
representation of the overall collection and similar results have been observed for the
remaining circuits in the collection. An impressive percentage of critical paths are
covered by the advanced basis set and in most cases a maximum basis set is found,
producing one hundred percent coverage of every path in the circuit. The increased
size of the testable basis set is shown to produce improvements when determining
circuit timing characteristics as demonstrated in Table 2.2. An advantage of deter-
mining circuit timing characteristics using linear dependency relationships is that
26
only the testable basis path set is tested.
2.6 CONCLUSION
This work presents an improved approach for determining delay values of crit-
ical paths by using linear dependency relationships. Theoretical aspects of delay
measurable PDF sensitization are extended and results show an increase in the num-
ber of MD-PDFs. The improved measuring techniques and other practical aspects of
delay fault testing are effectively utilized to improve coverage for determining timing
characteristics of critical paths. Experimental results show a significant increase in
coverage of critical paths for most circuits.
27
Chapter 3
FUNCTION-BASED ATPG FOR PATH DELAY FAULTS USING
THE LAUNCH-OFF-CAPTURE SCAN ARCHITECTURE
3.1 INTRODUCTION
With increasing complexity, and shrinking technology for low power and
greater performance modern ICs are becoming more sensitive to timing related de-
fects. These defects can be modeled using appropriate delay fault models such as
the transition fault model and the path delay fault model. While the transition fault
model and path delay fault model provide good coverage for delay induced defects
the latter becomes increasingly popular as it can be used to detect small delay de-
fects and noise related aspects in deep-submicron devices. A path delay fault can
be tested robustly or non-robustly. A robust test is guaranteed to detect the delay
defect with or without the existence of other delay defects within the circuit. On
the other hand a non-robust test assumes the circuit has delay defects only along
the PDF. This assumption is necessary because the transition of the PDF may be
masked due to other delay defects within the circuit thereby producing an incorrect
passing test result.
Path delay fault testing requires the application of a vector pair (V1, V2 ) to
sensitize and propagate the PDF throughout the selected path. The first test vector
initializes the circuit and the second test vector activates and propagates the desired
transition. The vector V1 enforces the robust sensitization criteria and is knows as
28
the initialization vector. Vector V2 which is known as the the launch vector initiates
and propagates the PDF transition. Vector V2 propagates the PDF by bringing
non-controlling values at all off inputs along the PDF. The response due to the
transition of the PDF is captured at the operational frequency of the circuit, also
known as at-speed testing. The application of the two vector sequence depends on
the scan architecture of the design. The three most popular scan architectures used
in the industry are enhanced-scan, launch-off-shift, and launch-off-Capture (LOC).
In the enhanced-scan architecture [4] any vector pair that sensitizes and prop-
agates the PDF can be applied to the circuit under test. The scan flip-flops used
in this architecture have the ability to store two test patterns instead of one. This
allows the scan and application of any two-vector test without imposing any scan
architecture constraints. The hardware overhead associated with scan flip-flops pre-
vents the use of the enhanced-scan architecture in industrial applications. In the
LOS method [20, 21] vector V2 is simply vector V1 shifted by one bit.
LOC [5, 6] overcomes the limitations of enhanced scan architecture and has
thus been widely adopted in industrial applications. Under the LOC scan architec-
ture the second vector V2 is the functional response of the first vector. The LOC
test pattern application is illustrated in Figure 1. The first vector is scanned in
while the scan enable(SE) is high. The response of the first vector is captured by
the scan cells producing vector V2 (launch vector) and the transition along the PDF
is initiated during the Launch phase of the clock cycle. The response of the launch
vector is then measured during the capture phase of the clock cycle. Any delay
29
defect along the path that exceeds the operational frequency is observed during the
capture phase.
Launch Capture
CLK
SE
shift shift shift shift
Figure 3.1. LOC Waveform
Several test generation techniques based on branch and bound algorithms such
as PODEM are proposed for delay faults. LOC test generation performed by struc-
tural techniques may require several backward/forward justifications when generat-
ing a valid test vector pair. The time and memory requirements for these justifica-
tions can be enormous and most of the time these test generation techniques abort
on a given path and may not be scalable for path intensive circuits. On the other
hand the proposed function-based technique is based on an implicit framework that
can overcome the limitations encountered while using structural techniques. A lot of
research effort has been directed towards developing LOC test generators for tran-
sition faults [22, 23, 24], however to our knowledge, no test generation techniques
for path delay faults have been proposed under the LOC architecture.
The work proposed in [7] generates tests for path delay faults under the en-
hanced scan architecture using functions and is scalable to handle path intensive
circuits. In this work we present a new function-based test generation methodology
for the path delay fault model under the LOC scan architecture that is built on top
30
of the scalable techniques proposed in [7]. The functions required to generate test
patterns that comply with the LOC test architecture conform well with the frame-
work of [7] allowing for the design of a scalable LOC ATPG tool. Just as in [7] the
method presented in this chapter uses Binary Decision Diagrams [25] (a canonical
data structure) to represent the test functions, and Zero-Suppressed Binary Decision
diagrams to store the paths in the circuit.
The rest of the chapter is organized as follows. In Section 3.2 we present
the path implicit framework and rationale. The proposed LOC test generation is
presented in Section 3.3. Experimental results are discussed in Section 3.4 and
Section 3.5 concludes the chapter.
3.2 PATH IMPLICIT FRAMEWORK AND RATIONALE
Traditional Automatic Test Pattern Generation (ATPG) tools for PDFs are
path enumerative therefore the exponential number of PDFs within a circuit in-
troduces problems such as ATPG execution time when trying to generate tests for
PDFs. A two phase approach is employed to reduce the time required for ATPG. In
the first phase static implications are used to remove a large number of untestable
PDFs [26, 27, 28]. The second phase incorporates a non-enumerative ATPG tech-
nique [7] that significantly improves the execution time required when compared
to traditional ATPG structural methodologies by avoiding path enumeration. The
second phase which is presented in Section 3.3 of this chapter, will identify testable
and untestable PDFs under the LOC scan architecture by processing partial paths
(fanout free segments) using the path implicit framework presented in [7].
31
A fanout free segment is formally defined in Definition 3 and the number of
fanout free segments in a circuit is linear with respect to the number of gates in the
circuit.
Definition 3. (Fanout-Free Segment [26]): A partial path or a fanout-free segment
is a sub-path in the circuit between a primary input and a fanout stem or between
two fanout stems or between a fanout stem and a primary output, with no other
fanout stems in between the starting node and terminal node of the segment.
Under the PDF model each fanout-free segment contains two faults. One
fault associated with the rising transition at the beginning of the segment as well
as one fault associated with the falling transition at the beginning of the segment.
A complete path from a primary input to a primary output can be represented by
concatenating the series of fanout-free segments comprising that path.
To avoid path enumeration test functions are generated for every fanout-free
segment. The test function for a fanout-free segment is dependent on the rising or
falling transition of the primary input as well as the rising or falling transition at
the beginning of the fanout-free segment. For a given primary input(PI) and a given
segment, the four possible test functions for that segment are the four combinations
of falling and rising transitions on the PI and the beginning of the segment. As
stated in [7] the maximum number of functions to generate tests for all the PDFs
in a circuit is:
4 * number of primary inputs * number of segments
32
The number of functions is a polynomial number because the test functions
for fanout-free segments are invariant for a given primary input transition and a
given falling input transition. Once all four functions are derived for each segment
and primary input pair, the test function for an entire PDF can easily be found by
taking the conjunction of the individual tests for each fanout-free segment along the
respective PDF. The procedure is formally described below in Lemma 4.
Lemma 4. [7] Let RP and RL be the functions containing all possible tests for the
PDF P and for the fanout-free segment li respectively. Representing PDF P as a
set of its fanout-free segments l1 ... ln allows the calculation of the test function for
PDF P by using the following formula:
n
Y
RP = RLi
i=1
Decomposing the PDFs into fanout-free segments allows the test function for a
particular segment to be calculated once and stored for later reuse. The fanout-free
decomposition prevents the function from being recalculated for each PDF passing
through that individual fanout-free segment thus eliminating the enumerative na-
ture of traditional structural based ATPG methodologies. This implicit framework
accelerates the ATPG computation and makes the technique very efficient for large
and path intensive circuits.
The details of a fanout-free segment representation scheme that allows quick
segment identification is described in [7]. Previous functional based ATPG method-
33
ologies targeting PDFs [7, 18] obey path sensitization criteria under the enhanced
scan test architecture. This chapter will utilize the implicit framework introduced
in [7] in a way such that the test functions at each segment obey the constraints
imposed by the LOC scan architecture as well as PDF sensitization criteria. The
technique for functional based ATPG for PDFs under the LOC scan architecture is
presented in Section 3.3.
3.3 LAUNCH-OFF-CAPTURE TEST GENERATION
In this section we present the proposed launch-off-capture test generation
method. Launch-off-capture test application involves a vector pair in which the
first test vector is the scan in steady state vector and the second test vector is
the functional response of the first test vector. The LOC test pattern generation
technique uses methods similar to those used in function-based sequential circuit
verification where the circuit under test is modeled as a finite state machine. The
problem of finding the second test vector is identical to finding all the possible next
states from a given current state in a finite state machine and is obtained using
reachability analysis. Reachability analysis is done by forming transition relations
and image computation.
3.3.1 Required Functions
Given an m-variable Boolean function f(x1 ,...,xm ), the existential abstraction
of f with respect to variable xi is the disjunction of the positive and negative cofac-
tors with respect to xi and is given below.
34
∃xi = fxi + fxi
Let s, x, and t represent vectors which denote the present state, input, next
state variables and δ(s, x) be the next state function for a sequential circuit with n
flip-flops. Let ≡ denotes the Xnor Operation. The transition relation function T(s,
x, t) of a sequential circuit describes the set of states connected through one state
transition and is defined as.
i=n−1
Y
T (s, x, t) = (ti ≡ δi (s, x))
i=0
Given the above definitions we easily compute the Image Im(T, C) for the set
of valid initial states C(s) as:
Im(T, C) = ∃x ∃s C(s) · T (s, x, t)
The Image computation will give the set of states connected through one state
transition under the restricted set of initial states C(s). In a similar way the set
of previous states for the current state I(t) can be determined using the Pre-Image
computation. The previous sates are the set of states which on a single transition
can reach the current state I(t). The Pre Image is defined as
35
P re − Image = ∃x ∃t I(t) · T (s, x, t)
3.3.2 LOC ATPG Procedure
ATPG for PDFs under the LOC scan architecture involves the use of standard
functional techniques and a set of image and pre-image computations. Standard
functional techniques [7, 18] are used to generate the set of all possible test vectors
that can be used during the first test sequence (V1 ) as well as during the second test
sequence (V2 ). Figure 2 shows LOC test generation procedure in a Venn diagram
format. The region represented by V1 is the set of all possible V1 vectors, and the
region represented by V2 is the set of all possible V2 vectors that are generated
using the techniques described in . We define ValidV1 vectors as the set of vectors
that can be initially applied as scan vectors and ValidV2 vectors as the set of vec-
tors that can be applied as launch vectors, where the application of ValidV1 and
ValidV2 vectors activate and sensitize the PDF under the LOC scan architecture.
After generating the possible V1 and V2 vectors and computing the transition rela-
tions we compute the image with C(s) being the set of all possible V1 vectors. The
result is the set of vectors which are reachable from V1 through one state transition.
This is represented by the region Im1.
Not all of the reachable states of V1 form the ValidV2 vectors. In order to
obtain the ValidV2 vectors , we take the conjunction of Im1 and V2, this is denoted
36
ValidV1 Im1
ValidV2
V1 V2
Pimg
ScanV1 LaunchV2
Figure 3.2. LOC Test Generation
by ValidV2 which is represented by the shaded region in V2. The resultant of the
conjunction will give the set of tests that can be applied during the second test
sequence(valid Launch vectors). After finding the ValidV2 vectors we need to find
the ValidV1 vectors. This is done in two phases, in the first phase the pre-image of
ValidV2 is computed, this is denoted by Pimg in the Venn diagram. In the second
phase the conjunction of V1 vectors and the Pimg is computed, the result is a set
of ValidV1 vectors. This is represented by the shaded region in V1. After obtain-
ing the ValidV1 vectors one cube ScanV1 is randomly extracted from ValidV1 and
the image of ScanV1 is computed to give the LaunchV2 vector LaunchV2. Thus
ScanV1 and LaunchV2 form a valid test pattern under the LOC scan architecture.
The entire test generation procedure is given in Procedure 1.
When using BDDs the resulting Image as well as the individual transition re-
lations may be small in size but the intermediate transition relation functions may
37
Algorithm 4 LOC Test Generation Algorithm
1: for each path P do
2: Generate all possible V1 and V2 vectors using standard functional Techniques

[7, 18].
3: Compute Transition Relations
4: Compute Image of V1, Im1 = Image(V1)
5: Identify valid vectors in V2, ValidV2 = V2 ∧ Im1
6: Compute the Pre-Image of ValidV2, Pimg = Pre-Image(ValidV2)
7: Identify the valid initialization(scan) vectors V1, ValidV1 = V1 ∧ Pimg
8: Pick a random vector ScanV1 from ValidV1
9: Compute Image of ScanV1 to obtain a LaunchV2 vector
10: end for
grow to a large size and become inapplicable on large designs. However the pro-
posed algorithm overcomes this problem because we do not compute the transition
relations for the entire circuit. In addition, as section 3.3 shows below, we adapt
the partition image computation technique as in [29].
We generate the next state and transition relation functions for the flops which
are present in the input cone of the flop/primary output where the path terminates.
All the paths that end at a flop/primary output are stored in a zero suppressed de-
cision diagram (ZDD) [7] and then considered for test generation before considering
the paths which end at other primary outputs. In this way the transition relations
are built only once for the flops which are in the input cone of a flop/primary output
and reused for all the paths that end at the flop/primary output. The test genera-
tion procedure for each flop/primary output is given in Procedure 2.
38
Algorithm 5 LOC ATPG Procedure
1: for each primary output/flip-flop P Oi do
2: Store all Paths that end at P Oi in a ZDD

3: Compute Transition Relations
4: LOC Test Generation Algorithm
5: end for
3.3.3 Details on Computing the Partitioned Image Method
The image computation involves a series of conjunctions of functions that
contain many variables followed by the quantification of a number of variables.
The individual transition relation functions as well as the result from the image
computation may be small in size however the intermediate products may grow quite
large. The standard image procedure takes all of the transition relation products
and then quantifies the variables. To avoid excessive sizes in the BDDs and to
increase the computational speed previous work in [29] describes a partitioned image
computation that allows the intermediate quantification of some variables during the
conjunction process by using the following lemma:
Lemma 5. [29] Let f:B m+n → B be a function of y1 ,...,ym , x1 ,...,xn and g : B m+n−i+1
→B be a function of y1 ,...,ym , xi ,...,xn , 1 < i ≤ n. Then:
∃x1 ...xn (f · g) = ∃xi ...xn (∃x1 ...xi−1 (f ) · g)
Lemma 5 states that the partial distribution of quantification can be performed
when all of the terms of the product do not depend on the variables. To be more
39
specific, if function g does not depend on x1 ,...,xi−1 then variables x1 ,...,xi−1 should
be quantified out of function f followed by a conjunction of function g with the
quantified result. Quantifying a variable out of the intermediate product will remove
that variable from the quantified function and reduce the size of the intermediate
result.
To determine the order in which quantification takes place a transition list is
built by building sets of next state functions and then determining the appropriate
intermediate quantifications by examining the support variables of the next state
functions. As an example consider a circuit with three flip-flops and n primary
inputs. In this circuit variable s1 is in support of next state functions δ 1 , and δ 2 .
Variable s2 is in support of next state functions δ 2 , and δ 3 . And variable s3 is in
support of δ 1 , and δ 3 . Because s1 is in support of next state functions δ 1 and δ 2 a
partial transition relation function can be created when the following quantification
is computed:
Ts1 = ∃s1 ((t1 ≡ δ1 ) · (t2 ≡ δ2 ) · C(s))
Since δ 2 is already included in the conjunction of the previous calculation it is
not included again in the quantification of s2 .
Ts2 s1 = ∃s2 (Ts1 · (t3 ≡ δ3 ))
40
To complete the image computation we have s3 in support of δ 1 , and δ 3 . These
two next state functions already exist in the partial transition relation function
therefore a quantification of s3 is performed on the intermediate result as follows:
Img(C(s)) = ∃x ∃s1 Ts2 s1
It is very important not to violate Lemma 5 by quantifying a variable before
every next state function that is supported by that variable is included in the partial
transition relation through a conjunction at either the current step or through a
previous step.
Critical % Rob % Critical CPU(s)
Bench PDFs Rob. Test LOC Test PDFs Rob. Test LOC Test LOC Rob. LOC Total Per PDF Mem (Mb)
s510 738 729 190 71 69 26 26.1 37.7 12 0.174 2.2
s635 2492 2429 162 88 81 16 6.7 19.7 17 0.210 3.2
s938 3460 3428 756 132 130 47 22.0 36.2 24 0.185 3.9
s13207 2690738 27603 3628 25326 12521 3873 13.1 30.9 1627 0.123 271.0
s38584 2161446 92239 21615 2053 1495 1047 23.4 70.0 264 0.177 383.0
s526 820 694 143 57 36 4 20.6 11.1 7 0.194 1.9
s991 11781 8175 2465 151 92 52 30.2 22.0 22 0.239 3.6
s1423 89452 28696 3492 3891 560 8 12.1 1.4 88 0.157 5.8
s9234 489708 21389 7646 12529 317 52 35.7 16.4 62 0.196 46.0
s35932 394282 21783 12960 19762 986 172 59.4 17.4 159 0.161 245.0
Table 3.1. Robust PDF Testability for LOC
In this section we present the experimental results for the proposed LOC
ATPG tool for path delay faults. The proposed approach is implemented in C lan-
guage and was evaluated on the ISCAS’89 benchmark circuits using a SunWBlade-
1000 Workstation with 2GB RAM. The CUDD package [29] was used to generate
41
the test functions in BDD format. Test functions based on the robust sensitization
criteria were generated first using the methods in [7]. The set of robustly testable
paths for the enhanced scan architecture [7] are then identified using the test func-
tions. The proposed LOC method is applied on the robustly testable paths. The
results for some of the ISCAS’89 benchmarks are listed in Table 3.1.
Column 2 shows the total number of PDFs in the circuit. Column 3 shows the
total number of robustly testable paths under the enhanced scan architecture. The
number of paths that are robustly testable under the LOC scan architecture are
shown in column 4. Columns 5-7 show the test data for the critical paths obtained
under the unit delay model. Column 5 shows the total number of critical paths.
Column 6 shows the total number of critical paths that are robustly testable under
the enhanced scan architecture and column 7 shows the total number of critical
paths that are testable under the LOC scan architecture. Column 8 shows the
percentage of the total number of paths that are robustly testable under the LOC
scan architecture. Column 9 shows the percentage of the total number of critical
paths that are robustly testable under the LOC scan architecture. Column 10 shows
the CPU time in seconds for LOC test generation for the critical PDFs. Column 11
shows the average CPU time for each robustly testable PDF processed. Column 12
shows the memory utilization for the BDDs.
The experimental results showed that for a large number of circuits the critical
paths ran through a very small set of output flip-flops. As a result some circuits
showed a very high percentage of critical PDFs that are robustly testable under
42
the LOC scan architecture when compared to the percentage of the total number
of PDFs testable under the LOC scan architecture. The first five benchmarks in
Table 3.1 exhibit this type of characteristic. These benchmarks have good LOC
testability for critical PDFs because the set of outputs for which the critical PDFs
run through have a functionality that favorably supports LOC when compared to
the functionality of the entire circuit.
On the other hand some circuits showed very poor LOC testability when com-
paring the percentage of critical PDF that are LOC testable with the total number
of PDFs that are LOC testable. The last five benchmarks in Table 3.1 exhibit this
type of characteristic. Those benchmarks have poor LOC testability for critical
PDFs because the set of outputs for which the critical PDFs run through have a
functionality that does not supports LOC very well. It is difficult to test for delay
defects under the LOC scan architecture for circuits that exhibit this characteristic.
3.5 CONCLUSION
In this chapter we proposed a novel function-based technique for path de-
lay faults under the LOC scan architecture. The proposed method uses standard
functional test generation techniques as well as function-based sequential circuit
verification techniques. A path implicit framework and a partitioned Image compu-
tation technique are incorporated into the LOC ATPG procedure to improve ATPG
performance and make the procedure scalable to path intensive circuits.
43
Chapter 4
COMPACT TEST PATTERN GENERATION FOR PATH DELAY
FAULTS USING IMPLICIT PATH SELECTION
4.1 INTRODUCTION
Modern circuits contain an exponential number of path delay faults (PDFs).
A large number of these faults are critical [7] and affect the timing characteristics
of the circuit, however only a small number of critical PDFs can be tested because
of limited automatic test equipment (ATE) test time. There are several test set
compaction techniques that try to increase the number of tested PDFs without
increasing test application time.
The proposed compaction technique will focus on non-robust and robust sensi-
tization. A robustly sensitized PDF is guaranteed to detect a delay defect irrespec-
tive of other delay defaults in the circuit [30]. On the other hand, a non-robustly
sensitized PDF may not detect a defect in the presence of other defects. Robust
sensitization is much more restrictive than non-robust sensitization therefore it is
usually more difficult to compact robustly sensitizable PDFs.
Previous work in [31] shows that a large number of PDFs are untestable.
Static implications [27, 26] have been used to identify a lower bound on the number
of untestable PDFs. The work in [7] utilizes static implications alongside binary de-
cision diagrams (BDDs) [32] to identify all untestable PDFs by iteratively processing
fanout-free segments. The proposed compaction methodology is built on top of the
framework in [7], and uses canonical data structures to process circuit segments to
compact PDFs with similar segment characteristics.
44
Existing compaction techniques are presented in [33, 34, 35, 36, 37, 38]. The
technique in [33] proposes a dynamic compaction scheme based on selecting circuit
cross points between primary and secondary faults. The cross points are chosen
in a way such that compaction is improved on the selected primary and secondary
paths and is also intended to improve detection of some other unselected paths. This
method can be effective, however it compromises fault coverage to achieve small test
sizes.
Previous work in [3] performed compaction with test functions however the
method operates on fanout free segments which hinder performance with high ex-
ecution time. The work in [3] achieved high compaction rates through multiple
iterations which may not be practical for large designs. The proposed work uses in-
telligent path selection that provides compaction rates better than those presented
in [3], without the added expense of multiple iterations. The iteration procedure
presented in [3] can be used with the presented work to further improve compaction
if desired.
The compaction technique presented in [34] uses a multi-value algebra system
that focuses on expanding primary and secondary faults. The work in [35] selects
two subsets of paths. Primary paths are selected as long paths and will have tests
generated for them. Tests for primary paths are generated in a way such that they
also cover a good number of secondary paths. In [36] sets of maximal fault compat-
ibility are considered. Necessary condition on circuit lines are identified along with
conflicting path sensitization values of lines. In [34, 35, 36] fault detection is not
45
guaranteed and the methods rely heavily on accidental detection. A function based
ATPG compaction tool is proposed in [37], however the method requires multiple
circuit traversals and complete fault coverage is not guaranteed. Recently a dy-
namic compaction scheme [38] was proposed to compact PDFs with non-conflicting
assignments. However the technique is path enumerative, and paths are greedily
selected without considering how justification and backtracking may influence the
structural-based compaction technique. The path selection technique presented in
Section 4.3 of this chapter can be used to guide the procedures in [38] if one is to
rely on structural based compaction techniques.
The proposed work presents a function-based ATPG tool that generates very
compact test sets while avoiding path enumeration. The proposed compaction tech-
nique utilizes a canonical representation of paths in the form of a zero suppressed
binary decision diagram (ZBDD) [39]. ZBDDs are very efficient at storing sparse
sets, such as PDFs [17]. An effective path selection tool encodes compaction-specific
information into the ZBDDs and the ATPG tool consults the ZBDD data structure
to determine what paths should be considered for compaction into each individual
test. When compared to previous work, the use of the proposed function-based
ATPG tool alongside the encoded ZBDD path selection tool shows significant im-
provements in compaction rates of both non-robust and robustly sensitizable PDFs.
The compaction approach presented in this chapter can be applied to any scan ar-
chitecture. It can easily be used with the LOC test generation technique presented
in Chapter 3 by using LOC test functions (instead of enhanced scan test functions)
46
durring the compaction procedure.
This chapter is organized as follows. Section 4.2 describes the basic function
based compaction approach. Section 4.3 describes an enhancement in test com-
paction that applies implicit path storage and selection to guide an ATPG tool for
compaction. Section 4.4 presents the experimental result, and Section 4.5 concludes
the chapter.
4.2 FUNCTION-BASED COMPACTION
This section outlines the non-enumerative ATPG compaction tool that uses
boolean functions within a path implicit framework to achieve enormous savings in
computational effort. Traditional structural compaction techniques do not perform
well due to the lengthy justification/backtrack phase. However, previous work in
[18] and [40] showed how Reduced Ordered Binary Decision Diagrams (BDDs) [32]
can be used to implicitly store all possible satisfying assignments to sensitize a PDF.
Storing functions for segments benefits from the fact that a particular segment is
an element of a large number of PDFs. A test function for a particular segment is
computed one time and can be reused to generate a test for any PDF that passes
through that segment. Test functions for segments can be individually stored since
the number of segments in a circuit is linear with respect to the size of the circuit.
Satisfying assignments for each segment are stored and used to perform ATPG for
PDFs. Test functions in [32, 7] are stored in BDDs, however they can be stored in
other formats such as SAT equations [41].
The work in [7] presents a non-enumerative test generation technique based
47
on fanout-free segments segments. A fanout-free segment is defined as a sub-path
between the primary input and a fanout stem or between two fanout stems or
between a fanout stem and primary output, given that no other fanout stem is
between the starting node and terminal node of the segment. A test for a PDF is
constructed by intersecting the test functions of all the segments along that PDF.
During the construction of a test, it is often the case where the test for a sub-path
has no satisfying assignments. When a sub-path has no satisfying assignments, all
PDFs that run through that sub-path are identified as untestable and are removed
from further consideration. This iterative approach avoids path enumeration and is
very effective because many paths are removed by identifying untestable subpaths.
The work in [7] is a very fast and effective non-enumerative test generation
technique that generates a test for each sensitizable PDF on every available bench-
mark. However a single test for each PDF results in prohibitively long test sets. The
proposed work mimics, and improves the implicit nature of [7] and is capable of pro-
ducing very compact test sets. The proposed work stores a single test function that
sensitizes many PDFs in a single test. This compact test sensitizes PDFs denoted as
P C and has a respective test function denoted as F C . A candidate PDF is selected
to be compacted into the existing test. An intelligent path selection technique is
presented in Section 4.3, however for explanational purpose assume a random PDF
is selected. Compaction is performed by processing the gate segments along the
candidate PDF. A gate segment is defined as a sub-path that includes an input to
a gate g and the output of the same gate g. For the remainder of this chapter gate
48
segments will be referred to as segments. As in [7] test functions for segments will
be calculated once and will be reused by many different PDFs.
The proposed approach attempts to compact a new candidate PDF p with the
existing set P C by intersecting function F C with the test functions of the segments
along path p until p is compacted with the existing test set P C or it is identified
that p is incompatible with P C . PDF p is incompatible with P C if p and P C cannot
be compacted into a single test. The detailed explanation of the two conditions for
compaction compatibility are listed below.
Condition 3. If p is compatible with P C , the test function for the compact set (F C )
is intersected with the test function for the candidate path (FP ) and a new compact
test P N
C
ew
with respective test function F N
C
ew
are formed where P N
C
ew
= P C ∪ p and
N ew
F C = F C ∩ FP .
Condition 4. If p and P C are incompatible the intersection of F C and FP is

an empty set. The compaction procedure considers a single uncommon segment si
along path p and determines whether or not it is compatible with the test function
for the existing compact test. Uncommon segments are processed until a sub-path of
one or more uncommon segments are identified as incompatible. All PDFs that run
through the incompatible sub-path are also incompatible and are no longer considered
for compaction with the existing test.
The use of functions allows the proposed compaction technique to non-
enumeratively process PDFs in an iterative manner as follows: a path is iteratively
selected and considered for compaction with an existing test; however if that path
is not compatible with the existing test many PDFs can be removed from con-
sideration. PDFs can be implicitly identified and removed by means of efficient
ZDD (zero-suppressed binary decision diagram ) operators [17]. Previous work [7]
processes fanout-free segments to avoid path enumeration. The presented work im-
proves on the ideas from [7] and processes gate segments instead to maximize the
49
number of PDFs that can be implicitly identified as incompatible. Processing gate
segments benefits the proposed non-enumerative compaction methodology because
gate segments are smaller than fanout free segments and identification of incompati-
ble gate segments increases the number of PDFs implicitly removed when compared
to identification of fanout free segments.
The processing of gate segments is especially useful in compaction, where
often a single gate segment can be identified as incompatible and many PDFs can be
removed from consideration. The most basic example considers an existing test that
contains a single PDF with a rising transition on a primary input i. If a candidate
PDF starts from the same input i and has a falling transition, the test functions
identify the falling segment as incompatible with the existing test set. Then all
PDFs through that falling input i would be implicitly removed from consideration
of compacting with the existing test.
This implicit framework makes the proposed compaction technique very effi-
cient, even for path intensive circuits. The path selection technique described in
Section 4.3 elaborates on how to effectively identify incompatible PDFs and how to
select candidates for the implicit compaction methodology.
Algorithm 6, denoted as Single Set Compaction (SSC), describes the process
for generating a single compact test pattern for a set of PDFs. Before SSC is
invoked, test functions for all gate-segments are generated and stored in a look-up
table LT . The procedure SSC accepts three arguments. A set of potentially testable
50
Algorithm 6 Single Set Compaction - SSC(ζ, P C , F C )
1: for each path p ∈ ζ do
2: f lag = f alse
3: temp = Fc
4: for all uncommon segments si ∈ p, i = 1 to n do
5: temp = temp ∩ LT [si ]
6: if temp == then
7: ζ = ζ − pdf sT hrough(s1 , ..., si )
8: f lag = true
9: break
10: end if
11: end for
12: if not f lag then
13: P C = PC ∪ p
14: FC = temp
15: end if
16: end for
candidate PDFs (ζ); this set can be critical PDFs or can be the set of all PDFs as
in this chapter. The second argument is a set of compacted paths P C , and is the
set of paths that have been compacted into a single test. The third argument, F C
is the boolean function that stores all satisfying assignments to sensitize all paths
in P C with a single test. In order to generate a new compact test, P C is an empty
set (Ø), and F C is constant “one”.
Algorithm 6 attempts to compact a single PDF p into the compacted path
set P C . This is accomplished by considering uncommon segments along p and
51
Algorithm 7 Compact PDFs (ζ)
1: for each segment s do
2: generate LT [s]
3: end for
4: k = 1
5: while 1 do
6: PC [k] =
7: SSC(ζ, PC [k], 1)
8: if PC [k] == then
9: break
10: end if
11: remove PC [k] f rom ζ
12: k =k+1
13: end while
intersecting the test functions as described in Conditions 3 and 4.
Algorithm 7 compacts all testable PDFs ζ into k test patterns. Before com-
pacting paths, the test functions for segments are created and stored in the look-up
table LT . Procedure SSC (Algorithm 6) is called repeatedly to create new sets of
compacted paths. P C [k] represents a single set of compacted PDFs. After a new
compact set P C [k] is found, the paths in P C [k] are removed from ζ so they are not
considered for compacting in any other test. The while loop runs until the new set
of compacted PDFs ( P C [k] ) is empty, at that point there are no more testable
PDFs left in ζ and the procedure stops.
To illustrate the compaction procedure described in Algorithm 7, s27 from the
ISCAS ’89 benchmark collection is processed. Figure 4.1 shows s27 and Figure 4.2
52
Figure 4.1. s27
shows the compaction of a set of randomly selected PDFs for one test pattern P.
Once again Section 4.3 provides a novel technique to select PDFs, however for time
being assume arbitrary PDFs are selected for compaction. To begin the procedure
a random PDF is selected { 9F - 10R - 11R - 12F - 13R – 19F }. Then a test is
formed using LT and the PDF is added to compact path set P C . The next PDF
selected is { 9F - 10R - 11R - 12F - 13R – 16R }. The uncommon segment 16R is
highlighted in bold. Common sub-path { 9F - 10R - 11R - 12F - 13R } is already
contained in the test function F C . The test function for this segment is compatible
with the test function for the existing test set (F C ) so path { 9F - 10R - 11R - 12F
- 13R – 16R } is compacted with compact set P C . Compacted paths CP3 and CP4
are compacted in a similar fashion. The next path selected {9R - 10F - 17R – 18R }
contains uncommon segment 9R which is identified as incompatible (highlighted in
bold with italic subscript) with P C so all paths through segment 9R are removed
from consideration.
Figure 4.2 demonstrates the implicit non-enumerative nature of the proposed
compaction technique as there are 14 compacted paths and the test function inter-
53
Input 9: CP 1 : 9F - 10R - 11R - 12F - 13R - 19F
CP 2 : 9F - 10R - 11R - 12F - 13R - 16R
CP 3 : 9F - 10R - 11R - 12F - 13R - 14F - 15F
CP 4 : 9F - 10R - 17F - 18F
Incompatible: 9R - 10F - 17R - 18R
Input 4: CP 5 : 4F - 13R - 19F

CP 6 : 4F - 13R - 16R
CP 7 : 4F - 13R - 14F - 15F
Input 3: CP 8 : 3R - 8R - 12F - 13R - 19F
CP 9 : 3R - 8R - 12F - 13R - 16R
CP 10 : 3R - 8R - 12F - 13R - 14F - 15F
Input 1: CP 11 : 1F - 10R - 11R - 12F - 13R - 19F
CP 12 : 1F - 10R - 11R - 12F - 13R - 16R
CP 13 : 1F - 10R - 11R - 12F - 13R - 14F - 15F
CP 14 : 1F - 10R - 17F - 18F
Incompatible: 6R – 7R - 11R - 12F - 13R - 16R
Figure 4.2. Compaction of a set of PDFs
sects with 17 compatible segments (highlighted in bold). The example also shows
the effectiveness of the implicit removal of incompatible PDFs. Segment 9R is iden-
tified as incompatible and 4 PDFs are removed with the intersection of test function
LT [9R] with F C . When PDF {6R – 7R - 11R - 12F - 13R – 16R } is processed sub-
path {6R – 7R } is incompatible and all PDFs through {6R – 7R } are removed from
consideration. A total of 6 paths can be removed after identifying sub-path {6R –
7R } is incompatible. The compacted result listed in Figure 4.2 can be obtained after
one application of Algorithm 6; however the individual PDFs compacted into a test
set depends on the order of processing the candidate PDFs. A second compact set
is obtained in the same manor (as described in Algorithm 7); however the PDFs
compacted in the first test set should not be considered during the second call to
54
procedure Single Set Compaction (SSC).
Section 4.3 presents a technique which provides the ATPG tool a mechanism
for selecting the order of candidate PDFs. The path selection is performed in a
way such that a selected PDF can help improve the quality and performance of
the ATPG process irrespective of whether or not the PDF is compatible with the
existing test set.
4.3 ZDD-BASED PATH SELECTION
Section 4.2 demonstrated how the proposed compaction technique processed
segments to avoid path enumeration. This section describes how a canonical data
structure will guide the function based compaction algorithm presented in Section
4.2. The PDF selection technique presented in this section attempts to implicitly
identify PDFs that have a high chance of being compacted with an existing test, and
at the same time allows a large number of paths to be removed from consideration
if the selected PDF cannot be compacted with the existing test. The selection
criteria relies on implicitly identifying paths with the fewest uncommon segments
with respect to the current test.
All candidate PDFs that are eligible to compact with an existing test are stored
in a ZDD [17]. Each path in the ZDD is encoded with an extra variable which denotes
the number of uncommon segments. An uncommon segment is defined as a segment
that is an element of at least one PDF in the candidate set and is not an element
of any PDF in the existing test. The extra variable is referred to as a path length
encoding (PLE) variable because it represents the length of the sub-path that will
55
be processed to determine whether or not the candidate PDF can be compacted
into the existing test. This PLE variable can be added to all PDFs stored in the
ZDD with a single topological traversal of the circuit.
Initially compaction begins with an empty test set and the PLE of each PDF
is equal to the length of the PDF because no segments have been added to the
existing test set. When a PDF is identified as compatible with the existing test,
it is removed from the candidate set (ZDD) and all uncommon segments along
that PDF are identified as newly common segments. The PLE variables of all
remaining candidate PDFs stored in the ZDD are adjusted to reflect the fact that
some uncommon segments are now termed as newly common segments because they
are now elements of the existing test. Adjusting the PLE of all PDFs in the ZDD is
implicitly performed using efficient ZDD operators.
The function-based compaction methodology presented in Section 4.2 consults
the ZDD and implicitly selects a PDF with the smallest PLE. The selected PDF is
P LE P LE
denoted as Pmin . There are two advantages of selecting Pmin as the candidate PDF
P LE
for compaction. Pmin contains the fewest uncommon segments among all candidate
PDFs, therefore requires the smallest number of test function intersections with the
existing test. Performing a minimal number of function manipulations generally
P LE
increases the likelihood that Pmin will be compatible with the existing test. It also
results in a less constrained test function (because of fewer function intersections)
P LE
if in fact Pmin is compatible with the existing test. A test function that is less
constrained is in general, also easier to compact with other PDFs when the next
56
P LE
candidate is selected from the ZDD. The second advantage occurs when Pmin is
P LE
incompatible with the existing test. Selecting Pmin in general means that a small
number of uncommon segments are processed. Hence the incompatible sub-path
identified (s1 , ..., si ) in Algorithm 6 is likely to be a short sub-path. All PDFs
through the incompatible sub-path are removed from the candidate set. A short
sub-path generally removes many more PDFs when compared to a long sub-path.
The PLE Zdd-based path selection presented in this section has advantages
P LE
irrespective of whether or not the selected candidate PDF Pmin is compatible with
the existing test. Results show that the path selection technique is extremely effec-
tive when used alongside the function-based compaction scheme presented in Section
4.2. The path selection technique can also be applied to structural based techniques
to help reduce time required for justification and backtracking.
The proposed approach was implemented in C++ and run on a 900 MHz Sun
Blade 1000 workstation. The performance was experimented on the ISCAS’85 and
ISCAS’89 benchmarks. The compact ATPG is evaluated in terms of the average
number of PDFs detected by each test, denoted as T AV . T AV is calculated by
dividing the total number of PDFs detected by the total number of tests generated.
The experimental results of the proposed methodology is compared with results
published in [42, 34, 35, 36, 37].
Table 4.1 shows the results for robust tests on the ISCAS’89 benchmark cir-
cuits. Column 1 of Table 4.2 give the circuit name, and column 3 shows the number
of robustly testable PDFs identified using the methods in [7]. Note that [7] does
57
Circuit CPU [7] [34] [35] [36] NEAT [37] Proposed
sec Robust PDFs # tests/ T AV # tests/ T AV # tests/ T AV # tests/ T AV # tests/ T AV
s298 0.4 343 62 / 5.3 67 / 5.11 61 / 5.62 61 / 5.62 58 / 5.91
s344 0.17 611 112 / 5.4 105 / 5.81 98 / 6.23 96 / 6.36 88 / 6.94
s349 0.16 611 112 / 5.4 107 / 5.71 NA 108 / 5.65 85 / 7.18
s382 0.13 667 123 / 5.4 113 / 5.9 106 / 6.29 110 / 6.06 97 / 6.87
s386 0.18 413 NA 136 / 3.03 118 / 3.50 118 / 3.50 113 / 3.65
s400 0.25 663 NA 109 / 6.08 102 / 6.50 101 / 6.5 96 / 6.9
s444 0.26 586 106 / 4.8 108 / 5.42 97 / 6.03 99 / 5.90 96 / 6.10
s526 0.20 694 NA 161 / 4.31 131 / 5.30 133 / 5.77 117 / 5.93
s641 0.78 1941 NA 212 / 9.5 187 / 10.58 186 / 10.59 170 / 11.41
s713 0.29 1184 NA NA NA 205 / 5.77 83 / 14.26
s820 0.60 980 263 / 3.7 273 / 3.58 250 / 3.92 250 / 3.92 219 / 4.47
s832 0.52 984 269 / 3.6 275 / 3.57 NA 265 / 3.71 223 / 4.41
s953 1.53 2348 454 / 4.9 495 / 4.55 411 / 5.6 411 / 5.6 354 / 6.63
s1196 0.89 3581 649 / 4.5 725 / 4.93 556 / 6.44 555 / 6.45 500 / 7.16
s1238 1.64 3589 NA NA NA 595 / 6.03 482 / 7.44
s1423 76.32 28696 NA NA NA 2978 / 7.1 3787 / 7.57
s1488 4.86 1875 427 / 4.3 435 / 4.31 390 / 4.81 NA 343 / 5.46
s5378 25.08 18482 860 / 19.3 NA NA NA 884 / 20.90
s9234 63.46 NA NA NA NA NA 1437 / 14.87
s13207 197.12 NA NA NA NA NA 2287 / 12.04
s38417 2571.30 598,062 NA NA NA NA 41764 / 14.32
* T AV = total number of PDFs detected / the total number of tests generated
Table 4.1. Compaction of Robust PDFs in the ISCAS’89 Benchmarks
not perform compaction and generates a single test for each path. Column 2
reports the CPU time for the proposed method. Columns 4-7 compares the pro-
posed compaction scheme with existing methodologies that target the generation
of compact test sets [34, 35, 36, 37]. The methods in [34, 35, 36] explicitly target
the generation of the compact test sets, but are path enumerative. Those methods
generate compact test sets on a path by path basis, which is found to be ineffi-
cient approach for circuits with large number of paths. The approach in [37], is
a function-based non-enumerative compact test generation technique, however the
compaction approach processes PDFs from a collapsed lists of outputs and inputs,
therefore the compaction scheme requires several lengthy passes to achieve high fault
58
coverage. Even so the proposed compaction scheme provides one-hundred percent
fault coverage whereas the work in [37] cannot. Column 8 lists the compact test
results of the presented work. It is shown by the bold entries that our compaction
scheme outperforms all existing approaches and generates better compaction results
for every listed benchmark. Entries with “NA”, indicate data was not available for
comparison.
Table 4.2 shows the results for compacting non-robust PDFs from the IS-
CAS’89 benchmarks. Column 1 gives the circuit name. Column 2 reports the CPU
time required for compaction. Column 3 shows the number of PDF identified by
[7]. Column 4 shows compaction results from NEAT [37]. Column 5 shows the
proposed approach reports a higher T AV (more than double in most of the circuits)
for all the circuits listed in Table 4.2.
Table 4.3 shows the result for robust test on the ISCAS’85 benchmarks.
Columns 1 and 2 show the circuit name with the respective time required for com-
paction. Column 3 shows the number of PDF identified by [7]. Columns 4 and 5 show
the compaction results published in the works of [42] and [37] respectively. Column
6 demonstrates the proposed approach achieves higher T AV for all the benchmarks.
It can be noted that for some circuits column 6 reports more tests. This is because
it was difficult to generate the same number of critical PDFs as those generated by
[42] and [37]. Table 4.3 demonstrates the proposed approach greatly outperforms
both [42] and [37].
Table 4.4 presents the result for the non-robust tests on the ISCAS’85 bench-
marks. Columns 1 and 2 report the circuit with CPU time. Column 3 shows the
number of PDF identified by [7]. Column 4 shows the results reported in NEAT [37].
It is shown that the proposed work outperforms NEAT [37] for all the benchmarks
presented. Due to time limitations we were not able to include the results for the
59
non-robust of [33].
Table 4.5 compares the results for compacting robust PDFs from the ISCAS’89
benchmarks between methods in [3] and the proposed approach. Column 1 reports
the circuit. Columns 2 and 4 reports the CPU time. Column 3 reports the results
in [3]. Column 5 presents the compaction results reported in this chapter.
Table 4.6 compares the results for compacting non-robust PDFs from the IS-
CAS’89 benchmarks between methods in [3] and the proposed approach. Column 1
reports the circuit. Columns 2 and 4 reports the CPU time. Column 3 reports the
results in [3]. Column 5 presents the compaction results reported in this chapter.
Table 4.7 compares the results for compacting robust PDFs from the ISCAS’85
benchmarks between methods in [3] and the proposed approach. Column 1 reports
the circuit. Columns 2 and 4 reports the CPU time. Column 3 reports the results
in [3]. Column 5 presents the compaction results reported in this chapter.
Table 4.8 compares the results for compacting non-robust PDFs from the IS-
CAS’85 benchmarks between methods in [3] and the proposed approach. Column 1
reports the circuit. Columns 2 and 4 reports the CPU time. Column 3 reports the
results in [3]. Column 5 presents the compaction results reported in this chapter.
The tables demonstrate the proposed approach greatly outperforms the work
in 4.8 in terms of compaction rate as well as execution time.
4.5 CONCLUSION
This chapter presented an efficient scheme for compact test pattern genera-
tion. The presented approach avoids path enumeration and generates small test sets
based on an implicit framework of PDF selection and removal. The experimental
results demonstrate the effectiveness of the scheme when compared with existing
work in test compaction for PDFs. The compaction rates found by the proposed
technique outperforms all other existing methodologies. The compaction approach
60
Circuit CPU [7] NEAT [37] Proposed
sec # tests/ T AV # tests/ T AV
s298 0.06 364 64 / 5.68 29 / 12.55
s344 0.06 654 102 / 6.19 44 / 14.86
s349 0.05 656 97 / 6.53 44 / 14.90
s382 0.04 734 118 / 6.22 54 / 13.59
s386 0.12 414 101 / 4.10 64 / 6.46
s400 0.11 753 107 / 7.05 57 / 13.21
s444 0.17 813 83 / 7.06 57 / 14.26
s526 0.18 720 116 / 6.21 78 / 9.23
s641 0.62 2231 181 / 12.54 110 / 20.28
s713 0.52 4922 259 / 19.00 112 / 43.94
s820 0.16 984 209 / 4.71 95 / 10.35
s832 0.37 996 210 / 4.74 95 / 10.48
s953 1.13 2358 361 / 6.4 193 / 12.21
s1196 3.91 3759 477 / 7.88 308 / 12.20
s1238 2.91 3684 416 / 8.85 293 / 12.57
s1423 30.72 45198 2637 / 4.56 1873 / 24.13
s1488 0.68 1916 NA 125 / 15.32
Table 4.2. Compaction of Non-Robust PDFs ISCAS’89
was presented to compact PDFs under the enhanced scan architecture. The pre-
sented compaction methodology can easily be adjusted to compact PDFs under the
LOC scan architecture by using the appropriate LOC test functions instead of the
enhanced scan test functions. This dissertation showed how to generate LOC test
functions in Chapter 3. The LOC test functions in Chapter 3 can be directly appied
the the compaction technique presented in this chapter.
61
Circuit CPU [7] NEST [42] NEAT [37] Proposed
sec # tests/ T AV # tests/ T AV tests/ T AV
c880 40.3 16083 3108 / 2.7 3005 / 5.23 2537 / 6.34
c1355 78.2 22784 115 / 1.42 115 / 2.62 6863 / 3.32
c1908 705.3 97588 4748 / 1.95 4501 / 6.2 14062 / 6.94
c2670 44.7 15370 2898 / 2.73 2411 / 5.81 1581 / 9.71
c3540 237.3 88408 1486 / 4.7 1485 / 11.81 1084 / 14.18
c5315 545.85 81435 6651 / 2.55 6005 / 8.68 8318 / 9.79
c7552 283.48 86251 4580 / 4.75 4500 / 9.4 8053 / 10.71
Table 4.3. Compaction of Robust PDFs ISCAS’85
Circuit CPU [7] NEAT [37] Proposed

sec # tests/ T AV # tests/ T AV
c880 608.4 16652 1573 / 9.24 1286 / 12.95
c1355 3875.26 1110300 9859 / 62.04 12715 / 87.32
c1908 1228.02 355168 8635 / 18.58 13387 / 26.53
c2670 35.93 130626 2822 / 30.42 769 / 169.86
c5315 540.81 342117 4247 / 57.78 4553 / 75.14
c7552 277.55 NA 7711 / 34.48 6956 / 39.86
Table 4.4. Compaction of Non-Robust PDFs ISCAS’85
62
Circuit CPU [3] [3] CPU Proposed
sec # tests/ T AV sec # tests/ T AV
s298 9.98 65 / 5.28 0.4 58 / 5.91
s344 37.38 102 / 5.99 0.17 88 / 6.94
s349 36.78 102 / 5.99 0.16 85 / 7.18
s382 37.3 107 / 6.23 0.13 97 / 6.87
s386 41.69 123 / 3.35 0.18 113 / 3.65
s400 37.86 103 / 6.43 0.25 96 / 6.9
s444 42.93 113 / 5.18 0.26 96 / 6.10
s526 71.52 133 / 5.21 0.20 117 / 5.93
s641 644.89 183 / 10.6 0.78 170 / 11.41
s713 169.18 95 / 12.46 0.29 83 / 14.26
s820 310.79 252 / 3.88 0.60 219 / 4.47
s832 323.62 256 / 3.84 0.52 223 / 4.41
s953 851.01 383 / 6.13 1.53 354 / 6.63
s1196 2419 544 / 6.58 0.89 500 / 7.16
s1238 2539 533 / 6.7 1.64 482 / 7.44
s1423 23675 4646 / 6.17 76.32 3787 / 7.57
s1488 713.19 402 / 4.66 4.86 343 / 5.46
s5378 13429 975 / 18.95 25.08 884 / 20.90
s9234 49677 1581 / 13.52 63.46 1437 / 14.87
s13207 NA NA 197.12 2287 / 12.04
s38417 NA NA 2571.30 41764 / 14.32
Table 4.5. Comparison of Robust PDF Compaction with [3]: ISCAS’89
63
s298 2.38 31 / 11.74 0.06 29 / 12.55
s344 7.21 52 / 12.57 0.06 44 / 14.86
s349 7.21 52 / 12.61 0.05 44 / 14.90
s382 9.87 59 / 12.44 0.04 54 / 13.59
s386 10.98 67 / 6.17 0.12 64 / 6.46
s400 11.22 60 / 12.55 0.11 57 / 13.21
s444 11.72 61 / 13.32 0.17 57 / 14.26
s526 22.46 79 / 9.11 0.18 78 / 9.23
s641 247.40 132 / 16.90 0.62 110 / 20.28
s713 288.27 129 / 28.15 0.52 112 / 43.94
s820 48.92 104 / 9.46 0.16 95 / 10.35
s832 47.66 105 / 9.48 0.37 95 / 10.48
s953 408.19 209 / 11.28 1.13 193 / 12.21
s1196 667.6 320 / 11.74 3.91 308 / 12.20
s1238 479.59 317 / 11.62 2.91 293 / 12.57
s1423 7315 2115 / 21.37 30.72 1873 / 24.13
s1488 54.47 137 / 13.98 0.68 125 / 15.32
Table 4.6. Comparison of Non-Robust PDF Compaction with [3]: ISCAS’89

sec # tests/ T AV sec tests/ T AV
c880 83.4 3261 / 4.93 40.3 2537 / 6.34
c1355 101.6 7861 / 2.90 78.2 6863 / 3.32
c1908 2288.1 17943 / 6.31 705.3 14062 / 6.94
c2670 69.8 2749 / 5.59 44.7 1581 / 9.71
c3540 NA NA 237.3 1084 / 14.18
c5315 730.2 11058 / 7.36 545.85 8318 / 9.79
c7552 626.1 9751 / 8.84 283.48 8053 / 10.71
Table 4.7. Comparison of Robust PDF Compaction with [3]: ISCAS’85
64
c880 1056.2 1408 / 11.82 608.4 1286 / 12.95
c1355 11281.3 16795 / 66.10 3875.26 12715 / 87.32
c1908 1913.8 19473 / 18.24 1228.02 13387 / 26.53
c2670 73.9 1648 / 79.26 35.93 769 / 169.86
c5315 1265.3 7061 / 48.45 540.81 4553 / 75.14
c7552 589.5 9386 / 29.54 277.55 6956 / 39.86
Table 4.8. Comparison of Non-Robust PDF Compaction with [3]: ISCAS’85
65
Chapter 5
CONCLUDING REMARKS FOR THE DISSERTATION
This dissertation presents three different techniques to help determine circuit

timing characteristics by testing for path delay faults (PDFs). Chapter 2 presented
an improved approach for determining delay values of critical paths by using linear
dependency relationships. Theoretical aspects of delay measurable PDF sensitiza-
tion are extended and results show an increase in the number of MD-PDFs. The
improved measuring techniques and other practical aspects of delay fault testing
are effectively utilized to improve coverage for determining timing characteristics of
critical paths. Experimental results show a significant increase in coverage of critical
paths for most circuits.
Chapter 4 presented an efficient scheme for compact test pattern generation.
The presented approach avoids path enumeration and generates small test sets based
on an implicit framework of PDF selection and removal. The experimental results
demonstrate the effectiveness of the scheme when compared with existing work in
test compaction for PDFs. The compaction rates found by the proposed technique
outperforms all other existing methodologies.
Chapter 3 proposed a novel function-based test generation technique for path
delay faults under the LOC scan architecture. The proposed method uses standard
functional test generation techniques as well as function-based sequential circuit
verification techniques. A path implicit framework and a partitioned Image compu-
tation technique are incorporated into the LOC ATPG procedure to improve ATPG
performance and make the procedure scalable to path intensive circuits.
All three chapters are function-based techniques, therefore they can all be
easily integrated and used together. The compaction methodology presented in
Chapter 4 can easily be adjusted to compact PDFs under the LOC scan architecture
66
by using the appropriate LOC test functions generated in Chapter 3.
67
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73
VITA
Graduate School
Southern Illinois University
EDWARD FLANIGAN Date of Birth: March 12, 1981
5943 S. Arrowhead Ln, Tucson, AZ 85746
Southern Illinois University at Carbondale

Bachelor of Science, Electrical and Computer Engineering, May 2003
Southern Illinois University at Carbondale
Master of Science, Electrical Engineering, May 2005
Dissertation Title:
Scalable Test Generation for Path Delay Faults
Major Professor: Dr. Spyros Tragoudas
Publications:
• E. Flanigan, S. Tragoudas. "Path Delay Measurement Techniques Using Lin-

ear Dependency Relationships", IEEE Transactions on Very Large Scale Inte-
gration Systems 2009 (TVLSI’09).
• E. Flanigan, S. Tragoudas, A. Abdulrahman. "Scalable Compact Test Pattern
Generation for Path Delay Faults Based on Functions", VLSI Test Symposium
2009 (VTS’09).
• D. Jayaraman, E. Flanigan, S. Tragoudas. "Implicit Identification of Non-
Robustly Unsensitizable Paths using Bounded Delay Model", IEEE Interna-
tional Test Conference 2008 (ITC’08).
• E. Flanigan, A. Abdulrahman, S. Tragoudas. "Sequential Path Delay Fault
Identification Using Encoded Delay Propagation Signatures", International
Symposium on Quality Electronic Design 2008 (ISQED’08).
• R. Adapa, E. Flanigan, S. Tragoudas. "A Novel Test Generation Methodol-
ogy for Adaptive Diagnosis", International Symposium on Quality Electronic
Design 2008 (ISQED’08).
74
• D. Jayaraman, E. Flanigan, S. Tragoudas. "Implicit Identification of Non-
Robustly Unsensitizable Paths", Proc. of the 11th WSEAS International Con-
ference on Circuits 2007.
• E. Flanigan, S. Tragoudas. "Enhanced Identification of Strong Robustly
Testable Paths", International Symposium on Quality Electronic Design
2007(ISQED’07).
• R. Adapa, E. Flanigan, S. Tragoudas, M. Laisne, H. Cui, T. Petrov. "Function-
Based Test Generation for (Non-Robust) Path Delay Faults using the Launch-
Off-Capture Scan Architecture", International Symposium on Quality Elec-
tronic Design 2007 (ISQED’07).
• E. Flanigan, R. Adapa, H. Cui, M. Laisne, S. Tragoudas, T. Petrov. "Function-
based ATPG for Path-Delay Faults using Launch-off-Capture Scan Architec-
ture", International Conference on VLSI Design 2007 (VLSID’07).
• E. Flanigan, T. Haniotakis, S. Tragoudas. "An Improved Method for Iden-

tifying Linear Dependencies in Path Delay Faults", International Symposium
on Quality Electronic Design 2006 (ISQED’06).
• E. Flanigan, S. Tragoudas. "A Novel Representation of Path Delay Faults

Using Linear Dependency Relationships", Master’s Research Report, Dept. of
Electrical and Computer Engineering, Southern Illinois University Carbondale
2005.
Manuscripts under review/submission
• E. Flanigan, T. Haniotakis, S. Tragoudas. "Efficient Linear Dependency Iden-

tification in Path Delay Faults", ACM Transactions on Design Automation of
Electronic Systems.
75

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SCALABLE TEST GENERATION FOR PATH DELAY FAULTS

M.S. in Electrical Engineering, Southern Illinois University, 2005

B.S. in Electrical Engineering, Southern Illinois University, 2003

Department of Electrical and Computer Engineering

SCALABLE TEST GENERATION FOR PATH DELAY FAULTS

A Dissertation Submitted in Partial

Fulfillment of the Requirements

for the Degree of

in Electrical and Computer Engineering

Dr. Spyros Tragoudas, Chair

Dr. Dimitri Kagaris

Dr. Ning Weng

Dr. Mohammad Seyeh

Dr. Manoj Mohanty

EDWARD FLANIGAN, for the Doctor of Philosophy degree in ELECTRICAL

AND COMPUTER ENGINEERING, presented on 05/02/2009, at Southern Illinois

TITLE: Scalable Test Generation for Path Delay Faults

MAJOR PROFESSOR: Dr. Spyros Tragoudas

of a circuit. Due to the exponential number of paths in modern circuits a subset

architectures. Experimental results demonstrate the effectiveness of the proposed

2 Identification of Delay Measurable PDFs Using Linear Dependency Rela-

2.2 Previous Work and Rationale . . . . . . . . . . . . . . . . . . . . . 6

2.3 Measurable Path Identification . . . . . . . . . . . . . . . . . . . . 8

2.3.1 Off Input Path Selection . . . . . . . . . . . . . . . . . . . . 11

2.3.2 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4 Advanced Measurement Procedures . . . . . . . . . . . . . . . . . . 18

2.4.1 Off-Input Sub-Path Sensitization . . . . . . . . . . . . . . . 18

2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Function-based ATPG for Path Delay Faults using the Launch-Off-Capture

3.2 Path Implicit Framework and Rationale . . . . . . . . . . . . . . . . 31

3.3 Launch-off-Capture Test Generation . . . . . . . . . . . . . . . . . . 34

3.3.2 LOC ATPG Procedure . . . . . . . . . . . . . . . . . . . . . 36

3.3.3 Details on Computing the Partitioned Image Method . . . . 39

3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2 Function-Based Compaction . . . . . . . . . . . . . . . . . . . . . . 47

4.3 Zdd-Based Path Selection . . . . . . . . . . . . . . . . . . . . . . . 55

4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 57

5 Concluding remarks for the dissertation . . . . . . . . . . . . . . . . . . . 66

2.1 Basis Sizes by Different Methods . . . . . . . . . . . . . . . . . . . . . 22

2.2 Testable Basis Coverage of Critical Paths . . . . . . . . . . . . . . . . 23

2.3 Number of Identified DM-PDFs . . . . . . . . . . . . . . . . . . . . . . 25

3.1 Robust PDF Testability for LOC . . . . . . . . . . . . . . . . . . . . . 41

4.1 Compaction of Robust PDFs in the ISCAS’89 Benchmarks . . . . . . . 58

4.2 Compaction of Non-Robust PDFs ISCAS’89 . . . . . . . . . . . . . . . 61

4.3 Compaction of Robust PDFs ISCAS’85 . . . . . . . . . . . . . . . . . . 62

4.4 Compaction of Non-Robust PDFs ISCAS’85 . . . . . . . . . . . . . . . 62

4.5 Comparison of Robust PDF Compaction with [3]: ISCAS’89 . . . . . . 63

4.6 Comparison of Non-Robust PDF Compaction with [3]: ISCAS’89 . . . 64

4.7 Comparison of Robust PDF Compaction with [3]: ISCAS’85 . . . . . . 64

4.8 Comparison of Non-Robust PDF Compaction with [3]: ISCAS’85 . . . 65

2.1 Validation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Strong Robust PDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Delay Measurable PDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Validated Off-Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 LOC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 LOC Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2 Compaction of a set of PDFs . . . . . . . . . . . . . . . . . . . . . . . 54

Modern circuits contain an exponential number of path delay faults (PDFs).

prevents the use of the enhanced-scan architecture in industrial applications. LOC

second vector V2 is the functional response of the first vector.

applicable to both the traditional enhanced-scan architecture as well as launch-of-

therefore they can all be easily integrated and used together.