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CHAPTER 1 1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure b eing measured and can assume any value in the given range. (b) Digital. An elect ric pulse is produced for every person entering the exhibition using a photoelec tric device. These pulses are counted using a digital circuit. (c) Analog. The r eading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals 1 and 0 corresponding to the switch in the ON or OFF position. These signals are processed using digi tal circuits and the results are displayed using digital display devices. (e) An alog. It receives modulated signals which are analog in nature. These signals ar e processed by analog circuits and the output is again in the analog form. (f) D igital. It has only two possible positions (states), ON and OFF. (g) Digital. An electric pulse is produced for every vote cast by pressing of switch of a candi date. The pulses thus produced for each candidate are counted separately and als o the total number of votes polled are counted. 1.2 (a) (i) S1 OFF OFF ON ON (iii) S OFF ON S2 OFF ON OFF ON Bulb ON OFF Bulb OFF OFF OF F ON (iv) (ii) S1 OFF OFF ON ON S1 OFF OFF ON ON S2 OFF ON OFF ON S2 OFF ON OFF ON Bulb OFF ON ON ON Bulb OFF ON ON OFF (b) (i) S1 0 0 1 1 (iii) S 0 1 S2 0 1 0 1 Bulb 1 0 Bulb 0 0 0 1 (iv) (ii) S1 0 0 1 1 S1 0 0 1 1 S2 0 1 0 1 S2 0 1 0 1 Bulb 0 1 1 1 Bulb 0 1 1 0 (c) (i) AND (ii) OR (iii) NOT (iv) EX-OR

1.3 1 Input A 0 1 Input B 0 0 1 2 3 4 5 t(ms) 0 1 2 3 4 5 t(ms) 1 AND 0 1 OR 0 1 NAND 0 1 NOR 0 1 EX-OR 0 1.4 Inputs A 0 0 1 1 B 0 1 0 1 (a) 1 0 0 0 Outputs of (b) (c) 1 1 1 0 0 0 0 1 (d) 0 1 1 1 The operations performed are (a) NOR (b) NAND (c) AND 2 (d) OR

5 For Fig. 1. NOR (c) NAND (a) Inputs A 0 0 1 1 B 0 1 0 1 (b) AND (d) OR AB 0 0 1 0 AB 0 1 0 0 Output Y 0 1 1 0 (b) EX–OR (c) A Y . 1.8 (a) A 0 1 Y 1 0 (b) A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1 A+B Y 0 1 1 1 1 0 0 0 (c) A 0 0 1 1 B 0 1 0 1 A 1 1 0 0 B 1 0 1 0 1.6 (a) A 0 1 Y 1 0 (b) A 0 0 1 1 B 0 1 0 1 Y 0 1 1 1 AB 1 1 1 0 Y 0 0 0 1 (c) A 0 0 1 1 B 0 1 0 1 A 1 1 0 0 B 1 0 1 0 For Fig.7 (a) NAND.1.6 1.

B 3 .

9 . (b) Repeat part (a) for NAND and NOR ga tes.8 For simplicity. On the other hand in th e negative logic system. the logic system will change from positive to negative and vice-versa. Therefore. if all ones and z eros are interchanged in the truth table of the OR gate. The re sulting truth table is same as that of the OR gate. (a) A + A B + A B = (A + A B ) + A B = A (1 + B ) + A B = A 1 + AB = A + AB = (A + A ) (A + B) = A + B (b) AB + A B + A B = (A + A ) B + A B = B + A B = (B + A ) (B + B ) = A +B (c) A BC + A B C + AB C + ABC = A BC + A B C + AB (C + C ) = A BC + A B C + AB = A BC + A (B + B C) = A BC + A (B + B ) (B + C) 4 1. (a) In the truth table of positive logic AND gate replace all zeros by ones and all ones by zeros. the resulting truth tab le will be same as that of the AND gate. In the positive logic system.(d) \ Y = AB + A B Y = AB + A B = AB ⋅ A B Y = Y = AB ⋅ AB = Y1 ⋅ Y2 where. the lower of the two voltage is designated as 1 and the higher voltage as 0. Similarly. we shall consider 2-input gates. but the results are equally val id for any number of inputs. the higher of the two voltages is designated as 1 and the lower voltage as 0. if 1s and 0s are interchanged. A Y1 Y Y1 = AB and Y2 = AB B Y2 1.

and o ne 3-input OR gate.= A BC + AB + AC = C (A + A B) + AB = C (A + A ) (A + B) + AB = C (A + B) + AB = AB + BC + CA 1. A A B B (i) 5 (ii) . two 2-input AND gates.11 (a) The realization of LHS requires.10 (a) A 0 0 1 1 B 0 1 0 1 AB AB 0 0 1 0 A + A B + AB 0 1 1 1 A+B 0 1 1 1 0 1 0 0 (b) A 0 0 1 1 B 0 1 0 1 AB 0 0 0 1 AB AB AB + A B + A B 1 1 0 1 A +B 0 1 0 0 1 0 0 0 1 1 0 1 (c) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A BC 0 0 0 1 0 0 0 0 AB C 0 0 0 0 0 1 0 0 AB C 0 0 0 0 0 0 1 0 ABC LHS 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 AB 0 0 0 0 0 0 1 1 BC 0 0 0 1 0 0 0 1 CA 0 0 0 0 0 1 0 1 RHS 0 0 0 1 0 1 1 1 1. whereas the realization of RHS requires only one two input O R gate. two inverters.

A B C (i) A B C (ii) 1. three 2-input AND gates and o ne 3-input OR gate. four 3-input AND gates and one 4-input OR gate. whereas the realization of RHS requires only one inverter an d one 2-input OR gate.12 (a) AB + CD = AB + CD = AB ⋅ CD 6 . A A B B (i) (ii) (c) The realization of LHS requires three inverters.(b) The realization of LHS requires two inverters. whereas the realization of RHS requires only three 2-input AND gates and one 3-input OR gate.

(ii) The left hand side of (b) is realizable by two 2-input OR gates followed by a 2-inpu t AND gate. while the right hand side i s realizable by two 2-input NAND gates followed by another 2-input NAND gate.(b) (A + B) (C + D) = ( A + B) ⋅ ( C + D ) = ( A + B) + ( C + D ) (i) The left hand side of (a) can be realized by using tw o 2-input AND gates followed by one 2-input OR gate. 1. while the right hand side is realizable by two 2-input NOR gates fol lowed by another 2-input NOR gate. Hence an OR-AND configuration is equivalent t o a NOR-NOR configuration. This can be proved by making truth table as given below: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 (A B) C 0 0 0 0 0 0 0 1 A (B C) 0 0 0 0 0 0 0 1 7 C) . He nce an AND-OR configuration is equivalent to a NANDNAND configuration. the AND operation is commutative. If A (B = (A B) C. then the AND operation is associative.14 (a) Since A B = B A Therefore.13 (a) A B A B Y C D (i) (b) A B A B Y C D (i) C D (ii) Y C D (ii) Y 1.

. = 0 (iii) Similarly. . . which means A ⋅ ( B ⋅ C ) ≠ ( A ⋅ B) ⋅ C This shows that the NAND operation is not associative. if o ee of the variables are 1. . . The associative property requires (A Å B) Å C = A Å (B Å C) This can be proved by mak ing truth table 1. we prepar e the truth table as given below. therefore.15 (a) Since = A ⋅ B = B ⋅ A . =0 Å1Å0Å0Å0Å. = 0 Å 0 Å 0 Å 0 Å . A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A ⋅ ( B ⋅ C) 1 1 1 1 0 0 0 1 ( A ⋅ B) C 1 0 1 0 1 0 1 1 (b) Since. . By maki ng a truth table similar to the truth table of (a) above we can verify that ( A + B) + C ≠ A + ( B + C ) 1. = 1 Å 0 Å 0 Å . OR operati on is commutative. therefore. A + B = B + A.. . From the Table we observe that the last two co lumns are not identical. then (1 Å 0) Å 0 Å 0 Å . =1 8 . which proves that t he AND operation is associative. which means the EX-OR operation is commutativ e. .. (b) Since. then (since EXOR operation is commutative and associative) (1 Å 1) Å 0 Å 0 Å 0 Å . To verify whether the NAND operation is associative or not. the NOR operation is not associative. The associative property requires A + (B + C) = (A + B) + C w hich can be proved by making the truth table in a way similar to the truthtable of (a) above (c) Since.16 1.Since the last two columns of the truth table are identical. . A + B = B + A . A Å B = B Å A. which means the NOR operation is commutative. Two possible realizat ions are given on page 9: (i) If only one of the variables is 1 and all others a re zero.17 Therefore. the NAND operation is co mmutative. . =1 Å0=1 (ii) If only two of the v les are 1 and all others are zero. then (1 Å 1) Å 1 Å 0 Å 0 Å .

The number of pins = 5 ´ 2 + 2 = 12. The number of pins = 4 ´ 3 + 2 = 14. (c) 7408 is a quad 2-input AND gate. therefore. It is obvious from the above d iscussion that Z = 1. Hence it is a 14 -pin IC. Two pins are left free (NC). (a) 7402 is a quad 2-input NOR gate. (b) 7404 is a hex inverter. (e) 7411 is a triple 3-input AND gate.17 Y AÅBÅCÅD 1. (d) 7410 is a tr iple 3-input NAND gate. The number of pins = 4 ´ 3 + 2 = 14. 1. (h) 7432 is a quad 2-input OR gate. 111 in normal binary ascending order. it is packaged as 14-pin IC. This means there are four identical 2-input NOR gates. 9 . (g) 7427 is a triple 3-input NOR gate. The number of pins = 4 ´ 3 + 2 = 14. Take an N-bit binary num ber bN–1 bN–2 . The number of pins = 3 ´ 4 + 2 = 14. . b2b1b0 and write all combinations from 00 .19 In the same way we can try higher number of ones. (f) 7420 is a dual 4-input NAND gate. 000 to 11 . The number of pins = 3 ´ 4 + 2 = 14. . the four gates requires 3 ´ 4 = 12 pins. Since 12-pin IC package is not use d. Therefore. The number of pins = 2 ´ 6 + 2 = 14. Each gate requires three pins. . . .18 1. Since a logical variable can assume one of the two val ues (0 or 1) the number of possible combinations is 2N.A B C D AÅB AÅBÅC Y AÅBÅCÅD or A B AÅB C D CÅD Fig. if an odd number of variables are 1 and Z = 0 if an even n umber of variables are 1. Two pins are required for the power supply (VCC and GND). . two for inputs and one for output.

1.75V = 1 –1.22 1.23 (a) Yes. (a) (i) 7408 a 7402 Logic Circuit A 0. A B C Y or A B C Logic 1 (b) A B C Y or A B C Logic 0 (c) A B C Y or A B C Logic 1 (d) A B C Y or A B C Logic 0 10 Y Y Y Y pins = 3 ´ 4 + 2 = 14. The number of nd 7432 (ii) 7400 (b) (i) 7432 and 7408 (ii) 1 Logic Circuit B –0.20 1.55V = 0 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 OR Y2 0 1 1 1 1 1 1 1 Output NAND Y3 1 1 1.21 (i) 7486 is a quad EX-OR gate.4V = 0 2V = 0 1 0 1 0 1 0 1 AND Y1 0 0 0 0 0 0 1 1 1 1 1 0 NOR Y4 1 0 0 0 0 0 0 0 .

26 1. (a) Active-high (b) Active-low (c) Active-high (d) Active-low (a) Active-low (b) Active-high (c) Active-low (d) Active-high (a ) A B Y C Y = A B A B Y C C = (A B) Y = A + B + C = (A + B) + (C) (c) A B AB Y C AB C Y = A ⋅ B ⋅ C = ( A ⋅ B) + C = ( A ⋅ B) ⋅ C = A⋅ B⋅C (d) A B C 11 Y (C) (b) .24 1.1.27 Yes.25 1. AND — by connecting one of the inputs to logic 0 OR — by connecting one of the inputs to logic 1 NAND — by connecting one of the inputs to logic 0 NOR — by connect ing one of the inputs to logic 1.

1.28 (a) A Å B = A B + A B A Å B = AB + A B = AB + AB = A Å B (b) A ⊕ B = AB + AB A A B = AB + A B = AB + AB (c) B (B

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CHAPTER 2 2.1 (a) 111001 = 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 16 + 8 + 0 + 0 1 = (57)10 (b) 101001 = 1 ´ 25 + 0 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 0 + 8 + 0 + 0 + 1 = (41)10 (c) 11111110 = 1 ´ 27 + 1 ´ 26 + 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 1 ´ 22 + 1 ´ + 0 ´ 20 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10 (d) 1100100 = 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10 (e) 1101.0011 = 1 ´ 23 + 1 ´ 22 + 0 ´ 21 + 1 ´ 20 + 0 ´ 2–1 + 0 + 1 ´ 2–3 + 1 ´ 2–4 = 8 + 4 + 0 + 1 + 0 + 0 + 0.125 + 0.0625 = (13.1875)10 (f) 1010.101 0 = 8 + 2 + 0.5 + 0.125 = (10.625)10 (g) 0.11100 2.2 (a) = 0.5 + 0.25 + 0.125 = (0.875)10 Quotient Remainder 1 0 1 0 0 1 1 Thus (37)10 = (100101)2 Similarly, (b ) (255)10 = (11111111)2 (c) (15)10 = (1111)2 13 37 2 18 2 9 2 4 2 2 2 1 2 18 9 4 2 1 0 0 0 1 0 1

(d) Integer part: (26)10 = (11010)2 Fractional part: 0.25 0.5 ´2 ´2 0.5 1.0 ‾ ‾ 0 1 Ther efore, (26.25)10 = (11010.01)2 (e) Integer part: (11)10 = (1011)2 Fractional par t: 0.75 0.5 ´2 ´2 1.5 1.0 ‾ ‾ 1 1 Thus (11.75)10 = (1011.11)2 (f) 0.1 0.2 0.4 0.8 0.6 0. 2 0.4 0.8 ´2 ´2 ´2 ´2 ´2 ´2 ´2 ´2 0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6 ‾ ‾ ‾ ‾ ‾ ‾ ‾ ‾ 0 0 0 1 1 2 = (0.00011001)2 The process may be terminated at the required number of signif icant bits. 2.3 (a) 1 1 1 1 0 0 ¬ Carry 1 1 0 1 0 +1 1 1 1 0 Final carry (b) 1 1 + 1 0 Final carry 2.4 (a) 01000 –01001 1 0 1 0 1 1 0 0 1 0. 1. 0. 1 1 0 0 1 1 0 ¬ Carry 0 0 1 1 01000 + 10111 (2’s complement) 11111 Since the MSB of the sum is 1, which means th e result is negative and it is in 2’s complement form. 2’s complement of 11111 = 000 01 = (1)10 Therefore, the result is –1. 14

25 = (83.65625)10 01 010 011.1110 +1110.125)10 = (0.001)2 11 011 100.001)2 Therefore .(b) (c) 01100 Þ 01100 –00011 + 11101 (2’s complement) 101001 = + 9 Ignore 0011.010 101 = (123.1001 Þ 0011.000 ‾ 1 Thus (0.6875 Ignore Quotient 375 8 46 8 5 8 2.1)8 = (011011.1011 = + 1.5 (a) Remainder 7 6 5 6 7 46 5 0 5 Therefore.52)8 (334.125)10 = (33.328125)10 10 110 011 = (263)8 = (179)10 15 .6 (a) (b) (c) Therefore.1001 – 001. (249)10 = (371)8 = (011111001)2 Integer part: (27)10 = (33)8 = (01101 1)2 Fractional part: 0.0010 (2’s complement) 10001. (375)10 = (567)8 = (101110111)2 (b) Quotient Remainder 249 31 1 8 3 1 3 7 8 3 0 3 8 3 7 1 (c) 2.101 010 = (334.1)8 = (0. (27.125 ´8 1.52)8 = 3 ´ 82 + 3 ´ 81 + 4 ´ 80 + 5 ´ 8–1 + 2 ´ 8–2 = (220.

2H \ (27.54)1 = (83. (249)10 = (F9)16 (or F9H) = (1111 1001)2 (c) Integer part: Quotient Remainder 27 1 11 16 1 0 1 16 1 B Thus (27)10 = 1BH Fractional part: 0.A8)16 (DC.0010)2 2. (a) 46 = 0111 1001 (Excess-3) (b) 327.328125)10 (c) 1011 0011 = (B3)16 = (179)10 2.0110 0011 1000 (Excess3) 16 .7 (a) 375 16 23 16 1 16 Quotient 23 1 0 Remainder 7 7 1 1 7 7 Therefore.125 ´ 16 2.305 = 00100000.305 = 0101 0011.1010 10 = (DC.89 = 0011 0010 0111.89 = 01 10 0101 1010.A8)16 = 13 ´ 161 + 11 ´ 160 + 10 ´ 16–1 + 8 ´ 16–2 = (220.0101 01 = (53.125)10 = (1B.2.8 (a) 1101 1100.100 0 1001 (BCD) (c) 20.2) 16 = 1B.9 For each decimal digit wri te its natural BCD code (a) 46 = 0100 0110 (BCD) (b) 327.10 For each decimal di git write its 4-bit Excess-3 code.000 ‾ 2 \ (0. (375)10 = (177)16 (or 177H) = (0001 0111 0111)2 (b) Quotient Re mainder 249 15 9 16 15 0 15 16 F 9 Therefore.1011 1100 (Excess-3) (c) 20.65625)10 (b) 0101 0011.125)10 = 0.2H = (00011011.0011 0000 0101 (BCD) 2.

P.11 Starting from 4-bit Gray code given in Table 2. 17 .9) R.P. a 1 is to be attached as MSB and the resulting 8-bit code with even parity will be 1 1010010 Similarly.8 formulate 5-bit Gray code as given below in Table 1. Therefore. we obtain (46 )10 = 111001 (Gray Code) 2. the code for l is 0101110 which has four ones. Table 1 Decimal No.13 (a) Write the 7-bit A SCII code for each character (See Table 2. From Table 2.12 Writing the 6-bit code for each character (See Tab le 2.P. 0 1 2 : : 13 14 15 16 17 18 : : 29 30 31 G4 0 0 0 : : 0 0 0 1 1 1 : : 1 1 1 G3 0 0 0 G2 0 0 0 : : 0 0 0 0 0 0 G1 0 0 1 G0 0 1 1 3 1 1 0 0 1 1 Decima l No.14 (a) Count the number of ones for every character from ASCII table and attach a 1 or 0 as the MSB for odd or even number of ones respectively. we obtain 100111 001011 000011 101100 101000 2. which has three ones. 0 1 2 0 : 17 : 30 31 32 33 : 46 : 62 63 G5 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 G4 0 0 0 Table 2 G3 0 0 0 G2 0 0 0 G1 0 0 1 G0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 Similarly. JAIN = 1010010 0101110 101000 0 0101110 1001010 1000001 1001001 1001110 (b) Write the 8-bit EBCDIC code for ea ch character (See Table 2.10) R. For example. Therefore. JAIN = 11011001 01001011 11010111 01001011 110 10001 11000001 11001001 11010101 (c) Write the 6-bit internal code for each char acter (See Table 2.9). JAIN = 101001 011011 100111 011011 100001 010001 0110 01 100101 2. the ASCII code for R is 1010010. a 0 is to be attached as MSB and the resulting 8-bit code with even parity will be 00101110.2. form 6-bit Gray Code as given in Table 2.9) R.

(b) 27 < 130 < 28 Therefore.3.21 Let us consider the BCD code for 9 and f ind out its Hamming code for error correction. 2. 2. R = 1101001 0 = D2 H and l = 00101110 = 2EH for even parity and R = 01010010 = 52H and l = 1 0101110 = AEH for odd parity.7 requires p3 = 1 ® 1 p1 : : : 1 : 1 : 1 2 p2 : : : : : 1 : 1 18 Hamming Code 3 4 5 n1 p3 n2 1 : : 1 : 1 : 1 : : : : : : : 0 0 : : 0 : 0 : 0 6 n3 0 : : 0 : 0 : 0 7 n4 1 : : 1 : 1 : 1 .18 Consider the following examples: (i) 7 0111 Þ 0 111 –3 –0011 + 1100 (1’s complement) 4 10011 1 End-Around Carry (EAC) 0100 = 4 (ii) 3 0011 Þ 0011 –7 – 0111 + 1000 (1’s complement) –4 1011 = –4 in 1’s complement form From the ve examples the rules of subtraction can be summarized as: (a) Add ones compleme nt of the subtrahend to the minuend. 2 . if binary to hexadecimal conver sion is used.7 requires p2 = 1 odd parity for 4.17 In the 8 bit ASCII code with the parity bit. the result is negative and it is in one’s complement format. (b) If a carry is produced. (b) Repeat part (a) for EBCDIC code. Decimal digit 9 Position BCD odd parity for 1. 25 = 32 and 26 = 64.20 132 ´ 7 bits.6. the mini mum number of bits required to encode 56 elements of information is 6. therefore. 8-bit ASCII code for R with odd parity is 01010010 (b) Repeat pa rt (a) for EBCDIC code. the result is positive (d) If the MS B of the sum is 1.7 requires p1 = 1 odd parity f or 2. 2.6. 2. add end-around carry (EAC) (c) If the MSB of the sum is 0. 2. 8 bits are required to encode 130 elements of information.3. 2. the resulting format will be hexadecimal.15 (a) Attach 0 or 1 as MSB to make the number of ones od d.In a similar way parity bit can be attached to every character.5.5. 19 100 ´ 20 ´ 8 bits.16 (a) Since. For example. For example.

Therefore. Decimal digit 0 1 2 3 4 5 6 7 8 9 Position ® 1 p1 1 0 1 0 0 1 0 1 0 1 2 p2 1 0 0 1 1 0 0 1 0 1 Hamming code 3 4 5 n1 p3 n2 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 6 n3 0 0 1 1 0 0 1 1 0 0 7 n4 0 1 0 1 0 1 0 1 0 1 19 . Hamming code for decimal digit 9 is 1 1 1 0 0 0 1. Similarly. Hamming code is determined for each BCD digit and the complete sequence is given below.

i.2) From Eqs. 3.1 (a) The number of covalent bonds breaking away increases with temperature. (3.1) (3.616 I2 = 2.5 (a) The circuit will be under steady state at t = 20ms. whereas at room temperature some of the covalent bonds break away resultin g in small conductivity. This results in a decrease in the mobility and hence resistivity increases with temperature.CHAPTER 3 3.3 From the V–I relation of the diode.e. and hence decreases the mean free path of the free electrons. we obtain I1 » I0 exp (700/hVT) and \ or (b) I2 » I0 exp (750/hVT) I2/I1 = exp (50/2 ´ 26) = 2.. w hich decreases the resistivity of the semiconductor material. V1 = 700 mV Therefore.6% 3. dQ =0 dt 20 ¢ . = 5.73 mV 3. (b) All the covalent bonds are intact at 0 K and hence there are no free charge carr iers.14% 3. V2 = 700 + 36 = 736 mV Percentage change = 736 − 700 × 100% 700 (3.616 ´ 2 = 5.1) and (3. whereas in a metal an increase in the temperature results in a greater thermal motion of the ions.2). we obtain I1 » I0 exp (V1/hVT) and I2 = 2I1 » I0 exp (V2/hVT) 2 = exp (V2 – V1/hVT) or (b) V2 – V1 = hVT 1n 2 = 2 ´ 26 ´ 0.2 (a) Using the V-I relation of the diode.4 I2 = 10 = e {(V2 – V1)/2 ´ 26} I1 or V2 – V1 = 52 1n 10 = 119.693 mV » 36 mV Since.232 mA Percent change = 5. 232 − 2 × 100% 2 = 161.

The recovery Vi V1 = 0V 0 -V2 = -5V Vd 0 0 1.V1 R = 10 = 1mA 10 Q =I t Q = 1 ´ 10–6 ´ 10–3 = 10–9 C (b) The diode will turn off when excess minority charge has been removed.5 ´ 10–9 e– Se Q = iven below.099 ms (c) The various waveforms are g ime cons an R = RCO = 10 ´ 103 ´ 10 ´ 10–12 = 0.7V 0 -5V Id 1 mA 0 -0. R ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ VR = 5 = 0. we ob ain Q = – 0.5 ´ 10–9 0 for cu -off \ = 1.099 ms 21 R ¤ ¤ ¤ ¤ ¤ ¤ ¤ £ differential equation is dQ Q + = − 0. ¤ ¤ ¤ .5 mA Excess Q Minori y Charge ∴ I1 ≈ Since. 5 mA R 10 The Solving his wi h ini ial + 1. 5 × 10 −3 dt τ IR ≈ condi ion Q(0) = 10–9 C (par (a)).1 ms 0.

sa (= 0. 1 4. IC is flowing). Then he base and collec or vol ages will be VBE. I may ei her be opera ing in he ac ive region or in he sa ura ion region.e.8 V) and VCE.1 ≈ 2 mA 3 The current IB remains same as in part (a). ⋅ 6 − 0. 1 = 3. sat RB = 10 − 0. he collec or curren IC and he base curren IB are given by IC = and IB = VCC − VCE . If the value of RC used is more than 4.3. sat RC V BB − V BE .. Therefore. 3 127. now IC < hFE IB which means the transistor is certainly operating in the saturation region. Therefore . Therefore. Hence it is conducting in the active region. Le us assume ha he ransis or is opera ing in he sa ura ion region. with VCC = 6V.6 (a) Since he E-B junc ion is forward-biased.1 V) respec ively. 8 = 21 µA 200 = hFE IB = 21 ´ 100 = 2.1 mA Since IC>hFE IB. 33 mA 3 5 − 0. sat RB 5 − 0. ( b) The value of RC required for the transistor to be in saturation is given by I C = VCC − VCE . herefore. 1 kW 2. the transistor will co ntinue to be operating in the saturation region. therefore the transistor cannot be in saturation. let us a gain assume that the transistor is operating in the saturation region. (c) The value of RB required to drive the transistor into saturation is given by IC ≤ h FE × or RB ≤ 100 ⋅ ≤ h FE I B V BB − V BE . sat RC or RC ≥ 10 − 0. sa (= 0. 8 kW 3.7kW. he ransis or is c onduc ing (i.7 kW The value of Rc just sufficient for saturation wi ll be 4.27 kW 22 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ £ ¤ ¤ ¤ ¥ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¦ .7 kW.

sat + RE (IC + IB) = VBB Substituting the values.1 < 100 ⋅ + 0. If a smaller value of RB than the value calculated above is used.8 23 ¤ 5 − 0. VBB < R B VCC − VCE . sat RB ⋅ h FE or. he range of VBB for ac ive region is 0. sat RC ≤ V BB − V BE . sat RC ≥ V BB − V BE .7 (a) For the transistor to be in the cut off region.25 V 3. hFE (min) = R ⋅ V C BB − V BE . we obtain. sat 5 − 0. 1 = 200 ⋅ 1 5 − 0.9 Assume the transistor to be in saturation. the transistor will be driven deeper into saturation. sat + RE (IC + IB) = VCC and RBIB + VBE. sat ⋅ + V BE . Writing KVL equations for the collector and base circuits.3 3.8 For he ransis or o be in sa ura ion ¤ ¤ ¤ ¦ ¦ ¤ ¤ ¤ ¤ ¤ ¢ ¤ ¤ .25 V ( c) The range of VBB for sa ura ion region is VBB ³ 3. 8 = 233. 8 2 100 < 3. 53 IC + 50 IB = 4. RCIC + VCE.5 V < VBB < 3.5 V (b) For active region operation VCE − VCE . sat or.25 V Therefore.27 kW. sat RB ⋅ h FE R B VCC − V CE. 3.The value of RB just sufficient to drive the transistor into saturation will be 127. cut–in 0. sa RC h FE VCC − VCE . the voltage VBB VBE.

A ssuming VBE = 0.11 (a) For the load trans istors IC.7 V in the active region. This helps in improving the switching speed of transistor circuit. the voltage at B will change as soon as Vi changes because of the capacitive voltage divider. IC = 0. gi ven below: C + Vi – Equivalent circuit at the transistor input B RB Ri Ci £ £ . 5 µA 100 The minimum value of Vi required for the load transistors to be in saturation is Vi(min) = 25 ´ 10–3 ´ 10 + 0. 5 mA = 2. 3.096 mA and IB = –6.sat = IB.214 mA Since IB comes out to be negative.43 ´ 10–2 mA and IE .When fast changes occur in Vi.5 mA 2 kW 2.2 Solving these equations.7 or. the voltages at B change with the time constant C i (RB Ri) If a capacitor C is connected across RB.43 ´ 10–2 mA 3.05 V 24 § and 50 IC + 100 IB = 4.8 = 1. KVL for the base circuit will be [RB + (1 + hFE) RE] IB = 5 – 0.sat = 5V = 2. hence the transistor is not in saturation. IB = 8.10 The equivalent circuit at the input of a transistor consists of i nput resistance Ri in parallel with the input capacitance Ci as shown in Fig.43 ´ 10–4 mA IC = hFE IB = 8.

(b) When both the transistors are in saturation.12 (a) When both the transistors are cut off. 042 mA 1 100 hFE IB = 150 ´ 0.13 (a) Assume the transistor to be in saturation. æ VCC ö the voltage at Y will be 0 V. the voltage at Y is 0V. 8 mA 10 = 0. the voltage Vi = VO can be determined using the principle of supe rposition and is given by Vi = VO = = 3. the transistor is definitely in saturation. I B = = 0. IC = 5 = 5 mA. 8 Therefore. Now.(b) Assuming the load transistors to be in saturation the equivalent circuit at their input will be as shown in Fig.042 = 6. if T1 is in saturation and T2 is cut off then IC1 = I1 + I2 (d) V1 0V 0V 5V 5V V2 0V 5V 0V 5V Y 5V 0V 0V 0V It performs NOR operation. 5 − 0.8 5+2 5+2 (c) The base current IB1 = I B2 = 3.8 V (a) (b) Vi 5 kW 0. 3. therefore. and the voltage at Y is 5 V. (a). (b). (c) Assume T1 to be cut off and T2 t o be in saturation. Similarly. 3 mA Since IC < hFE IB.8 V 5 2 ´5+ ´ 0. 25 ¢ ¢ ¢ .3 mA 3. Since T2 is in saturation. there is no current dra wn from the supplies. The currents I1 and I2 will be same ç = è RC ÷ ø and IC2 = I1 + I2.8 V 10 kW Vi 0. 8 − 0.8 V 10 kW 0. which reduces to the circuit shown in Fig.

Therefore.14 The base curren required for each ransis or o be in sa ura ion is 25mA. o al base curren will be 25 ´ 100 mA. RC 3.075 = 6.15 Le T1 be cu -off. Hence.7/4) = 1.075 mA assuming the transistor to be i n saturation. I1 = (5 – 0. 3.(b) When S1 is closed. he o al resis ance in he collec or circui of T2 is RC RC = RC/2 whic h means its collector current increases. This requires the base current to be do ubled for the transistor to remain in saturation. the transistor will be operating in the active region. IC = I + I1 = 5 + 1. he ransis or con inues o remain in sa ura ion. he load ransis ors will no remain in sa ura ion. if we again assume he ransis or o be in sa ura ion. (c) When bo h S1 an d S2 are closed. I C = I + I1 + I2 = 5 + 2 ´ 1.15 Now IC <hFE⋅IB Which means he ransis or no longer remains in sa ura ion. Therefore. i is con duc ing in he ac ive region. 3.075 mA Since IC < hFE ⋅ IB Therefore. he vol age a i s collec or will be VO = 5 – 2 ´ 103 ´ 25 ´ 100 ´ 10–6 =0 Which shows ha i is no possible o have a base cu ren of 25 mA for each of he load ransis or.16 The effective resistance = RC RC = 2 26 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .075 = 7. he circui will be as shown below: VCC RC T1 VCC RC T2 Now. I f his curren flows hrough RC of driver. Therefore. Therefore. Therefore.

From his we see ha when Vi = 0. herefore. for a given value of ID. mA Load curve 4 3 2 1 0 A 0 5 10 B VGS = 5 V 4 V 3 V 2 V 1 V VDS.17 (a) Since VGS = 0. Thus. V 27 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ § ¤ .RC ⋅ CO 2 3. ID on he charac eris ic of Fig. he v ol age. (b) Transis or T2 ac s a s load for T1. Therefore. 3. Since he curren ID is same in bo h T1 and T2.28. VO = 5V VO 0V Therefore. we ge a lo ad curve AB as shown below. herefore. he ime cons an = VDS1 = VDD – VDS2 Take various values of ID and for each ID de ermine VDS2 from he curve of (a). Calcula e VDS1 and loca e a poin corresponding o VDS1. 3. he VDS VS ID charac eris ic will be same as he charac eris ic for VGS = 0 in Fig.41(b). and Vi = 5V. he v-i charac eris ic of he load is ha of par (a). he circui func ions as an inver er. ID.

578 mA Average Power drawn from the supply = VCC ´ Iav = 3. Therefore. the load gate tr ansistors come out of saturation. Therefore .3 (a) Let us consider all the possible cases: Case I A = B = C = D = 0 . 844 + 5. we can consider 28 ¤ ¤ ¤ ¤ ¢ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¢ ¤ . TB. 6 − 1. Alternatively.09 1. I1 = VCC − VO 3.064 The voltage VO and noise margin D1 are given in Table.09 1.015 Load gate transistors not in saturation ’’ ’’ VO 1. 2 = 5.14 1. 14 = = 3. The current drawn from the supply I2 = Average current 3.CHAPTER 4 4. Therefore.22 0. 312 mA 640 I1 + I 2 3. 844 mA 640 RC when the output of the driver is low.135 0. he load ga es are in sa ura ion and T1 and T2 are cu -off. (d) For hFE = 10.04 <1. 2V.578 mW = 16. 6 − 0.077 0. hence Y = Y1 = Y2 = 1 Corresponding to this.6 ´ 4.14V.04 <1. 312 = 2 2 = I av = = 4. The value of noise margin decreases with incre ased N.48 mW 4. VO = 1.1 0. all the transistors TA.984 hFE = 20 Noise Margin D1 0.17 0.055 1. TC. 4. (c) Fan out and noise mar gin increases with increase in hFE.14 1. the fan out of this combination will be 10.997 0. The curren drawn from he su pply. each gate will be able to drive 5 gates. and TD are cut off.055 <1. if N > 7.026 0.05 0.2 (a) & (b) hFE = 10 N 5 6 7 8 9 10 VO 1.106 0.04 Noise Margin D1 0. T1 and/or T2 are in saturation and VO = 0.1 When he ou pu of he driver ga e is high.

he propaga ion delay ime-cons an for a single driver (wi hou wired-logic) is RB æ ç RC + N è ö ÷ ( CO + NCi ) ø where. for low ou pu IL = 5. This will drive the corresponding transistors into saturation and consequentl y Y = Y1 = Y2 will be LOW and hence the load transistors will be cut off.6 ´ 9.4 ng of T2 and 100 W resis or) ins ead es.equivalent collector resistance R¢C = RC RC = RC/2.844 ´ 2 mA Si 2 mA \ Iav = 9. Therefore. 4. The transistor whose input is HIGH will be driven to s aturation forcing the output voltage to LOW.312 ´ pply = 3. there is no problem of fan out. This will lead to a situation similar to that of Case III. which means the base curren t of 5 + 5 load transistors can flow through R¢C and give same output voltage corr esponding to logic 1 as the output voltage of each gate individually while drivi ng 5 load gates. RB is he resis ance in he base circui o f a load ga e. Wi h wire-ANDing.96 mW 4. Ci is he inpu capaci ance of a load ga e.156 mA Power drawn from he su (a) This circui has ac ive pull-up (consis i of passive pull-up RC used in normal RTL ga ¤ ¤ ¤ ¤ ¤ ¢ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¢ ¤ ¤ ¤ ¤ ¢ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¢ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . Case II At least one of the inputs of each gate P and Q are HIG H. W i h load ga es. the pro pagation delay time constant = RC ⋅ 2C O 2 = RC ⋅ CO which is same as he propaga ion delay ime-cons an of a single ga e. (b) Without load gates.156 mW = 32.1) ¤ ¤ ¤ ¤ When he ou pu is high. he curren milarly. The s a e of ransis or T2 29 drawn from he supply is IH = 3. Theref ore. the fan out is 10. Consequently. Case III At least one of the inputs to gate P is HIGH and C = D = 0. he imecons an will be æ RC RB ç 2 + N è ö ÷ (2 CO + NCi ) ø (see Prob. Y = Y1 = Y2 will be L OW and this situation is similar to that of Case II. Case IV A = B = 0 and at le ast one of the inputs to gate Q is LOW. N is he number of load ga es.

6 V) 640 W 450 W IB 100 W T2 IO 450 W/N P VBE. The ou pu vol age VO will be HIGH. i.6 ´ç ê2 ÷ ú 100 + 450/ N 1090 ê N è 100 + 450/ N ø ú ë û ¥ ¥ From the above equation. Therefore. we obtain VCC – 1090 IB – VBE. Prob.5.8 0.8 ç 100 + 450/ N ÷ ú 1090 ê N è øú ë û 3 since N is an integer. 2 − 0. 8 100 + 450 / N 2. T2 is in sa ura ion and T3 is cu -off. VCC(3. ¤ ¤ ¤ ¤ ¤ ¤ ¤ § ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ § ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . T 3 will be in sa ura ion. sat − or IB = 450 I – VBE. while T2 is cu -off and VO = VCE. he ou pu circui corresponding o HIGH s a e will be as shown in Fig. 4. we obtain N 30 2.. when he inpu Vi is HIGH. 4.6 0. sat 100 + 450 / N 3. Prob. Therefore. if T3 is cu -off.IB IO öù 30 é 450 æ 2. T2 is in sa ura i on (since T1 is cu -off) and vice-versa.4(a). 6 100 + 45 0 / N = = Writing KVL for the closed path P.6 1 é ê 3.8 V Equivalen inpu circui of load ga es For T2 to be in saturation hFE. (b ) If i is driving N load ga es. 6 − 0. sat = 0 N O 0.4(a) IO = VCC − VCE .e. sa Fig.6 2. N £ ¥ ¥ ¢ ¢ öù 450 æ 2.will always be opposi e o ha of T3.sa 0 V. When Vi is LO W. sat − V BE.

16 = 0.8 V to 0. 7 mA 5 and IB = 0. 2 100 = 32 mA VCC = 3. Neglec ing he base curren s IE2B = I C 3 A = 3. I1 = I2 = .7 – 0. Therefore.54 mA This will increase the fan out to 17.8 + 0. ∴ I1 = 31 ¤ ¢ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . Prob. 4.Since. whe reas T2A and T3B are cu -off. which is very large. 5 = 0.4(b) 4. (c) The relevan por ion of h e circui is shown in Fig.2 V. = IN. 6 = N ⋅ I1 100 + 450 / N The values of I1 for various values of N are given in Table Table N1 30 40 50 60 70 I1 (mA) 750 585 480 403 349 The base curren required for sa ura ion for a normal RTL is abou 300 mA.7 = 1. 4. which means N can be aken as 70. Prob. Here T3A and T2B are in sa ura ion.5 volts. 6 − 0. . .4(b). IO = 2.5 (a) When all the inputs are HIGH the voltage at the point P will be Vp = 0.6 V 100 W T2A IC3A A = 1 T3A T3B T2B 100 W IE2B B = 0 Fig. 2 − 0 . but the noise margin D0 will be reduced from 0. 5 − 1.

6 For a fan out of 10.4 V . This collector current must be same as the collector current of the single gate driving N gates which is given by NIL + I¢1 NIL + I¢1 = N¢IL + MI¢1 VCC(5 V) I¢1 RC T1 Y1 Y P1 IL VCC(5 V) R VCC RC T2 I¢1 Y2 IL P2 VCC R VCC RC TM I¢1 YM IL VCC R PN¢ M Gates wire ANDed Fig.7 32 N¢ Load gates ¢ § ¢ £ £ ¢ ¢ ¢ § ¢ .42 mA. and IB = 0.182 = hFE ´ 0.(b) In this case VP = 0.7 The Fig. Prob .4 or hFE 26 4.82 ´ 10 + 2. N¢ IL + MI¢1 where.7 ´ 3 = 2. Corresponding to this the output voltage a t Y is VCE. Assuming all the other inputs of load gate s to be HIGH.9 V I1 = 0. 4. IL = 0. but the noise margin D0 will be increased to 1. the collector curren t of T1 is given by.2 V. 0. 4.82 mA Assuming T1 to be in saturation.8 + 0. 4. which means the input diodes of all the load gates driven from this combination are conducting. N¢ is the fan out with the wire ANDed connect ion.26 mA This will reduce the fan out to 6. The worst condition corresponds to the situation when the output transistor of one of the driving gates is in s aturation and all others are cut off.sat 0.7 shows the relevant portion of the circuit. Prob.

8 + 0. the i nput diodes will be nonconducting. sat + VD + V BE.16 = 1.7 V in active region. 7 − 0. sat = 0. 82 = N – 2.or N¢ = N – (M – 1) I¢1/IL = N – (M – 1) 2. 093 mA 1. 4. If all the inputs are HIGH. 75 × 31 + 2 V BE 2 . Hence Y = 0.7 + 0. sat = 0. I2 = IB2 = I1 – I2 = 1. wh ich keeps T1. the assumption that T1 is in saturation is inconsistent.7 + 0. VCC – VP = R1I1 + R2IB1 Also I1 = (1 + hFE) IB1 IB1 = 5 − 2.9 If any in put is LOW.3 V The voltage at the collector of T1 = VCE. 182 0.sat R1 + R 2 = 5 − 0. Therefore. then VP = VBE.383 mA Standard load = VCC − V D − VCE. T1 will be in active region and T2 in saturat ion region. Hence T1 is in active region.182 RC 33 IC2 = N ⋅ I L + ¢ ¢ ¢ ¢ £ . sat + VD + VBE.8 = 2.8 = 1.16 mA.2 V Here. In fact when T1 is conducting. the corresponding input diode conducts and therefore. therefore. VP = VBE1 + VD + VBE3. (a ) When all the inputs are HIGH. 78 µA 1. Hence Y = 1. and I1 = 1. VP = 0. 093 N + 2. the input diodes are non conducting.66 (M – 1) 4. sat = 1. This shows that the circuit operates as a NAND gate.7 + 0. IB1 cannot exist.7 + 0. 2 = 1. the voltage drop across R2 will reverse bias the C B junction of T1 and therefore T1 will definitely be operating in active region.7 V Since the voltage at P is higher than the volt age at the collector of T1. sat 5 = 0. 2 × 10 3 = 49.543 – 0.2 + 0. D2.9 V. VBE has been assumed to be 0. 75 + 2 VCC − VCE .8 = 2 . If we ass ume that the transistor T1 is in saturation.543 mA. and T2 cut off.8 When all the inputs are HIGH. sat = 0.

182) ´ 5 = 18.5 – 0.12. (b) Noise margins D1 = 0.5 – 0.2 + 0.625 mW When he ou pu is HIGH. 4.4 V (c) When he ou pu is LOW. 465 = 12 . ac ive + VZ + VBE. N < 36 Therefore.7 + 6. T1 will be conduc ing in ac ive region.8 = 8.543 + 2.6 = – 7. IC2 hFE IB2 or. sa = 0.4 V. VP = 8.9 + 0. he fan-ou of his ga e is 35 which is much higher han he fanou o f he DTL ga e of Fig.9 + 0. Wri ing KVL from VCC o VP .9 = 0.9 =7V The 0 level noise margin = D0 = – [V (1) – (VP – VDg)] = – [15 – (8. VCC – VP = R1 (1 + hFE) IB1 + R2 IB1 34 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¦ ¤ ¤ ¤ ¤ ¤ ¤ ¦ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 1. 045 mW 2 4.093 N + 2. Therefore.2 V (b) When all he inpu s are HIGH.6) = – 3. he powe r P (0) = (I1 + I¢1) VCC = (1.5 + 0. When all he inpu s are HIGH. VP = V (0) + VD = 0.383 or.10 (a) When a leas one of he inpu s is LOW.7 V D0 = –V(1) + (VP – VDg) = – 5 + (2.7 = 0 .2 – 0.465 mW The average power Pav = = P ( 0 ) + P (1) 2 18.182 30 ´ 1.9 V Corresponding o his T1 and T2 will be nonconduc ing.4 – 0. 625 + 5.093 ´ 5 = 5.5 + 6. he power P (1) = I1 ´ Vcc = 1. VP = VBE.For T2 o be in sa ura ion. Zener will be in he breakdown region and T2 in sa ura ion.6 + 0.4 V The 1 level noise margin = D1 = Vg + VZ + Vg – VP = 0.

13 (a) When the output is LOW.8 + 0.0489 = 2.844 mA The current through RC = 14. the temperature sensitivity o f the circuit depends on the temperature sensitivities of D2 and the base emitte r junction of T2. 3 = 0 . Therefore.004 mA IB2 = I 1 – I2 = 2. 8 = 0.004 – 0. I1 = 41 ´ 0.12 The noise margins depend upon temperature because the voltage across a cond ucting diode and VBE are temperature dependent.48 mW 4. Therefore.3 V Cur rent through RB1 = 5 − 2. Since the temperatu re sensitivity of a Zener diode is positive whereas for a forwardbiased diode it is negative. VB1 = 0. therefore.9867) ´ 15 = 44. Base collector junction of T1 is forward biased T2 and T3 are in saturation.844 or. 4. (c) N 76 P(0) = ( I1 + I¢1) ´ VCC = (2. 4 = R1 (1 + h FE ) + R 2 3 ( 41) + 12 = 0.8 + 0.2 = 1V Current through RC2 = 5 −1 = 2.004 + 0.or. I¢1 = 0. In HTL. D2 is replaced by the Zener diode.1 mW Pav = 29. 675 mA 4 VC2 = 0.9867 mA N¢ = N – (M – 1) I¢1/IL = N – 1.16 = 1.95 mA IC2 = 0.0489 mA The current through Zener diode. The input diode and the base emi tter junction of T1 are in polarity opposition. 857 mA 1. 4 35 £ ¢ ¢ ¦ £ ¢ ¢ ¦ ¢ £ .94 ´ 15 = 14.95 N 40 ´ 1. 9867 mA 15 The load current IL = 0.11 IL = 0. therefore.8 = 2. IB1 = VCC − V P 15 − 8. Hence the tempe rature sensitivity of the HTL gate is significantly better than that of the DTL gate. the temperature sensi tivities of these two junctions cancel.94 mA.86 mW P(1) = I1 ´ VCC = 0.7 + 0.03 (M – 4. the temperature sensitivities of Z and the base emitter junction of T2 cancel (their magnitudes are of the same order).9867 + 0.

Moreo ver. therefore. 4. 8 − 0. Since T3 does not turn off (because of storage time) as quickly as T4 turns on .15 (a) If RC4 = 0.532 mA (b) At least one of the inputs is LOW. both T3 and T4 will be conducting simultaneously for some time whic h will cause almost short circuiting of the VCC supply. VB4 = 1 V which makes VBE4 = 0. 9 4 = 1. T3 and T4 are cut off ICC1 = Current through RB1 = 5 − 0. Prob. (ii) When output is in HIG H state. The base current and the collector current of T4 will be come IB4 = = VCC − V BE 4 . 4.025 + 41.36 = 42. ICC(0) = 0.2 + 0. IC4 = 0 Therefore.Since.11 = 1. VB1 = 0. 5 mA 1. 2 = 46 mA 100 = which is very large and will increase significantly the power dissipation.7 = 0.1 4 The current I remains same and it does not affect the fan out of the gate G1.15. T his means T4 will be in saturation and its collector current would be IC4 = VCC − VCE 4 .025 mA (c) The total current will be sum of current through RB1 (as given in (b) part above) and given in Eqs. 4 36 ¢ £ ¢ £ ¢ .10 and 4.385 mA 4. the relevant portion of the circuit with output shorted to ground is sh own in Fig. T4 and D are cut off.9 T2. it is simply a wastage of power. 2 − 0. 7 = 2. 4.sat − V D RC 2 5 − 0 . (c) (i) When output is in LOW state. sat − VCE 3. the change in output from logic 0 to logic 1 will be faster .675 + 2. (b) When the output is i n LOW state. the s horting of output to ground will not have any effect.85 7 = 3. therefore.8 V if the diode D is not present. sat 100 5 − 0.

RC(max) = VCC − VOH (5 − 2. When both the outputs are HIGH or LOW.15 4. which will make the trans istor T4 of the gate whose T3 is cut off to conduct through T3 of the other gate which is in saturation. This will damage the transistor T4 and the diode D.5 mA This large current will continuously be drawn from the supply as long as at leas t one of the inputs is LOW. 1. 7 = 41 mA 100 = Is = IC4 + IB4 = 41 + 2. This continuous current will damage these transistor s.18 The relevant portion of the circuit is giv en in Fig. 4.17. Prob.17 The circuit is shown in Fig. The corresponding current drawn from the power supply w ill be IC4 + IB4 = 41. Prob.4 mA.44kW < RC < 4.56 kW 4. VCC = 5V RC4 = 100 kW RC2 = 1.56 kW RC(min) = Therefore. (i) When the output Y = 1. 2 − 0. 4. while that of th e other gate is cut off.18.5 = 43.and IC4 = VCC − VCE 4 . 4. 6 = 4. the currents drawn from the supply wil l be same as the currents without this connection. 4) × 10 3 kW = I OH + 8 I IH 250 + 8 × 40 VCC − VOL 5 − 0. 4 = = 1. 4. Prob.16 Let the output transistor T3 of one gate is in saturation.4 kW T4 IB4 C2 E2 C3 D Is IC4 E3 Fig. The voltage at Y will be LOW. 44 kW I OL + 8 I IL 16 − 8 × 1. VCC – (5 IOH + 6 IIH) RC VOH 37 ¥ ¢ ¢ £ .sat − V D RC 4 5 − 0.

which gives RC(max) = VCC − VOH ( 5 − 2 . Prob. 4. 4.18 38 RC Load gates IIH IIL IIH IIL IIH IIL IIH IIL IIH IIL IIH IIL Y ¢ . 4 ) × 10 3 kW = 1. Prob.17 VCC = 5 V IOL IOH IOH IOH IOH IOH Fig. 74 kW = 5 I OH + 6 I IH 5 × 250 + 6 × 40 VCC = +5 V RC IIH IOH Output circuit of open collector gate Fig.

159kW < RC < 1.4 V RC(max) = RC(min) = ( 5 − 2.19 Let us assume a supply voltage VCC = + 5V and corresponding VOH = 2. 4.20 7407 is an open collector non inverting buffer with VOH = 30V (maximum). 72 kW 16 − 6 × 1. A value of RC = 1 kW is rea sonable. 6 and Therefore.6 mA 39 ¢ ¢ ¢ ¦ £ . 4. 6 = Therefore.28 kW 4.72 kW and 1.20.159 kW 40 − 7 × 1. which m eans a lamp load along with the necessary supply voltage may be connected as sho wn in Fig. 0. 30 A Lamp 7407 Fig. 4 ≈ 0. it is assumed that only one of the driving gates has its output transistor in saturation while the output transistors of all the oth er gates are cut off. Prob. 4. 4 ≈ 0.20 (a) No (b) No (c) No VCC = +5 V A (d) Yes VCC = +10 V 10 V. 4 ) × 10 3 ≈ 1. 28 kW 7 × 250 + 7 × 40 5 − 0. (i) A LS driving standard devices IOH (ALS) = – 400 mA IOL (ALS) = 8 mA (74 series) IIH (Standard) = 40 mA IIL (Standard) = – 1. Prob. RC should be between 0.74 kW.(ii) When the output Y = 0. 4. VCC − VOL IOL + NIIL RC which gives RC(min) = VCC − VOL I OL + NI IL 5 − 0.21 Let us take ALS devices driving other devices.

22 (b) Y Vn RC2 B4 I E4 RE4 Q C4 hFE I Y P From the equivalent circuit. 3 Since T4 is operati ng as an emitter follower. 4. P RC2 T4 Vn RE4 Q (a) Fig.797 Vn (b) VYP = – (Vn – 0. whereas it is 10 when the output is HIGH. 4. Similarly. 5 (101) V 0. the fan out is 5 (ii) ALS driving ALS IIH (ALS) = 20 mA IIL (ALS) = – 0. Therefore.Here. the nois e voltage present in the output is negligibly small. the fan out is 5. (a) The noise voltage at the collector of T2 = the noise vo ltage at the base of T4. when the output is LOW. 797 Vn .002 Vn Therefore.797 Vn) = – 0 . the complete table can be verified. Prob.998 Vn = (b) VYP = – (Vn – VYQ) = – 0. therefore. 4. we obtain (a) VYQ = R E 4 (1 + h FE ) V R C 2 + (1 + h FE ) R E 4 n 1.22(a). Prob.203 Vn 40 ¢ ¢ ¢ ¢ ¢ ¢ ¢ . and – IOH (ALS) = 10 ´ IIH (Standard) – IOL (ALS) = 5 ´ IIL (Standard) This means. = 1.22 Case I Let T2 be cut off. 4. VYQ = 0.22(b). 1.1 mA Which gives a fan out of 20 when the output is HIGH and 80 when it is LOW. whose equivalent circuit is shown in Fig. if the terminal P is grounded. Therefore. Case II Let T2 be conductin g and T1 be cut off. 5) n = 0. Then the output circuit will appear as shown in Fig. Prob.18 + 0. the fan out is 20. 3 + (101) (1.18 Vn = 0.

5V –0. input/output logic levels of MC10H125 IC. Corresponding to this T4 of G1 is acting as an emitter follower while tha t of G2 is acting as a diode. 4.7V VOL ECL (a) Output logic level voltages of ECL TTL (c) Input logic level voltages of TTL ¢ ¢ ¢ ¢ ¢ ¢ ¢ .75 V) T4 RC2 RE4 Fig. the output transistor will burn out. a nd the input logic levels of TTL are shown in Fig.24 In a TTL gate. 4.. 4. Consequently T4 goes to cut off. When Y1 and Y2 both are sa me.26 41 –1. Similarly.55 V) 5. The relevant portions of the circuits are shown in Fig.2 V supply voltage will appear across the output transistor T4 or T3.8 VIH VIL 0.85 V) T4 Y1 RE4 ( 1.25 Let A = B = C = 0. Y1 = 0 and Y 2 = 1.25. D = 1. VCC = 0 VCC = 0 RC2 ( 0.4 mA is produced.2 V 4. the voltage at the output terminal will be equal to – 0.23 (a) The 5.13V VIH –1. 4. 4.This again shows that the noise voltage is very small between Y and P and hence the terminal P is grounded.48V VIL MC10H125 Translator (b) Input/output logic level volt ages of Translator Fig. a current spike of 41.e.2 V Y2 ( 0. Prob.5V VOL –1. when Y1 = 1 and Y2 = 0 identical situation will prevail making the output 1. 4.2 V supply get s applied to their bases through RC2 and RC1 respectively. the voltage across T4 acting as a diode). and E = 0 Therefore. 4. Prob. Similarly. This confirms that OR operation is perf ormed when the outputs are connected in wired logic. (b) The 5. Prob. Therefore.25 5. Also 5.26 2.26 The output logic levels of ECL.2 V supply will appear across RE4 or RE3 and no damage is caused to the supply and the circuit. it can be proved for all the other cases. the output will be equal to Y1 = Y2. In this when Y1 and Y2 are connected together. Prob. whereas in the case of ECL the change in current is negligibly small when the output changes from LOW to HIGH and vice versa.9V VOH VOH 2V 0. when the output changes from V(0) to V(1).75 V (i.

the output voltage is LOW ( 0V). When T1 is ON .33. we observe. and if the output gets shorted to ground. 4. VIH (Translator) < VOH (ECL) VIL (Translator) > VOL (ECL) which shows that the input of MC10H125 IC is ECL compatible. 4. since T2 is not meant to carry such large currents. it d oes not cause any problem.29 Its operation is given below Inputs A 0 0 VCC VCC B 0 VCC 0 VCC T1 OFF ON OFF ON State of T2 OFF OFF ON ON T3 ON OFF ON OFF T4 ON ON OFF OFF Output Y VCC 0 0 0 42 ¢ § . A B ECL Y Y MC10H125 Translator Fig.From the logic levels. 3. T1 is cut off. 4. whole of VCC will appear across T2 which i s conducting. If the output accidently gets shorted.28 (a) Consider the NMOS in verters shown in Fig. Prob. Now if the output gets shorted to ground. The nor mal current through T1 and T2 is extremely small being the OFF current of either T1 or T2.25.27 The output Y of ECL NO R gate is Y = A + B The output of the Translator circuit is Y and the output of TTL Inverter will be Y = Y. This will cause a relatively very high current to flow through T2 which may damage it. On the other hand when Vi is LOW. 4. 4. Simila rly.27 Y TTL The complete circuit is shown in the above figure. VIH (TTL) < VOH (Translator) VIL (TTL) > VOL (Translator) which shows that the output of the translator is compatible with TTL. (b) Consider the CMOS inverter of Fig. large current from VDD will continuously flow through the load transistor T2 which may damage the load transistor.

Since the output of the translator is compatible with ECL. 43 ¢ ¢ ¢ ¢ ¢ ¢ ¢ .32 When output is HIGH.34. 4 . maximum possible number of A LS gates which can be driven is 140. we observe. it can drive a total of up to 1200 gates. The remaining 14 mA of current can drive 140 74ALS gates. Prob. VOH 3. 4.76V VIH VOL 0.31 54/74 (a) 74HC/74HCT (b) 74 AC/74 ACT 2 15 54H/74H 2 12 54L/ 74L 21 133 54S/ 74S 2 12 54LS/ 74LS 11 66 54AS/ 54ALS/ 74AS 74ALS 8 48 40 240 4. 4.37V VIL 2V 0. therefore. When output is LOW. 4. Prob.30 The fan out is given below.33. Prob.8V CMOS (a) MC10H124 translator (b) Fig. CMO S to ECL interfacing is possible using TTL to ECL translator. Therefore.33 From these logic levels.4. VIH (Translator) < VOH (CMOS) VIL (Translat or) > VOL (CMOS) which shows that the input of the translator is compatible with CMOS. it can drive 20 74AS gates requiring 10 mA of current.33 The output logic levels of CMOS and th e input logic levels of MC10H124 TTL to ECL translator are given in Fig. TTL/CMOS 54/74 54H/74H 54L/74L 54S/74S 54LS/74LS 54AS/74AS 54ALS/74ALS 74HC 400 500 200 1000 4000 2000 400 74HCT 400 500 200 1000 4000 2000 400 74AC 400 500 200 1000 4000 2000 400 74ACT 400 500 200 1000 4000 2000 400 4. 4.34 The output lo gic levels of MC10H125 translator and the input logic levels of CMOS (74HCT & 74 ACT) are shown in Fig.

and 74 AC series VIL = 1.34 From these logic levels.8V VIL 0. we observe.5V VIH 2V 0. 4.VOH 2.5V For these CMOS ICs.35V VIH = 3. Since the input of the translator is compatible with ECL.85V and for CMOS 74 C series VIL = 1. the output of the translator is compatible with thes e CMOS devices. Prob. 4. theref ore.5V VOL MC10H125 Translator (a) CMOS (74HCT & 74ACT) (b) Fig.5V VIH = 3. VIH (CMOS) < VOH (Translator) VIL (CMOS) > VOL (Translator) Therefore. Prob. ECL toCMOS interfacing is possible. VIL (CMOS) > VOL Translator but VIH (CMOS) < VOH (Translator) Therefore. a resistance R and VCC are required to be connected to pull up the voltage at P co rresponding to VOH (Translator) VCC R P MC10H125 Translator (c) Fig.34 CMOS 44 ¢ . For CMOS 74 HC.

2 (a) A 0 0 0 0 0 0 0 B 0 0 0 0 1 1 1 Inputs C 0 0 1 1 0 0 1 45 D 0 1 0 1 0 1 0 Output f 0 0 0 0 0 1 1 (Contd. 5. The circuit diagram of the system is show n in Fig.1(b): S1 S2 L Fig. 5. 5. 5. The resulting circuit will be NAND NAND realization. Prob.1 Let S1 and S2 be the two switches.1(a) Bulb (a) The truth table is given below: S1 0 0 1 1 S2 0 1 0 1 L 0 1 1 0 (b) The logic equation is L = S 1 S2 + S1 S 2 (c) The AND OR realization is give n in Fig.CHAPTER 5 5.1(a): 0 S1 1 L 0 S2 ON = 1 OFF = 0 1 Supply Fig. Prob.1(b) (d) Replace each of the AND gates and the OR gate in the above figure by NAND ga tes.) ¢ ¢ . Prob. 5. Prob.

3 (a) f1 = (A + B + C + D ) ( A + B + C + D) ( A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) ( A + B + C + D) ( A + B + C + D ) f2 = (A + B + C + D) (A + B + C + D ) (A + B + C + D ) (A + B + C + D ) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (b) The K maps for f1 and f2 are given in Fig. T he minimized expressions are: CD AB 00 00 01 11 10 0 0 0 0 (a) Fig. The simplified expression is f = BC + BD CD AB 00 00 01 11 10 1 1 1 (a) Fig. 5. 5.(Contd.3(a) and (b) respectively. Prob. Prob. Prob.) Inputs A 0 1 1 1 1 1 1 1 1 B 1 0 0 0 0 1 1 1 1 C 1 0 0 1 1 0 0 1 1 D 1 0 1 0 1 0 1 0 1 Output f 1 0 0 0 0 0 1 1 1 (b) The K map is given in Fig. 5.2 1 1 B 1 BC D (b) BD 01 11 10 B C f 5. 5. Prob.3 46 0 01 0 11 0 0 10 0 CD AB 00 0 0 01 11 10 0 0 0 0 0 0 (b) 0 0 0 01 11 10 ¢ ¢ .2.

5.4(a) 47 ¢ .4 (a) A B C D B C B D A D f A B Fig. Prob. 5. Prob. Prob. B C D A C A B f1 B f2 A B C A B D A B D A B C D A C D Fig.3 (c) (d) (d) Replace all the AND and OR gates in figures (A) and (B) by NOR gates to obta in realizations using only NOR gates. 5. 5.3(c) and (d) for f1 and f2 respectively.f1 = ( B + C + D) ( A + B + C) ( A + B + D) (A + B + D ) (A + B + C ) f2 = (A + C ) (A + B) ( A + C + D ) (B + D ) (c) The OR AND realizations are shown in Fig.

5 48 . 5. 5.5 (a) A C A C D 7410 Y B (b) A B C A B C B C D Y 1/ 3 7427 7427 Fig. Prob. Prob. Realization for (b) requires 7427 – 1 74260 – 1 a total of only two chips.(b) A B C D A B C f A B D A B D Fig. 5.4(b) (c) Realization for (a) requires 7400 – 1 7420 – 1/2 7430 – 1 a total of three chips.

8. Prob.(c) Realization of (a) requires only one chip whereas (b) requires two chips. Prob. 5. 5. Prob.6 5.8 (i) below gives the K map. Prob. 11. 5. 6. 5.7(b) 5. 6 A D 3/4 7402 C D f B Fig. 5. 9.8(i) 49 ¡ C D (A B) CD (A ¤ B) C D (A B) ¢ ¢ ¡ . 14.7(a) (b) f = å m (2.8 (a) Figure Prob. 15) (c) f = A + C A f B Fig. 12. Using offset adjacencies sho wn in the K map. 3.7 (a) CD AB 00 01 11 1 1 10 1 1 1 1 A 00 01 11 10 C 1 1 1 1 1 1 Fig. 5. the expression for f1 can be written as f1 = (C ¤ D) (A ¤ B) + (C ⊕ D ) (A ⊕ B) = (A ⊕ B) ¤ (C ⊕ D) CD AB C D (A ¤ B) 00 01 11 10 1 1 1 1 1 1 1 1 00 01 11 10 Fig. 13. 7. 10.

This realizati on requires only one 7486 IC chip.8(iv). 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 1 E3 0 0 0 0 0 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 Excess 3 E1 1 0 0 1 1 E0 1 0 1 0 1 0 1 0 1 0 ¢ ¢ ¢ . Prob. (b) Its K map is given in Fig.8(ii) f1 Its realization using EX OR gates is given in Fig. 5.9 BCD 0 1 0 0 Truth D 0 0 0 1 0 1 1 0 table of BCD to Excess 3 code converter is given below. Prob. Prob.8 f2 (iv) Here only ten out of sixteen combinations are used and the other six are taken a s don’t care conditions. CD AB 00 00 01 11 10 1 1 1 1 (iii) 1 1 1 A 01 11 1 10 B A B D A C D Fig. 5.8(iii) The minimized expression is f2 = A B + AB D + ACD The realization using NAND ga tes is given in Fig. The K maps for the outputs E0. 5. 5.A B C D Logic 1 Fig. 5. Prob. Pro. The minimized expressions are: E0 = A 50 ¢ ¢ ¢ ¢ ¢ 5. E1. This requires one 7410 chip and one gate of 7 400 chip. 5.9. Prob.8(ii). E2 and E3 are given in Fig.

The minimized expressions are given below.9 E1 = BA + B A E2 = CB A + C A + C B E3 = D + CA + CB The circuit can be drawn us ing NAND gates. A = E0 B = E1 E 0 + E1 E 0 C = E 2 E 1 + E2 E1 E0 + E3 E1 E 0 D = E3 E2 + E3 E1 E0 The circuit can now be drawn using NAND gates.11(c). 5.BA DC 00 1 0 0 1 01 11 1 0 0 1 E0 (a) ´ ´ ´ ´ 10 1 0 ´ ´ BA DC 00 1 0 1 0 01 11 1 0 1 0 ´ ´ ´ ´ E1 (b) 10 1 0 ´ ´ 00 01 11 10 00 01 11 10 BA DC 00 0 1 1 1 01 11 1 0 0 0 E2 (c) ´ ´ ´ ´ 10 0 1 ´ ´ BA DC 00 0 0 0 0 01 11 0 1 1 1 ´ ´ ´ ´ E3 (d) 10 1 1 ´ ´ 00 01 11 10 00 01 11 10 Fig. 5. Prob. 5.11(a). 5. Prob.11(b). 5. and f3 can be drawn using NOR gates. The minimized expression is f 2 = ( A + B + D) ( B + C + D ) ( A + C ) (c) The K map is shown in Fig. Prob. The K maps can then be prepared and minimized. Prob. f2.9.10 Truth table of Excess 3 to BCD converter can be prepared us ing the truthtable of Prob.11 (a) The K map is shown in Fig. The minimized expression is f 3 = ( A + B + C + D ) ( B + C + D) ( A + B + C ) ( A + C + D ) The circuits for f1. The minimized ex pression is f1 = C D = C + D (b) The K map is shown in Fig. 51 ¢ ¢ ¢ ¢ ¢ ¢ ¢ . 5. 5.

.

12 The K map for f1 is shown in Fig. Prob.11 5. 5. 5. the minimized expression for f 2 is f 2 = C E + ABD + ADE + AD E + B CE + CDE + AB E which can be realized using NAND gates.12 and the minimized expression i s f 1 = A BE + AC E + ABD + BC + AB CD E This can be realized using NAND gates.12 ¢ . Prob. Similarly. 5. A = 0 BC DE 00 00 01 11 10 A BE BC 10 1 DE 00 01 11 10 A = 1 AB CDE 00 1 1 1 1 1 1 1 01 11 10 1 AC E 01 11 1 1 1 1 1 ABD BC Fig.CD AB 00 01 11 10 CD AB 00 01 11 0 10 00 01 11 10 0 0 0 0 0 0 (a) CD AB 00 0 0 0 0 0 0 00 01 11 10 0 0 0 0 (b) 0 0 0 01 11 0 10 0 0 00 01 11 10 0 0 0 (c) Fig. Prob.

5. 513(a). Prob. 52 ¢ .13 (a) Its K map is given in Fig.

Prob.14(a) and (b) show the K maps of f1 for NAND and NOR rea lizations respectively. 5. the minimized expressions are obtained which are given below.(a) CD AB 00 00 01 11 10 1 1 01 11 0 1 0 0 1 0 10 1 0 0 Fig. Prob.13(b) (b) The K map is given in Fig. 5.13(a) The minimized expression is Y = AC D + B C D + ACD A C D B C D A C D Y Fig. C D Y C D Fig. Prob. The minimized expressions are f1 = ABC + CD + BD + AD (S OP) and f1 = ( A + B + C ) (C + D) ( B + D) ( A + D) (POS) Circuits using NAND a nd NOR gates can be designed using the above expressions. 5.18 of the book and Y = C D + CD (c) Realization of part (a) requires 2 IC chips (7410) whereas for part (b) one IC chip (7400) only is required. f2 = A C D + BC + AB 53 (SOP) ¢ ¢ .13(c) 5.14 (a) Figure Prob. 5. (b) Similar to part (a ). 5.

15. Prob. Prob.and f2 = ( A + B ) ( B + D ) ( B + C ) ( A + C ) (POS) These equations can be used to design circuits with NAND and NOR gates.15 Its K map and circuit realization are given in Fig. (a) A C (B D) AB CD 00 00 01 11 10 A C (B ¤ D) 1 01 11 1 1 D f1 10 1 A B C AB CD 00 00 01 11 10 10 C A 1 1 f2 1 C D 54 ¡ (b) B 01 11 1 1 1 A 1 1 A(C A (B C) ¢ ¡ D) ¡ . AB CD 00 01 11 10 1 1 ´ (a) Fig.14 1 ´ 1 00 01 11 10 1 1 1 CD 00 01 11 10 ´ 0 0 (b) 0 0 AB 00 0 01 0 11 0 ´ 10 5. 5. 5.

16 Its truth table is given in Table Prob.16.16(b).(c) AB CD 00 00 01 11 10 1 1 01 11 1 1 10 A C A C (B D) B D Fig. 5. AB CD 00 00 01 11 10 1 0 1 0 01 11 0 1 0 1 (a) Fig.16(a).15 f3 A C(B D) 5. 5. from which Po is obtained as Po = AC (B ¤ D) + A C (B D) + A C (B D) + AC (B ¤ D) = (A C) ¤ (B + D) Its realization sing EX OR and EX NOR gates is given in Fig. Prob. 5. Prob.16 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 4 bit word B C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Odd parity bi t PO 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 Even parity bit PE 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 The K map for Po is given in Fig. Prob. 5. Table Prob. Prob. 5.16 55 1 0 1 0 10 0 1 0 B 1 D (b) A C Po ¡ ¡ ¡ ¢ ¡ ¢ ¢ ¡ ¢ . 5.

Its truth table is given in Table Prob. 5.18(b). 5. and Cn – 1 respective ly and Sn.19. These are given in Fig.19 Let the augen d. we can minimize the function us ing 1s which will lead to a circuit realizable by NAND gates. 5. 5.18(a). (b) The K map usin g 0’s is given in Fig.17. The minimized express ion for f1 is f 1 = ABC D E + ABCD F + CEF + A B C DEF The circuit for f1 can be realized using NAND gates. 5. we can minimize using 0’s which will lead to a circuit realizable by NOR gates. Its outputs are S1 (Sum) and C1 (Carry). 5.5. 5. (a) An and Bn are a pplied at the two inputs of first half adder HA – 1. K map is prepared and the circuit is designed. The minimized expression for f2 is f2 = (A + B + C + D + E + F ) ( A + B + D + E + F) ( A + B + C + E + F ) (A + C + D + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + E + F) (A + B + C + D ) (A + B + D + E) (B + C + D + E) (B + C + D + F ) (A + B + C + D) The circuit fo r f2 can be realized using NOR gates. Bn. Similarly. Prob.16. Table Prob. 5. Prob. Similarly.17 (b) PE 5.18 (a) The K map using 1’s is given in Fig.17 From the truthtable given in Prob. Prob. Prob.19(a) An 0 0 1 1 Bn 0 1 0 1 56 S1 0 1 1 0 C1 0 0 0 1 ¢ ¢ ¢ ¢ ¢ . PE = A ⊕ B ⊕ C ⊕ D AB CD 00 00 01 11 10 1 (a) 1 1 1 01 11 1 1 1 10 1 A B C D Fig. addend. and the carry inputs to the full adder be An. and Cn be the sum and carry outputs respectively.

5. Prob.B A CD 00 00 0 01 11 10 1 0 CD 00 1 EF 01 11 10 EF 01 11 10 00 1 1 01 11 10 1 1 AB CDEF CD 00 00 1 01 11 10 1 1 1 1 1 CEF 01 11 10 EF CD 00 01 11 10 00 01 11 10 1 1 EF ABC D E ABCDF Fig.18(a) 0 1 CD 10 0 EF 00 01 11 10 CD 00 0 00 0 0 0 0 01 11 10 0 B A CD 00 00 0 01 11 10 CD 00 00 1 01 11 10 0 0 0 0 0 0 EF 01 11 0 0 0 0 0 0 EF 01 11 0 10 EF 01 11 .

5.10 00 0 01 11 10 Fig.18(b) 57 . Prob.

19(a) Truth table of the full adder using input variables S1. C1.19(b) C1 0 0 1 0 0 1 S1 0 1 0 0 1 0 Cn – 1 0 0 0 1 1 1 Cn 0 0 1 0 1 1 Sn 0 1 0 1 0 1 K maps for Cn and Sn are shown below: Cn – 1 C 1 S1 00 0 1 0 0 01 0 1 11 ´ ´ 10 1 1 Cn – 1 C1 S1 00 0 1 0 1 01 1 0 11 ´ ´ 10 0 1 K map for Cn K map for Sn Cn = C1 + S1 × Cn – 1 Sn = S1 C n 1 + S 1 Cn – 1 = C1 + C2 = S1 Cn – 1 Sn and Cn are g enerated using HA –2 and an OR gate as shown in the block diagram. 58 ¡ ¢ ¢ ¢ ¢ ¢ . and Cn – 1 is given be low: Table Prob. 5. Prob 5.An Bn Cn – 1 HA – 1 C1 S1 HA – 2 C2 S2 = Sn Cn Fig.

13. it is not counted.19(b) OR Cn 5. 5.20 Propagation delay time for Sn = tpd [EX OR(1)] + tpd [EX –OR(2)] = 20 + 20 = 40 ns.(b) An Bn EX–OR(1) S1 EX–OR(2) S2 = Sn C2 C1 AND 2 AND–1 Cn–1 Fig. 5 0 0 0 0 Grouping of two minterms Variables Check for inclusion B C D in groups of 4 0 — 0 0 — 0 1 1 ü ü ü (Contd. 10. A 0 1 4 3 5 6 11 13 14 15 0 0 0 0 0 0 1 1 1 1 Variables B C D 0 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 Check for inclusion in groups of 2 ü ü ü ü ü ü ü Minterm 2 3 4 Table (b) Group 0 Minterms A 0.21 f (A. 4. C. 15) Table (a) Group 0 1 Grouping of minterms according to number of 1’s. 5. 11.) 59 0 — — 0 ¢ ¢ ¢ ¢ ¢ . 1. 3 1. Since the propagation delay time (tpd) of AND–1 is less than the tpd of EX OR(1). 4 1. therefore. 1 0. 5. D) = p M(2. 8. 12) = S m (0. Propagation dealy time for Cn = tpd [EX OR(1) + tpd (AND 2) + tpd(OR) = 2 0 + 10 + 10 = 40 ns. Prob. 3. 14. 7. 6. B. 9.

1. 15 0 0 — — — 1 1 1 Variables Check for inclusion B C D in group of 4 1 1 0 1 1 — 1 1 0 — 1 0 1 1 — 1 — 0 1 1 0 1 1 — ü 2 3 Table (c) Grouping of 4 minterms Group 0 Minterms A 0. 15 A . 11 5. we see that the column for minterms 0 contains only one ´. 5 0 0 Variables B C — — 0 0 D — — Table (d) PI table PI terms Decimal numbers 0 1 ´ ´ 3 ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ ´ Minterms 4 5 6 11 13 14 15 0. 15 14. the minimized function is f (A. ther efore. All the other columns contain 2 or m ore Xs.13 6. we see the minterms that are covered by each prime implicant and find the minimum number of prime im plicants that will cover all the minterms. 15 ABC 14. Therefore. 4. D) = AC + ABD + ABD + B CD + BC D + BCD + ACD There can be other options also. 6 A B Dü B CDü 3. B. A C is an essential prime implicant. 4.13 BC D ü 6. 3 AB Dü 4. 60 ¢ ¢ ¢ ¢ ¢ . 1. 14 11. 11 BC Dü 5. 6 3. C.) Group 1 Minterms A 4. 15 13.5 4. starting from the prime implicant A B D. 1. 5 Ä AC ü 1. Depending upon the prime implicants s elected above.(Contd. 14 ACD ü 11. 15 ü ü ü ü ü ü ü From the PI table. 5 0. 4.

61 ¢ . 13*. 13) Table (a) Grouping o to number of 1’s. 9. 9 2*.5. 3. 9. 13* 11. 11 1. 11 5. D) = Sm (1. 3 8. 13* 9. B. 3. 11 1. f minterms/don’t care terms according Group Minterm/ don’t care term 1 2* 8 s B C 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 n in group of 2 ü ü ü ü ü ü ü ü ü 1 2 3 4 Table (b) Group 9. 11. 9 3. 11. 11 . 5. 5. 11 9. 3 5 9 11 13* 15 A 0 0 1 0 0 1 1 1 1 Variable 0 1 D 1 0 0 1 1 1 1 1 1 Check for inclusio Grouping of 2 minterms/don’t care terms A 0 0 — 0 1 — — 1 1 1 1 Variables B C 0 — 0 0 0 0 1 0 — — 1 — 0 0 1 0 1 0 — 0 1 — D 1 1 1 — 1 1 Check for inclusion in group of 4 ü ü ü Minterms/ don’t care terms 1. 5. 15 13. 9. 15) + d(2. 3. 15 A — — — — 1 1 Variables B C 0 — 0 — — — — 0 — 0 — — D 1 1 1 1 1 1 1 2 There are a total of 5 prime implicants BD . 5 1. 8. and AD from Table (c) and AB C and AB C from Table (b). 15 9. C. 9. 15 1 2 3 ü ü ü ü ü ü Table (c) Group Grouping of 4 minterms/don’t care terms Minterms/ don’t care terms 1.22 f (A. 3 1. 13*. 13* 9. CD. 13* 1.

5. C. 5. 9 ü ´ ´ ´ Ä ü ´ ´ ´ ´ Ä ´ ´ ü ´ ü The essential prime implicants are: CD.Table (d) PI Table PI terms Decimal numbers 1 2* Minterms/don’t care terms 3 5 8 9 11 13* ´ Ä 15 BD 1. Therefor e. B. 9. Except the minterm 3 all the other minterms have heen covered by the essential prime implicatns. 15 ü ABC 2*. and ABC .) 62 of minterms 10 18 24 11 1 1 0 1 1 1 0 1 1 1 1 1 ü ü ü ü ü ü according to number of 1’s 13 21 25 26 15 27 30 31 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 B 1 0 1 1 1 Variables C D 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 E 0 0 1 0 0 0 1 1 1 1 0 1 1 0 1 Check for inclusion in grou ü ü ü ü ü ü ü ¢ ¢ . C. 18 . E) = Sm (8. D) = B D + C D + AD + AB C . 13*. 27. 21. AD. The minimized function is f (A. 9. 11. 9. 9 8. 10. 11 ´ CD 1. 24. 13* ü ´ AD 9. D. 10 0 0 Grouping of 2 minterms B 1 1 Variables C D 0 0 0 — E — 0 Check for inclusion in group of 4 ü ü (Contd. 16. 26. 11. B. B D is to be included in the minimized expression. 3 AB C 8. 30. 25. 3. 13.23 f (A. 15. 31) Table (a) Group 1 Grouping A 8 16 9 1 1 0 1 0 1 0 0 p of 2 ü Minterm 2 3 4 5 Table (b) Group Minterms A 1 8.

24 9. 26 16. 26 24. 24. 26. 27. 26. 11 9. 27 11. 26 18. 9. 15 9. 11. 27 10.) Group Minterm A 8. 11. 9. 15 9. 13 9. 27 26. 26 16.31 30. 26. 25. 25. 24 16. 26. 26 11. 27 9. 27 24. 30 1 1 0 0 — 0 — 1 1 1 0 — 0 1 1 1 — 1 1 B Variables C D 0 0 0 0 — 0 0 1 1 1 0 — 1 1 — — 1 1 1 1 1 E 0 0 0 1 1 1 — 0 0 — 0 on in group of 4 ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü 2 3 4 1 0 — 1 1 1 1 1 — 1 1 1 1 1 1 1 1 1 1 1 25 10. 18. 24. 18. 11 8. 11. 15. 11. 24. 9. 24. 9. 15 11. 27. 11. 18 16. 30. 25 8. 25 8. 31 31 31 31 0 — 0 — — — 1 1 0 — 0 — — — 1 B Variables C D 0 0 0 0 0 0 0 0 — 0 — 0 0 0 0 0 — — — — 63 — 0 — — 0 — — — — — — — 1 1 — 1 1 — — — — 1 1 — — Check for inclusion in group of 8 ü ü ü ü ü 1 1 1 1 1 1 1 — — 1 1 1 1 1 1 1 1 1 1 1 1 ü ü ü ü ü ü 2 3 . 25.(Contd. 26 8. 10. 10. 15. 27 26. 26. 10. 27 13. 31 27. 27. 13. 26. 26 9. 24. 25 24. 15. 11. 15 25. 27 24. 31 — 0 — 0 0 0 0 0 0 — 0 1 0 0 — 1 — 1 1 1 1 — 0 1 1 — Check for cir Table (c) Grouping of 4 minterms Group Minterms A 8. 27 10. 11. 30. 25. 11 8. 27. 11 10. 24. 10. 13 .

Tabe (d) Group 1 Minterms Grouping of 8 minterms A B 1 Variables C D 0 — E — 8, 9, 10, 11, 24, 25, 26, 27 — Tabe (e) PI Table PI terms Decimal numbers 8 Minterms 9 10 11 13 15 16 18 21 24 25 26 27 30 31 Ä 21 AB CDE ü ü 16, 18, 24, 26 ACE ü 9, 11, 13, 15 ABE BDE 11, 15, 27, 31 ABD ü 26, 27, 30 , 31 ü 8, 9, 10, 11, 24, ´ BC 25, 26, 27 ´ Ä ´ ´ ´ ´ ´ Ä ´ ´ ü ´ ´ Ä ´ ´ ü ´ ´ ´ ´ ´ Ä ü ü ü ´ ´ The minimized function is f (A, B, C, D, E) = A B C D E + A C E + A BE + ABD + B C 64

CHAPTER 6 6.1 (a) In the 16:1 multiplexer IC 74150, the data output is inverted input, i.e ., complement of the data input line selected. Since the data output is 1 when t he input variables correspond to decimal numbers 2, 4, 6, 7, 9, 10, 11, 12 and 1 5, therefore, the data input lines corresponding to these decimal numbers are to be connected to logic 0 and the data input lines 0, 1, 3, 5, 8, 13, and 14 are to be connected to logic 1. The circuit is shown in Fig. Prob. 6.1. Logic 0 Logic 1 0 1 2 3 4 5 6 7 16:1 8 9 Multiplexer 10 74150 11 12 13 14 15 G S 3 S2 S1 S0 Logic 0 (MSB) A B C D (LSB) Fig. Prob. 6.1 Y (b) To realize a four variable truthtable or logic expression using an 8:1 multi plexer the truth table is partitioned as shown by dotted lines (Table 6.3). In t his, the inputs A, B, and C are to be connected to S2, S1 , and S0 Table Prob. 6 .1(b) A 0 0 0 0 1 1 1 1 Inputs B 0 0 1 1 0 0 1 1 65 C 0 1 0 1 0 1 0 1 Output Y 0 D D 1 D 1 D D

select inputs respectively. Now, we observe the relationship between input D and output Y for each group of two rows. There are four possible values of Y and th ese are 0, 1, D, and D . These are given in Table Prob. 6.1(b). From this table, we note the output Y for each of the combinations of A, B, and C and then make the connections accordingly. The implementation of this function using a 74152 I C is shown in Fig. Prob. 6.1(b). This IC also has the data output which is compl ement of the data input line selected. Logic 1 0 D 1 2 D Logic 0 3 4 5 6 7 S2 S1 S0 74152 Y A B Fig. Prob. 6.1(b) C 6.2 A 32:1 multiplexer can be designed using two 16:1 multiplexers following any one of the following approaches. (i) A 32:1 multiplexer will have five selectio n lines, say, A, B, C, D, and E, where A is the MSB. If A is connected to the En able input of one of the 16:1 multiplexers, while the enable input of the other multiplexer is connected to A , then for A = 0, the first multiplexer is enabled and for A = 1 the second multiplexer is enabled. Thus for the first 16 of the 3 2 data inputs one multiplexer gives output depending upon the select inputs whil e for the remaining 16 data inputs the other multiplexer gives the output. Now i f the two outputs are ORed together, the system will function as a 32:1 multiple xer. The complete circuit is shown in Fig. Prob. 6.2(i). (ii) Another method can use two 16:1 multiplexers with their select lines connected together. This is f ollowed by a 2:1 multiplexer to select one of the two outputs. The select line o f the 2 : 1 multiplexer is driven from input A. The complete circuit is shown in Fig. Prob. 6.2(ii). 6.3 The truth table of a full adder in given in Table Prob. 6.3. To realize this, using 8:1 multiplexers requires one multiplexer for Sn an d one for Cn output. Assuming 74152 IC, the circuit is shown in Fig. Prob. 6.3. 66

¢

ì ï ï Data í inputs ï ï î G1 E (LSB) D C B 0 1 2 M 1 Y1 15 16 : 1 S3 S2 S1 S0 Output F (A. C. D. Prob. B. E) S3 S2 S1 S0 ì ï Data ï í inputs ï ï î A (MSB) 16 17 M2 18 16 : 1 31 G2 Y2 Fig. Prob. 6. D. E) G3 S3 S2 S1 S0 16 17 18 31 G2 M2 16 : 1 Y2 ì ï Data ï inputsí ï ï î Logic 0 Logic 0 Fig.2(ii) 67 . C. 6. B.2(i) ì ï ï Data í inputs ï ï î G1 Logic 0 B C D E (LSB) 0 1 2 M1 Y1 15 16 : 1 A(MSB) S3 S2 S1 S0 S 0 Output M3 Y 1 2 : 1 F (A.

6. 6.Table Prob.3 68 74152 IC2 Cn S2 S1 S0 S2 S1 S0 74152 IC1 Sn ¢ ¢ ¢ ¢ . Pr ob.3 An 0 0 0 0 1 1 1 1 Inputs Bn 0 0 1 1 0 0 1 1 Outputs Cn–1 0 1 0 1 0 1 0 1 Sn 0 1 1 0 1 0 0 1 Cn 0 0 0 1 0 1 1 1 The gates required for NAND NAND realization are: 4 input NAND gate 1 3 input NA ND gates 5 2 input NAND gates 3 Inverters 3 Logic 1 0 1 2 3 4 5 6 7 Logic 0 An Bn Cn–1 Logic 1 0 1 2 3 4 5 6 7 Logic 0 Fig.

Therefore.5 Table Prob 6.5(i) G3 0 0 0 0 0 0 0 0 1 1 Gray code G2 G1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 G 0 0 1 1 0 0 1 1 0 0 1 69 D 0 0 0 0 0 0 0 0 1 1 C 0 0 0 0 1 1 1 1 0 0 BCD code B 0 0 1 1 0 0 1 1 0 0 A 0 1 0 1 0 1 0 1 0 1 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ .4 The A inputs are applied dire ctly to the adder. the following IC packages will be required: 7420 – 1 7410 – 2 7400 – 1 In c ontrast to four packages required in NAND NAND realization. the circuit functions as a 4 bit adder. 6. Also Cin = 1. when S is in SUB position. the EX OR gates function as inverters. 64444 74444 8 4 4 B3 B2 B1 B0 B Input A3 A2 A1 A0 64748 A input 7 4 8 3 4 bit Adder ADD Cin S SUB VCC C0 S3 S2 S1 S0 6. On t he other hand. The complete circuit is shown below.5 (i) gives the truth table of Gray to BCD code converter. whereas the B inputs are applied through EX OR gates.Therefore. therefore. the realization usin g 8:1 multiplexers require only 2 IC packages. 6. When th e switch S is in ADD position the outputs of the EX OR gates will be same as the B inputs. Tabl e Prob. the circuit adds A to the 2’s complement of B and hence functions as a 4 bit subtractor. Also Cin = 0.

5(ii) G3 0 0 1 1 G2 0 1 0 1 D 0 0 X 1 C 0 1 X 0 B G1 G1 X 0 A G1 ⊕ G0 G 1 ¤ G0 X G1 ⊕ G0 The G3 and G2 are used as the select inputs.) 70 ¢ ¢ ¢ ¢ ¢ ¢ £ £ £ £ . one 7420. 6.6(i) D 0 0 0 0 0 0 C 0 0 0 0 1 1 BCD Inputs B A 0 0 1 1 0 0 0 1 0 1 0 1 a 0 1 0 0 1 0 b 0 0 0 0 0 1 Seven Segment Outputs c d e f 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 g 1 1 0 0 0 0 (Contd. and B o utputs. we can obtain the expressions for the D. The complete circuit can be drawn w hich requires two 74153 packages and one 7486 package. one 7430. Prob 6. 6. These are given in Table Prob. Table Prob.6(i) shows a common anode 7 segment display d evice. C. Prob. 6.(a) For A output (i) When G3 G2 = 00 G1 0 0 1 1 G0 0 1 1 0 A 0 1 0 1 (ii) When G3G2 = 01 G1 1 1 0 0 G0 0 1 1 0 A 0 1 0 1 A = G1 ⊕ G0 (iii) When G3 G2 = 10 G1 1 1 0 0 G0 0 1 1 0 A X X X X A = G1 ¤ G0 (iv) When G3 G2 = 11 G1 0 0 1 1 G0 0 1 1 0 A 0 1 X X A= X A = G1 ⊕ G0 Similarly. 6. and on e 7400 IC packages. Table Prob.6(i) and Fig. 6. It requires one 74154. (b) The complete circuit is shown in Fig.6 The truth table of BCD to 7 segment decoder is given in Table Prob.5 (ii). 6.5(b).

6 (ii) is shown in Fig.6(i) (Contd. Prob. Prob. 6.6(ii) which gives outp uts in terms of A and B inputs for each combination of D and C inputs.6(i).) D 0 0 1 1 1 1 1 1 1 1 C 1 1 0 0 0 0 1 1 1 1 BCD Inputs B A 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 a 1 0 0 0 X X X X X X b 1 0 0 0 X X X X X X Seven Segment Out puts c d e f 0 0 0 0 X X X X X X 0 1 0 1 X X X X X X 0 1 0 1 X X X X X X 0 1 0 0 X X X X X X g 0 1 0 0 X X X X X X Y0 Y1 Y2 Y3 Y4 Y5 G1 G0 74154 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 S3 S2 S1 Y15 S0 Aü ( LSB)ï ï ï ï ï ï Bï ï ï ï ï BCD ï ýoutputs ï ï Cï ï ï ï ï ï ï ï Dï (MSB) ï þ 0 13 4 444 44 2 2 1 3 G G G G Gray code inputs Fig.6 (ii).Table Prob. 6. we can prepare Table Prob. 6. The circu it for generating data inputs for the multiplexers corresponding to Table Prob.5(b) (a) From Table Prob. 6. The ICs required are: 74153 3 1 packag es 2 71 ¢ . 6. 6.

6(ii) D 0 0 1 1 Inputs C 0 1 0 1 a BA b 0 B⊕ A 0 X c Outputs d BA e A A+ B A X f A+B AB 0 X g B A 0 X BA 0 0 X B¤A A X AB 0 X B A+ B B BA A+B AB BA B A B¤A A A Fig. 6.5. Prob. 6.6(ii) (b) The circuit is designed in a way similar to Prob.7408 7432 7404 3/4 package 3/4 package 1/2 package Anode a b c d e f g f e a b g c d DP DP Fig. 6. Prob. 6. The ICs required are: 74154 one package 7420 one package 7410 one package 72 ¡ .6(i) Table Prob.

(d) From the IC packages requirem ents for parts (a). Table Prob. (b). 6. and B inputs are to be applied to the S2.7(a) D 0 0 0 0 1 C 0 0 1 1 0 B 0 1 0 1 0 G3 0 0 0 0 1 G2 0 0 1 1 1 G1 0 1 1 0 0 G0 A A A A A The circuit can now be designed using four 74151A ICs (one for each of the outpu ts). 6.7 (a) is obtained fol lowing the procedure used in Prob. S1. 6. and (c).1(b). we obtain Table Prob. 6. Table Prob.5 (a). The circuit can now be designed using two 74153 ICs and two EX OR (7486) gates. (b) Table Prob.7430 one package 7404 1/6 package (c) The IC 7442 is a BCD to decimal decoder ci rcuit with active low outputs. 6. Table Prob. C.7(b) D 0 0 1 1 C 0 1 0 1 G3 0 0 1 X G2 0 1 1 X G1 B B 0 X G0 A⊕ B A⊕ B A X (c) Following the approach similar to (b). 6. The IC packages required are sa me as in part (b) with 74154 replaced by 7442. 6.7(c) D 0 1 G3 0 1 G2 C 1 G1 B⊕ C 0 G0 A ⊕ B A 73 ¢ ¢ ¢ ¢ ¢ . and S0 select input s respectively. (a) From the truth table. 6. 6. Table Prob.7 T able Prob. The D. 6.5(i) can be rearranged suitably to give the truth table of BCD toGr ay code converter. These outputs are to be connected exactly in the same way as in the case of part (b) realization.7(b) can be obtained from the truth table foll owing the procedure of Prob. Here e ight rows of the truth table are grouped together.7 (c). we observe the savings in hardware when demult iplexers/decoders are used for the realization of multiple output systems.

a nd f3 can be designed following the procedure outlined in Example 6. (b) Using the truth table the circuits for f1.The circuit can now be designed using one 74157 (Quad 2:1 multiplexer) IC and tw o EX OR gates of 7486. of IC packages 74151A – 4.8 The truth table for f1.3. The circuits can now be designed for f1. 7420 – 1 7400 – 3 6. 7486 – 1 75157 – 1. 7404 – 1 74153 – 2. 7486 – 1 7442 – 1. the circ uit can be designed using one BCD to decimal decoder IC 7442 and NAND gates (2 . 4 . f2. (f) The package count for each part are given in Table Prob 6. 5 . (c) The circuit can be designed using one demultiplexer and two 8 input and one 6 input NAND gates. (d) Following the procedure used in Example 6. 6. f2.1. 6.7(d) Part a b c d e No. and f3 outputs is given in Table Prob. The reali zations will require one 16 : 1 multiplexer for each output.7(d) Table Prob.8(ii) for realization using 8 : 1 multiplexers.8(i) D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Inputs C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Outpu ts B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 74 f1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 f2 1 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 f3 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ .8(i) (a ) The truth table is reduced to Table Prob. and f3 outputs using multiplexers and inverters. 6. 6. (e) The minimized expressions are G3 = D G2 = C + D G1 = C B + C B G0 = B A + B A The realization will require eleven 2 input NAND gates. Table Prob. 7430 – 2. f2. and 6 input).

9 75 . and D are used as select inputs S2. and S0 fo r the multiplexer M6. 6 sel ect lines FEDCBA. there are 40 data input lines (I0 through I39). The lower order three select bits C.9 In a 40:1 multiplexer. S1.Table Prob. Prob. The higher order three select bits F. 6. and A are used as S2. I0 – I7 G M1 S2 S1 S0 C B A I8 – I15 S2 S1 S0 G M2 0 1 2 3 4 M6 5 6 7 G S2 S1 S0 Y I16 – I23 G I24 – I31 M3 S2 S1 S0 C B A S2 S1 S0 M4 G C B A (LSB) F E (MSB) D I32 – I39 Enable S2 S1 S0 G M5 Fig. S0 select inputs respectively for 8:1 multiplexers M1 through M5. B. 6. E.8(ii) D 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 f1 A A A A A A A A f2 1 1 0 0 0 A A 1 f3 0 A 1 A A 0 A 0 6. S1. which selects output of one of the multiplexers M1 through M5.

and A. 6.10 76 ¢ ¢ .For example if the select inputs are 011111. B. data input 7 of M2 (I15) will appea r at the output Y.10 The BCD to decimal decoder is to be used as an 1 : 8 dem ultiplexer. Prob. The address inputs for demultiplexers D1 through D6 are C. D is active0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 D X2 X1 X0 (LSB) C B A D1 7442 D X2 X1 X0 0 1 2 3 D6 4 D 7442 5 6 7 8 C B A9 C B A D2 7442 8 9 10 11 12 13 14 15 D X2 X1 X0 ( C B A D3 7442 Enable 16 17 18 19 20 21 22 23 X5 X4 X3 (MSB) X2 X1 X0 D C B A D4 7442 24 25 26 27 28 29 30 31 D X2 X1 X0 C B A D5 7442 32 33 34 35 36 37 38 39 Fig. 6.

Q4 P4 Q3 P3 Q2 P2 Q1 P1 BCD adder #4 C¢¢¢¢ C2 0 BCD adder #3 C¢¢¢ C1 0 BCD adder #2 C¢¢ C0 0 BCD adder #1 C¢0 C–1 144444444444444 2444444444444444 4 3 5 digit output Fig. The higher order three bits of the address X5. 6. The outputs 8 and 9 of D1 through D5 are n ot used in this configuration. 6. This corresponds to out put on line 15 (which is same as the decimal equivalent of 001111). the propagation delay time for the carry to propagate from C–1 t o Cn–1 in the circuit of Fig. For an nbit adder. X4. B. X1. then output 1 of D6 is activated. Therefore. Prob.12 (a) will be n ´ 40 = 40 ns. For example. 6. B. Prob. Prob.12 77 C0 S15–S12 S11–S8 S7–S4 S3–S0 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ . and A select inputs respectively of D6. 6.11. 6. The complete circuit is shown in Fig.10. 6. The lower order three bits of the address X2.11 For the full adder circuit designed u sing half adder circuits shown in Fig. Prob. A select inputs respectively of each decoder ch ip D1 through D5. if the 6 bit select inputs are 001111. and X3 are applied at the C. EX–OR(1) An Bn S1 EX–OR(2) S2 = Sn C1 AND 2 AND–1 Cn–1 Fig. P4 and Q4 are applied at the A and B i nputs respectively of adder # 4 and similarly the other inputs are applied as sh own below. and X0 are applied at the C. which activat es decoder D2 and the output 7 of this decoder goes low. 6.11 C2 OR Cn The propagation delay time for Cn is tpd = tpd [EX OR(1)] + tpd (AND 2) + tpd (O R) = 20 + 10 + 10 = 40 ns This is the propagation delay time for carry to travel one full adder. this carry has to ripple through all the n a dders.12 Let the four dig its BCD numbers be P4P3P2P1 and Q4Q3Q2Q1.low input for demultiplexer function.

6.14 The comparator C1 compares the least significant four b B.13 Its truth table is given in Table Prob.14 78 ¢ 6. 6. Prob. Using pressions given below are obtained. 6. The complete circuit is shown below. A = B. B3 C1 7485 A>B A=B A<B A4 – A7 A>B A=B A<B 7485 A>B A=B A<B B4 – B7 C2 A>B Logic 1 Logic 0 Fig. 6. Its A > ading inputs A0 – A3 B0 – A=B A<B 1 B0 + A1 A0 B 0 + A1 B 1 A = B = A1 B 1 (A0 ¤ B0) + A1B1 (A0 ¤ B0) = ( ¤ B1) A < B = A 1 A 0 B0 + A 0 B1B0 + A 1B1 The complete circuit can be gates.13 Inputs A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 Outputs A=B 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 K maps the minimized ex .1 1 0 0 0 0 1 1 1 1 B1 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 A > B = A0 B A0 ¤ B0) (A1 drawn using its.13. and A < B outputs are connected to the corresponding casc of C2 respectively. Table Prob.

B. and B1) are applied to C.16 The least significant bit (A1) of BCD input is same as the least significan t bit of the output.6. The other three bits (D1. Inputs CIC 1 A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B A B A>B A=B A<B = 1001 = 1011 =1 =0 =1 = 0000 = 0000 =1 =0 =1 = 101 1 = 1101 =1 =0 =1 = 0010 = 0001 =1 =0 =0 = 0010 = 0011 =0 =1 =0 = 0001 = 1000 =0 =0 =1 Outputs A>B=0 A<B=1 CIC 2 A>B=0 A<B=0 CIC 3 A>B=0 A<B=0 CIC 4 A>B=1 A<B=0 CIC 5 A>B=0 A<B=1 A=B=0 CIC 6 A>B=0 A=B=0 A<B=1 6. and A inputs respectively.15 The operation is given below.16. 6. The binary o utput is obtained at B3B2B1B0 outputs as shown in Fig. C1. Prob. 79 ¢ ¢ . D and E inputs are connected to logic 0.

which will disable t he IC1 chip. then E0 of IC2 will be HIGH. whereas. 6.17 The IC 74148 is a priority octal to binary encoder.16 6. This shows that the circuit is a priority encoder. å EVEN output will be 1. A G A G SEVEN ü ï 8 bit odd ý parity word ï þ 74180 H EVEN SODD ODD Logic 1 Logic 0 Fig. 6. then å ODD output will be 1.18 Apply the 6 bit input to A through F inputs and connect the other two inputs G and H to log ic 0. If more than one inputs are given in the same chip. If two inputs are given simultaneously.19 The 7 bit input is applied at A through G inputs and H = 0. The circuit is shown below. Connect EVEN and ODD inputs to logic 1 and 0 respectively.19 80 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ . Prob. If the parity o f the 6 bit word is even. Therefore. these seven bits along with the å EVEN output bit will give a n 8 bit word with odd parity.ì A1 ï BCD ï B1 inputs í C ï 1 ïD î 1 B0 A B C D E G 74184 Y1 Y2 Y3 Y4 Y5 B1 ï Binary ï ý outputs B B3 ï þ 2 ü ï (MSB) Fig. Prob. the highest numbered input will appear in the binar y form at the output. If EVEN and ODD inputs are at logic 1 and 0 respec tively. 6. 6. one of which is in IC1 and the other one in IC2. if the parity of the 6 bit word is ODD. then å EVEN output is 1 if the 7 bit input is even and 0 if the 7 bit inpu t is odd.

6. 6. B0 – B7 SEVEN P1 74180 SODD EVEN B8 – B13 Logic 0 SEVEN P2 74180 SODD G H B0 – B13 EVEN ODD Fig.21 and its operation is explained in the Table P rob. B0 B1 B2 B3 B4 B5 B6 B7 7486 B8 B9 Logic 1 Fig. 6. Prob. 6. 6. Prob. Prob.20 The circuit is shown in Fig. 6. Prob.20.20 and its operation is given in Table Prob.6.20 Parity of B0 – B7 åEVEN EVEN ODD 1 0 P1 åODD 0 1 Parity of B8 – B13 EVEN ODD EVEN ODD åEVE N 1 0 0 1 P2 åODD 0 1 1 0 From the table we see that the parity of B0 – B13 and åODD of P2 is even.21 81 A B C S EVEN D E F 74180 G H EVEN SODD ODD 1 on even parity 15 bit even parity word Logic 1 B14 ¢ . 6.21 The c ircuit is shown in Fig.20 ODD ü ï ý ï þ Table Prob. 6.21.

Table Prob. The circuit is given in Fig. Prob. which drives a BCD to decimal decoder. 6. 82 ¢ ¢ ¢ ¢ ¢ . 6.22 b0 – b 7 SEVEN P1 EVEN ODD b8 b9 – b16 SEVEN P2 EVEN ODD SEVEN P10 EVEN ODD High on EVEN High on ODD b17 b72 – b79 SEVEN P9 EVEN ODD Fig. 6.26 Le t the four BCD digits be ABCD. with A as MSD.26.21 Parity of B0 – B7 EVEN EVEN ODD ODD Parity of B8 – B9 EVEN ODD ODD EVEN Cascading in puts EVEN ODD 1 0 0 1 0 1 1 0 Outputs åEVEN 1 0 1 0 åODD 0 1 0 1 6.25 See Fig. 6. and M4.22 b80 6. Here P1. P2. 6.24 See Fig. Prob.25 6.23. The least significant bits of the BCD digits are applied at the data inpu ts of M1 and similarly higher order bits are applied to M2.23 The circuit is given in Fig. Prob. 6.24 (a and b) 6. M3. 6. and P3 are 9 bit pari ty checkers. Prob. Prob. The sele ct input are fed from the mod 4 counter.

6. 6. Prob.23 (a) VCC VCC Current Limiting resistor VCC BCD input (MSB) ìD ïC í ïB îA 7442 GND 0 1 2 3 4 5 6 7 8 9 Fig.24(a) 83 . Prob.b0 P1 b8 SEVEN b9 P2 b15 SEVEN High on EVEN SODD High on ODD b16 SEVEN P3 b24 Fig.

and 11 B.26. ¢ ¢ ¢ ¢ ¢ ¢ . the inputs required at the rows for each column are as give n in Table Prob.24 0 1 2 3 (LSB) A B C D Enable (logic 0) D1 E F G H D2 0 1 15 Detects 0001 Fig. 6. C. The circuit is to be designed in a way similar to that of Prob. digit A is selected and at the same time anode A1 goes HIGH. 6. and fourth displays in sequen ce. 6. Similarly. Prob. If the clock frequency is sufficiently high. 10. 6. One column must glow at a time in sequence. Seven 5:1 multiplexers and a mod 5 counter will be required for this. and D d igits are displayed respectively on second.25 14 15 Detects 0001111 84 ¢ The multiplexer outputs are decoded by the BCD to 7 segment decoder with active low outputs.27 For R to glow. When the counter output is 00. third. 6. thereby displaying the digit A on the left most 7 segme nt display.27. Prob.(b) +170 V R = 10 kW 0 1 2 3 4 5 6 7 8 9 Anode NIXIE Tube 0 1 2 3 4 5 6 7 8 9 +5V VCC 74141 D C A 1444 24444 4 B 3 BCD Input (b) Fig. In this way each display will be ON for onefourth of the total time. when the counter outputs are 01. the display would appear to be continuous.

6. 6.26 Table Prob. Prob.27 Row/Column ® ‾ 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 2 1 0 0 1 0 0 0 3 1 0 0 1 1 0 0 4 1 0 0 1 0 1 0 5 0 1 1 0 0 0 1 85 ¢ ¢ ¢ ¢ ¢ ¢ .A0 B0 C0 D0 0 1 M1 2 3 S S 1 0 BCD to 7 segment decoder a b c d e f g Buffer inverters 0 1 2 3 4 BCD to decimal decoder A1 B1 C1 D1 0 1 M2 2 3 S S 1 0 A B C (MSB) D A2 B2 C2 D2 0 1 2 M3 3 S S 1 0 A1 A2 A3 A4 A3 B3 C3 D3 0 1 2 M4 3 S S 1 0 Q0 Q1 Q2 Q3 Mod 4 counter Clock Fig.

2 (a) With S = 1 and R = 0. therefore. i.3 R Q Q S Fig. if Qn = 0. Similarly. This makes both the inputs of G2 as 1 giving an output Q = 0.5 (i) When Jn = Kn = 0. the FLIP FLOP is s et irrespective of the S. (b) With S = 0 and R = 1..e. if Qn = 1. That is. if Qn = 1 then Sn = 0. when a clock pulse is applied . 7. 7. Therefore. Therefore.4 is same as that of Fig. the outputs of G3 and G4 are 0 and 1 res pectively. 7. then Sn = Q n and Rn = 0. This results in both the inputs of AND gate G5 to be 1 giving Q = 1. On the other hand if Qn = 0 then Sn = 1 which will ma ke Qn+1 = 1. Now. Therefore. (iv) If Jn = Kn = 1. i. it will go t o set state in this condition when a clock pulse is applied. then the FLIP FLOP is reset following the same logic as discussed in part (a). which makes the lower input of G1 as 0 while the upper one becomes one giving again Q = 1. This means the outputs do not change. Following the above discussion. its output will be 1. and CK inputs. Therefore. Qn+1 = Qn. making this circuit identical to a normal clo cked S – R FLIP FLOP as shown in Fig.4 (a) With Pr = 0. its output Q = 1. Hence.5.3. Now if S = R = 0. then Sn = 1 and Rn = 0 which makes Qn+1 = 1. Qn+1 = Q n.1 When S = R = 0. Prob 7. (iii) If Jn = 0 and Kn = 1 then Sn = 0 and Rn = Qn.e. whatever may be the other input of G3. the outputs Q and Q will not change.CHAPTER 7 7. th e AND gates G5 and G6 are enabled. the inputs and output of G2 remain unaffected. Sn = Rn = 0 and the output Qn+1 = Qn = 1. 7.. Q will be 0 which makes one of the inputs of G3 0. the outputs of the gates G3 and G4 will be 1. (b) If Cr = 0. (c) If Pr = Cr = 1. (ii) When Jn = 1 and Kn = 0. 7. the AND gates are disabled resulting in Sn = Rn = 0. Since one of the inputs of G1 is 0. 86 ¢ ¢ ¢ ¢ ¢ . R. 7. the circuit of fig. Q1 = 1 and Q = 0 in a manner similar to pa rt (a) and also Q and Q will remain unchanged when S and R both are made 0. then Sn = Q n and Rn = Qn. Therefor e. then Sn = 0 and Rn = 1 whi ch will make Qn+1 = 0. Now. we find that th e FLIP FLOP will go to the reset state when a clock pulse is applied. whatever may be the state of the FLIP FLOP. G1 and G2 will act as inverters.3 7.

9 Clock Inpu ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . When a clock pulse is applied. This makes R = Q = 1 and S = Q = 0.7. Y1 = Y2 7.8 Clock Inpu Q2 = Q Ou pu í ìQ îQ Ou pu í ìQ îQ 7. Q and Q will become 0 and 1 respec ively. R = Q = 0 and S = Q = 1 and on 87 ¤ ¤ 7.11 Le Q = 1 and Q = 0.6 Y1 = ( J ⋅ Q ) ⋅ CK = J ⋅ Q ⋅ CK and Y2 = J ⋅ Q ⋅ CK Hence. Now.10 Clock Inpu Ou pu Q 7.7 Q1 = Q and 7.

a clock pulse will make Q and Q 0 and 1 respec ively.applica ion of a clock pulse.14 The charac eris ic able and he ru h able for decoder are given in Table Prob. The K-maps can be prepared and minimized. 7. 7. Qn+1 = Qn. and hence he circui behaves as a ogg le swi ch. when Tn = 1. 7. 7.13 When Q = D = 0. This show ha Q and Q change wi h every clock pulse. Now Q = D = 1 and he nex clock pulse will change he Q ou pu o 1.14 (a). 7. From his able we observe ha when Tn = 0. The minimized expressions a re: 88 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 7. 7.12 The ru h able is given in Table Prob. whereas. Thus. Table Pr ob.14(b). Q and Q become 1 and 0 respec ively.14 (a) CK 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 J 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Charac eris ic able K Qn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q n + 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Tru h able for decoder Y1 Y2 1 X 1 X 1 X 1 X 1 X 1 1 0 X 0 1 X 1 X 1 X 1 X 1 X 1 X 0 1 1 1 0 (b) The exci a ion able and he ru h able for decoder are given in Table Prob . The K-maps for Y1 and Y2 are shown below. he ou p u s change wi h every clock pulse. which give Y1 = Q + CK + J = Q ⋅ J ⋅ CK and Y2 = CK + K + Q = Q ⋅ K ⋅ CK Table Prob.12. Qn+1 = Q n.12 Tn 0 0 1 1 Qn 0 1 0 1 Sn 0 1 1 0 Rn 1 0 0 1 Qn+1 0 1 1 0 7.

7.15(a).1 5(a) Da a inpu D 0 1 0 1 Ou pu Q 0 0 1 1 89 S-R FF inpu s S R 0 1 0 X X 0 1 0 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .14(b) CK 0 0 0 0 1 1 1 1 Exci a ion able D 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 0 1 0 1 0 0 1 1 Tru h able for decoder Y1 Y2 1 X 1 X 1 1 0 X X 1 X 1 X 0 1 1 (c) Using he above me hod. 7. 7. 7.KQ CKJ 00 00 1 01 ´ 11 ´ 10 1 01 1 ´ ´ 1 11 0 ´ 1 0 10 1 ´ 1 1 KQ CKJ 00 ´ 1 1 ´ 01 ´ 1 1 ´ 11 1 1 0 1 10 ´ 1 0 ´ 00 01 11 10 Y 1 = Q + CK + J = Q ⋅ J ⋅ CK (a) Y 2 = CK + K + Q = Q ⋅ K ⋅ CK (b) Y1 = CK + D = CK ⋅ D and Y = CK + D = CK ⋅ D Table Prob. The K-maps f or S and R ou pu s are prepared as shown in Fig. we ob ain Y1 = CK ⋅ T ⋅ Q Y2 = CK ⋅ T ⋅ Q Comple e circui s can be drawn for each of he above cases.15(i) from which we ob ain he minimized expressions for S and R as S = D and R = D and Table Prob. 7.15 (a) The ru h able required for conversion from S-R o D FLIP-FLOP is given in Table Prob. Prob.

7.Q D 0 0 1 0 0 1 1 ´ (a) Q D 0 0 1 ´ 1 1 0 0 (b) Fig.15(c) and he minimized e xpression for D is given by D = JQ + KQ Table Prob. 7. 7.15(c) Da a inpu s J 0 0 1 1 0 1 0 1 K 0 1 0 1 1 1 0 0 Ou pu Q 0 0 0 0 1 1 1 1 D-FF in pu D 0 0 1 1 0 0 1 1 (d) Table Prob.15(b) Da a inpu D 0 1 0 1 Ou pu Q 0 0 1 1 J 0 1 X X J-K FF inpu s K X X 1 0 (c) The required ru h able is given in Table Prob. 7.15 (d) gives he required ru h able from which we ob ain he minimized expressions for S and R as S = T ⋅Q and R =T⋅Q 90 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 7. 7.15(i) (b) The required ru h able is given in Table Prob. Prob.15(b) from which he mini mized expressions are ob ained as J= D and K= D Table Prob.

even if h e swi ch 91 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . K = R 7. if here is any change in D. 7. Prob. as soon as i makes con ac for he firs ime. This means he s a e of he FLIP-FLOP canno change.15(d) Da a inpu T 0 1 1 0 Ou pu Q 0 0 1 1 S S – R FF inpu s R X 0 1 0 0 1 0 X (e) The ru h able can be prepared and expressions for J and K inpu s ob ained. When he clock goes back o 0.18 (a) When he swi ch is in posi ion 1. Pr = 0 and Cr = 1.16 Le he inpu s o he la ch be Y1 and Y2. Therefore. Now. all he o her conversions can be made. While he clock is HIGH. When he clock comes back o 0 from 1. Q becomes 0. 7. while he clock is HIGH.17. Now. if here is an y change in D. if he swi ch is changed over o posi ion 0. hen Y1 = Y2 = 1 which also doe s no affec he ou pu Q. J=K=T Similarly. (ii) When he clock is HIGH: Y1 and Y2 are complemen o each o her and for each valu e of D we find ha he values of Y1 and Y2 do no change. Y1 and Y2 will remain unal ered. Q goes o 1. Case II: Le D = 1. hen Y1 = Y2 = 1 which will no affec he ou pu Q. Q will become 0. Y2 will remain 1 and Y1 changes f rom 1 o 0. (iii) When he clock goes from LOW o HIGH: Case I: Le D = 0 Y1 will remain 1 and Y2 changes from 1 o 0. Now.17 The waveforms ob ained are shown in Fig. 7. Y1 and Y2 will remain u nal ered. 7.Table Prob. (i) When he clock is LOW: Y1 = Y 2 = 1 independen of D inpu and he s a e of he FLIP-FLOP canno change. The minimized expressio ns ob ained are given below: (f) (g) (h) (i) (j) (k) T = J Q + KQ T =D⊕Q D = S + R Q D =T⊕Q T = S Q + RQ J = S. Therefore. Q = 1. Therefore.

he da a is loaded in o he des ina ion FF. 7. When he swi ch is hrown o posi ion 0. if h e delay ime D 2 is more han i akes o change he presen ou pu of he sourc e FF.ype FF will opera e as a posi ive-edge.19 7. A he rising edge of he cl ock CKs. Q = 0 and Q = 1 . 7.21 The waveform a CK will be as shown in Fig. Prob. The s a es of he coun er are 0 0. (b) When he swi ch is in posi ion 1. he swi ch will opera e in he reverse swi ching. Clock CKS D 1 CKD D 2 Fig. This difficul y can be overcome by adding addi ional delay o assure reliable opera ion. he level riggered D. when he swi ch debounces.17 (a) debounces. In fac . Similarly. he ou pu Q will no be affec ed. he opera ion will no be reliable.19.21. Now . 7. he clock skew may viola e h e hold ime requiremen s of he des ina ion FF. 7.20 The waveforms are shown in Fig. 01 and 10. Prob 7. he da a presen a he da a inpu erminal Ds is loaded in o he sourc e FF.19 The clock. CKs and CKD waveforms are shown in Fig.Clock 1 0 0 1 1 2 3 4 5 6 7 8 9 10 11 12 J 0 1 Q 0 1 Q 0 (b) Fig. 7. 92 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 7. Prob. a he firs con ac Q becomes 1.riggered F F. he ou pu s Q and Q do no change. Prob. Now. This means. Prob. When CKD goes HIGH.20.

7. Prob. 7.21 93 .1 Clock pulses 1 0 1 0 1 Q 0 = J1 Q1 0 1 0 2 3 4 5 6 7 J 0 = Q1 Fig.20 Fig. Prob.

e..1(ii).1(ii) 8. I s s a e diagram is shown in Fig.1 (i) When he mode con rol inpu . Q3 FF3 D3 Q2 FF2 D2 Q1 FF1 D1 D0 FF0 Q0 Serial inpu Fig. he circui comes back o i s ini ial s a e . 8. 8.1(i) (ii) When M = 0. 94 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . Le us assume ha all he FLIP-FLOPs are in he clear s a e.e. 8. 8.. The circui effec ively reduces o ha of Fig. Prob. i func ions as a lef shif regis er. M = 1.2. 8. Prob. Prob. This is a righ -shif regis er. Therefore. Th e various ou pu s when clock pulses are applied are given in Table Prob. The circui effec ively reduces o ha of Fig .1(i). Serial inpu D3 FF3 Q3 D2 FF2 Q2 D1 FF1 Q1 D0 Q0 FF0 Fig. 8. 2(b).2(a). i.2 A 5-s age wis ed-ring coun er is shown in Fig. Ta ble Prob. 8. Prob. Prob. all he B AND ga es are enabled and all he A AND ga es are dis abled.2 A he end of clock pulse 0 1 2 3 4 5 6 7 8 9 10 Q4 0 1 1 1 1 1 0 0 0 0 0 Q3 0 0 1 1 1 1 1 0 0 0 0 Ou pu s Q2 0 0 0 1 1 1 1 1 0 0 0 Q1 0 0 0 0 1 1 1 1 1 0 0 Q0 0 0 0 0 0 1 1 1 1 1 0 A he end of he en h clock pulse. i. In his ca se he da a will ge shif ed o he lef direc ion.CHAPTER 8 8. all he A AND ga es are enabled and all he B AND ga es are disabled. Q4 = Q3 = Q2 = Q1 = Q0 = 0. 8. Prob. i is a mod-10 coun er.

he Y ou pu s are don’ care. respec ively. 8. Figure Prob. . Similarly.3 gives he K-map for Y0 . 8.D4 Q4 FF4 Clock Clear D3 Q3 FF3 D2 Q2 FF2 D1 Q1 FF1 D0 Q0 FF0 Q0 Fig. For all he remaining combina ions of Q’s. 8. be he ou pu s corresponding o pulses 0. .3 Q4 0 1 1 1 1 1 0 0 0 0 Q3 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 Q0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 Y2 0 0 1 0 0 0 0 0 0 0 Y3 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Y6 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Y9 0 0 0 0 0 0 0 0 0 1 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . Prob.3. The ru h able for he decoder is given in Table Prob. The minimized expressions are given by Y0 = Q 4 Q 0 Y1 = Q4 Q 3 Y2 = Q3 Q 2 Y3 = Q2 Q 1 Y4 = Q1 Q 0 Y5 = Q4Q0 Y6 = Q 4Q3 Y7 = Q 3Q2 Y8 = Q 2Q1 Y9 = Q 1Q0 0 0 Inpu s Q2 Q1 0 0 0 1 1 1 1 1 0 0 0 Y0 1 0 0 0 0 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 0 0 0 0 Ou pu s Y 4 Y5 0 0 0 0 1 0 0 1 0 0 0 Y7 0 0 0 0 0 0 0 1 0 0 Y8 0 95 ¤ ¤ ¤ Table Prob. . The K-map is o be pre pared for each ou pu . 8. 1. Y1. Prob.2(a) 00000 10000 11000 11100 11110 00001 00011 00111 01111 11111 Fig. 8. 2.2(b) 8. . o he r K-maps can be prepared. .3 Le Y0.

3. Prob. 8. a 4-s age wis ed-ring coun er is required. The required. Q3Q2 Q1Q0 00 00 01 11 10 1 0 0 ´ Q4 = 0 01 ´ ´ 0 ´ 11 ´ ´ 0 ´ 10 ´ ´ ´ ´ Fig. 8. 1 Clock Pulses Q3 Q2 Q1 2 3 4 5 6 7 8 9 10 11 12 13 Q0 Fig. 8. Prob. From he coun sequence we o bserve ha Q0 changes wi h every clock pulse.4 To genera e hese waveforms.4(i) Q3 Q2 f1 Q1 Q0 f2 Q2 f3 Q0 f4 Q3 Q1 Fig. 8.4(ii). 8.4(i).The circui can be drawn using en 2-inpu AND ga es. 8. wavefo rms can be ob ained by using decoders shown in Fig. Prob. 96 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .3 Q4 Q0 00 00 01 11 10 0 ´ ´ ´ 01 ´ ´ ´ ´ 11 0 ´ 0 0 10 0 ´ ´ ´ 8.4(ii) 8.5 The coun sequence is given in Table Prob.ype FLIP-FLOP (FF0) wi h T0 = 1. Prob. This can be ob ained by using a T . The waveforms a he Q ou pu s are shown in Fig.5. 8. Prob. which are des igned in he same way as Prob.

8. Q2 changes whenever Q1 goes from 0 o 1. T0 = T1 = T2 = 1 T0 Clock Q0 FF0 Q0 T1 Q1 FF1 Q1 T2 FF2 Q2 Q2 Fig. T0 = T1 = T2 = T3 = 1 T0 Clock pulses Q0 FF0 A0 T1 Q1 FF1 B0 A1 T2 Q2 FF2 B1 Q2 A2 T3 Q3 FF3 Q0 Q1 B2 Q3 UP/ DOWN Fig. Simila rly. 8. 8. connec ing Q ou pu s o clock inpu s.6 97 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . whereas he AND ga es B are e nabled when UP/DOWN inpu is a logic 0 connec ing Q ou pu s o he clock inpu s . herefore. 8. Prob. The comple e circui is shown in Fig. AND-OR ga es are used b e ween s ages as shown below.6 For a ripple UP coun er Q ou pu s of he preceding s ages are o be connec e d o he clock inpu s of he succeeding s ages. The desired changes in Q2 can be o b ained by using Q1 as he clock inpu for FF2 wi h T2 = 1. The AND ga es A are enabled when UP/ DOWN inpu is a logic 1.Q1 changes whenever Q0 changes from 0 o 1. he desired changes in Q1 will be ob ained. if Q 0 is used as he clo ck inpu for FF1 wi h T1 = 1.5.5 Q2 0 1 1 1 1 0 0 0 Q1 0 1 1 0 0 1 1 0 Q0 0 1 0 1 0 1 0 1 8. Prob.5 Table Prob. Therefore. whereas for a DOWN coun er Q ou pu s are o be connec ed o he clock inpu s. Prob.

8. and ou pu s respec ively. 001. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . he coun sequence will be 000. he ou pu of he la ch con inues o be 0. a 3-inpu l be required o clear he FLIP-FLOPs. 8.7 Pr Q2 FF2 Q2 Pr Q3 FF3 Q3 The prese inpu s are used for asynchronous loading. QD. Prob. he ou pu of he la ch is 0. Prob ha he frequency divisions by 3. Q1. Prob. 8 . 010. T0 = T1 = T2 = 1 T0 Clock pulses Q0 FF0 Cr Q 0 T1 Q1 FF1 Cr Q 1 Fig. 8. I is clear from he waveforms 12 are ob ained a he QC. 100.9. 8. as soon as he coun reaches 101.9 (a) For he divide-by-5 circui . he ou pu of G becomes 0. The relevan por ion of he circui is shown on nex page. . 6. The circui is shown in Fig. he rese ing coun reaches 111. and QA of FLIP-FLOPs is required as soon as he NAND ga e wi h inpu s Q0.D0 D1 D2 D3 Load Pr Q0 FF0 Q0 Pr Q1 FF1 Q1 Fig.6. The o her de ails will be same as in Prob. 000. Therefore. 01 1.9 T 2 Q2 FF2 Cr Q 2 98 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ (b) For he divide-by-7. herefore. A lso CK = 0. When he eleven h clock pulse appears a CK.8 A he end of he en h pulse Q3 = Q1 = 1. and Q2 wil 8. he da a a he D inpu s will be en ered in he FLIP-FLOPs. Now if Q1 or Q3 goes o 0.10 The waveforms are shown in Fig. When load inpu is HIGH. 8. Therefore. Prob. 8. he ou pu of he la ch will go o 1 and normal coun ing will proceed. all he hree FLIPFLOP s mus be cleared.10.

8.11(a) 99 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ sequence when QB = QA = 1 ¤ ¤ ¤ . 8. 8.11(a). Prob. Prob. 8.10 are given below. QD 0 0 0 1 1 1 0 0 0 1 1 1 0 QC 0 0 1 0 0 1 0 0 1 0 0 1 0 QB 0 1 0 0 1 0 0 1 0 0 1 0 0 QA 0 0 0 0 0 0 1 1 1 1 1 1 0 (a) The ÷ 7 coun er is ob ained by ermina ing he coun .Clock 1 pulses 0 1 QD QC 0 1 0 1 QB QA 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Fig. Ou pu QA QB QC QD A inpu 7 Clock pulses B inpu R1 R2 4 9 2 Fig.11 The s a es of he circui of Prob. The circui is shown in Fig.10 8. Prob.

11(b) (c) The ÷ 11 coun er is ob ained by ermina ing he coun sequence as soon as QD = QC = QA = 1. QC.(b) The ÷ 9 coun er is ob ained by ermina ing he coun QA = 1. 8.11(c). Ou pu QA QB QC QD A inpu Clock pulses B inpu 7 4 9 R1 2 R2 Fig. and QA as outputs. 8. we obtain the D OWN counter. The sequence is given in Table Prob.11(c) 8. 8.12 If we use the complements of QD.) ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ sequence as soon as QD = ¤ ¤ ¤ ¤ ¤ .12. Prob. Prob. The circui is shown in Fig. Prob. 8. QB. Ou pu QA QB QC QD A input Clock pulses B input 7 4 9 R1 2 R2 Fig. Prob. 8. QD QC QB QA 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 100 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 (Contd.11(b). The circui is shown in Fig.

the counter is reset as soon as it becomes 1001 0110. Prob.13 Since 128 = 16 ´ 8. The complete circuit is shown below. 8. If two such ICs are cascaded. 8. it becomes a divi deby 100 circuit.13. two IC packages will be required. therefore. Q0 QA Q1 QB Q2 QC Q3 QD QA Q4 QB Q5 QC Q6 QD A input Clock pulses B input A input IC1 7493 R1 R2 B input IC2 7493 R1 R2 Logic 0 Fig. 100 101 QA QB QC A input Clock pulses B input QD A input QA QB QC QD IC1 7490 S1 S2 R1 R2 IC2 7490 S1 S2 R1 R2 B input Fig. To get a divide by 96 counter.14 101 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ .(Contd. Prob. a divide by 16 counter followed by a divide by 8 counter will become a divide by 128 counter. IC 7493 is a 4 bit binary counter .13 Logic 0 8. Prob.14 IC7490 is a decade counter. The resulting circuit is shown in Fig. 8.) QD QC QB QA 0 0 0 0 0 0 1 1 0 1 0 1 8. Therefore.

15. and QA outputs of 7493 are ANDed and used to clear the counter when the count reaches 1101.16 Clock pulses QA 1 2 3 4 5 6 7 8 9 10 11 12 13 QB QC QD Fig. For the mod 6 counter. we have to use 7493 as a mod 13 and 7492 as mod 6 counters.15 8.16 102 ¢ ¢ ¢ ¢ . 8. QC. QA QB QC QD QA QB QC QD A input Clock pulses B input 7493 R1 R2 A input B input 7492 R1 R2 Fig.15 Since 78 = 13 ´ 6. Prob.8. The complete circuit is shown in Fig. therefore. 8. 8. For the mod 13 counter QD. Prob. Prob. Q A output of 7492 is connected to B input and the QD output of 7493 is connected to A input of 7492.

The clearing operation will occu r at the rising edge of the next clock. When the count reaches the maximum value (111 in 4 bit binary and 1 001 in decade counter) its RC output goes HIGH which makes ENP = ENT of IC2 HIGH for one clock cycle advancing its output by 1 and making Q 103 ¢ .18 The counter have states from 0000 to 1100.19 The counter ICI operates as a counter for counting in the UP direction when Cr = L = 1.17 Clock pulses QA 1 2 3 4 5 6 7 8 9 10 11 12 13 QB QC QD RC Fig. The waveforms are 1 Clock pulses QA 2 3 4 5 6 7 8 9 10 11 12 13 14 QB QC QD Cr Fig. Prob.17 8. Prob.8. 8. 8.18 8.

Prob. 8. The circuit is given in Fig. This way the counting will continue. 8. 8.27.20(a) between the QC. Prob.21(a) 104 ¢ ¢ ¢ . When t he output becomes 0. 0010. When the outputs of IC1 and IC2 b oth reach the maximum count. QD outputs and the clear input (with L = 1). the counter is loaded with P inputs which must be PA = PB = PC = PD = 0. 0011. QA +VCC CK UP CK DOWN Cr PA PB PC PD L Borrow 74192 QB QC QD Carry Clock pulses +VCC Fig. 8. whereas only one type of operation is possible in the circuit of Fig. There are two possible operations i n this circuit.20 Alternative I: Connect the circuit shown in Fig . the counter is loaded with preset inputs 0101 and the state s will be: 0101. 8. the counter is cleared. Prob. 8. This will make ENP = ENT of IC3 HIGH and therefore. As soon as the count reaches 1100.20 QC QD (b) Cr L 8.21(b). 8. and 0001. QC QD (a) Fig. 0100. 8.21 For the DOWN counter. After this clock cycle ENP = ENT = 0 f or IC2 and IC1 will go on counting the pulses. the clock pulses are applied at CK DOWN input. Alternative II: Connect the circuit shown in Fig. QD outputs and load (L) inpu t (with Cr = 1). the next clock pulse will be regi stered in this counter and simultaneously IC1 and IC2 will be cleared. Prob.21(a) and waveforms are shown in Fig. RC outputs of both of these ICs will go HIGH.20(b) between QC. Prob.outputs of ICI 0 at the next clock cycle. As soon as the count becomes 1100. Prob.

8. 8. 8. Prob. 8. 8.) ¢ .22(i) from which Table Prob. Prob.22(ii) is obtained to d the FF inputs. Its state table in Table Prob.21(b) 8.22(a). 0 10 Fig.Clock 1 pulses 0 1 QA 0 QB 1 0 QC QD 1 0 1 0 Borrow Fig.22 The is given etermine 1 11 1 0 modified state diagram is given in Fig.22(a) 00 0 0 1 1 01 Table 8.22(ii) X 0 0 Counter State QA QB 0 1 0 1 JA 1 X 105 FLIP FLOP Inputs KA JB X 0 1 X KB X 1 (Contd. Prob.22(i) Next State Present State A B 0 0 1 1 0 1 0 1 X=0 A 1 0 0 1 B 1 0 1 0 A 0 1 1 0 X =1 B 1 0 1 0 Table Prob. 8.

FF0 : J0.22(b) QB QB QB JA FFA KA QA QA 8.) 106 ¢ ¢ ¢ ¢ . K2 J3. 8. The FFs with their inp uts are given as follows. K0 FF1 : J1. 001. Logic 1 JB FFB KB Clock pulses x = 1 UP = 0 DOWN Fig. K1 FF2 : FF3 : J2. Prob.(Contd. 8.24 Sin ce there are ten states.22(ii) X 0 0 1 1 1 1 Counter State QA QB 1 0 0 0 1 1 0 1 0 1 0 1 JA X 0 0 1 X X FLIP FL OP Inputs KA JB 1 X X X 0 1 1 X 1 X 1 X KB X 1 X 1 X 1 This gives and JB = KB = 1 JA = KA = (QB ¤ X) The circuit is shown in Fig. Prob. 011. The unused states are taken as don’t care (X) conditions. The states of this circuit are: 000. 8. K3 The count sequence and the corresponding values of the FF inputs required to get the count sequence are given below. and 100.23 A divide by 5 circuit will give the required input output relationship. it requires four FFs.22(b). The Q2 output will be the required output when the input waveform is used as the clock input. Q3 0 0 Count Sequence Q2 Q1 Q0 0 1 1 0 1 0 J0 X 1 K0 1 X J1 X 0 FF Inputs K1 J2 1 X 1 X K2 X 0 J3 0 0 K3 X X (Contd. therefore. 010.) Table Prob. 8.

Prob. 8.25 107 ¤ ¤ ¤ ¤ ¢ ¤ . Pulses Logic 1 QA ENT ENP QB QC QD 74163 Load Cr Logic 1 Fig. Prob.25. 8. the expressions for FF inputs can be minimized and the minimized e xpressions are: J0 = K0 = 1 J1 = Q1 ⋅ Q0 + Q3 ⋅ Q2 K1 = Q0 J2 = Q1 ⋅ Q0 K2 = Q1 ⋅ Q0 + Q 3 ⋅ Q2 J3 = Q2 ⋅ Q1 ⋅ Q0 K3 = Q2 Using he FLIP-FLOPs and he above expressions.(Contd.) Q3 0 0 0 0 1 1 0 1 1 0 1 0 X 1 FF Inputs K1 X X X X X K3 X X 1 1 1 1 1 0 Count Sequence Q2 Q1 Q0 1 1 1 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 J0 X 1 X 1 X 1 X 1 K0 1 X 1 X 1 X 1 X J1 1 X X 0 1 X J2 X 0 1 X X 0 1 X X X X 0 0 0 1 X K2 0 0 1 X X X X 1 J3 0 0 1 X 0 0 0 0 1 Using K maps. he c ircui can be drawn. 8.25 The circui is given in Fig.

26 (a) Q1 Q1 Q0 Q1 Q0 D1 Q1 FF1 Q1 Y Q0 Q0 X D0 Q0 FF0 Q0 (b) Clock Fig. 8. Prob.8. Prob. 8.26(b) 1/0 01 0/0 00 1/0 (c) Presen S a e Q1 0 0 Q0 0 0 Inpu X 0 1 Nex s a e Q1* 0 0 Q0* 0 1 108 Ou pu Y 0 0 J1 0 0 FF FF1 K1 X X J0 0 1 Inpu s FF0 K0 X X (Con d.) ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .26(a) 0/0 1/1 0/0 11 1/0 10 0/0 Fig.

Prob.27 (a) D1 = Q1 ⊕ X D0 = Q0 ⊕ Q1 Z = Q1 ⋅ X + Q0 109 Q0 X ´ 0 1 0 1 ´ ´ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 8.26(c) Q0 Q0 8.(Con d.) Presen S a e Q1 0 0 1 1 1 1 Q0 1 1 0 0 1 1 Inpu X 0 1 0 1 0 1 Nex s a e Q1* 0 1 1 1 1 0 Q0* 1 0 0 1 1 0 Ou pu Y 0 0 0 0 0 1 J1 0 1 X X X X FF FF1 K 1 X X 0 0 0 1 J0 X X 0 1 X X Inpu s FF0 K0 0 1 X X 0 1 Q1Q0 X 00 01 11 10 0 1 0 0 0 1 ´ ´ ´ ´ Q1Q0 X 00 01 11 10 0 ´ 1 ´ ´ ´ 0 1 0 0 J1 = Q0 X Q1Q0 X 00 01 11 10 0 1 0 1 ´ ´ ´ ´ 0 1 K1 = Q0 X Q1Q0 X 00 01 11 10 0 ´ 1 Y = Q1 J0 = X K0 = X X J1 FF1 K1 Q1 Q1 J0 FF0 K0 Clock Fig.

Prob.28 Presen Q1 0 0 0 0 1 1 1 1 S a e Q0 0 0 1 1 0 0 1 1 Inpu X 0 1 0 1 0 1 0 1 Nex S a e Q1* 0 0 1 0 1 1 1 0 Q0* 0 1 0 1 0 1 1 0 FF1 J1 0 0 1 0 X X X X K1 X X X X 0 0 0 1 J0 0 1 X X 0 1 X X FF inpu s FF0 K0 X X 1 0 X X 0 1 From he s a e diagram.28(a) The circui can be drawn using he above expressions. From he able. X Q1Q0 00 01 11 10 0 0 1 0 1 0 ´ ´ ´ ´ X Q1Q0 00 01 11 10 0 ´ 1 ´ ´ ´ 0 1 0 0 J1 = Q0 X Q1Q0 X 00 01 11 10 0 1 0 1 ´ ´ ´ ´ 0 1 K1 = Q0 X Q1Q0 X 00 01 11 10 0 ´ 1 0 ´ 1 ´ 0 1 ´ K0 = Q1 ¤ X J0 = X Fig. K-maps are prepared for J1. Q0. he ini ial s a e has been assumed as Q1 Q0 = 00 and correspondingly he o her s a es have been assigned. 8. and X as he inpu variables as given below. J0. and K0 wi h Q1. 110 ¤ ¤ (b) The s a e able will be Q1 0 0 1 1 1 1 0 0 Presen S a e Q0 0 0 0 0 1 1 1 1 Inpu X 0 1 0 1 0 1 0 1 Nex S a e Q1* Q0* 0 1 1 0 1 0 0 1 0 0 1 1 0 0 1 1 Ou pu Z 1 0 0 0 1 1 1 1 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 8.Here. s a e able as shown above is prepared and inpu s o FF0 and FF1 are ob ained using he exci a ion able of J-K FF. K1. we ob ain he ou pu sequence as 001110.

and J-K FLIPFLOPs are given in he Table. Prob. 8. 111 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . These are T2 = Q 2 ⋅ Q1 ⋅ Q 0 ⋅ X + Q 2 ⋅ X + Q 0 ⋅ X T1 = Q 0 + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X + Q 2 ⋅ Q1 ⋅ X T0 = Q 0 + Q1 X and Y = Q0 ⋅ X S2 = Q 0 ⋅ X + Q1 ⋅ 2 = Q 0 ⋅ X S1 = Q 0 + Q 2 ⋅ X R1 = Q 2 ⋅ X + Q 2 ⋅ Q 0 ⋅ X S0 = Q 1 ⋅ Q 0 ⋅ X R0 = Q0 and Q0 ⋅ X J2 = Q1 ⋅ Q 0 ⋅ X + Q 0 ⋅ X K2 = X J1 = Q 0 + Q 2 ⋅ X K1 = Q 2 ⋅ X + Q 2 ⋅ X J0 = Q K0 = 1 (a) (b) (c) and Y = Q0 ⋅ X The comple e circui s can be drawn using he above expressions.J0 FF0 K0 Clock X Q0 J1 FF1 Q1 Q0 K1 Q1 Fig.29 The S a e able along wi h he inpu s required for T. From his he simplified expressions for hese inpu s are o b ained using K-maps. S-R.28 (b) 8.

112 .

31 The s a e diagram is given below. J1.31 0/0 011 0/0 0/0 100 1/0 113 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .17 along wi h he inpu s J2.30 Table 8. K2. Prob. 8. and K0 required for h e FFS is given below. K1.8. 1/0 1/0 000 1/0 001 1/1 010 1/0 0/0 1/0 111 1/1 0/1 110 0/0 0/1 101 0/1 Fig. J0. 8. Presen S a e Q2 Q1 Q0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Inpu Nex S a e Ou pu X Q2* Q1* Q0* Y J2 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 X X K2 X X X X X X X X 1 0 FF inpu s J1 K1 J0 1 0 0 1 X X X X 1 0 X X X X 0 1 1 1 X X 0 1 X X 1 0 X X 1 0 K0 X X 1 1 X X 1 1 X X The simplified expressions are: J2 = Q 0 ⋅ X + Q1 ⋅ Q 0 ⋅ X K2 = X J1 = Q 0 ⋅ X + Q 0 ⋅ X K1 = Q0 + X J0 = Q 2 ⋅ Q1 ⋅ X + Q1 ⋅ X + Q 2 ⋅ X K0 = 1 Y = Q 2 ⋅ X + Q1 ⋅ X + Q1 ⋅ Q 0 The mple e circui can be drawn using he above expressions.

and 8.29(c).26(c). 01000111010 8.28.From Table 8. second column). When X1 . Similarly. 8. 8.31(a) Presen S a e Q2 Q1 Q0 * Q2 Nex S a e X=0 * * Q1 Q0 0 1 0 1 0 1 1 1 1 0 1 0 * Q2 X=1 * * Q1 Q0 0 1 0 0 0 1 1 0 1 0 1 1 Ou pu Y X=0X=1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 Table Prob.34 (a) (i) The cir cui is ini ially in s able o al s a e 0001 (firs row. 8. (b) The circui can be designed using he me hod similar o he design of Probs.27(b) and is given below. Prob. 8. he s a e 010 can be elimina ed and he reduced s a e able is given in Table Prob. he s a es 011 and 111 are iden ical. 8. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . 8. The refore.30. elimina ing he s a es 100 and 111 we ob ain Table Prob. From his we observe ha he s a es 000 and 010 are iden ical. Therefore. 8. he nex s a es and he ou pu s are same. X2 because 11.32 (a) The circui can be designed using he me hod similar o ha of Example 8.15. 8.33 The ou pu sequence can be ob ain ed similar o Prob. This means hese wo s a es are iden ical and one of hem can be elimina ed. he s a e ransi ions will be 00 ® 11 ® 11 Shown in 114 he Fig. 8.31 ( b).31 (a).18 we observe ha from he presen s a es 001 and 100. 8. Table Prob.34(a) (i) by solid arrows.31 (b) Presen S a e Q2 Q1 Q0 * Q2 Nex S a e X=0 * * Q1 Q0 0 1 1 0 1 1 1 0 1 0 * Q2 X=1 * * Q1 Q0 0 0 0 0 1 1 0 0 1 1 Ou pu Y X=0X=1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 8.

herefore. The circui will be makin g ransi ions. Prob. Prob. 00 ® 10 ® 10 (ii) The circui is ini ially in s able o al s a e 1111 ( hird row. herefore. In (a)-(ii). 8.34 (a) (ii) 11 11 10 00 01 11 10 (b) In (a)-(i) The circui is required o change from s able s a e 00 o s able s a e 11 . he circui goes o s able s a e 10 w hich shows ha he race is cri ical. 8. When X1 X2 becomes 01. 8. he circui goes o 10 s able s a e from 10 uns able s a e.34(a) (i) by do ed a rrows. he s a e ransi ions will be 11 ® 00 ® 00 I is shown by solid arrows in Fig. race condi ion ex is s and he circui will ei her a ain 01 or 10 s a e firs . Prob.X1 X2 Q1 Q2 00 00 01 11 10 01 00 11 10 11 10 11 10 Fig.34(a) (i) Since. Bo h are shown in Fig.34(a) (ii) Q1 Q2 X1 X2 00 01 00 00 00 00 Fig. race condi ion exis s. 11 ® 10 ® 00 ® 00 or 11 ® 01 ® 00 ® 00 depending upon whe her Q1 changes fir or Q2 changes firs . If i is 10. 8.34(a) (ii) Here again bo h he s a es are required o change. If i is 01. Prob. 8. s a e ransi ions will be 00 ® 01 ® 10 ® 10 Shown in he Fig. bo h he s a es are required o change here. Prob. bu due o unequal ime delays. h ird column). 115 ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ .

The s a e change is from 11 o 00 hrough bo h he pa hs and herefore, he race is non-cri ical. 8.35 (a) X1 X2 00 Q 2 Q2 00 01 11 10 00 00 – – 01 – 11 11 – 11 01 01 11 – 10 00 01 01 – Fig. Prob. 8.35 (a) Transi ion Table For X1 X2 = 00, he nex s a e specified is 00, herefore, he en ry in he firs row, firs column will be 00 . When X1 changes o 1 while X2 = 0, again he ne x s a e specified is 00, herefore, he en ry in he firs row, four h column w ill be 00 . Similarly, squares corresponding o inpu sequence are filled. These are shown in Fig. Prob. 8.35(a). All he remaining squares are unspecified. + + (b) K-maps are prepared for Q1 and Q 2 from he s a e ransi ion able. Thes e are shown in Fig. Prob. 8.35(b). X1 X 2 Q1 Q2 00 01 11 10 00 0 0 ´ ´ 01 ´ 1 1 ´ 11 0 0 1 ´ 10 0 0 0 ´ X1 X2 Q1 Q2 00 00 01 11 10 0 0 ´ ´ 01 ´ 1 1 ´ 11 1 1 1 ´ 10 0 1 1 ´ + (i) K-map for Q 1 + (ii) K-map for Q 2 Fig. Prob. 8.35 (b) The nex s a e logic equa ions are + Q1 = X 1 X2 + X2 Q1 + Q 2 = X2 + X1 Q2 116

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(c) The logic circui is shown in Fig. Prob 8.35 (c). X1 X2 X2 Q1 X1 Q2 Q1+ Q2+ Fig. Prob. 8.35(c) Logic diagram 8.36 When he circui is in s able s a e e inpu s can change o 01 or 10. When X 1 X2 = 01, he ou pu Y may be 0 or 1 and he nex -s a e will be b. Since for h e s able s a e b , he ou pu is 0 and for he s able s a e e he ou pu is 1, w hile ransi ion from e ® b ® b , he ou pu may change during uns able b or s able b . Similarly, when X1 X2 = 10, X2 has changed while X1 = 1, herefore, Y = 1 and he nex s a e will be f and hen f . X1 X2 = 00, is no possible when he circ ui is in s able s a e e , herefore, he nex s a e and he ou pu are unspecif ied for X1 = X2 = 0 and he en ry in he firs column, fif h row will be –, –. When he circui is in s able s a e f , he inpu can change o 00 or 11. If i chang es o 00, he nex -s a e will be a and he ou pu may be 0 or 1, since he ou pu s for s able s a es f and a are 1 and 0 respec ively. When X1 X2 becomes 11, h e nex -s a e will be e and since X1 = 1 and X2 is changing s a e, herefore, Y = 1. From f , i can no go o X1 X2 = 01, herefore, he en ries in he second c olumn, six h row will be –, –. 117

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CHAPTER 9 9.1 Le us assume ha he vol age vc = V(0), i.e., he vol age corresponding o LOW level, a = 0. Therefore, vo = V(1), he ou pu of he AND ga e will be V (1) which will charge he capaci or C wi h he ime cons an = RC. When vc rea ches V(1), he ou pu of he inver er goes o V(0), hereby discharging he capa ci or wi h he same ime cons an hrough he ou pu ransis or of he AND ga e, and so on. Thus, square waveform will be genera ed a he ou pu . The waveforms of vc and vo are illus ra ed below. vc V(1) V(0) vo V(1) V(0) 0 T1 T2 Fig. Prob. 9.1

9.2 Le vo be in logic 0 s a e under s eady-s a e condi ion. The ou pu of he N AND ga e will be logic 1; he capaci or will ge charged o vol age V(1) making he inpu o he inver er as logic 0 which produces logic 1 a he ou pu . This shows ha i is no possible for vo o be in logic 0 s a e under s eady s a e. 9.3 When he vol age vi a he inpu is very low, he ou pu vol age will be max imum posi ive. I will sa ura e a vo = VD + VZ1. This makes he vol age a he non-inver ing inpu erminal as R2 R1 (V Z 1 + V D ) + V R1 + R 2 R1 + R 2 R Whe n he vol age a he inpu increases and passes hrough he above vol age, he o u pu vol age vo will change from (VD + VZ1) o – (VZ2 + VD). Hence R2 R1 (V Z 1 + VD ) + VUT = V R1 + R 2 R1 + R 2 R Now, when vi > VUT , vo = – (VZ2 + VD) This gi ves vol age a he non-inver ing inpu erminal as − (V Z 2 + V D ) 118 R2 R1 + V R1 + R 2 R1 + R 2 R

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0042 V VLT = − 0.1 0 t 5.2 V. we obtain VUT = 0. Prob.3. Prob. As soon as the decreasing input voltage passes through VLT.2 V.9938 V The input waveform is shown in Fig. the output is + 5. 6 + 0. 9. Hence VLT = − R2 R1 (V + VD ) + V R1 + R 2 Z 2 R1 + R 2 R 9.1 100 + 0. 6 ) + 100 (1) 100 + 0.2 V (b) Fig.4(b). 1 0.4 119 ¢ ¢ § § t 1. When the input voltage is zero. 1 100 + 0. vi 5V VUT VLT 0 5V (a) vo 5. 9. Now.2 V and remains at that level as long as the input voltage is higher than VL T. when the increasi ng input voltage passes through the voltage VUT. The output waveform is illustrated in Fig.4 Using the expressions for VUT and VLT derived in Prob.2 V to –5. the outpu t vo changes from – (VZ2 + VD) to + (VZ1 + VD). the output changes from +5.2 V . the output comes back to +5. 1 ( 4. 6) + 100 (1) 100 + 0.1 ( 4. 9. Prob. 9. 6 + 0.When the voltage at the input decreases and passes through this value.4(a) with VUT and VLT marke d.

5 The maximum negative output voltage Vo′ and the maximum positive output voltag e Vo′′ are given by Vo′ = VZ2 + VD1 and Vo′′ = VZ1 + VD2 Let us assume the output voltage to be maximum positive (V 0′′ ). a which time the output will swing back from – Vo′ to + Vo′′ . vc = b Vo′ b Vo′ = – o′ + b V o′′ ) e–T2/t T2 = t 1n Vo′ + bVo′′ Vo′ (1 − b ) The charging and discharging will go on in the same way and the time period of t he resulting output square waveform will be T = T1 + T2 1 1 and the frequency = f = = T T1 + T2 9. the discharge will be terminated as soon as vc reaches –b Vo′ . during the in terval T2 when the output is negative. The capacitor voltage is given by vc = V o′′ – (Vo′′ + b Vo′ )e – t/t at \ or t = T1. Therefore.9. where b = (R2/R1 + R2 ). the output voltage levels will be Vo′ = VZ2 + VD1 – VD » VZ2 and Vo′′ = VZ1 + VD2 – VD » VZ1 120 ¨ ¢ ¨¨ .6 During the interval T1 when vo is positive. vc b Vo′′ b Vo′′ = Vo′′ – ( Vo′′ + b Vo′ ) e T1 /t T1 = t 1n Vo′′ + bVo′ Vo′′ (1 − b ) At T1. Consequently. the capacitor will discharge with the same time constant from b Vo′′ to – Vo′ . Similarly. The capacitor C wi ll be charging from –b Vo′ to Vo′′ with the time constant t = RfC. vc = – Vo′ + ( Vo′ + b V o′′ ) e – t/t at \ or t = T2. However. the feedback resistance R f in ser ies with the conducting diode D will be in the circuit. the output voltage changes from positive maximum to negative maximum ( Vo′ ). During the discharging of the capacitor. R in series with the conducting diode will f be effective.

the capacitor C charges with the time consta nt t = RC. 9. v V o bVO vc t2 t vo t1 0 Fig. The ti mings T1 and T2 corresponding to the charging and discharging of C respectively are given by T1 = RC 1n T2 = RC 1n V (1) − V LT V (1) − VUT and VUT V LT 121 ¢ ¢ ¨ ¢ ¨¨ ¢ bV O VO T1 T2 T3 T4 ¨¨ ¨ ¨¨ ¨ ¨¨ ¨¨ .If we assume identical Zeners for convenience. the square wave f will b e symmetrical. When the capacitor voltage passes through the voltage bVo. V(1).5 and are given by T1 = t 1 1n T2 = t 2 1n Vo′′ + bVo′ . the capacitor discharges with the same time constant unti l its voltage becomes VLT.6.6 9. Prob. This shows that the output voltage cannot remain as –Vo under steady state. and R f = R . the output goes back to V(1). 9. At this voltage. In case R f ¹ R f .e. Prob. t 2 = R ′′ C f Vo′ (1 − b ) and The output voltage waveform is shown in Fig. the capacitor C will get charged with the pola rity opposite to that indicated in the figure.8 When the output volta ge is in logic 1 state. the periods T1 and T2 can be obtained using the rela tionships derived in Prob. the output voltage will go to +Vo. 9. Now. 9.. i.7 If vo = –Vo under steady state. t 1 = R′ C f Vo′′(1 − b ) Vo′ + bVo′′ . The charging gets terminated when vc reaches VUT and the output chang es to V(0) = 0 V.

6 kW TON » 0.5 kW C = 0.9 – GREEN and Let \ T2 = τ 2 1n 1+β 1−β R1 = R2 = 100 kW. 7 1. rcuit when the output is positive. 5 10 3 122 9. 2 × 10 −6 ≈ 200 pF 0. Assuming identical Zener diodes. 9.10 (a) The pulse dura ion is given by = ¢ ¤ © ¢ for this p In this ci is ON. T1 = τ 1 1n 1+ β 1− β R¢ f R¢¢ f – + D1 D2 R – R1 + + VZ VZ RED D3 D4 vo C R2 Fig.Hence. we ing the results of Prob.6). the diode D4 will conduct when the output is negative uently the GREEN bulb will be ON. A circuit using OP AMP Schmit trigger circuit is shown below. 9. diode D3 conducts and the RED bulb the other hand.9 An astable multivibrator with T1 = 30 s and T2 = 60 s can be used urpose. 1 2 and C = 1000 mF R¢f = 27.3 kW and R¢¢f = 54. Pro . VUT ù é V (1) VLT + 1n T = T1 + T2 = RC ê1n ú VLT û ë V (1) VUT 9. On and conseq obtain (us © .7 RC Assuming R = 1.

Therefore. 9. Therefore.2) 10 −3 5 × 10 −3 ≈ 178. ns R = 50 kW R = 30 kW R = 20 kW R = 10 kW R = 5 kW 1 2 4 10 20 40 100 200 400 1000 CEXT Ex ernal iming capaci ance. Prob. 10000 7000 4000 2000 1000 700 400 200 100 70 40 20 10 122 123 TON Ou pu pulse wid h. 5 (b) C= The du y cycle is 90% wi h an ex ernal resis ance of 40 kW. 4 f= C (RA + 2RB ) and D = (9. 5 m s 0. 6 nF 0. 9. he maxim um frequency. pF Fig. Prob. 67 and the maximum frequency.12 The frequency and du y cycle are given by 1.8 9. fmax = 1 ≈ 134 Hz 7.11 (a) Here R = 2 kW \C= 5 10 −3 = 3. T = 5 = 7. fmax = 180 Hz 9. we ob ain from he graph C 35 pF.(b) The pulse dura ion for C < 1000 pF is given by he graph shown in Fig.1) RA + RB 123 (9. 7 × 2 × 10 −3 The duty cycle is 67% with the internal resistor. 7 40 10 3 100 RA + 2RB ¤ ¤ § ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . the time period. Assuming R = 10 kW. 57 µF 0.8.

9 .01 mF Fig. he ou pu vol age is HIGH and he capaci or charges wi h he ime c ons an 1 = RAC. During charging the voltage across the capacitor. we ob ain C= 1. he capaci or ge s discharged hrough RA and RB wi h he ime cons an 2 = (RA RB) C and the output voltage drops t o 0 V. Prob. Pr ob. Prob. The waveforms of vc and output voltage.From Eq. When vc reaches 2/3 VCC. 9.2) 60 = or RA + RB RB = 2RA. (9. vc = 2 VCC 3 124 a ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ 100 RA + 2RB 10 3 3 ¤ ¤ ¤ ¤ . 9. 67 nF 10 3 100 The circui is shown in Fig.12 9. (b) The circuit corresponding to the charging of the capacitor C is show n in Fig. 9.13(c). 4 ≈ 4. is given by v c = 1 VCC + 2 VCC (1 − e − t / τ 1 ) 3 3 = T1. the charging starts a gain. from Eq.13 (a) When he vol age across he capaci or (vc) is increasing and is less h an 2/3 VCC. (9. VCC RA 4 8 7 2 555 6 + C 5 1 3 – vC vO RB 0.13(a).13(b) and corresponding to the discharging is shown in Fig. vc.12. Prob. Prob. vo are illustrated in Fig.1). As soon as this decreasing voltage crosses 1/3 VCC. Assuming RA = 1 kW Now. 9.

RB ù C 1n ê ú + RB RA ë RA . 9.13 (c) \ or e . vc = 1 3 VCC R A RB é 2 R A .T1 / 1 = 1 2 T1 0.7 1 = 0.7 RAC During discharging.2 RB û 125 ¤ ¤ ¤ ¤ ¤ ¤ § ¤ ¤ 2 ¤ ¤ . Prob.vC To VCC 2/3VCC 1 1/3VCC To 0V 0 T1 vo V(1) T2 0 T (a) VCC RA RA vC + – vC C + – C RB VCC (b) Fig. vc is given by RB RB é2 ù VCC ú e / 2 + VCC vc = ê VCC R A + RB R A + RB ë3 û a which gives T2 = = T2.

1 RAC and hen goes LOW. 9.2 RB û (c) From he expressions for T1 and T2 ob ained in par (b). Prob.14. T1 Inpu pulses Ou pu 0 1 T Fig.35 are given in Fig.RB ù C 1n ê ú RA + RB ë RA .\ T = T1 + T2 = 0.7RA = (d) If R A RB é 2 R A . 9.20 ù 1n ê ú = 0. I remains HIGH for a period T = 1. or R B < A 3 2 RA + RB 9. 50% du y cycle).40 û or RA 48 kW (e) From Fig. Prob. we ob ain RB R VCC < 1 VCC .7 RAC + Du y cycle = T1/T ´ 100% RA RB é 2 RA .13 c. we observe ha i is possible o make T1 = T2 (i. If (n – 1) T < T < nT1 wh ere n is an in eger. 126 his monos able circu ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ § ¤ ¤ ¤ ¤ . 9. a which i me i goes HIGH. 9. Prob. hen he frequency of he ou pu waveform will be fo = fi æ 1ö ç fi = T ø ÷ n è 1 Thus he circui func ions as a frequency divider.7 R A RA + 20 ë RA .e.14 A B The ou pu is in LOW s a e un il he firs falling edge (A) appears. we ob ain RA 20 é 2 RA . I will remain LOW ill he nex nega ive edge (B) appears. The condi ion which mus be sa isfied o achieve his is 0.14 (a) The inpu pulses and he corresponding ou pu for i of Fig.2 RB û RB = 20 kW From par (a).RB ù 1n ê ú RA + RB ë RA ..

When he inpu pulse goes from LOW o HIGH. he circui becomes a re riggerable monos able mul ivibra or.1 R C. whenever he rigger pulse goes LOW. he ou pu goes o HIGH for a ime period T = 1.2 ms < T < 0. 9. 9. 127 ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ha Since 0.(b) Here T1 = 1 m s 10 Choose RA and C values in Fig.15 If h e ou pu is in HIGH s a e under s eady-s a e. if w e connec pin-4 (Rese ) o pin-2 (Trigger) i becomes a re riggerable monos able mul ivibra or.e. if we choose RA = 2. he ransis or T1 of he imer is cu -off and he capaci or is herefore ge ing charged.. he ou pu and he discharge erminals go LOW.35 such RAC Therefore.2 kW and C = 0.35. hereby discha rging C and he ou pu goes LOW. In his circui .16 In he circui of Fig.1 ¤ ¤ ¤¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ . Hence.3 m s T = 1.242 m s 9. Thus. When he vol age across he capaci or reaches 2/3 VCC. 9. i.1 mF hen T = 0. he ransis or goes o sa ura ion. he circui is rese . i is no possible for he circui o be in HIGH ou pu s a e under s eady-s a e.

128 © CHAPTER 10 10.The step size or resolution = Digital Input S2 S1 S0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output voltage without offset – 3.5 – 3.5 – 1. 10.3(a).3(b).5 Output due to offset + 3. 2 = 1 and 1 = 0 = 0. From this we o serve that this circuit converts digital input s in one’s complement format to analog output. and b1 = 1. The equivalent circuit correspondin g to the lower order four its is shown in Fig.3 (i) Let 3 = 0. The analog output voltages for each of the digital input s are given elow. As long as DV < . The corresponding equivalent circuit is s hown in Fig.2 10 10 S = V. Prob. Prob. From this we o ta in Iin = VR (8 /11R) × ( r + 8 /11R) r (8 /11R) 2R + ( r + 8 /11R ) VR 2R The current due to 6 is \ or V R (8/ 11R ) VR = 2 R( r + 8 /11R) + r (8/ 11r ) 16 × 2 R r=8R RF 2 2R r Iin + VO VR R 4R 8R Fig.5 + 0. 10. 2 8 − 1 255 2 5/255 V the least significant it will e significant. i. 10.5 + 3.5 + 2. © ¢ © © © © © © © © © © © .5 – 3.5 + 3.5 – 2.5 – 0. Pro ..5 + 3.5 Net Output Vo 0 1 2 3 –3 –2 –1 0 10.1 10.e.5 – 3.5 + 1.5 – 3.5 + 3.3(a) (ii) Let b3 = b2 = b0 = 0.

we obtain r = 8 R. to satisfy the same condition. The analog output voltages for various digital inputs are given in table The out put voltage is given by ¢ RF RF æ RF ö Vo + V1 + V2 ÷ Vo = 129 ç R R /2 R /3 ø è . Therefore. we obt ain r = 8R RF b0 8R r Iin VR R 2R 4R + VO Fig. 10. and b0 = 1 The equivalent circuit is shown in Fig.3(b) (iii) Let b3 = b2 = b1 = 0. P rob. 10.3(c) from which we obtain Iin = VR ( 4 / 7 R) × ( r + 4 / 7 R) r ( 4 / 7 R) 8R + ( r + 4 / 7 R) The current due to b4 is VR/8R. Prob.3 (c) 10. 10. Prob.Iin = VR (8 /13 R) ´ r (8 /13 R ) ( r + 8 /13 R) 4R + r + 8 /13 R VR . 10.4.4 The modified circuit will be equivalent to the circuit given in Fig. RF b1 4R r Iin + VO VR R 2R 8R Fig. 4R The current due to b5 is To satisfy the same condition.

S0 R RF = R R/2 + S1 VO S2 R/3 Fig. Prob. 10.4 where Vn = – =+ 1 2 1 2 if Sn = 1 if Sn = 0. Table Prob. 10.4 S2 0 0 0 0 1 1 1 1 Digital Inputs S1 S0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Analog Output V 0 +1 +2 +3 –3 –2 –1 0 We observe from the table that this circuit also converts digital input in one’s c omplement format to analog output. 10.5 The circuit for 4 bit D/A converter is s hown in Fig. Prob. 10.5. This circuit without offset gives an analog output of –7. 5 V for the digital input 0000 and + 1/2 V1 0 1 0 1 0 R/2 RF = R + VO R 0 1 S2 ROFF 1/2 V + R/4 V (1) = 1/2 V R/8 1 0 V (0) = 1/2 V Fig. Prob. 10.5 130

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+7.5 V for the digital input 1111. Therefore, the offset required is +7.5 V for 0000 input and –7.5 V for 1111 input. R Therefore, ROFF = 15 10.6 When the 4 bit d igital input is 0000, the output voltage will be

1 2

where, RX is the resistance in the path of switch S 3 . This voltage must be 0. Therefore, R RX = 4 + 2 + 1 or RX = R/7 R R/2 R/4 R/7 S3 Fig. Prob. 10.6 + VO The resulting circuit is shown in Fig. Prob. 10.6. S0 S1 S2 RF = R 10.7 Let the analog voltage range be from –V0 to +V0. The step size will be 2/7 V0 . The reference voltages are given below. There is one more negative number than the positive numbers in 2’s complement representation. The circuit is shown in Fi g. Prob. 10.7. Reference voltages V0 VR7 = 5/7 V0 VR6 = 3/7 V0 VR5 = 1/7 V0 VR4 = –1/7 V0 VR3 = –3/ 7 V0 VR2 = –5/7 V0 VR1 = –V0 –9/7 V0 0 2’s complement digital output S 011 010 001 000 1 11 110 101 100 If we choose to ignore 100 output, the resistor chain will be connected between +V0 and –Vo and only six comparators will be required. The decoder circuit can be designed in the usual manner. 131

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RF RF RF ö æ RF ç

R + R /4 + R /2 + R ÷ è ø X

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V R Va Analog voltage VR7 = +5/7 V0 R VR6 = +3/7 V0 R VR5 = +1/7 V0 R VR4 = –1/7 V 0 R VR3 = –3/7 V0 R VR2 = –5/7 V0 R VR1 = –V0 R –9/7 Vo Fig. Prob. 10.7 – + – + – C5 Two’s ement format + – + – + – + – + C1 C2 C3 C4 L A T C H E S D E C O D E R C6 C7 B2 ü B1 ý B0 þ ï ï 10.8 The conversion time t is given by Va ⋅ 2 N ⋅ TC VR where, N is he number of bi s in he digi al ou pu , TC is he im e period of he clock, Va is he analog vol age, and VR is he reference vol age . The larges Va can be equal o VR. Therefore, when Va = VR = 2 N ⋅ TC + = 2 N + 1 ⋅ TC = 2 13 10 −5 or, f< 10 5 8192 Therefore, f < 12 per second. 132

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44 mV mV mV mV mV 10.11 (a) CSB: It is complementary straight inary code. the voltage corresponding to LSD = 10/1000 = 10 mV ( ) ADC 80 is a 12 it A/D converter. Therefore. (c) CTC: It is complementary two’s complement code.10(a) Analog output range 0 0 0 0 0 to 2. natural BCD code 133 © © © © © © © © © © © © © © © © © ¢ © ¢ © © © © © © © © © © © © . Ta le Pro . 10. 10.44 mV mV mV mV mV (ii) Complementary coded decimal code (CCD) input The analog output range for th is code is 0 to + 10 V. ( ) COB: It is complementary offset inary code. It is o tained y complementing the natural BCD code. it will e coded in CTC as 0001. For example. 10( ) Analog input voltage range 2. For example. (d) CCD: It is co mplementary coded decimal code. For example. It is o t ained y complementing two’s complement.22 2.44 4.88 1. (i) Complementary inary input (CBI) Ta le Pro .44 4. decimal 2 will e coded as 1101 – 1000 = 0101. Where n is the nu m er of its used to represent the num er. 10. The voltages corresponding to LSB fo r various analog input ranges are given in Ta le Pro . It i s determined y finding out CSB and then offsetting it y –2n – 1.10(a) gives the voltage corresponding to LSB for each of the ran ges.5 V to 5 V to 10 V to + 5 V to + 10 V Voltage corresponding to LSB 1.22 2.5 V 5V 10 V 0 to 5 V 0 to 10 V Voltage corresponding to LSB 1. two’s complement representatio n of – 2 is 1110 and therefore.10 (a) DAC 80 is a 12 it D/A converter.10( ). for example.22 2. Decimal 2 will e coded in CSB as compleme nt of 0010.88 1.9 The voltage step = = 10 V 26 −1 10 V 63 10.22 2. the straig ht inary code for decimal 2 is 0010. which is 1101.10. Ta le Pro . 10.

Ta le Pro . 10.11 gives the decimal num er for each of the 4 it inary num ers in each of the a ove codes. 10. it will e coded in CCD as 1101. Ta le Pro .for decimal 2 is 0010 and therefore.11 Binary CSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Equivalent decimal values COB C TC +7 +6 +5 +4 +3 +2 +1 0 –1 –2 –3 –4 –5 –6 –7 –8 –1 –2 –3 –4 –5 –6 –7 –8 +7 +6 +5 +4 +3 +2 3 2 1 0 134 © © © © ¢ © © © © © © .

Memory A B Maximum rate 1 × 10 9 = 666666/s 1500 1 × 10 9 = 1724137/s 580 (Contd. 0 to F.) 135 © © © © © . 000 to 7FF. 11. 000 0 to 3777. It is given elow for each memory. 000000 to 177777. 00 to FF.2 (a) 0 to 3. 0000 to FFF F. 0000 to 1777. ( ) 0 to 3. 00000 to FFFFF.1 The num er of pins P is given y 2P = M (a) P = 2 Address range: A1A0 = 00 to 11 ( ) P = 4 Address range: A3A2A1A0 = 0000 to 1111 (c) P = 6 Address range: A5A4A3A2A1A0 = 000000 to 111111 (d) P = 8 Address range: A7A6A5A4A3A2A1A0 = 0000 0000 to 11111111 (e) P = 10 Address range: A9A8A7A6A5A4A3A2A1A0 = 0000000000 to 1111111111 (f) P = 11 Address range: A10A9A8A7A6A5A4A3A2A1A0 = 00000000000 to 11 111111111 (g) P = 16 Address range: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ( h) P = 20 Address range: A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11.3 The maximum access rate = 1/Cycle time gives the maximum rate for each memory. 00 to 3F. 0000000 to 3777777.CHAPTER 11 11. 00 to 77. 000 to 3FF. 00 to 17. 000 to 377.

two 2142 RAM chips are connected as shown in Fig. ( ) 2 chips of 2142. for convenience. 2 line to 4 line) decoder IC will e required.) Memory C D E F Maximum rate 1 × 10 9 = 2222222/s 450 6 1 × 10 9 = 5 ´ 10 /s 200 1 × 10 9 = 16666666/s 60 1 × 10 9 = 1250000/s 800 11. This decoder will select one out of the four chips depending upon the values of A10 a nd A11.(Contd. 11.5 (a). of the 8 it word. The complete circuit is shown in Fig. 16 sets of 1 K ´ 8 circuits as shown in Fig. (c) 4 K ´ 16 = 2 ´ 2 ´ (2 K ´ 8) The num er of 2716 chips required is four. Here. ( ) For o taining 1024 ´ 8.. Pro . the address A0 – A9 is applied to oth the chips. One inver ter will e required to select one pair of 2716s. The lower ten its of the address (A0 – A9) are connected to the address us of each RAM chip. therefore. the width of the address us required is 1 2. 11. and A10 and A11 are applied to a 2 line to 4 line decoder. ( ) 2 K ´ 16 = (2 K ´ 8) ´ 2 This also requires two chips of 271 6. 11.5 (a) which can e unders tood easily. (c) 16 K ytes = 16 K ´ 8 = (16 ´ 1024) ´ (4 ´ 2) = 32 ´ (1024 ´ 4) Therefore. 11.7 (a) For 4 K locations. The address it A11 is applied at the chip select ( CS 1 ) input o f ROM 0 and its complement is applied at 136 © ¢ ¢ ¢ © ¢ © ¢ © ¢ ¢ © © © © ¢ ¢ ¢ © © ¢ ¢ ¢ ¢ © © ¢ © © ¢ © © © © ¢ © ¢ © ¢ © © © © © © © © © © © © © © © © ¢ © © ¢ © .5 (a) Since the total n um er of locations is 4 K. T he upper chip. For this purpose a 4 line to 16 line decoder circuit is to e used in a way similar to that used in Fig. Pro . The most significant it A11 of the a ddress is used to select the chip and the other 11 its A10 A0 are applied to o th the chips. Pro . One 1 out of 16 dec oder will e required to select a specific chip pair. num er these sixteen sets as RAM 0 to RAM 1 5. (c) For o taining 16 K ytes of RAM . th e width of the address us required is 12.5 ( ) are required. Let us. Pro . A0 – A9 will e same for all the 16 sets. IC1 has een used for the lower four its and the lower chip.e. 32 chips of 2142 will e required.4 (a) 4 chips of 2142 and one 1 out of 4 (i. IC2 for the upper four its.6 (a) 4 K ytes = 4 K ´ 8 = 2 ´ (2 K ´ 8) Therefore. 11. The most significant four its of the addresse s are to e used to select one out of the 16 sets. 11. 11.5 ( ). two chips of 2716 and one i nverter are required.

11 . Pro . 11. (c) For o taining 4 K ´ 16 ROM. Figure Pro . use two sets of 2 K ´ 16 memory (Fig.7( )) and connect them as shown in Fig. 11. 137 D A0 – A9 A +VCC T A B U © © ©¢ ¢ © ¢ © ¢ © © © © ¢ ¢ ¢ © ¢ 2142 RAM 3 I/O1 – I/O4 ¢ +VCC S 2142 RAM CS 1 CS2 2 I/O1 – I/O4 ¢ +VCC A0 – A9 2142 RAM CS 1 CS2 ¢ 2142 RAM CS 1 CS2 0 I/O1 – I/O4 1 I/O1 – I/O4 © ¢ © ¢ ¢ © . Therefore. Pro .7(a). ( ) Figure Pro . 11.5(a) CS 2 input.A0 – A9 WE OD 2 3 A0 – A9 A11 WE OD WE WE OD OD CS 1 CS2 +VCC Fig.7(a) illustrates the relevant portion of the circuit.7( ) shows 2 K ´ 16 ROM. Pro . 11. Pro .8 (a) In the linear selection addressing. a one out of N decoder is us ed to select one of the N memory locations. when A11 = 0 ROM 0 is selected. For example. 11. whereas A11 = 1 will sele ct ROM 1.8(a) show s as 4 line to 16 line decoder used to select one out of sixteen memory location s. The lower order eight its of each of the 16 it words are stored in IC1 and the higher order eight its are stored i n the corresponding location in IC2. 11. Fig.

(4 A10 2 lineto 4linedecoder 1 OD – 0 B WE I T) ¢ ¢ .

A0 – A9 2142 IC1 OD I/O1 – I/O4 WE CS 1 OD CS2 2142 IC2 A0 – A9 I/O1 – I/O4 ï ï ï ï ï ï8 it output ý (D0 – D7) ï ï ï ï (D4 – D7) ï ï ï þ (D0 – D3) ü Fig.7( ) 138 © ¢ © © ¢ © ¢ © © © ¢ . 11. 11.7(a) 2716 A0 – A10 IC1 CS CS CS 2716 IC2 A0 – A10 ü ï ï ï 16 it output ï ý (D – D ) 0 15 ï ï ï ï þ Fig.5( ) (8 – B I T) D0 – D7 D A T A O0 – O7 O0 – O7 D8 – D15 B U S CS 2 2716 2716 A0 – A10 ROM 0 CS 1 O0 – O7 A11 A0 – A10 ROM 1 O0 – O7 Fig. Pro . Pro . 11. Pro .

Pro 11. a memory location is selected y app lying an X address and a Y address. 0 1 2 3 Column Row 0 D00 1 of 4 Decoder DL A0 D01 D02 D03 ì ï A1 ï ï ï ï ï ï Row drivers ï í Diode ï matrix ï Column ïA ena le 2 ï ï ï ï A3 ï î 1 of 4 Decoder DH D10 D11 D12 D13 1 D20 D21 D 22 D23 2 4 it address D30 D31 ¢ ¢ © ¢ © © © © ¢ ¢ ¢ ¢ © ¢ ¢ ¢ © © . Each memory element is placed at the intersection of a row and a column. the X address is A1A0 which selects a row and the Y address is A3A2 which ena les a column. 11. Here.0 Memory location 0 Memory location 1 Memory location 2 ì 3 ï ï A2 Address ï ï inputs í ï A1 ï ï ï A0 î A 1 4 line to 16 line decoder 2 14 15 Memory location 14 Memory location 15 Fig.8(a) ( ) In the coincident selection addressing. The decoder circuitry consists of 1 out of X and 1 out of Y decoders as shown in Fig. Pro .8 ( ).

Pro .D32 D33 3 Column sense amplifiers Chip select (CS) Data output Fig. 11.8( ) 139 © © .

11. match condition will e checked only for I0 it. The outputs of the NOR gates will e 0. T4 also conducts. 11. the gates of the inverters are not held at VDD ut are clocked so th at T3 conducts only when f2 = 1 and not when f1 = 1. 11. (iv) Read Operation: When A1A0 = 00. even if the it stored on C 1 is 1. Here. the power is always drawn from the supply throughout the clock cycle. When T3 conducts.9a.e. T2 is OFF). 11. C charges to logic 1 through T3. (v) Write Operation : When A1A0 = 00. Therefore. Therefore.9 The operation of this circuit is similar to that of the circuit of Fig.. The output will e OR operation performed on all the selected outputs. the ratio C2/C3 must e very large. On the other hand. in the circuit of Fig. and W = 1. In contrast to this. therefore. and W = 1. independently of data input (since f2 = 0.10 When the transistor T4 conducts. (ii) Associate Operation with Higher Bit Masked: When A1A0 = 01. T1 will e OFF and C will continue at logic 1 level. otherwise it is 1. the operation of the circuit will e similar to the operation explained i n (i) a ove except that the output of the AND gate on the I1 side will always e 0. the latches are disa led. the output of the AND gate is 1 for mismatch and 0 for match. The data outputs D1 and D0 are oth 0. (iii) Associate Operation with Lower Bit Masked: The opera tion is similar to the operation of (ii) a ove.12 (i) Association Operat ion: When A1A0 = 11. 9(a). The f2 needs to e 1 only long enoug h to allow C2 to charge from VDD through T3 and T4. the output Q0 of the latch appears at the corresponding D output. then during f2 = 1. Therefore.11 During the int erval when f1 = 1.11. The output of the EX OR gate will e 0. if the i nput is at logic 0. It is also possi le to read more than one locatio n at a time. Similarly. otherwise it will e 1. The same data also appears at the D outputs following the argumen ts of (iv) a ove. Now. 140 © © © © © © ¢ © © © © © © © © © © © © © © © ¢ © © © © © © © © © © © © © . This logic level remains on C after f1 ret urns to logic 0. C2 >> C3. C3 charges from C2 forming a capacitive loop. Depend ing upon which Y is selected y making it 0. T1 and T2 will conduct and C will get discharged to logic 0 level. 11. the latches are ena led for the location y making the Y input 0. there is considera le reduction in power dissipation in this circuit. This happens when more than one address input is made 0. In order to charge C3 without causing apprecia le voltage dro p. which will disa l e the latches. the complement of logic level on C will e transferred to output capacitor ( etween drain of T6 and ground). In gene ral. and W = 0. therefore. the logic level of C will e complement of input logic level. W = X). outputs of the OR gates are 1 irrespective of the logic lev el at W (i. The output Y of the wired OR gate will e 0 if oth the data inputs match with the its stored. The AND gate of D1 output is ena led. if the data input is 1. du ring f3 and f4 phases. if the data input it is same as the it stored (Q0).

8 it word CAM. 11. it requires two chips. The matching will e performed for hig her its and the lower it (I0) will e stored in the locations for which I1 mat ch. Y0 – Y7 of each chip are connected to a common us . ( ) When A1A0 = 10 and W = 0.. Thus. I1 I0 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 D0 D1 A0 A1 I0 I1 8´2 CAM IC1 D1 D0 W W W A0 A1 I0 I1 D1 D0 8´2 CAM IC2 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Fig. the corresponding higher it (I1) is latched into the latch and it also appears at the D1 output. for designing a 16 ´ 8 CAM. Pro . 11. i. The resulting system has 16 address inputs (Y0 – Y15).16 It is a 16 word. Pro . 11. the key is 141 © © © © © ¢ © © ¢ © © © © © © ¢ © © © © © © © © © © . 11. the num er of chips required is four. t he association operation is performed for the lower it (ii) a ove.15.13 Since 16 ´ 2 = 2 ´ (8 ´ 2). it ecomes a CAM of sixteen 2 it words. therefore. The data input s. The f irst operation is to interrogate the MSB of all words for a 1 with all other it s masked. the operation will e si milar to the operation of part (a) a ove. The outputs will e 0 for matched conditions and 1 for mismatch conditions.14 8 ´ 8 = 4 ´ (8 ´ 2) Therefore. data outputs. 11. Pro . 11. two 8 ´ 8 CAMs as shown in Fig.13. When there is ma tching.14. Since the n um er of words is 8. Pro . 11. The circuit of 8 ´ 8 CAM is shown in Fig. 11.15 16 ´ 8 = 2 ´ (8 ´ 8) Ther efore. therefore.e. and mode control inputs of two 8 ´ 2 CAMs are connected as shown in Fig.(vi) Associate and Write at the Match Addresses: (a) When A1A0 = 01 and W = 0.13 11.14 can e conn ected as shown in Fig.

14 I7 8 ´ 8 CAM I0 Y0 Y7 Y0 Y7 D0 D1 D2 D3 D4 D5 D6 D7 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 W D7 D6 D5 D4 D3 D2 D1 D0 8 ´ 8 CAM Y8 Y15 ¢ © ¢ ¢ . 11. Pro .A7 A6 I7 I6 A5 A4 I5 I4 A3 A2 I3 I2 A1 A0 I1 I0 A1 A0 I1 I0 8´2 CAM A1 A0 I1 I0 8´2 CAM A1 A0 I1 I0 8´2 CAM A1 A0 I1 I0 8´2 CAM Y0 – Y7 Y0 – Y7 Y0 – Y7 D0 D4 Y0 – Y7 W D1 D7 D0 D6 W D1 D5 W D1 D3 D0 D2 W D1 D1 D0 D0 W Fig.

However. In case no match occurs when the MSB i s interrogated. if several words indicate a match. then the CAM is to e interrogated again with key as 11XXXXXX. Pro . then the next key has to e 142 © © © ¢ .15 I0 1XXXXXXX. then the maximum valued word searc h is complete.Y0 Y7 I7 Fig. If only one word indicates a match. 11.

chip select.20 01XXXXXX. In the case of RAM. th e search process is serial in a RAM which is time consuming and hence a RAM is n ot suita le for this purpose. the time required for the search will e depe ndent on the num er of words stored which is sixteen in this case. The operation is similar to the operation of Pro . The inputs and the outputs of all the CCDs are to e connected in parallel. just in one cycle. w rite ena le.19 11. In any case no more than 8 interrogation cycles will e requi red to determine the maximum valued word. we can find out whether the word is already stored or not. A CAM is ideal for this. 143 © © © © © © © © © © © © © © © © © © . If not. In contrast to this.11. This process is to continue till at the most all the its of the words are interrogated. The additional address its are decoded and used to se lect one of the CCDs for read/write operation. Because of the parallel search operation in CAM . The num er of data inputs and outputs are used independently. The num er of inputs/o utputs will e equal to the num er of CCDs. Therefore. the address.18 11.16 with 1’s replaced y 0’s in the search p rocess.17 11. each word is to e compared sequentially. it can e stored in the next location availa le. and clock inputs of all the devices are connected in parallel. The clock and write ena le are al so connected in parallel. For expanding word length. 11.

E2. ( ) Logical expressions can e w ritten for E3. a PROM of size 10 ´ 4 is required. For example at the address 0000.C. Pro . Data i s to e stored in the PROM at the addresses corresponding to the BCD code. the data stored is 0011 a nd at the address 1001 the data stored is 1100. E1. the d ata is Excess 3 code. a PROM of size 16 ´ 4 is to e used. ut since PROM o f this size does not exist.CHAPTER 12 12. 12. and E0 outputs in terms of A. A B C D E3 E2 E1 E0 Fig. and D inputs.1 ( ) The simplified expressions are: E3 = A + BC + BD E2 = B C D + B C + B D E1 = C D + CD E0 = D 144 © ¢ © © © © © © ¢ © ¢ © ¢ ¢ ¢ © . these expressions can e minimized using K maps.B. BCD A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 Excess 3 E2 E1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 E0 1 0 1 0 1 0 1 0 1 0 (a) For the design using PROM. To reduce the hardware requirements.1 The BCD to Excess 3 code converter’s truth ta le is given elow. therefore.

the num er of i nputs increases. Hence.6 Architecture of a PLD refers to the attri utes of the devi ce significant to the logic of a design to e implemented.1. 12. A E3 B E2 C E1 D E0 Fig.The size of PLA required is No.2 Follow similar procedure as given in Pro .1(c).3 Prepare truth ta le a nd follow similar procedure as given in Pro . Pro . of inputs =4 No. 12. 12.1 (c) 12. one of the output lines of the decoder will go LOW activatin g the corresponding PLA and disa ling all the other PLAs. This will result in 8 + 8 = 16 output s. Config uration of the input and output interface logic. Pro . of outputs =4 Minimum num er of =3 AND gates for each ou tput The circuit is given in Fig. 12. 145 © © © © © © © © © © © ¢ © ¢ © . The size and the arrangement of the programmable array(s). Depending on the valu es of IM to IM+Q 1. of outputs =4 No.1( ). of inputs =4 No. Pro .1. (c) The required size of PAL is No. 12. 12. It includes.4 The inputs of two 82S10 0 devices are to e connected in parallel. 12. 12. Configur ation of pins. 12. of product te rms =9 The circuit is given in Fig.5 The inputs I0 to IM 1 are common for all the PLAs.

8 Input I1 I1 I2 I2 I3 I3 I4 I4 Column 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 Input/output IO1 IO 1 IO8 IO 8 O2 Column 2 3 30 31 6 7 10 11 14 15 18 19 22 23 26 27 O2 O3 O3 O4 O4 O5 O5 O6 O6 O7 O7 I5 I5 I6 I6 I7 I7 I8 I8 146 .12.7 Input I1 I1 I2 I2 I3 I3 I4 I4 I5 I5 I6 I6 I7 I7 I8 I8 I9 I9 I10 I 10 Column 2 3 0 1 4 5 8 9 12 13 16 17 20 21 24 25 28 29 30 31 Input/output IO2 IO 2 IO3 IO 3 IO4 IO 4 IO5 IO 5 IO6 IO 6 IO7 IO 7 Column 6 7 10 11 14 15 18 19 22 23 26 27 12.

0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 8 8 8 8 8 7 7 7 7 7 7 7 7 Comb. for x1 =1 when and when x2 = 1. topmost cell will be selecte d and f will be 1. C. MUX–2. Similarly. Reg.12. (a) Open all the inputs to the controlling AND gate. Comb. f will be obtained from the upper multiplexer.10 These are given in Fig.12 When x1 = 0. Table below gives all the possible conditions. Reg. 12. For x2 = 0. Each one may be programmed to be in 0 or 1. F . G and H intact to the controlling AND gate and open all other connections. (c) Keep the c onnections corresponding to the inputs A. MUX – 1 MUX – 2 MUX – 3 MUX – 4 No. Comb. Reg. Prob. MUX–1. Reg.11 Here the output of an AND gate controls the output. Reg. the cell second from the top will get sel ected and f = 0. f = 1 147 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ . of product Terms 8 8 8 Output Enable pin 11 pin 11 T erm Controlled Term Controlled pin 11 pin 11 Term Controlled Term Controlled pin 11 pin 11 Term Controlled Term Controlled pin 11 pin 11 Term Controlled Term Co ntrolled Output Output pin/FF output feedback input feedback 0 0 0 0 0 0 0 0 1 0 1 0 Reg. (b) Ke ep all the inputs intact (connected) to the controlling AND gate. comb. Comb. E . MUX–3 and MUX–4. Reg. Reg. B. 12.10. 12. f = 0 x2 = 1. Comb. which means its output will be either same as input 0 or input 1. D. Comb. Comb. whereas for x2 = 1. input feedback input feedback input feedback input feedback input feedback input feedback input 12.9 It has four multiplexers.

Registered output B = 1 Combinational output B = 0 AR D Q SP A=0 AR D Q SP A=1 AR D Q SP AR D Q A=0 SP AR D Q AR D Q SP A=1 SP Q A=0 AR D Q SP AR D Q SP Q Fig. 12.10 148 REGISTER FEEDBACK CD = 00 COMBINATIONAL FEEDBACK CD = 10 BI DIRECTIONAL I/O CD = 11 A=1 ¢ . Prob.

f will be obtained from output of bottom multiplexers’ structure. the truth table will be as given below. the complete circuit can be analyzed. the output will be from the top most cell. f will be obtained from output of top multiplexers’ structure. it will be obtained from the next multiplexer. and when x3 = 1 it will be from be next cell.Therefore. Similar ly. When x3 = 0. The bits to be stored will be 0 1 1 0 1 0 0 1 149 ¢ ¢ . when x 1 = 1. the output will be obtained from the top most multiplexer and when x2 = 1.13 The truth table of the given function f is x1 0 0 0 0 1 1 1 1 x2 0 0 1 1 0 0 1 1 x3 0 1 0 1 0 1 0 1 f 0 1 1 0 1 0 0 1 when x1 = 0. Now. when x2 = 0. x1 0 0 1 1 x2 0 1 0 1 f 1 0 0 1 12.

The memory address space for the mPs are given below. Prob. 4 K bytes = 4 K ´ 8 bits = 4 ´ 2 ´ (1 K ´ 8) bits = 8 chips 2716 is a 2 K ´ 8 bits EPRPM. th e total number of instruction codes.1 The memory address space is given by M = 2P where. Therefore.CHAPTER 13 13.3 (a) 2142 is a 1024 ´ 4 bit s RAM Therefore. A8 – A15 8085 A WR RD AD0 – AD7 ALE A0 – A7 8212 CLR DS2 MD DS 1 +VCC Fig. The tot al number of instruction codes in 8085A mP is 246. 13. (b) Let the first 2 K bytes be in EPROM and next 4 K bytes be in the RAMs. P is the address bus wid th. The relevant connections are shown below.2 The number of distinct combinations of 8 bit words = 28 = 256 Therefore. Microprocessor 8080A 6800 8086 9900 Z8000 Memory address space 64 K bytes 64 K b ytes 1 M bytes 64 K bytes 8 M bytes 13. only one 2716 chip is required. 13. assuming single byte op code = 256.3(a) 150 ¢ .

Store in destination memory INX D . Complement A MOV M. Prob. 13. Load accumulator with zero (ii) SUB A . A . 07FF 0BFF 0FFF 13FF 17FF 13. Load A with contents of sour ce memory CMA . 0F00 H .3(b) (c) The address of various chips are given below. Subtract A from A (iii) ANI 00H . Initialize source pointer LXI H. AND A with zero (iv) XRA A .5 Let D E and H L pairs be pointers to source and destination memory locations respectively. 1F00 H . 1 2 3 4 0000 0800 0C00 1000 1400 Last address in hex. A EX OR A Note that the information beyo nd semicolon (. Memory chips EPROM RAM pair RAM pair RAM pair RAM pair Starting address in hex. The program is given below: LXI D . 00H . Initialize counter LOOP: LDAX D . Incr ement pointers INX H 151 ¢ ¢ ¢ .Other connections are indicated below: A0 – A10 from mP to A0 – A10 of 2716 A0 – A9 fr om mP to A0 – A9 of each of 2142 CS2 of each 2142 to Vcc WR from mP to WE of each 2142 RD from mP to OD of each 2142 A10 A11 A12 (from mP) A13 A14 A15 (from mP) A0 A1 A2 8205 E1 0 1 2 3 4 5 6 7 To CS of 2716 To CS 1 of RAM set 1 To CS 1 of RAM set 2 To CS 1 of RAM set 3 To CS 1 of RAM set 4 E2 E3 Fig. 100H . 13.4 (i) MVI A.) are comments. Initialize destination poin ter LXI B.

DCX B MOV A. LXI H. Get a byte of data in A REP : DCR C JZ STOP . Increase pointer by 1 START : MOV A. Load A with first number MOV B. (A) < (B) MOV M.8 LXI H. Stop at end o f data INX H CMP M . Otherwise (A) > (B) JMP FINIS GREAT: MOV M.10 LOOP: DCR 0 JZ FINIS IN DATA MOV M. M . A INX H JMP LOOP FINIS: MOV B. Decrement counter . Initial ize pointer MOV C. A .7 The following instructions wil l clear the memory location. Store destination address in H L pair LDA 0A00H .9 ANI 0FH 13. A 152 ¢ . Store the smallest element END 13. B FINIS : 13.6 The program is given below: LXI H. C ORA B JNZ LOOP . Transfer to B LDA 0A 01H . A . Compare A and B JZ FINIS . Get the number of bytes in C INX H . Check counter for zero NEXT: 13. try next number JMP START ST OP: STA FF00H . 01A0H MVI M. If CY = 1. Go to FINIS i f the two numbers are equal JC GREAT . 00H 13. Compare JC REP . Load A with second number CMP B . A001H . If (A) < (M). M . 0A02H .

13. The program can be written as MVI B. 13. ADD B instruction must be followed by DAA instruction. A . Go to loop FINIS: MOV B.11 N=3+3+1+1+1+1+1+1 = 12 bytes 13. Initialize H L pair with address BUFR MOV C.1 3 Assume a set of ten keys for entering BCD number and a 7 segment display for d isplaying this number. Decrease counter by one JZ FINIS . 0BH .SOLUTION The operation performed by each instruction is given below: START: LXI H. The effect of this is given below: 1001 1011 0000 0110 Add 6 because the least significant four bits d o not represent a valid BCD digit 1010 0001 0110 0000 Add 60 because the most si gnificant four bits do not represent a valid BCD digit 10000 0001 = (101)10 13. Go to FINIS if counter = 0 IN DATA . A . Advance the pointer by one JMP LO OP . M OUT 02H 153 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ . 0000H IN 01H ADD B MOV L. BUFR . Input a byte from DATA port MOV M. Move the byte to me mory . Assume 01 H and 02H as the port addresses of the input device and output device respective ly.13(a) and (b) respectively. The block diagrams for the input and output devices are shown in Fig. The addresses are decoded and proper signals are generated for Enable and De vice Select terminals for reading and writing.12 (A) 0000 1000 (B) 1001 0011 ADD B 1001 1011 The result is not a valid BCD numbe r. location pointed to by H L pair INX H . Move the contents of A to B The operation perf ormed by this program is to input ten bytes from input port DATA and store them in memory locations starting from BUFR. Initialize counter with decimal 11 LOOP: DCR C . It is also assumed that BCD to 7 segment codes are stored in memory from the starting address 00XXH. Prob. A MOV A. XXH LXI H.

13 13. 13. Prob.14 The last six instructions will be POP PSW POP H POP D POP B EI RET 154 ¢ ¢ ¢ .VCC D (MSB) Decimal toBCD Encoder (Inputs & outputs active low) C B Inverting Trista te Buffer D3 D2 D1 Data bus of mP b c d A D0 Enable (a) Current limiting resistors VCC Common anode a b c f d e e f g a g Data bus D type Latch Device Select (b) Fig.

20 20 bit current address of the stack will be 24000 + A000 2 E000 H 155 ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ ¢ . 13.19 CS = 2000H I P = 1A00H 20 bit address of the next instruction byte will be fetched from 20000 + 1A00 21A00 H 13.17 Eight 8 bit or four 16 bit AX: AH.3 mP 8086 80186 80286 80386SL 80386 DX 80486 DX Pentium Address bus width 20 20 24 25 32 32 32 13. The program is given below: LXI H. 18 Four zeros at the least significant four bit positions are appended to the 16 bit segment register. AL BX: BH. Actual physical 20 bit address i s this 20 bit data plus the contents of the pointer register. CL DX: DH. making it 20 bit address.15 The ASCII code for decimal 0 is 0110000 and for? is 0111 111. DL 13. 00F1H LDA 00F0H CPI 0AH JNC QUE ADI 0011 0000 B MOV M.16 Refer to Table 13. 13. 00111111 B STOP: END 13.Here it is assumed that the interrupts are kept disabled during the execution of the sub routine. BL CX: CH. A JMP STOP QUE : MVI M.

3 A 4:1 multiplexer is shown in Fig. character ‘ ’ is not permitted. Z : OUT BIT). I2. A. There is o ne output Y.CHAPTER 14 14.1 (a) (b) (c) (d) (e) (f) 14. Y : OUT BIT). (b) For 3 input NAND gate ARCHITECTURE df _nand 3 OF NAND 3 IS BEGIN Y Ü NOT (A AND B AND C) AFTER 10 ns. END NAND 2. No. I2. IN STD LOGIC. END df nand 2. 1164 ALL. Two consecutive underscores are not allowed. Y : I N BIT. 14. I1. 14. END df_nand 3. (b) ENTITY NAND 3 IS PORT (A. Prob. No. B. Yes. Prob. Y: OUT STD LOGIC). 5 LIBRARY IEEE. END MULTI_4 . It contains all the allowed character s. 14. and I3 and two select inputs A and B. ENTITY MULT I 4 IS PORT (IO. I0 I1 I2 I3 AB Fig. ALL. 14.3 Y The entity declaration is LIBARY IEEE. No. I1. STD_LOGIC_1164. No.2 (a) Yes. Name of entity chosen is F_A 156 ¢ ¢ ¢ ¢¢ ¢ ¢ ¢ ¢ . USE IEEE.4 (a) For 2 input NAND gate ARCHITECTURE df_nand 2 OF NAND 2 IS BEGIN Z Ü NOT (X AND Y) AFTER 10 ns. Upper and lower case characters can be mixed. 14. USE IEEE STD LOGIC. END NAND 3. C : IN BIT. B . ENTITY NAND 2 IS PORT (X.3. Hyphen (–) is not allowed. starting character can not be a numeral. I3. It h as four data inputs I0.

CIN: IN STD_LOGIC. CINB. S3). S3. Q : OUT STD_LOGIC). END FULL_ADDER. X7 : IN STD L OGIC. BB. BB). END F_A. 14. S3. N6 : NAND2 PORT MAP (A. CIN. C OUT Ü (A AND B) OR (B AND CIN) OR (A AND CIN) AFT ER 10 ns. BEGIN I1 : INV PORT MAP (A. ALL. N5 : NAND4 PORT MAP (S1. S2. BB. COMPONENT INV PORT (P : IN STD_LOGIC. N1 : NAND3 PORT MAP (AB. S TD_LOGIC 1164. Y: OUT STD_LOGIC). B. X6. B. S COUT: OUT STD_LOGIC). X3 : IN STD LOGIC. B. CINB. S6). S6. X2. BB. 157 ¢ ¢ ¢ ¢ ¢ ¢ . END COMPONENT. N2 : NAND3 PORT MAP (AB. R : OUT STD_LOGIC). AR CHITECTURE FA_STR OF F_4 IS COMPONENT NAND 3 PORT (X1. B. CIN. COUT: OUT ST D_LOGIC) END F A. END FA_STR. CIN. S2). BEGIN S Ü ((NOT A) AND B AND (NOT CIN)) OR ((NOT A) AND (NOT B) AND CIN) OR (A AND (NOT B) AND (NOT CIN)) OR (A AND B AND CIN) AFTER 15 ns. S7 COUT). CIN: IN STD_LOGIC. END COMPONENT.6 LIBARY IEEE. S. S7). S1). N7 : NAND2 PORT MAP (B. CINB. N4 : NAND3 PORT MA P (A. X5. B. S7 : STD_LOGIC. SIGNAL AB. N8 : NAND2 PORT MAP (A. END COMPONENT. CIN. S1.ENTITY F A IS PORT (A. N3 : NAND3 PORT MAP (A. S5. CINB). AB). S4. S6. ARCHITECTURE FULL_ADDER OF F_A IS. END COMPONENT. S4). COMPONENT NAND2 PORT (X8. N9 : NAND3 PORT MAP (S5. S2. I3 : I NV PORT MAP (CIN. ENTITY F A IS PORT (A. S4. I2 : INV PORT MAP (B. X9 : IN STD_LOGIC. COMPONENT NAND 4 PORT (X4. Z: OUT STD_LOGIC). USE IEEE. S5). S).

A I1 AB B I2 CIN I3 N 1 BB CINB N2 S2 S1 N5 N3 S3 S N4 A B B CIN A CIN N6 S5 S4 N7 S6 N9 COUT N8 S7 Fig. 14. Prob.5 158 .

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