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# EE133 Analog Communication Laboratory

Phase Locked Loop (PLL) Basics

**Where would you find a PLL?
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Any way of synchronizing two signals? High Q oscillator (difficult to modulate) and low Q oscillator (low frequency stability), any way of transferring some of the high Q oscillator characteristics? Any way of generating multiples or fractional frequencies using a single signal as a reference? Any easy method of generating and demodulate FM signals?

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the loop acquires lock and input and output frequencies have a fixed phase relationship while tracking each other.PLL Block Diagram Basic parts Phase detector : compares phase between the VCO output and the incoming signal. 2 . Finally. VCO: simply generates a signal whose frequency is some function of the control voltage. Produces an output that is some function of the phase difference. PLL’s Basic Idea Phase detector drives the VCO frequency is a way such that the phase difference decreases.

XOR gate. Implemented as: four quad multiplier. Basic Components Voltage controlled oscillator (VCO). Transfer function: KVCO/s [radians/(V•s)] 3 . Frequency is the first derivative of phase. state machine.Basic Components Phase detector Transfer function: KΦ [V/radians].

Determines loop order and loop dynamics.Basic Components Low pass filter Removes high frequency components coming from the phase detector. Putting All Together Linear model Transfer function : Error function : θo K Φ KVCO F ( s ) = θ i s + K Φ KVCO F ( s ) θe s = θ i s + K Φ KVCO F ( s ) s 2θ i s + K Φ KVCO F ( s ) Loop gain : K Φ KVCO F ( s ) Steady state error : lim sθ e = s →0 4 .

Simplicity and stability. We need some way of decoupling all these factors. overshoot).Selecting your filter No filter. Useful if you have a huge bandwidth available and no other constraints. Example: harmonic locked oscillators Selecting your filter One pole RC filter Second order system Wide loop bandwidth (small steady state error) may lead to a poor transient response (ripple. First order system. 5 . Steady state error and bandwidth are tightly linked.

Selecting your filter One pole one zero RC filter Small gain→ small damping gain→ As gain increases damping first decreases but then increases again. one zero) passive filter. the transfer function becomes: ( sτ 2 + 1) (τ 1 + τ 2 ) H ( s) = (1 + KVCO K Φτ 2 ) KVCO K Φ 2 + s +s (τ 1 + τ 2 ) (τ 1 + τ 2 ) KVCO K Φ ωn = 1 KVCO K Φ τ1 + τ 2 ⎛ ⎝ ⎞ ⎟ ⎟ VCO K Φ ⎠ 1 ξ = ω n ⎜τ 2 + 2 ⎜ K τ 1 = R1C1 τ 2 = R2C1 2 s 2 + 2ξω n +ωn 6 . p1 = z1 = 1 2π ( R1 + R2 )C 1 2πR2C Second order system with stabilizing zero For a (one pole. good bandwidth easy to design. Good transient response.

Root Locus Single pole low pass filter 7 .Second order system Parameters: Natural frequency: ωn Damping coefficient: ξ Related to: How fast your system should settle. How much overshoot you are willing to tolerate.

Tracking/Hold-in range: range of frequencies over Tracking/Holdwhich the PLL can track and follow the input signal once it has acquired locked. Usually: Lock in range ≤ Tracking range 8 .Root Locus One pole one zero LP filter Acquiring Lock Some important parameters: Capture/lock-in range: range of frequencies over Capture/lockwhich the PLL is able to acquire lock given that it was initially unlocked.

Tracking Range Basically given by the loop gain and phase detector range. Δω LOCK = K Φ KVCO (Phase detector range in rad) Watch out for finite output range of real-life blocks.Acquiring Lock Pull-in range: frequency range over which the PLL will always lock. 9 . Pull-out range: maximum frequency step that can be applied without losing lock.

Capture Range Involves a non-linear process where the linear model breaks down.0MHz Capture Range Non-linear response 10 .0MHz Transient from fi=1. Transient from fi=1.

A=1 (no gain) “summing node” in the O/A-like model of PLL Again.Capture Range What is going on? PLL Simulation SPICE model The F(s) is simply an RC. this block is indeed a multiplier (see SPICE deck) 11 . as in O/A model.

FM Modulator 12 . PLL Applications FM demodulator. but it is very efficient (short simulation time).PLL simulation Time domain simulation (SPICE): very small time step required (long simulation time). Frequency domain simulators: initial conditions may be difficult to set.

one zero filter.5 KHz Voice signal: 6 KHz Modulation index=7.9 Krad/(V•s) Phase detector: 5/4π V/rad (PC2) One pole.PLL Applications Frequency Synthesis Simple Design Example FM signal: 450 KHz Frequency deviation: ±7.25 VCO: 450 KHz ±10 KHz (VC=25VDC)→KVCO=41.5KHz/6KHz=1. 13 . Minimize overshoot.

5KHz during the positive and negative cycle. This give us a ωn= 48Krad/s. Simple Design Example This means we have only 84 μs to acquire lock.5KHz and 442. Let C=1.Simple Design Example VCO range of 450KHz ± 10KHz ensure the incoming signal is within the capture and tracking range of a MC14046. Check damping factor →ξ=1. Assume a 6KHz square wave audio signal that shifts the VCO to 457.5nF and R3=10R4→ R3=4. this mean a single time constant is about 21 μs. Assume 84μs is about 4 time constants.3K Ω and R4=430Ω.47 OK 3dB close loop bandwidth is about: 22KHz 14 .

15 . Bandwidth is usually limited to about one tenth of your reference frequency. Leave enough margin for part to part variations. Phase detector can also be non linear.Final Comments PLL model usually assumes linearity. VCO tuning range is usually non linear.