Code No: R05311403

Set No. 1

III B.Tech I Semester Supplimentary Examinations, February 2008 SWITCHING THEORY AND LOGIC DESIGN (Mechatronics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Explain different methods used to represent negative numbers in binary system. [6] (b) Perform the subtraction with the following unsigned binary numbers by taking the 2’s complement of the subtrahend. [5 ×2 = 10] i. ii. iii. iv. v. 11010 - 10110 11011 - 1001 100 - 110100 1010101 - 1010101 11 - 1101

2. (a) Express the following functions in sum of minterms and product of maxterms. [8] i. (xy + z) ( y + xz) ii. B’D + A’D + BD (b) Obtain the complement of the following Boolean expressions. i. ii. iii. iv. AB’C + AB’D + A’B’ A’B’C + ABC? + A’B’C’D ABCD + ABC’D’ + A’B’CD AB + ABC’ [8]

3. (a) Differentiate prime implicant and non prime implicant, essential prime implicant and non essential prime implicant. [8] (b) Reduce the following function using K- map and identify prime implicants and essential prime implicants F= m(0, 1, 2, 3, 6, 7, 13, 15) [8] 4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates. (b) Draw the logic diagram of a single bit comparator. 5. Write a brief note on: (a) Architecture of PLDs (b) Capabitation and the limitations of threshold gates. 6. (a) Compare synchronous & Asynchronous circuits (b) Design a Mod-6 synchronous counter using J-K flip flops. 1 of 2 [6+10] [8+8] [12+6]

Code No: R05311403

Set No. 1

7. (a) Convert the given Mealy machine to Moore Machine. Present State Next State Output x=0 x=1 P R,0 Q, 0 Q P,1 S,0 R Q,1 P,1 S S,1 R,0 (b) Give the state diagram of a binary serial adder and design the circuit for carry output using D - flip-flop. [8+8] 8. For the ASM chart given 8:

Figure 8 (a) Draw the state diagram. (b) Design the control unit using D flip-flops and a decoder. ⋆⋆⋆⋆⋆ [8+8]

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Code No: R05311403

Set No. 2

III B.Tech I Semester Supplimentary Examinations, February 2008 SWITCHING THEORY AND LOGIC DESIGN (Mechatronics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Binary. (a) 101116 (b) ABCD16 (c) 72348 (d) 77668 (e) 12810 (f) 72010 . [3+3+3+3+2+2]

2. (a) Draw the NAND logic diagram that implements the complement of the following function. [8] F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12) (b) Obtain the complement of the following Boolean expressions. i. AB + A(B + C) + B’(B + D) ii. A + B + A’B’C (c) Obtain the dual of the following Boolean expressions. i. A’B + A’BC’ + A’BCD + A’BC’D’E ii. ABEF + ABE’F’ + A’B’EF [4] [4]

3. Apply Branching method to simplify the following function F (A, B, C, D) = M (0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30). [16] 4. (a) Realize Full Adder Using two half adders and logic gates. (b) Draw the block diagram of BCD adder using two 4-bit parallel binary adders and logic gates. [4+12] 5. (a) Derive the PLA programming table for the combinational circuit that squares a 3 bit number. (b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate the PAL programming table for the circuit. [8+8]

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Code No: R05311403 Inputs y 0 0 1 1 0 0 1 1 Output B C 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1

Set No. 2
D 0 1 1 1 0 1 0 1

x 0 0 0 0 1 1 1 1

z A 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0

6. Explain in detail the following: (a) Johnson counter (b) Serial binary adders (c) Pulse mode & level mod sequential ckts. [5+5+6]

7. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D - flip-flops. [4+4+8] 8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8] ⋆⋆⋆⋆⋆

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Code No: R05311403

Set No. 3

III B.Tech I Semester Supplimentary Examinations, February 2008 SWITCHING THEORY AND LOGIC DESIGN (Mechatronics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Perform the following using BCD arithmetic. Verify the result. [2 X 4 = 8] i. 127310 + 958710 ii. 776210 + 383810 (b) Convert the following. i. ii. iii. iv. 97710 = ( )16 65710 = ( )8 75410 = ( )2 100116 = ( )10 [8] [4 X 2 = 8]

2. (a) Simplify the following Boolean expressions to minimum no. of literals. i. ii. iii. iv. i. ii. iii. iv. x’y’ + xy + x’y xy’ + y’z’ + x’z’ x’ ? + xy + xz’ + xy’z’ (x + y)(x + y’)

(b) Obtain the complement of the following Boolean expressions. AB + A(B + C) + B‘(B + D) A + B + A‘B’C A’B + A‘BC’ + A’BCD + A‘BC‘D’E ABEF + ABE‘F’ + A‘B’EF

[8]

3. Minimize the following function using tabular minimization and verify the same with K-map minimization F (A, B, C, D) = m(0, 1, 2, 5, 7, 8, 9, 10, 13, 15). [8+8] 4. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five NAND gates and the EXCLUSIVE ?OR circuit made by four NAND gates as shown in figure 4 Hazard or Dynamic Hazard? [16]

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Code No: R05311403

Set No. 3

Figure 4 5. (a) Specify the size of a ROM (number of words and numbers bits per word) that will accommodate the truth table of a BCD to seven segment decoder with an enable input. (b) Write a brief note on programmable logic devices. [8+8]

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter. (b) Compare synchronous & Asynchronous. [10+6]

7. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D - flip-flops. [4+4+8] 8. (a) Draw the ASM chart for the following state transistion, start from the initial state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other wise go to T3 . (b) Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. [8+8] ⋆⋆⋆⋆⋆

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Code No: R05311403

Set No. 4

III B.Tech I Semester Supplimentary Examinations, February 2008 SWITCHING THEORY AND LOGIC DESIGN (Mechatronics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. Convert the following to Decimal and then to Octal. (a) 423416 (b) 125F16 (c) 100100112 (d) 101111112 (e) 39210 (f) 77910 2. (a) Simplify the following Boolean functions. i. ii. iii. iv. i. ii. iii. iv. x’yz + x’yz’ + xy’z’ + xy’z x’yz + xy’z’ + xyz + xyz’ x’z + x’y + xy’z + yz x’y’z’ + x’yz’ + xy’z’ + xy’z + xyz’ [8] A’C’ + ABC + AC’ (x’y’ + z)’ + z + xy + wz A’B(D’ + C’D) + B(A +A’CD) (A’ + C)(A’ + C’)(A + B + C’D) [3+3+3+3+2+2] [8]

(b) Obtain the complement of the following Boolean expressions.

3. Apply Branching method to simplify the following function F (A, B, C, D) = M (0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30). [16] 4. (a) Implement the full adder function by using two 4:1 multiplexers. (b) What is a decoder? How do you convert a decoder to a Demultiplexer.[10+6] 5. Write a brief note on: (a) Architecture of PLDs (b) Capabitation and the limitations of threshold gates. [8+8]

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter. (b) Compare synchronous & Asynchronous. [10+6]

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Code No: R05311403

Set No. 4

7. (a) A clock mode sequential circuit has to provide z=1 whenever the input completes the Sequence of pulses 1010 and overlapping is allowed. Draw the state diagram and obtain minimal state using partition method. (b) Draw the state diagram of mod-8 Up - Down counter in Moore model and obtain its state table. [8+8] 8. (a) For the given ASM chart obtain its equivalent state diagram 8. (b) Design the circuit using multiplexers. (c) Also design the circuit using D-Flip-flop per state. [4+8+6]

Figure 8 ⋆⋆⋆⋆⋆

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