Code No: RR310401

Set No. 1

III B.Tech I Semester Supplimentary Examinations, February 2008 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ ¯ ¯ 1. (a) Design a CMOS transistor circuit with the functional behavior f(X) = (A + B)(C + D) (b) Distinguish between static and dynamic power dissipation of a CMOS circuit? Derive the expression for dynamic power dissipation? [8+8] 2. (a) Draw the circuit diagram of two-input 10K ECL OR gate and explain the circuit? (b) Explain the difference in program structure of VHDL and any other procedural language? Give an example? [8+8] 3. (a) Write a data-flow style VHDL program for the following functions? F(S) = A⊕B⊕CI F(CO ) = AB + A⊕CI +BCI [4+4]

(b) Design the logic circuit and write a data-flow style VHDL program for the following function? [8] F (X) = ΣA,B,C,D (3,5,6,7,13) + d(1,2,4,12,15) 4. (a) Using two 74×138 decoders design a 4 to 16 decoder? (b) Write a data flow style VHDL program for the above design? [8+8]

5. Design a combinational logic circuit that counts the number of ones in a 24-bit register? Write a VHDL program for the above implementation? [8+8] 6. (a) Draw the logic diagram of 74×74 IC and explain the operation? Develop the VHDL model for this IC? (b) With the help of logic diagram discuss PAL16R8? [8+8]

7. (a) Design an 8-bit parallel-in and parallel-out shift register and explain the operation? (b) What is the difference between ring counter and Johnson ring counter? Design a self-correcting 4-bit, 4-state ring counter with a single circulating 0 using 74×194? [8+8] 8. (a) Explain the internal structure of 64Kx1 DRAM? With the help of timing waveforms discuss DRAM access? (b) Explain XC4000 programmable interconnect structure? ⋆⋆⋆⋆⋆ [8+8]

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Code No: RR310401

Set No. 2

III B.Tech I Semester Supplimentary Examinations, February 2008 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Explain the effect of floating inputs on CMOS gate? (b) Explain how a CMOS device is destroyed? (c) What is the difference between transmission time and propagation delay? Explain these two parameters with reference to CMOS logic? [4+4+8] 2. (a) Draw the circuit diagram of two-input 10K ECL OR gate and explain the circuit? (b) List out different categories of characteristics in a TTL data sheet? Discuss electrical and switching characteristics of 74LS00. [8+8] 3. Design the logic circuit and write a data-flow style VHDL program for the following functions? (a) F (P) = ΠA,B,C,D (1,7,9,13,15) (b) F (Y) = ΣA,B,C,D (1,4,5,7,12,14,15) + d(3,11) [8+8]

4. (a) Draw the digits created by 74x49 seven-segment decoder for non-decimal inputs 1010 through 1111? (b) Realize the following expression using 74×151 IC ¯ ¯ ¯ f (X) = ABC + ABC + AB C [8+8]

5. (a) Design a full subtractor with logic gates and write VHDL data flow program for the implementation of the above subtractor? [4+4] (b) Design a 4-bit carry look ahead adder using gates and write data-flow VHDL program? [8] 6. With the help of logic diagram explain the function of PAL16R6? Explain how an 8-bit synchronous binary counter can be realized with this device? [8+8=16] 7. (a) Draw the logic diagram of 74x194 and explain the operation? (b) Write data-flow style VHDL program for the above logic circuit? [8+8]

8. (a) Explain the internal structure of 64Kx1 DRAM? With the help of timing waveforms discuss DRAM access? (b) Explain XC4000 programmable interconnect structure? ⋆⋆⋆⋆⋆ [8+8]

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Code No: RR310401

Set No. 3

III B.Tech I Semester Supplimentary Examinations, February 2008 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Design CMOS transistor circuit for 2-input AND gate? With the help of function table explain the circuit? (b) Draw the resistive model of a CMOS inverter and explain its behavior for LOW and HIGH outputs? [8+8] 2. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL gate? Draw the interface circuit and explain the operation? (b) Draw the circuit diagram of basic CMS gate and explain the operation?[10+6] 3. Design a logic circuit to detect prime number of a 5-bit input? Write the structural VHDL program for the above design? [8+8] 4. With the help of logic diagram explain 74×157 multiplexer? Write the data flow style VHDL program for this IC? [8+8] 5. (a) Design a full subtractor with logic gates and write VHDL data flow program for the implementation of the above subtractor? (b) Using the above subtractor design a 8-bit ripple subtractor and write the corresponding VHDL program? [8+8] 6. (a) Design a conversion circuit to convert a T flip-flop to J-K flip-flop? Write a data-flow VHDL program? (b) With the help of logic diagram discuss PAL16R8? 7. (a) Draw the logic diagram of 74x194 and explain the operation? (b) Design a serial binary adder? Develop the VHDL program for simulating serial binary adder? [8+8] 8. (a) Explain the necessity of two-dimensional decoding mechanism in memories? Draw MOS transistor memory cell in ROM and explain the operation? (b) Discuss the operation of IOB in XC4000 FPGA with a neat sketch? ⋆⋆⋆⋆⋆ [8+8] [8+8]

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Code No: RR310401

Set No. 4

III B.Tech I Semester Supplimentary Examinations, February 2008 DIGITAL IC APPLICATIONS (Electronics & Communication Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Distinguish between static and dynamic power dissipation of a CMOS circuit? Derive the expression for dynamic power dissipation? (b) Compare HC, HCT, VHC and VHCT CMOS logic families with the help of input specifications with VCC from 4.5V to 5.5V? [10+6] 2. (a) Compare CMOS, TTL and ECL with reference to logic levels, DC Noise margin, propagation delay and fanout? (b) List out different categories of characteristics in a TTL data sheet? Discuss electrical and switching characteristics of 74LS00? [8+8] 3. (a) Explain with example the syntax and the function of the following VHDL statements? i. Process statement ii. Case statement [4+4]

(b) Design the logic circuit and write a data-flow style VHDL program for the following function? F (Q) = ΣA,B,C,D (0,2,5,7,8,10,13,15) + d(11) [8] 4. (a) Design a 16-bit comparator using 74×85s? (b) Write a behavioral VHDL program to compare 16-bit signed and unsigned integers? [8+8] 5. (a) Design a full subtractor with logic gates and write VHDL data flow program for the implementation of the above subtractor? (b) Using the above subtractor design a 8-bit ripple subtractor and write the corresponding VHDL program? [8+8] 6. (a) Differentiate between ripple counter and synchronous counter? Design a 4-bit counter in both modes and estimate the propagation delay? (b) It is necessary to generate 6 control lines in regular intervals sequentially. Design the necessary circuit using 74×163 and 74×138? [8+8] 7. (a) Design an 8-bit serial-in and serial-out shift register? Write the data-flow style VHDL program for this shift register? (b) Define clock skew? Explain how clock skew leads to incorrect outputs in synchronous circuits? Design one logic circuit that minimizes clock skew? [8+8] 1 of 2

Code No: RR310401

Set No. 4
[8+8]

8. (a) Explain the internal structure of 64Kx1 DRAM? With the help of timing waveforms discuss DRAM access? (b) Explain XC4000 programmable interconnect structure? ⋆⋆⋆⋆⋆

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