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**3, JUNE 2007 1495
**

Digital Repetitive Control of a Three-Phase

Four-Wire Shunt Active Filter

Robert Griñó, Member, IEEE, Rafael Cardoner, Ramon Costa-Castelló, Senior Member, IEEE, and Enric Fossas

Abstract—Shunt active power ﬁlters have been proved as useful

elements to correct distorted currents caused by nonlinear loads

in power distribution systems. This paper presents an all-digital

approach based on a particular repetitive control technique for

their control. Speciﬁcally, a digital repetitive plug-in controller for

odd-harmonic discrete-time periodic references and disturbances

is used for the current control loops of the active ﬁlter. This

approach does not introduce a high gain at those frequencies for

which it is not needed and, thus, improves robustness of the

controlled system. The active power balance of the whole system

is assured by an outer control loop, which is designed from

an energy-balancing perspective. The design is performed for a

three-phase four-wire shunt active ﬁlter with a full-bridge boost

topology. Several experimental results are also presented to show

the good behavior of the closed-loop system.

Index Terms—Active power ﬁlters, digital repetitive control,

three-phase four-wire power distribution systems, unbalanced

systems.

I. INTRODUCTION

E

LECTRICAL power quality has been, in recent years,

an important and growing problem because of the pro-

liferation of nonlinear loads such as power electronic convert-

ers in typical power distribution systems. Particularly, voltage

harmonics and power distribution equipment problems result

from current harmonics produced by nonlinear loads. This fact

has led to the proposal of more stringent requirements regarding

power quality like those speciﬁcally collected in the standards

IEC-61000-3-{2,4} and IEEE-519.

Much work has been done in the area of active ﬁlter control

[1]–[7]. Nevertheless, it seems that, as a conclusion, the main

point is the need for high-gain current control loops [2], [5],

[7]. Perhaps, the easiest way to obtain them is to use some

kind of hysteresis controller (or relay controller) [8]. However,

this controller has the disadvantage of a varying switching

frequency, which produces a continuous harmonic spectrum.

This problem is not present in ﬁxed-frequency pulsewidth-

modulated schemes that have their high-frequency content

around switching frequency harmonics. Therefore, it would

be interesting to develop digital controllers with pulsewidth

Manuscript received August 17, 2005; revised June 8, 2006. This work was

supported in part by the Ministerio de Educación y Ciencia (MEC) under

Project DPI2004-06871-C02-02.

The authors are with the Institut d’Organització i Control de Sistemes In-

dustrials (IOC), Escola Tècnica Superior d’Enginyeria Industrial de Barcelona

(ETSEIB), Universitat Politècnica de Catalunya, 08028 Barcelona, Spain

(e-mail: roberto.grino@upc.edu; rafel.cardoner@upc.edu; ramon.costa@

upc.edu; ramon.costa-castello@ieee.org; enric.fossas@upc.edu).

Color versions of one or more of the ﬁgures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TIE.2007.894790

modulators (PWMs) for the active ﬁlter system. Fulﬁlling these

requirements, there is a technique, called repetitive control, that

allows control loops to be designed with a high gain at the

harmonic frequencies of a fundamental one. This methodology

arose fromthe Internal Model Principle (IMP) [5], [9] in control

theory and is particularly suitable for periodic-signal tracking

problems and periodic-signal disturbance rejection problems.

Therefore, the necessary high-gain requirements of current

control loops in active ﬁlters can be met with this approach.

Particularly, this paper uses the repetitive control technique to

design high-gain digital controllers for the current loops of the

three-phase four-wire active ﬁlter.

The repetitive control concept and technique has been largely

used in different control areas such as compact disk and hard

disk arm actuators [10], [11], robotics [12], electro-hydraulics

[13], torque vibration suppression in motor control [14] and

power electronics applications like, for example, unity power

factor rectiﬁers [15], pulsewidth-modulated inverters [16]–[19]

and uninterruptible power supply (UPS) systems [20].

Normally, in power electronic systems, the reference and

disturbance signals appearing in control loops (in this case,

source and load currents, respectively) are, in steady state,

periodic signals with only odd harmonics in their Fourier series

expansion. If the usual repetitive control methodology is used

in these systems, the open-loop transfer function includes a

high gain in all the harmonic frequencies [21]. However, it

is not necessary to include a high gain at even-harmonic fre-

quencies; it only means a waste of control effort and a reduction

of system robustness without improving system performance.

Besides, the introduction of a high gain at even-harmonic fre-

quencies generally implies that the open-loop transfer function

includes an integral term that corresponds to zero frequency

harmonic. This fact, together with the inclusion of sensors that

use transformers

1

in the loop, gives closed loops that are not

internally stable. Hence, traditional repetitive controllers must

be precluded in systems with pure derivative terms in order to

obtain internally stable closed-loop systems.

This paper designs and implements odd-harmonic digital

repetitive current controllers [22] for a three-phase shunt active

ﬁlter that only introduces a high gain where it is needed, i.e.,

at odd-harmonic frequencies. Furthermore, an outer voltage

control loop that assures the active power balance of the whole

system is designed from an energy-balancing point of view,

and the zero dynamics of the system is characterized. It is

important to emphasize that the designed control architecture

1

The dynamic model of the transformer has a pure derivative term, i.e.,

a transmission zero in s = 0.

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1496 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 3, JUNE 2007

only uses three sensors for source currents, unlike the usual

control schemes that double this number, sensing the load

currents and the active ﬁlter input currents. Then, the task of the

current loops is to maintain sinusoidal-shape source currents

in phase with the line-to-neutral voltages in spite of the corre-

sponding load currents. From a control theory point of view,

this approach matches a disturbance attenuation problem, and

from this perspective, the current controllers are designed using

the aforementioned linear control design technique. In addition,

the computational cost of the overall controller is reduced

in front of the usual six current sensors architecture because

the proposed controller structure does not need a load current

analysis module.

This paper is organized as follows. Section II introduces the

problem, the control objectives, and the model of the system.

Section III shows the multiloop controller design with the

underlying theoretical aspects and the steady-state analysis.

Section IV describes the experimental setup and gives some

implementation issues. Section V presents some selected ex-

perimental results that show the good behavior of the whole

system. Finally, Section VI summarizes the results of this paper.

II. PROBLEM FORMULATION

A. Physical Model of the Boost Converter

Fig. 1 presents the complete system architecture. A three-

phase mixed linear and nonlinear load is connected to the

power source; in parallel, a three-phase four-wire active ﬁlter is

applied in order to fulﬁll the desired behavior, i.e., to guarantee

a unity power factor and a three-phase balanced current set in

the network side. A three-leg boost converter with an ac neutral

wire connected directly to the midpoint of the dc-bus is used

as the active ﬁlter. The averaged (at the switching frequency)

model of the boost converter is given by

L

k

di

f,k

dt

= −r

L,k

i

f,k

−v

1

d

k

−v

2

(d

k

−1) +v

s,k

(1)

C

1

dv

1

dt

= −r

C,1

v

1

+

¸

k

i

f,k

d

k

(2)

C

2

dv

2

dt

= −r

C,2

v

2

+

¸

k

i

f,k

(d

k

−1) (3)

where d

k

is the duty ratio of the k-phase,

2

i

f,k

are the induc-

tor currents, v

1

and v

2

are the dc capacitor voltages, v

s,k

=

V

s

√

2 sin(ω

r

t +φ

k

) are the voltage sources that represent the

three-phase ac-line source with φ

a

= 0, φ

b

= −2π/3, and φ

c

=

−4π/3, L

k

are the converter inductors, r

L,k

are the inductor

parasitic resistances, C

1

and C

2

are the converter capacitors,

and r

C,1

and r

C,2

are the parasitic resistances of the capacitors.

The control variables d

k

take their values in the closed real in-

terval [0, 1] and represent the averaged value of the pulsewidth-

modulated control signal injected to the actual system.

2

k ∈ {a, b, c}.

Fig. 1. Three-phase four-wire parallel active ﬁlter connected to the network-

load system.

B. Load Description

The load current, in steady state, is usually a periodic signal

with only odd harmonics in its Fourier series expansion, so the

current in each phase can be written as

i

l,k

=

¸

n

a

n,k

sin (ω

r

(2 · n + 1)t +φ

k

)

+ b

n,k

cos (ω

r

(2 · n + 1)t +φ

k

) (4)

where a

n,k

, b

n,k

∈ R are the real Fourier series coefﬁcients of

the k-phase current.

3

C. Control Objectives

The active ﬁlter goals are to assure that the load is seen

as a resistive one and to balance the load current set. These

goals can be stated

4

as i

∗

s,k

= I

∗

d

sin(ω

r

t +φ

k

), i.e., all the

source currents have a sinusoidal shape in phase with the

corresponding line-to-neutral voltage and the same amplitude.

Another collateral goal that is necessary for a correct operation

of the converter is to assure a constant average value of the dc-

bus voltage,

5

i.e., v

1

+v

2

∗

0

= V

d

, where V

d

must fulﬁll the

boost condition. It would also be desirable that this voltage

would be almost equally distributed among both capacitors

(v

1

≈ v

2

).

These two objectives deﬁne a nonstandard control problem:

the second one is a regulation objective for the mean value of

v

1

+v

2

, but the ﬁrst one is not a tracking speciﬁcation because

only a shape and not a signal is deﬁned, that is, I

∗

d

is not

known a priori, and it must take the adequate value to maintain

the power balance of the whole system. This special form of

the problem speciﬁcations implies the particular structure of the

controller loops described in the next section.

D. Rewriting the Equations

It is a standard for this kind of systems to linearize the

current dynamics by the state feedback α

k

=v

1

d

k

+v

2

(d

k

−1).

3

In a balanced load, a

n,k

=a

n,j

and b

n,k

=b

n,j

∀k=j; k, j ∈{a, b, c}.

4

x

∗

represents the steady-state value of signal x(t).

5

x

0

means the dc value, or mean value, of signal x(t).

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GRIÑÓ et al.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1497

Fig. 2. Controller scheme showing one of the current control loops (inner)

and the voltage (or energy) control loop (outer).

Moreover, the change of variables i

f,k

= i

f,k

, E

C

=

1/2(C

1

v

2

1

+C

2

v

2

2

), D = C

1

v

1

−C

2

v

2

yields two more mean-

ingful variables, namely: E

C

, which is the energy stored in the

converter capacitors, and D, which is the charge unbalance

between them. Assuming that the two dc-bus capacitors are

equal (C=C

1

=C

2

, r

C

=r

C,1

=r

C,2

), the system dynamics in

the new variables results in

L

k

di

f,k

dt

= −r

L,k

i

f,k

+v

s,k

−α

k

(5)

dE

c

dt

= −

2r

C

E

c

C

+

1

C

¸

k

i

f,k

α

k

(6)

dD

dt

= −

r

C

C

D +

1

C

¸

k

i

f,k

. (7)

It is important to note that the state feedback, together with

the change of variables, results in a state and input diffeomor-

phism, provided that v

1

+v

2

= 0. In addition, (7) is also linear.

Taking beneﬁt from the fact that current equations (5) are linear

and decoupled, a linear controller is designed for each one to

force a sinusoidal shape in the network current (see Fig. 2). The

sine-wave amplitude is given by an outer digital control loop

to fulﬁll the appropriate active power balance for the whole

system. This balance is achieved if the energy

6

stored in the

active ﬁlter capacitors E

c

is equal to its reference value E

d

c

.

The full control scheme for one phase current is depicted in

Fig. 2. The speciﬁc controller designs will be presented in

Sections III-A and B. It is worth remarking that, under the

fulﬁllment of current speciﬁcations, (7) is decoupled as well.

The corresponding zero dynamics is studied in Section III-C.

III. CONTROL DESIGN

A. Current Loop

The dynamics of (5) can also be described by

G

p

(s) =

Y

k

(s)

α

k

(s)

=

−1/r

L

r

s + 1

. (8)

6

A similar reasoning can be done with the dc-bus capacitor voltages, as it is

implied by the change of the variables used.

Fig. 3. Basic block diagram of the digital repetitive control loop.

Fig. 4. Digital repetitive current control loop.

This continuous-time transfer function is sampled with a

zero-order hold at a sampling frequency equal to the switching

frequency of the converter giving, as a result, G

p

(z), and

then this function is taken as a plant for the digital current

controller design, as can be seen in Fig. 4. An odd-harmonic

digital repetitive controller [22] is designed for tracking and

disturbance rejection purposes.

Odd-harmonic repetitive control consists of placing a basic

block (internal model) into the loop (Fig. 3), which introduces

an inﬁnite gain at a certain frequency and all its odd harmonics.

This basic block is used as a basis to feed back a delay of

N/2 ∈ Nsampling periods, where N = T

r

/T

s

, T

r

is the period

of the periodic signal to be tracked or rejected, and T

s

is the

sampling period. It can be proven that this internal model has

poles at the fundamental frequency and at its odd-harmonic

frequencies [22].

Repetitive controllers are usually implemented in a “plug-in”

fashion, i.e., the repetitive compensator is used to augment an

existing nominal controller G

c

(z) (Fig. 4). This nominal com-

pensator is designed to stabilize the plant G

p

(z) and provides

disturbance attenuation across a broad frequency spectrum.

This scheme was ﬁrst introduced by Inoue et al. [23]. The con-

troller is composed of the internal model and a linear system

G

x

(z), which is designed to ensure closed-loop stability. In

practical implementations, a null-phase ﬁnite-impulse response

(FIR) low-pass ﬁlter H(z) is introduced into the basic block

in order to reduce the gain at those frequencies where system

behavior is not properly modeled (Fig. 3). It is important to

emphasize that the FIR ﬁlter H(z) reduces the repetitive loop

gain to ﬁnite values for all the frequencies, giving it a general

low-pass shape.

The closed-loop system of Fig. 4 is stable if the following

conditions are fulﬁlled [22].

1) The closed-loop system without the repetitive controller

is stable, i.e., G

o

(z) = G

c

(z)G

p

(z)/(1 +G

c

(z)G

p

(z))

is stable.

2) H(z)

∞

< 1.

3) 1 −G

o

(z)G

x

(z)

∞

< 1, where G

x

is a design ﬁlter to

be chosen.

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1498 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 3, JUNE 2007

These conditions are fulﬁlled by a proper design of G

c

(z)

and G

x

(z), which is described as follows.

• Condition 1: It is advisable to design the controller G

c

(z)

with a high-enough robustness margin.

• Condition 2: There is no problem with the causality of

H(z) because it is series connected with the delay z

−N/2

and the repetitive loop will be executed as a whole in a

controller real-time operation.

• Condition 3: A trivial structure that is often used is [24]

G

x

(z) = k

r

G

o

(z)

−1

. This structure can only be used

if G

o

is a minimum-phase transfer function. Otherwise,

other techniques should be applied in order to avoid

closed-RHS plane zero–pole cancellations [24]. Moreover,

as said before, there is no problem with the no causality

of G

x

(z).

As argued in [25], k

r

must be designed while looking

for a tradeoff between robustness and transient response.

B. Energy Shaping (Voltage Loop)

Without taking into account the active ﬁlter losses, all the

power obtained from the net is due to load requirements, and

under this ideal assumption, the following constraint holds:

P

net

=

¸

k

I

d

√

2V

s

sin

2

(ω

r

t +φ

k

)

=

¸

k

v

s,k

i

l,k

= P

load

. (9)

However, as I

d

is designed locally constant in order to fulﬁll

the harmonic requirements, it is not possible to satisfy this

requirement instantaneously. What can be achieved is an energy

compensation within one period

t

t−T

r

P

net

=

t

t−T

r

P

load

(10)

that yields the I

d

ideal value.

Fromthe power ﬂowpoint of view, the converter redistributes

the power ﬂow within one period in order to assure the stated

power balance. Hence, the total energy stored in the converter

(E

T

) does not suffer variations within a period, i.e.,

t

t−T

r

˙

E

T

= 0. (11)

The stored energy in the converter can be decomposed into

the energy stored in the inductors (E

L

=

¸

k

(1/2)L

k

(i

f,k

)

2

)

and the energy stored in the capacitors (E

c

). Additionally, it

is important to note that some energy is lost in the parasitic

resistors of the inductors and the capacitors.

Presuming the currents’ steady state and discarding the

parasitic resistance of the inductors and capacitors, it can be

easily proven that independent of the value of I

d

and the

Fig. 5. Simpliﬁed 50-Hz model with a PI controller.

load currents, the variation of energy in the inductors in one

period is zero. Thus,

t

t−T

r

˙

E

T

=

t

t−T

r

˙

E

c

. (12)

Using (6) and (12) results in

t

t−T

r

˙

E

T

= E

T

(t) −E

T

(t −T

r

) =

¸

k

√

2V

s

π(I

d

−a

0,k

)

ω

.

This energy balance can be seen as a linear discrete-time system

(with the sample time T

r

) with an input I

d

and a constant

disturbance a

0,k

, i.e.,

E

T

(z) =

1

z −1

√

2V

s

π

ω

3Id(z) −

¸

k

a

0,k

. (13)

As the value of a

0,k

is usually unknown but constant in steady

state, it can be considered as a step disturbance in the closed-

loop system (see Fig. 5). Thus, a classical PI controller will reg-

ulate E

T

to the desired value E

d

T

without steady-state error, i.e.,

I

d

(z) =

k

p

+k

I

z + 1

z −1

E

d

T

(z) −E

T

(z)

. (14)

The losses in the inductor and capacitor parasitic resistances

can be considered as an additive complex-dynamics disturbance

in the voltage closed-loop system. However, as the experimen-

tal results will show, it is not worth taking these losses into

account in the design of the voltage loop.

It is important to note that, from (12), the control deﬁned

for E

T

can be applied to E

c

. From the practical point of view,

this is of great relevance because E

c

can be directly calculated

by means of measuring the dc-bus voltage (v

1

+v

2

). If this

assumption is used, the voltage loop design uses a steady-state

condition in the current loop.

C. Zero Dynamics

In this section, the complete system zero dynamics is charac-

terized while assuming that i

s,k

I

∗

d

sin(ω

r

t +φ

k

).

The charge unbalance is described in (7). This equation is

a linear differential equation with an unknown input

¸

k

i

f,k

.

As γ

= (r

C

/C) > 0, the system is stable, and if

¸

k

i

f,k

= 0

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GRIÑÓ et al.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1499

(balanced load), then it tends to zero in steady state. Oth-

erwise, as the input is a periodic signal, the output is also

periodic. Then,

D

∗

(t) =

1

C

¸

k

¸

n

−

a

n,k

ς

n

sin (ω

r

(2 · n + 1)t +φ

k

+δ

n

)

−

b

n,k

ς

n

cos

ω

r

(2 · n + 1)t +φ

k

+δ

n

−

π

2

(15)

where ς

n

=

γ

2

+ ((2 · n + 1)ω

r

)

2

, and δ

n

= − tan

−1

(γ/

(2 · n + 1)ω

r

).

As ς

n

increases with the frequency, and assuming that, as

usual, higher harmonics have lower amplitudes than the ones

near the fundamental, the contribution of these harmonics to

the evolution of D

∗

(t) may be neglected in most cases.

As a conclusion, in the particular case of balanced loads,

D is identically zero due to the fact that load currents will

compensate among them. Otherwise, D

∗

presents an intrinsic

oscillatory behavior with a zero-mean value. If these intrinsic

oscillations are seen from the voltage point of view, then it can

also be seen that their amplitude is proportional to the capaci-

tance inverse; thus, increasing the capacitance will reduce their

amplitude.

The other important variable that should be analyzed is the

energy stored in the capacitors (E

c

); the evolution of this

variable is described in (6). This equation describes a stable

linear system with an exogenous input. This input is i

f,k

· α

k

,

where i

∗

f,k

is an odd-harmonic periodic signal, and it is easy

to prove that α

∗

k

is also an odd-harmonic periodic signal. Con-

sequently, i

∗

f,k

· α

∗

k

will be an even-harmonic periodic signal.

Hence, E

∗

c

will also be an even-harmonic periodic signal. These

oscillations are the same ones as that in i

∗

f,k

· α

∗

k

but are ﬁltered

by a ﬁrst-order ﬁlter 1/s + 2γ.

The voltage loop (Section III-B) will assure that the ﬁrst

harmonic of these intrinsic oscillations will be regulated to the

desired value (E

d

C

). As a conclusion, E

∗

C

presents an intrinsic

oscillatory behavior with a mean value that can be regulated by

the energy (voltage) loop. Its amplitude, from the voltage point

of view, is proportional to the inverse of the capacitance C;

hence, the amplitude of the voltage oscillations can be reduced

by increasing the capacitance.

IV. EXPERIMENTAL SETUP AND

IMPLEMENTATION ISSUES

A. Experimental Setup

The experimental setup used to test the designed controller

has the following parts:

1) Active ﬁlter: This is the full-bridge (three-legged) boost

converter with insulated gate bipolar transistor (IGBT)

switches (nominal current 100 A) and the following para-

meters: r = 0.034 Ω, L

1

= L

2

= L

3

= 1 mH, and C

1

=

C

2

= 6600 µF. The switching frequency of the converter

is 20 kHz and a synchronous (regularly) centered-pulse

single-update PWM strategy is used to map the con-

troller’s output to the IGBT gate signals.

Fig. 6. Three-phase nonlinear load: mains voltage (phase R) and current from

phase R (90 V/div and 12.5 A/div, respectively).

Fig. 7. Three-phase nonlinear load: mains voltage (phase R) and load current

from phase R (rms and THD).

2) Rectiﬁer (nonlinear load): This is the three-phase full-

wave diode rectiﬁer with C = 1500 µF. The active power

with nominal dc resistor is P = 5.6 kW, and its reactive

power is approximately zero. The rectiﬁer also includes

three series inductors (0.2 mH) in its ac side to limit the

derivative of its inputs currents. Fig. 6 shows the shape of

the ac mains voltage and current for phase R, and Fig. 7

shows the harmonic content of the phase R ac mains

line-to-neutral voltage and current for the rectiﬁer with

the nominal dc resistor. It is worth remarking that the

total harmonic distortion

7

(THD) of this current is about

110%, and its maximum derivative is about 70 kA/s.

3) Single-phase linear load: The resistive load of 1.9 kW

is connected between phase R and the neutral wires. It is

used experimentally to unbalance the load and to make up

a mixed load together with the three-phase nonlinear load.

4) Analog circuitry of feedback channels: The three ac

mains line-to-neutral voltages, the three ac mains cur-

rents, and the dc-bus voltage are sensed with voltage

transformers, Hall-effect sensors, and an isolation ampli-

ﬁer, respectively. All the signals from the sensors pass

through the corresponding gain conditioning stages to

7

In this paper, the THD ﬁgures and the harmonic content are always taken

with respect to the fundamental harmonic (50 Hz), and they have been obtained

using a Power Quality Analyzer Fluke 43 instrument.

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1500 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 3, JUNE 2007

adapt their values to an A/D converter input, taking

advantage of their full dynamic range. In addition, all

the feedback channels include a ﬁrst-order low-pass ﬁlter

with a unity dc gain and a 4.3-kHz cutoff frequency.

8

5) Control hardware and DSP implementation: The con-

trol board has been internally developed and is based

on an ADSP-21161 ﬂoating-point DSP processor with

an ADSP-21990 ﬁxed-point mixed-signal DSP processor

that acts as coprocessor, both from Analog Devices.

The DSP-21161 and the ADSP-21990 communicate with

each other using a high-speed synchronous serial channel

in the direct memory access mode. The ADSP-21990

deals with the three-phase PWM generation and the A/D

conversions with its integrated eight 14-bit high-speed

A/D channels.

6) Voltage and frequency: The nominal line-to-neutral volt-

age of the ac three-phase mains is V

s

= 220 Vrms, and

its nominal frequency is 50 Hz.

B. Implementation Issues

Some implementation issues that are worth remarking are

listed as follows.

1) The sampling rate of the A/D channels and the current

loop is F

s

= 20 kHz, which is the same as the switching

frequency of the active ﬁlter. Because the sampling rate

of the ac mains voltages and currents is the same as the

converter switching frequency, some aliasing problems

can arise. Particularly, the switching ripple appears as

a dc component on the discrete-time side (after A/D

conversion). This fact has proved especially critical in

ac mains line-to-neutral voltage sensing because these

signals are used as the carrier signals in the controller.

To solve this problem, the sampled ac voltages are passed

through parametric equalizer ﬁlters that include a zero in

z = 1 to reject, in steady state, the dc component of the

signals. In the ac mains currents, the problem is not very

important because the open-loop dc gain of the current

loops is low, and the current loops are hardly affected by

the ﬁctitious current dc component.

2) The controller and its related code (communications,

alarm supervision, data collection routines, etc.) are

coded in the C programming language without an under-

lying real-time operating system. Only a fewof the lowest

level procedures are coded in assembler for efﬁciency

reasons. The available computing power of the ﬂoating-

point DSP processor allows the controller operations to

be calculated in about two-thirds of the current loops’

sampling period. Thus, it is only necessary to force one

period of computing delay; in any case, this delay would

be necessary due to the hardware PWM unit peculiarities.

It is worth noting that the one-period computing delay

has been included in the plant model G

p

(z) to take it into

account in the current controller design process.

8

The oscilloscope screens in the ﬁgures cited in this section and the following

show the voltages and currents after the corresponding low-pass ﬁlters.

3) In this paper, the current loop plants G

p

(z) (one for each

phase) have no zeros, and the designed controllers G

c

(z)

are minimum-phase ﬁrst-order lag controllers, speciﬁ-

cally G

c

(z) = −[(0.0135z −0.01)/(z −0.905)]. Then,

the closed-loop functions G

o

(z) are minimum-phase

functions, and there is no problem choosing G

x

(z) =

k

r

G

o

(z)

−1

. The assigned value for k

r

is 0.2, and the

null-phase low-pass FIR ﬁlter selected is H(z) = 1/4z +

1/2 + 1/4z

−1

. It is worth stressing that the digital repeti-

tive current controller designed for one phase is repeated

for the other two.

4) The outer dc-bus voltage (energy) control loop needs to

feed back the dc-bus voltage sampled at 50 Hz. However,

direct sampling of this signal at 50 Hz sampling rate is

not a reliable option because of inherent noise and syn-

chronization issues when the dc-bus voltage oscillates.

Therefore, to alleviate this problem, the dc-bus voltage

is sampled at a sampling rate of 20 kHz, and after that,

it is passed through a comb ﬁlter tuned to the even-

harmonic values of the fundamental frequency (with the

exception of zero frequency). The output of the comb

ﬁlter is decimated to a 50-Hz sampling rate, and after a

low-order low-pass ﬁltering, it is compared to the desired

value to generate the error signal for the voltage (energy)

loop controller.

V. EXPERIMENTAL RESULTS

This section shows some of the experimental results obtained

for the active ﬁlter operation with the designed all-digital con-

troller. The results are presented by means of an oscilloscope

and power analyzer screen dumps of the ac mains electrical

variables and, when it is necessary, the active ﬁlter semibus

dc voltages.

Apart from the selected experiments collected in this section,

a lot of numerical simulations, including mainly capacitive or

inductive loads, have been carried out, showing the same good

performance as it will be shown later in this paper. Furthermore,

it is worth noting that several numerical simulations, including

loads that work as generators at some periods

9

(thus imposing

a negative active power ﬂow to the source), have been carried

out without problems. The voltage loop of the overall controller

assures the active power balance, and after a transient, in steady

state, the inputs to the AM modulators are negative, giving

current references shifted π rad from corresponding line-to-

neutral voltages that the current loops track without difﬁculty.

A. Active Filter Operation With No Load

This section presents some results of the no-load operation of

the active ﬁlter. Fig. 8 shows the line-to-neutral voltage and cur-

rent for phase R. The rms value of the current is about 1 A, and

its THDvalue is 6%. Then, the resulting active power consumed

by the ﬁlter to cover its losses without compensating any load

is about 720 W. It is worth noting that the fundamental com-

ponent of the current is in phase with the voltage (cos φ = 1;

9

This problem was established as a hard one by Depenbrock and Staudt [26].

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GRIÑÓ et al.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1501

Fig. 8. Active ﬁlter with no load: mains voltage (phase R) (90 V/div), current

from phase R (12.5 A/div) and semibus dc voltage (65 V/div), respectively.

Fig. 9. Active ﬁlter with no load: rms and THD values of the mains current

i

R

(t) and P, Q, cos φ, and PF for phase R.

see Fig. 9). Therefore, almost no reactive power is consumed

by the ﬁlter. The low ﬁgure of the power factor (PF = 0.71) is

owed to the high value of the switching ripple with respect to

the fundamental component of the current.

B. Active Filter Operation With the Three-Phase

Nonlinear Load

In this experiment, the three-phase diode rectiﬁer described

in Section IV-A is connected to the network. This nonlinear

load is balanced and has no reactive power at the fundamental

frequency; however, the active ﬁlter must work to compensate

all the generated higher order harmonics. Fig. 10 shows the

current for phase R, which appears with a good sinusoidal shape

and in phase with the grid voltage. This ﬁgure also shows the

values of each semibus of the active ﬁlter dc-bus. It is important

to remark that there are no oscillation, aside from the switching

ripple, in these variables because the load is a balanced one. As

shown in Fig. 11, the THD of the current is very low (0.9%),

and the power factor is very close to 1. Obviously, although

not shown, the results for the other two phases (S and T) are

quite similar, and the three currents form a balanced set in the

grid side, thus giving a neutral current with only high-frequency

components and very low rms values.

Fig. 10. Active ﬁlter with the three-phase nonlinear load: mains voltage

(phase R) (90 V/div), current from phase R (12.5 A/div), and semibus dc

voltages (65 V/div), respectively.

Fig. 11. Active ﬁlter with the three-phase nonlinear load: rms and THD

values of the mains current i

R

(t) and P, Q, cos φ, and PF for phase R.

Fig. 12. Active ﬁlter with the three-phase nonlinear load plus a single-

phase (R) resistive load: (left) i

R,load

(t), i

S,load

(t), i

T,load

(t) and (right)

i

R,source

(t), i

S,source

(t), i

T,source

(t) (12.5 A/div).

C. Active Filter Operation With the Three-Phase Nonlinear

Load Plus a Single-Phase Resistive Load

In this case, the single-phase resistive load described in

Section IV-A is connected between phase R and neutral wires

to create and unbalanced mixed (linear and nonlinear) load.

Fig. 12 (left) shows the three load currents that are clearly un-

balanced. The ﬁgure on the right shows the three grid currents

forming a sinusoidal balanced set.

Fig. 13 (left) details the phase R current, which is in phase

with the corresponding line-to-neutral voltage and shows the

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1502 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 3, JUNE 2007

Fig. 13. Active ﬁlter with the three-phase nonlinear load plus a single-phase

(R) resistive load: mains voltage (phase R) (90 V/div), current from phase R

(12.5 A/div), and semibus dc voltages (65 V/div), respectively, and rms and

THD values of the mains current i

R

(t).

semibus dc voltages. As theoretically predicted, these voltages

present an intrinsic oscillatory behavior because of the unbal-

anced characteristic of the load to compensate. In the power

analyzer screen dump of this ﬁgure, it can be observed that the

phase R current THD is 0.5%, which is a very low value, thus

conﬁrming the sinusoidal shape of the current. The THD for the

current has a lower value than that in Section V-B case due to

the fact that its rms value is higher; hence, the current switching

ripple is comparatively lower.

VI. CONCLUSION

This paper has shown the design and implementation of an

all-digital linear controller for a three-phase four-wire current

active ﬁlter. The controller consists of three inner current con-

trol loops and an outer dc-bus voltage control loop. The current

references for the inner control loops are created, passing the

output of the voltage controller through AM modulators that

use as a carrier a ﬁltered version of the corresponding line-

to-neutral voltage. The inner current control loops that, as the

experimental results show, perfectly shape the grid currents

are designed using a digital repetitive control approach. The

high loop gain injected by the repetitive controllers at the fun-

damental and harmonic frequencies of the network frequency

guarantees good tracking of the reference current and rejection

of the high-order harmonics of the load current. It is important

to remark that, because the current sensors have been placed

on the network side, the control problem for the current loops

can be discussed from a disturbance rejection point of view.

This approach allows for obtaining a controller with half the

usual current sensors, thus reducing the hardware cost, and

a lower computational cost due to the load current analysis

module is unnecessary. In addition, the external slow dynamics

voltage loop ensures the active power balance of the whole

system, adequately rejecting the load variations and providing

the inner current control loops with the correct current rms

references.

The paper also discussed the steady-state behavior of the

active ﬁlter in order to characterize the dc-bus voltage os-

cillations that appear during the controlled-system operation,

especially under the unbalanced load condition. Additionally,

some relevant practical implementation issues were commented

upon, and a selection of the obtained experimental results was

included, which shows that the closed-loop performance of the

designed system is good, with low THD values for the network

currents and a near-unity power factor at network terminals in

front of linear and nonlinear, balanced or unbalanced, loads.

REFERENCES

[1] H. Akagi, “New trends in active ﬁlters for power conditioning,” IEEE

Trans. Ind. Appl., vol. 32, no. 6, pp. 1312–1322, Nov./Dec. 1996.

[2] S. Buso, L. Malesani, and P. Mattavelli, “Comparison of current control

techniques for active ﬁlters applications,” IEEE Trans. Ind. Electron.,

vol. 45, no. 5, pp. 722–729, Oct. 1998.

[3] P. Mattavelli, “A closed-loop selective harmonic compensation for active

ﬁlters,” IEEE Trans. Ind. Appl., vol. 37, no. 1, pp. 81–89, Jan./Feb. 2001.

[4] P. Jintakosonwit, H. Fujita, and H. Akagi, “Control and performance

of a fully-digital-controlled shunt active ﬁlter for installation on a

power distribution system,” IEEE Trans. Power Electron., vol. 17, no. 1,

pp. 132–140, Jan. 2002.

[5] S. Fukuda and R. Imamura, “Application of a sinusoidal internal model to

current control of three-phase utility-interface converters,” IEEE Trans.

Ind. Electron., vol. 52, no. 2, pp. 420–426, Apr. 2005.

[6] H. Komurcugil and O. Kukrer, “A new control strategy for single-phase

shunt active power ﬁlters using a Lyapunov function,” IEEE Trans. Ind.

Electron., vol. 53, no. 1, pp. 305–312, Feb. 2006.

[7] I. Etxeberria-Otadui, A. L. D. Heredia, H. Gaztanaga, S. Bacha, and

M. Reyero, “A single synchronous frame hybrid (ssfh) multifrequency

controller for power active ﬁlters,” IEEE Trans. Ind. Electron., vol. 53,

no. 5, pp. 1640–1648, Oct. 2006.

[8] B. Singh, K. Al-Haddad, and A. Chandra, “A new control approach to

three-phase active ﬁlter for harmonics and reactive power compensation,”

IEEE Trans. Power Syst., vol. 13, no. 1, pp. 133–137, Feb. 1998.

[9] B. Francis and W. Wonham, “Internal model principle in control theory,”

Automatica, vol. 12, no. 5, pp. 457–465, 1976.

[10] K.-K. Chew and M. Tomizuka, “Digital control of repetitive errors in

disk drive systems,” IEEE Control Syst. Mag., vol. 10, no. 1, pp. 16–19,

Jan. 1990.

[11] Y. Onuki and H. Ishioka, “Compensation for repeatable tracking errors in

hard drives using discrete-time repetitive controllers,” IEEE/ASME Trans.

Mechatronics, vol. 6, no. 2, pp. 132–136, Jun. 2001.

[12] Y. Ye and D. Wang, “Learning more frequency components using p-type

ilc with negative learning gain,” IEEE Trans. Ind. Electron., vol. 53, no. 2,

pp. 712–716, Apr. 2006.

[13] D. H. Kim and T.-C. Tsao, “Robust performance control of electrohy-

draulic actuators for electronic cam motion generation,” IEEE Trans.

Control Syst. Technol., vol. 8, no. 2, pp. 220–227, Mar. 2000.

[14] S. Hattori, M. Ishida, and T. Hori, “Suppression control method for

torque vibration of brushless dc motor utilizing repetitive control with

Fourier transform,” in Proc. 6th Int. Workshop Adv. Motion Control, 2000,

pp. 427–432.

[15] K. Zhou, D. Wang, and G. Xu, “Repetitive controlled three-phase re-

versible PWM rectiﬁer,” in Proc. Amer. Control Conf., 2000, vol. 1,

pp. 125–129.

[16] Y. Tzou, S. Jung, and H. Yeh, “Adaptive repetitive control of PWM

inverters for very low THD ac-voltage regulation with unknown loads,”

IEEE Trans. Power Electron., vol. 14, no. 5, pp. 973–981, Sep. 1999.

[17] K. Zhou, D. Wang, and K. Low, “Periodic errors elimination in CVCF

PWM dc/ac converter systems: Repetitive control approach,” Proc. Inst.

Electr. Eng., vol. 147, no. 6, pp. 694–700, Nov. 2000.

[18] K. Zhou and D. Wang, “Digital repetitive learning controller for three-

phase CVCF PWM inverter,” IEEE Trans. Ind. Electron., vol. 48, no. 4,

pp. 820–830, Aug. 2001.

[19] C. Rech, H. Pinheiro, H. Grundling, H. Hey, and J. Pinheiro, “Analysis

and design of a repetitive predictive-PID controller for PWM inverters,”

in Proc. 32nd Annu. IEEE PESC, 2001, vol. 2, pp. 986–991.

[20] C. Rech, H. Grundling, and J. Pinheiro, “Comparison of discrete control

techniques for ups applications,” in Conf. Rec. IEEE IAS Annu. Meeting,

2000, vol. 4, pp. 2531–2537.

[21] R. Griñó, R. Costa-Castelló, and E. Fossas, “Digital control of a single-

phase shunt active ﬁlter,” in Proc. 34th IEEE Power Electron. Spec. Conf.,

Acapulco, Mexico, Jun. 15–19, 2003, pp. 1038–1042.

[22] R. Griñó and R. Costa-Castelló, “Digital repetitive plug-in controller for

odd-harmonic periodic references and disturbances,” Automatica, vol. 41,

no. 1, pp. 153–157, Jan. 2005.

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GRIÑÓ et al.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1503

[23] T. Inoue, M. Nakano, T. Kubo, S. Matsumoto, and H. Baba, “High accu-

racy control of a proton synchroton magnet power supply,” in Proc. 8th

IFAC World Congr., 1981, pp. 216–220.

[24] M. Tomizuka, T. Tsao, and K. Chew, “Analysis and synthesis of

discrete-time repetitive controllers,” Trans. ASME, J. Dyn. Syst., Meas.,

Control, vol. 111, no. 3, pp. 353–358, Sep. 1989.

[25] G. Hillerström and R. C. Lee, “Trade-offs in repetitive control,” Univ.

Cambridge, Cambridge, U.K., Tech. Rep. CUED/F-INFENG/TR 294,

Jun. 1997.

[26] M. Depenbrock and V. Staudt, “Stability problems if three-phase systems

with bidirectional energy ﬂow are compensated using the FBD-method,”

in Proc. 8th ICHQP, Oct. 14–16, 1998, pp. 325–330.

Robert Griñó (S’90–M’99) received the M.Sc. de-

gree in electrical engineering and the Ph.D. degree

in automatic control from the Universitat Politècnica

de Catalunya (UPC), Barcelona, Spain, in 1989 and

1997, respectively.

From 1990 and 1991, he was a Research Assistant

with the Instituto de Cibernética, UPC. From 1992

to 1998, he was an Assistant Professor with the

Department of Systems Engineering and Automatic

Control and the Institute of Industrial and Control

Engineering, UPC, where he has been an Associate

Professor since 1998. His research interests include digital control, nonlinear

control, and control of power electronic converters.

Dr. Griñó is an Afﬁliate Member of the International Federation of Auto-

matic Control (IFAC) and a member of the Comité Español de Automática

(CEA)-IFAC.

Rafel Cardoner was born in Barcelona, Spain, in

1960. He received the M.Sc. degree in technical

telecommunications engineering from the Universi-

tat Ramon Llul (La Salle), Barcelona.

He is currently a Development Engineer with the

Institut d’Organització i Control de Sistemes Indus-

trials (IOC), Escola Tècnica Superior d’Enginyeria

Industrial de Barcelona (ETSEIB), Universitat

Politècnica de Catalunya, Barcelona, Spain. His re-

search interests include digital control and power

electronics.

Ramon Costa-Castelló (S’95–A’03–M’04–SM’07)

was born in Lleida, Spain, in 1970. He received the

M.Sc. and Ph.D. degrees in computer science from

the Universitat Politècnica de Catalunya (UPC),

Barcelona, Spain, in 1993 and 2001, respectively.

Since July 1996, he has been teaching various

topics in digital control and real-time systems at

UPC. His research interests include digital control

and nonlinear control.

Dr. Costa-Castelló is a member of the Society for

Industrial and Applied Mathematics and an Afﬁliate

Member of the International Federation of Automatic Control.

Enric Fossas received the Graduate and Ph.D. de-

grees in mathematics from Barcelona University,

Barcelona, Spain, in 1981 and 1986, respectively.

Since 1981, he has been teaching mathematics

at the Universitat de Barcelona and mathematics

and automatic control at the Universitat Politècnica

de Catalunya, Barcelona, where he is currently an

Assistant Professor. His research interests include

the ﬁeld of system theory (VSS) and control from

a mathematical viewpoint.

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D.j ∀k = j. and rC.k = n an. represents the steady-state value of signal x(t). Finally. The averaged (at the switching frequency) model of the boost converter is given by Lk dif. VOL. C1 and C2 are the converter capacitors. Lk are the converter inductors. This paper is organized as follows.5 i. b.2 if..e. this approach matches a disturbance attenuation problem.k are the inductor√ currents. and it must take the adequate value to maintain the power balance of the whole system. II. k. is usually a periodic signal with only odd harmonics in its Fourier series expansion. This special form of the problem speciﬁcations implies the particular structure of the controller loops described in the next section.1496 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. 1. In addition.k = Vs 2 sin(ωr t + φk ) are the voltage sources that represent the three-phase ac-line source with φa = 0. JUNE 2007 only uses three sensors for source currents. x 0 means the dc value. 3 In 4 x∗ 5 (1) (2) C1 C2 if. A threephase mixed linear and nonlinear load is connected to the power source. P ROBLEM F ORMULATION A. and φc = −4π/3. in parallel. It would also be desirable that this voltage would be almost equally distributed among both capacitors (v1 ≈ v2 ). an. Section VI summarizes the results of this paper. Then. NO.k = −rL. 1 presents the complete system architecture. Section III shows the multiloop controller design with the underlying theoretical aspects and the steady-state analysis. vs. 1] and represent the averaged value of the pulsewidthmodulated control signal injected to the actual system. Section IV describes the experimental setup and gives some implementation issues. but the ﬁrst one is not a tracking speciﬁcation because ∗ only a shape and not a signal is deﬁned. Section V presents some selected experimental results that show the good behavior of the whole system. bn. Another collateral goal that is necessary for a correct operation of the converter is to assure a constant average value of the dcbus voltage. 3. and from this perspective. v1 and v2 are the dc capacitor voltages. The control variables dk take their values in the closed real interval [0. the control objectives. Authorized licensed use limited to: IEEE Xplore Customer. Section II introduces the problem.e. the computational cost of the overall controller is reduced in front of the usual six current sensors architecture because the proposed controller structure does not need a load current analysis module.k dt dv1 = −rC. Load Description The load current. c}. Rewriting the Equations It is a standard for this kind of systems to linearize the current dynamics by the state feedback αk = v1 dk + v2 (dk −1). to guarantee a unity power factor and a three-phase balanced current set in the network side. v1 + v2 ∗ = Vd .k if.2 are the parasitic resistances of the capacitors. that is. where Vd must fulﬁll the 0 boost condition. B. i. 2k ∈ {a. or mean value. . a balanced load. all the s. and the model of the system. 54. A three-leg boost converter with an ac neutral wire connected directly to the midpoint of the dc-bus is used as the active ﬁlter. c}. 2008 at 07:33 from IEEE Xplore. the current controllers are designed using the aforementioned linear control design technique. j ∈ {a.k − v1 dk − v2 (dk − 1) + vs.k dk k Fig.1 and rC..k cos (ωr (2 · n + 1)t + φk ) (4) where an.1 v1 + dt dv2 = −rC. i. φb = −2π/3. sensing the load currents and the active ﬁlter input currents.k sin (ωr (2 · n + 1)t + φk ) + bn. in steady state. Control Objectives The active ﬁlter goals are to assure that the load is seen as a resistive one and to balance the load current set. Downloaded on December 17. Id is not known a priori.2 v2 + dt if.k . Physical Model of the Boost Converter Fig. b. unlike the usual control schemes that double this number.k source currents have a sinusoidal shape in phase with the corresponding line-to-neutral voltage and the same amplitude.e. a three-phase four-wire active ﬁlter is applied in order to fulﬁll the desired behavior. the task of the current loops is to maintain sinusoidal-shape source currents in phase with the line-to-neutral voltages in spite of the corresponding load currents. so the current in each phase can be written as il.3 C.. These ∗ goals can be stated4 as i∗ = Id sin(ωr t + φk ). Three-phase four-wire parallel active ﬁlter connected to the networkload system. These two objectives deﬁne a nonstandard control problem: the second one is a regulation objective for the mean value of v1 + v2 . Restrictions apply.k are the inductor parasitic resistances. of signal x(t).k = an. rL. From a control theory point of view.k (dk − 1) k (3) where dk is the duty ratio of the k-phase.j and bn.k ∈ R are the real Fourier series coefﬁcients of the k-phase current.k = bn.

6 A similar reasoning can be done with the dc-bus capacitor voltages.k − αk dt dEc 2rC Ec 1 =− + if. It is important to emphasize that the FIR ﬁlter H(z) reduces the repetitive loop gain to ﬁnite values for all the frequencies. i. k It is important to note that the state feedback. .GRIÑÓ et al. and Ts is the sampling period. It can be proven that this internal model has poles at the fundamental frequency and at its odd-harmonic frequencies [22]. Current Loop The dynamics of (5) can also be described by Gp (s) = −1/r Yk (s) = L . 3). which is the charge unbalance between them. 1) The closed-loop system without the repetitive controller is stable. 2). Digital repetitive current control loop. results in a state and input diffeomorphism. Go (z) = Gc (z)Gp (z)/(1 + Gc (z)Gp (z)) is stable. 4). 2. This basic block is used as a basis to feed back a delay of N/2 ∈ N sampling periods. and D.k . which is designed to ensure closed-loop stability. III. Taking beneﬁt from the fact that current equations (5) are linear and decoupled. namely: EC . giving it a general low-pass shape. the system dynamics in the new variables results in Lk dif.. a null-phase ﬁnite-impulse response (FIR) low-pass ﬁlter H(z) is introduced into the basic block in order to reduce the gain at those frequencies where system behavior is not properly modeled (Fig. The corresponding zero dynamics is studied in Section III-C. Basic block diagram of the digital repetitive control loop. as it is implied by the change of the variables used. 3. where Gx is a design ﬁlter to be chosen. 4. Moreover. αk (s) rs+1 (8) This continuous-time transfer function is sampled with a zero-order hold at a sampling frequency equal to the switching frequency of the converter giving. which introduces an inﬁnite gain at a certain frequency and all its odd harmonics.2 ).k = if. Downloaded on December 17.k . which is the energy stored in the converter capacitors. Gp (z). i. 3) 1 − Go (z)Gx (z) ∞ < 1. Odd-harmonic repetitive control consists of placing a basic block (internal model) into the loop (Fig. as can be seen in Fig. and then this function is taken as a plant for the digital current controller design. Fig. under the fulﬁllment of current speciﬁcations. This scheme was ﬁrst introduced by Inoue et al. [23]. Tr is the period of the periodic signal to be tracked or rejected. (5) (6) (7) dD rC 1 = − D+ dt C C if. It is worth remarking that. The sine-wave amplitude is given by an outer digital control loop to fulﬁll the appropriate active power balance for the whole system. The closed-loop system of Fig.e. Assuming that the two dc-bus capacitors are equal (C = C1 = C2 . D = C1 v1 − C2 v2 yields two more meaningful variables. as a result..k if. Restrictions apply. 2) H(z) ∞ < 1. 4. 4 is stable if the following conditions are fulﬁlled [22]. An odd-harmonic digital repetitive controller [22] is designed for tracking and disturbance rejection purposes. The speciﬁc controller designs will be presented in Sections III-A and B. (7) is also linear. 3). The controller is composed of the internal model and a linear system Gx (z). This balance is achieved if the energy6 stored in the d active ﬁlter capacitors Ec is equal to its reference value Ec . provided that v1 + v2 = 0. the change of variables if. In addition. In practical implementations. (7) is decoupled as well.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1497 Fig. together with the change of variables. C ONTROL D ESIGN A. 2.e. where N = Tr /Ts .k = −rL. The full control scheme for one phase current is depicted in Fig. Controller scheme showing one of the current control loops (inner) and the voltage (or energy) control loop (outer). a linear controller is designed for each one to force a sinusoidal shape in the network current (see Fig. the repetitive compensator is used to augment an existing nominal controller Gc (z) (Fig. rC = rC. 2008 at 07:33 from IEEE Xplore.k αk dt C C k Fig.1 = rC. This nominal compensator is designed to stabilize the plant Gp (z) and provides disturbance attenuation across a broad frequency spectrum. Authorized licensed use limited to: IEEE Xplore Customer. EC = 2 2 1/2(C1 v1 + C2 v2 ).k + vs. Repetitive controllers are usually implemented in a “plug-in” fashion.

• Condition 2: There is no problem with the causality of H(z) because it is series connected with the delay z −N/2 and the repetitive loop will be executed as a whole in a controller real-time operation. 2008 at 07:33 from IEEE Xplore. 5.k a0. load currents. Thus. It is important to note that. Moreover. it is important to note that some energy is lost in the parasitic resistors of the inductors and the capacitors.e. JUNE 2007 These conditions are fulﬁlled by a proper design of Gc (z) and Gx (z). the system is stable. as said before.k = 0 The stored energy in the converter can be decomposed into the energy stored in the inductors (EL = k (1/2)Lk (if. the variation of energy in the inductors in one period is zero.k )2 ) and the energy stored in the capacitors (Ec ). From the power ﬂow point of view. C. from (12). i. As γ = (rC /C) > 0.. 5). Energy Shaping (Voltage Loop) Without taking into account the active ﬁlter losses. Restrictions apply. This equation is a linear differential equation with an unknown input k if.k ) . there is no problem with the no causality of Gx (z).k Id sin(ωr t + φk ).e. From the practical point of view. This structure can only be used if Go is a minimum-phase transfer function. The charge unbalance is described in (7). As argued in [25]. Presuming the currents’ steady state and discarding the parasitic resistance of the inductors and capacitors. Id (z) = kp + kI z+1 z−1 d ET (z) − ET (z) . If this assumption is used. 3. What can be achieved is an energy compensation within one period t t As the value of a0. all the power obtained from the net is due to load requirements. Otherwise. t t ˙ ET = t−Tr t−Tr ˙ Ec . the voltage loop design uses a steady-state condition in the current loop. Simpliﬁed 50-Hz model with a PI controller. Thus.k . (12) Using (6) and (12) results in t ˙ ET = ET (t) − ET (t − Tr ) = t−Tr k √ 2Vs π(Id − a0. NO.k is usually unknown but constant in steady state..k . kr must be designed while looking for a tradeoff between robustness and transient response. it is not possible to satisfy this requirement instantaneously. the control deﬁned for ET can be applied to Ec . (13) = = Pload . t−Tr (11) The losses in the inductor and capacitor parasitic resistances can be considered as an additive complex-dynamics disturbance in the voltage closed-loop system. (9) However. and under this ideal assumption. 54. Zero Dynamics In this section. i. Additionally. it is not worth taking these losses into account in the design of the voltage loop. it can be considered as a step disturbance in the closedloop system (see Fig. the converter redistributes the power ﬂow within one period in order to assure the stated power balance.e. • Condition 3: A trivial structure that is often used is [24] Gx (z) = kr Go (z)−1 . . as Id is designed locally constant in order to fulﬁll the harmonic requirements. it can be easily proven that independent of the value of Id and the Authorized licensed use limited to: IEEE Xplore Customer.k i k l..1498 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. a classical PI controller will regd ulate ET to the desired value ET without steady-state error. i. as the experimental results will show. this is of great relevance because Ec can be directly calculated by means of measuring the dc-bus voltage (v 1 + v 2 ). • Condition 1: It is advisable to design the controller Gc (z) with a high-enough robustness margin. the following constraint holds: Pnet = k This energy balance can be seen as a linear discrete-time system (with the sample time Tr ) with an input Id and a constant disturbance a0. the total energy stored in the converter (ET ) does not suffer variations within a period. t ˙ ET = 0. Hence. other techniques should be applied in order to avoid closed-RHS plane zero–pole cancellations [24].k . Fig. VOL. which is described as follows. Pnet = t−Tr t−Tr (14) Pload (10) that yields the Id ideal value. However. ω B. and if k if. the complete system zero dynamics is charac∗ terized while assuming that is. Downloaded on December 17. 1 ET (z) = z−1 √ 2Vs π ω 3Id(z) − k √ Id 2Vs sin2 (ωr t + φk ) vs.

Hall-effect sensors. 2) Rectiﬁer (nonlinear load): This is the three-phase fullwave diode rectiﬁer with C = 1500 µF. the output is also periodic. Three-phase nonlinear load: mains voltage (phase R) and current from phase R (90 V/div and 12. 7. 7 shows the harmonic content of the phase R ac mains line-to-neutral voltage and current for the rectiﬁer with the nominal dc resistor.k · αk . Its amplitude. EC presents an intrinsic oscillatory behavior with a mean value that can be regulated by the energy (voltage) loop.k π − cos ωr (2 · n + 1)t + φk + δn − ςn 2 where ςn = γ 2 + ((2 · n + 1)ωr )2 . if. The active power with nominal dc resistor is P = 5. as usual.k ∗ to prove that αk is also an odd-harmonic periodic signal. If these intrinsic oscillations are seen from the voltage point of view. The rectiﬁer also includes three series inductors (0. and δn = − tan−1 (γ/ (2 · n + 1)ωr ). the three ac mains currents. 6 shows the shape of the ac mains voltage and current for phase R. from the voltage point of view. 6. It is worth remarking that the total harmonic distortion7 (THD) of this current is about 110%. This equation describes a stable linear system with an exogenous input. Authorized licensed use limited to: IEEE Xplore Customer. . and C1 = C2 = 6600 µF. Fig. The voltage loop (Section III-B) will assure that the ﬁrst harmonic of these intrinsic oscillations will be regulated to the d ∗ desired value (EC ). 2008 at 07:33 from IEEE Xplore. 3) Single-phase linear load: The resistive load of 1. is proportional to the inverse of the capacitance C. and an isolation ampliﬁer. Restrictions apply. higher harmonics have lower amplitudes than the ones near the fundamental. Fig. These ∗ oscillations are the same ones as that in i∗ · αk but are ﬁltered f.2 mH) in its ac side to limit the derivative of its inputs currents. and assuming that.GRIÑÓ et al. D∗ presents an intrinsic oscillatory behavior with a zero-mean value. respectively. As a conclusion. Con∗ ∗ sequently. Then. Downloaded on December 17. and its maximum derivative is about 70 kA/s. and Fig.k · αk will be an even-harmonic periodic signal.k by a ﬁrst-order ﬁlter 1/s + 2γ. then it can also be seen that their amplitude is proportional to the capacitance inverse. D∗ (t) = 1 C − k n an. and the dc-bus voltage are sensed with voltage transformers. the evolution of this variable is described in (6). and its reactive power is approximately zero. Three-phase nonlinear load: mains voltage (phase R) and load current from phase R (rms and THD). E XPERIMENTAL S ETUP AND I MPLEMENTATION I SSUES A. IV.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1499 (balanced load). It is used experimentally to unbalance the load and to make up a mixed load together with the three-phase nonlinear load. respectively). the THD ﬁgures and the harmonic content are always taken with respect to the fundamental harmonic (50 Hz).9 kW is connected between phase R and the neutral wires. then it tends to zero in steady state. hence. The other important variable that should be analyzed is the energy stored in the capacitors (Ec ). Experimental Setup The experimental setup used to test the designed controller has the following parts: 1) Active ﬁlter: This is the full-bridge (three-legged) boost converter with insulated gate bipolar transistor (IGBT) switches (nominal current 100 A) and the following parameters: r = 0. in the particular case of balanced loads. 4) Analog circuitry of feedback channels: The three ac mains line-to-neutral voltages. as the input is a periodic signal. ∗ Hence. Ec will also be an even-harmonic periodic signal. Fig. increasing the capacitance will reduce their amplitude. and it is easy f. As ςn increases with the frequency. Otherwise. the contribution of these harmonics to the evolution of D∗ (t) may be neglected in most cases. This input is if. L1 = L2 = L3 = 1 mH.k sin (ωr (2 · n + 1)t + φk + δn ) ςn (15) bn.6 kW. thus. The switching frequency of the converter is 20 kHz and a synchronous (regularly) centered-pulse single-update PWM strategy is used to map the controller’s output to the IGBT gate signals.034 Ω. All the signals from the sensors pass through the corresponding gain conditioning stages to 7 In this paper.5 A/div. and they have been obtained using a Power Quality Analyzer Fluke 43 instrument. Otherwise. the amplitude of the voltage oscillations can be reduced by increasing the capacitance. D is identically zero due to the fact that load currents will compensate among them. As a conclusion. where i∗ is an odd-harmonic periodic signal.

6) Voltage and frequency: The nominal line-to-neutral voltage of the ac three-phase mains is Vs = 220 Vrms. which is the same as the switching frequency of the active ﬁlter.2. Therefore. Downloaded on December 17. However. all the feedback channels include a ﬁrst-order low-pass ﬁlter with a unity dc gain and a 4. Fig. B. speciﬁcally Gc (z) = −[(0. data collection routines. in any case. Thus. 3) In this paper. Implementation Issues Some implementation issues that are worth remarking are listed as follows. and the designed controllers Gc (z) are minimum-phase ﬁrst-order lag controllers. In addition.0135z − 0. this delay would be necessary due to the hardware PWM unit peculiarities. and the null-phase low-pass FIR ﬁlter selected is H(z) = 1/4z + 1/2 + 1/4z −1 . The output of the comb ﬁlter is decimated to a 50-Hz sampling rate. A. in steady state. the closed-loop functions Go (z) are minimum-phase functions. alarm supervision. taking advantage of their full dynamic range. Active Filter Operation With No Load This section presents some results of the no-load operation of the active ﬁlter. to alleviate this problem.905)]. the current loop plants Gp (z) (one for each phase) have no zeros. including loads that work as generators at some periods9 (thus imposing a negative active power ﬂow to the source). and its THD value is 6%. Particularly. Apart from the selected experiments collected in this section. when it is necessary. 4) The outer dc-bus voltage (energy) control loop needs to feed back the dc-bus voltage sampled at 50 Hz. The available computing power of the ﬂoatingpoint DSP processor allows the controller operations to be calculated in about two-thirds of the current loops’ sampling period. Then. the dc-bus voltage is sampled at a sampling rate of 20 kHz. 9 This problem was established as a hard one by Depenbrock and Staudt [26]. the dc component of the signals. The results are presented by means of an oscilloscope and power analyzer screen dumps of the ac mains electrical variables and. and there is no problem choosing Gx (z) = kr Go (z)−1 . 2) The controller and its related code (communications. The voltage loop of the overall controller assures the active power balance. the problem is not very important because the open-loop dc gain of the current loops is low. a lot of numerical simulations. and the current loops are hardly affected by the ﬁctitious current dc component. 2008 at 07:33 from IEEE Xplore. Then.8 5) Control hardware and DSP implementation: The control board has been internally developed and is based on an ADSP-21161 ﬂoating-point DSP processor with an ADSP-21990 ﬁxed-point mixed-signal DSP processor that acts as coprocessor. have been carried out without problems. showing the same good performance as it will be shown later in this paper. V. and its nominal frequency is 50 Hz. including mainly capacitive or inductive loads.) are coded in the C programming language without an underlying real-time operating system. direct sampling of this signal at 50 Hz sampling rate is not a reliable option because of inherent noise and synchronization issues when the dc-bus voltage oscillates. To solve this problem. It is worth noting that the fundamental component of the current is in phase with the voltage (cos φ = 1. E XPERIMENTAL R ESULTS This section shows some of the experimental results obtained for the active ﬁlter operation with the designed all-digital controller. The assigned value for kr is 0.3-kHz cutoff frequency. JUNE 2007 adapt their values to an A/D converter input. 8 shows the line-to-neutral voltage and current for phase R. have been carried out. 8 The oscilloscope screens in the ﬁgures cited in this section and the following show the voltages and currents after the corresponding low-pass ﬁlters. etc. Furthermore. 1) The sampling rate of the A/D channels and the current loop is Fs = 20 kHz. It is worth stressing that the digital repetitive current controller designed for one phase is repeated for the other two. Because the sampling rate of the ac mains voltages and currents is the same as the converter switching frequency. the sampled ac voltages are passed through parametric equalizer ﬁlters that include a zero in z = 1 to reject. and after a transient. . the switching ripple appears as a dc component on the discrete-time side (after A/D conversion). Only a few of the lowest level procedures are coded in assembler for efﬁciency reasons. the active ﬁlter semibus dc voltages. it is only necessary to force one period of computing delay. NO. 54. in steady state. the resulting active power consumed by the ﬁlter to cover its losses without compensating any load is about 720 W. 3. it is compared to the desired value to generate the error signal for the voltage (energy) loop controller. This fact has proved especially critical in ac mains line-to-neutral voltage sensing because these signals are used as the carrier signals in the controller. Authorized licensed use limited to: IEEE Xplore Customer. The ADSP-21990 deals with the three-phase PWM generation and the A/D conversions with its integrated eight 14-bit high-speed A/D channels. it is passed through a comb ﬁlter tuned to the evenharmonic values of the fundamental frequency (with the exception of zero frequency).1500 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. some aliasing problems can arise. both from Analog Devices. VOL. The rms value of the current is about 1 A. and after a low-order low-pass ﬁltering. Restrictions apply. It is worth noting that the one-period computing delay has been included in the plant model Gp (z) to take it into account in the current controller design process. and after that. The DSP-21161 and the ADSP-21990 communicate with each other using a high-speed synchronous serial channel in the direct memory access mode.01)/(z − 0. it is worth noting that several numerical simulations. In the ac mains currents. the inputs to the AM modulators are negative. giving current references shifted π rad from corresponding line-toneutral voltages that the current loops track without difﬁculty.

Downloaded on December 17. however. 8. and PF for phase R.source (t). cos φ. 2008 at 07:33 from IEEE Xplore. Fig. C. 9. Active Filter Operation With the Three-Phase Nonlinear Load In this experiment. and PF for phase R.load (t) and (right) iR. thus giving a neutral current with only high-frequency components and very low rms values. the THD of the current is very low (0. respectively. although not shown. 9).5 A/div). cos φ. It is important to remark that there are no oscillation.9%). 11. almost no reactive power is consumed by the ﬁlter. iS. Active ﬁlter with no load: mains voltage (phase R) (90 V/div). Therefore. 10 shows the current for phase R. which is in phase with the corresponding line-to-neutral voltage and shows the Authorized licensed use limited to: IEEE Xplore Customer. 13 (left) details the phase R current. the three-phase diode rectiﬁer described in Section IV-A is connected to the network. iT. which appears with a good sinusoidal shape and in phase with the grid voltage. 12.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1501 Fig.GRIÑÓ et al. Fig. current from phase R (12. 11. Active ﬁlter with the three-phase nonlinear load plus a singlephase (R) resistive load: (left) iR. Fig. As shown in Fig. the single-phase resistive load described in Section IV-A is connected between phase R and neutral wires to create and unbalanced mixed (linear and nonlinear) load.source (t) (12. Obviously. respectively. the results for the other two phases (S and T) are quite similar.load (t). Active ﬁlter with the three-phase nonlinear load: mains voltage (phase R) (90 V/div). and the power factor is very close to 1. and semibus dc voltages (65 V/div).5 A/div) and semibus dc voltage (65 V/div). This nonlinear load is balanced and has no reactive power at the fundamental frequency. Active Filter Operation With the Three-Phase Nonlinear Load Plus a Single-Phase Resistive Load In this case.5 A/div). This ﬁgure also shows the values of each semibus of the active ﬁlter dc-bus. Fig. see Fig. Fig. 12 (left) shows the three load currents that are clearly unbalanced. B. in these variables because the load is a balanced one.load (t). the active ﬁlter must work to compensate all the generated higher order harmonics. current from phase R (12. The low ﬁgure of the power factor (PF = 0. The ﬁgure on the right shows the three grid currents forming a sinusoidal balanced set. and the three currents form a balanced set in the grid side. Active ﬁlter with the three-phase nonlinear load: rms and THD values of the mains current iR (t) and P . Active ﬁlter with no load: rms and THD values of the mains current iR (t) and P . iS. Q. aside from the switching ripple. . Q. iT. Fig.71) is owed to the high value of the switching ripple with respect to the fundamental component of the current. Fig.source (t). 10. Restrictions apply.

Buso.” IEEE Trans. Tzou. K.-C. Jun. Power Electron. no. Komurcugil and O.. no. Jun. these voltages present an intrinsic oscillatory behavior because of the unbalanced characteristic of the load to compensate. “Digital repetitive plug-in controller for odd-harmonic periodic references and disturbances. “Repetitive controlled three-phase reversible PWM rectiﬁer. IEEE IAS Annu. some relevant practical implementation issues were commented Authorized licensed use limited to: IEEE Xplore Customer. Ishida. Ind. Ind. Ind. 1.” IEEE Trans. vol. S.” in Proc. and H. no. L.” IEEE Trans. H. and G. “Robust performance control of electrohydraulic actuators for electronic cam motion generation. 1996. no. no. thus reducing the hardware cost. 420–426. 5. 2. pp. Low. vol. Tsao. 1.” in Proc. 53. 2003. 14. Zhou and D. Downloaded on December 17. and rms and THD values of the mains current iR (t). “Application of a sinusoidal internal model to current control of three-phase utility-interface converters. JUNE 2007 upon. H. vol. which is a very low value. 1. and M. 2006. “Digital control of repetitive errors in disk drive systems. Rech. with low THD values for the network currents and a near-unity power factor at network terminals in front of linear and nonlinear. 457–465. pp. 2000. 712–716.. no. 820–830. 125–129. 1976. “A single synchronous frame hybrid (ssfh) multifrequency controller for power active ﬁlters. Eng. 2008 at 07:33 from IEEE Xplore. pp. vol. D. Wang. Electron. Wonham. [21] R. [20] C. 2000.” IEEE Control Syst. [22] R. . 4. [8] B. pp. Active ﬁlter with the three-phase nonlinear load plus a single-phase (R) resistive load: mains voltage (phase R) (90 V/div). “Comparison of discrete control techniques for ups applications. Heredia. and T. vol.. 81–89. Mexico. no. Yeh. Oct./Feb. Griñó and R... Rec. and a selection of the obtained experimental results was included. 4..” IEEE Trans. 2000. 53. Acapulco. Control Conf. “A new control strategy for single-phase shunt active power ﬁlters using a Lyapunov function. Meeting. Ind. This approach allows for obtaining a controller with half the usual current sensors. Ind. 2001. Workshop Adv. Zhou. pp.” IEEE Trans. 6. pp. Wang. pp. “Learning more frequency components using p-type ilc with negative learning gain. 6th Int. 52. 153–157. 132–140. “Internal model principle in control theory. “A closed-loop selective harmonic compensation for active ﬁlters. L. H. 694–700..” IEEE Trans. The controller consists of three inner current control loops and an outer dc-bus voltage control loop.” IEEE Trans. which shows that the closed-loop performance of the designed system is good. H. 54. Ishioka. no. Appl. Tomizuka. 305–312. hence. “A new control approach to three-phase active ﬁlter for harmonics and reactive power compensation. H. vol. 1. Motion Control. S. adequately rejecting the load variations and providing the inner current control loops with the correct current rms references. pp. The THD for the current has a lower value than that in Section V-B case due to the fact that its rms value is higher. 6. Malesani. Jan. “New trends in active ﬁlters for power conditioning. Power Electron. Technol. [4] P. Akagi. Electron. and P. Jan. Spec. Aug. The paper also discussed the steady-state behavior of the active ﬁlter in order to characterize the dc-bus voltage oscillations that appear during the controlled-system operation. Gaztanaga. Power Syst.” in Proc. 2006. 32nd Annu.” IEEE Trans. “Digital control of a singlephase shunt active ﬁlter. “Control and performance of a fully-digital-controlled shunt active ﬁlter for installation on a power distribution system. Jintakosonwit. no. [10] K. [2] S. Electr. 2. vol. and K. 1. 1312–1322. Chew and M. Grundling. Costa-Castelló.” Proc. Ye and D. vol. Fossas. as the experimental results show. [15] K. The high loop gain injected by the repetitive controllers at the fundamental and harmonic frequencies of the network frequency guarantees good tracking of the reference current and rejection of the high-order harmonics of the load current. Jung. “Periodic errors elimination in CVCF PWM dc/ac converter systems: Repetitive control approach. 10. In the power analyzer screen dump of this ﬁgure. “Adaptive repetitive control of PWM inverters for very low THD ac-voltage regulation with unknown loads. IEEE PESC. vol. 2005. [19] C. 34th IEEE Power Electron. Feb. Xu. Bacha. no. 1640–1648. 5. “Comparison of current control techniques for active ﬁlters applications. pp. Appl. [7] I.. pp. [11] Y. vol. Kim and T. Jan. and J. 2. 1038–1042. Hori... no. Singh.” in Conf. 2002. 5. 13.. the external slow dynamics voltage loop ensures the active power balance of the whole system. M. perfectly shape the grid currents are designed using a digital repetitive control approach. 1998. VI. no. 8. [3] P. [16] Y. no. respectively. Hattori. Electron. semibus dc voltages. [5] S. 1. 2001. pp. 6. Kukrer. vol. [9] B. loads.” IEEE Trans.” Automatica. and a lower computational cost due to the load current analysis module is unnecessary.. Etxeberria-Otadui. and semibus dc voltages (65 V/div). it can be observed that the phase R current THD is 0. pp. Hey. NO. balanced or unbalanced. Pinheiro. Apr. Chandra. 53. Griñó. Feb. the control problem for the current loops can be discussed from a disturbance rejection point of view. pp. “Suppression control method for torque vibration of brushless dc motor utilizing repetitive control with Fourier transform. 147. 1999. 37. Oct. no. VOL. H. Zhou. pp. Restrictions apply. Fig. 2001. Apr. and A. no. H. and H. 2000. thus conﬁrming the sinusoidal shape of the current.” IEEE Trans. “Compensation for repeatable tracking errors in hard drives using discrete-time repetitive controllers. 973–981. Fukuda and R. “Analysis and design of a repetitive predictive-PID controller for PWM inverters. 2. 220–227. Inst. [13] D. 2531–2537. current from phase R (12. the current switching ripple is comparatively lower. Nov. 3. Grundling. vol. [18] K. Mattavelli. Ind. Imamura.. Amer. 48. 13. Conf. R EFERENCES [1] H. D. [12] Y. Onuki and H. because the current sensors have been placed on the network side. vol. Akagi. Electron. 986–991. and E. Mattavelli. pp. pp. vol. [17] K. 132–136. 2005.” Automatica. 427–432. In addition. 1990. 12. 45. Costa-Castelló.” IEEE Trans. vol. 41. no.5%. Wang. R. Jan. pp. no. Sep. 2001. 16–19. Al-Haddad. Ind.. “Digital repetitive learning controller for threephase CVCF PWM inverter.” IEEE Trans. Mag. The current references for the inner control loops are created. pp. vol.. pp. Francis and W. vol. vol. Control Syst.1502 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. A. Wang. Reyero.. C ONCLUSION This paper has shown the design and implementation of an all-digital linear controller for a three-phase four-wire current active ﬁlter. pp. Pinheiro. pp. As theoretically predicted. Nov. 133–137. Ind. Pinheiro. Rech. 722–729. Additionally. D. 2000. vol. 5. Mar. 17. 2006. vol. 1998.” in Proc. 15–19.5 A/div).-K. Electron. [6] H. Electron. and J. Fujita. pp. It is important to remark that. especially under the unbalanced load condition. Mechatronics. 32. passing the output of the voltage controller through AM modulators that use as a carrier a ﬁltered version of the corresponding lineto-neutral voltage.” IEEE/ASME Trans. [14] S./Dec. 2. The inner current control loops that. 1.

degree in automatic control from the Universitat Politècnica de Catalunya (UPC). Downloaded on December 17. U. vol. UPC.Sc. “Trade-offs in repetitive control. degree in technical telecommunications engineering from the Universitat Ramon Llul (La Salle). UPC. in 1960.Sc. he has been teaching various topics in digital control and real-time systems at UPC.Sc. Universitat Politècnica de Catalunya.: DIGITAL REPETITIVE CONTROL OF A THREE-PHASE FOUR-WIRE SHUNT ACTIVE FILTER 1503 [23] T. Rep.GRIÑÓ et al. Dr. Meas. Barcelona. From 1990 and 1991. degree in electrical engineering and the Ph. Staudt. Spain.” in Proc. J. “Analysis and synthesis of discrete-time repetitive controllers. 2008 at 07:33 from IEEE Xplore.D. respectively. degrees in mathematics from Barcelona University. Depenbrock and V. Hillerström and R. C. 1989. “High accuracy control of a proton synchroton magnet power supply. Baba. His research interests include digital control and nonlinear control. and H. no. [24] M. Cambridge. 3. and K. T. 8th ICHQP. From 1992 to 1998. Inoue.D. Enric Fossas received the Graduate and Ph.” Univ. Barcelona. Escola Tècnica Superior d’Enginyeria Industrial de Barcelona (ETSEIB).” Trans.. 353–358. 1997. Tech.K. 1998. Oct. degrees in computer science from the Universitat Politècnica de Catalunya (UPC). Tomizuka. 1981. 111. Syst. Barcelona.D. [25] G. Tsao. he was an Assistant Professor with the Department of Systems Engineering and Automatic Control and the Institute of Industrial and Control Engineering. He received the M. Restrictions apply. Since 1981. Matsumoto. respectively.” in Proc.. Cambridge. CUED/F-INFENG/TR 294. Spain. Rafel Cardoner was born in Barcelona. Spain. where he is currently an Assistant Professor. Nakano. and control of power electronic converters. 14–16. Griñó is an Afﬁliate Member of the International Federation of Automatic Control (IFAC) and a member of the Comité Español de Automática (CEA)-IFAC. Control.. nonlinear control. in 1993 and 2001. Robert Griñó (S’90–M’99) received the M. Barcelona. [26] M. respectively. and Ph. His research interests include digital control. His research interests include digital control and power electronics. 216–220. Dyn. S. pp. Spain. in 1981 and 1986. Sep. . Spain. 8th IFAC World Congr. “Stability problems if three-phase systems with bidirectional energy ﬂow are compensated using the FBD-method. Barcelona. pp. Costa-Castelló is a member of the Society for Industrial and Applied Mathematics and an Afﬁliate Member of the International Federation of Automatic Control. Ramon Costa-Castelló (S’95–A’03–M’04–SM’07) was born in Lleida. M. Jun. Barcelona. he has been teaching mathematics at the Universitat de Barcelona and mathematics and automatic control at the Universitat Politècnica de Catalunya. Since July 1996. His research interests include the ﬁeld of system theory (VSS) and control from a mathematical viewpoint. in 1989 and 1997. pp. Dr. Authorized licensed use limited to: IEEE Xplore Customer. ASME. Lee. Spain. 325–330.. he was a Research Assistant with the Instituto de Cibernética. He is currently a Development Engineer with the Institut d’Organització i Control de Sistemes Industrials (IOC). T. Kubo. Chew. where he has been an Associate Professor since 1998. in 1970. He received the M.

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