MICRO CONTROLLER DAS | Microcontroller | Analog To Digital Converter






_______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 1


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We take immense pleasure in thanking the management of NFC for having permitted me to carry out this project work. We wish to express our deep sense of gratitude to our Project Guide, Shri V.NAGA BHASKAR, Manager, IMS-F, NFC. His guidance and motivation has helped us in carrying out the project work efficiently and effectively. Mr.RAMA KRISHNA , Scientific Officer-C, IMS, who had constantly monitored our work and inspired us to develop a scientific thinking. It wouldn’t have been possible to complete the project without his able guidance. We would express our heartfelt thanks to the Supervisor and Operating Staff in the CFFP and------ for their great cooperation and support. Their experience has taught us many things apart from the project. It was a great experience to work in NFC, and we are looking forward to work here again, if given an opportunity.


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6 Power Supply 4.5 Multiplexer CD4051B 4.0 Data Acquistion system 2.0 Principle of operation 3.8 MAX 232 Serial Level Converter 4.7 Differential Bus Transreceiver SN75176 4.Table of contents I Introduction 1.1 Micro controller 4.9 Modbus Protocol 5.0 Schematic Diagram 7.0 Functional description 4.0 Conclusions and Recommendations _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 4 .4 Precision Centigrade Temperature Sensors LM35 4.0 Block Diagram 4.0 Software 6.2 Analog to Digital converter TC7109A 4.3 LCD 4.

The task of performing such transformations falls on devices called sensors. which convert conditioned sensor signals to digital values. fluid flow. Signal conditioning circuitry to convert sensor signals into a form that can be converted to digital values. we seek for better methods to operate our plants and thus improve upon our processes. light intensity. and force. Analog-to-digital converters. Regardless of the type of physical property to be measured. • Source: Data acquisition begins with the physical phenomenon or physical property to be measured. Consider the following five components when building a data acquisition system. DAQ systems also employ various signal conditioning techniques to adequately modify various different electrical signals into voltage that can then be digitized using an Analog-to-digital converter (ADC).0 References CHAPTER 1 INTRODUCTION As technology advancements take place. Examples of this include temperature. the physical state that is to be measured must first be transformed into a unified form that can be sampled by a data acquisition system. gas pressure.The components of data acquisition systems include: • • • Sensors that convert physical parameters to electrical signals. Data acquisition is the process of sampling signals that measure real world physical conditions and converting the resulting samples into digital numeric values that can be manipulated by a computer. The data acquisition systems thus become essential part of any automated system. • Signals: _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 5 .8.

Driver software is the layer of software for easily communicating with the hardware. A crystal oscillator circuit is used to synchronize all the frequencies. DAC. This +5V is given to the micro controller _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 6 . Software transforms the pc and the data acquisition hardware into complete data acquisition. switch multiplexer. The 89C51 core microcontroller will be used to run and control these activities. yet cheaper than a CPU so that it is alright to block it with simple polling loops. let DAC proceed with voltage ramp. The frequency of crystal oscillator used is 11.0592MHZ. As the micro controller needs +5V dc. ADC. TTL-IO. waiting for the ADC to finish. serial. starting the ADC. • DAQ Hardware: DAQ hardware is what usually interfaces between the signal and a PC.) or cards connected to slots in the mother board. etc. this supply is obtained from the power supply circuit consists of a step down transformer and two diodes which acts as rectifiers and a regulator to get an output voltage of +5V. looking up the time. get TTL input. move value to RAM.presentation tool. In order to initialize all the internal register and operations a reset circuit is used. Many times reconfigurable logic is used to achieve high speed for specific tasks and Digital signal processors are used after the data has been acquired to obtain some results. These are accessible via a bus by a microcontroller. RAM).. These digitized analog samples processed and transmitted through RS485 serial bus using MODBUS protocol. USB. For example: Waiting for a trigger. high speed timers.analysis. DAQ cards often contain multiple components (multiplexer.0 Principle of operation: The proposed DAS project digitizes eight analog inputs by using multiplexer and A/D converter. It prevents a programmer from having to do register level programming or complicated commands to access the hardware functions. 2. The fixed connection with the PC allows for comfortable compilation and debugging • DAQ software: It is needed in order for the DAQ hardware to work with a PC.the observations will be displayed on LCD or PC using MODSCAN software. which can run small programs.Signals may be digital (also called logic signals sometimes) or analog depending on the transducer used. This reset circuit is done in the programming. A controller is more flexible than a hard wired logic. It could be in the form of modules that can be connected to the computer's ports (parallel.

0 Functional Description 3. and registers.1. counters and a clock circuit. Many instructions are _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 7 . serial I/O. Micro controllers: Figure shows the block diagram of a typical micro controller. SP. PC. ROM. The three basic elements-the CPU. Like the microprocessor. which is a true computer on a chip. the memory devices fall into generalpurpose category and the I/O devices may be grouped somewhere in-between. parallel I/O. While the CPU has been the proprietary item. It also has added the other features needed to make a complete computer. RAM. I/O devices and memory-have developed in distinct directions. one would first come across the development of microprocessor that is the processing element. The micro controller design uses a much more limited set of single and double byte instructions. The prime use of a micro controller is to control the operation of a machine using a fixed program that is stored in ROM and that does not change over the lifetime of the system. the micro controller is a general –purpose device that is meant to read data. which are used to move code and data from internal memory to the ALU. program limited calculations.1 Introduction Looking back into the history of microcomputers.. The design incorporates all of the features in a microprocessor CPU ALU. 3.1 8 Bit Micro controller (89C51): 3. and later on the peripheral devices.

InApplication Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 8 . The P89C51RD2 has the following on-chip facilities: • • 64KB ISP/IAP Flash program memory.This device is a Single-Chip 8-Bit Microcontroller manufactured in advanced CMOS process and is a derivative of the 80C51 microcontroller family. 8 bit program counter (PC). Features: The P89C51RD2 device contains a non-volatile 64kB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. The device also has four 8-bit I/O ports. program status word (PSW) and stack pointer (SP). Internal RAM of 1KB bytes. • • • Internal ROM or EPROM of 0 to 64K. The added features of the P89C51RD2 makes it a powerful microcontroller for applications that require pulse width modulation.This device executes one machine cycle in 6 clock cycles. an enhanced UART and on-chip oscillator and timing circuits. Four register banks each containing 8 registers. three 16-bit timer/event counters. the pins are” programmable” that is. data pointer (DPTR). In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. The instruction set is 100% compatible with the 80C51 instruction set. The micro controller is concerned with getting data from and to its own pins. fourpriority-level. nested interrupt structure. the architecture and instructions set are optimized to handle data in bit and byte size.coupled with pins on the integrated circuit package. A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. a multi-source. hence providing twice the speed of a conventional 80C51. An OTP configuration bit lets the user select conventional 12 clock timing if desired. high-speed I/O and up/down counting capabilities such as motor control. For InApplication Programming. capable of having several different functions depending on the wishes of the programmer.

Three 16-bit timer/counters. A full duplex enhanced UART -Framing error detection -Automatic Address recognition Control registers: TCON. SCON. 32 input-output port lines. PCON. IP and IE. 7 interrupt sources and 4 level priority interrupt • • • • • • _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 9 . which may be addressed at bit level. TMOD. On-chip clock oscillator and power on reset circuitry.• • 16 bytes .

1.2 Internal Block diagram P89C51 internal block diagram _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 10 .3.

00H – 1FFH/2FFH) are indirectly accessed by move external instruction. (addresses 80H to FFH) are directly addressable only. available abundantly. The crystal used for generation of CPU clock has therefore to be chosen carefully. Table 4. The 256/768-bytes expanded RAM (ERAM. For this its external access (EA) pin has to be grounded. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. The list of special function registers along with their hex addresses is given . The data memory is external only and a separate RD* signal is available for reading its contents. SFRs. MOVX. 3. The P89C51RB2/RC2/RD2 has internal data memory that is mapped into four separate segments: 1. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 4. The UART utilizes one of the internal timers for generation of baud rate. The program store enable (PSEN) signal acts as read pulse for program memory.The 89C51 can be configured to bypass. can provide a baud rate of 9600. 2. which makes it equivalent to 8031. and with the EXTRAM bit cleared. the internal 64kB ROM and run solely with external program memory.3 P89C51 Address register Address 80 81 82 83 88 89 8A 8B 8C 8D 90 98 99 A0 A8 Port/Register P0 (Port 0) SP (stack pointer) DPH (data pointer High) DPL (data pointer Low) TCON (timer control) TMOD (timer mode) TLO (timer 0 low byte) TL1 (timer 1 low byte) TH0 (timer 0 high byte) TH1 (timer 1 high byte) P1 (port 1) SCON (serial control) SBUF (serial buffer) P2 (port 2) Interrupt enable (IE) _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 11 .0592 MHz crystals. The 11. The Special Function Registers.

7RD External memory read pulse Table 4.The VPP supply should be adequately decoupled and VPP not allowed to exceed datasheet limits. and VPP . RxD. It is also adaptable to a wide range of oscillator frequencies. VCC. Only a small connector needs to be available to interface your application to an external circuit in order to use this feature .5T1 External timer 1 input P3.3INT1 External interrupt 1 P3.2INTO External interrupt 0 P3. independent of the oscillator frequency.ITXD Serial data output P3.B0 B8 D0 E0 F0 P3 (port 3) Interrupt priority (IP) Processor status word (PSW) Accumulator (ACC) B register Table 4.4TO External timer 0 input P3. An internal resistor to VSS permits a power-on reset using only an external capacitor to VCC. This firmware is provided by Philips and embedded within each P89C51RB2/RC2/RD2 device. The ISP feature allows for a wide range of baud rates to be used in your application. SFR SBUF SBUF TCON-1 TCON. The In-System Programming (ISP) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89C51RB2/RC2/RD2 through the serial port.2 TMOD TMOD ------------ 3.3.ORXD Serial data input P3. resets the device.4. VSS.1.6WR External memory write pulse P3. This is _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 12 .4 In-System Programming (ISP): The In-System Programming (ISP) is performed without removing the microcontroller from the system.1 – P89C51 serial port pins Reset: A high on this pin for two machine cycles while the oscillator is running.1 –P89C51RD2 SFR P89C51 Serial port pins PIN ALTERNATE USE P3. The ISP function uses five pins: TxD.

In this application. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. additional record types will be added to indicate either commands or data for the ISP facility. There are two 16-bit DPTR registers that address the external memory. the ISP firmware will only accept Intel Hextype records.accomplished by measuring the bit-time of a single bit in a received character. If there are zero bytes in the record. Commercial serial ISP programmers are available from third parties. WinISP. a software utility to implement ISP programming with a PC. and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below: :NNAAAARRDD. The “RR” string indicates the record type.DDCC<crlf> In the Intel Hex record.The maximum number of data bytes in a record is limited to 16 (decimal). • New Register Name: AUXR1# • SFR Address: A2H • Reset Value: xxxxxxx0B AUXR1 (A2H): 7 6 5 4 3 2 1 0 Where: - ENBOOT - GF2 0 - DPS DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. The ISP firmware provides auto-echo of received characters. The “AAAA” string represents the address of the first byte in the record. Dual DPTR: The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. this field is often set to 0000. A record type of “01” indicates the end-of-file mark.is available from Philips. Once baud rate initialization has been performed. Select Reg DPS _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 13 . The P89C51RB2/RC2/RD2 will accept up to 16(10H) data bytes. The ISP feature requires that an initial character (an uppercase U) be sent to the P89C51RB2/RC2/RD2 to establish the baud rate.. A record type of “00” is a data record. the “NN” represents the number of data bytes in the record.

Flags and program status word: Flags are bit wise registers provided to store the results of certain program instructions.DPTR0 DPTR1 0 1 The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. The flags are grouped inside the PSW and the power control (PCON) registers. The 8-bit stack pointer (SP) register is used by micro controller to hold an internal RAM address. The GF2 bit is a general purpose user-defined flag. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the GF2 bit. Stack and stack pointer: The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly. that is called the top of the stack. Auxiliary carry (AC).Over flow(OF) and Parity(P) and three general purpose user flags which can be set to one or cleared to zero by the programmer. Note that bit 2 is not writable and is always read as a zero. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 14 . The 89C51 has 4 mathematical flags which include carry (CF). Other instructions can test the conditions of the flag and make decisions based on the flag states.

3.5 Pin Description VCC Supply voltage. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 15 .1.

In this application.GND Ground. In this application. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification. As inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. The Port 3 output buffers can sink/source four TTL inputs. As inputs. Port 0: Port 0 is an open-drain. it uses strong internal pull-ups when emitting 1s. it uses strong internal pull-ups when emitting 1s. As inputs. The Port 2 output buffers can sink/source four TTL inputs. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). Port 2 also receives the highorder address bits and some control signals during Flash programming and verification. Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 16 . bidirectional I/O port. Port 3 also serves the functions of various special features of the P89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. During accesses to external data memory that use 8-bit addresses (MOVX @ RI). Port 2 emits the contents of the P2 Special Function Register.

EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency. however. however. the pin is weakly pulled high. Note. for parts that require 12-volt VPP. EA/VPP External Access Enable. ALE operation can be disabled by setting bit 0 of SFR location 8EH. that one pulse is skipped during each access to external Data Memory. Note. PSEN Program Store Enable (PSEN) is the read strobe to external program memory. PSEN is activated twice each machine cycle. except that two PSEN activations are skipped during each access to external data memory. EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. XTAL1 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 17 . and may be used for external timing or clocking purposes. Setting the ALE-disable bit has noEffect if the micro controller is in external execution mode. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. With the bit set. When the AT89C51 is executing code from external program memory. This pin is also the program pulse input (PROG) during Flash Programming. If desired. that if lock bit 1 is programmed. Otherwise. ALE is active only during a MOVX or MOVC instruction.ALE/PROG Address Latch Enable (ALE) output pulse for latching the low byte of the address during accesses to external memory.

Oscillator and clock circuit: The heart of the micro controller is the crystal oscillator that generates the clock pulses by which all internal operations are synchronized. as shown in Figure 1. Specifying Quartz Crystals Counters and Timers: _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 18 . respectively. since the input to the internal clocking circuitry is through a divide-by-two flip-flop. There are no requirements on the duty cycle of the external clock signal.Input to the inverting oscillator amplifier and input to the internal clock operating circuit. which can be configured for use as an on-chip oscillator. establishes the smallest internal time within the micro controller called the pulse time. or the part of complex instruction be the machine cycle. of an inverting amplifier. but minimum and maximum voltage high and low time specifications must be observed. Either a quartz crystal or ceramic resonator may be used. Pins XTAL1 and XTAL2 are provided for connection of the resonant network to form an oscillator. The smallest internal time to accomplish any simple instruction. XTAL2 Output from the inverting oscillator amplifier. The clock frequency F. To drive the device from an external clock source.The time to execute the instruction is obtained by Tinst = No of cycles x12d Crystal frequency Oscillator Characteristics XTAL1 and XTAL2 are the input and output. XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.

IP.determines the priority of each interrupt. The counters are divided into two 8-bit registers called the timer low (TL0. TL1) and high (TH0. Register SCON controls data communication and register PCON controls data rates and pins RXD (P3.Three 16 bit microprocessor counters named T0 and T1 and T2 are provided for the general use of the programmer.x PRIORITY BITS 0 Interrupt priority level Level (low 0 1 1 0 priority ) Level 1 Level 2 0 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 19 .receive data from external sources using RXD. The other is read only and hold. when combined with the IP SFR. They are the IE. the timer/counter control register (TCON) and certain program instructions. TMOD is dedicated solely to the two timers and can be considered to be two duplicate four bit registers each of which controls the action of one of the TCON has control bits and flags for timers in upper nibble and for timers external interrupts in lower nibble. and IPH. The 89C51 has a serial data communication circuit but uses register SBUF to hold data. SBUF is physically two registers. All counter action is controlled by bit states in the time mode control register (TMOD).There are 3 SFRs associated with the four-level interrupt.x PRIORITY BITS 0 IP. The IPH is located at SFR address B7H. One is write only and used to hold data to be transmitted out of the micro controller using TXD. TH1) bytes. The priority of each interrupt is determined as shown in the following table IPH. The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible.1) connect to the serial data network. Each counter may be programmed to count internal clock pulses acting as a timer or programmed to count external pulses as counter. The function of the IPH SFR.0) and TXD(P3. Serial data Input/Output: One cost –effective way to communicate with other computers is to send and receive data bits serially. Interrupts: The P89C51RB2/RC2/RD2 has a 7 source four-level interrupt structure.

Features like true differential input and reference.Internal operations timer flag0. low power integrating A/D converter designed to easily interface with microprocessors and micro controllers. timer flag1 and the serial port generate three of these automatically interrupt (R1 or T1). the new interrupt will wait until it is finished before being serviced. and typical power consumption of 20mW make the ICL7109 an attractive per-channel alternative to analog multiplexing for many data acquisition applications. 3. it will be stopped and the new interrupt serviced. Features: • 12-Bit Binary (Plus Polarity and Over-Range) Dual Slope Integrating Analog-to-Digital Converter _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 20 . CMOS. maximum input bias current of 10pA. The ICL7109 provides the user with the high accuracy. If an interrupt of equal or higher level priority is being serviced. The RUN/HOLD input and STATUS output allow monitoring and control of conversion timing.2 Analog to Digital converter TC7109A: Description: The ICL7109 is a high performance. the lower priority level interrupt that was stopped will be completed. Five interrupts are provided in the 89C51. The priority scheme for servicing the interrupts is the same as that for the 80C51. low drift versatility and economy of the dual-slope integrating A/D converter. drift of less than 1μV/oC. When the new interrupt is finished. Two interrupts are triggered by external signals provided by circuitry which are connected to pins INT0 and INT1. If a lower priority level interrupt is being serviced. polarity and over-range) may be directly accessed under control of two byte enable inputs and a chip select input for a single parallel bus interface. except there are four interrupt levels rather than two as on the 80C51. A UART handshake mode is provided to allow the ICL7109 to work with industry-standard UARTs in providing serial data transmission. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. low noise.The output data (12 bits.1 1 Level (high priority) 3 Interrupts may be generated by the internal chip operations or provided by external sources.

. .1pA • Operates At Up to 30 Conversions/s • On-Chip Oscillator Operates with Inexpensive 3. . . . . . . .5 Conversions/s for 60Hz Rejection. . . . . . . . . . . . . _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 21 . . . .May Also Be Used with An RC Network Oscillator for other clock frequencies. . TTL Compatible Three-State Outputs and UART Handshake Mode for Simple Parallel or Serial Interfacing to Microprocessor Systems • RUN/HOLD Input and STATUS Output Can Be Used to Monitor and Control Conversion Timing. . .• Byte-Organized. . . .58MHz TV Crystal Giving 7. • True Differential Input and Differential Reference • Low Noise (Typ) . . . . . . . . . . . . . . . . . 15[VP-P] • Input Current (Typ) . . .

and the internal clock will be of the same frequency and phase as the signal at the BUFFERED OSCILLATOR OUTPUT.Oscillator: The ICL7109 is provided with a versatile three terminal oscillator to generate the internal clock. the overdriving signal should be applied at the OSCILLATOR INPUT. The OSCILLATOR SELECT input changes the internal configuration of the oscillator to optimize it for RC or crystal operation. When the OSCILLATOR SELECT input is high or left open (the input is provided with a pullup resistor). The circuit will oscillate at a frequency given by f = 0. and phase as the input signal when OSCILLATOR SELECT is left open. and the OSCILLATOR OUTPUT should be left open. A 100kΩ resistor is recommended for useful ranges of frequency. The oscillator may be overdriven. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 22 . the capacitor value should be chosen such that 2048 clock periods is close to an integral multiple of the 60Hz period (but should not be less than 50pF).45/RC. The internal clock will be of the same frequency. duty cycle.When the OSCILLATOR SELECT input is low a feedback device and output and input capacitors are added to the oscillator If at any time the oscillator is to be overdriven. the oscillator is configured for RC operation. or may be operated with an RC network or crystal. For optimum 60Hz line rejection.

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and are provided with pullup resistors to ensure an inactive high level when left open. which could lead to erroneous data. Direct Mode: When the MODE pin is left at a low level. taking a byte enable input low will allow the outputs of that byte to become active (threestated on). Synchronizing the access of the latches with the conversion cycle by monitoring the STATUS output will prevent this. where the output data is directly accessible under the control of the chip and byte enable inputs. bits 9 through 12. Thus it is possible to access the latches while they are being updated. When the MODE pin is low or left open the converter is in its “Direct” output mode.It should be noted that these control inputs are asynchronous with respect to the converter clock . Data is never updated while STATUS is low. These three inputs are all active low.This allows a variety of parallel data accessing techniques to be used.After the minimum autozero _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 24 . the converter enters the UART handshake mode and outputs the data in two bytes. the converter will output data in the handshake mode at the end of every conversion cycle.the ICL7109 continuously performs A/D conversions with a fixed length of 8192 clock cycles per conversion.the data may be accessed at any time. When the MODE input is left high. the data outputs (bits 1 through 8 low order byte. then returns to “direct” mode.the ICL7109 will complete the conversion in progress. polarity and over-range high order byte) are accessible under control of the byte and chip enable terminals as inputs. RUN/HOLD INPUT: When the Run/Hold input is tied high. When the chip enable input is low.Mode input: The MODE input is used to control the output mode of the converter. When the MODE input is pulsed high.When Run/Hold is taken low.then wait in the autozero phase.

a new conversion will start and status will go high within 7 clock cycles after Run/Hold goes high. Test Input When the TEST input is taken to a level halfway between V+ and GND. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 25 .If the ICL 7109 is holding at the end of the autozero phase. When the RUN/HOLD returns high and the TEST input returns to the 1/2 (V+ .but any pulses during a conversion or upto 2048 clock cycles after Status goes low will be ignored.a high going pulse on Run/Hold of atleast 200 nanoseconds is required to start anew conversion.GND) voltage (or to V+) and one clock is applied. and the internal clock is disabled. the counter outputs are all forced into the high state.time has been completed.all the counter outputs will be clocked to the low state.When the RUN/HOLD is low and the TEST input is connected to GND. This allows easy testing of the counter and its outputs. allowing the counter contents to be examined anytime. the counter output latches are enabled.

3. and ports 3. Port1 is used to furnish the command or data byte. It also contains a user-programmed RAM area(the character RAM) that can be programmed to generate any desired character that can be formed using a dot matrix. The protocol for the display is shown below. G +5V-5V +5V G 1 2 3 15 16 TWO LINES X 16 CHARACTERS INTELLIGENT LCD DISPLAY 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 RS R/W EN 10 11 12 13 14 4 5 6 The display contains two internal byte-wide registers.2 to 3. initializing the interface can be a problem and the displays themselves are expensive. The most common type of LCD controller is the Hitachi 44780.3 LCD (LIQUID CRYSTAL DISPLAY) An intelligent LCD display of two lines. Pins 1 2 Description Ground Vcc _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 26 . 16 characters per line is interfaced to the microcontroller.4 furnish register select and read/write levels. debugging an application or just giving it a "professional" look. the hex command byte 80 will be used to signify that the display RAM address 00h is chosen. In experienced designers do often not attempt using this interface and programming because it is difficult to find good documentation on the interface. To distinguish between these two data areas. which provides a relatively simple interface between a processor and an LCD. one for commands (RS=0) and the second for characters to be displayed (RS=1). LCDs can add a lot to your application in terms of providing an useful interface for the user.

To wire a micro controller to an LCD in four bit mode. While there are secondary considerations and modes. Eight-bit mode is best used when speed is required in an application and at least ten I/O pins are available. two "nibbles" of data (Sent high four bits and then low four bits with an "E" Clock pulse with each nibbles) are sent to make up a full eight bit transfer. Four bit mode requires a minimum of six bits. then the byte at the current LCD "Cursor" Position can be read or written. The ASCII code to be displayed is eight bits long and is sent to the LCD either four or eight bits at a time. If the Bit is set. The "E" Clock is used to initiate the data transfer within the LCD. This waveform will write an ASCII Byte out to the LCD's screen. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 27 . deciding how to send the data to the LCD is most critical decision to be made for an LCD interface application.3 4 5 6 7 – 14 Contrast Voltage "R/S" _Instruction/Register Select "R/W" _Read/Write LCD Registers "E" Clock Data I/O Pins The interface is a parallel bus. If four bit mode is used. The "R/S" bit is used to select whether data or an instruction is being transferred between the micro controller and the LCD. Sending parallel data as either four or eight bits are the two primary modes of operation. allowing simple and fast reading/writing of data to and from the LCD. either an instruction is being sent to the LCD or the execution status of the last instruction is read back (whether or not it has completed). just the top four bits (DB4-7) are written to. When the Bit is reset.

The LCD can be thought of as a "Teletype" display because in normal operation. For most applications. This simplifies the application because when data is read back. it also frees up a micro controller pin for other uses. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 28 . the internal "Cursor" is moved one character to the right.The different instructions available for use with the 44780 are shown in the table below: R/S 4 0 0 0 0 0 0 0 0 0 1 1 R/W 5 0 0 0 0 0 0 0 0 1 0 1 D7 14 0 0 0 0 0 0 0 1 BF D D D6 13 0 0 0 0 0 0 1 A * D D D5 12 0 0 0 0 0 1 A A * D D D4 11 0 0 0 0 1 DL A A * D D D3 10 0 0 0 1 SC N A A * D D D2 9 0 0 1 D RL F A A * D D D1 8 0 1 ID C * * A A * D D D0 7 1 * S B * * A A * D D Instruction/Description Pins Clear Display Return Cursor and LCD to Home Position Set Cursor Move Direction Enable Display/Cursor Move Cursor/Shift Display Set Interface Length Move Cursor into CGRAM Move Cursor to Display Poll the "Busy Flag" Write a Character to the Display at the Current Cursor Position Read the Character on the Display at the Current Cursor Position Reading Data back is best used in applications which required data to be moved back and forth on the LCD (such as in applications which scroll data between lines). the micro controller I/O pins have to be alternated between input and output modes. I recommend just using the maximum delays given above.1 milliseconds for clearing the display or moving the cursor/display to the "home position". just tie the "R/W" line to ground because I don't read anything back. The "Clear Display" and "Return Cursor and LCD to Home Position" instructions are used to reset the Cursor's position to the top right character on the display. 160 microseconds for all other commands). The "Busy Flag" can be polled to determine when the last instruction that has been sent has completed processing. after a character has been sent to the LCD. Different LCDs execute instructions at different rates and to avoid problems later on (such as if the LCD is changed to a slower unit). As well as making my application software simpler. I usually tie "R/W" to ground and just wait the maximum amount of time for each instruction (4. there really is no reason to read from the LCD. In most applications.

which matches the maximum number of LCD character addresses available.To move the Cursor. bit 7 of the instruction byte is set with the remaining seven bits used as the address of the character on the LCD the cursor is to move to. The table above should be used to determine the address of a character offset on a particular line of an LCD display. the "Move Cursor to Display" instruction is used. These seven bits provide 128 addresses. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 29 . For this instruction.

I say "basically" because some characters do not follow the ASCII convention fully (probably the most significant _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 30 .The Character Set available in the 44780 is basically ASCII.

The last aspect of the LCD to discuss is how to specify a contrast voltage to the Display. I noted that the 44780 could interface with four or eight bits. the shift register is cleared by loading every latch with zeros. a shift register is often used (as is shown in the diagram below) to reduce the number of I/O pins to three. The ASCII Control Characters (0x008 to 0x01F) do not respond as control characters and may display funny (Japanese) characters. You may find that different LCDs work differently with lower voltages providing darker characters in some and higher voltages do the same thing in others. Before data can be written to it. I typically use a potentiometer wired as a voltage divider. In the diagram to the right. This will provide an easily variable voltage between Ground and Vcc. the "Data" line is pulsed to Strobe the "E" bit. There are a variety of different ways of wiring up an LCD. Once that is loaded in correctly. which will be used to specify the contrast (or "darkness") of the characters on the LCD screen. a "1" (to provide the "E" Gate) is written followed by the "R/S" bit and the four data bits. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 31 . I have shown how the shift register is written to for this circuit to work.difference is 0x05B or "\" is not available). The biggest difference between the three wire and two wire interface is that the shift register has to be cleared before it can be loaded and the two wire operation requires more than twice the number of clock cycles to load four bits into the LCD. Above. Next. To simplify the demands in micro controllers.

less than 0. The LM35’s low output impedance. The LM35 does not require any external calibration or trimming to provide typical accuracies of ±1⁄4°C at room temperature and ±3⁄4°C over a full −55 to +150°C temperature range. and precise inherent calibration make interfacing to readout or control circuitry especially easy. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 32 . as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling.3. As it draws only 60 μA from its supply. The LM35 is rated to operate over a −55° to +150°C temperature range.linear output.1°C in still air. The LM35 thus has an advantage over linear temperature sensors calibrated in ° Kelvin. whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. it has very low self-heating. It can be used with single power supplies.4 Precision Centigrade Temperature Sensors: LM35 General Description: The LM35 series are precision integrated-circuit temperature sensors. or with plus and minus supplies.

The general equation used to convert output voltage to temperature is: Temperature ( oC) = Vout * (100 oC/V) So if Vout is 1V .FEATURES: • The output voltage is converted to temperature by a simple conversion factor. that is 100 oC/V. then Temperature = 100 oC • • • • The output voltage varies linearly with temperature. The sensor has a sensitivity of 10mV / oC. Use a conversion factor that is the reciprocal. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 33 .

4 MULTIPLEXER CD4051B: _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 34 .Typical Applications: 3.

The CD4052B is a differential 4-Channel multiplexer having two binary control inputs. the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. all channels are off. and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Applications: • Analog and Digital Multiplexing and Demultiplexing • A/D and D/A Conversion • Signal Gating Power Supply _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 35 . and an inhibit input. and C. a VDD-VEE of up to 13V can be controlled. for VDD-VEE level differences above 13V. B. When these devices are used as demultiplexers.5V to +4.5V can be controlled by digital inputs of 0V to 5V. The three binary signals select 1 of 8 channels to be turned on. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. CD4052B. and VEE = -13. and an inhibit input. VSS = 0V. a VDD-VSS of at least 4.5V to 20V (if VDD-VSS = 3V. For example.5V.5V. A and B. independent of the logic state of the control signals. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4. analog signals from -13. The CD4051B is a single 8-Channel multiplexer having three binary control inputs.The CD4051B. if VDD = +4. A. These multiplexer circuits dissipate extremely low quiescent power over the full VDD-VSS and VDD-VEE supply-voltage ranges.5V is required). and connect one of the 8 inputs to the output. When a logic “1” is present at the inhibit input terminal.

Hence the voltage V1 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 36 . Monolithic voltage regulator Rectifier: Here the step down transformer 230-0v/12-0-12V gives the secondary current up to 500mA. The secondary Transformer is provided with a center tap. Rectifier 2.Power supply unit provides 5V regulates power supply to the systems. to the Rectifier. It consists of two parts namely. 1.

and V2 are equal and are having a phase difference of 180 0. So it is anode of Diode D1 which is positive with respect to the center tap, the anode of the other diode d2 will be negative with respect to the center tap. During the positive half cycle of the supply D1 conduct’s and current flows through the center tap D1 and load. During this period D2 will not conduct as its anode is at negative potential. During the negative half cycle of the supply voltage, the voltage on the diode D2 will be positive and hence D2 conducts. The current flows through the transformer winding, Diode D2 and load. It is to be noted that the current i1 and i2 are flowing in the same direction in load. The average of the two current i1 and i2 flows through the load producing a voltage drop, which is the D.C. output voltage of the rectifier. Using monolithic IC voltage regulators, voltage can be regulated. Monolithic IC voltage regulator: A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load currents. Although voltage regulators can be designed using op-amps, it is quicker and easier to use IC voltage regulators. Furthermore, IC voltage regulators are versatile and relatively inexpensive and are available with features such as programmable output, current/voltage boosting, internal short-circuit current limiting, thermal shutdown and floating operation for high voltage applications Here 7800 series voltage regulators are used. The 7800 series consists of 3-terminal positive voltage regulators with seven voltage options. These ICs are designed as fixed voltage regulators and with adequate heat sinking can deliver output currents in excess of 1A. Although these devices do not require external components, such components can be used to obtain adjustable voltages and currents. For proper operation a common ground between input and output voltages is required. In addition, the difference between input and output voltages (Vi – Vo) called drop out voltage, must be typically 1.5V even during the low point as the input ripple voltage. The capacitor Ci is required if the regulator is located at an appreciable distance from a power supply filter. Even though Co is not needed, it may be used to improve the transient response of the regulator. Typical performance parameters for voltage regulators are line regulation, load regulation, temperature stability and ripple rejection. Line regulation is defined as the change in output voltage for a change in the input voltage and is usually expressed in milli volts or as a percentage of Vo. Temperature stability or average temperature coefficient of output voltage (TCVo) is the change in output voltage per unit change in temperature and is expressed in either milli volts/ºC or parts per million (PPM/ºC). Ripple rejection is the measure of a regulator’s

_______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 37

ability to reject ripple voltage. It is usually expressed in decibels. The smaller the values of line regulation, load regulation and temperature stability better the regulation. 3.5 DIFFERENTIAL BUS TRANSCEIVER SN75176: SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data communication on multipoint bus-transmission lines. It is designed for balanced transmission lines and meets ANSI Standard EIA/TIA-422-B and ITU Recommendation V.11.

The heart of this communication is the Texas Instruments SN75176 Differential Bus Transceiver chip. This chip converts RS485 signals to RS232 TTL-level signals allowing devices that traditionally communicate over standard RS232 serial connections to communicate over a single two-wire RS485 network. The SN75176B combines a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be externally connected together to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line applications. The SN75176 chip has only 8 pins Setting RE (Not Receiver Enable) to Low, the R (Receiver) pin is enabled, allowing the micro contrllerr to receive any data coming over the A and B RS485

_______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 38

network lines. Setting DE (Driver Enable) to High allows the microcontroller to transmit data over the RS485 network 3.6 MAX 232 Serial Level Converter : The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels.These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs.Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels.

RS-232 -------------15V ...-3V +3V ... +15V <-> <->

TTL ---------------- +2V ... +5V 0V ... +0.8V

Logic ---------<-> 1 <-> 0

_______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 39

Also the low and high voltage level has to be inverted. Thus the RS-232 signal levels are far too high TTL electronics. because it just needs one voltage (+5V or +3. The MAX232 from Maxim was the first IC which in one package contains the necessary drivers and receivers to adapt the RS-232 signal voltage levels to TTL logic.This protocol defines a message structure that controllers will recognize and use. It became popular. Modern low power consumption logic operates in the range of 0V and +3. It describes the process a controller uses to request access to another device. in which only onedevice (the master) can initiate transactions (called ‘queries’).3V) and generates the necessary RS-232 voltage levels. This level converter uses a Max232 and five capacitors .7 MODICON MODBUS Protocol Modicon programmable controllers can communicate with each other and with other devices over a variety of networks. Typical master _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 40 . 3.regardless of the type of networks over which they communicate.3V or even lower. It establishes a common format for the layout and contents of message fields.24) communication works with voltages -15V to +15V for high and low. The other devices (the slaves) respond by supplying the requested data to the master. or by takingthe action requested in the query. and the negative RS-232 voltage for high can’t be handled at all by computer logic. The common language used by all Modicon controllers is the Modbus protocol. To receive serial data from an RS-232 interface the voltage has to be reduced. how it will respond to requests from the other devices. and how errors will be detected and reported.Serial RS-232 (V. Controllers communicate using a master–slave technique. TTL logic operates between 0V and +5V . and standard networks such as MAP and Ethernet. On the other hand. Supported networks include the Modicon Modbus and Modbus Plus industrial networks.

The data field must contain the information telling the slave which register to start at and how many registers to read. Users select the desired mode. The Two Serial Transmission Modes Controllers can be setup to communicate on standard Modbus networks using either of two transmission modes: ASCII or RTU. The data bytes contain any additional information that the slave will need to perform the function. The Response: If the slave makes a normal response. The error check field provides a method for the slave to validate the integrity of the message contents. parity mode. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 41 .devices include host processors and programming panels. and the data bytes contain a code that describes the error. and expects a response from a slave device. Similarly.during configuration of each controller. For example. The Query–Response Cycle: The Query: The function code in the query tells the addressed slave device what kind of action to perform. Typical slaves include programmable controllers. when a controller receives a message it constructs a slave response and returns it to the originating controller. Slaves return a message (called a ‘response’) to queries that are addressed to them individually. function code 03 will query the slave to read holding registers and respond with their contents. the Modbus protocol still applies the master–slave principle even though the network communication method is peer–to–peer.along with the serial port communication parameters (baud rate. etc). If a controller originates a message. or can initiate a broadcast message to all slaves. At the message level. The master can address individual slaves. such as register values or status. Responses are not returned to broadcast queries from the master. If an error occurs. The data bytes contain the data collected by the slave. The mode and serial parameters must be the same for all devices on a Modbus network . it does so as a master device. the function code is modified to indicate that the response is an error response. the function code in the response is an echo of the function code in the query.

The main advantage of this mode is that it allows time intervals of up to one second to occur between characters without causing an error.It determines how information will be packed into the message fields and decoded.It defines the bit contents of message fields transmitted serially on those networks. hexadecimal 0–9. ASCII characters 0–9. each 8–bit byte in a message is sent as two ASCII characters. A–F One hexadecimal character contained in each ASCII character of the message Bits per Byte: 1 start bit 7 data bits. 2 bits if no parity Error Check Field: RTU Mode: When controllers are setup to communicate on a Modbus network using RTU (Remote Terminal Unit) mode.The selection of ASCII or RTU mode pertains only to standard Modbus networks. no bit for no parity 1 stop bit if parity is used. least significant bit sent first 1 bit for even/odd parity. ASCII Mode: When controllers are setup to communicate on a Modbus network using ASCII(American Standard Code for Information Interchange) mode. Each message must be transmitted in a continuous stream. The format for each byte in RTU mode is: Coding System: 8–bit binary. The format for each byte in ASCII mode is Coding System: Hexadecimal. no bit for no parity 1 stop bit if parity is used. The main advantage of this mode is that its greater character density allows better data throughput than ASCII for the same baud rate. each 8–bit byte in a message contains two 4–bit hexadecimal characters. least significant bit sent first 1 bit for even/odd parity. 2 bits if no parity Longitudinal Redundancy Check (LRC) _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 42 . A–F Two hexadecimal characters contained in each 8–bit field of the message Bits per Byte: 1 start bit 8 data bits.

a Modbus message is placed by the transmitting device into a frame that has a known beginning and ending point. A–F. each device decodes it to find out if it is the addressed _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 43 . When the first field (the address field) is received. each device decodes the next field (the address field) to find out if it is the addressed device.Error Check Field Modbus Message Framing: Cyclical Redundancy Check (CRC) In either of the two serial transmission modes (ASCII or RTU). messages start with a silent interval of at least 3. This allows receiving devices to begin at the start of the message. Networked devices monitor the network bus continuously for the ‘colon’ character.This is most easily implemented as a multiple of character times at the baud rate that is being used on the networkThe allowable characters transmitted for all fields are hexadecimal 0–9.read the address portion and determine which device is addressed (or all devices. A–F. LRC FUNCTION DATA START 1CHAR ADDRESS 2 CHARS 2 CHARS N CHARS CHECK 2 CHARS END 2 CHARS CRLF ASCII MESSAGE FORMAT RTU Framing In RTU mode. Intervals of up to one second can elapse between characters within the message.5 character times.Networked devices monitor the network bus continuously. ASCII Framing In ASCII mode.if the message is broadcast). Partial messages can be detected and errors can be set as a result. and to know when the message is completed. including during the ‘silent’ intervals. messages start with a ‘colon’ ( : ) character (ASCII 3A hex).When one is received. The allowable characters transmitted for all other fields are hexadecimal 0–9. and end with a ‘carriage return – line feed’ (CRLF) pair (ASCII 0D and 0A hex).

5 character times occurs before completion of the frame. If a silent interval of more than 1.device. the error checking field contains a16–bit value implemented as two 8–bit bytes. the receiving device will consider it a continuation of the previous message. the receiving device flushes the incomplete message and assumes that the next byte will be the address field of a new message. A typical message frame is shown below LRC FUNCTIO START T1-T2-T3-T4 ADDRESS 8 BITS N 8 BITS DATA N* BITS RTU MESSAGE FRAME When RTU mode is used for character framing. each character or byte is sent in this order (left to right): With RTU character framing. as the value in the final CRC field will not be valid for the combined messages. Similarly.5 character times following a previous message. This will set an error. the low–order byte of the field is appended first. if a new message begins earlier than 3. The error check value is the result of a Cyclical Redundancy Check calculation performed on the message contents The CRC field is appended to the message as the last field in the message.The entire message frame must be transmitted as a continuous stream. The CRC high–order byte is the last byte to be sent in the message. When this is done. followed by the high–order byte. When messages are transmitted on standard Modbus serial networks. the bit sequence is: Bit Order(RTU): With parity checking start 1 2 3 4 5 6 7 8 par stop CHECK 8 16 BITS END T1-T2-T3T4 Without parity checking _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 44 .

0 : SINGLE TASK : 15-01-2010 LAST MODIFIED Dt: 26-01-2011 added No parity feature and LED1 for Rx communication LED2 for Tx communication LED1 & 2 Blinking for Error //features added .8 data. .code 03 Read Input Reg.Com settings 19200.C & I (F) .h> #include <mbrtu.0 SOFTWARE /* ------------------------------------------------------------------------------*/ N U O F P .*/ #define MY_ADD 1 // FILES INCLUDED #include <gnrl_typ.h> #include <reg52.1 stop.start 1 2 3 4 5 6 7 8 stop stop 4. no parity ------------------------------------------------------------------------.input register address ranges from 0000 to 0007 .NUCLEAR FUEL COMPLEX PROJECT MCU MEMORY : MCU BASED ANALOG DATA AQUISITION : AT89C51 : 64 K ROM (PROGRAM MEMORY) 2 K EEPROM (SERIAL) UTILITY VERSION ORGANISATION START Dt : MCS51 KEIL 'C'COMPILER : V0.h> #include <header.channel data canbe read through func.c> //MCU internal //project header // key scan _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 45 .

rx_state = START. } } if(msecs_rt) msecs_rt--. } else f_dummy_pkt = 0. if(!f_error) po_led1=OFF. if(rtu_tout==0){ if(!f_dummy_pkt){ f_pkt_ready = 1. two_msecs_count++. // K_TIMER0_HI. if(!f_dummy_pkt){ f_pkt_ready = 1. } else f_dummy_pkt = 0. rx_state = START. /* for 1msec interrupt */ _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 46 .//-----------------------------------------------------------/* void timer1 (void) interrupt 3{ ET1 = 0. } */ //-------------------------------------------------------------------------void timer0 (void) interrupt 1 using 1{ TL0 = 0xff. // else msecs_rt = 0. //K_TIMER0_LO. if(rtu_tout){ rtu_tout--. TH0 = 0xf3. TR1 = 0. if(!f_error) po_led1=OFF.

Run_adc(). po_led2 = ~po_led2. com_send(). case 3:break. case 10: default:two_msecs_count = 0. case 8:break. case 7:break. po_led1 = ~po_led1. case 6:break. } } //---------------------------------------------------// void serial_port_int(void)interrupt 4 using 2 { unsigned char sbuf. case 4: if(f_error){ one_sec_count++. if(one_sec_count > 20){ one_sec_count=0. switch(two_msecs_count){ case 1: case 2:break. } } break. if(TI){ TI=0. case 9:break. case 5:break. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 47 .

// TH0 = K_TIMER0_HI. // TL2 = RCAP2L = K_RCAP2L. /* disable the interrupts */ P1 = K_P1_DIRECTION. /* direction assignment to the ports */ P2 = K_PORT2_DIRECTION. RI = 0. com_receive(sbuf). // TL1 = K_TIMER1_LO. // TL0 = K_TIMER0_LO. P0 = K_PORT0_DIRECTION. } //--------------------------------------------------void initialise(void){ IE = 0. // T2CON = K_T2CON. msecs_rt = 0. P3 = K_P3_DIRECTION. // SCON = K_SCON.} if(RI){ sbuf = SBUF. // TCON = K_TCON. } } //--------------------------------------------------void adc_status_isr(void)interrupt 0 using 3{ f_eoc = 1. /* reload the timer values */ /* for 2msec interrupt */ _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 48 . // TMOD = K_TMOD. // TH2 = RCAP2H = K_RCAP2H. po_adc_run = HOLD. EX0 = 0.

//power on blinking ES=0. po_485_en = 0. TCON=0x50. // IE = K_IE. // IE = K_IE. TL1=0xFB. TH0=0xF3. adc_run_state = STEP1. SCON=0x50. po_led2 = OFF. // EA = 1. // TR1 = 0. po_adc_oebar = 1.// TH1 = K_TIMER1_HI. po_adc_run = HOLD. TMOD=0x21. // ET1 = 0. ET0=1. // ES = 1. TB8 = 1. ES=1. TL0=0xFF. TH1=0xFB. current_ch = 0. /* global enable the interrupts */ _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 49 . } //----------------------------------------------------------// void main(void){ initialise(). EA=1. po_led1 = OFF.

combuf[gc2++] = analog_values[gc1]. gc2 = 3. combuf[2] = 16. po_led2 = OFF. for(gc1=0. gc2++){ po_led1 = po_led2 = ON. while(1){ if(f_pkt_ready){ if(!check_crc()){ f_error = 1. combuf[1] = FC_READ_HOLDING_REGISTERS . } ES=1. com_init(). gc1++){ for(gc2=0. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 50 . } delayms(1200). po_led1 = OFF. gc1<8. gc2<3.f_error = 0. } else{ f_error = 0. delayms(200). gc1++){ combuf[gc2++] = (analog_values[gc1]>>8). f_pkt_ready = 0. gc1<3. delayms(300). po_led1 = po_led2 = OFF. po_led1 = po_led2 = OFF. if(combuf[1]==FC_READ_HOLDING_REGISTERS ){ combuf[0] = MY_ADD. for(gc1=0. delayms(300).

f_eoc = 0. case STEP3: if(!f_eoc)break. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 51 . po_adc_oebar = 0. adc_run_state = STEP3. case STEP2: po_adc_run = RUN. } } } } //-----------------------------------------------------------------------// void delayms(unsigned int tag){ msecs_rt = tag. a = ADC_DATA_HI. break. f_pkt_ready = 0. } //-----------------------------------------------------------------------// void Run_adc(void) using 1{ unsigned int a.} } nw_send(19). a <<= 8. EX0 = 1.current_ch). while(msecs_rt). switch(adc_run_state){ case STEP1: P1 &= 0xe0. adc_run_state = STEP2. break. P1 |= (15 .

01 No. analog_values[current_ch] = a. of data bytes read 1st eight coils (Byte 1) 2nd eight coils (Byte 2) -0X01 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 52 . break. adc_run_state = STEP1. } } //-----------------------------------------------------------------------// “END OF AI” //-----------------------.of coils Lo <.of coils Hi No.a += ADC_DATA_LO. a &= 0xfff. break.MODBUS. case STEP4: current_ch++. if(current_ch > 7) current_ch = 0. po_adc_oebar = 1.C-----------------------------------// MODBUS COM ROUTINES IN RTU MODE //--------------------------------------------------------------------/* //MODBUS FUNCTION CODES #define FC_READ_COIL_STATUS -> 01 1st coil add Hi 1st coil add Lo No. adc_run_state = STEP4.

03 No.of Register Hi (set to 0) No.02 No.-#define FC_READ_INPUT_STATUS -> 02 1st input add Hi 1st input add Lo No. of data bytes read 1st eight inputs (Byte 1) 2nd eight inputs (Byte 2) --#define FC_READ_HOLDING_REGISTERS 0X03 -> 03 1st Register add Hi 1st Register add Lo No.of inputs Hi No.of Register Lo <. of data bytes read 1st Register Hi 1st Register Lo 2nd Register Hi 2nd Register Lo --#define FC_READ_INPUT_REGISTERS -> 04 1st Register add Hi 0X04 0X02 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 53 .of inputs Lo <.

06 0x06 0x05 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 54 . of data bytes read 1st Register Hi 1st Register Lo 2nd Register Hi 2nd Register Lo --#define FC_FORCE_SINGLE_COIL -> 05 coil add Hi coil add Lo (High Byte) 0xff = Coil SET or 0x00 = Coil RESET (Low Byte) Set to 00 <.05 coil add Hi coil add Lo (High Byte) 0xff = Coil SET or 0x00 = Coil RESET (Low Byte) Set to 00 #define FC_PRESET_SINGLE_REGISTER -> 06 Reg add Hi Reg add Lo New Reg Data(High Byte) New Reg Data(Low Byte) <.1st Register add Lo No.of Register Hi (set to 0) No.of Register Lo <.04 No.

of coils force Low #define FC_PRESET_MULTIPLE_REGISTERS 0x10 -> 10 1st Register add Hi 1st Register add Lo No.Reg add Hi Reg add Lo New Reg Data(High Byte) New Reg Data(Low Byte) #define FC_FORCE_MULTIPLE_COILS 0x0F -> 0F 1st coil add Hi 1st coil add Lo No. of bytes in the Query data buffer Query data buffer first byte --<.0F 1st coil add Hi 1st coil add Lo No.of Register Hi No. of coils forced Hi No. of coils force Low No. of coils forced Hi No.10 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 55 .of Register Lo No. of bytes in the Query Data Buffer Query Data Buffer First Byte --<.

delayms(2).5 char // TB8 = get_even_parity(combuf[0]). f_dummy_pkt = 0. TI=0. combuf_index = 1. //Pkt start 3.of Register Lo */ //--------------------------------------------------------// void com_init(void){ po_485_en = 0. delayms(2). combuf_count = length. po_led2 = OFF. // f_pkt_ready = 0.1st Register add Hi 1st Register add Lo No. tx_state = START. combuf_count = 0. f_parity_error = 0. combuf[length++] = crcLO. f_transmission_over=0. rx_state = tx_state = START. while(!f_transmission_over). po_led2 = ON. f_pkt_ready=0. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 56 . f_transmission_over=1.5 char po_485_en=1. combuf[length++] = crcHI. } //--------------------------------------------------------// void nw_send(unsigned char length){ get_crc(length). //Pkt start 3. SBUF = combuf[0].of Register Hi No.

case STEP1: f_transmission_over=1. if(!f_error) po_led1=ON. //Pkt start 3.5 char po_485_en = 0. SBUF = combuf[combuf_index++]. if(scombuf!=MY_ADD){ f_dummy_pkt = 1. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 57 . rx_state = STEP1. combuf_count = 0. if(combuf_index >= combuf_count) tx_state = STEP1. tx_state = START. // break. f_parity_error = 0.delayms(2). } //--------------------------------------------------------// void com_send(void) using 2 { switch(tx_state){ case START: if(combuf_count){ //TB8 = get_even_parity(combuf[combuf_index]). } else f_dummy_pkt = 0. po_485_en = 0. } } //--------------------------------------------------------// void com_receive(unsigned char scombuf) using 2 { switch(rx_state){ case START: if(f_pkt_ready)break. } break.

ET1 = 1. } } break.if(!f_dummy_pkt){ combuf[0] = scombuf. //if(get_even_parity(scombuf) != RB8) f_parity_error = 1. TL1 = K_TIMER1_LO. } } //-------------------------------------------------------bit nw_receive(void){ msecs_rt = RX_TIMOUT. TH1 = K_TIMER1_HI. case STEP1: // // // // TR1=0. //if(get_even_parity(scombuf) != RB8) f_parity_error = 1. TL1 = K_TIMER1_LO. TH1 = K_TIMER1_HI. rtu_tout=5. rtu_tout=5. // // // // break. TR1 = 1. while(!f_pkt_ready){ if(!msecs_rt)return 0. TR1=1. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 58 . } combuf_count = 1. } return 1. if(!f_dummy_pkt){ if(combuf_count < INBUF_LIMIT){ combuf[combuf_count++] = scombuf.

0. 0. 1. //80-8f 0.1.0 //f0-ff }.1. get_crc(combuf_count-2). if(crcLO != combuf[combuf_count-1])return 0.0. //90-9f 0. 0. //30-3f 1.0. //70-7f 1.0. } //--------------------------------------------------------// _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 59 . //10-1f //60-6f 1.1. } //--------------------------------------------------------// unsigned char code even_parity_table[256]={ if(crcHI != combuf[combuf_count-2])return 0. 1.0. //--------------------------------------------------------// bit get_even_parity(unsigned char val){ if(even_parity_table[val])return //b0-bf //20-2f 0. 0.0. //c0-cf //a0-af //40-4f //0-0f return //50-5f 0. 0.0. //e0-ef} //--------------------------------------------------------// bit check_crc(void){ //if(f_parity_error)return 0.0.0. //d0-df else return 0.1.

0x81. 0x40. 0xC0. 0xC0. 0x01. 0x81. 0x40. 0x81. 0x40. 0x01. 0x41. 0x81. 0xC1. 0x00. 0x41. 0x80. 0xC0. 0x81. 0xC0. 0xC0. 0x40. 0xC0. 0xC0. 0xC0. 0x01. 0x81. 0x01. 0xC0. 0x40./* Calculation of crc for modbus message combuffer. 0x01. 0xC1. 0x00. 0x41. 0xC0. 0xC1. 0x40. 0x01. 0x00. 0x81. 0x00. 0xC1. 0x81. 0x00. 0x81. 0x40. 0x00. 0x80. 0x81. 0x40. 0x40. 0x40. 0xC0. 0x40. 0xC1. 0x81. 0x81. 0x00. 0x80. 0xC0. 0x80. 0x40. 0x80. */ /* Table of CRC values for highorder byte */ unsigned char code HItbl[] = { 0x00. 0x00. 0x41. 0x80. 0x40. 0x80. 0x41. 0x40. 0x01. 0xC1. 0x41. 0x01. 0x00. 0xC1. 0x81. 0x00. 0x41. 0x40. 0x40. 0x00. 0x00. 0x01. 0x41. 0x80. 0x01. 0x00. 0x41. 0x81. 0x01. 0xC0. 0x41. 0x41. 0x40. 0x40. 0x01. 0x41. 0x80. 0x80. 0x41. 0x01. 0x80. 0xC1. 0x00. 0x01. 0x01. 0x80. 0x41. Arguments:message pointer. 0xC1. 0x01. 0x40. 0xC1. 0xC1. 0x01. 0x01. 0xC0. 0x00. 0xC0. 0x00. 0x40. 0x01. 0x01. 0x41. 0xC0. 0x80. 0x41. 0x41. 0x00. 0x81. 0xC0. 0x41. 0x41. 0xC1. 0xC0. 0x81. 0xC0. 0xC1. 0x81. 0xC0. 0x00. 0xC1. 0x41. 0x01. 0x80. 0x40. 0x40. 0x80. 0x81. 0x00. 0x81. 0x80. 0x81. 0x80. 0x80. 0x41. 0xC1. 0x41.e. 0x80. 0xC1. 0x00. 0x00. 0x41. 0x41. 0x40. 0x80. 0x81. 0x80. 0x00. 0x40. 0x40. 0x00. 0x01. 0x80. 0xC1. 0x40. 0x40. 0x40. 0x81. 0x81. 0x81. 0x80. 0x41. 0x80. 0x41. 0x80. 0xC0. 0x81. 0x01. 0xC1. 0xC1. 0xC0. 0x01. 0xC1. 0x81. 0xC1. 0x81. 0x41. 0x00. 0x41. 0xC0. 0x00. 0x80. 0x00. 0xC1. 0x81. 0x81. ret value can be send HI byte first Low byte next. 0xC1. 0xC0. 0x00. 0x41. 0xC1. 0x41. 0x80. 0xC0. 0xC0. 0xC1. 0xC1. 0x40. 0x00. 0x80. 0xC0. 0x01. 0xC1. 0xC1. 0x81. 0xC0. 0xC1. 0xC0. 0x81. 0x01. 0x01. 0x01. 0xC0. 0x80. 0x01. 0xC0. 0xC0. 0x00. 0x80. 0x40 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 60 . 0x81. 0xC1. 0x40. 0x00. 0x40.length of the message Return value: unsigned int value or crc (Already swapped) i. 0x41. 0xC1. 0x80. 0x01. 0x80. 0x01. 0x00. 0x01. 0x41. 0xC1.

0x16. 0xEE. 0xD0. 0x4C. 0x74. 0xB1. 0x98. 0x78. 0x09. 0xBD. 0x51. 0x92. 0xAB. 0x40 }. 0x6C. 0x75. 0x1E. 0x41. 0xED. 0x8D. 0x7F. 0x7B. 0x13. 0x23. 0xAD. 0x84. 0x71. 0x2C. 0xF3. 0x08. 0xA7. 0xB3. 0xCB. 0x3F.a. 0x3B. 0xEA. 0x8E. 0x31. 0x63. 0xE2. 0x0C. 0x79. 0xD5. 0x10. 0x88. 0xEF. void get_crc(unsigned char length){ unsigned char index. 0x97. 0xDC. 0xB4. 0x4B. 0x07. 0x80. 0xAC. 0xDF. 0x83. 0x7D. 0xBF. 0x2E. 0x29. 0x22. 0x53. 0x9F. 0x72. 0x96. 0x20. 0xF5. 0xA6. 0xD9. 0x91. 0x45. 0x3D. 0xA1. 0xB0. 0xAF. 0x36. 0x6D. 0x81. 0xEB. 0x18. 0xC7. 0x9C. 0xFC. 0x3C. 0x6B. 0x8A. 0xBE. 0x0B. 0x42. 0x5A. 0xC6. 0xF2. 0xCC. 0xE7. 0x89. 0x47. 0x9A. 0xF8. 0x0E. 0x62. 0x2D. 0x6F. 0x85. 0x1D. 0x49. 0xB2. 0x87. 0xD8. 0xD6. 0x01. 0x0F. 0xFB. 0x26. 0x3E. 0x59. 0x37. 0x28. 0xF9. 0x9D. 0x27. 0xD3. 0x50. 0x6E. 0xF4. 0xD1. 0x95. 0xB6. 0xE6. 0xD4. 0x77. 0xBB. 0x93. 0x2A. 0x44. 0xC4. 0xA8. 0x73. 0x4E. 0xC9. 0x7A. 0x4A. 0x52. 0x60. 0xA5. 0xC5. 0x4F. 0xF7. 0xBA. 0x14. 0x0A. 0xBC. 0x5C. 0xC0. 0xB8. 0xDA. 0xDB. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 61 .}. 0xFA. 0xC8. 0xCA. 0x70. 0xE8. 0x67. 0x33. 0xE3. 0xA2. 0x6A. 0x02. 0x54. 0x4D. 0x8F. 0x05. 0x21. 0xA9. 0x5F. 0x82. 0x17. 0xCD. 0x35. 0x1F. 0x12. 0x15. 0x3A. 0xFE. 0x65. 0x03. 0x8B. 0xEC. 0x39. 0xCE. 0x66. 0x69. 0xF0. 0x1A. 0x32. 0x5E. 0x9B. 0x86. 0x0D. 0x8C. 0xDE. 0xE4. 0xC1. 0xC3. 0x64. 0x1C. 0x34. 0xB7. 0xFF. 0x90. 0x94. 0xFD. 0x06. 0xE5. 0x38. 0x58. 0xE0. 0xAE. 0x76. 0x99. 0xE1. crcHI = crcLO = 0xff. 0xA3. 0xD7. 0xF1. 0xA4. 0x48. 0x25. 0x61. 0xDD. 0xCF. 0xB5. 0x43. 0x2B. 0xA0. 0x9E. 0x19. 0x5D. 0x24. 0x1B. 0x7E. 0xB9. 0xE9. 0x2F. 0xAA. 0x55. 0x56. 0x5B. 0x30. 0xF6. 0x04. /* Table of CRC values for loworder byte */ unsigned char code LOtbl[] = { 0x00. 0xC2. 0x46. 0x7C. 0xD2. 0x57. 0x11. 0x68.

T_INT32. crcHI = (crcLO ^ HItbl[index]).GNRL_TYP. “END OF GENERAL” _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 62 . while(length--){ index = (crcHI ^ combuf[a]).ON=1}. typedef unsigned int T_UINT16.TRUE=1}. enum {FALSE=0. typedef unsigned long T_UINT32. enum {OFF=0. } } //--------------------------------------------------------// “END OF MODBUS PROT” //-----------------. a++. typedef unsigned char UC.a=0. T_INT16. typedef unsigned int USI. crcLO = LOtbl[index].H -------------------------------typedef unsigned char T_UINT8. typedef char typedef int typedef long int T_INT8. typedef unsigned long ULI.

Freq.3 Baud Rate = Osc.[Osc./* ******************** PROJECT HEADER ******************************** */ #define CRYSTAL 20 #define K_P1_DIRECTION #define K_P3_DIRECTION 0xff 0xff 0Xff 0Xff #define K_PORT0_DIRECTION #define K_PORT2_DIRECTION //for 1msecs #define #define #define TIMER_COUNT K_TIMER0_LO K_TIMER0_HI (0XFFFF-0x682) (unsigned char)(TIMER_COUNT%0X100) (unsigned char)(TIMER_COUNT/0X100) //rtu delay for 4msecs #define #define #define /* #define #define #define #define */ /* modes 1./(32*[65536-RCAP]) RCAP = 65536 .Freq/(32*BR)] */ //for 19200 baud #define K_RCAP2H 0xff RTU_START_DELAY TIMER1_COUNT K_TIMER1_LO K_TIMER1_HI (50000000/K_BAUD) (0XFFFF-((RTU_START_DELAY*CRYSTAL)/12)) (unsigned char)(TIMER1_COUNT%0X100) (unsigned char)(TIMER1_COUNT/0X100) RTU_DELAY K_TIMER1_LO K_TIMER1_HI (0XFFFF-0x1A08) (unsigned char)(RTU_DELAY%0X100) (unsigned char)(RTU_DELAY/0X100) _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 63 .

enable */ /* EA IE.SM1 //SCON.SM0 //SCON.6 .1 .4 ET1 IE. enable */ /* serial int.5 .4 .TB8 //SCON.3 0X0A _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 64 .SM2 //SCON.7 ES IE.4 TR1 TCON.TI //SCON.2 .#define /* K_RCAP2L 0xE0 //for 9600 baud #define #define */ #define K_T2CON #define K_T2MOD #define #define K_TMOD K_TCON 0X051 0x34 0 0X011 K_RCAP2H 0xff K_RCAP2L 0xbf /* timer0 run timer1 run */ /* TR0 TCON.7 .REN //SCON.RI #define K_IE 0X12 /* timer0 int.RB8 //SCON.0 .3 .6 */ #define K_SCON 0x58 //SCON.

= P3^2. = P1^0. = P1^6.1 EX0 IE.2 ET0 IE. = P1^4.4 #define ON #define OFF //-------------------------------------------------------------------------//port1 pins declarations sbit po_mux_a0 sbit po_mux_a1 sbit po_mux_a2 sbit po_mux_a3 sbit po_mux_oebar sbit po_led1 sbit po_led2 sbit po_17 sbit pio_sdata = P3^6. sbit po_nvr_clk = P3^7. //p3. = P1^5.2 K_IP 0X02 */ 0 1 0X008 /* PS IP.0 */ #define PT1 IP. //return error //port3 pins declarations sbit po_485_en sbit po_adc_oebar sbit pi_adc_status sbit po_adc_run = P3^3.EX1 IE. = P1^3. = P1^7. = P1^1. = P3^4.5 #define ADC_DATA_LO P0 #define ADC_DATA_HI P2 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 65 .3 PX1 IP. = P1^2. = P2^6.

gc2.. //----------------------. //unsigned long int data gl2. unsigned char rtu_tout. void delayms(unsigned int). T_UINT8 two_msecs_count. unsigned int idata analog_values[8]. void Run_adc(void). //T_UINT8 data buf[20].nvr. void timer0 (void).gc3.gc4. void initialise(void). unsigned int data gi1.#define RUN bit f_eoc. T_UINT8 data gc1.adc_run_state.h #define FADD 0xa0 #define PADD 0 #define SIZE #define PSIZE 8 #define ENABLE 1 #define DISABLE 0 //data base organisation in eeprom //50 bytes for prgramming parameters 0X800 ------------------------------------// //fixed address for at24cxx eeproms //2kbytes for 24c16 //programmable add (0.one_sec_count.gi2. unsigned int data msecs_rt.7) //8bytes _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 66 . 1 #define HOLD 0 unsigned char data current_ch. //unsigned char idata tid[10]. bit f_error.

bit load_add(T_UINT16 add). bit shout(void). bit start (void). 0 A_CH1_zero+2 A_CH2_zero+2 A_CH3_zero+2 A_CH4_zero+2 A_CH5_zero+2 A_CH6_zero+2 A_CH7_zero+2 A_CH8_zero+2 A_CH1_span+2 A_CH2_span+2 A_CH3_span+2 A_CH4_span+2 A_CH5_span+2 A_CH6_span+2 A_CH7_span+2 sbit rtc_bdata_bit0 = rtc_bdata^0. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 67 .T_UINT16 val). void nvr_write_int(T_UINT16 add.#define A_CH1_zero #define A_CH2_zero #define A_CH3_zero #define A_CH4_zero #define A_CH5_zero #define A_CH6_zero #define A_CH7_zero #define A_CH8_zero #define A_CH1_span #define A_CH2_span #define A_CH3_span #define A_CH4_span #define A_CH5_span #define A_CH6_span #define A_CH7_span #define A_CH8_span unsigned char bdata rtc_bdata. void nvr_write_byte(T_UINT16 add.T_UINT8 byte).T_UINT8 byte). void error(void). void shin(void). T_UINT8 nvr_read_byte(T_UINT16 add). sbit rtc_bdata_bit7 = rtc_bdata^7. void stop(void). void no_ack(void). bit random_read(T_UINT16 add). bit nvr_byte_write(T_UINT16 add.

T_UINT16 nvr_read_int(T_UINT16 add).modbus. //----------------------.h -------------------------------// #define INBUF_LIMIT 50 #define START_FLAG #define CR #define LF 0x0d 0x0a ':' #define START 1 #define STEP1 2 #define STEP2 3 #define STEP3 4 #define STEP4 5 #define STEP5 6 #define STEP6 7 #define UNKNOWN 0 #define ANALOG_INPUT 1 #define ANALOG_OUTPUT 2 #define DIGITAL_INPUT 3 #define DIGITAL_OUTPUT 4 #define DISPLAY_UNIT 5 //function codes from host #define FC_ACK #define FC_NWSEND #define FC_RUN #define FC_STOP 0X20 0X21 0X22 0X23 0X24 0X25 #define FC_MEM_WRITE #define FC_MEM_READ #define FC_RESET 0X26 _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 68 .

bit f_dummy_pkt. void get_crc(unsigned char length). void com_receive(unsigned char sbuf).f_transmission_over. bit nw_receive(void). void nw_send(unsigned char len).combuf_index. bit f_pkt_ready.tx_state. unsigned char data com_timeout. void com_send(void). unsigned char data combuf_count. unsigned char data crcLO. unsigned char idata combuf[30]. //-----------------------------------------------------------“END OF HEADER” _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 69 . void com_init(void). unsigned char data rx_state. bit check_crc(void).crcHI. bit f_parity_error. bit get_even_parity(unsigned char val).#define FC_REPORT_SLAVE 0X27 #define FC_LOAD_DEFAULTS 0X28 #define FC_TIMEOUT 0X29 #define FC_FORCE_DATA_REGISTERS 0X2A //MODBUS FUNCTION CODES #define FC_READ_COIL_STATUS #define FC_READ_INPUT_STATUS #define FC_READ_INPUT_REGISTERS #define FC_PRESET_SINGLE_REGISTER 0X01 0X02 0X04 0x06 #define FC_READ_HOLDING_REGISTERS 0X03 #define FC_PRESET_MULTIPLE_REGISTERS 0x10 #define RX_TIMOUT 500 //unsigned int idata values[16].

sfr IE = 0xA8. sfr TH1 = 0x8D. sfr DPL = 0x82. sfr DPH = 0x83. Inc. sfr ACC = 0xE0. sfr SP = 0x81. sfr TL0 = 0x8A. sfr TCON = 0x88. sfr SCON = 0x98. = 0xB0. sfr TMOD = 0x89.. sfr TH0 = 0x8C. sfr TL1 = 0x8B. 1987-1992 *----------------------------------------------------------------------------*/ /* 8052 Processor Declarations */ /* BYTE Registers */ sfr P0 sfr P1 sfr P2 sfr P3 = 0x80. sfr B = 0xF0. = 0xA0. /* 8052 Extensions */ sfr T2CON = 0xC8. sfr SBUF = 0x99. = 0x90. _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 70 ./* *----------------------------------------------------------------------------* Copyright (c) KEIL ELEKTRONIK GmbH and Franklin Software. sfr RCAP2L = 0xCA. sfr IP = 0xB8. sfr PSW = 0xD0. sfr PCON = 0x87.

sbit OV sbit P = 0xD2. /* IP */ _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 71 . sbit EX0 = 0xA8. sbit IE1 = 0x8B.sfr RCAP2H = 0xCB. = 0xD6. sbit TR0 = 0x8C. sbit ES = 0xAC. = 0xD5. sfr TL2 = 0xCC. sbit EX1 = 0xAA. sbit RS1 = 0xD4. = 0xD0. /* IE */ sbit EA = 0xAF. sbit ET1 = 0xAB. sbit ET0 = 0xA9. sbit IE0 = 0x89. sbit TF0 = 0x8D. /* BIT Registers */ /* PSW */ sbit CY sbit AC sbit F0 = 0xD7. sbit IT1 = 0x8A. /* TCON */ sbit TF1 = 0x8F. sbit RS0 = 0xD3. sbit IT0 = 0x88. sfr TH2 = 0xCD. sbit TR1 = 0x8E.

sbit PS = 0xBC. = 0xB4. /* SCON */ sbit SM0 = 0x9F. sbit WR = 0xB6. sbit PT0 = 0xB9. sbit SM2 = 0x9D. sbit PX1 = 0xBA. = 0x98. /* 8052 Extensions */ /* IE */ sbit ET2 = 0xAD. sbit TXD = 0xB1. sbit RXD = 0xB0. /* IP */ sbit PT2 = 0xBD. sbit TB8 = 0x9B. sbit INT1 = 0xB3. sbit PX0 = 0xB8. sbit INT0 = 0xB2. sbit TI sbit RI = 0x99. sbit RB8 = 0x9A. sbit PT1 = 0xBB. /* P3 */ sbit RD sbit T1 sbit T0 = 0xB7. sbit SM1 = 0x9E. = 0xB5. /* P1 */ _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 72 . sbit REN = 0x9C.

sbit T2IP = 0xCE. sbit TR2 = 0xCA. sbit T2RSE = 0xCC. sbit BGEN = 0xCB. /* T2CON */ sbit TF2 = 0xCF. sbit T2 = 0x90. sbit CP_RL2= 0xC8. sbit C_T2 = 0xC9. sbit T2IE = 0xCD.sbit T2EX = 0x91. “END” _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 73 .

0 SCHEMATIC DIAGRAM: _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 74 .5.

6.0 Conclusions and recommendations _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 75 .

Ayala.html _______________________________________________________________________ _ Micro Controller Based analog 8 channel Data Acquisition System 76 . J.0 REFERENCES: References 1.THE 8051 Microcontroller and Embedded Systems-By Mazidi Web sites 1www.best-microcontroller-projects.7. Hall.com/temperature-recorder.com/prodinfo/dataacquisition.html 3 www.com (Micro controller) 2 http://www. 3.atmel. 8051 programming and applications –By K. 2.omega. Microprocessors and interfacing –By Douglas V.

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