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# EDSA T2K Design Master

## 1.0 Scope of a Load Flow Analysis

A Load Flow analysis is used to evaluate the running steady-state condition of a system, under different
load, supply and configuration conditions. The idea behind the load flow algorithm is to determine the
following parameters, given that the load consumption at all busses is known:

## a. Power flow in each branch (Lines & Transformers).

b. Power consumption at each source of generation.
c. Voltage magnitude and electrical angle at each bus.
d. System Losses.

Once this data is known, corrective actions can be taken in order to ensure that every load is supplied
with power that is within the acceptable limits of operation. Such actions can include the calculation of:

## a. Transformer tap settings.

b. Reactive power compensation.
c. Generator set points.
d. Emergency power requirements.

A properly built load flow model of the system, lays a solid foundation for other important studies such
as short circuit, motor starting, harmonic and transient stability. The load flow model constitutes the
basic network information and the initial steady-state condition which these studies rely upon.

Loads in general can be modeled in 4 different ways:

## a. Constant Power Load (kVA)

b. Constant Current (Amps)
c. Constant Impedance (Ohms)

Notes:

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Page LF.1
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 2.1 Constant Power Load (kVA)

This type of load is treated as constant demand of power. The load flow algorithm will attempt
convergence under the premise that these types of loads always draw the kVA specified by the user.
Caution should be exercised when interpreting the convergence results in the presence constant kVA
loads. To illustrate this, let’s assume that a given load is rated 1.2kVA at 120 Volts; let’s further assume
that the system experiences excessive losses (say 20% voltage drop on the load’s supply branch).
Under these circumstances the only way in which the system can sustain the load at the prescribed kVA
is by supplying more current in order to compensate for the voltage drop. More current means more
voltage drop and this cycle will lead to a non-convergence situation. The analysis is basically telling us
that the system, as it has been designed, cannot supply 1.2 kVA to the load due to excessive losses. At
this point one can switch the definition of the load from constant load to constant impedance and
determine exactly how much power can be transferred to the load. This issue will be illustrated with an
example in further sections of this manual.

## 2.2 Constant Current Load (Amps)

The load (P+jQ) is treated as constant current load. The current is calculated by using the following
equation:

P − jQ
I=
V∗

## P = Load Active Power (kW)

Q = Load Reactive Power (kVAR)
I = Load equivalent constant current

## How does this work?

When a load of rated “P” (kW), “Q” (kVAR) and “V” (Voltage) is entered, the program calculates the
equivalent current “I” and defines the load as a constant draw of “I” (Amps).

Notes:

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Page LF.2
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 2.3 Constant Impedance Load (Ohms)

The load (P+jQ) is treated as constant impedance load. The impedance is calculated by using the
following equation:

V2
Z=
P − jQ
P = Load Active Power (kW)
Q = Load Reactive Power (kVAR)
Z = Load equivalent constant Impedance

## How does this work?

When a load of a rated “P” (kW), “Q” (kVAR) and “V” (Voltage) is entered, the program calculates the
equivalent impedance “Z” and defines the load as a constant shunt impedance of “Z” (Ohms).

A functional load is a load that is composed of any combination of constant load, constant current,
and/or constant impedance. For example, in a single phase system, the total load at 120 Volts may be
(12 kW+j0 kVAR) broken down as follows:

## 30% as constant power load: 3.6 kW – 3.6 kW

60% as constant current: 7.2 kW – 60.0 Amps
10% as constant impedance: 1.2 kW – 12.0 ohms

Notes:

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Page LF.3
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 3.0 Generator Models

The Load Flow study algorithm, specifies each bus based on; Active/Reactive power consumption (Load
or PQ Bus), Voltage magnitude (Generation or PV Bus), and Voltage reference (Swing Bus). Supply
busses that contain synchronous generators may also be specified as PQ busses depending on
application, or re-designation from PV busses if the prescribed limits of reactive power generation are
reached during the Load Flow Analysis.

The Swing bus is the only bus at which the power is not specified. Net power flows cannot be fixed in
advance at every generating bus, since the network power losses are not known until the study has
been completed. The Swing bus is therefore defined based solely on voltage and angle, leaving the
rest of the variables (kW & kVAR, including system losses) free to adjust (SWING) to the requirements
of the network. In other words, Active and Reactive Power are the unknown variables of the Swing
bus.

In light of the above, a Load Flow Analysis is not mathematically feasible (by computer, by hand, or
otherwise) without the presence of a Swing bus or busses in the network. The Swing bus designation is
bestowed upon the stiffest busses in the network, traditionally Power Company or Utility busses.

The table below summarizes the critical variables for each type of bus:

## Bus Type Known Variables Unknown Variables

V = 1.0 PU
Swing P&Q
δ = 0 deg
PQ Generator P&Q V&δ
PV Generator P&V Q&δ

Notes:

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Page LF.4
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.0 Conducting a Balanced Load Flow Analysis (File: EDM7.axd)

Step 1.
Proceed to open
the file EDM7.axd”

Step 2.
Error Check”, and correct any
problems as required.

Notes:

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Page LF.5
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## Switch Scenario Name

Position Table 1. Co-Gen. 2. Normal 3. Emergency
BKR-1 Closed Closed Open
BKR-2 Closed Open Closed

Notes:

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Page LF.6
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Generator Model

Generator Full
Rating in kVA.

Generator Type.

Flow set-points.

Notes:

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Page LF.7
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Utility Model

Calculated SC
Short Circuit Levels. Impedance values.

## When X” is selected, the positive The positive sequence

sequence SC impedance, is included impedance is passed onto
in the Load Flow model for the
Swing bus. This allows the program
to calculate the voltage drop at the
“non-ideal” Swing-Bus.

Notes:

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Page LF.8
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 1.
program by selecting either
of these commands.

Step 2.
Select the scenario to be
analyzed.

Step 3.
Select the calculation
method.

Step 4.
Verify the “Scenario” to
be studied (Normal).

Step 5.
Select the rest of the
options.
Refer to steps
6a & 6b in the
next page.

Step 6.
Select “OK”.

Notes:

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Page LF.9
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 6a.
Fine-tune the
needed.

Step 7.
Here the program is letting the user know that there is a
dead island caused by the “Normal” scenario configuration.
This scenario calls for BKR-2 to be opened, which isolates
the generator from the system. Select “Yes” to initiate the Step 6b.
analysis. Select “OK”.

Notes:

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Page LF.10
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.2 Viewing the Load Flow Analysis Results

Step 1.
Verify that the analysis
has converged.

Step 2.
To view the results, select the
desired output format from the

Step 3.
Select the desired
report sections and
options to be displayed.

Step 4.
Select “OK”.

Notes:

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Page LF.11
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## Partial view of the output

results for scenario 2
“Normal Power”.

## Using the same procedure explained in this section, conduct load

flow analyses for the cases 1 & 3 (Co-Gen, and Emergency).
Exercise
Compare the results of the 3 scenarios.
Do the results make sense? Why?

Notes:

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Page LF.12
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.3 Convergence & Constant kVA Loads (File EDM8.axd)

Step 1.
Open the file named
“EDM8.axd”.

Step 2.

Notes:

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Page LF.13
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 3.
and verify that in this case
it does NOT converge.

Step 4.
View the report. The results, which in cases of non-
convergence ARE NOT TO BE RELIED UPON, seem to indicate
that the losses are too great. The system is not able to supply

Notes:

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Page LF.14
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.4 Convergence & Constant Impedance Loads (File EDM8.axd)

Step 1.
Open the file named
“EDM8.axd”.

Step 2. Step 3.
“Constant Impedance” verify that in this case it DOES

Notes:

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Page LF.15
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 4.
View the report. The results confirm that due to the high
losses in the transformer and the line, the system is only able
to supply 484.5 kVA to the load.

## kVA = 4122 + 2552 = 484.5 kVA

Notes:

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Page LF.16
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.5 Voltage Control Techniques (File EDM7.axd)

The EDSA Object Oriented Load Flow analysis program can assist in correcting voltage levels by means
of the any of the following techniques:

## - Transformer tap settings.

- Static reactive power adjustment (Capacitors & Inductors).
- PV Generator reactive power adjustment (Exciter Control).
- A combination of any the above techniques.

## The first step is to prepare the network as follows:

- Select the transformer(s) with adjustable taps that will be used as voltage control transformers.
- Select the bus or busses at which static reactive compensation is to be considered.
- Select the voltage control generators by defining them as PV units. PQ generators cannot regulate
voltage.

Step 1.
Open the file named
“EDM7.axd”.

Notes:

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Page LF.17
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 2.
Define the settings for all
the potential voltage control
means desired.

Notes:

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Page LF.18
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 3.
Following the guidelines explained in
previous sections of this manual, run
a Load Flow Analysis using scenario
No.1 (Co-Generation).

Step 4.
Produce a report that includes the
“Bus Voltage” results and a voltage
violation summary for all busses
outside a ±10% voltage tolerance.
The screen-capture shown here is a
partial view of the report showing
the voltage violation report

Notes:

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Page LF.19
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.5.1 Voltage Control / Transformer Taps

Step 1. Step 2.
Select “Voltage Control”. Complete the “Voltage
Control Limits” section as
indicated here.

Step 3.
Select “Transformer Tap
control. Press “OK”.

Step 4.
Select “OK”.

Notes:

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Page LF.20
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 5.
Review the results and select
“Done” to exit.

Step 6.
Select “No’ for now. This
option will be explained later.

Notes:

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Page LF.21
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.5.2 Voltage Control / Capacitors-Inductors

Step 1. Step 2.
Select “Voltage Control”. Complete the “Voltage
Control Limits” section as
indicated here.

Step 3.
Select “Capacitor/Inductor...”
as a means of control. Press
“OK”

Step 4.
Select “OK”.

Notes:

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Page LF.22
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## Required amount of reactive compensation, in per unit of base

kVA. To obtain actual kVA, multiply by the base kVA (10,000 kVA).

Step 5.
Review the results and select
“Done” to exit.

Step 6.
Select “No’ for now. This
option will be explained later.

Notes:

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Page LF.23
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.5.3 Voltage Control / Transformer Taps & Generator Settings

Step 1. Step 2.
Select “Voltage Control”. Complete the “Voltage
Control Limits” section as
indicated here.

Step 3.
Select “Transformer…” and “Generator…”
as combined means of control. Press “OK”

Step 4.
Select “OK”.

Notes:

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Page LF.24
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## Required amount of additional generator reactive compensation, in per unit

of base kVA. To obtain actual kVA, multiply by the base kVA (10,000 kVA).

Step 5.
Review the results and select
“Done” to exit.

Step 6.
Select “Yes’ to test the results.
Step 7.
Select OK to acknowledge.

Notes:

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Page LF.25
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 8.
Select “Yes” and verify
convergence.

Step 9.
The solution proves to be
effective as indicated here.

Notes:

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Page LF.26
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 10.
Select “Exit”.

Step 11.
Select “Yes”.

Step 12.
Save the file under a different
name, if you wish to avoid over-
writing the original one. Press
“Save”.

## Conduct a voltage control analysis for case 1 (Co-Generation),

using ONLY Generator Reactive Power control as means of
Exercise
correcting the voltage drops in the network. Use ±7% as the
acceptable tolerance. Is the calculation successful? Why?

Notes:

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Page LF.27
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.6 Load Flow Transformer Sizing (File EDM7.axd)

Step 1.
on the subject file.

Step 2. Step 3.
Select “Xfr Sizing”. Enter the “Design Margin” in
%, and select “OK”.

Notes:

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Page LF.28
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 4.7 Back Annotation of Load Flow Results (File EDM7.axd)

Step 2.
Select “ON”.
Step 1.
“Back Annotation” tool.

Step 3.
Select the desired components
from the “AC Load Flow” section.

Step 4.
Select “OK”.

Notes:

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Page LF.29
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

annotation.

Notes:

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Page LF.30
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 5.0 Unbalanced Load Flow Analysis (File EDM9.axd)

Step 1.
Proceed to open the
file “EDM9.axd”

Note:
be entered as unbalanced

Step 2.
Error Check”, and correct any
problems as required.

Notes:

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Page LF.31
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 5.1 Preparing the Master File Editor

Step 2.
Select the
Step 1. “Visibility” tab.
“Master File Editor”.

## The steps described in this section, will

enable the “Unbalanced Load Flow” tab at
every load in the single line diagram. The
user can enter, as required, the percentile
distribution of the load across the phases.
These % figures are based on the full load
condition entered in the “Load Flow” tab.
The initial default assumed by the program is
a balanced state as indicated here.

Step 3.
Check the “View Unbalanced
Step 4.
Select “OK”.

Notes:

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Page LF.32
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 5.2 Preparing the Unbalanced Loads

Step 1.
Double click on each of the static
loads fed from bus J#1066, and edit
as indicated in steps 2 & 3.

Step 2.
Flow” tab.

Step 3.
Enter a per-phase distribution
as indicated here. Assume the
same percentile values for all

Notes:

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Page LF.33
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 5.3 The Unbalanced Load Flow Analysis Interface

Step 2.
Select “Run”.

Step 1.
Select “AC 3-Phase
Unbalanced”.

Step 3.
Select “Continue”.
Step 4.
Select the desired options
and press “OK”.

Step 5.
Allow the program to adjust the
tolerance by selecting “Yes”.

Notes:

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Page LF.34
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

Step 6.
Verify that the calculation
has converged and select
“View Results”.

## Partial view of the

final report. To
exit select “Done”

Notes:

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Page LF.35
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 6.0 Load Flow Analysis Voltage / Profile Method (File EDM10.axd)

Step 1.
Proceed to open the
file “EDM10.axd”

Note:

Step 2.
Error Check”, and correct any
problems as required.

Notes:

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Page LF.36
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 6.1 Preparing the Master File Editor

Step 1.
“Master File Editor”.

Step 2.
Select the “Visibility” tab.

Step 3.
Check the “View Voltage Profile
Fields” option.

Step 4.
Select the “Time Periods” tab.

Step 5.
time periods. Select “OK”.

Notes:

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Page LF.37
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 6.2 Preparing the Cycling Loads

Step 1.
Double click on each of the loads fed from
bus J#1066, and edit the cycling

Notes:

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Page LF.38
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 6.3 The Voltage Profile Load Flow Interface

Step 2.
Select “Run”.

Step 1.
Select “AC
Step 3. Voltage Profile”.
Options”, and select
“OK”.

Step 4.
Verify convergence for all
periods, and select “Done”.

Step 5.
To view the results, select
“Results”.

Notes:

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Page LF.39
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 6.4 Graphical View of the Results

Step 3.
Select “OK”
to return.

Step 1.
Select the bus to
view, by clicking
on it once.

Step 2.
View and edit the graphs.
When done press “Exit”.

Notes:

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Page LF.40
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 7.0 Single Phase Load Flow Analysis / Building the Job-File

Step 2.
Select Electrical One Line
Single-Phase.axd”, and press
“OK”.

Step 1.
new job-file.

Step 3.
Name the file, and
select “Open”. Step 4.
requirement, and press
“OK”.

Notes:

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Page LF.41
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## Single-Phase Element catalog.

This catalog contains both, single-
phase busses and branches.

## Master Job-File Editor settings.

Step 5.
Following the same guidelines outlined in the
“Main User Interface” section of this manual,
proceed to build the required single-phase
network.

Notes:

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Page LF.42
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## 7.1 Conducting a Single-Phase Load Flow Analysis (File: EDM6.axd)

Step 2.
connectivity error check.

Step 3.
Analysis program.

Step 1.
Proceed to open the
single-phase file named
“EDM6.axd”.

Step 3.
The AC Load Flow Analysis program is designed to analyze both
Exercise single and three-phase systems. To continue, simply repeat the
same steps explained in section 4.0 of this manual.

Notes:

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Page LF.43
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

## Power Factor Correction

Capacitor Bank.

Using the File “EDM7X.axd”, shown in the above picture, complete the following questionnaire:

## 4. Voltage Drop at 480 V Bus J#1066: _______________%

5. List the transformers loaded beyond 100% of their capacity: F:______ T:______

F:______ T:______

Notes:

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Page LF.44
©2002 EDSA Micro Corp. / PQ Logic Corp.
EDSA T2K Design Master

F:______ T:______

## 6. Assuming a design margin of 120%, resize the transformers listed in question 5.

Size 1:___________kVA

Size 2:___________kVA

Size 3:___________kVA

7. Design a Power Factor Correction Capacitor Bank (as shown in the figure) that will improve the
overall system power factor to a value of 92%.

## Capacitor Bank Size: ___________kVA

Once the required kVA has been calculated, enter the value into the network and re-run the Load
Flow Analysis to confirm the results.

8. Calculate suitable transformer Tap Settings that will maintain system voltages within a ±10%
tolerance at all busses. Assume the following:

All Transformers:

## Tap Location: Secondary

Total Steps: 4 steps

## The capacitor bank calculated in question 7. is on-line.

Notes:

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Page LF.45
©2002 EDSA Micro Corp. / PQ Logic Corp.