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Algorithmic State Machines (ASM)

Algorithm State Machines is used for designing finite state machines. It is used to
represent diagrams of digital integrated circuits. The ASM diagram is like a state
diagrambut less formal and thus easier to understand. An ASM chart is a method of
describing the sequential operations of a digital system.

Brief History
The Algorithmic State Machine (ASM) method for specifying digital designs in an
abstract behavioral form was originally documented by Claire in the early 1970’s, based
on work done at Hewlett Packard. Since then, it has become a staple of almost every
text on the subject of Digital Logic Design, being covered in some fashion in most
texts. Whereas most books simply give it treatment as a means to specify the control of
digital systems using complex finite state machine (FSM) models, some texts actually
use it as a primary means for presenting the abstract design methods for digital systems

Early texts by Fletcher and Wakerley in the 1980s codified the ASM method into the
pedagogy of digital systems analysis and design techniques. These texts demonstrated
how an algorithmic approach to controller design could be used to manage complexity
of digital control specifications involving large numbers of state variables or
inputs. These texts were preceded by Hayes’ late 1970s treatment of standardized
register-transfer notation (RTN) in computer architecture design, later incorporated into
Hayes’ text on digital logic design and into Wakerley’s later text editions in the
1990s. This incorporation of RTN into ASM notation allowed datapath operations to be
specified along with control signals as the result of finite state machine (FSM)

Many of the texts on Digital Logic cover the ASM method in conjunction with
other methods for specifying FSMs, namely state tables and state diagrams. Several
authors of newer texts on the subject, such as Lee and Arnold, recognize the value of
presenting the design of digital systems solely in terms of the ASM method,
incorporating both the FSM and the register transfer notation (RTN) models in a single
representation corresponding to the control and datapath structures of a digital system.

Armstrong et al. and Arnold have written texts that recognize the importance of
using the ASM method to model algorithms, and present the method as a manual
analysis technique to devise digital systems for algorithm implementation. In particular,
Arnold appears to have written to an audience consisting primarily of high-level software
language developers, such as C programmers, as he uses the ASM as a means to
introduce digital systems development using the Verilog HDL language. Armstrong et
al., on the other hand, are writing to an audience that will engage in digital systems
design using the VHDL language.

The ASM method is composed of the following steps:

1.) Create an algorithm, using pseudocode, to describe the desired operation of the device.
2.) Convert the pseudocode into an ASM chart.

3.) Design the datapath based on the ASM chart.

4.) Create a detailed ASM chart based on the datapath.

5.) Design the control logic based on the detailed ASM chart.

ASM Chart

A key point to remember about ASM charts is that given a state, they do not
enumerate all the possible inputs and outputs. Only the inputs that matter and the
outputs that are asserted are indicated. It must be known whether a signal
is positive or negative logic:

• Positive logic signals that are high are said to be asserted

• Negative logic signals that are low are said to be asserted

The drawing of ASM charts must follow certain necessary rules:

• The entrance paths to an ASM block lead to only one state box
• Of 'N' possible exit paths, for each possible valid input combination, only one exit
path can be followed, that is there is only one valid next state.
• No feedback internal to a state box is allowed. The following diagram indicates
valid and invalid cases.

Incorrect Correct

Symbols for creating ASM

An ASM chart has an entry point and is constructed with blocks. A block is constructed
with the following type of symbols.
One state box. The state box has a name and lists
outputs that are asserted when the system is in that
state. These outputs are called synchronous
or Moore type outputs.
Optional decision box(es). A decision box may be
conditioned on a signal or a test of some kind.

Optional conditional output box(es). Such an ouput

box indicates outputs that are conditionally asserted.
These outputs are called asynchrous
or Mealy outputs.

The idea is that flow passes from ASM block to ASM block, the decision boxes
decide the next state and conditional output. Consider the following example of an ASM
diagram block. When state S0 is entered, output Z5 is always asserted. Z1_n however
is asserted only if X2 is also high. Otherwise Z2 is asserted.

Parallel vs. Serial

We can bend the rules, several internal paths can be active, provided that they
lead to a single exit path. Regardless of parallel or serial form, all tests are performed
concurrently. Usually we have a preference for the serial form. The following two
examples are equivalent.

Serial Form

Parallel Form

Sequence Detector

Figure 1 : State diagram of a sequence detector

Figure 2 : ASM chart of a sequence detector

Figure 3 : Timing Diagram