®

Software Defined Radio Handbook
Eighth Edition
Sampling Principles of SDR Technology Products Applications Summary Links
by

Rodger H. Hosking
Vice-President & Cofounder of Pentek, Inc.

Pentek, Inc.
One Park Way, Upper Saddle River, New Jersey 07458 Tel: (201) 818-5900 • Fax: (201) 818-5904 Email: info@pentek.com • http://www.pentek.com

Copyright © 1998, 2001, 2003, 2006, 2008, 2009, 2010 Pentek Inc. Last updated: June 2010 All rights reserved. Contents of this publication may not be reproduced in any form without written permission. Specifications are subject to change without notice. Pentek, GateFlow, ReadyFow and VIM are registered trademarks of Pentek, Inc.

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Software Defined Radio Handbook

Preface

SDR (Software Defined Radio) has revolutionized electronic systems for a variety of applications including communications, data acquisition and signal processing. This handbook shows how DDCs (Digital Downconverters) and DUCs (Digital Upconverters), the fundamental building blocks of SDR, can replace conventional analog receiver designs, offering significant benefits in performance, density and cost. In order to fully appreciate the benefits of SDR, a conventional analog receiver system will be compared to its digital receiver counterpart, highlighting similarities and differences. The inner workings of the SDR will be explored with an in-depth description of the internal structure and the devices used. Finally, some actual board- and system-level implementations and available off-the-shelf SDR products for embedded systems will be described.

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Software Defined Radio Handbook

Sampling

Nyquist’s Theorem and Sampling
Before we look at SDR and its various implementations in embedded systems, we’ll review a theorem fundamental to sampled data systems such as those encountered in software defined radios.

A Simple Technique to Visualize Sampling

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Nyquist’s Theorem: “Any signal can be represented by discrete samples if the sampling frequency is at least twice the bandwidth of the signal.”
Notice that we highlighted the word bandwidth rather than frequency. In what follows, we’ll attempt to show the implications of this theorem and the correct interpretation of sampling frequency, also known as sampling rate.
Zone 1 Zone 2 Zone 3 Zone 4 Zone 5 Zone 6 Zone 7

Figure 1

To visualize what happens in sampling, imagine that you are using transparent “fan-fold” computer paper. Use the horizontal edge of the paper as the frequency axis and scale it so that the paper folds line up with integer multiples of one-half of the sampling frequency ƒs. Each sheet of paper now represent what we will call a “Nyquist Zone”, as shown in Figure 1.

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Software Defined Radio Handbook

Sampling

Sampling Basics

Baseband Sampling

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Use the vertical axis of the fan-fold paper for signal energy and plot the frequency spectrum of the signal to be sampled, as shown in Figure 2. To see the effects of sampling, collapse the transparent fan-fold paper into a stack.

A baseband signal has frequency components that start at ƒ = 0 and extend up to some maximum frequency. To prevent data destruction when sampling a baseband signal, make sure that all the signal energy falls ONY in the 1st Nyquist band, as shown in Figure 4. There are two ways to do this: 1. Insert a lowpass filter to eliminate all signals above ƒs /2, or 2. Increase the sampling frequency so all signals present fall below ƒs /2. Note that ƒs/2 is also known as the “folding frequency”.

Folded Signals Fall On Top of Each Other

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Sampling Bandpass Signals
Let’s consider bandpass signals like the IF frequency of a communications receiver that might have a 70 MHz center frequency and 10 MHz bandwidth. In this case, the IF signal contains signal energery from 65 to 75 MHz. If we follow the baseband sampling rules above, we must sample this signal at twice the highest signal frequency, meaning a sample rate of at least 150 MHz. However, by taking advantage of a technique called “undersampling”, we can use a much lower sampling rate.

Figure 3

The resulting spectrum can be seen by holding the transparent stack up to a light and looking through it. You can see that signals on all of the sheets or zones are “folded” or “aliased” on top of each other — and they can no longer be separated. Once this folding or aliasing occurs during sampling, the resulting sampled data is corrupted and can never be recovered. The term “aliasing” is appropriate because after sampling, a signal from one of the higher zones now appears to be at a different frequency.

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Software Defined Radio Handbook

Sampling

Undersampling
Folded signals still fall on top of each other - but now there is energy in only one sheet !

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Figure 6

Undersampling allows us to use aliasing to our advantage, providing we follow the strict rules of the Nyquist Theorem. In our previous IF signal example, suppose we try a sampling rate of 40 MHz. Figure 5 shows a fan-fold paper plot with Fs = 40 MHz. You can see that zone 4 extends from 60 MHz to 80 MHz, nicely containing the entire IF signal band of 65 to 75 MHz. Now when you collapse the fan fold sheets as shown in Figure 6, you can see that the IF signal is preserved after sampling because we have no signal energy in any other zone. Also note that the odd zones fold with the lower frequency at the left (normal spectrum) and the even zones fold with the lower frequency at the right (reversed spectrum). In this case, the signals from zone 4 are frequency reversed. This is usually very easy to accommodate in the following stages of SDR systems.

The major rule to follow for successful undersampling is to make sure all of the energy falls entirely in one Nyquist zone. There two ways to do this: 1. Insert a bandpass filter to eliminate all signals outside the one Nyquist zone. 2. Increase the sampling frequency so all signals fall entirely within one Nyquist zone.

Summary
Baseband sampling requires the sample frequency to be at least twice the signal bandwidth. This is the same as saying that all of the signals fall within the first Nyquist zone. In real life, a good rule of thumb is to use the 80% relationship: Bandwidth = 0.8 x ƒs/2 Undersampling allows a lower sample rate even though signal frequencies are high, PROVIDED all of the signal energy falls within one Nyquist zone. To repeat the Nyquist theorem: The sampling frequency must be at least twice the signal bandwidth — not the signal frequency.

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7 MHz for commercial AM and FM broadcasts. For example.7 = 90 MHz This is called “downconversion” or “translation” because a signal at a high frequency is shifted down to a lower frequency by the mixer. The frequency of the local oscillator is set so that the difference between the local oscillator frequency and the desired input signal (the radio station you want to receive) equals the IF. This amplified RF signal is then fed into a mixer stage. The IF stage acts as a narrowband filter which only passes a “slice” of the translated RF input.com . AM uses an envelope detector and FM uses a frequency discriminator. The mixer performs an analog multiplication of the two inputs and generates a difference frequency signal. you would tune the local oscillator to: 100. For commercial FM. 6 Pentek. if you wanted to receive an FM station at 100. The demodulator recovers the original modulating signal from the IF output using one of several different schemes. the bandwidth is about 100 kHz and for AM it is about 5 kHz. • One Park Way. typically with a tuned RF stage that amplifies a region of the frequency band of interest.7 MHz. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.10. Upper Saddle River.com • http://www. Inc. has been in use for nearly a century.7 MHz and the IF is 10. respectively. the demodulated output is fed to an audio power amplifier which drives a speaker. The IF stage is a bandpass amplifier that only lets one signal or radio station through.7 . The mixer translates the desired input signal to the IF (Intermediate Frequency) as shown in Figure 8. Common center frequencies for IF stages are 455 kHz and 10. For example.Software Defined Radio Handbook Principles of SDR Analog Radio Receiver Block Diagram SPEAKER ANTENNA ANALOG MIXER RF AMP IF AMP (FILTER) DEMODULATOR (Detector) AUDIO AMP Analog Radio Receiver Mixer RF INPUT SIGNAL FROM ANTENNA MIXER TRANSLATES INPUT SIGNAL BAND to IF FREQUENCY Signal ANALOG LOCAL OSCILLATOR ANALOG LOCAL OSCILLATOR 0 Figure 7 FIF Figure 8 FRF The conventional heterodyne radio receiver shown in Figure 7. The bandwidth of the IF stage is equal to the bandwidth of the signal (or the “radio station”) that you are trying to receive. In a typical home radio.pentek. The other input to the mixer comes from the local oscillator whose frequency is determined by the tuning control of the radio. Let’s review the structure of the analog receiver so comparison to a digital receiver becomes apparent. First the RF signal from the antenna is amplified. This is consistent with channel spacings of 200 kHz and 10 kHz.

any portion of the RF input signal can be mixed down to DC. the complex representation of the signal allows us to go right down to DC. decoding and other processing tasks. SDR Receiver Mixer CHANNEL BANDWIDTH Signal MIXER TRANSLATES INPUT SIGNAL BAND to DC IF BW DIGITAL LOCAL OSCILLATOR FLO = FSIG 0 Figure 10 FSIG At the output of the mixer. The digital baseband samples are then fed to a block labeled DSP which performs tasks such as demodulation. Note that upper and lower sidebands are preserved. By tuning the local oscillator over its range. This is similar to the analog receiver mixer except there. 7 Pentek. The digital downconverter includes a lot of hardware multipliers. Traditionally. and it is a key part of the SDR system. Inc. Here. the wideband RF signal spectrum can be “slid” around 0 Hz.com • http://www. left and right. adders and shift register memories to get the job done. The RF tuner converts analog RF signals to analog IF frequencies. These samples are fed to the next stage which is the digital downconverter (DDC) shown within the dotted lines. simply by tuning the local oscillator. the same as the first three stages of the analog receiver. The digital downconverter is typically a single monolithic chip or FPGA IP. • One Park Way.com . the high frequency wideband signals from the A/D input (shown in Figure 10 above) have been translated down to DC as complex I and Q components with a frequency shift equal to the local oscillator frequency. the mixing was done down to an IF frequency. and programmable DSPs. The A/D converter that follows digitizes the IF signal thereby converting it into digital samples.pentek. Upper Saddle River.Software Defined Radio Handbook Principles of SDR SDR Receiver Block Diagram DDC Digital Downconverter Analog RF Signal RF TUNER Analog IF Signal A/D CONV Digital IF Samples DIGITAL MIXER LOWPASS FILTER Digital Baseband Samples DSP DIGITAL LOCAL OSC Figure 9 Figure 9 shows a block diagram of a software defined radio receiver. In effect. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. A conventional DDC has three major sections: • A digital mixer • A digital local oscillator • An FIR lowpass filter The digital mixer and local oscillator translate the digital IF samples down to baseband. these needs have been handled with dedicated application specific ICs (ASICs). The FIR lowpass filter limits the signal bandwidth and acts as a decimating lowpass filter.

There is no aging. If we are keeping only one out of every N samples. or stored in less memory. Since the output of the FIR filter is band limited. the Nyquist theorem allows us to lower the sample rate. can be transmitted at a lower rate.pentek. the DDC performs two signal processing operations: 1. If the decimated output sample rate is kept higher than twice the output bandwidth. Decimated Filter Output Sample Rate: Fs/N Figure 11B FIR Filter Decimation Because the local oscillator uses a digital phase accumulator. The frequency accuracy and stability are determined entirely by the A/D clock so it’s inherently synchronous to the sampling frequency. no information is lost.Software Defined Radio Handbook Principles of SDR DDC Local Oscillator and Decimation DDC Signal Processing Translation Digital IF Samples Filtering Digital Baseband Samples 90O A/D CONV DIGITAL MIXER LOWPASS FILTER DIGITAL LOCAL OSC Tuning Freq Decimation F1 F2 F3 Figure 12 Figure 11A Local Oscillator Frequency Switching A/D Sample Rate (before decimation) Sample Rate: Fs This process is called decimation and it means keeping one out of every N signal samples. It switches between frequencies with phase continuity. 8 Pentek. We will next turn our attention to the Software Defined Radio Transmitter. Lowpass filtering with the bandwidth controlled by the decimation setting.com • http://www. drift or calibration since it’s implemented entirely with digital logic. it has some very nice features. so you can generate FSK signals or sweeps very precisely with no transients as shown in Figure 11A. Frequency translation with the tuning controlled by the local oscillator. decimation can dramatically reduce system costs! As shown in Figure 12. Upper Saddle River. 2. as shown in Figure 11B above. As a result. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. • One Park Way.com . Inc. The clear benefit is that decimated signals can be processed easier. we have dropped the sampling rate by a factor of N.

Software Defined Radio Handbook Principles of SDR SDR Transmitter Block Diagram Digital Baseband Samples DSP INTERPOLATION FILTER Digital Baseband Samples DIGITAL MIXER Digital IF Samples Fs D/A CONV Analog IF Signal RF Upconverter Analog RF Signal Power Amplifier Fs/N Fs DUC Digital Up Converter DIGITAL LOCAL OSC Figure 13 The input to the transmit side of an SDR system is a digital baseband signal. The local oscillator already operates at a sample rate of ƒs . The mixer generates one output sample for each of its two input samples. The D/A converter that follows converts the digital IF samples into the analog IF signal.com . DUC Signal Processing Digital Baseband Samples Fs/N INTERPOLATION FILTER Digital Baseband Samples DIGITAL MIXER Digital IF Samples Fs Fs DUC Digital Up Converter Figure 14 DIGITAL LOCAL OSC Inside the DUC shown in Figure 14. The digital hardware block in the dotted lines is a DUC (digital upconverter) that translates the baseband signal to the IF frequency. 9 Pentek. This problem is solved with the Interpolation Filter.pentek. Upper Saddle River. the RF upconverter converts the analog IF signal to RF frequencies. but the input baseband sample frequency at the left is usually much lower. Therefore. the sample frequency at the mixer output must be equal to the D/A sample frequency ƒs . Finally. And. the digital mixer and local oscillator at the right translate baseband samples up to the IF frequency. the local oscillator sample rate and the baseband sample rate must be equal to the D/A sample frequency ƒs . • One Park Way. the power amplifier boosts signal energy to the antenna. Next. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. typically generated by a DSP stage as shown in Figure 13 above. The IF translation frequency is determined by the local oscillator.com • http://www. Inc.

The interpolation filter increases the sample frequency of the baseband input signal by a factor N. known as the interpolation factor. 10 Pentek.pentek. This is exactly the opposite of the frequency domain view of the DDC in Figure 10. The signal processing operation performed by the interpolation filter is the inverse of the decimation filter we discussed previously in the DDC section. At the bottom of Figure 15. • One Park Way. The local oscillator setting is set equal to the required IF signal frequency. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Inc. Upper Saddle River.com • http://www. just as with the DDC. Figure 16 is a frequency domain view of the digital upconversion process.Software Defined Radio Handbook Principles of SDR Interpolation Filter: Time domain Fs/N I Q BASEBAND INPUT Interpolation Filter: Frequency Domain Fs INTERPOLATING LOW PASS FIR FILTER I Q INTERPOLATED OUTPUT Digital Baseband Samples Fs/N INTERPOLATION FILTER Digital Baseband Samples Fs DIGITAL MIXER Digital IF Samples Fs DUC Digital Up Converter INTERPOLATION FACTOR = N INTERPOLATED BASEBAND INPUT DIGITAL LOCAL OSC TRANSLATED OUTPUT MIXER Baseband Input Sample Rate: Fs/N LOCAL OSCILLATOR F = IF Freq Interpolating Filter Output Sample Rate: Fs 0 IF Freq Figure 15 Figure 16 The interpolation filter must boost the baseband input sample frequency of ƒs /N up to the required mixer input and D/A output sample frequency of ƒs .com . Notice the baseband signal frequency content is completely preserved by filling in additional samples in the spaces between the original input samples. the effect of the interpolation filter is shown in the time domain.

8 x ƒb Output sample frequency ƒs = ƒb x N Baseband sample frequency ƒb = ƒs /N Baseband bandwidth = 0. The “bandwidth” knob represents the programmability of the decimation factor to select the desired baseband signal bandwidth. Frequency translation from baseband up to IF is performed by the local oscillator and mixer.pentek.com .com • http://www. Inc. The “bandwidth” knob represents the programmability of the interpolation factor to select the desired input baseband signal bandwidth. The “tuning” knob represents the programmability of the local oscillator frequency to select the desired signal for downconversion to baseband. • One Park Way. ● ● Baseband bandwidth = 0. and complex (I+Q) samples. The “tuning” knob represents the programmability of the local oscillator frequency to select the desired IF frequency for translation up from baseband. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Upper Saddle River. Frequency translation from IF down to baseband is performed by the local oscillator and mixer.8 x ƒb Again. 11 Pentek.Software Defined Radio Handbook Principles of SDR DDC Processing Translation A/D CONV DIGITAL MIXER DUC Processing Filtering LOWPASS FILTER Filtering INTERPOLATE FILTER Translation DIGITAL MIXER D/A CONV DSP DSP Fs DIGITAL LOCAL OSC Fb ¸ N Deci mation Fb ´ N DIGITAL LOCAL OSC Fs Freq uency Inter polation Freq uency Tuning Bandwidth Bandwidth Figure 18 Tuning Figure 17 Figure 17 shows the two-step processing performed by the digital downconverter. The baseband signal bandwidth is set by setting decimation factor N and the lowpass FIR filter: ● ● Figure 18 shows the two-step processing performed by the digital upconverter: The ratio between the required output sample rate and the sample rate input baseband sample rate determines the interpolation factor N. The baseband bandwidth equation reflects a typical 80% passband characteristic. the bandwidth equation assumes a complex (I+Q) baseband input and an 80% filter.

and reduces traffic and bandwidth across communication channels. At the lower right are tasks like analysis and decision making which are highly variable and often subjective. 12 Pentek. with compute Processing Intensity on the vertical axis and Flexibility on the horizontal axis. are dedicated functions like A/D converters and DDCs that require specialized hardware structures to complete the operations in real time. you can dramatically reduce the cost and complexity of the programmable DSPs or GPPs in your system. As a result. Upper Saddle River. Programmable general-purpose processors or DSPs are usually chosen for these tasks since these tasks can be easily changed by software. Not only do DDCs and DUCs reduce the processor workload. The same applies to the DUC. by reducing the sampling frequency.com . performs digital frequency translation. Inc. It preselects only the signals you are interested in and removes all others. • One Park Way. Here we’ve ranked some of the popular signal processing tasks associated with SDR systems on a two axis graph.Software Defined Radio Handbook Principles of SDR Key DDC and DUC Benefits Digital Baseband Samples Fs/N DIGITAL LOCAL OSC SDR Tasks A/D CONV Digital IF Samples Fs DIGITAL MIXER LOWPASS FILTER DUC Digital Down Converter Digital Baseband Samples Fs/N INTERPOLATION FILTER Digital Baseband Samples DIGITAL MIXER Digital IF Samples Fs D/A CONV Fs DUC Digital Up Converter DIGITAL LOCAL OSC Figure 19 Figure 20 Think of the DDC as a hardware preprocessor for programmable DSP or GPP processor. the reduction of bandwidth and sampling rate helps save time in data transfers to another subsystem. Now let’s temporarily step away from the software radio tasks and take a deeper look at programmable logic devices.com • http://www. At the upper left. The processor only needs to generate and deliver the baseband signals sampled at the baseband sample rate. This provides an optimum bandwidth and minimum sampling rate into the processor. This helps minimize recording time and disk space.pentek. and delivers samples to the D/A at a very high sample rate. The number of processors required in a system is directly proportional to the sampling frequency of input and output data. The DUC then boosts the sampling rate in the interpolation filter. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Flexibility pertains to the uniqueness or variability of the processing and how likely the function may have to be changed or customized for any specific application. What we mean by process intensity is the degree of highly-repetitive and rather primitive operations. ASICs are usually chosen for these functions.

counters.com • http://www.com . programmable logic vendors started offering predefined logic blocks for flip-flops. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. You had tools for accepting boolean equations or even schematics to help generate the interconnect pattern for the growing number of gates. loading. gates. they were used extensively by hardware engineers to replace control logic. clocking and synchronizing—all tricky problems that usually had to be solved the hard way—with oscilloscopes or logic analyzers. • One Park Way. These programmable logic devices were mostly the domain of hardware engineers and the software tools were tailored to meet their needs.pentek. registers and counters that gave the engineer a leg up on popular hardware functions. Then. 13 Pentek. multipliers § Successful designs required high-level hardware engineering skills for: Ÿ Ÿ Ÿ Ÿ Ÿ Critical paths and propagation delays Pin assignment and pin locking Signal loading and drive capabilities Clock distribution Input signal synchronization and skew analysis § Devices were selected by hardware engineers § Programmed functions were seldom changed after the design went into production Figure 21 Figure 22 As true programmable gate functions became available in the 1970’s. registers. Nevertheless. He had to worry about propagation delays.Software Defined Radio Handbook Technology Early Roles for FPGAs Legacy FPGA Design Methodologies § Used primarily to replace discrete digital hardware circuitry for: Ÿ Control logic Ÿ Glue logic Ÿ Registers and gates Ÿ State machines Ÿ Counters and dividers § Tools were oriented to hardware engineers Ÿ Schematic processors Ÿ Boolean processors Ÿ Gates. registers. Upper Saddle River. and state machines which otherwise would have required many discrete. dedicated ICs. Often these programmable logic devices were onetime factory-programmed parts that were soldered down and never changed after the design went into production. Inc. the hardware engineer was still intimately involved with testing and evaluating the design using the same skills he needed for testing discrete logic designs.

14 Pentek. BGA and flip-chip packages provide plenty of I/O pins to support on-board gigabit serial transceivers and other user-configurable system interfaces. computation clocks to 500 MHz and above. Logic slices with the equivalent of over ten million gates result from silicon geometries shrinking down to 0.000 Logic Cells Gigabit Ethernet media access controllers On-chip 405 PowerPC RISC micro-controller cores Memory densities approaching 15 million bits Reduced power with core voltages at 1 volt Silicon geometries to 65 nanometers High-density BGA and flip-chip packaging Over 1200 user I/O pins Configurable logic and I/O interface standards Figure 23 FPGAs: New Development Tools § High Level Design Tools Ÿ Block Diagram System Generators Ÿ Schematic Processors Ÿ High-level language compilers for VHDL & Verilog Ÿ Advanced simulation tools for modeling speed. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. these new tools accept entire block diagrams as well as VHDL and Verilog definitions. • One Park Way. New announcements seem to be coming out every day from chip vendors like Xilinx and Altera in a neverending game of outperforming the competition. propagation delays. In the last few years. About five years ago. since new advancements are being made every day. Excellent simulation and modeling tools help to quickly analyze worst case propagation delays and suggest alternate routing strategies to minimize them within the part. These are ready to drop into the FPGA design process to help beat the time-to-market crunch and to minimize risk. skew and board layout Ÿ Faster compilers and simulators save time Ÿ Graphically-oriented debugging tools § IP (Intellectual Property) Cores Ÿ FPGA vendors offer both free and licensed cores Ÿ FPGA vendors promote third party core vendors Ÿ Wide range of IP cores available Figure 24 It’s virtually impossible to keep up to date on FPGA technology.Software Defined Radio Handbook Technology FPGAs: New Device Technology § § § § § § § § § § § § § § 500+ MHz DSP Slices and Memory Structures Over 1000 dedicated on-chip hardware multipliers On-board GHz Serial Transceivers Partial Reconfigurability Maintains Operation During Changes Switched Fabric Interface Engines Over 330. Choosing the best FPGA vendor often hinges heavily on the quality of the design tools available to support the parts. and lower core voltages to keep power and heat down.pentek. Inc.com • http://www. High memory densities coupled with very flexible memory structures meet a wide range of data flow strategies.com . To support such powerful devices. This minimizes some of the tricky timing work for hardware engineers and can save one hours of tedious troubleshooting during design verification and production testing. a new industry of third party IP (Intellectual Property) core vendors now offer thousands of application-specific algorithms.1 micron. new design tools are appearing that now open up FPGAs to both hardware and software engineers. Instead of just accepting logic equations and schematics. The hottest features are processor cores inside the chip. Upper Saddle River. dedicated hardware multipliers started appearing and now you’ll find literally hundreds of them on-chip as part of the DSP initiative launched by virtually all FPGA vendors.

Upper Saddle River.Software Defined Radio Handbook Technology FPGAs for SDR FPGAs Bridge the SDR Application Space § Parallel Processing § Hardware Multipliers for DSP Ÿ FPGAs can now have over 500 hardware multipliers § Flexible Memory Structures Ÿ Dual port RAM. As we said. so that the whole signal processing task operates in parallel in a systolic pipelined fashion. FIFOs. These advantages may come at the expense of increased power dissipation and increased product costs. this is dramatically different from sequential execution and data fetches from external memory as in a programmable DSP. However. 15 Pentek. Inc. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. These memories can be distributed along the signal path or interspersed with the multipliers and math blocks. Again. and you can now get over 1000 of them on a single FPGA. these considerations are often secondary to the performance and capabilities of these remarkable devices. FIFOs. As a result. This includes the hardware multipliers. This is in sharp contrast to programmable DSPs. They offer the advantages of parallel hardware to handle some of the high process-intensity functions like DDCs and the benefit of programmability to accommodate some of the decoding and analysis functions of DSPs. § Parallel and Pipelined Data Flow Ÿ Systolic simultaneous data movement § Flexible I/O Ÿ Supports a variety of devices. FPGAs now have specialized serial and parallel interfaces to match requirements for high-speed peripherals and buses. • One Park Way. all the logic elements in FPGAs can execute in parallel. etc. buses and interface standards § High Speed § Available IP cores optimized for special functions Figure 25 Figure 26 Like ASICs. shift registers.com . which normally have just a handful of multipliers that must be operated sequentially. FPGAs have significantly invaded the application task space as shown by the center bubble in the task diagram above. look up tables. FPGA memory can now be configured with the design tool to implement just the right structure for tasks that include dual port RAM. shift registers and other popular memory types.pentek.com • http://www.

I/Q. of Filter Taps No. 24-Bit 16-Bit.32.Software Defined Radio Handbook Technology Typical Pentek Products with Installed SDR IP Cores Model Model Feature Feature Input Channels Input Channels Max Sample Rate Max Sample Rate Input Resolution Input Resolution DDC Channels DDC Channels Decimation Range Decimation Range No. Inverse 16-Bit. I/Q. Offset.8. Other information that’s specific to each core is included as well as an indication of the Models that include an interpolation filter and output D/A. 24-Bit 32-bits --0 to Fs 32-bits 0 to Fs 32-bits ± 180 deg 32-bits ± 180 deg 32 bits 32 bits None None 7152 7152 4 4 200 MHz 200 MHz 16-Bit 16-Bit 32 32 16 to 8192 16 to 8192 Steps of 8 Steps of 8 28*DEC/8 28*DEC/8 32 32 32 32 32 channels 32 channels I/Q. of Filter Taps Power Meters Power Meters Thresh Detectors Thresh Detectors Channel Summers Channel Summers Output Format Output Format Output Resolution Output Resolution Tuning Frequency Tuning Frequency Phase Offset Phase Offset Gain Control Gain Control DAC Interpolation DAC Interpolation 7141-430 7141-430 1 1 125 MHz 125 MHz 14-Bit 14-Bit 256 256 1K-10K 1K-10K 24*DEC/512 24*DEC/512 None None None None None None Normal I/Q Normal I/Q 16-Bit 16-Bit 32-bits --0 to Fs 32-bits 0 to Fs -32 bits 32 bits None None 7141-420 7141-420 2 2 125 MHz 125 MHz 14-Bit 14-Bit 2 or 4 2 or 4 Core: 2. Offset.4. Inverse Offset.64 Core: 2. Offset. PCIe and VPX formats as well. Offset. Real Inverse. Real 16-Bit. Inverse. 16 Pentek. Inverse 16-Bit. I/Q. Inverse 16-Bit. All the Models shown here are PMC or PMC/XMC modules. Inverse Offset. 24-Bit 16-Bit. 24-Bit 32-bits --0 to Fs 32-bits 0 to Fs 32-bits ± 180 deg 32-bits ± 180 deg 32 bits 32 bits None None 7153 7153 4 4 200 MHz 200 MHz 16-Bit 16-Bit 2 or 4 2 or 4 2 Ch: 2 to 65536 2 Ch: 2 to 65536 4 Ch: 2 to 256 4 Ch: 2 to 256 28*DEC 28*DEC 2 or 4 2 or 4 2 or 4 2 or 4 2 or 4 channels 2 or 4 channels I/Q. Offset. 24-Bit 16-Bit. Inc.8.com • http://www. and gain along with phase offset control for optimizing results in applications such as direction-finding and beamforming. 24-Bit 32-bits --0 to Fs 32-bits 0 to Fs 32-bits ± 180 deg 32-bits ± 180 deg 32 bits 32 bits 2 --32768 2 32768 7142-428 7142-428 4 4 125 MHz 125 MHz 14-Bit 14-Bit 4 4 2 to 64K 2 to 64K Steps of 1 Steps of 1 28*DEC 28*DEC None None None None None None I/Q. I/Q. threshold detectors.4. 24-Bit 16-Bit. Upper Saddle River. cPCI. These products are also available in PCI. Inverse Offset.16.pentek. As shown in the chart. 24-Bit 32-bits --0 to Fs 32-bits 0 to Fs 32-bits ± 180 deg 32-bits ± 180 deg 32 bits 32 bits 2 --32768 2 32768 7151 7151 4 4 200 MHz 200 MHz 16-Bit 16-Bit 256 256 128 to 1024 128 to 1024 Steps of 64 Steps of 64 24*DEC/64 24*DEC/64 None None None None None None I/Q. • One Park Way. maximum sampling frequency of their A/Ds. Offset. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.32. The chart provides information regarding the number of input channels. Inverse 16-Bit.com . some of these Models include power meters. 24-Bit 16-Bit.64 GC4016: 32to 16k GC4016: 32to 16k Core: 28*DEC Core: 28*DEC None None None None None None I/Q. 24-Bit 32-bits --0 to Fs 32-bits 0 to Fs 32-bits ± 180 deg 32-bits ± 180 deg 32 bits 32 bits None None Figure 27 The above chart shows the salient characteristics for some of Pentek’s SDR products with IP cores installed in their FPGAs.16. I/Q. This information is followed by DDC characteristics regarding the decimation range and available steps along with the output format and resolution. and number of DDC channels in each one. Inverse Offset.

The Virtex-6 devices offer higher density. faster clock speeds and enhanced logic slices. gigabit serial transceivers. SX 41K–152K 18K–68K 49K–93K 1. Inc.0 in x1 through x8 configurations.com • http://www.com . Upper Saddle River. PowerPC cores. Virtex-5 and Virtex-6 Slices actually require 6.Software Defined Radio Handbook Technology FPGA Resource Comparison Virtex-II Pro VP50. ● Virtex-II Pro: VP50 and VP70 ● Virtex-4: FX.904 18x18 Multipliers 132–328 – – – Virtex-4 FX. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The SXT devices push DSP capabilities with all of the same extras as the LXT.784 DSP48E 48–640 12–16 – 480–640 Virtex-6 LXT. LX. The ample DSP slices are responsible for the majority of the processing power of the Virtex-6 family. SXT 46K–156K 7K–24K 150K–207K 2.728–6. averagers. Virtex-6 tops out at an impressive 2016 DSP slices. LXT. The FXT devices follow as the embedded system resource devices. The FX family is a generous mix of all resources and is the only family to offer RocketIO. 17 Pentek. and the newly added gigabit Ethenet ports. • One Park Way.304 DSP48E 480–2. Virtex-6 supports PCI Express 2.504–38.pentek. Increases in operating speed from 500 MHz in V-4 to 550 MHz in V-5 to 600 MHz in V-6 and increasing density allows more DSP slices to be included in the same-size package. demodulators and FFTs—a major benefit for software radio signal processing. The Virtex-4 family is offered as three subfamilies that dramatically boost clock speeds and reduce power dissipation over previous generations.4 Logic Cells Figure 28 The above chart compares the available resources in the four Xilinx FPGA families that are used in most of the Pentek products. VP70 Logic Cells Slices* CLB Flip-Flops Block RAM (kb) DSP Hard IP DSP Slices Serial Gbit Transceivers PCI Express Blocks SelectIO 53K–74K 24K–33K 47K–66K 4. and updated interface features to match the latest technology I/O requirements including PCI Express.25 Logic Cells. As shown in the chart. They also improve the clocking features to handle faster memory and gigabit interfaces.016 20 2 600 *Virtex-II Pro and Virtex-4 Slices actually require 2.176–5. The Virtex-5 devices offer lower power dissipation. LX and SX ● Virtex-5: FXT. The Virtex-4 LX family delivers maximum logic and I/O pins while the SX family boasts of 512 DSP slices for maximum DSP performance. The Virtex-5 family LXT devices offer maximum logic resources. LXT and SXT ● Virtex-6: LXT and SXT The Virtex-II family includes hardware multipliers that support digital filters. SXT 128K–476K 20K–74K 160K–595K 9. They support faster single-ended and differential parallel I/O buses to handle faster peripheral devices.768 DSP48 64–512 0–20 – 448–768 Virtex-5 FXT.160–8. The Virtex-II Pro family dramatically increased the number of hardware multipliers and also added embedded PowerPC microcontrollers. and Ethernet media access controllers. lower power consumption. more processing power.

Pentek’s comprehensive software support includes the ReadyFlow® Board Support Package. • One Park Way. All of the software radio products include input A/D converters. and VMEbus Software Radio 3U VPX Board Half-length PCI Express Board PMC/XMC Module 6U CompactPCI Board PCI Board Full-length PCI Express Board VMEbus Board Figure 29 The Pentek family of board-level software radio products is the most comprehensive in the industry. All Pentek software radio products include multiboard synchronization that facilitates the design of multichannel systems with synchronous clocking. In addition. 18 Pentek. A complete listing of these products with active links to their datasheets on Pentek’s website is included at the end of this handbook. PMC/XMC. Most of these products are available in several formats to satisfy a wide range of requirements. Upper Saddle River. many software radio products are available in ruggedized and conduction-cooled versions. Some of these products are software radio receivers in that they include only DDCs.com • http://www. Pentek software radio recording systems are supported with SystemFlow® recording software that features a graphical user interface. Inc.pentek. VPX. PCI. Others are software radio transceivers and they include DDCs as well as DUCs with output D/A converters. the GateFlow® FPGA Design Kit and high-performance factoryinstalled IP cores that expand the features and range of many Pentek software radio products.Software Defined Radio Handbook Products PMC. CompactPCI. In addition to their commercial versions. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com . gating and triggering. PCI Express. These come with independent input and output clocks.

5 MHz channels can be combined for output bandwidths of 5 MHz or 10 MHz. The LVDS bus allows multiple modules to be synchronized with the same sample clock. a 16-Channel Multiband Receiver. • One Park Way. Four parallel outputs from the four DDCs deliver data into the Virtex-II FPGA which can be either the XC2V1000 or XC2V3000. Custom interfaces can be implemented by using the 64 user-defined FPGA I/O pins on the P4 connector. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. gating. Upper Saddle River.pentek.com . 19 Pentek. Up to 80 modules can be synchronized with the Model 9190 Clock and Sync Generator. respectively. The unit supports the channel combining mode of the 4016s such that two or four individual 2. Versions of the 7131 are also available as a PCI board (Model 7631A). Both inputs are connected to four TI/GC4016 quad DDC chips. is a PMC module. 3U cPCI (Model 7331) and 3U VPX (Model 5331). Two 14-bit 105 MHz A/D Converters accept transformer-coupled RF inputs through two front panel SMA connectors.com • http://www. The 7131 PMC may be attached to a wide range of industry processor platforms equipped with PMC sites. so that all 16 DDC channels can independently select either A/D. The sampling clock can be sourced from an internal 100 MHz crystal oscillator or from an external clock supplied through an SMA connector or the LVDS clock/sync bus on the front panel.Software Defined Radio Handbook Products Multiband Receivers Model 7131 PMC ● Model 7231 6U cPCI ● Model 7331 3U cPCI ● Model 7631A PCI ● Model 5331 3U VPX Model 7631A PCI Model 7131 PMC Model 5331 3U VPX Figure 30 Model 7331 3U cPCI Model 7231D 6U cPCI The Model 7131. Inc. All these products have similar features. triggering and frequency switching signals. The outputs of the two A/D converters are also connected directly to the FPGA to support the DDC bypass path to the PCI bus and for direct processing of the wideband A/D signals by the FPGA. 6U cPCI (Models 7231 and 7231D dual density).

com . The FPGA also serves as a control and status engine with data and programming interfaces to each of the on-board resources. All these products have similar features.pentek.2 INTERFACE (64 Bits / 66 MHz) 8X 64 PCI BUS (64 Bits / 66 MHz) P15 XMC P4 PMC VITA 42. These resources include a quad digital downconverter. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 32 DDR SDRAM 128 MB 32 DDR SDRAM 256 MB Model 7140 PMC/XMC 64 PCI 2. Versions of the 7140 are also available as a PCI board (Model 7640). The digitized output signals pass to a Virtex-II Pro FPGA for signal processing or routing to other module resources. The front end of the module accepts two RF inputs and transformer-couples them into two 14-bit A/D converters running at 105 MHz. 512 MB DDR SDRAM delay memory and the PCI bus. developed using Pentek’s GateFlow and ReadyFlow development tools.com • http://www. or 3U cPCI (Model 7340). channel selection.Software Defined Radio Handbook Products Multiband Transceivers with Virtex-II Pro FPGA Model 7140 PMC/XMC ● Model 7240 6U cPCI Sample Clock A In TIMING BUS GENERATOR A XTL OSC A ● Model 7340 3U cPCI RF In RF XFORMR RF In RF XFORMR ● Model 7640 PCI RF Out RF XFORMR RF Out RF XFORMR LVDS Clock A LVDS Sync A LVDS Gate A TTL Gate/ Trigger TTL Sync LVDS Gate B LVDS Sync B LVDS Clock B Clock/Sync/Gate Bus A SYNC INTERRUPTS & CONTROL Clock/Sync/Gate Bus B 16-bit D/A AD6645 105 MHz 14-bit A/D 14 AD6645 105 MHz 14-bit A/D 14 16 16 16 16-bit D/A DAC5686 DIGITAL UPCONVERTER GC4016 4-CHANNEL DIGITAL RECEIVER 14 32 FLASH 16 MB 16 24 TIMING BUS GENERATOR B Sample Clock B In XTL OSC B To All Sections Control/ Status 32 DDR SDRAM 128 MB VIRTEX-II Pro FPGA XC2VP50 DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc. In addition to acting as a simple transceiver. The upconverter translates a real or complex baseband signal to any IF center frequency from DC to 160 MHz and can deliver real or complex (I + Q) analog outputs through its two 16-bit D/A converters. triggering. and SDRAM memory control. The digital upconverter can be bypassed for two interpolated D/A outputs with sampling rates to 500 MHz. Each channel in the downconverter can be set with an independent tuning frequency and bandwidth.0 FPGA I/O (Serial RapidIO. the module can perform user-defined DSP functions on the baseband signals.) Figure 31 The Model 7140 PMC module combines both receive and transmit capability with a high-performance Virtex II-Pro FPGA and supports the VITA 42 XMC standard with optional switched fabric interfaces for high-speed I/O. 20 Pentek. Inc. gating. a digital upconverter with dual D/A converters. Upper Saddle River. (Option –104) PCI-Express. 6U cPCI (Models 7240 and 7240D dual density). etc. Factory-installed FPGA functions include data multiplexing. data packing. The module includes a TI/GC4016 quad digital downconverter along with a TI DAC5686 digital upconverter with dual D/A converters. • One Park Way.

Software Defined Radio Handbook Products Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores Model 7140-420 PMC/XMC ● Model 7240-420 6U cPCI Model 7340-420 3U cPCI ● Model 7640-420 PCI CH A RF In RF XFORMR AD6645 105 MHz 14-bit A/D WIDEBAND DDC CORE CH B RF In RF XFORMR AD6645 105 MHz 14-bit A/D DDC C DDC D MEMORY D/A A CONTROL D/A B & A/D A DATA ROUTING A/D B 128 MB DDR SDRAM 128 MB DDR SDRAM 256 MB DDR SDRAM Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D MEMORY MEMORY A/D A A/D B DDC A DDC B A/D A A/D B DDC A DDC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION: 2 – 64 MEM W FIFO MEM W FIFO A/D A FIFO A/D B FIFO WB DDC A DDC A WB DDC B DDC B MUX MUX DDC A FIFO DDC B FIFO DDC C FIFO PCI BUS 64 bit / 66 MHz CLOCK & SYNC GENERATOR XTAL OSC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION:.25 MHz for an A/D sampling of 100 MHz. A multiplexer in front of the Core 420 DDCs allows data to be sourced from either the A/Ds or the GC4016. Factory-installed in the Model 7140 FPGA. Inc. extending the maximum cascaded decimation range to 1. A complex FIR low pass filter removes any out-of-band frequency components. • One Park Way.768 programmable in steps of 2. The FIR filter is capable of storing and utilizing up to four independent sets of 18-bit coefficients for each decimation value. all the standard features of the 7140 are retained. 4. The mixer utilizes four 18x18-bit multipliers to handle the complex inputs from the NCO and the complex data input samples. 32.2 INTERFACE CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A DAC 5686 DIGITAL 16-bit UPCONVERTER 500 MHZ D/A MUX CIC FILTER CFIR FILTER MUX MEMORY D/A A FIFO MEMORY D/A B FIFO DDC D FIFO D/A A FIFO D/A B FIFO INTERPOLATION CORE XC2VP50 Figure 32 The Pentek IP Core 420 includes a dual highperformance wideband DDC and an interpolation filter.com • http://www. Including the DUC. 21 Pentek. Upper Saddle River. The decimation settings of 2. or 3U cPCI (Model 7340-420). Like the GC4016. and 64 provide output bandwidths from 40 MHz down to 1. These coefficients are user-programmable by using RAM structures within the FPGA. In addition to the Core 420. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.768 which is comparable to the maximum decimation of the GC4016 narrowband DDC. 6U cPCI (Models 7240-420 and 7240D-420 dual density).com . each of the core 420 DDCs translates any frequency band within the input bandwidth range down to zero frequency.048. An output decimator and formatter deliver either complex or real data. All these products have similar features. An input gain block scales both I and Q data streams by a 16-bit gain term. 8.576.pentek. the maximum interpolation factor is 32. they extend the range of both the GC4016 ASIC DDC and the DAC5686 DUC. The interpolation filter included in the 420 Core. 16. and relieves the host processor from performing upsampling tasks.2 – 64 PCI 2. expands the interpolation factor from 2 to 32. Versions of the 7140-420 are also available as a PCI board (Model 7640-420).

In addition to the DDC outputs. • One Park Way. A multiplexer in front of the core allows data to be sourced from either A/D converter A or B. 22 Pentek. and are independently programmable to any value. Added flexibility comes from programmable global decimation settings ranging from 1024 to 8192 in steps of 256.Software Defined Radio Handbook Products Transceivers with 256-Channel Narrowband DDC Installed Core Model 7140-430 PMC/XMC ● Model 7240-430 6U cPCI Model 7340-430 3U cPCI ● Model 7640-430 PCI CH A RF In RF XFORMR AD6645 105 MHz 14-bit A/D MEM W FIFO MEM W FIFO CH B RF In RF XFORMR AD6645 105 MHz 14-bit A/D 256 CHANNEL DIGITAL DOWNCONVERTER BANK CORE 1 DDC 1 Local Oscillator. Mixer. Unlike classic channelizer methods.2 INTERFACE INT PCI BUS 64 bit / 66 MHz Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A MUX A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D M U X CLOCK & SYNC GENERATOR XTAL OSC B .com • http://www.pentek. A TI DAC5686 digital upconverter and dual D/A accepts baseband real or complex data streams from the PCI Bus with signal bandwidths up to 40 MHz. Mixer. the Pentek 430 core allows for completely independent programmable tuning of each individual channel with 32-bit resolution as well as filter characteristics comparable to many conventional ASIC DDCs. Inc. At the output. Upper Saddle River. a multiplexer allows the 7140430 to route either the output of the GC4016 or the Core 430 DDC to the PCI Bus. CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A 16-bit 500 MHZ D/A DAC 5686 DIGITAL UPCONVERTER D/A A FIFO D/A B FIFO XC2VP50 Figure 33 For applications that require many channels of narrowband downconverters.com . Versions of the 7140-430 are also available as a PCI board (Model 7640-430). Factory installed in the Model 7140 FPGA. 6U cPCI (Models 7240-430 and 7240D-430 dual density). or 3U cPCI (Model 7340-430). NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Default DDC filter coefficient sets are included with the core for all possible decimation settings. All these products have similar features. and 18-bit user programmable FIR decimating filter coefficients for the DDCs. It differs from others in that the channel center frequen- cies need not be at fixed intervals. Filter OUT A DDC A OUT B DDC B OUT C DDC C OUT D DDC D DDC A FIFO DDC B FIFO DDC C FIFO DDC D FIFO PCI 2. Core 430 utilizes a unique method of channelization. Core 430 creates a flexible. Filter 256 DDC 256 Local Oscillator. Mixer. Filter M U X 255 DDC 255 Local Oscillator. very high-channel count receiver system in a small footprint. Core 430 DDC comes factory installed in the Model 7140-430. Filter 2 DDC 1 Local Oscillator. data from both A/D channels are presented to the PCI Bus at a rate equal to the A/D clock rate divided by any integer value between 1 and 4096. Pentek offers the GateFlow IP Core 430 256-channel digital downconverter bank. Mixer.

Software Defined Radio Handbook Products Multiband Transceivers with Virtex-II Pro FPGA Model 7141 PMC/XMC ● Model 7241 6U cPCI ● Model 7341 3U cPCI ● Model 7641 PCI ● Model 7741 Full-length PCIe ● Model 7841 Half-length PCIe ● Model 5341 3U VPX Sample Clock A In TIMING BUS GENERATOR A XTL OSC A RF In RF XFORMR RF In RF XFORMR RF Out RF XFORMR RF Out RF XFORMR LVDS Clock A LVDS Sync A LVDS Gate A TTL Gate/ Trigger TTL Sync LVDS Gate B LVDS Sync B LVDS Clock B FRONT PANEL CONNECTOR SYNC Clock/Sync/Gate Bus A 16-bit D/A LTC2255 AD6645 105 MHz 125 14-BITA/D 14-bit A/D 14 LTC2255 AD6645 105 MHz 125 14-BITA/D 14-bit A/D 14 16 16 16 GC4016 4-CHANNEL DIGITAL RECEIVER 14 32 16-bit D/A INTERRUPTS & CONTROL Clock/Sync/Gate Bus B DAC5686 DIGITAL UPCONVERTER FLASH 24 16 MB 16 TIMING BUS GENERATOR B Sample Clock B In XTL OSC B To All Sections Control/ Status 32 DDR SDRAM 128 MB VIRTEX-II Pro FPGA XC2VP50 DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc.pentek. developed using Pentek’s GateFlow and ReadyFlow development tools. and SDRAM memory control. In addition to acting as a simple transceiver. Factory-installed FPGA functions include data multiplexing. These resources include a quad digital downconverter. 23 Pentek. 512 MB DDR SDRAM delay memory and the PCI bus. • One Park Way. and 3U cPCI (Model 7341). etc. data packing. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Model 7141-703 is a conduction-cooled version. The FPGA also serves as a control and status engine with data and programming interfaces to each of the on-board resources. 6U cPCI (Models 7241 and 7241D dual density). the module can perform user-defined DSP functions on the baseband signals.2 INTERFACE (64 Bits / 66 MHz) 64 P4 PMC P15 XMC FPGA I/O VITA 42.0 (Serial RapidIO.com • http://www. The digitized output signals pass to a Virtex-II Pro FPGA for signal processing or routing to other module resources. gating. channel selection. PCI board (Model 7641). triggering. Versions of the 7141 are also available as a PCIe full-length board (Models 7741 and 7741D dual density). PCIe half-length board (Model 7841). The front end of the module accepts two RF inputs and transformer-couples them into two 14-bit A/D converters running at 125 MHz. Inc. a digital upconverter with dual D/A converters.) PCI BUS (64 Bits / 66 MHz) Figure 34 The Model 7141 PMC/XMC module combines both receive and transmit capabilities with a highperformance Virtex II-Pro FPGA and supports the VITA 42 XMC standard with optional switched fabric interfaces for high-speed I/O. The digital upconverter can be bypassed for two interpolated D/A outputs with sampling rates to 500 MHz.com . The module includes a TI/GC4016 quad digital downconverter along with a TI DAC5686 digital upconverter with dual D/A converters. The upconverter translates a real or complex baseband signal to any IF center frequency from DC to 160 MHz and can deliver real or complex (I + Q) analog outputs through its two 16-bit D/A converters. 32 DDR SDRAM 128 MB 32 DDR SDRAM 256 MB Model 7141 PMC/XMC 64 PCI 2. (Option –104) PCI-Express. Upper Saddle River. Each channel in the downconverter can be set with an independent tuning frequency and bandwidth. 3U VPX board (Model 5341).

The interpolation filter included in the 420 Core.25 MHz for an A/D sampling of 100 MHz.pentek. The decimation settings of 2. they extend the range of both the GC4016 ASIC DDC and the DAC5686 DUC. PCIe full-length board (Models 7741-420 and 7741D-420 dual density). Including the DUC. A multiplexer allows data to be sourced from either the A/Ds or the GC4016. An output decimator and formatter deliver either complex or real data. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.2 – 64 PCI 2. The FIR filter is capable of storing and utilizing up to four independent sets of 18-bit coefficients for each decimation value. Upper Saddle River.com . These coefficients are user-programmable by using RAM structures within the FPGA. • One Park Way. Inc. The mixer utilizes four 18x18-bit multipliers to handle the complex inputs from the NCO and the complex data input samples. 6U cPCI (Models 7241-420 and 7241D-420 dual density). 24 Pentek. expands the interpolation factor from 2 to 32. Model 7141703-420 is a conduction-cooled version.768 which is comparable to the maximum decimation of the GC4016 narrowband DDC. An input gain block scales both I and Q data streams by a 16-bit gain term. Each of the core 420 DDCs translates any frequency band within the input bandwidth range down to zero frequency.768 programmable in steps of 2. A complex FIR low pass filter removes any outof-band frequency components.2 INTERFACE CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A DAC 5686 DIGITAL 16-bit UPCONVERTER 500 MHZ D/A MUX CIC FILTER CFIR FILTER MUX MEMORY D/A A FIFO MEMORY D/A B FIFO DDC D FIFO D/A A FIFO D/A B FIFO INTERPOLATION CORE XC2VP50 Figure 35 The Pentek IP Core 420 includes a dual highperformance wideband DDC and an interpolation filter. PCI board (Model 7641-420).com • http://www. 8. 4. and relieves the host processor from performing upsampling tasks. the maximum interpolation factor is 32. or 3U cPCI (Model 7341-420).048. and 64 provide output bandwidths from 40 MHz down to 1. 32. Factory-installed in the Model 7141 FPGA. PCIe half-length board (Model 7841-420). extending the cascaded decimation range to 1.Software Defined Radio Handbook Products Transceivers with Dual Wideband DDC and Interpolation Filter Installed Cores Model 7141-420 PMC/XMC ● Model 7241-420 6U cPCI ● Model 7341-420 3U cPCI Model 7641-420 PCI ● Model 7741-420 Full-length PCIe Model 7841-420 Half-length PCIe ● Model 5341-420 3U VPX CH A RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D WIDEBAND DDC CORE CH B RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D DDC C DDC D MEMORY D/A A CONTROL D/A B & A/D A DATA ROUTING A/D B 128 MB DDR SDRAM 128 MB DDR SDRAM 256 MB DDR SDRAM Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D MEMORY MEMORY A/D A A/D B DDC A DDC B A/D A A/D B DDC A DDC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION: 2 – 64 MEM W FIFO MEM W FIFO A/D A FIFO A/D B FIFO WB DDC A DDC A WB DDC B DDC B MUX MUX DDC A FIFO DDC B FIFO DDC C FIFO PCI BUS 64 bit / 66 MHz CLOCK & SYNC GENERATOR XTAL OSC B M U X WIDEBAND DIGITAL DOWNCONVERTR A DECIMATION:.576. 16. Versions of the 7141-420 are also available as a 3U VPX board (Model 5341-420).

Mixer. Core 430 creates a flexible. 3U VPX board (Model 5341-430). Model 7141-703430 is a conduction-cooled version.com . or 3U cPCI (Model 7341-430). In addition to the DDC outputs. At the output. Factory installed in the Model 7141 FPGA. data from both A/D channels are presented to the PCI Bus at a rate equal to the A/D clock rate divided by any integer value between 1 and 4096. Pentek offers the GateFlow IP Core 430 256-channel digital downconverter bank. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. PCI board (Model 7641430). • One Park Way. Inc. 6U cPCI (Models 7241-430 and 7241D-430 dual density). It differs from others in that the channel center frequen- cies need not be at fixed intervals. Core 430 utilizes a unique method of channelization. and 18-bit user programmable FIR decimating filter coefficients for the DDCs. Filter M U X 255 DDC 255 Local Oscillator. CH A RF Out CH B RF Out RF XFORMR RF XFORMR 16-bit 500 MHZ D/A 16-bit 500 MHZ D/A DAC 5686 DIGITAL UPCONVERTER D/A A FIFO D/A B FIFO XC2VP50 Figure 36 For applications that require many channels of narrowband downconverters. Core 430 DDC comes factory installed in the Model 7141-430. Default DDC filter coefficient sets are included with the core for all possible decimation settings. Versions of the 7141-430 are also available as a PCIe full-length board (Models 7741-430 and 7741D-430 dual density). Filter OUT A DDC A OUT B DDC B OUT C DDC C OUT D DDC D DDC A FIFO DDC B FIFO DDC C FIFO DDC D FIFO PCI 2.Software Defined Radio Handbook Products Transceivers with 256-Channel Narrowband DDC Installed Core Model 7141-430 PMC/XMC ● Model 7241-430 6U cPCI ● Model 7341-430 3U cPCI Model 7641-430 PCI ● Model 7741-430 Full-length PCIe Model 7841-430 Half-length PCIe ● Model 5341-430 3U VPX CH A RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D MEM W FIFO MEM W FIFO CH B RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D 256 CHANNEL DIGITAL DOWNCONVERTER BANK CORE 1 DDC 1 Local Oscillator.2 INTERFACE INT PCI BUS 64 bit / 66 MHz Sample Clock A In Clock/Sync Bus Sample Clock B In XTAL OSC A MUX A B C D MUX GC4016 DIGITAL DOWNCONVERTR A B C D M U X CLOCK & SYNC GENERATOR XTAL OSC B . Mixer. A multiplexer allows data to be sourced from either A/D. 25 Pentek. and are independently programmable to any value. Added flexibility comes from programmable global decimation settings ranging from 1024 to 8192 in steps of 256.com • http://www. Unlike classic channelizer methods. a multiplexer allows for routing either the output of the GC4016 or the 430 DDC to the PCI Bus. Filter 256 DDC 256 Local Oscillator. Upper Saddle River. the Pentek 430 core allows for completely independent programmable tuning of each individual channel with 32-bit resolution as well as filter characteristics comparable to many conventional ASIC DDCs. Mixer. Filter 2 DDC 1 Local Oscillator.pentek. PCIe half-length board (Model 7841-430). very high-channel count receiver system in a small footprint. A TI DAC5686 digital upconverter and dual D/A accepts baseband real or complex data streams from the PCI Bus with signal bandwidths up to 50 MHz. Mixer.

and 3U cPCI (Model 7342). 3U VPX (Model 5342).0 64 LOCAL BUS 32 32 32 HI-SPEED BUSES Model 7142 PMC/XMC VIRTEX-4 FPGA XC4VFX60 or XC4VFX100 SERIAL INTERFACE 64 P4 PMC FPGA I/O (Option –104) Figure 37 The Model 7142 is a Multichannel PMC/XMC module. • One Park Way. It also features 768 MB of SDRAM for implementing up to 2. A 16 MB flash memory supports the boot code for the two on-board IBM 405 PowerPC microcontroller cores within the FPGA. 6U cPCI (Models 7242 and 7242D dual density). Inc. PCI board (Model 7642). implemented with the Xilinx Rocket I/O interfaces. A 9-channel DMA controller and 64 bit / 66 MHz PCI interface assures efficient transfers to and from the module. The first FPGA is used for control and signal processing functions. It also supports large. while the second one is used for implementing board interface functions including the XMC interface.Software Defined Radio Handbook Products Multichannel Transceivers with Virtex-4 FPGAs Model 7142 PMC/XMC ● Model 7242 6U cPCI ● Model 7342 3U cPCI ● Model 7642 PCI Model 7742 Full-length PCIe ● Model 7842 Half-length PCIe ● Model 5342 3U VPX Sample Clock In TIMING BUS GENERATOR A XTL OSC A RF In RF XFORMR RF In RF XFORMR RF In RF XFORMR RF In RF XFORMR RF Out RF XFORMR LVDS Clock A LVDS Sync A LVDS Gate A TTL Gate/ Trigger TTL Sync LVDS Gate B LVDS Sync B LVDS Clock B LTC2255 125MHz INTERRUPTS Clock/Sync/Gate 14-bit A/D & CONTROL Bus B 14 SYNC Clock/Sync/Gate Bus A LTC2255 125MHz 14-bit A/D 14 LTC2255 125MHz 14-bit A/D 14 LTC2255 125MHz 14-bit A/D 14 16-bit D/A DAC5686 DIGITAL UPCONVERTER 32 TIMING BUS GENERATOR B XTL OSC B To All Sections Control/ Status VIRTEX-4 FPGA XC4VSX55 DSP – Channelizer – Digital Delay – Demodulation – Decoding – Control – etc. multichannel applications where the relative phases must be preserved. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. A dual bus system timing generator allows separate clocks. Upper Saddle River. gates and synchronization signals for the A/D and D/A converters. 26 Pentek.0 sec of transient capture or digital delay memory for signal intelligence tracking applications at 125 MHz. It includes four 125 MHz 14-bit A/D converters and one upconverter with a 500 MHz 16-bit D/A converter to support wideband receive and transmit communication channels.pentek.5 GB/sec data links to the carrier board.com • http://www. connect the second FPGA to the XMC connector with two 2.com . 32 DDR 2 SDRAM 256 MB 32 DDR 2 SDRAM 256 MB 32 DDR 2 SDRAM 256 MB PCI 2. A high-performance 160 MHz IP core wideband digital downconverter may be factory-installed in the first FPGA. PCIe half-length board (Model 7842). Versions of the 7142 are also available as a PCIe fulllength board (Models 7742 and 7742D dual density). Two Xilinx Virtex-4 FPGAs are included: an XC4VSX55 or LX100 and an XC4VFX60 or FX100.2 INTERFACE PCI BUS (64 Bits / 66 MHz) P15 XMC VITA 42. Two 4X switched serial ports.

Software Defined Radio Handbook Products Transceivers with Four Multiband DDCs and Interpolation Filter Installed Cores Model 7142-428 PMC/XMC ● Model 7242-428 6U cPCI ● Model 7342-428 3U cPCI Model 7642-428 PCI ● Model 7742-428 Full-length PCIe Model 7742-428 Half-length PCIe ● Model 5342-428 3U VPX CH A RF In RF XFORMR LTC2255 AD6645 125 MHz 105 14-bit A/D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D D/A M U X DIGITAL DOWNCONVERTR A STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR B STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR C STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR D STAGE 1 DECIMATION: 2 – 256 DIGITAL DOWNCONVERTR A STAGE 2 DECIMATION: 1 – 256 DIGITAL DOWNCONVERTR B STAGE 2 DECIMATION: 1 – 256 DIGITAL DOWNCONVERTR C .com . provides output bandwidths from 50 MHz down to 1. programmable in steps of 4. The interpolation filter can be used in series with the DUC’s built-in interpolation. The overal decimation range from 2 to 65. for a maximum interpolation of 32. they add DDCs to the Model 7142 and extend the range of its DAC5686 DUC.536. Versions of the 7142-428 are also available as a PCIe full-length board (Models 7742-428 and 7742D-428 dual density). The decimation of each DDC can be set independently. These coefficients are user-programmable by using RAM structures within the FPGA. PCIe half-length board (Model 7842-428).pentek. An input multiplexer allows any DDC to independently select any of the four A/D sources. 27 Pentek. Upper Saddle River. After each filter stage is a post filter gain stage. NCO tuning frequency. 6U cPCI (Models 7242-428 and 7242D-428 dual density). and 3U VPX (Model 5342-428). NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.52 kHz for an A/D sampling rate of 125 MHz and assuming an 80% filter. programmable in steps of 1. The DDCs consist of two cascaded decimating FIR filters. Inc. and relieves the host processor from performing upsampling tasks. The Core 428 downconverter translates any frequency band within the input bandwidth range down to zero frequency. PCI board (Model 7642-428). Factory-installed in the Model 7142 FPGA. The Core 428 interpolation filter increases the sampling rate of real or complex baseband signals by a factor of 16 to 2048. The FIR filter is capable of storing and utilizing two independent sets of 18-bit coefficients. decimation and filter coefficients can be changed dynamically. Four identical Core 428 DDCs are factory installed in the 7142-428 FPGA. This gain may be used to amplify small signals after out-of-band signals have been filtered out.2 INTERFACE PCI BUS 64 bit / 66 MHz 256 MB DDR SDRAM MEMORY CONTROL & DATA ROUTING 256 MB DDR SDRAM 256 MB DDR SDRAM CH B RF In RF XFORMR LTC2255 125 MHz 14-bit A/D CH C RF In RF XFORMR LTC2255 125 MHz 14-bit A/D CH D RF In RF XFORMR LTC2255 125 MHz 14-bit A/D M U X M U X Sample Clock In Clock/Sync Bus CLOCK & SYNC GENERATOR XTAL OSC A XTAL OSC B M U X DIGITAL DOWNCONVERTER CORE RF Out RF XFORMR 16-bit 500 MHZ DAC 5686 16-bit D/A 500 MHZ DIGITAL D/A UPCONVERTER CIC FILTER CFIR FILTER MUX MEMORY D/A FIFO D/A FIFO INTERPOLATION CORE XC4VSX55 Figure 38 The Pentek IP Core 428 includes four highperformance multiband DDCs and an interpolation filter. 3U cPCI (Model 7342-428). The NCO provides over 108 dB spurious-free dynamic range (SFDR). • One Park Way. STAGE 2 DECIMATION: 1 – 256 DIGITAL DOWNCONVERTR D STAGE 2 DECIMATION: 1 – 256 MEM W FIFO MEM W FIFO A/D A DDC A A/D B DDC B A/D C DDC C A/D D DDC D MUX MUX MUX MUX A/D A FIFO A/D B FIFO A/D C FIFO A/D D FIFO PCI 2.768.com • http://www.

The digitized output signals pass to a Virtex-5 FPGA for routing.com • http://www. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. where N is the decimation setting. with a sampling rate of 200 MHz. the available output bandwidths range from 156. and 3U VPX (Model 5351). Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.8*ƒs/N. 3U cPCI (Model 7351).1024 I&Q DDC BANK 1 MUX A/D A FIFO PCI BUS 64 bit / 66 MHz M U X I&Q A/D B DDC BANK 2 MUX A/D B FIFO Sample Clock In PPS In TTL In TIMING BUS GENERATOR Clock / Gate / Sync / PPS M U X I&Q A/D C DDC BANK 3 PCI 2. Inc. selectable from 0 to 64. PCI board (Model 7651). Each of the 256 DDCs has an independent 32-bit tuning frequency setting. formatting and DDC signal processing. The Model 7151 employs an advanced FPGA-based digital downconverter engine consisting of four identical 64-channel DDC banks.2 INTERFACE MUX A/D C FIFO M U X I&Q A/D D DDC BANK 4 MUX A/D D FIFO Sync Bus XTAL OSC DIGITAL DOWNCONVERTER CORE XC5VSX95T Figure 39 The Model 7151 PMC module is a 4-channel highspeed digitizer with a factory-installed 256-channel DDC core. Upper Saddle River.1024 DIGITAL DOWNCONVERTR BANK 4: CH 193 . 28 Pentek.com . Any number of channels can be enabled within each bank. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples. 6U cPCI (Models 7251 and 7251D dual density). 16-bit A/D Model 7151 PMC ● Model 7251 6U cPCI ● Model 7351 3U cPCI ● Model 7651 PCI Model 7751 Full-length PCIe ● Model 7851 Half-length PCIe ● Model 5351 3U VPX CH A RF In RF XFORMR ADS5485 AD6645 200 MHz 105 16-bit A/D 14-bit ADS5485 200 MHz 16-bit A/D ADS5485 200 MHz 16-bit A/D CH B RF In RF XFORMR CH C RF In RF XFORMR CH D RF In RF XFORMR ADS5485 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D A/D A A/D B A/D C A/D D M U X DIGITAL DOWNCONVERTR BANK 1: CH 1 .128 DECIMATION: 128 .25 kHz to 1. The front end of the module accepts four RF inputs and transformer-couples them into four 16-bit A/D converters running at 200 MHz. • One Park Way.256 DECIMATION: 128 .pentek.1024 DIGITAL DOWNCONVERTR BANK 3: CH 129 . Versions of the 7151 are also available as a PCIe full-length board (Models 7751 and 7751D dual density). The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. The 80% default filters deliver an output bandwidth of 0. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.25 MHz. All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024. PCIe half-length board (Model 7851).1024 DIGITAL DOWNCONVERTR .64 DECIMATION: 128 . BANK 2: CH 65 . programmable in steps of 64. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank. For example.Software Defined Radio Handbook Products 256-Channel DDC Installed Core with Quad 200 MHz.192 DECIMATION: 128 .

where N is the decimation setting.32 POWER DEC: 16 .2 INTERFACE A/D C FIFO Sync Bus XTAL OSC A/D A A/D B A/D C A/D D M U X A/D D BANK 4 MUX A/D D FIFO XC5VSX95T Figure 40 The Model 7152 PMC module is a 4-channel highspeed digitizer with a factory-installed 32-channel DDC core. 3U cPCI (Model 7352).53 kHz to 10.0 MHz. For example. 6U cPCI (Models 7252 and 7252D dual density). PCI board (Model 7652). The rejection of adjacent-band components within the 80% output band-width is better than 100 dB. power meters and threshold detectors are included. formatting and DDC signal processing. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank. the available output bandwidths range from 19. and 3U VPX (Model 5352). • One Park Way. PCIe half-length board (Model 7852). The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.Software Defined Radio Handbook Products 32-Channel DDC Installed Core with Quad 200 MHz.8192 METER & THRESHOLD DETECT 8x4 CHANNEL SUMMATION SUM A/D B BANK 1 MUX A/D A FIFO CH C RF In RF XFORMR ADS5485 200 MHz 16-bit A/D M U X CH D RF In RF XFORMR ADS5485 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D M U X A/D B BANK 2 MUX A/D B FIFO PCI BUS 64 bit / 66 MHz Sample Clock In PPS In TTL In TIMING BUS GENERATOR Clock / Gate / Sync / PPS A/D A A/D B A/D C A/D D M U X A/D C BANK 3 MUX PCI 2. Versions of the 7152 are also available as a PCIe fulllength board (Models 7752 and 7752D dual density).24 DEC: 16 . Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples. Each 8-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths for the board. Upper Saddle River.8192 METER & THRESHOLD DETECT DIGITAL DOWNCONVERTR I & Q BANK 3: CH 17 . All of the 8 channels within a bank share a common decimation setting that can range from 16 to 8192. Each of the 32 DDCs has an independent 32-bit tuning frequency setting. The Model 7152 employs an advanced FPGA-based digital downconverter engine consisting of four identical 8-channel DDC banks.8192 METER & THRESHOLD DETECT DIGITAL DOWNCONVERTR I & Q BANK 2: CH 9 . The digitized output signals pass to a Virtex-5 FPGA for routing. Gain and phase control.8192 POWER METER & THRESHOLD DETECT DIGITAL DOWNCONVERTR I & Q BANK 4: CH 25 . NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank.com . 29 Pentek. DEC: 16 . with a sampling rate of 200 MHz. Any number of channels can be enabled within each bank. Inc.8*ƒs/N. selectable from 0 to 8.16 POWER. 16-bit A/D Model 7152 PMC ● Model 7252 6U cPCI ● Model 7352 3U cPCI ● Model 7652 PCI Model 7752 Full-length PCIe ● Model 7852 Half-length PCIe ● Model 5352 3U VPX CH A RF In RF XFORMR ADS5485 AD6645 200 MHz 105 16-bit A/D 14-bit CH B RF In RF XFORMR ADS5485 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D DIGITAL DOWNCONVERTER CORE DIGITAL DOWNCONVERTR I & Q BANK 1: CH 1 .com • http://www. programmable in steps of 8.8 POWER DEC: 16 .pentek. The front end of the module accepts four RF inputs and transformer-couples them into four 16-bit A/D converters running at 200 MHz.

PCI board (Model 7653). where N is the decimation setting. PCIe half-length board (Model 7853). The power meters present average power measurements for each channel in easy-to-read registers.com • http://www. and 3U VPX (Model 5353). Each of the 4 DDCs has an independent 32-bit tuning frequency setting. Four independently controllable input multiplexers select one of the four A/Ds as the input source for each DDC bank.pentek. The Model 7153 employs an advanced FPGA-based DDC engine consisting of four identical multiband banks. The 80% default filters deliver an output bandwidth of 0. Each channel also includes a threshold detector that sends an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 3U cPCI (Model 7353). Upper Saddle River. 16-bit A/Ds Model 7153 PMC/XMC ● Model 7253 6U cPCI ● Model 7353 3U cPCI ● Model 7653 PCI Model 7753 Full-length PCIe ● Model 7853 Half-length PCIe ● Model 5353 3U VPX CH A RF In CH B RF In CH C RF In CH D RF In 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D A/D A A/D B A/D C A/D D P15 XMC A/D A A/D B A/D C A/D D DIGITAL DOWN CONVERTER CORE M U X Sum In Sum Out POWER METER & THRESHOLD DETECTOR I&Q Aurora Gigabit Serial Interface 4X 4X SUMMER S DDC 1 DEC: 2 . Each channel contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output.256 Gain & Phase Adj POWER METER & THRESHOLD DETECTOR I&Q A/D D M U X PCI-X I/F XC5VSX50T FPGA Figure 41 Model 7153 is a 4-channel.256 Gain & Phase Adj I&Q A/D B M U X Timing Clock Sync A/D A A/D B A/D C A/D D M U X POWER METER & THRESHOLD DETECTOR DDC 3 DEC: 2 . The time constant of the averaging interval for each meter is programmable up to 8 ksamples. Versions of the 7153 are also available as a PCIe fulllength board (Models 7753 and 7753D dual density). programmable independenly in steps of 1. The rejection of adjacent-band components within the 80% output band-width is better than 100 dB. high-speed software radio module designed for processing baseband RF or IF signals. • One Park Way. 6U cPCI (Models 7253 and 7253D dual density).256 Gain & Phase Adj A/D C I&Q M U X PCI-X Bus 64-bits 100 MHz A/D A A/D B A/D C A/D D M U X DDC 4 DEC: 2 .8*ƒs/N. In addition to the DDCs. it provides everything needed for implementing multichannel beamforming systems. Inc.Software Defined Radio Handbook Products 4-Channel DDC and Beamformer Installed Core with four 200 MHz. the 7153 features a complete beamforming subsystem. With built-in multiboard synchronization and an Aurora gigabit serial interface. All four DDCs have a decimation setting that can range from 2 to 256.com . 30 Pentek. It features four 200 MHz 16-bit A/Ds supported by a highperformance 4-channel DDC (digital downconverter) installed core and a complete set of beamforming functions. The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients.256 Gain & Phase Adj A/D A M U X Sample Clock Gate / Trigger PPS Clock & SYNC Bus XTAL OSC A/D A A/D B A/D C A/D D POWER METER & THRESHOLD DETECTOR M U X DDC 2 DEC: 2 .

pentek. The Model 7156 architecture includes two Virtex-5 FPGAs.5 GB/sec data links to the carrier board. It also supports large. PCIe half-length board (Model 7856). enabling factory installed functions such as data multiplexing.com . The first FPGA is used primarily for signal processing while the second one is dedicated to board interfaces.com • http://www. A 5-channel DMA controller and 64 bit/100 MHz PCIX interface assures efficient transfers to and from the module. SX95T or FX100T LVDS GTP GTP GTP 64 4X GTP 4X 4X Model 7156 PMC/XMC SDRAM SDRAM 512 MB 512 MB P4 PMC 32 32 PCI X BUS 64 4X P15 XMC Figure 42 Model 7156 is a dual high-speed data converter suitable for connection as the HF or IF input of a communications system.Software Defined Radio Handbook Products Dual SDR Transceivers with 400 MHz A/D. 800 MHz D/A. PCI board (Model 7656). All of the board’s data and control paths are accessible by the FPGAs. and 3U VPX (Model 5356). A dual bus system timing generator allows for sample clock synchronization to an external system reference. It features two 400 MHz 14-bit A/Ds. • One Park Way. multichannel applications where the relative phases must be preserved. 31 Pentek. Two 4X switched serial ports implemented with the Xilinx Rocket I/O interfaces. a DUC with two 800 MHz 16-bit D/As. All these products have similar features.and post-triggering. Inc. 6U cPCI (Models 7256 and 7256D dual density). NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Upper Saddle River. connect the FPGA to the XMC connector with two 2. channel selection. Built-in memory functions include an A/D data transient capture mode with pre. Two independent 512 MB banks of DDR2 SDRAM are available to the signal processing FPGA. triggering and SDRAM memory control. Model 7156 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces. SX50T. SX50T or FX70T LVDS PCI-X GTP RF XFORMR RF XFORMR RF XFORMR A/D Clock Bus TIMING BUS GENERATOR Clock/ Sync / Gate / PPS ADS5474 400 MHz 14-bit A/D ADS5474 400 MHz 14-bit A/D 800 MHz 16-bit D/A 800 MHz 16-bit D/A D/A Clock Bus DIGITAL UPCONVERTER 14 Control/ Status 14 32 VCXO To All Sections PROCESSING FPGA VIRTEX –5: LX50T. data packing. and two Virtex-5 FPGAs. All memory banks can be easily accessed through the PCI-X interface. gating. A high-performance IP core wideband DDC may be factory-installed in the processing FPGA. and Virtex-5 FPGAs Model 7156 PMC/XMC ● Model 7256 6U cPCI ● Model 7356 3U cPCI ● Model 7656 PCI Model 7756 Full-length PCIe ● Model 7856 Half-length PCIe ● Model 5356 3U VPX RF XFORMR ple Clock In PPS In L Gate / Trig L Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS Timing Bus 32 DDR 2 32 DDR 2 16 FLASH 32 MB INTERFACE FPGA VIRTEX-5: LX30T. 3U cPCI (Model 7356). Versions of the 7156 are also available as a PCIe fulllength board (Models 7756 and 7756D dual density).

A 5-channel DMA controller and 64 bit / 100 MHz PCI-X interface assures efficient transfers to and from the module.Software Defined Radio Handbook Products Dual SDR Transceivers with 500 MHz A/D. The first FPGA is used primarily for signal processing while the second one is dedicated to board interfaces. PCI board (Model 7658). Built-in memory functions include an A/D data transient capture mode with pre. connect the FPGA to the XMC connector with two 2. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. and two Virtex-5 FPGAs. 3U cPCI (Model 7358). The Model 7158 architecture includes two Virtex-5 FPGAs.5 GB/sec data links to the carrier board. • One Park Way. A dual bus system timing generator allows for sample clock synchronization to an external system reference. a digital upconverter with two 800 MHz 16-bit D/As. etc. and Virtex-5 FPGAs Model 7158 PMC/XMC ● Model 7258 6U cPCI ● Model 7358 3U cPCI ● Model 7658 PCI Model 7758 Full-length PCIe ● Model 7858 Half-length PCIe ● Model 5358 3U VPX RF In RF XFORMR Sample Clock / Reference Clock In PPS In TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS Timing Bus 32 DDR 2 SDRAM 256 MB 32 DDR 2 SDRAM 256 MB 16 FLASH 32 MB INTERFACE FPGA VIRTEX-5: LX30T.com • http://www. LX155T.) Figure 43 Model 7158 is a dual high-speed data converter suitable for connection as the HF or IF input of a communications system. enabling factory installed functions such as data multiplexing. 6U cPCI (Models 7258 and 7258D dual density). All of the board’s data and control paths are accessible by the FPGAs. Versions of the 7158 are also available as a PCIe fulllength board (Models 7758 and 7758D dual density). Two 4X switched serial ports implemented with the Xilinx Rocket I/O interfaces. Two independent 256 MB banks of DDR2 SDRAM are available to the signal processing FPGA. PCIe half-length board (Model 7858). SX50T or FX70T LVDS PCI-X GTP RF In RF XFORMR RF Out RF XFORMR RF Out RF XFORMR A/D Clock Bus TIMING BUS GENERATOR Clock/ Sync / Gate / PPS D/A Clock Bus ADS5463 500 MHz 12-bit A/D ADS5463 500 MHz 12-bit A/D 800 MHz 16-bit D/A 800 MHz 16-bit D/A DIGITAL UPCONVERTER 14 Control/ Status 14 32 VCXO To All Sections PROCESSING FPGA VIRTEX –5: LX50T.x (PCIe.com . SX95T or FX100T LVDS GTP GTP GTP 64 4X GTP 4X 4X Model 7158 PMC/XMC P4 PMC FPGA I/O 32 32 PCI-X BUS (64 Bits 100 MHz) 64 4X P15 XMC VITA 42. gating. multichannel applications where the relative phases must be preserved. All these products have similar features. triggering and SDRAM memory control. 32 Pentek.pentek. data packing. Model 7158 uses the popular PMC format and supports the VITA 42 XMC standard for switched fabric interfaces.and post-triggering. 800 MHz D/A. Upper Saddle River. It features two 500 MHz 12-bit A/Ds. Inc. It also supports large. channel selection. SX50T. All memory banks can be easily accessed through the PCI-X interface. and 3U VPX (Model 5358).

The Model 71620 is compatible with the VITA 42. triggering and memory control. 2. and four banks of memory. LX240T. gating. 2-Channel 800 MHz D/A. PCIe interface.x Figure 44 Model 71620 is the first member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. The Model 71620 Cobalt architecture features a Virtex-6 FPGA. DUC. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions. DDR3 SDRAM or QDRII+ SRAM memory. It includes three 200 MHz. The FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. SX95T or SX475T LVDS GTP GTP GTP 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 16 16 FLASH 32 MB 40 x8 x4 x4 Model 71620 XMC QDRII+ SRAM 8 MB Optional memory configurations DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB P14 PMC FPGA I/O P15 XMC PCIe P16 XMC VITA 42. channel selection. A multichannel.XMC RF In RF XFORMR TIMING BUS GENERATOR Clock / Sync / Gate / PPS 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D RF Out RF XFORMR RF Out RF XFORMR Sample Clk / Reference Clk In A/D Clock Bus 800 MHz 16-BIT D/A 800 MHz 16-BIT D/A TTL Gate / Trig TTL Sync / PPS Sample Clk Sync Clk Gate A Gate B Sync PPS Timing Bus DIGITAL UPCONVERTER D/A Clock Bus 14 To All Sections 14 14 32 VCXO Control / Status FPGA VIRTEX-6 LX130T. enabling factory installed functions including data multiplexing. 2 bus specifications. users can install their own custom IP for data processing. and synchronization circuits. DDR3 SDRAM. it is suitable for connection to HF or IF ports of a communications and radar system. Inc. gate. Multiple 71620’s can be driven from the LVPECL bus master. All of the board’s data and control paths are accessible by the FPGA.0 XMC format and supports PCI Express Gen. two 800 MHz 16-bit D/As. Upper Saddle River. LX365T.com • http://www. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. The FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters.com . LX240T. or SX475T. SX315T. data packing. 16-bit A/Ds. one DUC. high-speed data converter. programmable LVDS I/O and clock. or as combination of two banks of each type of memory. 33 Pentek. LX365T. Supported FPGAs include: Virtex-6 LX130T.Software Defined Radio Handbook Products 3-Channel 200 MHz A/D. In addition to the built-in functions. Virtex-6 FPGA Model 71620 . The Model 71620 includes an industry-standard interface fully compliant with PCI Express Gen. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.pentek. • One Park Way. supporting synchronous sampling and sync functions across all connected boards. The 71620 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM.

etc. 2. A multichannel. 34 Pentek. The 71660 architecture supports up to four independent memory banks which can be configured with all QDRII+ SRAM. The FPGA serves as a control and status engine with data and programming interfaces to each of the on-board resources including the data converters. LX240T. PCIe interface. The Model 71660 includes an industry-standard interface fully compliant with PCI Express Gen. channel selection. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. LX240T. 2 bus specifications. Inc. All of the board’s data and control paths are accessible by the FPGA. Upper Saddle River. LX365T. Multiple 71660’s can be driven from the LVPECL bus master.Software Defined Radio Handbook Products 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA Model 71660 . enabling factory installed functions including data multiplexing. and four banks of memory. Supported FPGAs include: Virtex-6 LX130T. DDR3 SDRAM. PCIe. data packing. it is suitable for connection to HF or IF ports of a communications and radar system.XMC RF In RF XFORMR TIMING BUS GENERATOR Clock / Sync / Gate / PPS 16 To All Sections RF In RF XFORMR 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D RF In RF XFORMR 200 MHz 16-BIT A/D Sample Clk / Reference Clk In Gate / Trigger Sync / PPS TTL Gate / Trig TTL Sync / PPS Sample Clk Aux Clk Gate A Gate B Sync / PPS A Sync / PPS B Timing Bus A/D Clock / Sync Bus 200 MHz 16-BIT A/D 16 16 16 VCXO Control / Status FPGA VIRTEX-6 LX130T. high-speed data converter. LX365T. SX95T or SX475T LVDS GTX GTX GTX 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 QDRII+ SRAM 8 MB 16 16 FLASH 32 MB 40 x8 x4 x4 Model 71660 XMC FPGA I/O PCIe VITA 42.pentek. programmable LVDS I/O and clock.com . gating. The x8 lane interface includes multiple DMA controllers for efficient transfers to and from the module. users can install their own custom IP for data processing. The FPGA can be populated with a variety of different FPGAs to match the specific requirements of the processing task. SX315T. and synchronization circuits. supporting synchronous sampling and sync functions across all connected boards. gate.) P16 XMC Optional memory configurations P14 PMC DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB P15 XMC Figure 45 Model 71660 is a member of the CobaltTM family of high performance XMC modules based on the Xilinx Virtex-6 FPGA. or SX475T.x (Aurora. or as combination of two banks of each type of memory. The Model 71660 Cobalt architecture features a Virtex-6 FPGA. • One Park Way. In addition to the built-in functions. The Model 71660 is compatible with the VITA 42. DDR3 SDRAM or QDRII+ SRAM memory.0 XMC format and supports PCI Express Gen. It includes four 200 MHz 16-bit A/Ds.com • http://www. triggering and memory control. Pentek GateFlow FPGA Design Kits facilitate integration of user-created IP with the factory shipped functions.

The sampling clock can be supplied either from a front panel input or from an internal crystal oscillator. A VMEbus interface supports configuration of the FPGAs over the backplane and also provides data and control paths for runtime applications. This Model is available in commercial as well as conduction-cooled versions.Software Defined Radio Handbook Products 215 MHz. digital filters. 35 Pentek. 12-bit A/D with Wideband DDCs .com .pentek.25 GB/sec 32 32 FPDP-II Out B Slot 1 FPDP-II Out D Slot 2 32 32 32 32 FPDP-II Out A Slot 1 FPDP-II Out C Slot 2 128k FIFO 128k FIFO Ext Clock In 50 ohms XTAL OSC 16 128k FIFO 128k FIFO 16 VME Slave Interface VMEbus 4x Switched Serial Fabric 1. Capable of digitizing input signal bandwidths up to 100 MHz. memory boards or storage devices. Data from the A/D converter flows into two Xilinx Virtex-II Pro FPGAs where optional signal processing functions can be performed. and digital delay lines for tracking receivers. one for each FPGA. it is ideal for wideband applications including radar and spread spectrum communication systems. A VXS interface is optionally available. support large memory applications such as swinging buffers.25 GB/sec Model 6821 VXS Switched Backplane Figure 46 The Model 6821 is a 6U single slot board with the AD9430 12-bit. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 215 MHz A/D converter. Two 128 MB SDRAMs.VME/VXS Model 6821-422 RF Input 50 ohms 215 MHz 12-Bit A/D AD9430 Fs LVDS I/O 128 MB SDRAM 16 MB FLASH Fs/2 Front Panel LVDS Timing Bus CLOCK. DSP algorithms. Either two or four FPDP-II ports connect the FPGAs to external digital destinations such as processor boards. none are included on the board. Instead. The size of the FPGAs can range from the XC2VP20 to the XC2VP50. the Pentek GateFlow IP Core 422 Ultra Wideband Digital Downconverter can be factory- installed in one or both of the FPGAs to perform this function. Because the sampling rate is well beyond conventional ASIC digital downconverters. • One Park Way. SYNC & TRIGGER GENERATOR 128 MB SDRAM 16 MB FLASH Control and Status To All Sections 32 XILINX VIRTEX-II PRO FPGA XC2VP50 32 XILINX VIRTEX-II PRO FPGA XC2VP50 64 LVDS I/O 32 32 4x Switched Serial Fabric 1. Upper Saddle River.com • http://www. Inc.

NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. and digital delay lines for tracking receivers. A VXS interface is optionally available. DSP algorithms. The size of the FPGAs can range from the XC2VP20 to the XC2VP50.pentek. the Pentek GateFlow IP Core 422 Ultra Wideband Digital Downconverter can be factory- installed in one or both of the FPGAs to perform this function.25 GB/sec 32 32 FPDP-II Out B Slot 1 FPDP-II Out D Slot 2 32 32 32 32 FPDP-II Out A Slot 1 FPDP-II Out C Slot 2 215 MHz 12-Bit A/D AD9430 Fs LVDS Clock & Sync Bus 128k FIFO 128k FIFO Ext Clock In 50 ohms XTAL OSC 16 16 XILINX VIRTEX-II PRO FPGA XC2VP50 128k FIFO 128k FIFO VME Slave Interface VMEbus 4x Switched Serial Fabric 1.com • http://www. A VMEbus interface supports configuration of the FPGAs over the backplane and also provides data and control paths for runtime applications. • One Park Way. none are included on the board. The sampling clock can be supplied either from a front panel input or from an internal crystal oscillator. Data from each A/D converter flows into a Xilinx Virtex-II Pro FPGA where optional signal processing functions can be performed. digital filters.VME/VXS Model 6822-422 RF Input 50 ohms LVDS I/O 128 MB SDRAM 16 MB FLASH 32 XILINX VIRTEX-II PRO FPGA XC2VP50 64 CLOCK GEN Fs/2 RF Input 50 ohms 215 MHz 12-Bit A/D AD9430 128 MB SDRAM 16 MB FLASH Control and Status To All Sections 32 LVDS I/O 32 32 4x Switched Serial Fabric 1. Because the sampling rate is well beyond conventional ASIC digital downconverters. support large memory applications such as swinging buffers.com . Instead.Software Defined Radio Handbook Products Dual 215 MHz. Upper Saddle River. memory boards or storage devices. it is ideal for wideband applications including radar and spread spectrum communication systems. This Model is available in commercial as well as conduction-cooled versions. 12-bit A/D with Wideband DDCs . Two 128 MB SDRAMs. Inc. Capable of digitizing input signal bandwidths up to 100 MHz. Either two or four FPDP-II ports connect the FPGAs to external digital destinations such as processor boards. 36 Pentek.25 GB/sec Model 6822 VXS Switched Backplane Figure 47 The Model 6822 is a 6U single slot VME board with two AD9430 12-bit 215 MHz A/D converters. one for each FPGA.

Software Defined Radio Handbook Products Dual 2 GHz.25 GB/SEC 4x SWITCHED SERIAL FABRIC 1. Because the sampling rate is well beyond conventional digital downconverters. 10-bit A/D with Very High-Speed DDCs . memory boards or storage devices. support large memory applications such as swinging buffers. it is ideal for extremely wideband applications including radar and spread spectrum communication systems.com • http://www. The sampling clock is an externally supplied sinusoidal clock at a frequency from 200 MHz to 2 GHz. Upper Saddle River. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. none are included on the board.VME/VXS Model 6826 RF INPUT 50 OHMS 2 GHz 10-Bit A/D AT84AS008 Fs 10 4:1 DEMUX AT84CS001 40 2:1 DEMUX V4 FPGA 512 MB DDR RAM 80 32 128k FIFO 128k FIFO 16 MB FLASH 128k FIFO 128k FIFO 32 FPDP-II 400 MB/sec FPDP-II 400 MB/sec EXT CLOCK INPUT XTAL OSC 64 Fs/4 Fs Fs/8 512 MB DDR RAM 64 XILINX VIRTEX-II PRO FPGA XC2VP70 32 32 16 RF INPUT 50 OHMS 2 GHz 10-Bit A/D AT84AS008 10 4:1 DEMUX AT84CS001 Fs/4 40 2:1 DEMUX V4 FPGA Fs/8 80 32 32 FPDP-II 400 MB/sec FPDP-II 400 MB/sec 32 Fs/8 IN Fs/8 OUT FPGA SYNC IN GATE A IN GATE B IN GATE TRIGGER & SYNC 32 VME SLAVE INTERFACE VMEbus 4x SWITCHED SERIAL FABRIC 1. This Model is also available in a single-channel version and in commercial as well as conduction-cooled versions. digital filters. Data from each of the two A/D converters flows into an innovative dual-stage demultiplexer that packs groups of eight data samples into 80-bit words for delivery to the Xilinx Virtex-II Pro XC2VP70 FPGA at one eighth the sampling frequency.pentek. Inc. • One Park Way.25 GB/SEC Model 6826 VXS SWITCHED BACKPLANE Figure 48 The Model 6826 is a 6U single slot VME board with two Atmel AT84AS008 10-bit 2 GHz A/D converters. and digital delay lines for tracking receivers. DSP algorithms. Capable of digitizing input signals at sampling rates up to 2 GHz. Two 512 MB or 1 GB SDRAMs. The customer will be able to incorporate this core into the Model 6826 by ordering it as a factory-installed option. A VMEbus interface supports configuration of the FPGA over the backplane and also provides data and control paths for runtime applications. A very high-speed digital downconverter IP core for the Model 6826 can be developed for a customer who is interested in one. Either two or four FPDP-II ports connect the FPGA to external digital destinations such as processor boards. This advanced circuit features the Atmel AT84CS001 demultiplexer which represents a significant improvement over previous technology. A VXS interface is optionally available. 37 Pentek.com .

com • http://www. Upper Saddle River. A programmable delay allows the user to make timing adjustments on the gate and sync signals before they are sent to an LVPECL buffer. Gate and sync signals can come from an external source. Sets of input and output cables for two to eight boards are available from Pentek. triggering and gating functions. Up to eight boards can be synchronized using the 6890.Software Defined Radio Handbook Products 2. The second output of the 1:2 power splitter feeds a 1:2 buffer which distributes the clock signal to both the gate and synchronization circuits. Sync and Gate Distribution Board synchronizes multiple Pentek I/O boards within a system.VME Front Panel Gate Enable Front Panel Gate Input TTL / PECL SELECTOR GATE CONTROL TTL / PECL SELECTOR PROG DELAY BUFFER 1:2 REG MUX 2:1 LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Gate Ch 6 Output Ch 7 Ch 8 Front Panel Clock Input POWER SPLITTER 1:2 POWER SPLITTER BUFFER 1:2 1:8 Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Clock Ch 6 Output Ch 7 Ch 8 Front Panel Sync Enable Front Panel Sync Input TTL / PECL SELECTOR SYNC CONTROL TTL / PECL SELECTOR REG PROG DELAY BUFFER 1:2 MUX 2:1 LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Front Ch 4 Panel Ch 5 Sync Ch 6 Output Ch 7 Ch 8 Model 6890 VME Figure 49 Model 6890 Clock. Clock signals are applied from an external source such as a high performance sine wave generator. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Sync and Gate Distribution Board Model 6890 . The 6890 features separate inputs for gate/trigger and sync signals with user-selectable polarity. A bank of eight MMCX connectors at the output of each buffer delivers signals to up to eight boards. Separate Gate Enable and Sync Enable inputs allow the user to enable or disable these circuits using an external signal. or from one supported board set to act as the master. 38 Pentek. A 2:1 multiplexer in each circuit allows the gate/ trigger and sync signals to be registered with the input clock signal before output. each receiving a common clock of up to 2. The first output of this power splitter sends the clock signal to a 1:8 splitter for distribution to up to eight boards using SMA connectors.2 GHz and uses a 1:2 power splitter to distribute the clock. Each of these inputs can be TTL or LVPECL. • One Park Way.com . DSP and software radio applications.2 GHz Clock. The 6890 accepts clock input at +10 dBm to +14 dBm with a frequency range from 800 MHz to 2. if desired. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition.2 GHz along with timing signals that can be used for synchronizing.pentek. Inc.

com . triggering and gating functions. each receiving a common clock up to 500 MHz along with timing signals that can be used for synchronizing. compatible with a wide range of Pentek I/O modules. Two additional inputs are provided for separate gate and sync enable signals. up to eight 6891’s can be linked together to provide synchronization for up to 64 I/O modules producing systems with up to 256 channels. 39 Pentek.pentek. Clock signals can be applied from an external source such as a high performance sine-wave generator. This clock is used to register all sync and gate/trigger signals as well as providing a sample clock to all connected I/O modules. Up to eight modules can be synchronized using the 6891. one for gate or trigger and one for a synchronization signal. simplifying system design. Model 6891 accepts three TTL input signals from external sources: one for clock.VME Gate Clock Sync Gate to Sync Bus Outputs 2-8 Sync Bus Output 1 Front Panel Gate Enable Front Panel GateInput GATE CONTROL MUX 2:1 PROG DELAY BUFFER 1:2 REG MUX 2:1 GATE LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Clock Sync Gate Clock Sync Gate Clock Sync Sync Bus Output 2 Sync Bus Output 3 Front Panel Clock Input MUX 2:1 CLOCK LVPECL BUFFER 1:10 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Sync Bus Output 4 to Sync Bus Outputs 2-8 Gate Clock Sync Gate Sync Bus Output 5 Front Panel Sync Enable Front Panel Sync Input SYNC CONTROL MUX 2:1 PROG DELAY BUFFER 1:2 REG MUX 2:1 SYNC LVPECL BUFFER 1:8 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Clock Sync Gate to Sync Bus Outputs 2-8 Sync Bus Output 6 Clock Sync Gate Clock Sync Sync Bus Output 7 Gate Sync Bus Input Clock Sync Sync Bus Output 8 Figure 50 Model 6891 VME Model 6891 System Synchronizer and Distribution Board synchronizes multiple Pentek I/O modules within a system. sync and gate/trigger signals. a Sync Bus connector accepts LVPECL inputs from any compatible Pentek products to drive the clock. The 6891 accepts clock input at +10 dBm to +14 dBm with a frequency range from 1 kHz to 800 MHz. For larger systems. The 6891 provides eight front panel Sync Bus output connectors. It enables synchronous sampling and timing for a wide range of multichannel high-speed data acquisition. Gate/trigger and sync signals can come from an external system source. Alternately.com • http://www. Inc. • One Park Way. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The Sync Bus is distributed through ribbon cables. DSP and software radio applications. A programmable delay allows the user to make timing adjustments on the gate and sync signals before they are sent to an LVPECL buffer for output through the Sync Bus connectors.Software Defined Radio Handbook Products System Synchronizer and Distribution Board Model 6891 . Upper Saddle River.

• One Park Way. thereby allowing any combination of output signals from the four CDC7005s. the settings return to the saved configuration upon power up. Upper Saddle River.pentek. Each quad VCXO is programmed to generate one of four base frequencies. 8 or 16. This supports a single identical clock to all eight outputs or five different clocks to various outputs. 2. Each output can be independently enabled to drive each bus. Each CDC7005 generates five output signals. Eight front panel SMC connectors supply synthesized clock outputs driven from the five clock buses. or 3U cPCI (Model 7390). This reference is a 5 or 10 MHz signal supplied to a front panel SMC connector.com . The 7190 is equipped with a non-volatile memory. Each signal is independently programmable as a submultiple of the associated VCXO base frequency using divisors of 1. 6U cPCI (Models 7290 and 7290D dual density). 40 Pentek. The five clock output signals from each of the four CDC7005s are joined into five clock buses. as shown in the block diagram.Software Defined Radio Handbook Products Multifrequency Clock Synthesizer Model 7190 PMC ● Model 7290 6U cPCI ● Model 7390 3U cPCI ● Model 7690 PCI Model 7790 Full-length PCIe ● Model 7890 Half-length PCIe ● Model 5390 3U VPX Reference In QUAD VCXO A CLOCK SYNTHESIZER AND JITTER CLEANER A Clock Out 1 Clock Out 2 Clock Out 3 Clock Out 4 Clock Out 5 QUAD VCXO B CLOCK SYNTHESIZER AND JITTER CLEANER B QUAD VCXO C CLOCK SYNTHESIZER AND JITTER CLEANER C Clock Out 6 Clock Out 7 QUAD VCXO D CLOCK SYNTHESIZER AND JITTER CLEANER D NON-VOLATILE CONFIGURATION MEMORY Clock Out 8 Model 7190 PMC Control PCI INTERFACE 32 PCI BUS (32 Bits / 66 MHz) Figure 51 Model 7190 generates up to eight synthesized clock signals suitable for driving A/D and D/A converters in high-performance real-time data acquisition and software radio systems. 4. numerous other combinations are possible. 3U VPX board (Model 5390). Each device includes phase-locking circuitry that locks the frequency of its associated quad VCXO (Voltage Controlled Crystal Oscillator) to the input reference clock. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com • http://www. PCIe half-length board (Model 7890). Once configured. These clocks are synthesized from an input reference signal using phase-locked oscillators. The clocks offer exceptionally low phase noise and jitter to preserve the signal quality of the data converters. Inc. PCI board (Model 7690). Versions of the 7190 are also available as a PCIe fulllength board (Models 7790 and 7790D dual density). The 7190 uses four Texas Instruments CDC7005 clock synthesizer and jitter cleaner devices.

41 Pentek. the master clock can come from a socketed. Inc.75 in.pentek. Model 9190 can drive a maximum of 80 clock and sync cables. Clock LVDS DIFF. Separate cable assemblies extend from openings in the front panel of the 9190 to the front panel clock and sync connectors of each I/O module. DRIVERS Timing Signals LINE RCVRS Multiplexer Switches Clock Ext. DSP and software radio applications. Upper Saddle River. high metal chassis suitable for mounting in a standard 19 in. Clock and timing signals can come from six front panel SMA user inputs or from one I/O module set to act as the timing signal master. 1 To Module No. either above or below the cage holding the I/O modules.) Alternately. Up to 80 I/O modules can be driven from the Model 9190.com • http://www.com . DRIVERS To Module No. 2 Timing Signals LVDS DIFF. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Fewer cables may be installed for smaller systems. RECEIVER Timing Signals To Module No. 40 to the card cage above and 40 to the card cage below. • One Park Way. (In this case.Rack-mount Model 9190 LVDS DIFF. 1. equipment rack. triggering and gating functions. multichannel data acquisition. each receiving a common clock and up to five different timing signals which can be used for synchronizing. user-replaceable crystal oscillator within the Model 9190. 80 OPTIONAL INTERNAL OSCILLATOR LINE DRIVERS Front Panel Output SMA Connectors Figure 52 Model 9190 Clock and Sync Generator synchronizes multiple Pentek I/O modules within a system to provide synchronous sampling and timing for a wide range of high-speed.Software Defined Radio Handbook Products Clock and Sync Generator for I/O Modules Model 9190 . Buffered versions of the clock and five timing signals are available as outputs on the 9190’s front panel SMA connectors. DRIVERS From Module Master Source Front Panel Input SMA Connectors LVDS DIFF. Model 9190 is housed in a line-powered. Mounted between two standard rack-mount card cages. the master I/O module will not be synchronous with the slave modules due to delays through the 9190.

Upper Saddle River. and DUC with two 16-bit 500 MHz D/As. File headers include recording parameter settings and time stamping so that the signal viewer correctly formats and annotates the displayed signals. or as a cost-effective strategy for deploying high-performance. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Multiple RAID levels. • One Park Way. signal processing. Inc. The Pentek RTS 2701 serves equally well as a development platform for advanced research projects and proofof-concept prototypes. ASIC DDC. Included with this instrument is Pentek’s SystemFlow recording software. provide a choice for the required level of redundancy. The core also includes an interpolation filter that expands the interpolation factor of the ASIC DUC. 1. including 0. A high-performance PCI Express SATA RAID controller connects to multiple SATA hard drives to support storage to 4 terabytes and real-time sustained recording rates to 480 MB/sec. The Model 7641-420 combines downconverter and upconverter functions in one PCI module and offers recording and playback capabilities. 42 Pentek. 5. 6. 10 and 50.0 CH 1 OUT 500 MHz 16-BIT D/A DIGITAL UP CONVERTER PS/2 KEYBOARD RAID CONTROLLER PS/2 MOUSE CLK A IN CLK B IN TTL GATE/ TRIG IN SAMPLE CLOCK AND SYNC GENERATOR MODEL 7641-420 TRANSCEIVER AUX VIDEO OUT XTAL OSC A XTAL OSC B CLOCK SYNC BUS DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES RAID ARRAY PENTEK RTS 2701 RECORDER - Figure 53 The Pentek RTS 2701 is a highly scalable recording and playback system in an industrial rack-mount PC server chassis. it utilizes the Model 7641-420 multiband transceiver PCI module with two 14-bit 125 MHz A/Ds.Software Defined Radio Handbook Products Rack-mount Real-Time Recording and Playback Transceiver Instrument Model RTS 2701 CH 1 IN 125 MHz 14-BIT A/D DIGITAL DOWN CONVERTER DIGITAL DOWN CONVERTER DDR SDRAM INTEL SYSTEM DRIVE PROCESSOR GIGABIT ENET CH 2 IN 125 MHz 14-BIT A/D USB 2. multichannel embedded systems.pentek.com • http://www. Built on the Windows XP professional workstation.com . The factory-installed IP core 420 provides a dual wideband DDC and expands the decimation range of the ASIC DDC. and waveform generation.The RTS 2701 uses a native NTFS record/playback file format for easy access by user applications for analysis.

one array for each A/D channel.Software Defined Radio Handbook Products 2-Channel 200 MSample/sec Real-Time Recorder Instrument Model RTS 2703 CH 1 IN 200 MHz 16-BIT A/D INTEL GIGABIT ETHERNET Sample Clock In Ext. The RTS 2703 retains all 16 bits of each A/D sample (2 bytes). recording two signals at up to 200 MSamples/sec. users can install post processing and analysis tools to operate on the recorded data. A total of 4 TB of RAID storage is provided. Multiple RAID levels. forming a powerful dual-channel 4U rack-mount recording system. providing immediate access to the recorded data.com . Reference TIMING BUS GENERATOR Model 7850 DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES VCXO RAID Array PENTEK RTS 2703 Figure 54 The Pentek RTS 2703 is a turnkey recording instrument that allows the user to record and analyze two highbandwidth signals. 2 TB arrays. 43 Pentek. • One Park Way. aggregate recording rates of up to 800 MB/sec. which are organized as two 5-drive. The RTS 2703 records data to the native NTFS file system. provide a choice for the required level of redundancy. Upper Saddle River. Custom configurations can be stored as profiles and later retrieved for easy selection of pre-configured settings with a single click. Inc. including 0. Pentek’s RTS 2703 provides a flexible architecture that can be easily customized to meet user needs. 1 and 5. The RTS 2703 features a Windows- based GUI (graphical user interface) providing a simple means to configure and control the instrument. Included with this instrument is Pentek’s SystemFlow Recording Software. The front end of the RTS 2703 consists of two Pentek Model 7850 PCIe modules each equipped with 200 MHz 16-bit A/D converters. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Reference TIMING BUS GENERATOR PROCESSOR USB Model 7850 SYSTEM DRIVE VCXO PS/2 MOUSE DDR SDRAM PS/2 KEYBOARD Host Processor VIDEO OUT CH 2 IN 200 MHz 16-BIT A/D Sample Clock In Ext.pentek.com • http://www. Built on a Windows XP Professional workstation. The total drive capacity is 4 TB using 10 drives. allowing sustained 2 TB recordings at 200 MSamples/sec simultaneously on each of two channels for over one hour. The RTS 2703 provides sustained.

The RTS 2711 records data to the native NTFS file system. allowing sustained 2 TB recordings at 500 megasamples per second simultaneously on each of two channels for over one hour. Included with this instrument is Pentek’s SystemFlow Recording Software. providing immediate access to the recorded data. Built on a Windows XP Professional workstation. A total of 4 TB of RAID storage is provided. 2-TB arrays. users can install post-processing and analysis tools to operate on the recorded data. 10 and 50 provide a choice for the required level of redundancy.com .pentek. The RTS 2711 features a Windows- based GUI (graphical user interface) that provides a simple means to configure and control the instrument. • One Park Way. Upper Saddle River. Custom configurations can be stored as profiles and later retrieved for easy selection of preconfigured settings with a single click. Reference TIMING BUS GENERATOR Model 7858 DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES VCXO RAID Array PENTEK RTS 2711 Figure 55 The Pentek RTS 2711 is a turnkey recording instrument that allows the user to record and analyze two highbandwidth signals. The front end of the RTS 2711 consists of two Pentek Model 7858 PCIe modules equipped with 500 MHz 12-bit A/D converters. aggregate recording rates of up to 1 GB/sec forming a powerful dual-channel 4U rack-mount recording system. Inc. The RTS 2711 retains the eight most significant bits of each A/D sample to record two signals at 500 megasamples per second. The RTS 2711 provides sustained. 1.Software Defined Radio Handbook Products 2-Channel 500 MSample/sec Real-Time Recorder Instrument Model RTS 2711 CH 1 IN 500 MHz 12-BIT A/D INTEL GIGABIT ETHERNET Sample Clock In Ext. 6. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Multiple RAID levels.com • http://www. The total drive capacity is 4 TB using 16 drives which are organized as two 8-drive. 5. including 0. one for each A/D channel. Pentek’s RTS 2711 provides a flexible architecture that can be easily customized to meet user needs. Reference TIMING BUS GENERATOR PROCESSOR USB Model 7858 SYSTEM DRIVE VCXO PS/2 MOUSE DDR SDRAM PS/2 KEYBOARD Host Processor VIDEO OUT CH 2 IN 500 MHz 12-BIT A/D Sample Clock In Ext. 44 Pentek.

Built on the Windows XP professional workstation. and DUC with two 16-bit 500 MHz D/As. A high-performance PCI Express SATA RAID controller connects to multiple SATA hard drives to support storage to 3 terabytes and real-time sustained recording rates up to 480 MB/sec.com . The core also includes an interpolation filter that expands the interpolation factor of the ASIC DUC. 5. File headers include recording parameter settings and time stamping so that the signal viewer correctly formats and annotates the displayed signals. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. including 0. • One Park Way. The factory-installed IP core 420 provides a dual wideband DDC and expands the decimation range of the ASIC DDC. The Model 7641-420 combines downconverter and upconverter functions in one PCI module and offers real-time recording capabilities. Pentek’s portable recorder instrument provides a flexible architecture that is easily customized to meet special needs. 6. ASIC DDC. the system supports signal bandwidths from 8 kHz to 60MHz. 1. a high-resolution 17-inch LCD monitor and a high-performance SATA RAID controller.pentek. the RTS 2721 uses a native NTFS record/playback file format for easy access by user applications for analysis.com • http://www. Fully supported by Pentek’s SystemFlow recording software. Multiple RAID levels. With its wide range of programmable decimation and interpolation. provide a choice for the required level of redundancy. 10 and 50. Inc.Software Defined Radio Handbook Products Portable Real-Time Recording and Playback Transceiver Instrument Model RTS 2721 CH 1 IN 125 MHz 14-BIT A/D DIGITAL DOWN CONVERTER DIGITAL DOWN CONVERTER GIGABIT ENET HIGH RESOLUTION VIDEO DISPLAY USB 2.0 DDR SDRAM INTEL SYSTEM DRIVE PROCESSOR PS/2 MOUSE PS/2 KEYBOARD CH 2 IN 125 MHz 14-BIT A/D CH 1 OUT 500 MHz 16-BIT D/A DIGITAL UP CONVERTER CLK A IN CLK B IN TTL GATE/ TRIG IN TTL SYNC IN SAMPLE CLOCK AND SYNC GENERATOR MODEL 7641-420 TRANSCEIVER RAID CONTROLLER AUX VIDEO OUT XTAL OSC A XTAL OSC B CLOCK SYNC BUS DATA DRIVES DATA DRIVES DATA DRIVES DATA DRIVES RAID ARRAY PENTEK RTS 2721 RECORDER - Figure 56 The Pentek RTS 2721 is a turnkey real-time recording and playback instrument supplied in a convenient briefcase-size package that weighs just 30 pounds. The RTS 2721 utilizes the Model 7641 multiband transceiver PCI module with two 14-bit 125 MHz A/Ds. signal processing. Upper Saddle River. and waveform generation. it includes a dual-core Xeon processor. 45 Pentek.

record. The viewer can also be used to inspect and analyze the recorded files after the recording is complete. each with intuitive controls and indicators. 46 Pentek.Software Defined Radio Handbook Pentek SystemFlow® Recording Software Model 4990 Recorder Interface Hardware Configuration Interface Signal Viewer Figure 57 The Model 4990 SystemFlow Recording Software provides a rich set of function libraries and tools for controlling all Pentek RTS real-time data acquisition and recording instruments. Upper Saddle River.com • http://www. second and third harmonic components. Advanced signal analysis capabilities include automatic calculators for signal amplitude and frequency. SystemFlow software allows developers to configure and customize system interfaces and behavior.pentek. It is extremely useful for previewing live inputs prior to recording. • One Park Way. play back a recorded signal and monitor board temperatures and voltage levels. The Recorder Interface includes configuration. decimation. the SystemFlow Signal Viewer can often eliminate the need for a separate oscilloscope or spectrum analyzer in the field. panning modes and dual annotated cursors to mark and measure points of interest. control and monitor a recording. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The user can easily move between screens to set configuration parameters. Inc. THD (total harmonic distortion) and SINAD (signal to noise and distortion). All parameters contain limit-checking and integrated help to provide an easier-to-use out-of-the-box experience. With time and frequency zoom. and for monitoring signals as they are being recorded to help ensure successful recording sessions. playback and status screens. as well as gate and trigger information.com . The Hardware Configuration Interface provides entries for input source. The SystemFlow Signal Viewer includes a virtual oscilloscope and spectrum analyzer for signal monitoring in both the time and frequency domains. center frequency.

Cellular phone applications are one of the strongest high-volume applications because of the high density of tightly-packed frequency division multiplexed voice channels. 47 Pentek. DUC. As a general capability. and DSP functions to process wideband signals.com • http://www. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. DDC. Signal intelligence applications and radar benefit from the tight coupling of the A/D. any system requiring a tunable bandpass filter should be considered a candidate for using DDCs. • One Park Way. Take a look at the following application examples to give you some more details. Inc. Direction finding and beamforming are ideal applications for digital receivers because of their excellent channel-to-channel phase and gain matching and consistent delay characteristics.com . Upper Saddle River.pentek.Software Defined Radio Handbook Applications Applications of Software Defined Radio ● ● ● ● ● Tracking Receiver System Software Radio Transceiver System 512-Channel SDR System in a single VMEbus Slot Radar Signal Processing System 8-Channel Beamforming System Software Radio can be used in many different systems: Tracking receivers can be highly automated because software radio allows DSPs to perform the signal identification and analysis functions as well as the adaptable tuning functions.

As shown above. to implement this receiver. across a VXS link. Upper Saddle River. so that frequency-agile or transient signals can be recovered from their onset. Samples from the A/D are sent into a circular buffer within the SDRAM and also to a Pentek FFT IP core implemented in the FPGA. locks onto them and tracks them if their frequency changes. • One Park Way. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. we use the 128 MB SDRAM of the Model 6821 to create a delay memory function. This Model is also available in a dual-channel version as Model 6822. optionally. It then tunes the Pentek DDC core. The spectral peaks of the FFT indicate the frequencies of signals of interest present at the input. The delayed data from the circular buffer feeds the input of this DDC core.Software Defined Radio Handbook Applications Tracking Receiver System 215 MHz 12-Bit A/D AD9430 128 MB SDRAM Delayed Data FPGA FFT IP CORE Peaks Power PC Controller Tuning DDC CORE 32 FIFO 32 16 MB FLASH Model 6821 215 MHz A/D Converter with FPGA System Highlights ● ● ● ● ● ● ● A/D data delivered into SDRAM acts as a digital delay memory A/D data also delivered into a Pentek FFT IP core in FPGA FFT core detects the strength of signals at each analysis frequency PowerPC controller in FPGA sorts signals according to peak strenth PowerPC controller also tunes DDC IP core in FPGA to the strongest signal frequencies Delayed data from SDRAM feeds DDC IP core to compensate for FFT calculation time DDC captures these moving signals in real time and downconverts them to baseband Figure 58 Model 6821 commercial (left) and conduction-cooled version A tracking receiver locates unknown signals. The digital delay can be set to match the time it takes for the FFT energy detection and the processor algorithm for the tuning frequency decision.com • http://www. Inc. accordingly. The dehopped baseband output is delivered to the rest of the system through the FPDP port or. Both Models are available in commercial and conduction-cooled versions. 48 Pentek. also implemented in the FPGA.com . The PowerPC microcontroller of the FPGA digests this frequency list and decides which signals to track.pentek.

NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.com . plus a Virtex-II VP-50 FPGA on each PMC module.com • http://www. Inc.and post-processing I/O front end for sending and receiving data to other system boards connected over the VMEbus or through switched fabric links using the VXS interface. It can also be used as a pre. Ruggedized and conduction-cooled versions of the boards used in this system are available.pentek. Signal processing resources include the Freescale MPC8641 AltiVec processor and an FX60 or FX100 Virtex-4 FPGA on the Model 4207 I/O processor. 100 MHz) SRIO 4x 8x PCI-X Bus 1 (64 Bits. Using these on-board processing resources this powerful system can process analog input data locally and deliver it to the analog outputs. • One Park Way. A total of eight DDC channels are independently tunable across the input band and can deliver downconverted output signal bandwidths from audio up to 2. Four analog outputs can deliver baseband or IF signals with bandwidths up to about 50 MHz and IF center frequencies up to 100 MHz. The system supports four independent D/A channels or two upconverted channels with real or quadrature outputs. Upper Saddle River.5 MHz. 49 Pentek.Software Defined Radio Handbook Applications 4-Channel Software Radio Transceiver System CH A OUT 500 MHz 16bit D/A CH B OUT PENTEK Model 7141 320 MHz DUC 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 PENTEK Model 7141 125 MHz 14bit A/D 125 MHz 14bit A/D CH A IN CH B IN CH A IN CH B IN 125 MHz 14bit A/D 125 MHz 14bit A/D 320 MHz DUC 32 CH A OUT 500 MHz 16bit D/A CH B OUT 32 XILINX VIRTEX-II PRO VP50 4 CLK A DUAL TIMING BUS GEN CLK A CLK B CLOCK & SYNC BUS DUAL TIMING BUS GEN CLK B CLOCK & SYNC BUS XILINX VIRTEX-II PRO VP50 4 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 32 32 64 4 QUAD DDC GC4106 16 MB FLASH QUAD DDC GC4106 16 MB FLASH 4 64 PCI INTERFACE PCI 32 32 PCI INTERFACE PCI P14 PENTEK Model 4207 Front Panel Optical Interface To VME P2 XMC // XMC PMC Site PMC Site MPC8641 Single/Dual Core FLASH 32 MB FLASH 256 MB DDR2 SDRAM 1 GB Dual 1000BT Enet Quad RS232C XMC XMC // PMC Site PMC Site PCI-X Bus 0 (64 Bits. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller Dual 4x 2x Zero Latency Crossbar Switch Dual 4x 2x Dual 4x VME64x 2eSST Gigabit ENET-x Dual 4x Virtex-4 FPGA XC4VFX60 / FX100 FLASH 32 MB DDR2 SDRAM 1 GB 2x VME64x VXS VITA 41 FLASH 128 MB Figure 59 This system accepts four analog inputs from baseband or IF signals with bandwidths up to 50 MHz and IF center frequencies up to 150 MHz.

50 Pentek.Software Defined Radio Handbook Applications 512-Channel Software Radio Recording System in a Single VMEbus Slot CH A OUT 500 MHz 16bit D/A CH B OUT PENTEK Model 7141-430 320 MHz DUC 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 PENTEK Model 7141-430 125 MHz 14bit A/D 125 MHz 14bit A/D CH A IN CH B IN CH A IN CH B IN 125 MHz 14bit A/D 125 MHz 14bit A/D 320 MHz DUC 32 CH A OUT 500 MHz 16bit D/A CH B OUT XILINX VIRTEX-II PRO VP50 IP CORE IP CORE 430 430 256-CHAN 256-CHAN DIGITAL DIGITAL DOWN DOWN CONVERTER CONVERTER 4 4 CLK A DUAL TIMING BUS GEN CLK A CLK B CLOCK & SYNC BUS DUAL TIMING BUS GEN XILINX VIRTEX-II PRO VP50 IP CORE 430 4 4 128 MB SDRAM 128 MB SDRAM 256 MB SDRAM 32 CLK B CLOCK & SYNC BUS 32 32 32 64 QUAD DDC GC4106 16 MB FLASH JBOD Disk Array QUAD DDC GC4106 16 MB FLASH PCI INTERFACE PCI 256-CHAN DIGITAL DOWN CONVERTER 64 PCI INTERFACE 32 32 PCI P14 2x Front Panel Optical Interface PENTEK Model 4207 MPC8641 Single/Dual Core Dual 1000BT Enet Quad RS232C To VME P2 XMC // XMC PMC Site PMC Site FLASH 32 MB FLASH 256 MB DDR2 SDRAM 1 GB XMC XMC // PMC Site PMC Site PCI-X Bus 0 (64 Bits. Either one of the two 14-bit A/D converters operating at 125 MHz sample rate can feed this core producing a range of output bandwidths from 10 kHz to 100 kHz. low cost system. The GUI executes on a Windows host PC connected to the 4207 via Ethernet. 100 MHz) SRIO 8x 8x PCI-X Bus 1 (64 Bits. A SystemFlow signal viewer on the PC allows previewing of data prior to recording and viewing of recorded data files in both time and frequency domains. This system is ideal for downconverting and capturing real time signal data from a very large number of channels in an extremely compact.com . Inc. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller Dual 4x 2x Zero Latency Crossbar Switch Dual 4x 2x Dual 4x VME64x 2eSST Gigabit ENET-x Dual 4x Virtex-4 FPGA XC4VFX60 / FX100 32 MB FLASH FLASH 128 MB 2x DDR2 SDRAM 1 GB VME64x VXS VITA 41 Figure 60 Each Model 7141 PMC features the Xilinx Virtex-II Pro VP50 with a Pentek 256-Channel Digital Downconverter (DDC) IP Core 430. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Pentek’s SystemFlow® software presents an intuitive graphical user interface (GUI) to set up the DDC channels and recording mode. Upper Saddle River. Each channel provides independent tuning frequency with a global decimation from 1024 to 9984. A dual 4-Gbit Fibre Channel copper interface allows wideband A/D data or DDC outputs from all 512 channels to be recorded in real time to a RAID or JBOD disk array at aggregate rates up to 640 MB/sec. Files can be moved between the Fibre Channel disk and the PC over Ethernet.com • http://www. • One Park Way.pentek.

data may be processed by custom user-defined algorithms before it is sent across the VXS interface for recording and off-line processing. The D/A output can also be used for countermeasures. takes advantage of a Model 7142-428 multichannel transceiver with an installed FPGA core that includes four wideband DDCs and an interpolation filter. the DDCs deliver complex (I & Q) data to the Model 4207 processor board. This is especially useful for a jet or UAV to prevent it from getting shot down. After frequency translation and filtering. The upconverter with the interpolation filter can be used to generate arbitrary radar pulse waveforms that can be used to calibrate the system. Here.com • http://www. Filter 320 MHz DUC 32 500 MHz 16bit D/A 256 MB SDRAM 256 MB SDRAM 256 MB SDRAM 32 32 CLK A CLOCK & SYNC BUS 96 64 VIRTEX-4 FPGA FX60 or FX100 I/O PCI XMC 16 MB FLASH 32 PENTEK Model 4207 XMC // XMC PMC Site PMC Site Front Panel Optical Interface P14 Dual 4x Dual 1000BT Enet Quad RS232C MPC8641 Single/Dual Core FLASH 32 MB FLASH 256 MB DDR2 SDRAM 1 GB XMC XMC // PMC Site PMC Site To VME P2 PCI-X Bus 0 (64 Bits. speed.pentek.Software Defined Radio Handbook Applications Radar Signal Processing System PENTEK Model 7142-428 CH A IN CH B IN 125 MHz 14bit A/D 125 MHz 14bit A/D 125 MHz 14bit A/D 125 MHz 14bit A/D DUAL TIMING BUS GEN CH A OUT CH C IN CH D IN XILINX VIRTEX-4 FPGA With 4-chan. The channelized system shown above. and spoofing deceives radars by making it seem that the target is a different shape. Factory-installed IP cores such as pulse compression and FFT are available and can be factory installed in this FPGA. The optional GateFlow FPGA Design Kit can be used to install custom algorithms in the Model 4207 FPGA. Inc. such as jamming or spoofing. 51 Pentek.com . Upper Saddle River. DDC & Interpol. • One Park Way. Note that one more PMC/XMC site is available for installation of an additional module. the A/D converters can digitize baseband signals with bandwidths up to 50 MHz. Operating at sampling rates up to 125 MHz. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller Dual 4x 2x Zero Latency Crossbar Switch Dual 4x 2x Dual 4x VME64x 2eSST Gigabit ENET-x Dual 4x Virtex-4 FPGA XC4VFX60 / FX100 32 MB FLASH 2x DDR2 SDRAM 1 GB VME64x VXS VITA 41 FLASH 128 MB Figure 61 Radar is well served by high-speed A/D converters and wideband digital downconverters. Jamming blasts energy that disables radars. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. direction or distance by using DSP techniques. 100 MHz) SRIO 4x 8x PCI-X Bus 1 (64 Bits.

Inc. The eight-channel combined sum is delivered through the crossbar switch into the Aurora engine implemented in the Virtex-4 FPGA of the 4207 processor board. signals from the second four channels of the right 7153 are summed in the right summation block. The PCI-X interface in this FPGA presents the SDRAM memory as a mapped resource appearing on the processor PCI-X bus 1.25 GBytes/sec. The Power PC reads the data from the FPGA DDR2 memory across the PCI-X bus.com • http://www.com . Signals from the first four channels of the left 7153 module are summed in the left summation block.pentek. 100 MHz) Front Panel Serial I/O 2x 4x 4x SRIO 4x 8x PCI .X Bus 1 (64 Bits. creates the beamformed pattern display and presents it via its front panel gigabit Ethernet port to an attached PC for display. Upper Saddle River. Each red 4x link is capable of data rates up to 1. 100 MHz) PCIe to PCIe to PCI-X Bridge PCI-X Bridge Dual 4 Gb Fibre Dual 4 Gbit ChannelChannel Fibre Controller 4x 4x 4x Virtex-4 FPGA 4x Gigabit ENET-x 2x Dual 4x VXS VITA 41 Aurora Engine FLASH 32 MB FLASH 128 MB 2x Zero Latency Crossbar Switch VME64x 2eSST PCI-X Interface DDR2 SDRAM 1 GB VME64x Figure 62 Two Model 7153 Beamformer PMC/XMC modules are installed on the Model 4207 I/O Processor board. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. The left 4-channel sum is connected through the crossbar switch and delivered into the summation input port of the right XMC module. 52 Pentek. Joining the two 7153 modules is a clock/sync cable that synchronizes the DDCs and guarantees synchronous sampling across all eight channels. This Aurora engine decodes the stream and delivers it to a designated block in the DDR2 memory attached to the FPGA. • One Park Way.Software Defined Radio Handbook Applications 8-Channel Beamforming System PENTEK Model 7153 DDC 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D DUAL TIMING BUS GEN Clock/Sync Cable CH A IN CH B IN CH A IN CH B IN PENTEK Model 7153 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D 200 MHz 16-bit A/D DUAL TIMING BUS GEN DDC SUMMATION BLOCK DDC DDC S CH C IN CH D IN CH C IN SUMMATION BLOCK DDC DDC S CH D IN DDC DDC VIRTEX-5 FPGAs PCI-X Aurora P15 CLK A CLOCK & SYNC BUS CLK A CLOCK & SYNC BUS VIRTEX-5 FPGAs PCI-X Aurora PENTEK Model 4207 MPC8641 Single/Dual Core FLASH 32 MB FLASH 256 MB Dual 1000BT Enet P15 To VME P2 XMC // XMC PMC Site PMC Site XMC XMC // PMC Site PMC Site DDR2 SDRAM 1 GB PCI-X Bus 0 (64 Bits. The eight signals to be beamformed are connected to the eight analog inputs of these modules. The summation output from the left XMC module is delivered using the Aurora 4x link into one port of the crossbar switch. The Aurora summation from the left four channels is combined with the right four channels and then delivered to the crossbar switch from the right summation output port.

stable filter characteristics Excellent dynamic range Figure 64 Pentek offers a comprehensive array of VMEbus DSP boards featuring the AltiVec G4 PowerPC from Freescale and the TMS320C6000 family of processor products from Texas Instruments. be sure to visit Pentek’s comprehensive website regularly. As we have seen. The Models 4205 and 4207 I/O processor boards feature the latest G4 PowerPCs. Full software development tools are available for workstations running Windows and Linux with many different development system configurations available. facilitates system requirement changes and performance upgrades. Dual. This also means excellent channel-to-channel matching and no need for calibration. 53 Pentek. On-board processor densities range from one to eight DSPs with many different memory and interface options available. FPGA technology allows one to incorporate custom algorithms right at the front end of these systems.com . The Models 4294 and 4295 processor boards feature four MPC74xx G4 PowerPC processors utilizing the AltiVec vector processor capable of delivering several GFLOPS of processing power. To summarize. the ability of the system designer to freely choose the most appropriate DSP processor for each software radio application. Since the entire circuitry uses digital signal processing. With the addition of FPGA technology. Furthermore. the characteristics are precise. predictable. Upper Saddle River. We stand ready to discuss your requirements and help you configure a complete SDR system. PCI and cPCI I/O peripherals VME/VXS platforms Figure 63 Benefits of Software Defined Radio: • • • • • • Reduction of DSP processing demands Very fast tuning Fast bandwidth selection Zero frequency drift and error Precise. DSP boards and data acquisition products. we restate the major benefits: SDRs can dramatically reduce the DSP requirements for systems which need to process signals contained within a certain frequency band of a wideband signal. there are inherently many benefits and advantages to when using SDR. The Models 4292 and 4293 processor boards feature the Texas Instruments latest TMS320C6000 family of fixed-point DSPs that represent a 10-fold increase in processing power over previous designs.com • http://www.Software Defined Radio Handbook Summary DSP Boards for VMEbus SDR Benefits • • • • • Freescale Altivec G4 PowerPC Texas Instruments C6000 DSPs Single. For all the latest information about Pentek SDRs. and will not drift with time. alignment or maintenance. The fast tuning of the digital local oscillator and the easy bandwidth selection in the decimating digital filter and interpolation filter make the SDR easy to control. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Inc. We hope that this introduction has been informative. Once again. accept PMC mezzanines and include built-in Fibre Channel interfaces. PMC/XMC. temperature or aging.pentek. Quad and Octal Processor versions PMC. dramatic increases in system density have been coupled with a significantly lower cost per channel. • One Park Way.

256-Channel Narrowband DDC .PCI Multiband Transceiver with Virtex-II Pro FPGA .6U cPCI Multiband Transceiver with Virtex-II Pro FPGA .PMC/XMC Multiband Transceiver with Virtex-II Pro FPGA . Dual Wideband DDC and Interpolation Filter .PCI Transceiver w.PMC/XMC Transceiver w. 256-Channel Narrowband DDC .6U cPCI Multiband Transceiver with Virtex-II Pro FPGA .3U VPX Transceiver w.PCI Transceiver w.3U cPCI Transceiver w.PMC/XMC Multiband Transceiver with Virtex-II Pro FPGA . Dual Wideband DDC and Interpolation .3U cPCI Transceiver w.3U cPCI Multiband Transceiver with Virtex-II Pro FPGA .3U VPX Page 19 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 25 25 25 25 25 25 25 More links on the next page ➤ 54 Pentek.PMC/XMC Transceiver w.com • http://www. Dual Wideband DDC and Interpolation Filter .6U cPCI Multiband Receiver . Dual Wideband DDC and Interpolation Filter . 256-Channel Narrowband DDC . 256-Channel Narrowband DDC .PMC/XMC Conduction-cooled Multiband Transceiver with Virtex-II FPGA .Software Defined Radio Handbook The following links provide you with additional information about the Pentek products presented in this handbook: just click on the Model number.PMC/XMC Transceiver w.6U cPCI Transceiver w.3U cPCI Transceiver w.Half-length PCIe Transceiver w. Dual Wideband DDC and Interpolation Filter . Dual Wideband DDC and Interpolation Filter .PCI Multiband Transceiver with Virtex-II Pro FPGA .com .Half-length PCIe Transceiver w.pentek.Full-length PCIe Transceiver w.PMC Multiband Receiver . Dual Wideband DDC and Interpolation .6U cPCI Transceiver w. NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek.PMC/XMC Transceiver w.PCI Transceiver w. Dual Wideband DDC and Interpolation Filter .Full-length PCIe Multiband Transceiver with Virtex-II Pro FPGA . • One Park Way.3U VPX Transceiver w. Dual Wideband DDC and Interpolation Filter .6U cPCI Transceiver w. 256-Channel Narrowband DDC . 256-Channel Narrowband DDC . 256-Channel Narrowband DDC .Full-length PCIe Transceiver w. Dual Wideband DDC and Interpolation . 256-Channel Narrowband DDC .3U cPCI Transceiver w.3U cPCI Multiband Receiver . 256-Channel Narrowband DDC . 256-Channel Narrowband DDC .6U cPCI Transceiver w.3U VPX Multiband Transceiver with Virtex-II Pro FPGA . Inc. Upper Saddle River.PCI Transceiver w. 256-Channel Narrowband DDC .PCI Multiband Receiver .3U cPCI Multiband Transceiver with Virtex-II Pro FPGA . Links are also provided to other handbooks or brochures that may be of interest in your software radio development projects. Dual Wideband DDC and Interpolation Filter .Half-length PCIe Multiband Transceiver with Virtex-II Pro FPGA . Model 7131 7231 7331 7631A 5331 7140 7240 7340 7640 7140-420 7240-420 7340-420 7640-420 7140-430 7240-430 7340-430 7640-430 7141 7141-703 7241 7341 7641 7741 7841 5341 7141-420 7241-420 7341-420 7641-420 7741-420 7841-420 5341-420 7141-430 7241-430 7341-430 7641-430 7741-430 7841-430 5341-430 Description Multiband Receiver .

16-bit A/D . 16-bit A/D .3U cPCI Dual SDR Transceiver. Virtex-5 FPGAs .Half-length PCIe Multichannel Transceiver w. 16-bit A/D . Virtex-5 FPGAs . Virtex-5 FPGAs .PCI 32-Channel DDC with Quad 200 MHz. Virtex-5 FPGAs .Full-length PCIe 4-Channel DDC with Quad 200 MHz. 16-bit A/D . 16-bit A/D .3U VPX 32-Channel DDC with Quad 200 MHz. Virtex-5 FPGAs . 400 MHz A/D.Half-length PCIe 256-Channel DDC with Quad 200 MHz.6U cPCI 256-Channel DDC with Quad 200 MHz. 800 MHz D/A.3U cPCI 256-Channel DDC with Quad 200 MHz. • One Park Way.3U VPX 4-Channel DDC with Quad 200 MHz. 800 MHz D/A. 400 MHz A/D. 16-bit A/D .PMC/XMC 4-Channel DDC with Quad 200 MHz. 16-bit A/D . Four Multiband DDCs and Interpolation Filter .PCI 4-Channel DDC with Quad 200 MHz.3U VPX 256-Channel DDC with Quad 200 MHz.3U VPX Multichannel Transceiver w. 16-bit A/D .PCI Multichannel Transceiver w. 400 MHz A/D. Four Multiband DDCs and Interpolation Filter.3U VPX More links on the next page ➤ 55 Pentek. 400 MHz A/D.PMC/XMC Multichannel Transceiver with Virtex-4 FPGAs .Half-length PCIe Multichannel Transceiver with Virtex-4 FPGAs .6U cPCI Dual SDR Transceiver. 16-bit A/D .6U cPCI Multichannel Transceiver w. 16-bit A/D . 800 MHz D/A.Full-length PCIe Multichannel Transceiver w.PMC/XMC Multichannel Transceiver w. 16-bit A/D . 400 MHz A/D. 800 MHz D/A. 400 MHz A/D. 16-bit A/D .PCI 256-Channel DDC with Quad 200 MHz. 16-bit A/D .3U cPCI Multichannel Transceiver with Virtex-4 FPGAs . 16-bit A/D .6U cPCI 32-Channel DDC with Quad 200 MHz. 16-bit A/D .PMC/XMC Dual SDR Transceiver.3U cPCI 4-Channel DDC with Quad 200 MHz.6U cPCI 4-Channel DDC with Quad 200 MHz. Four Multiband DDCs and Interpolation Filter.PCI Multichannel Transceiver with Virtex-4 FPGAs .6U cPCI Multichannel Transceiver with Virtex-4 FPGAs . 16-bit A/D . 400 MHz A/D.Full-length PCIe Dual SDR Transceiver.PMC 32-Channel DDC with Quad 200 MHz.Half-length PCIe 4-Channel DDC with Quad 200 MHz.PMC 256-Channel DDC with Quad 200 MHz. 16-bit A/D .Full-length PCIe 256-Channel DDC with Quad 200 MHz.Full-length PCIe Multichannel Transceiver with Virtex-4 FPGAs . NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. Inc. Virtex-5 FPGAs .Half-length PCIe 32-Channel DDC with Quad 200 MHz.com . 16-bit A/D .3U cPCI Multichannel Transceiver w. Virtex-5 FPGAs . 16-bit A/D .3U cPCI 32-Channel DDC with Quad 200 MHz. Four Multiband DDCs and Interpolation Filter. 800 MHz D/A. Four Multiband DDCs and Interpolation Filter.pentek.PCI Dual SDR Transceiver. 16-bit A/D . 16-bit A/D .Full-length PCIe 32-Channel DDC with Quad 200 MHz. 800 MHz D/A. 800 MHz D/A. Upper Saddle River. Four Multiband DDCs and Interpolation Filter.Software Defined Radio Handbook Model 7142 7242 7342 7642 7742 7842 5342 7142-428 7242-428 7342-428 7642-428 7742-428 7842-428 5342-428 7151 7251 7351 7651 7751 7851 5351 7152 7252 7352 7652 7752 7852 5352 7153 7253 7353 7653 7753 7853 5353 7156 7256 7356 7656 7756 7856 5356 Description Page 26 26 26 26 26 26 26 27 27 27 27 27 27 27 28 28 28 28 28 28 28 29 29 29 29 29 29 29 30 30 30 30 30 30 30 31 31 31 31 31 31 31 Multichannel Transceiver with Virtex-4 FPGAs .Half-length PCIe Dual SDR Transceiver.com • http://www. Four Multiband DDCs and Interpolation Filter.3U VPX Dual SDR Transceiver.

500 MHz A/D. Virtex-5 FPGAs .3U VPX 3-Channel 200 MHz A/D. 800 MHz D/A. • One Park Way.6U cPCI Dual SDR Transceiver. 12-bit A/D with Wideband DDCs .3U cPCI Multifrequency Clock Synthesizer . 800 MHz D/A.VME System Synchronizer and Distribution Board . 500 MHz A/D. 800 MHz D/A. DUC.com . 500 MHz A/D.Software Defined Radio Handbook Model 7158 7258 7358 7658 7758 7858 5358 71620 71660 6821-422 6822-422 6826 6890 6891 7190 7290 7390 7690 7790 7890 5390 9190 RTS 2701 RTS 2703 RTS 2711 RTS 2721 4990 4207 Description Dual SDR Transceiver.VME/VXS Page 32 32 32 32 32 32 32 33 34 35 36 37 38 39 40 40 40 40 40 40 40 41 42 43 44 45 46 49 Handbooks and Brochures Click here Click here Click here Click here Putting FPGAs to Work in Software Radio Systems Critical Techniques for High-Speed A/D Converters in Real-Time Systems Handbook High-Speed Switched Serial Fabrics Improve System Design Handbook Model 4207 PowerPC and FPGA I/O Processor Board Brochure 56 Pentek. Virtex-5 FPGAs .Half-length PCIe Dual SDR Transceiver. 800 MHz D/A. Virtex-6 FPGA 4-Channel 200 MHz 16-bit A/D with Virtex-6 FPGA .VME/VXS 2.3U cPCI Dual SDR Transceiver.com • http://www. 800 MHz D/A.PCI Dual SDR Transceiver.Half-length PCIe Multifrequency Clock Synthesizer . Sync and Gate Distribution Board .6U cPCI Multifrequency Clock Synthesizer .PMC/XMC Dual SDR Transceiver. 500 MHz A/D.PCI Multifrequency Clock Synthesizer . Virtex-5 FPGAs .VME Multifrequency Clock Synthesizer . Virtex-5 FPGAs . 500 MHz A/D.pentek. 12-bit A/D with Wideband DDCs . 800 MHz D/A. Inc.2 GHz Clock.XMC 215 MHz. 2-Channel 800 MHz D/A. Virtex-5 FPGAs .Full-length PCIe Multifrequency Clock Synthesizer . 500 MHz A/D.VME/VXS Dual 2 GHz 10-bit A/D .VME/VXS Dual 215 MHz. 800 MHz D/A.Full-length PCIe Dual SDR Transceiver. Upper Saddle River. Virtex-5 FPGAs .3U VPX Clock and Sync Generator for I/O Modules Rack-Mount Real-Time Recording and Playback Transceiver System 2-Channel 200 MSample/sec Real-Time Recorder Instrument 2-Channel 500 MSample/sec Real-Time Recorder Instrument Portable Real-Time Recording and Playback Transceiver Instrument Pentek SystemFlow Recording Software PowerPC and FPGA I/O Processor .PMC Multifrequency Clock Synthesizer . NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: info@pentek. 500 MHz A/D. Virtex-5 FPGAs .

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