i

AN FPGA IMPLEMENTATION OF ALAMOUTI’S TRANSMIT DIVERSITY TECHNIQUE

PUSHPAMALAR MUKILAN

A project report submitted in partial fulfillment of the requirements for the award of the degree of Master of Engineering (Electrical –Electronics & Telecommunication)

FACULTY OF ELECTRICAL ENGINEERING UNIVERSITI TEKNOLOGI MALAYSIA

MAY 2008

iii

DEDICATION

Especially dedicated to Pathi, Amma, Uncle, Mama, Auntie, Periakka, Maran Chinnakka, Revathy, Anna, Ganesh, Sara, Siva, Darshu, Aadish & In loving memory of Appa and Tata

iv

ACKNOWLEDGEMENT

In ashirvat of Lord Ganesh who made all possible.

Prior to begin with my project, I would like to pay my attribute to my supervisor, Dr. Sharifah Kamilah Yusof for her abundant advice, guidance and wise suggestions. She has helped me tremendously by keeping me on the right track and constantly motivating me to do the very best that I could possibly achieve. I would like to express my heartfelt gratitude to my dearest family for their support, encouragement and optimism. They have always given me words of wisdom and I am extremely overwhelmed with gratitude for all the graciousness. And lastly, I would like to thank all my friends for the guidance and advice. Thank You.

They are particularly attractive because they do not require any additional transmission bandwidth. However. Therefore considerable effort has been invested in making more efficient use of it. there are limits to growth. This project aims to present the Xilinx/Altera FPGA implementation of a multiple antenna wireless communications system based on Alamouti’s transmit diversity scheme [1]. . There is demand for ever faster wireless communications as this will allow for new applications such as wireless broadband Internet access. which is modeled to establish an end-to-end link over real wireless channels to form a complete multiple antenna wireless communications system. Multi-Antenna transmission schemes. The implementation demonstrates this space-time code in a baseband system with two transmit and just one antenna at the receiver with the encoding and decoding algorithms using Verilog Hardware Description Language (HDL).v ABSTRACT Wireless communications have grown tremendously over the last decade. and unlike traditional systems use multipath interference to their benefit. and associated coding techniques have been proposed as a way to fulfill the demand for increased capacity and the performance of wireless communication systems. Using the spectrum more efficiently caters for the ever increasing demand for faster communications since more bits per second can be transmitted using the same bandwidth. using multiple antennas at the transmitter and/or receiver. wireless LAN and mobile telephones have been the main reasons for the growth. Alamouti’s transmit diversity scheme is a space-time block code with support for two transmit antennas and an arbitrary number of receive antennas. and the radio spectrum used for wireless communications is a finite resource.

vi ABSTRAK Wayarles LAN dan telefon mudahalih adalah penyumbang utama yang menyebabkan sistem komunikasi wayales berkembang dengan pesatnya pada dekad yang lalu. Masih terdapat permintaan untuk sistem komunikasi wayarles yang laju. Skema penghantaran berbilang antenna menggunakan beberapa antenna pada penghantar dan penerima. Walaubagaimanapun. Projek ini bertujuan untuk melaksanakan sistem komunikasi wayarles berbilang antena yang berasaskan teknik kepelbagaian penghantaran Alamouti [1] dengan menggunakan perkakasan Altera/Xilinx FPGA. usaha telah diambil untuk mempergunakan spektrum radio ini dengan lebih cekap. Skema kepelbagaian penghantar Alamouti kod blok ruangmasa ini boleh menampung dua antena penghantar dan bilangan antena penerima yang sembarangan. perkembangan ini mempunyai hadnya kerana spektrum radio yang digunakan untuk komunikasi wayarles ini adalah terhad. beberapa teknik pengekodan yang tidak memerlukan penambahan lebarjalur telah dicadangkan. Oleh itu. . Pelaksanaan teknik ini akan mendemonstrasikan kod blok ruangmasa dalam sistem jalurdasar yang menggunakan dua antena penghantar dan satu antena penerima yang masing-masing melakukan pengekodan dan penyahkodan algoritma menggunakan “Verilog Hardware Description Language (HDL)”. yang membenarkan aplikasi baru seperti wayarles capaian Internet jalur lebar. Bagi memenuhi permintaan dalam peningkatan kapasiti dan prestasi sistem komunikasi wayarles. Sistem ini dimodelkan untuk mengadakan suatu perhubungan hujung-ke-hujung menggunakan saluran wayarles untuk membentuk satu sistem komunikasi wayarles yang lengkap. Ini akan memenuhi peningkatan permintaan untuk sistem komunikasi yang laju kerana lebih banyak bit /s dapat dihantar dengan menggunakan lebarjalur yang sama.

3 Scope of project 1 2 3 .2 Objective 1.vii TABLE OF CONTENTS CHAPTER TITLE PAGE DECLARATION DEDICATION ACKNOWLEDGEMENT ABSTRACT ABSTRAK TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF APPENDICES ii iii iv v vi vii xi xii xiv 1 INTRODUCTION 1.1 Project Backgorund 1.

1 Theoretical Background 2.7.1 Two-Branch Transmit Diversity with One Receiver 2.7.7 Altera Tools 3.6 Implementation Flow 3.4.4.1.8.3 The Maximum Likelihood Decision Rule 7 12 13 14 15 16 18 18 3 FIELD PROGRAMMABLE GATE ARRAYS (FPGA) 3.2 Modelling the Wireless Communications Channel 2.3 Multi Antenna System 2.1 Literature Review 3.5 FPGA design and programming 3.8 Xilinx Tools 3.2 The Combining Scheme 2.4 Alamouti’s code 2.8.2 History of FPGA 3.viii 2 ALAMOUTI’S TRANSMIT DIVERSITY TECHNIQUE 2.1 The Encoding and Transmission Sequence 2.1 Xilinx Spartan-3AN FPGA 3.3 Applications of FPGA 3.4 FPGA Architecture 3.1.2 Design Implementation Altera Quartus II 3.2 Design Implementation using Xilinx ISE 20 21 22 23 25 26 26 26 28 30 30 32 .4.1.1 Altera DE2 FPGA Board 3.4.

3.5 Gray Coding 34 36 37 42 49 52 53 54 57 58 59 63 5 RESULT AND CONCLUSION 5.2 QPSK Demodulator 4.2 QPSK Modulator 4.ix 4 HARDWARE DESIGN ANALYSIS 4.1 Alamouti decoder 4.1 Recommendations 70 REFERENCES 71 .3 Alamouti Receiver 4.2.4 Channel Modelling 4.2 Alamouti Transmitter 4.2.2.2.4 Transmitter (TX) 4.3.3 Alamouti Encoder 4.3.1 Introduction 4.1 Result and Conclusion 68 6 RECOMMENDATIONS ON FUTURE WORK 6.1 Serial-to-Parallel Converter 4.3 Receiver (RX) 4.

x Appendices 73 .

1 4.3 4. TITLE PAGE 2.4 4.6 Input-Output pin description of serial-t-parallel module Shift-register sample sequence Pin description of qpsk_const Pin description of ctrl_unit_qpsk Pin description of the Alamouti encoder Pin description of the Alamouti in decoder 38 40 45 47 51 56 .xi LIST OF TABLES TABLE NO.5 4.1 Encoding and transmission sequence for the two-branch transmit diversity scheme 17 4.2 4.

9 4.7 4.1 4.1 1.1 2.1 3.3 4.4 2.3 General block diagram of Alamouti transmitter General block diagram of Alamouti Receiver Alamouti Transmitter Alamouti Receiver Simplified example of multipath fading Potential communications channels in 2x1 system Two-branch transmit diversity scheme with two transmitter and one receiver 3 4 5 5 8 14 16 3.6 4. TITLE PAGE 1.5 4.xii LIST OF FIGURES FIGURE NO.3 1.2 4.2 3.11 Altera and Xilinx implementation flow Altera DE2 FPGA Status utility window The Spartan 3AN FPGA Platform Xilinx Integrated Software Environment (ISE) Block Diagram of Alamouti Transmitter Serial-to-parallel Internal part of the Serial-to-Parallel Converter Four-bit Shift Register Output waveform of Shift_reg Double clock Output waveform of Double_clk Output waveform of serial2parallel converter QPSK modulator Output waveform of QPSK_mod Internal part of QPSK_mod 27 28 30 31 32 36 37 39 39 40 41 41 42 43 43 44 .2 1.4 4.5 4.2 2.4 3.10 4.8 4.3 3.

21 4.22 4.14 4.36 4.16 4.43 QPSK control unit Output waveform of ctrl_unit_qpsk Transmit data process module Output waveform of TX_data_process Alamouti encoder Output waveform of the Alamouti encoder Transmitter module Output waveform of Transmitter Block Diagram of Alamouti Receiver Alamouti decoder Output waveform of rx_control_add Output waveform of rx_control_minus QPSK demodulator Output waveform of QPSK_demod Alamouti receiver Output waveform of Alamouti receiver Channel_capture module Capture module Output waveform of capture module Channel module Output waveform of Channel_capture module Gray_gen Output waveform of gray_gen Parallel2serial Output waveform of Parallel2serial Gen module Output waveform of gen module Output waveform of transmission (TRX) 47 47 48 49 50 50 52 52 53 54 55 55 57 57 58 59 60 61 61 62 62 63 64 65 66 66 67 67 44 45 46 46 .20 4.29 4.28 4.15 QPSK constellation QPSK constellation mapping Output waveform of QPSK_const ASM chart that represents the state diagram for the ctrl_unit_qpsk 4.38 4.37 4.39 4.35 4.27 4.13 4.23 4.xiii 4.33 4.17 4.12 4.32 4.40 4.24 4.26 4.30 4.34 4.25 4.19 4.41 4.42 4.31 4.18 4.

12 A.5 A.14 A.7 A.18 A.10 A.xiv LIST OF APPENDIX APPENDIX TITLE PAGE A A.13 A.9 A.20 HARDWARE DESIGN SOURCE CODE serial2parallel shift_reg_4 double_clk qpsk_mod qpsk_const ctrl_unit_qpsk tx_data_process encoder TX rx_control_add rx_control_minus qpsk_demod RX capture channel channel_capture gray_gen parallel2serial gen ALAMOUTI_TRX 74 77 79 80 82 84 85 87 89 91 95 99 100 102 105 108 110 112 114 115 .19 A.2 A.15 A.6 A.4 A.17 A.11 A.3 A.16 A.8 A.1 A.

xv B B.3 IMPLEMENTATION REPORT Transmitter (TX) Receiver (RX) Tramsmission TX-RX 119 120 121 .2 B.1 B.

and associated coding techniques could increase the performance of wireless communication systems [6] The diversity gain is responsible for the improvement in quality of communication link and can be obtained through the use of STC (Space Time Coding) [12] which spreads the transmitted symbols over the space and time dimensions. This growth has been fueled by the widespread popularity of mobile telephones and wireless computer networking. It has been proposed that using multiple transmit and receive antennas. and the radio spectrum used for wireless communications is a finite resource. . Using the spectrum more efficiently caters for the ever increasing demand for faster communications since more bits per second can be transmitted using the same bandwidth. there are limits to growth. particularly in the area of wireless communication.1 Project Background In recent years the telecommunications industry has experienced phenomenal growth. A major research focus in this area has been the use of multiple antennas for transmitting and receiving instead of the traditional single antenna [1].1 CHAPTER 1 INTRODUCTION 1. Therefore considerable effort has been invested in making more efficient use of it. However.

space-time OFDM (ST-OFDM) and space-frequency OFDM (SF-OFDM) are also based on the transmit diversity scheme proposed by Alamouti as described in [4]. While they provided substantial gains in a wireless communications system. It could also be argued that Alamouti’s transmit diversity scheme was the first example of a space-time code which requires only linear processing at the receiver. In it the transmission necessarily occurs through two antennas. Siavash M. these trellis. An important characteristic of the Alamouti’s scheme is its simplicity. Alamouti included a generalization of his scheme to an arbitrary number of receive antenna [2].2 Objectives This project aims to present the Altera and Xilinx FPGA implementation of a multiple antenna wireless communications system based on Alamouti’s transmit diversity scheme [1. Two transmit diversity scheme with OFDM. in the codification and in the decodification. 1. with one or more antennas in the reception. which establishes an end-to-end link over real wireless channels to form a complete multiple antenna wireless communications system with certain assumptions made. Previous space-time coding schemes used trellis based processing [5].based coding schemes were much more complicated to implement than the scheme proposed by Alamouti. The design requires providing the RTL code (Verilog .2 The first excellent work in the space-time coding subject was presented by Alamouti. [1]. The simplest case of Alamouti’s scheme utilizes two transmit antennas and one receive antenna. Alamouti’s scheme already is consolidated in the scientific area and is used in the standards of the UMTS WCDMA of third generation [5]. making of this as ideal candidate for real-world implementation. The implementation demonstrates the space-time code in a system with two transmit and just one antenna at the receiver with the encoding and decoding algorithms.

Figure 1. the project consists of two major parts which are the transmitter and receiver system.M. this design does not include the complete flow of the transmission as shown in Figure 1. The design is then verified and debugged and finally implemented on Altera and Xilinx FPGAs using the Quartus II tool and ISE tool respectively. Alamouti [1].3 Scope of project At the initial stage.1 and Figure 1.2. However. Hardware Description Language (HDL) is used to design.1: General block diagram of Alamouti transmitter . The design of the transmitter and receiver are based on the encoding and decoding algorithm of the S. mapping and place and routing the design onto the FPGA. timing recovery and carrier recovery on the receiver. 1.3 ’01) for the encoding and decoding algorithm. The implementation process involves the process of translating. The design is implemented on both Altera and Xilinx FPGA boards.1 and Figure 1. The general block diagram of Alamouti transmitter and receiver are shown in Figure 1. Verilog. model and verify the system. The Alamouti transmitter and receiver design in this work excludes pulse shaping and upsampling and upconversion on the transmitter and the downconversion and downsampling.2 respectively.

signals form the Alamouti transmitter had been connected directly via cable to the Alamouti receiver. The Alamouti transmitter consist of the serialto-parallel converter. Alamouti receiver and the channel modeling respectively. we have included another part in the design which is the channel modeling. Therefore. Therefore. To fulfill this requirement. The behavior of each of these blocks’s are explained in detail in Chapter 4. .2: General block diagram of Alamouti Receiver Due to the absence of these parts. the behavior of these signals which are connected directly to the receiver needed to be modeled as if they had been through the real wireless channels. the overall project consists of two major parts and an intermediate part which are the Alamouti transmitter. the signals cannot be transmitted from the transmitter to the receiver over real wireless channels. However. QPSK modulator and the Alamouti encoder and the Alamouti receiver consist of Alamouti decoder and QPSK demodulator. Figure 1.4 Figure 1.4 shows the design of Alamouti transmitter and receiver respectively. The Alamouti transmitter and receiver are made up of three circuits and two circuits respectively.3 and Figure 1. to perform the transmission in order for the implementation onto the FPGA.

two consecutive symbols. the design does not require a channel estimator and Maximum Likelihood (ML) part of design. Also assume that there is no noise and interference present at the receiver. And as mentioned earlier. the input bits are modulated into symbols of real (Q) and imaginary (I) and these numbers are integers. Also.3: Alamouti Transmitter Figure 1. in the design the transmitted signal is directly connected and the channel modeling modifies the transmitted signal to behave as it should as if the signal had been transmitted over real wireless environment before being received at the receiver. .5 Figure 1. The receiver is also assumed to have the knowledge of the channel experienced by the signal. Due to this.4: Alamouti Receiver There are several assumption made for the designed system. The first assumption is that the fading and inputs are constant for the duration of the encoding process.

the recommendations on what could be extended in terms of the design for the enhancement of the project in terms of design. part by part on the RTL and the implementation onto the FPGA. Chapter 2 describes the overview and the literature of the Alamouti’s transmit diversity technique. Chapter 3 describes the overview and the literature of an FPGA designs.6 The remainder of the thesis is organized as follows. implementation and the RTL code. . Finally Chapter 6. Chapter 4 discusses the actual design of the in detail. Chapter 5 discusses the obtained results of both implementation report of Altera/ Xilinx and concludes the project.

Yet the services must remain affordable for widespread market acceptance. Fortunately. Figure 2.1 Theoretical Background The next-generation wireless systems are required to have better quality and coverage. Inevitably. the economy of scale may allow more complex base stations.1 illustrates a simplified example of multipath fading. The fundamental phenomenon which makes reliable wireless transmission difficult is time-varying multipath fading [1]. In fact. however. . be more power and bandwidth efficient. it appears that base station complexity may be the only plausible trade space for achieving the requirements of next generation wireless systems.7 CHAPTER 2 ALAMOUTI’S TRANSMIT DIVERSITY TECHNIQUE 2. the new pocket communicators must remain relatively simple. and be deployed in diverse environments.

the most effective technique to mitigate multipath fading in a wireless channel is transmitter power control. without additional power or any sacrifice in bandwidth. If channel conditions as experienced by the receiver on one side of the link are known at the transmitter on the other side. Achieving the same in a multipath fading environment. The improvement in SNR may not be achieved by higher transmit power or additional bandwidth.noise ratio (SNR).8 Figure 2. Theoretically. coaxial cable. may require up to 10 dB improvement in SNR. however. as it is contrary to the requirements of next generation systems. using typical modulation and coding schemes. It is this phenomenon which makes tether less transmission a challenge when compared to fiber. Increasing the quality or reducing the effective error rate in a multipath fading channel is extremely difficult. line-of-sight microwave or even satellite transmissions. .or 2-dB higher signal to. In additive white Gaussian noise (AWGN). It is therefore crucial to effectively combat or reduce the effect of fading at both the remote units and the base stations.1 Simplified example of multipath fading. reducing the effective bit error rate (BER) from 10-2 to 10-3 may require only 1.

antenna diversity is a practical. the channel information has to be fed back from the receiver to the transmitter. it must increase its power by that same level. The same holds for spread spectrum. For instance. It is therefore more economical to add equipment to base stations rather than the remote units. In most scattering environments. The use of multiple antennas and radio frequency (RF) chains (or selection and switching circuits) makes the remote units larger and more expensive. effective and. together with error correction coding. Other effective techniques are time and frequency diversity. which results in throughput degradation and considerable added complexity to both the transmitter and the receiver. For this reason. Moreover. diversity techniques have almost exclusively been applied to base stations to improve their reception quality. and power of the remote units.9 the transmitter can predistort the signal in order to overcome the effect of the channel at the receiver [3]. For the transmitter to overcome a certain level of fading. time interleaving results in large delays when the channel is slowly varying. size. The major problem is the required transmitter dynamic range. which in most cases is not practical because of radiation power limitations and the size and cost of the amplifiers. However. can provide diversity improvement. . Time interleaving. transmit diversity schemes are very attractive. in some applications there may not be a link to feed back the channel information. Hence. As a result. The major problem with using the receive diversity approach is the cost. a widely applied technique for reducing the effect of multipath fading [1]. hence. A base station often serves hundreds to thousands of remote units. The classical approach is to use multiple antennas at the receiver and perform combining or selection and switching in order to improve the quality of the received signal. The second problem is that the transmitter does not have any knowledge of the channel experienced by the receiver except in systems where the uplink (remote to base) and downlink (base to remote) transmissions are carried over the same frequency. There are two fundamental problems with this approach.

It improves the signal quality at the receiver on one side of the link by simple processing across two transmit antennas on the opposite side [2]. for some applications it may not be practical or cost-effective. not in time or frequency. There are some other interesting approaches for transmit diversity that have been suggested. . The first solution is definitely more economical. Another interesting approach is space–time trellis coding. This scheme is very effective. A similar scheme was suggested by Seshadri and Winters [13] for a single base station in which copies of the same symbol are transmitted through multiple antennas at different times. A delay diversity scheme was proposed by Wittneben [14] for base station simulcasting and later. independently.10 one antenna and one transmit chain may be added to a base station to improve the reception quality of all the remote units in that base station’s coverage area [1]. The scheme requires no bandwidth expansion. Therefore. A maximum likelihood sequence estimator (MLSE) or a minimum mean squared error (MMSE) equalizer is then used to resolve multipath distortion and obtain diversity gain. where symbols are encoded according to the antennas through which they are simultaneously transmitted and are decoded using a maximum likelihood decoder. introduced in [6]. The cost for this scheme is additional processing. as it combines the benefits of forward error correction (FEC) coding and diversity transmission to provide considerable performance gains [8]. which increases exponentially as a function of bandwidth efficiency (bits/s/Hz) and the required diversity order.M Alamouti is the simple transmit diversity scheme. The technique proposed by S. as redundancy is applied in space across multiple antennas. hence creating an artificial multipath distortion. The alternative is to add more antennas and receivers to all the remote units. This is done without any feedback from the receiver to the transmitter and with small computation complexity.

.11 This transmit diversity scheme can improve the error performance. data rate. Previous space-time coding schemes used trellis based processing [7]. as it effectively reduces the effect of fading at the remote units using multiple transmit antennas at the base stations. these trellis based coding schemes were much more complicated to implement than the scheme proposed by Alamouti. and others later extended his work to include an arbitrary number of transmit antennas [2]. the new scheme is effective in all of the applications where system capacity is limited by multipath fading and. While it provided substantial gains in a wireless communications system. Furthermore. This project is based on implementation of the 2-to-1 scheme. or capacity of wireless communications systems. The simplest case of Alamouti’s scheme utilizes two transmit antennas and one receive antenna. or smaller reuse factors in a multicell environment to increase system capacity. Alamouti included a generalization of his scheme to an arbitrary number of receive antennas. In other words. may be a simple and costeffective way to address the market demands for quality and efficiency without a complete redesign of existing systems. The decreased sensitivity to fading may allow the use of higher level modulation schemes to increase the effective data rate. This lower complexity makes Alamouti’s scheme an ideal candidate for real-world implementation. hence.generation wireless systems. the scheme seems to be a superb candidate for next. As Alamouti’s transmit diversity scheme was the first example of a spacetime code which requires only linear processing at the receiver. The scheme may also be used to increase the range or the coverage area of wireless systems.

12 2.2 Modelling the Wireless Communications Channel

Under certain assumptions the complicated transmission environment can be mathematically modelled by using complex numbers to represent the magnitude and phase change of the transmission channel. The assumption made by this model is that the channel is a so called “flat fading” channel.

Flat fading refers to the frequency response of the channel being “flat”, meaning that all frequencies are subjected to the same attenuation [9]. One of the side effects of flat fading is that there is no Inter-Symbol Interference (ISI).

Even if the actual transmission environment is not flat fading this model can still be used provided the bandwidth of the transmitted signal is small enough. In particular the bandwidth needs to be less than the inverse of the delay spread of the channel for the flat-fading assumption to hold. This means that there should be negligible of ISI.

The use of complex numbers in the model derives from the fact that it is possible to represent a real-valued bandpass signal using complex numbers. It is from this complex number representation that the “in-phase” and “quadrature” components of a signal are derived. The in-phase component is the real part of the complex representation, and the quadrature component is the imaginary part.

For a SISO system this model can reduce the entire transmission environment to a single complex number. The system can then be represented using Equation 2.1, where h is the complex number representing the channel, x is the input signal, and e is a complex number modelling the thermal noise at the receiver.

13

y = hx + e

(2.1)

Similarly MIMO systems can be modelled with Equation 2.2. The variables (H, X and E) have the same meaning as for the SISO case, however instead of the scalar complex numbers in Equation 2.1 the variables are matrices of complex numbers.
Y = HX + E

(2.2)

2.3

Multi Antenna System

One possible way to improve the reliability of wireless communications is to employ diversity. Diversity is the technique of transmitting the same information across multiple channels to achieve higher reliability. It operates on the principle that it is unlikely that all of the channels used to transmit the redundant information will be experiencing deep fading at the same time. Even if one particular channel is unusable the information may still be recovered from the redundant transmission over the other channels. Therefore the overall reliability of the communications system is improved, at the cost of transmitting redundant information.

If multiple antennas are used at the transmitter or receiver there are potentially multiple transmission channels between the transmitter and receiver. In the 2×1 system shown in Figure 2.2 there is the potential for the transmit diversity. For instance the information sent from Tx1 is transmitted across channels h1 and received by Rx. Transmit diversity happens when the same information is sent from multiple transmit antennas. One possible way to achieve this is to code across multiple symbols periods. For instance, at time t antenna Tx1 could transmit the

14 symbol s then at time t+1 antenna Tx2 would transmit the same symbol, s. The Alamouti scheme uses a method similar to this to obtain transmit diversity.

Figure 2.2: Potential communications channels in 2x1 system

2.4

Alamouti’s code

The coding scheme implemented in this project is an Alamouti code which belongs to a class of codes called Space-Time Block Codes (STBC). The SpaceTime refers to coding across space and time. Coding across space by using multiple transmit and receive antennas, and across time by using multiple symbol periods. Like normal block codes the Alamouti code operates on blocks of input bits, however rather than having 1-dimensional code vectors it has 2-dimensional code matrices.

XX H = ∑ s n ⋅ (αI ) n =1 ns 2 (2.3) The code belongs to a special subclass of STBCs known as Orthogonal Space Time Block Codes (OSTBC). the combining scheme at the receiver.4) where ns is the number of symbols. sn is the nth complex symbol. α is an arbitrary constant and (.3. The code matrix is of dimension Nt × tb where Nt is the number of transmit antennas and tb is the number of symbol periods used to transmit a block. The code matrices of OSTBCs satisfy the following constraint. ⎡s X =⎢ 0 ⎣ s1 − s1 * ⎤ s0 * ⎥ ⎦ (2. and the columns are the time (symbol) periods. 2. the decision rule for maximum likelihood detection.)H denotes the Hermitian conjugate.1 Two-Branch Transmit Diversity with One Receiver Figure 2 3 shows the representation of the two branch transmit diversity scheme. The scheme uses two transmit antennas and one receive antenna and may be defined by the following three functions: • • • the encoding and transmission sequence of information symbols at the transmitter. . The code matrix for the Alamouti code is given in Equation 2. So the rows of the matrix represent the transmit antennas.15 STBCs can be described by a code matrix. which defines what is to be sent from the transmit antennas during transmission of a block.4.

3.16 Figure 2. During the next symbol period signal (− s1 ) is transmitted from antenna zero. This sequence is shown in Table 2.3: Two-branch transmit diversity scheme with two transmitter and one receiver 2. The signal transmitted from antenna zero is denoted by s 0 and * from antenna one by s1 . and signal ( s 0 * ) is transmitted from antenna one where * is the complex conjugate operation.1.4.1 The Encoding Sequence At a given symbol period.1. two signals are simultaneously transmitted from the two antennas. . as in the code matrix in equation 2.

may also be done in space and frequency.17 Table 2.6) where r0 and r1 are the received signals at time t and t + T and n0 and n1 are complex random variables representing receiver noise and interference.3 as: * ⎡ s − s1 ⎤ h1 ]⎢ 0 + [e0 * ⎥ ⎣ s1 s0 ⎦ Y = [h0 e1 ] (2. Assuming that fading is constant across two consecutive symbols. it is written as h0 (t ) = h0 (t + T ) = h0 = α 0 e jθ 0 h1 (t ) = h1 (t + T ) = h1 = α 1e jθ 1 (2. however.5) where T is the symbol duration.2 and Equation 2.1.7) . The received signals then expressed as r0 = r (t ) = h0 s0 + h1 s1 + n0 * * r1 = r (t + T ) = − h0 s1 + h1s0 + n1 (2. The encoding. two adjacent carriers may be used (space–frequency coding). The channel is modeled by a complex multiplicative distortion h0 (t ) for transmit antenna zero and h1 (t ) for transmit antenna one. Instead of two adjacent symbol periods. This is also represented in matrix form by combining Equation 2. the encoding is done in space–time coding.1: Encoding and transmission sequence for the two-branch transmit diversity scheme Antenna 0 time t time t + T s0 − s1 * Antenna 1 s1 s0 * In Table 2.

8) 2. The Maximum Likelihood (ML) detection of different symbols is decoupled.4.9) Substituting (10) and (11) into (12) gives ~ = α 2 + α 2 + h* n + h n* s0 0 1 0 0 1 1 ~ = α 2 + α 2 + h* n − h n* s1 0 1 1 0 0 1 ( ( ) ) (2.7 could be modified to be Y = [h0 * ⎡ s − s1 ⎤ h1 ]⎢ 0 * ⎥ ⎣ s1 s0 ⎦ (2.3 builds the following two combined signals that are sent to the maximum likelihood detector: ~ = h* r + h r* s0 0 0 1 1 ~ = h* r − h r* s1 1 0 0 1 (2.3 The Maximum Likelihood Decision Rule These combined signals are then sent to the maximum likelihood detector which.18 However. noise is ignored.1.2 The Combining Scheme The combiner shown in Figure 2.1. In the case of the Alamouti code this means that the two symbols which are coded together can be detected .10) 2. which means that the Equation 2.4. uses the decision rule expressed for QPSK signals and assuming n0 and n1 are Gaussian distributed. for each of the signals s0 and s1 .

. This is the decoupled ML detection that is s s 0 1 0 1 common to all OSTBCs. can be estimated in a maximum likelihood fashion by first combining the received signals according to Equation 2.19 independently at the receiver.10 and then using a standard Maximum Likelihood detector to attempt to recover s and s from ~ and ~ . The transmitted symbols s0 and s1 .

. and programmable interconnects. after the FPGA is manufactured. and XOR. A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer. or more complex combinational functions such as decoders or simple mathematical functions [10]. the logic blocks also include memory elements. somewhat like a one-chip programmable breadboard [11]. which may be simple flip-flops or more complete blocks of memories.1 Literature Review A field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks". Logic blocks can be programmed to perform the function of basic logic gates such as AND. Logic blocks and interconnects can be programmed by the customer or designer. In most FPGAs. to implement any logical function hence the name "field-programmable".20 CHAPTER 3 FIELD PROGRAMMABLE GATE ARRAYS (FPGA) 3.

Another alternative are complex programmable logic devices (CPLDs). while FPGAs typically range from tens of thousands to several million [10]. and draw more power. as they cannot handle as complex a design. invented the field programmable gate array in 1984. This makes them far more flexible (in terms of the range of designs that are practical for implementation within them) but also far more complex to design for.2 History of FPGA The historical roots of FPGAs are in complex programmable logic devices (CPLDs) of the early to mid 1980s. with the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. less flexible versions of their FPGAs which cannot be modified after the design is committed [11]. But their advantages include a shorter time to market. The designs are developed on regular FPGAs and then migrated into a fixed version that more resembles an ASIC.21 FPGAs are usually slower than their application-specific integrated circuit (ASIC) counterparts. on the other hand. CPLDs and FPGAs include a relatively large number of programmable logic elements. and lower non-recurring engineering costs. A CPLD has a somewhat restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. . Ross Freeman. are dominated by interconnect [10]. Vendors can sell cheaper. The primary differences between CPLDs and FPGAs are architectural. I have used the Cyclone II Altera Cyclone II 2C35 FPGA. For this project. ability to re-program in the field to fix bugs. The FPGA architectures. CPLD logic gate densities range from the equivalent of several thousand to tens of thousands of logic gates. DE2 development board and the Xilinx Spartan-3AN FPGA 3. The result of this is less flexibility. Xilinx co-founder.

A related. cryptography. and speed increased. computer vision. medical imaging. FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by their architecture. important difference is that many modern FPGAs support full or partial in-system reconfiguration. speech recognition. As their size. they began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SOC) [11]. ASIC prototyping. capabilities. FPGAs originally began as competitors to CPLDs and competed in a similar space. 3. that of glue logic for PCBs. Some FPGAs have the capability of partial reconfiguration that lets one portion of the device be re-programmed while other portions continue running. bioinformatics.3 Applications of FPGA Applications of FPGAs include digital signal processor DSP. of cryptographic algorithms. allowing their designs to be changed "on the fly" either for system upgrades or for dynamic reconfiguration as a normal part of system operation. computer hardware emulation and a growing range of other areas. One such area is code breaking. in particular brute-force attack. The use of FPGAs for computing tasks is known as reconfigurable computing [11]. . aerospace and defense systems. FPGAs are increasingly used in conventional High Performance Computing applications where computational kernels such as FFT or Convolution are performed on the FPGA instead of a microprocessor.22 Another notable difference between CPLDs and FPGAs is the presence in most FPGAs of higher-level embedded functions (such as adders and multipliers) and embedded memories. softwaredefined radio.

This has driven a new type of processing called reconfigurable computing. The adoption of FPGAs in high performance computing is currently limited by the complexity of FPGA design compared to conventional software and the extremely long turn-around times of current design tools. For example. where 4-8 hours wait is necessary after even minor changes to the source code. Multiple I/O pads may fit into the height of one row or the width of one column in the array. and a flip-flop. manufacturers have started moving to 6input LUTs in their high performance parts. Generally. all the routing channels have the same width (number of wires) [11]. A classic FPGA logic block consists of a 4-input lookup table (LUT). . all of which can compute a result every single clock cycle [11]. claiming increased performance. where time intensive tasks are offloaded from software to FPGAs.4 FPGA Architecture The typical basic architecture consists of an array of configurable logic blocks (CLBs) and routing channels. 3. In recent years.23 The inherent parallelism of the logic resources on the FPGA allows for considerable compute throughput even at a sub-500MHz clock rate. The flexibility of the FPGA allows for even higher performance by trading off precision and range in the number format for an increased number of parallel arithmetic units. as shown below. An application circuit must be mapped into an FPGA with adequate resources. the current (2007) generation of FPGAs can implement around 100 single precision floating point units.

(ii) Logic Block Pin Locations Each input is accessible from one side of the logic block. Generally.24 (i) Typical logic block There is only one output. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. The logic block has four inputs for the LUT and a clock input [11]. . post-silicon validation. longer paths can be constructed [10]. That is. they and other signals are separately managed. Similarly. Since clock signals (and often other high-fanout signals) are normally routed via special-purpose dedicated routing networks in commercial FPGAs. Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. This allows chip companies to validate their design before the chip is produced in the factory. while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block [11]. each wiring segment spans only one logic block before it terminates in a switch box. reducing the time to market. and firmware development. For higher speed interconnect. some FPGA architectures use longer routing lines that span multiple logic blocks. FPGAs are also widely used for systems validation including pre-silicon validation. the FPGA routing is unsegmented. which can be either the registered or the unregistered LUT output. Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. By turning on some of the programmable switches within a switch box. an I/O pad can connect to any one of the wiring segments in the channel adjacent to it.

Then. Languages such as SystemVerilog. a technology-mapped netlist is generated [11]. there exist libraries of predefined complex functions and circuits that have been tested and optimized to . Annapolis Micro Systems. usually performed by the FPGA company's proprietary place-and-route software. To simplify the design of complex systems in FPGAs. Approaches based on standard C or C++ (with libraries or other extensions allowing parallel programming) are found in the Catapult C tools from Mentor Graphics. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route. Common HDLs are VHDL and Verilog. there are moves to raise the abstraction level of the design. Companies such as Cadence. simulation. but are aimed at making existing hardware engineers more productive versus making FPGAs more accessible to existing software engineers. and in the Impulse C tools from Impulse Accelerated Technologies. Inc. place and route results via timing analysis.25 3. and other verification methodologies.5 FPGA design and programming To define the behavior of the FPGA the user provides a hardware description language (HDL) or a schematic design. There is more information on C to HDL and Flow to HDL in their respective articles.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry [10]. In an attempt to reduce the complexity of designing in HDLs. Synopsys and Celoxica are promoting SystemC as a way to combine high level languages with concurrency models to allow faster design cycles for FPGAs than is possible using traditional HDLs [10]. Once the design and validation process is complete. the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA [11]. using an electronic design automation tool. which have been compared to the equivalent of assembly languages. The user will validate the map. and Handel-C (from Celoxica) seek to accomplish the same goal. SystemVHDL.

and are available from FPGA vendors and third-party IP suppliers. In this project. Then. Figure 3.6 Implementation Flow In a typical design flow. from simple circuits to various multimedia projects.26 speed up the design process.1 Altera DE2 FPGA Board The DE2 board has many features that allow the user to implement a wide range of designed circuits. To provide maximum flexibility. an FPGA application developer will simulate the design at multiple stages throughout the design process. the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results.2 shows the block diagram of the DE2 board and the features available in the FPGA [11]. I had used both Altera and Xilinx FPGA’s.7. and Altera Quartus II design software and the Xilinx Integrated Software Environment (ISE) respectively. 3.1 shows the flow of the implementation of both Altera and Xilinx implementation flow. after the synthesis engine has mapped the design to a netlist. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. These predefined circuits are commonly called IP cores. all connections are made through . 3.7 Altera Tools 3. Figure 3.

the FPGA can be configured easily to implement any system design and this is proven when I implemented the design onto this board Figure 3.27 the Cyclone II FPGA device.1: Altera and Xilinx implementation flow. Thus. .

7. Figure 3. The ability to automate the FPGA design process saves time and increases productivity. or by using the Quartus II graphical user interface (GUI) [11]. maps the translated design to device specific .2 Design Implementation Altera Quartus II The Altera Quartus II design software provides a complete. The compilation flow is the sequence and method by which the Quartus II software translates design files. The Quartus II software provides the tools necessary to automate the FPGA design flow.2: Altera DE2 FPGA 3.1 shows a typical implementation flow using FPGA design software. multiplatform design environment that easily adapts to the specific design needs. The Quartus II software allows performing design implementation either by using command-line modular executbles and scripting.28 Figure 3.

3. places and routes the design in the device. . The report window opens automatically when a design is compiled. The Fitter performs additional optimization to improve design's timing and resource usage based on timing constraints. and generates a programming file. and a link to the floorplan view. When the optimized fit is achieved. statistics on the performance of the design. The status utility window shows progress of the current compilation as shown in Figure 3. the Assembler generates the programming files for the design. The Analysis & Synthesis engine optimizes design for the targeted Altera FPGA and maps the design to the device. maps the translated design to device specific elements. and Timing Analyzer. a compilation summary. Assembler. The Timing Analyzer performs a static timing analysis on every path in the design. and shows the design hierarchy. The compilation flow is the sequence and method by which the Quartus II software translates design files. The implementation flow that generates a programming file for FPGA design files exists within the Quartus II software known as the compilation flow [11]. places and routes the design in the device. These functions are performed by the Quartus II Analysis & Synthesis engine.29 elements. and generates a programming file. View the results of a compilation in the Compilation Report window (Processing menu) [11]. This analysis allows to identify critical paths and timing errors necessary to meet the design timing budget or achieve timing closure [11]. The Fitter places and routes the ATOMs created by the Analysis & Synthesis engine onto the selected device. Mapping converts design files into architecture-specific ATOMs that target device resources such as logic elements (LEs) and RAM blocks. Fitter. The programming files contain all placement and routing information for the design and are used to program the target Altera device.

this platform is optimized specifically for non-volatile applications where higher system integration . With the industry's largest user flash memory and enhanced security capabilities.3: Status utility window The Quartus II Programmer allows to use files generated in the compilation flow to program or configure all Altera programmable logic devices and supported configuration devices. select a device family in the Device family list and a device name in the Device Name list. Select the appropriate programming mode in the Mode list of the Programmer window.4 combines the performance and functionality advantages of SRAM-based technology with reliable non-volatile flash technology in a single-chip solution [10]. 3. Open the Programmer by choosing Programmer (Tools menu).30 Figure 3.8. In the Select Device dialog box.1 Xilinx Spartan-3AN FPGA The Spartan3AN FPGA platform as shown in Figure 3.8 Xilinx Tools 3.

4M system gates with up to 576Kb block RAM. multipliers. memory interfacing.31 or security is critical. Figure 3. All devices are pincompatible with Spartan-3A FPGAs. The Spartan-3AN platform is available in five non-volatile device options. cloning. and up to 502 I/Os supporting 26 popular I/O protocol standards. . Configurations range from 50K to 1. digital signal co-processing and embedded control applications [10]. unique FPGA capabilities such as digital clock managers (DCMs). The Spartan-3AN platform offers a range of device security features that safeguard against reverse engineering. 16Mb total embedded flash. and unauthorized overbuilding [10]. In addition. and low power modes make these devices ideal for bridging.4: The Spartan3AN FPGA platform We had used this board for the implementation of the design and it was fairly easy as the Spartan-3AN platform provides flexibility.

ISE as shown in Figure 3. mapping. all of the design entry and design implementation tools can be accessed. routing.32 3. ISE controls all aspects of the design flow [10].8. highest performance.5: Xilinx Integrated Software Environment (ISE) Design Implementation is the process of translating. and generating a BIT file for your design. The Design Implementation tools are embedded in the ISE software for easy access and project management. and most advanced design methodologies. Figure 3.5. Through the Project Navigator interface.2 Design Implementation using Xilinx ISE Xilinx Integrated Software Environment (ISE) is a powerful yet flexible integrated design environment that allows designing Xilinx FPGA devices from start to finish [10]. Design . includes design entry. synthesis and implementation tools delivering the industry's fastest place and route times. placing.

. and must incorporate placement constraints through a User Constraints File (UCF).33 Implementation tools.

1 Introduction In this project. rarely matter at earlier stages in the process. or whether an operation can be completed in parallel with another. The implemented components have all been tested to verify . For this project. all source code of design. Verilog HDL is used to code the Register Transfer Level (RTL)s of the designs.34 CHAPTER 4 HARDWARE DESIGN ANALYSIS 4. All designs of the system have been implemented in Verilog except for the channel estimator and Maximum Likelihood detector as the transmission was not performed over real wireless channels and there were assumptions made as mentioned in Chapter 2. the concept of Alamouti’s transmit diversity technique is implemented in Hardware Description Language (HDL). However details like these are critically important when implementing hardware. Considerations such as how many clock cycles a given operation takes. which are explained in this chapter are attached in Appendix A. Implementing the design in hardware poses some unique challenges.

The Verilog source code can be found in Appendix A. Verilog. . Both the Alamouti transmitter and receiver are made up of several circuits.35 correctness of operation and functionality. Alamouti’s transmit diversity scheme is a space-time block code with support for two transmit antennas and an arbitrary number of receive antennas. for the transmission between the designed transmitter and receiver system. the channel modeling modifies the transmitted signal to behave as it should as if the signal had been transmitted over real wireless environment before being received at the receiver. The project consists of two major parts and an intermediate part which are the Alamouti transmitter. The Alamouti transmitter is made up of three sub-blocks which are the serial-toparallel converter. The transmitted signal is directly connected to the receiver and the intermediate part of the design. there is channel modeling required as the transmission was not done in real wireless environment. receiver and the channel modelling respectively. model and verify the system. Hardware Description Language (HDL) is used to design. However. QPSK modulator and Alamouti encoder while the Alamouti receiver is made up of two sub-block which are the Alamaouti decoder and QPSK demodulator. The design is implemented on both Altera and Xilinx FPGA boards using the Altera Quartus II tool and Xilinx ISE tool respectively. The objective of the project is to present an FPGA (Altera and Xilinx) implementation of a wireless communication system based on Alamouti’s transmit diversity technique [1] using two transmit antennas and one receive antenna. the flow of the design is presented followed by the detail structures of each block in the system. First.

two consecutive symbols. Figure 4. At this point. The output from this block is fed into the QPSK modulator which maps the data and produce symbols of complex numbers. which will be discussed further later in this section. QPSK modulator and Alamouti encoder. The output of the encoding process is two streams of .1 shows the block diagram of Alamouti Transmitter which consist of three sub-blocks. These symbols are passed to the Alamouti encoder which performs the negation of either the real or the imaginary part of the modulated symbol. These sub-blocks are the serial-to-parallel converter. please take note that the there is an assumption that the fading and inputs are constant for the duration of the encoding process.36 4. The Alamouti transmitter design. manipulates these binary bits in such a manner that it follows the Alamouti’s transmit diversity technique to produce outputs at two transmit antenna. Data_in is the serial binary bits input data which are being fed into the Alamouti transmitter design.1: Block Diagram of Alamouti Transmitter First. All these sub-block are made up of several blocks. the Data_in information bits which are being fed in to the design in series are being converted into parallel data by the serial to parallel converter block performing the conversion. There is an assumption that these numbers are integers.2 Alamouti Transmitter Figure 4.

reset input (rst).2. Each stream can be fed to identical transmit chains each driving a separate antenna. It has a serial data input (Data_in). clock input (clk). The schematic of a serial to parallel converter is shown in Figure 4. parallel data outputs (out a. enable input (en). It consists of sending out a block of data parallelly.37 modulated symbols. out c. The pin description of each input/output port is given in Table 4.2: Serial-to-parallel .2.1 Serial-to-Parallel Converter A serial to parallel converter is a typical application of shift register. 4. out d) and a control signal output (Valid 4). Figure 4. out b.1.

. two control units (double_clk) and five D flip-flops (DFF). Output data represented in binary bit.5 shows the resulting output waveform of the shift-register. Each of these sub-blocks plays a different role in order to manipulate input data to perform the conversion of serial data to parallel data of 4 bits. Figure 4. When de-asserted. It is obvious here that the serial-to-parallel converter is made up of a shift register (Shift_reg). Output control signal. rst Input 1 Reset signal that resets the serial to parallel when asserted. 1. the serial to parallel is disabled.4 shows a four-bit shift register that is used to shift its contents one bit-position to the right. 0.1: Input-Output pin description of serial-t-parallel module Signal clk Direction Size Input 1 Description Clock signal that clocks all internal serial to parallel engine component. which is enabled when the conversion is completed. The data bits are loaded into shift register in a serial fashion using the data input. which shows what happens when the signal values at input data during eight consecutive clock cycles are 1.38 Table 4. 1. Output data represented in binary bit. Figure 4. The content of each flip-flop is transferred to the next flip-flop at each positive edge of the clock. Valid_4 Output Figure 4.2. 1. en Input 1 Active-high enable input. 0. Output data represented in binary bit.3 shows the internal part of the serial-to-parallel converter. 0 and 0. Output data represented in binary bit. Data_in Input out_A out_B out_C out_D Output Output Output Output 1 1 1 1 1 1 Input data represented in binary bit stream. An illustration of the transfer is given in Table 4.

39 Figure 4.4: Four-bit Shift Register .3: Internal part of the Serial-to-Parallel Converter Figure 4.

5: Output waveform of Shift_reg Double Clock circuits perform like one bit counter capable of counting from 0 to 1 at each positive edge of clock. 1. 1. 1. which are cascaded.40 Table 4. 0. 0. the second Double Clock .2: Shift-register sample sequence Time Qa Qb Qc Qd First Double Clock t0 t1 t2 t3 t4 t5 t6 t7 t8 1 0 1 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 1 0 Second Double Clock 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 out_a out_b out_c out_d Valid_4 Figure 4. 0.6. If we examine the first Double Clock circuit. it outputs a counting sequence of 0. With the same conditions. There are two Double Clock circuits in the serial-to-parallel converter. 1 and so on with the condition that enable (en) is high (1) and reset (rst) is low (0). The circuit of Double clock is shown in Figure 4.

6: Double_clock Figure 4. 0. it is also fed into another (fifth) D flip-flop. which is control signal that is being used as an indicator of the readiness/ validity of the parallel outputs. 1 and so on. Figure 4. 0. 1. which produces an output Valid_4. At the same time.7 shows the output waveform of the Double_clk. Figure 4. 0. where it sampled shift register output when second Double Clock was counting 1. This means that when the four bit . 0. all output of shift register was controlled by the Double Clock circuits specifically the second Double Clock.7: Output waveform of Double_clk. The four bit outputs of the shift register are fed into four D flip-flops. The parallel outputs are only clocked out at the resulting count 1 output of the second Double Clock which is every 4 consecutive clock cycle. To implement shift register in a serial-to-parallel converter. when the second Double Clock outputs a 1. 0.41 performs counting when the first Double Clock outputs a ‘1’which results the output of this circuit with sequence of 0.

10. . The resulting output waveform of the QPSK modulator is shown in Figure 4.2 QPSK Modulator The QPSK modulator maps the groups of 2 bits of the input into QPSK constellations.11. The modulator circuit consists of two parts which are the QPSK constellation (qpsk_const) and a QPSK control unit (ctrl_unit_qpsk) as shown in Figure 4.2. The following timing simulation in Figure 4. eight bit real part of complex number output (q_out) and eight bit imaginary part of complex number output.9 has reset input (rst).8 shows the output of the serial2parallel converter.42 parallel output and the control signal output Valid_4 will be concurrent.2. two bit input data (inp). Based on the illustration in Table 4. enable input (en). Figure 4. resetn input (rst_n). serial-to-parallel converter is sampled output at t4 and t8. clock input (clk). The QPSK modulator (QPSK_mod) circuit is as shown in Figure 4.8: Output waveform of serial2parallel converter 4.

groups of 2 bits sets are converted into complex numbers representing QPSK constellation points.10: Output waveform of QPSK_mod The circuit of the qpsk_const which does the mapping of 2 bits of the input into QPSK constellations is shown in Figure 4. the mapping of the modulator depends on the parallel input fed into the QPSK modulator. As for an example if inputs are 00 then. the mapping is such that it outputs a complex number of -1–j1.43 Figure 4.13. Figure 4.9: QPSK modulator Figure 4. .3.12 and the pin description is shown in Table 4. However. For the value of -1-j1 both the real and imaginary values are represented as an eight bit integer in q_out and i_out respectively. Since the output of this module is going to the Alamouti encoder. The conversion is performed to the gray-coded QPSK constellation mapping as shown in Figure 4.14 shows the resulting waveform of the qpsk_const.

11: Internal part of QPSK_mod Figure 4.12: QPSK constellation .44 Figure 4.

which represents binary bits Output data. inp q_out Input Output 2 8 Input data.45 Table 4. Active-high enables input and disables when de-asserted. rst en Input Input 1 1 Resets all signals when active high.3: Pin description of qpsk_const Signal clk Direction Input Size 1 Description Clock signals that clocks all internal QPSK mapping engine.13: QPSK constellation mapping . which represents the real part of complex number in integers i_out Output 8 Output data. which represents the imaginary part of complex number in integers Figure 4.

There are two states in the ctrl_unit_qpsk. Table 4. Figure 4. The circuit and the resulting waveform of ctrl_unit_qpsk are shown in Figure 4.16 and Figure 4. Figure 4.15 shows the ASM chart that represents the state diagram for the ctrl_unit_qpsk which clearly states the enabled instants.17 respectively.15: ASM chart that represents the state diagram for the ctrl_unit_qpsk .4 shows the pin description of the ctrl_unit_qpsk.14: Output waveform of qpsk_const The qpsk_const is enabled by the ctrl_unit_qpsk at the appropriate instants.46 Figure 4.

Signals RESET_N Description -occurs when rst_n is low -asserts en_QPSK = 0 to disable the QPSK mapping ENABLE_ON -occurs when rst_n is high -asserts en_QPSK = 1 to enable the QPSK mapping Figure 4.4 : Pin description of the ctrl_unit_qpsk. Table 4.17: Output waveform of ctrl_unit_qpsk .16: QPSK control unit.47 Figure 4.

then the two units of QPSK_mod will map this value as 1+j1 and 1-j1 respectively. Like for example if the serial-toparallel produces a 1001.19. Therefore. The resulting output waveform is shown in Figure 4. The serial-to-parallel module and the two units of QPSK_mod are then combined appropriately in order to create a single data processing unit (TX_data_process). representing the QPSK constellation in the form of complex number (integers). which is a 4 bit parallel data.48 The inputs to the QPSK_mod are the output of the serial-to parallel converter. TX_data_process module takes in serial binary bits input and outputs four eight-bits in parallel. This TX_data_process module is shown in Figure 4. Figure 4. Keeping in mind that the QPSK_mod only takes in 2 bit input to perform the mapping. the design required two units of QPSK_mod to be able to support the mapping of 4 bits parallel data.18.18: Transmit data process module .

3 Alamouti Encoder Figure 4. i0_in. It has a reset input (rst). The resulting output waveform of the designed encoder is shown in Figure 4. clock input (clk). i1_in) and four eight-bits data output (q0_out.21. There are also four eight-bit outputs for the real and imaginary parts of the encoded symbols. and are assumed to be held constant for the duration of the encoding process (two clock cycles). The encoder has four eight-bit inputs.20 shows the Alamouti encoder which contains sequential logic and thus requires some control logic and clock signals. q1_out. i0_out. . four eight-bits data inputs (q0_in.49 Figure 4. The inputs are not registered.1. enable input (en). these outputs are fed into the channel modeling circuit. the real and imaginary parts of the two symbols being encoded.4 shows the pin description of the encoder. i1_out).19: Output waveform of TX_data_process 4. The encoding of this module follows the algorithm suggested by Alamouti as shown in Table 2. in the case of this project.2. q1_in. However. Table 4. These outputs are to be transmitted to establish an end-to-end link over real wireless channels.

20: Alamouti encoder Figure 4.50 Figure 4.21: Output waveform of the Alamouti encoder .

5: Pin description of Almouti encoder Signal clk Direction Size Input 1 Description Clock signals that clocks all signals of the encoder rst en Input Input 1 1 Resets all signals when active high. which represents the imaginary part of complex number in integers . q0_in Input 8 Input data. which represents the imaginary part of complex number in integers q1_in Input 8 Input data. which represents the imaginary part of complex number in integers qo_out Output 8 Output data. which represents the real part of complex number in integers i0_in Input 8 Input data. Active-high enables input and disables when de-asserted. which represents the imaginary part of complex number in integers q1_out Output 8 Output data.51 Table 4. which represents the real part of complex number in integers i0_out Output 8 Output data. which represents the real part of complex number in integers i1_in Input 8 Input data. which represents the real part of complex number in integers i1_out Output 8 Output data.

52 4.2.4 Transmitter (TX)

The TX_data_process module and the Alamouti encoder module are then combined to form the entire transmitting module (TX). This is shown in Figure 4.22 and the resulting waveform is shown in Figure 4.23.

Figure 4.22: Transmitter module

Figure 4.23: Output waveform of Transmitter

53 4.3 Alamouti Receiver

Figure 4.24 shows the block diagram of Alamouti Receiver which consist of two sub-blocks. These sub-blocks are the Alamouti Decoder and QPSK demodulator. The received signal at the antenna is being fed into the Alamouti decoder, where the signal is being decoded according to the Alamouti’s diversity technique as mentioned in Chapter 2. Upon the decoding process, the signal is then fed into the QPSK demodulator to retrieve the original binary bit stream which was transmitted.

Figure 4.24: Block Diagram of Alamouti Receiver

The receiver is also assumed to have the knowledge of the channel experienced by the signal. Due to this, the design does not require a channel estimator and Maximum Likelihood (ML) part of design. And as mentioned earlier, in the design the transmitted signal is directly connected and the channel modeling modifies the transmitted signal to behave as it should as if the signal had been transmitted over real wireless environment before being received at the receiver.

54 4.3.1 Alamouti decoder

The Alamouti decoder is the combiner circuit that is made up of rx_control_add and rx_control_minus circuits as shown in Figure 4.25. It has clock input (clk), reset input (rst), and four eight-bit data input of received signals, four eight-bit channel representation input signals and four eight-bits outputs which represents two complex numbers which consist of the real and imaginary part each. These two complex numbers are the received signals at two consecutive symbol periods. The pin description of the decoder is shown in Table 4.6. Both this circuits implies the decoding algorithm of the Alamouti transmit diversity technique. The Alamouti’s transmit diversity technique applied in the Alamouti decoder has an addition and subtraction functions involved as mentioned in Chapter 2. This operation of addition and subtraction are performed by the rx_control_add and rx_control_minus circuits respectively according to Equation 2.8. The resulting output waveform of the rx_control_add and rx_control_minus are shown in Figure 4.26 and Figure 4.27 respectively.

Figure 4.25: Alamouti decoder

26: Output waveform of rx_control_add Figure 4.55 Figure 4.27: Output waveform of rx_control_minus .

which represents the real part of complex number in integers r0_im Output 8 Output data. h0_re Input 8 Received channel signal. Pin description of the Alamouti in decoder Signals clk rst s0_re Direction Input Input Input Size 1 1 8 Description Clock signals that clocks all signals of the encoder. s0_im Input 8 Received data signal. Received data signal. which represents the imaginary part of complex number in integers. which represents the real part of complex number in integers h1_im Input 8 Received channel signal. which represents the real part of complex number in integers r1_im Output 8 Output data.56 Table 4.6:. which represents the imaginary part of complex number in integers r1_re Output 8 Output data. s1_re Input 8 Received data signal. Resets all signals when active high. which represents the imaginary part of complex number in integers h1_re Input 8 Received channel signal. which represents the imaginary part of complex number in integers r0_re Output 8 Output data. s1_im Input 8 Received data signal. which represents the real part of complex number in integers. which represents the real part of complex number in integers. which represents the imaginary part of complex number in integers. which represents the imaginary part of complex number in integers . which represents the real part of complex number in integers h0_im Input 8 Received channel signal.

is used in the QPSK demodulator.57 4. if a decoded signal produce a 1 at q_out (real) and -1 at i_out (imaginary).28: QPSK demodulator Figure 4. this be demodulated as two binary bits of 01 as shown in the output waveform in Figure 4. A 1(8 bits) will be converted as a 1(1 bit) and a -1(8 bits) will be a 0(1 bit).2 QPSK Demodulator Figure 4.29 Figure 4. Like for example.3. The same QPSK constellation principles that was used in the QPSK modulator in the transmitter.28 shows the QPSK demodulator that demodulates the decoded received signal to produce the transmitted binary bit stream.29: Output waveform of QPSK_demod .

There is a need of two units of QPSK demodulator as the decoded output signal from the Alamouti decoder are four bits and the QPSK demodulator has only two bits of inputs. Figure 4.3. Figure 4.30: Alamouti receiver .30 and Figure 4.3 Receiver (RX) The Alamouti decoder and two units of QPSK demodulators are combined to form the Alamouti receiver (RX).58 4.31 shows the receiver circuit and the resulting output waveform.

the channel modeling modifies the transmitted signal to behave as it should as if the signal had been transmitted over real wireless environment before being received at the receiver.6 before being received at the receiver end. Therefore. .59 Figure 4. The transmitted signal is directly connected to the receiver and the intermediate part of the design.4 Channel Modelling For the transmission between the designed transmitter and receiver system. there is channel modeling involved as the transmission was not done in real wireless environment.31: Output waveform of Alamouti receiver 4. keep in mind that this intermediate part is only created because the transmitted signals need to be modified to be in the representation of Equation 2.

Since only four outputs are received at the first symbol period. Each signal is a complex number representation which has the real and imaginary part. The output becomes 8 eight-bits. as at the first symbol period.32: Channel_capture module The channel modeling involves the channel_capture unit which is made up of the capture module and the channel module. real and imaginary.34 shows the circuit and output waveform of this module respectively. However.60 Figure 4. This capture module then outputs the 8 eight-bits output in parallel. Figure 4.32 shows the channel_capture circuit. another two signals are transmitted. Therefore. two signals are transmitted and the consecutive symbol period. The capture module captures the signals and produces the 8 eight. . Which makes four outputs for two consecutive symbol periods.bit parallel output.33 and Figure 4. the capture module stores this data and waits for the next consecutive symbol period which will produce another four output. one signal will have two outputs. this does not happen in real transmission. Figure 4. there will be 8 eightbit outputs.

61 Figure 4. This channel module is shown in Figure 4. Assume that there is no noise and interference present at the receiver. The receive chain is modeled by a complex multiplicative distortion composed of a magnitude response and a phase response.35.33: Capture module Figure 4.34: Output waveform of capture module The channel module includes the effects of the transmit chain and the airlink. .

this is the signal which is fed directly into the Alamouti receiver.36 shows the resulting output waveform of the channel modeling.62 Figure 4.36: Output waveform of Channel_capture module . In other words.35: Channel module Figure 4. Figure 4.

and creates a symbol that represents on of four phase states. known as Gray coding. a gray-code input signal was designed and this module was identified as gen. First of all. (a) Block diagram of gray_gen . The gray encoder is used to map the data in such a way as to help reduce bit errors. This technique proves to help with error performance because if a symbol is received in error. Therefore for the purpose of testing on the implementation. many circuits were designed in order to provide input signals and control signals. This gen circuit was made up of two sub-blocks. One can see that each adjacent symbol is represented by two data bits that vary by one bit.5 Gray Coding The system performance of a digital communication network can be enhanced by incorporating a coding technique. two at a time. A QPSK system takes the input data bits.63 4. the gray code (gray_gen) and parallel to serial converter (parallel2serial) circuits.38 shows the resulting waveform. it will contain only one error bit if it was received in error to an adjacent symbol. within the system.37 shows the gray_gen circuit and Figure 4. Figure 4. The gray encoder therefore is used to map every two input data bits to one of four unique symbol values so that the bit pairs that are used to generate the symbols are only one bit different from each adjacent symbol.

40 shows the resulting waveform of this module. And this conduct was done by the designed parallel2serial. .38: Output waveform of gray_gen As the gray_gen produces a four bit parallel data and the fact that the input to the transmitter is serial bit stream.37: Gray_gen Figure 4. there was a need to convert these parallel data into serial form. Figure 4.64 (b) Internal part of gray_gen Figure 4.39 shows the circuit of the parallel2serial circuit and Figure 4.

39: Parallel2serial .65 (a) Block diagram of Parallel2serial (b) Internal part of Parallel2serial \ Figure 4.

40: Output waveform of Parallel2serial Both the gray_gen and parallel2serial circuits are combined together to produce one single module identified as gen.41: Gen module . The circuit of gen module is shown in Figure 4.66 Figure 4.41 and its resulting output waveform in Figure 4. which outputs the gray code signals in serial bit stream.42. (a) Block diagram of gen (b) Internal part of gen Figure 4.

Figure 4. The gray code in the sequence of 0.42: Output waveform of gen module Finally for the testing of the implementation of the design. The resulting complete transmission output waveform is shown in Figure 4.43. which was transmitted by the Alamouti transmitter was detected and decoded correctly by the Alamouti receiver in the designed system.43: Output waveform of transmission (TRX) . 2. the input signal generated by gen was fed into the Alamouti transmitter module and the output was monitored at the designed Alamouti receiver module. 6 and so on in the base of hexadecimal. 1.67 Figure 4.

1 Result and Conclusion Figure 5.1: Alamouti’s Transmit Diversity technique implemented on Altera and Xilinx FPGA .68 CHAPTER 5 RESULT AND CONCLUSION 5.

The Alamouti decoder design implemented multipliers by simply using the ‘*‘ operator in Verilog HDL. Some of these challenges were due to the constraints in implementing it on the FPGA as had to make sure that the FPGA had sufficient amount of multiplication resources available. In addition to simply getting the system to function there is much room for optimization in the hardware designs created for this project. this project has proved that it is quite feasible to implement an Alamouti code using commercially available FPGAs. . Chapter 2 showed the theoretical basis for the Alamouti code and these theories were confirmed by the implementation of the Alamouti code on created hardware design. For most constellations. Therefore. the hardware realization differs very little from the implementation of two standard wireless transmitters. In fact. Each stream is fed to identical transmit chains each driving a separate antenna. All source code of the design is attached in Appendix A. The implementation report of the design is attached in Appendix B. The output of the encoding process is two streams of modulated symbols. The implementation of an Alamouti receiver is somewhat more challenging. The only operation the Alamouti encoder performs on modulated symbols is the negation of either the real or imaginary part of a symbol. This could be seen in the implementation report. Chapter 4 contains the details of the design analysis. This puts the possibility of further testing and research into MIMO systems within reach. The two transmit antennas and one antenna at the receiver with the encoding and decoding algorithms are coded using Verilog Hardware Description Language (HDL) were successfully coded and verified.69 The design of two transmitter antenna and one receiver antenna wireless communications system based on Alamouti’s space-time code is successfully implemented onto both XILINX and ALTERA FPGA as shown in Figure 5. The inclusion of an Alamouti encoder in a transmitter design does not significantly increase its complexity. this process is analogous to mapping one symbol to another valid symbol.1.

1 Recommendations This implementation is part of an ongoing effort to develop an FPGA based multiple antenna wireless communications system which boasts both very high data rates and spectral efficiency. Other than these. .70 CHAPTER 6 RECOMMENDATIONS ON FUTURE WORKS 6. it can be generalized to support multiple receive antennas using the decoding algorithm provided in [1]. Other improvements would include the use of more advanced channel estimation and developing a carrier recovery scheme which would scale to accommodate higher order modulations or additional antennas. such as OFDM. when used in conjunction with space-time coding. First. The system can also be evaluated by the “real world” performance of MIMO systems under various circumstances to investigate how much diversity is available in different transmission environments. the project could also be extended by using a higher order constellation such as 16QAM. this design can be extended in a variety of ways. In working towards this goal. Besides that the design can be investigated by the use of different modulation techniques. It could be further extended to support more than two transmit antennas using the generalization of Alamouti’s code described in [2].

July 1999. M. Dick. pp. April 2000. and J. vol. Luiz Henrique Maia Junior. V. December 2001.REFERENCES 1.” in Proceedings of the 2003 Conference on Mobile and Wireless Communications Networks. 19. P. Lou. and A. Rice. “An FPGA Implementation of Alamouti’s Transmit Diversity Technique Applied To An OFDM System. 3. F. Alamouti. 1451–1458. pp.” IEEE J. Rui ROdrigues Simoes Junior. 2346–2357. “Multirate digitla filters for symbol timing synchronization in software defined radios. vol. 16. 1456–1467. Patrick Frantz. pp.” IEEE Journal on Select Areas in Communications.2006. Calderbank. October 1998.R. Jafarkhani. and M. F. 2.carrier and timing recovery using FPGAs. 4. H. Rice. “Spacetime block codes from orthogonal designs.” IEEE Journal on Select Areas in Communications. 5. C. Harris. “A hardware testbed for the implementation and evaluation ofMIMO algorithms. Murphy. October 2003 6.” IEEE Transactions on Information Theory. “A simple transmit diversity technique for wireless communications. Harris andM. Tarokh. pp. “Synchronization in software radios. 45. . F. S.” in Proceedings of 2000 IEEE Symposium on Field-Programmable Custom Computing Machines. vol. 195–204.

“A new bandwidth efficient transmit antenna modulation diversity scheme for linear digital modulation. May 1993. Tarkoh. http://www. Seshadri and J. and Computers. Poon. Zhu. “Two signaling schemes for improving the error performance of FDD transmission systems using transmitter antenna diversity. pp.” ICUPC. in 1989 and 1991. “Field test results for space. 41-59.” Bell Labs. pp.. W. 14. S. 703-707. November 2003. 13. Thesis. Australia. May 1993. 1996 8.xilinx. N. (VTC 43rd). P. University of Newcastle. 1.com 12. “Trellis coded modulation and transmit diversity. Wittneben. Tech. 2005. Foschini.” in Proc. pp. Alamouti. 1993 IEEE International Conf. 2. vol.” in Asilomar Conference on Signals.com 11. A. and P. 508–511. Communications (ICC’93). pp. Asilomar. J.72 7. and M. Winters.altera. 1993 IEEE Vehicular Technology Conf. 1998.time coding. Systems. . http://www. G. H. Eng. CA. November 1. “Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas. Ian Griffths.” in Proc. “FPGA Implementation of MIMO Wireless Communications System” B. respectively. 1630–1634. 10. Gupta. J. V. no. Fitz. 9.

. The code is written in Verilog HDL and have been tested and synthesized using both Altera and Xilinx tools as mentioned in Chapter 3.73 APPENDIX A HARDWARE DESIGN SOURCE CODE This Appendix contains the source code of the hardware designed.

out_d. qtwo_s2p. valid_4). // Instantiate the module shift_reg_4 U0 ( . out_c. wire Qa_s2p. out_d. input rst. out_c. Qd_s2p. input data_in. wire qone_s2p. output valid_4.74 APPENDIX A. input en.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module serial2parallel(clk. out_a. output out_d.data(data_in). output out_a. out_b. data_in. en. input clk. Qc_s2p. //to check when data is ready wire ok_4. output out_b. reg out_a.1 serial2parallel `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 00:19:59 03/29/2008 // Design Name : // Module Name : serial2parallel // // Revision: // Revision 0.01 . output out_c.Qb_s2p. out_b. . reg ok. rst.

//msb out_b <= 0. . . always@(posedge qtwo_s2p) begin if (rst) begin out_a <= 0. assign ok_4 = ok? 1'b1:1'b0. always@(posedge clk) if (rst) ok <= 0.enable(qone_s2p).clk(clk). else if (qtwo_s2p) ok <= ok+1. . .//lsb out_c <= 0.rst(rst).75 .rst(rst).clk(clk).Qc(Qc_s2p).clk(clk).Qd(Qd_s2p)).Qb(Qb_s2p).rst(rst). .q(qtwo_s2p)). .q(qone_s2p)). out_b <= Qb_s2p. assign valid_4 = ((ok_4== 1'b1)&(qtwo_s2p==1'b1))? 1'b1:1'b0. . .enable(en). . .//lsb end else begin out_a <= Qa_s2p. . // Instantiate the module double_clk U2 ( . // Instantiate the module double_clk U1 ( .Qa(Qa_s2p). .//msb out_d <= 0.

end end endmodule .76 out_c <= Qc_s2p. out_d <= Qd_s2p.

.2 shift_reg_4 `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 22:21:32 03/28/2008 // Design Name : // Module Name : shift_reg_4 // // Revision: // Revision 0. reg Qa. Qc <= 1'b0. Qb.//msb :the last to be in Qb <= 1'b0. Qc. Qb. Qd).//lsb:the 1st digit to be in end else begin Qa <= data. input clk. rst.77 APPENDIX A. Qc. Qd <= 1'b0.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module shift_reg_4(data. input data. clk.01 . Qa. output Qc. Qb <= Qa.rst. output Qb. output Qd. always@(posedge clk) if (rst) begin Qa <= 1'b0. Qd. output Qa.

end endmodule . Qd <= Qc.78 Qc <= Qb.

else q_temp <= q_temp+1.3 double_clk `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 23:18:02 03/28/2008 // Design Name : // Module Name : double_clk // // Revision: // Revision 0.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module double_clk(clk.79 APPENDIX A. q). input clk. enable. rst. always@(posedge clk) begin if ((enable == 1'b0)|(rst==1'b1)) q_temp <= 1'b0. end assign q = q_temp? 1'b1:1'b0. input enable. input rst.01 . reg q_temp. endmodule . output q.

File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module qpsk_mod(clk. input rst_n. output [7:0] i_out. rst_n.clk(clk). q_out.en_qpsk(en_qpsk) .4 qpsk_mod `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:33:08 03/29/2008 // Design Name : // Module Name : qpsk_mod // // Revision: // Revision 0. . wire en_qpsk. input rst.80 APPENDIX A. output [7:0] q_out. input [1:0] inp. // Instantiate the module ctrl_unit_qpsk U0 ( .01 . input clk. i_out). rst. .resetn(rst_n). inp.

. .rst(rst). endmodule .q_out(q_out). .en(en_qpsk).clk(clk). . .inp(inp).i_out(i_out)).81 // Instantiate the module qpsk_const U1 ( .

01 . en. input [1:0] inp. end else if (inp==2'b10) .5 qpsk_const `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 11:49:32 03/29/2008 // Design Name : // Module Name : qpsk_const // // Revision: // Revision 0. i_temp <= 8'b1111_1111. always@(posedge clk) begin if ((en == 1'b0)|(rst==1'b1)) begin q_temp <= 8'b0000_0000.//real output signed [7:0] i_out.rst. i_out). input clk. i_temp <= 8'b0000_0000. end else begin if (inp==2'b00) begin q_temp <= 8'b1111_1111. output signed [7:0] q_out. rst.//imaginary reg signed [7:0] q_temp. reg signed [7:0] i_temp.en.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module qpsk_const(clk. inp.82 APPENDIX A. q_out.

83 begin q_temp <= 8'b0000_0001. i_temp <= 8'b0000_0001. assign i_out = i_temp. end end end assign q_out = q_temp. end else if (inp == 2'b11) begin q_temp <= 8'b0000_0001. i_temp <= 8'b1111_1111. endmodule . i_temp <= 8'b0000_0001. end else if (inp==2'b01) begin q_temp <= 8'b1111_1111.

en_qpsk). output en_qpsk.6 ctrl_unit_qpsk `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 00:41:33 03/29/2008 // Design Name : // Module Name : ctrl_unit_qpsk // // Revision: // Revision 0. reg en_qpsk. resetn.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module ctrl_unit_qpsk(clk. else en_qpsk <= 1'b0.01 .//state rstn end endmodule . input resetn. input clk.84 APPENDIX A. always@(posedge clk) begin if (resetn==1'b1)//state en_on en_qpsk <= 1'b1.

01 . . input rst.clk(clk). temp_d. done_4). wire temp_a. reg done. output [7:0] data_outD. data_outB. en. rst. done1. wire [1:0] temp_1.7 tx_data_process `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:43:39 03/29/2008 // Design Name : // Module Name : tx_data_process // // Revision: // Revision 0. output [7:0] data_outA. // Instantiate the module serial2parallel U0 ( .85 APPENDIX A. input en. output done_4. output [7:0] data_outC. output [7:0] data_outB. assign done_4 = done1. input data_in. input clk. wire valid_4. data_outA. temp_2. temp_b. data_in. temp_c. data_outC. data_outD.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module tx_data_process(clk.

always@(posedge clk) if (rst) begin done <= 1'b0.out_b(temp_b). end else begin done <= valid_4. . //bit 2.data_in(data_in). .1 // Instantiate the module qpsk_const U1( . done1 <= 1'b0.clk(clk).valid_4(valid_4)). .i_out(data_outB)). // Instantiate the module qpsk_const U2( . . .en(en).q_out(data_outC).clk(clk).q_out(data_outA).rst(rst). . // bit2&3 for s1 . . temp_c}. temp_a}.out_c(temp_c). .out_d(temp_d).rst_n(valid_4).out_a(temp_a). .// bit0&1 for s0 .inp(temp_2).3 assign temp_1 = {temp_d. .rst(rst). done1 <= done. .rst_n(valid_4).86 . . . assign temp_2 = {temp_b.rst(rst).inp(temp_1). end endmodule . . //bit 0. .i_out(data_outD)).

tmp1_i <= 0. reg [7:0] tmp1_i. reg state. tmp1_q. q1_out. rst. en. output [7:0] q1_out. always@(posedge clk) begin if ((rst)|(en==1'b0)) begin tmp0_i <= 0. q0_out. q1_in.87 APPENDIX A. input clk. input [7:0] i0_in. output [7:0] q0_out.01 . tmp0_q <= 0. i1_in. . en.8 encoder `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:58:09 03/29/2008 // Design Name : // Module Name : encoder // // Revision: // Revision 0. i0_in. tmp0_q. input [7:0] q1_in. output [7:0] i0_out. output [7:0] i1_out. i1_out). rst. input [7:0] q0_in. i0_out.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module encoder(clk. input [7:0] i1_in. q0_in. reg [7:0] tmp0_i.

tmp0_i <= tmp1_i. assign i1_out = tmp1_i. endmodule . end else if (state ==1'b1)//t1 begin tmp0_q <= -tmp1_q.88 tmp1_q <= 0. tmp1_q <= tmp0_q. tmp1_i <= -tmp0_i. assign i0_out = tmp0_i. tmp1_i <= i1_in. state <= 1'b1. tmp0_i <= i0_in. end else if (state == 1'b0)//t0 begin tmp0_q <= q0_in. assign q1_out = tmp1_q. state <= 1'b0. tmp1_q <= q1_in. end end assign q0_out = tmp0_q. state <= 1'b0.

//instant t1 // Instantiate the module tx_data_process U0(. output [7:0] i0.clk(clk). q0. output ready0. //to en the encoder.9 TX `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 15:23:02 03/29/2008 // Design Name : // Module Name : TX // // Revision: // Revision 0. ready1. ready_4. ready_4). data_in.89 APPENDIX A. ready0. wire [7:0] outA_q. output [7:0] q1. input rst. outA_i. en. output [7:0] q0. .data_in(data_in). q1. . input data_in. take the output from tx_part1_4 wire done_4. ready1. i1. outB_i. i0. input en.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module TX(clk. outB_q. //to check for data valid instant reg ready0. input clk.01 . output [7:0] i1. rst.//instant t0 reg ready1.

i0_in(outA_i).data_outA(outA_q). .clk(clk). // Instantiate the module encoder U1 ( .q0_in(outA_q). .rst(rst). .q1_out(q1).data_outC(outB_q). always@(posedge clk) if (rst) begin ready0 <= 1'b0.//s0 . . ready1 <= 1'b0. .//s0 . . .done_4(done_4)).data_outD(outB_i). ready1 <= ready0. .data_outB(outA_i).q0_out(q0). .i1_in(outB_i).//s1 .en(en).i1_out(i1) ). . . endmodule . .q1_in(outB_q). end else begin ready0 <= done_4.//s1 .90 .rst(rst).en(en).i0_out(i0). end assign ready_4 = ((ready0)&(!ready1))|((!ready0)&(ready1))? 1'b1: 1'b0.

input [7:0] s0_re. r_im.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module rx_control_add(clk. s0_im.01 . h1_im. r_im. s1_im. s0_im. //result of mult of s*h reg [15:0] multre_state0. input clk. reg [7:0] tempr_re1. //sum of soho+sihi reg [7:0] tempr_re0. output [7:0] r_re.10 rx_control_add `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:15:55 03/30/2008 // Design Name : // Module Name : rx_control_add // // Revision: // Revision 0. tempr_im1. h0_re. rst .multre_state1. tempr_im0. reg [7:0] r_re. s1_re. h0_im. h1_im. h1_re. . r_re. s0_re. r_im). h0_im. s1_im. input [7:0] h1_re.91 APPENDIX A.//signal from 2nd antenna input [7:0] h0_re. rst.//signal from 1st antenna input [7:0] s1_re.

multre_state1 <= 0. end else begin multre_state0 <= (h0_re*s0_re). multre_state3 <= (h1_im*s1_im). end always@(posedge clk)//after completion of mult if ((rst)) begin tempr_re0 <= 0. mult1re = multre_state1[7:0].multim_state3. mult3im = multim_state3[7:0]. mult1im. tempr_re1 <= 0. reg [15:0] multim_state2. mult2re.multre_state3. mult1re. mult3re.92 reg [15:0] multre_state2. mult1im = multim_state1[7:0]. mult3im. mult2im = multim_state2[7:0]. mult0im = multim_state0[7:0]. multre_state3 <= 0. multre_state2 <= 0. multre_state2 <= (h1_re*s1_re). mult2im. mult0re = multre_state0[7:0].multim_state1. end . assign assign assign assign assign assign assign assign mult3re = multre_state3[7:0]. mult2re = multre_state2[7:0].(multre_state3[7:0])). end else begin tempr_re0 <= ((multre_state0[7:0]) . //check wire [7:0] mult0re. always@(posedge clk) if ((rst)) begin multre_state0 <= 0.(multre_state1[7:0])). wire [7:0] mult0im. tempr_re1 <= ((multre_state2[7:0]) . reg [15:0] multim_state0. multre_state1 <= (h0_im*s0_im).

93 always@(posedge clk)//after completion of mult if ((rst)) begin r_re <= 0. multim_state3 <= (h1_im*s1_re). multim_state1 <= (h0_im*s0_re). end always@(posedge clk)//after completion of mult if ((rst)) begin r_im <= 0. end else begin tempr_im0 <= ((multim_state0[7:0]) + (multim_state1[7:0])). tempr_im1 <= 0. multim_state2 <= (h1_re*s1_im). end else begin multim_state0 <= (h0_re*s0_im). multim_state3 <= 0. end else begin r_re <= (tempr_re0)+(tempr_re1). end always@(posedge clk)//after completion of mult if ((rst)) begin tempr_im0 <= 0. end else begin . multim_state1 <= 0. tempr_im1 <= ((multim_state2[7:0]) + (multim_state3[7:0])). end always@(posedge clk) if ((rst)) begin multim_state0 <= 0. multim_state2 <= 0.

94 r_im <= (tempr_im0)+(tempr_im1). end endmodule .

h1_im. //result of mult of s*h reg [15:0] multre_state0. s1_im. h1_im. h0_im.95 APPENDIX A. r_im).01 .//signal from 1st antenna input [7:0] s1_re. r_im.multre_state1. s0_re. output [7:0] r_re. .File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module rx_control_minus(clk. h0_im. tempr_im1. input clk. s0_im. rst. tempr_im0.multre_state3. r_re.11 rx_control_minus `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:16:57 03/30/2008 // Design Name : // Module Name : rx_control_minus // // Revision: // Revision 0. s1_im. reg [15:0] multre_state2. r_im. s0_im. reg [7:0] tempr_re1. rst . input [7:0] h1_re. input [7:0] s0_re. h0_re. //sum of soho+sihi reg [7:0] tempr_re0.//signal from 2nd antenna input [7:0] h0_re. reg [7:0] r_re. s1_re. h1_re.

wire [7:0] mult0im.(multre_state3[7:0])). end else begin tempr_re0 <= ((multre_state0[7:0]) . multre_state2 <= (h0_re*s1_re). always@(posedge clk) if ((rst)) begin multre_state0 <= 0. reg [15:0] multim_state2. mult2im = multim_state2[7:0].multim_state3. tempr_re1 <= 0. mult1im = multim_state1[7:0]. end else begin multre_state0 <= (h1_re*s0_re).96 reg [15:0] multim_state0. tempr_re1 <= ((multre_state2[7:0]) . assign assign assign assign assign assign assign assign mult3re = multre_state3[7:0]. mult0re = multre_state0[7:0]. mult1re. mult3im. multre_state3 <= 0. end always@(posedge clk)//after completion of mult if ((rst)) begin tempr_re0 <= 0. multre_state1 <= 0. mult3re.multim_state1. mult1re = multre_state1[7:0]. mult1im. multre_state1 <= (h1_im*s0_im). //check wire [7:0] mult0re. end . mult2re. multre_state2 <= 0.(multre_state1[7:0])). multre_state3 <= (h0_im*s1_im). mult0im = multim_state0[7:0]. mult2re = multre_state2[7:0]. mult3im = multim_state3[7:0]. mult2im.

end ///////////////////////////////////// always@(posedge clk) if ((rst)) begin multim_state0 <= 0. end always@(posedge clk)//after completion of mult if ((rst)) begin tempr_im0 <= 0. multim_state1 <= 0. multim_state1 <= (h1_im*s0_re). multim_state2 <= 0. tempr_im1 <= 0. multim_state2 <= (h0_re*s1_im). multim_state3 <= 0. multim_state3 <= (h0_im*s1_re). end else begin tempr_im0 <= ((multim_state0[7:0]) + (multim_state1[7:0])). tempr_im1 <= ((multim_state2[7:0]) + (multim_state3[7:0])). end else begin r_re <= (tempr_re0)-(tempr_re1). end else begin multim_state0 <= (h1_re*s0_im).97 always@(posedge clk)//after completion of mult if ((rst)) begin r_re <= 0. end else . end always@(posedge clk)//after completion of mult if ((rst)) begin r_im <= 0.

end endmodule .98 begin r_im <= (tempr_im0)-(tempr_im1).

//real input signed [7:0] i_out. else if ((!q_out[7])&(i_out[7])) inp <= 2'b10. input clk.rst.01 . i_out. q_out. always@(posedge clk) begin if ((rst==1'b1)) inp <= 2'bXX. else if ((q_out[7])&(!i_out[7])) inp <= 2'b01. else if ((!q_out[7])&(!i_out[7])) inp <= 2'b11. rst. else if ((q_out[7])&(i_out[7])) inp <= 2'b00. reg [1:0] inp. end endmodule . inp).//imaginary output [1:0] inp.12 qpsk_demod `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:14:39 03/30/2008 // Design Name : // Module Name : qpsk_demod // // Revision: // Revision 0. input signed [7:0] q_out.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module qpsk_demod(clk.99 APPENDIX A.

rx_im_in_1. rx_re_in_1.done). input [DATA_WIDTH-1:0]rx_re_in_0.13 RX `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 12:18:02 03/30/2008 // Design Name : // Module Name : RX // // Revision: // Revision 0. input [DATA_WIDTH-1:0]h_re_in_0. assign rx_im_in_1_modify = -rx_im_in_1. parameter DATA_WIDTH = 8.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module RX(clk. s1im_est. output done. wire [DATA_WIDTH-1:0] h_im_in_1_modify. wire [7:0] s0re_est. output [3:0] dataout. .01 . s0im_est.100 APPENDIX A. input clk. rst. h_im_in_1. input [DATA_WIDTH-1:0]rx_re_in_1. input [DATA_WIDTH-1:0]h_im_in_1. wire [DATA_WIDTH-1:0] h_im_in_0_modify. en. rst. input [DATA_WIDTH-1:0]rx_im_in_0. wire [DATA_WIDTH-1:0] rx_im_in_1_modify. dataout. input [DATA_WIDTH-1:0]rx_im_in_1. rx_im_in_0. en. h_re_in_1. h_im_in_0. h_re_in_0. rx_re_in_0. s1re_est. input [DATA_WIDTH-1:0]h_im_in_0. input [DATA_WIDTH-1:0]h_re_in_1.

r_re(s1re_est).inp(dataout[3:2])).h1_re(h_re_in_1). .clk(clk). .clk(clk).r_re(s0re_est).q_out(s1re_est).h1_im(h_im_in_1_modify).en(done).clk(clk).s0_re(rx_re_in_0).rst(rst). . // Instantiate the module qpsk_demod U1( . // Instantiate the module qpsk_demod U2( .h0_im(h_im_in_0_modify). . endmodule . . .h1_im(h_im_in_1). . .i_out(s0im_est).h1_re(h_re_in_1).s0_im(rx_im_in_0). .en(done).done(done)). . .rst(rst).inp(dataout[1:0])). //.s0_re(rx_re_in_0). . .clk(clk). rx_control_add s0_unit(. .r_im(s1im_est)).h0_im(h_im_in_0). . .rst(rst).clk(clk).s0_im(rx_im_in_0).rst(rst). . .s1_im(rx_im_in_1_modify). .s1_re(rx_re_in_1).rst(rst). . . . countdone uut_done(. .i_out(s1im_est). . .s1_im(rx_im_in_1_modify).101 assign h_im_in_0_modify = -h_im_in_0.h0_re(h_re_in_0). .s1_re(rx_re_in_1). . .q_out(s0re_est).r_im(s0im_est)).h0_re(h_re_in_0). . . rx_control_minus s1_unit(. assign h_im_in_1_modify = -h_im_in_1. . //. .

s0_im. sig0_im_t0. reg [7:0] sig0_re_t1. s1_im. r0_im_t0.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module capture(clk. output en_combiner. en_channel. reg [7:0] sig1_re_t1. reg [7:0] r0_re_t1. r1_re_t1. r1_re_t0. s1_re. s1_re.en_combiner).01 .14 capture `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 15:43:34 03/29/2008 // Design Name : // Module Name : capture // // Revision: // Revision 0. r0_im_t1. r0_re_t0. sig0_im_t1. s1_im.102 APPENDIX A. output [7:0] r0_re_t1. r1_im_t1. output [7:0] r0_re_t0. output en_channel. r1_re_t1. input clk. r1_im_t0. r1_im_t1. rst. sig1_im_t1. r0_im_t1. . input [7:0] s0_re. r1_re_t1. r0_re_t0. ready_4. ready1. r1_im_t0. reg [7:0] sig0_re_t0. ready1. r0_im_t0. r0_im_t1. r1_im_t0. s0_re. reg [7:0] r1_re_t0. r1_im_t1. ready_4. rst. reg [7:0] sig1_re_t0. r1_re_t0. ready0. s0_im. input ready0. r0_re_t1. sig1_im_t0. r0_im_t0.

reg ready0_temp3. sig1_re_t0 <= 0. r1_im_t1 <= s1_im. sig0_re_t1 <= s0_re. r0_im_t1 <= s0_im. sig0_im_t0 <= 0. sig1_re_t1 <= s1_re. r1_re_t1 <= s1_re. sig0_im_t1 <= 0. en_channel <= 1'b0. sig1_re_t0 <= 0.103 reg en_channel. sig1_im_t0 <= 0. reg ready0_temp0. sig0_im_t0 <= 0. reg en_combiner. sig0_im_t1 <= s0_im. en_channel <= 1'b1. sig1_im_t1 <= 0. always@(posedge clk) if (rst) begin sig0_re_t1 <= 0. sig1_im_t1 <= s1_im. r1_im_t0 <= sig1_im_t1. r0_im_t0 <= sig0_im_t1. reg ready0_temp1. sig0_re_t0 <= 0. reg ready0_temp2. end . sig1_re_t1 <= 0. r0_re_t1 <= s0_re. end else if ((ready0)&(ready_4)) begin sig0_re_t0 <= 0. r1_re_t0 <= sig1_re_t1. end else if ((ready1)&(ready_4)) begin r0_re_t0 <= sig0_re_t1. en_channel <= 1'b0. sig1_im_t0 <= 0.

ready0_temp0 <= 0. ready0_temp1 <= 0. en_combiner <= ready0_temp3. ready0_temp1 <= ready0_temp0. ready0_temp3 <= ready0_temp2. ready0_temp2 <= ready0_temp1. end endmodule . ready0_temp2 <= 0. en_combiner <= 0. ready0_temp3 <= 0. end else begin ready0_temp0 <= ready0.104 always@(posedge clk) if (rst) begin ready0_temp0 <= 0.

rst. h0_im. s0_re. input clk. //sum of soho+sihi reg [7:0] tempr_re0. s1_re. tempr_im1. en. r_re. //result of mult of s*h reg [15:0] multre_state0. h1_im. s0_im. output [7:0] r_re. reg [7:0] tempr_re1.multre_state1. . s1_im. tempr_im0.multre_state3. h1_re.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module channel(clk. rst. r_im. input [7:0] s0_re. r_im). h0_im. h1_im. input [7:0] h1_re. en.105 APPENDIX A.//signal from 1st antenna input [7:0] s1_re. s1_im. r_im. reg [15:0] multre_state2.//signal from 2nd antenna input [7:0] h0_re. h0_re.15 channel `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 16:31:19 03/29/2008 // Design Name : // Module Name : channel // // Revision: // Revision 0. s0_im.01 . reg [7:0] r_re.

multre_state3 <= 0. end always@(posedge clk) if ((rst)|(!en)) begin . always@(posedge clk) if ((rst)|(!en)) begin multre_state0 <= 0. end else begin r_re <= (tempr_re0)+(tempr_re1). multre_state1 <= 0. reg [15:0] multim_state2. multre_state1 <= (h0_im*s0_im). end always@(posedge clk)//after completion of mult if ((rst)|(!en)) begin tempr_re0 <= 0.multim_state3. end else begin multre_state0 <= (h0_re*s0_re). tempr_re1 <= ((multre_state2[7:0]) .(multre_state1[7:0])). tempr_re1 <= 0.multim_state1. multre_state2 <= (h1_re*s1_re).(multre_state3[7:0])). multre_state2 <= 0. end else begin tempr_re0 <= ((multre_state0[7:0]) . multre_state3 <= (h1_im*s1_im). end always@(posedge clk)//after completion of mult if ((rst)|(!en)) begin r_re <= 0.106 reg [15:0] multim_state0.

multim_state1 <= 0. end endmodule . tempr_im1 <= ((multim_state2[7:0]) + (multim_state3[7:0])). end else begin multim_state0 <= (h0_re*s0_im). end always@(posedge clk)//after completion of mult if ((rst)|(!en)) begin r_im <= 0. tempr_im1 <= 0. end always@(posedge clk)//after completion of mult if ((rst)|(!en)) begin tempr_im0 <= 0. multim_state3 <= (h1_im*s1_re). multim_state2 <= (h1_re*s1_im). multim_state3 <= 0. multim_state1 <= (h0_im*s0_re). end else begin r_im <= (tempr_im0)+(tempr_im1).107 multim_state0 <= 0. multim_state2 <= 0. end else begin tempr_im0 <= ((multim_state0[7:0]) + (multim_state1[7:0])).

ready1. h1_im. s1_re. s1_im. h0_re.01 . h1_im. r0_im_t1. r1_re_t1. rst.16 channel_capture `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 17:00:08 03/29/2008 // Design Name : // Module Name : channel_capture // // Revision: // Revision 0. r1_re_t0. ready_4.108 APPENDIX A. ready_4. . wire en_channel. h0_im. .rst(rst). h0_im. output [7:0] r0_re. wire [7:0] r0_re_t0. r0_im. input [7:0] s0_re. ready1. h1_re. h1_re.clk(clk). input clk. r1_re. r1_im_t0.s0_re(s0_re). s0_re.File Created // Additional Comments: // /////////////////////////////////////////////////////////////////////////////////////// module channel_capture(clk. r0_im_t0. rst. s1_im. wire [7:0] r0_re_t1. r0_im. . r1_im. r0_re. ready0. r1_im. s0_im. r1_re. s0_im. r1_im_t1. output en_combiner. //instantiation of module capture U1_capture ( . en_combiner). input [7:0] h0_re. input ready0. s1_re.

. .s0_im(r0_im_t1).rst(rst). . .en_channel(en_channel). . .s1_im(r1_im_t1).h0_re(h0_re). .ready0(ready0).r0_re_t1(r0_re_t1).s0_re(r0_re_t0). .en(en_channel). .r_re(r1_re). . . . //instantiation of module channel U3_channelt1 (. . .r_im(r0_im)).rst(rst). .r1_im_t0(r1_im_t0).s0_im(s0_im).r1_re_t1(r1_re_t1). .h0_im(h0_im).r0_re_t0(r0_re_t0).s1_re(r1_re_t0). .s0_im(r0_im_t0). .en_combiner(en_combiner)). .r_re(r0_re). .h0_re(h0_re).clk(clk).s0_re(r0_re_t1).ready1(ready1). . .s1_im(r1_im_t0). . //instantiation of module channel U2_channelt0 (. . . .h1_re(h1_re). .109 .r1_re_t0(r1_re_t0). .r1_im_t1(r1_im_t1).s1_re(s1_re). . .en(en_channel). endmodule . .h0_im(h0_im). .s1_re(r1_re_t1).r0_im_t0(r0_im_t0).h1_re(h1_re). .clk(clk).h1_im(h1_im). .s1_im(s1_im). .h1_im(h1_im).r_im(r1_im)).r0_im_t1(r0_im_t1). . . . .ready_4(ready_4).

17 gray_gen `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 22:10:12 03/29/2008 // Design Name : // Module Name : gray_gen // // Revision: // Revision 0. rst.01 . always@(posedge clk) if (rst) q <= 4'b0000. output [3:0] data. input clk. output valid.110 APPENDIX A.File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module gray_gen(clk. reg [1:0] p. always@(posedge clk) if (rst) p <= 0. assign valid = (p==2'b11)?1'b1:1'b0. else if (valid) . valid). data. else p <= p +1. reg [3:0] q. input rst.

^q[1:0]}. endmodule . ^q[3:2].111 q <= q+1. ^q[2:1]. assign data = {q[3].

File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module parallel2serial(clk. always@(posedge clk) if (rst) begin temp <= 4'b0000. reg [3:0] temp. input [3:0] data_in. else begin temp[3] <= temp[2]. rst. end else if (load) temp <= data_in. data_out). data_in. input rst. output data_out.18 parallel2serial `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 22:28:50 03/29/2008 // Design Name : // Module Name : parallel2serial // // Revision: // Revision 0. input clk. .112 APPENDIX A. load.01 . input load.

end assign data_out = temp[3]. temp[0] <= 1'b0.113 temp[2] <= temp[1]. endmodule . temp[1] <= temp[0].

114

APPENDIX A.19

gen

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : : 23:51:33 03/29/2008 // Design Name : // Module Name : gen // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module gen(clk, rst, dataout); input clk; input rst; output dataout; wire valid;//U0 wire [3:0] data; // Instantiate the module gray_gen U0_gray ( .clk(clk), .rst(rst), .data(data), .valid(valid)); // Instantiate the module parallel2serial U1_p2s ( .clk(clk), .rst(rst), .load(valid), .data_in(data), .data_out(dataout)); Endmodule

115

APPENDIX A.20

ALAMOUTI_TRX
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company : UTM // Engineer : Pushpamalar Mukilan // // Create Date : 19:46:47 03/29/2008 // Design Name : // Module Name : ALAMOUTI_TRX // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module ALAMOUTI_TRX(clk, en, rst, //h0_re, h0_im, //h1_re, h1_im, h, dataout, done); input clk, en, rst; //input [7:0] h0_re, h0_im; //input [7:0] h1_re, h1_im; input h; output [3:0] dataout; output done; //modify for fpga reg [24:0] count; wire [7:0] h0_re, h0_im; wire [7:0] h1_re, h1_im; wire clk_slow; //internal connections wire [3:0] datain;//U0 wire en_out;//U0 wire [7:0] q0, q1, i0, i1;//U1 wire ready0, ready1, ready_4;//U1

116 wire [7:0] r0_re_t0, r0_im_t0, r1_re_t0, r1_im_t0;//U2 wire [7:0] r0_re_t1, r0_im_t1, r1_re_t1, r1_im_t1;//U2 wire en_combiner;//U2 wire [7:0] r0_re, r0_im;//U3 wire [7:0] r1_re, r1_im;//U3 assign h0_re = {h,h,h,h,h,h,h,h}; assign h0_im = {h,h,h,h,h,h,h,h}; assign h1_re = {h,h,h,h,h,h,h,h}; assign h1_im = {h,h,h,h,h,h,h,h}; always@(posedge clk) if (rst) count <= 0; else count <= count+1; assign clk_slow = count[24]; // Instantiate the module gen U0_datagen ( .clk(clk_slow), .rst(rst), .dataout(datain)); // Instantiate the module delay_en U0_endelay (

.clk(clk_slow), .rst(rst), .en_in(en), .en_out(en_out));

// Instantiate the module TX U1_TX ( .clk(clk_slow), .en(en_out), .rst(rst), .data_in(datain), .q0(q0), .q1(q1), .i0(i0), .i1(i1), .ready0(ready0), .ready1(ready1), .ready_4(ready_4)); // Instantiate the module channel_capture U2_channel ( .clk(clk_slow), .rst(rst), .s0_re(q0), .s0_im(i0), .s1_re(q1), .s1_im(i1),

h0_im(h0_im).clk(clk_slow).h_im_in_1(h1_im).dataout(dataout). .rst(rst). . . . . .ready_4(ready_4).rx_im_in_0(r0_im). .h1_im(h1_im).en(en_combiner). . . .h1_re(h1_re). .r1_im(r1_im). .r1_re(r1_re).r0_im(r0_im). . .rx_im_in_1(r1_im).ready1(ready1).h_re_in_0(h0_re).done(done)). .en_combiner(en_combiner) ). .h_im_in_0(h0_im). . endmodule . .rx_re_in_1(r1_re).r0_re(r0_re). .rx_re_in_0(r0_re).117 .h0_re(h0_re).ready0(ready0). // Instantiate the module RX U3_RX ( . .h_re_in_1(h1_re). . . .

The report is the result of implementing the design onto FPGA as mentioned in Chapter 3 and in Chapter 5.118 APPENDIX B IMPLEMENTATION RESULTS This Appendix contains the implementation report of the hardware designed. .

119 APPENDIX B.1 Transmitter (TX) .

2 Receiver (RX) .120 APPENDIX B.

121 APPENDIX B.3 Transmission (TX-RX) .

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