STUDY OF OP-AMP

An operational amplifier or op-amp is a linear integrated circuit that has a very high voltage
gain, high input impedance and low output impedance. Op-amp is basically a differential amplifier
whose basic function is to amplify the difference between two input signals.
Op-amp has five basic terminals, that is, two input terminals, one o/p terminal and two
power supply terminals. Pin2 is called the inverting input terminal and it gives opposite polarity at
the output if a signal is applied to it. It produces a phase shift of 180
o
between input and output.
Pin3 is called the non-inverting terminal that amplifies the input signal without inversion, i.e.,
there is no phase shift or i/p is in phase with o/p. The op-amp usually amplifies the difference
between the voltages applied to its two input terminals. Two further terminals pins 7 and 4 are
provided for the connection of positive and negative power supply voltages respectively.
Terminals 1 and 5 are used for dc offset. The pin 8 marked NC indicates ‘No Connection’.
S t u d y o f o p - a m p
B l o c k s c h e m a t i c o f o p - a m p
1
2
4
3
6
7
8
N o n I n v e r t i n g
i / p
N / C
O / p
V
+
O f f s e t N u l l
5
O f f s e t N u l l
I n v e r t i n g i / p
V
-
I C 7 4 1
D i f f
a m p
D i f f
a m p
B u f f e r & l e v e l
t r a n s l a t o r
O / p
d r i v e r
+
-
V 2
V 1
V 0
The block diagram of op-amp shows 2 difference amplifiers, a buffer for less loading, a
level translator for adjusting operating point to original level and o/p stage. An ideal op-amp
should have the following characteristics:
1. Infinite bandwidth
2. infinite input resistance
3. infinite open loop gain
4. zero output resistance
5. zero offset.
Op-amps have two operating configurations; open loop and closed loop. In open loop
configuration, it can operate as a switch but gain is uncontrolled. In closed loop configuration, gain
can controlled by feed back resistance Rf and input resistance Rin.
1
EX.No:1
LINEAR OP-AMP CIRCUITS
Aim:
To design Voltage Follower, Inverting and Non inverting, Differentiator, Integrator,
Subtractor, summing amplifier using op-amp and test its performance.
Apparatus required:
S.No Components Range Quantity
1. Op-amp IC 741 1
2. Dual trace supply (0-30) V 1
3. Function Generator (0-1) MHz 1
4. Resistors
5. Capacitors
6 CRO (0-30) MHz 1
1) Voltage Follower:
Design:
Vin = Vout [Unity Gain] & Rin = ∞ & Rf = 0
Circuit Diagram
2
- 1 2 V
V o
+
-
U 1
I C 7 4 1
3
2
6
7
4
I 1
1 V / 1 K H z
0
+ 1 2 V
2) Inverting amplifier: [Closed Loop Configuration]
Design:
A
CL
= V
o
/V
in
= - R
f
/ R
in
; Assume R
in
= ______; Gain = _______;
Circuit Diagram:
3) Non inverting amplifier: [Closed Loop Configuration]
Design:
A
CL
= V
o
/ V
in
= 1 + R
f
/ R
in;
Assume R
in
= ______; Gain = _______;
Circuit Diagram

3
C R O
+
~
+


+ 1 0 V
7
6
4
v 0
- 1 0 V
R F
I C 7 4 1
2
3
R i n
F . G
C R O
+
~
+


+ 1 0 V
7
6
4
v 0
- 1 0 V
2
3
R i n
F . G
( V )
V i n
V o
( V )
t ( s e c )
t ( s e c )
I n v e r t i n g a m p
4) Differentiator:
Design:
Step1: Select f
a
equal to the highest frequency of the input signal to be differentiated. Then
assuming a value of C
1
< 1µ F. Calculate the value of R
f
.
Step2: Choose f
b
= 20 f
a
and calculate the values of R
1
and C
f
so that R
1
C
1
= R
f
C
f
.
f
a
= KHz ; f
b
= KHz ;C
1
= 0.1 µf; R
COMP
= R
f
; R
L
= 10KΩ
f
a
= 1/ [2πR
f
C
1
]; R
f
= 1/2π C
1
f
a
; f
b
= 1/ [2πR
1
C
1
];R
1
= 1/2π C
1
f
b;
R
1
C
1
= R
f
C
f
; C
f
= R1C1/ R
f

Circuit Diagram

4
( V )
V i n
V o
( V )
t ( s e c )
t ( s e c )
N o n - I n v e r t i n g a m p
V i n
R L
R 1
+ 1 2 V
- 1 2 V
C f
R f
V o = - R f C 1 [ d V i n / d t ]
R o m
C 1
+
-
I C 7 4 1
3
2
6
7
4
0
R
COMP
Observation:
For sine wave input:
Peak to peak amplitude of the input = volts.
Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz
For square wave input:
Peak to peak amplitude of the input = volts.
Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz
Model Graph:
5) Integrator:
Design:
Generally the value of the f
a
and in turn R
1
C
f
and R
f
C
f
values should be selected such that f
a
< f
b
.
From the frequency response we can observe that f
a
is the frequency at which the gain is 0 db and
f
b
is the frequency at which the gain is limited. Maximum input signal frequency = 1 KHz.
Condition is time period of the input signal is larger than or equal to R
f
C
f
(i.e.) T
1 f
R C ≥
f
b
= KHz ; f
a
= f
b
/10; R
f
= 10R
1
; R
COMP
= R
1;
R
L &
R
1
= 10KΩ
f
a
= 1/ [2πR
f
C
f
]; Rf

C
f
= 1msec &; Cf = 1msec/100K
5
I V
V i n
V o
t
t
- I V
M o d e l g r a p h
2 V
- 2 V
I V
V i n
V o
t
t
- I V
M o d e l g r a p h
Circuit Diagram:
Observation:
For sine wave input:
Peak to peak amplitude of the input = volts.
Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz
For square wave input:
Peak to peak amplitude of the input = volts.
Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz
Model Graph:

6
V i n
V o
t
t
M o d e l g r a p h
t
t
V i n
R L
R 1
+ 1 2 V
- 1 2 V
R f
C f
R o m = R 1
+
-
I C 7 4 1
3
2
6
7
4
0
V
O
= - [1/R
1
C
f
] ∫Vin dt
R
COMP
6) Summing Amplifier : [Inverting]
Design: R
1
=R
2
=R
3
=R & R = R
f
= 4.7KΩ; R
L
= 10 KΩ; R
COMP
= R
1
|| R
2
|| R
3
|| R
f
V
O
= - R
f
/ R [V
1
+V
2
+V
3
]
Circuit Diagram
7) Subtractor : [Differential Configuration]
Design: R
1
=R
2
=R
3
=R
f
= R = __________
V
O
= R
f
/ R [V
2
– V
1
]

Circuit Diagram:

7
V 1
+ 1 2 V
+
-
I C 7 4 1
3
2
6
7
4
R L
V o = V 2 - V 1
V 2
R 3
R f
R 1
- 1 2 V
0
R 2
V 2
V 1 + 1 2 V
+
-
I C 7 4 1
3
2
6
7
4
R L
V o = - R f / R [ V 1 + V 2 + V 3 ]
R 2
R o m
R f
- 1 2 V
V 3
R 1
0
R 3
R
COMP
Procedure:
1. Connect the components as per the circuit diagram.
2. Set the input voltage using {F.G [for 1 to 5]. and DC Supply [for 6 & 7]}observe the output
waveform at Pin no.6
3. Connect CRO at Pin no.6 and measure 0/p voltage and note it down.
4. Plot the output waveforms
Viva Question:
1. What is an op-amp?
2. Give the characteristics of an ideal op-amp:
3. How a non-inverting amplifier can be courted into voltage follower?
4. What is the necessity of negative feedback?
5. What are 4 building blocks of an op-amp?
6. What is the purpose of shunting C
f
across R
f
and connecting R
1
in series with the input
signal?
7. What are the applications of Differentiator?
8. What do you mean by unity gain bandwidth?
9. What did you observe at the output when the signal frequency is increased above f
a
?
10. How would you eliminate the high frequency noise in integrator?
11. What are the main applications of the Integrator?
12. Is it possible to design an analog computer using integrator and differentiator?
13. What happens to the output of integrator when input signal frequency goes below f
a
?
Result:
Thus Voltage Follower, Inverting and Non inverting, Differentiator, Integrator, Subtractor,
summing amplifier using op-amp was designed and tested.
8
Ex.No.2
COMPARATOR CIRCUITS
Aim:
To design and test the following circuits, Zero crossing detector, Window detector and
Schmitt trigger using Op-amp
Apparatus Required.
S.No Component Range Quantity
1. Op amp IC 741 1
2. F.G (0-1) MHz 1
3. Resistors
4. CRO (0-30) MHz 1
5. DTS (0-30) V 1
6. Diode 1N4007 2
1) Zero Crossing Detector: [Sine wave to square wave converter]

Model Graph:
9
+ 1 2 V
D 2
+
-
I C 7 4 1
3
2
6
7
4
0
D 1
1 0 K
1 K
1 K
5 V / 1 K H z
- 1 2 V
V o
V i n
2) Window Detector:


Circuit Diagram:
Model Graph:
Condition Output
V
TL
< V
i
> V
TH
V
O
= V
CC
V
i
> V
TH
OR V
i
< V
TL
V
O
= 0
10
V
TH
Vi
V
TL
1 K
1 K
+ 1 2 V
0
0
1 K
1 K
+
-
L M 3 3 9
7
6
1
3
1
2
L M 3 3 9
5
4
3
1
2
2
V o
1 0 K
+ 1 2 V
Observation:
S.No V
TH
V
TL
V
i
V
o
1 6V 3V 5V/1KHz
2 3V 0V 5V/1KHz
3 0V 6V 5V/1KHz
3) Schmitt Trigger:
Design
V
CC
= 12 V; V
SAT
= 0.9 V
CC
; R1= 47KΩ; R2 = 120Ω
V
UT
= + [V
SAT
R
2
] / [R
1
+R
2
] & V
LT
= - [V
SAT
R
2
] / [R
1
+R
2
] & HYSTERSIS [H] = V
UT
- V
LT

Circuit Diagram
Model Graph
Procedure
11
V i n
+ 1 2 V
R 1
- 1 2 V
R 2
0
+
-
3
2
6
7
4
R L = 1 0 K
1. Connect the circuit as shown in the circuit
2. Set the input voltage as 5V (p-p) at 1KHz. (Input should be always less than V
cc
)
3. Note down the output voltage at CRO
4. To observe the phase difference between the input and the output, set the CRO in dual
Mode and switch the trigger source in CRO to CHI.
5. Plot the input and output waveforms on the graph.
Observation:
Peak to peak amplitude of the output = Volts.
Frequency = Hz.
Upper threshold voltage = Volts.
Lower threshold voltage = Volts.
Viva Questions:
1. What is Hysteresis? What parameter determines Hysteresis?
2. How would you recognize that positive feedback is being used in the Op-amp circuit?
3. What do you mean by upper and lower threshold voltage in Schmitt Trigger?
4. What is the difference between a basic comparator and the Schmitt trigger?
5. What is a sample and hold circuit? Why is it needed?
6. What is a voltage limiting, and why is it needed?
7. What is the name of the circuit that is used to detect the peak value of the Nonsinusoidal
input waveforms?
8. How will you produce, definite Hysteris in a Schmitt trigger using op-amp?
Result:
Thus comparator circuits using op-amp was designed & tested.
12
Ex. No 3
SAMPLE AND HOLD CIRCUITS
Aim
To construct Sample and Hold circuit using op-amp and plot its waveforms.
Apparatus Required:
S.No Component Range Quantity
1. Op amp IC 741 1
2. DTS (0-30) V 1
3. CRO 1
4. Resistor 1
5. Capacitors – –
6. JFET BFW 10 1
7. Function Generator (0-1) MHz 2
Circuit Diagram:

13
V
O
3
2
7
4
1
+
-
V
+
V
-
O U T
+ 1 2 V
B F W 1 0
0 . 1 m f d
0
5 V / 1 K H z
- 1 2 V
1 0 K
1 0 K
6
Model Graph

Procedure
1. Connect the circuit as shown in the circuit diagram.
2. Set the input Sine waveform as 5V/1 KHz at FG1
3. Set the square waveform as 10V/100KHz at FG 2
4. Note down the output voltage at CRO
5. Plot the input and output waveforms on the graph.
Result:
Thus the sample and hold circuit using Op-amp was constructed and tested.
14
Ex. No 4
Astable and Monostable Multivibrators using op-amp
Aim
To design Astable and monostable Multivibrators using op-amp and plot its waveforms.
Apparatus Required:
S.No Component Range Quantity
1. Op amp IC 741 1
2. DTS (0-30) V 1
3. CRO 1
4. Resistor 1
5. Capacitors – –
6. Diode IN4001 2
7. Probes – 1
Design:
1. Monostable Multivibrators:
β = R
2
/R
1
+R
2
[β = 0.5 & R
1
= 10 K]
Find R
2
= ; R3 = 1K; R4 = 10K;
Let F =_____KHz ; C= 1mfd; C4 = 0.1mfd
Pulse width, T = 0.69RC
Find R =
Circuit Diagram

15
C R O
+

+ 1 0 V
7
4
- 1 0 V
2
3
I C 7 4 1
R
V β s a t
C 4 D 2
R 4
D 1
C
V C
6
R 3
V O
R 1
R 2
V i n
Model graph:
Procedure:
1. Make the connections as shown in circuit diagram.
2. A trigger pulse is given through differentiator circuit through pin no.3
3. Observe the pulse waveform at pin no.6 using CRO and note down the time period.
4. Plot the waveform on the graph.
2. Astable Multivibrators:
Design:
T = 2RC
R
1
= 1.16 R
2
Given f
O
= _______KHz
Frequency of Oscillation fo = 1 / 2 RC if R
1
= 1.16R
2

Let R
2
= 10 KΩ
R
1
= 10 ∗ 1.16 · 11.6ΚΩ
Let C = 0.05 µ F
R = 1 / 2 fC = 1/ (2 ∗ 1 ∗ 10
3
∗ 0.05 ∗ 10
−6
) ·
16
V i n
V C
V O
V s a t
V β s a t
V D
t
t
t
T
– V s a t
T P
Circuit Diagram
Model graph

V o l t a g e i n v o l t s
V o l t a g e a c r o s s t h e c a p a c i t o r
t ( m s e )
v o
Procedure:
1. Make the connections as shown in the circuit diagram
2. Keep the CRO channel switch in ground and adjust the horizontal line on the x axis so that
it coincides with the central line.
3. Select the suitable voltage sensitivity and time base on the CRO.
4. Check for the correct polarity of the supply voltage to op-amp and switch on power supply
to the circuit.
5. Observe the waveform at the output and across the capacitor. Measure the frequency of
oscillation and the amplitude. Compare with the designed value.
6. Plot the Waveform on the graph.
17
2
+ 1 0 V
I C 7 4 1
R
+
C R O
C
3
– 1 0 V
1 0 K Ω
R 1
R 2
1 1 . 6 Ω
V O
4
7

6
1 0 k Ω
0 . 0 5 µ f
Questions:
1. What is other name for Astable Multivibrators?
2. How an Op-amp is used to generate square wave?
3. What are the changes to be done in a symmetric square wave generator to generate
asymmetric square wave?
Result:
Thus Astable & Monostable Multivibrators were designed using op-amp and the
waveforms were plotted.
18
EXP.NO: 5
MULTIVIBRATORS USING IC 555
Aim:
To design and test an Astable and Monostable Multivibrators using 555 timer with duty
cycles ratio.

Apparatus Required:
S.No Component Range Quantity
1. 555 TIMER 1
2. Resistors 3.3K, 6.8k 1
3. Capacitors 0.1
µ F, 0.01µ F
2
4. Diode In4001 1
5. CRO 1
6. Power supply
t 15 V
1
7. Probe 2
8. Bread Board 1
Astable Multivibrators using 555
Fig shows the 555 timer connected as an Astable Multivibrators. Initially, when the output
is high. Capacitor C starts charging towards V
cc
through R
A
and R
B
. As soon as capacitor voltage
equals 2/3 V
cc
upper comparator (UC) triggers the flip flop and the output switches low. Now
capacitor C starts discharging through R
B
and transistor Q
1
.
When the voltage across C equals 1/3 V
cc
lower comparator (LC), output triggers the flip-
flop and the output goes high. Then the cycle repeats.
The capacitor is periodically charged and discharged between 2/3 V
cc
and 1/3 V
cc
respectively. The time during which the capacitor charges form 1/3 V
cc
to 2/3 V
cc
is equal to the
time the output is high and is given by
T
c
= 0.69(R
A
+R
B
)C (1)
Where R
A
and R
B
are in Ohms and C is in farads. Similarly the time during which the
capacitor discharges from 2/3 V
cc
to 1/3 V
cc
is equal to the time the output is low and is given by
T
d
= 0.69 R
B
C (2)
19
The total period of the output waveform is
T = T
c
+ T
d
= 0.69 (R
A
+ 2R
B
) C (3)
The frequency of oscillation
f
o
=

1 / T =1.45 / (R
A
+2R
B
)C (4)
Eqn (4) shows that fo is independent of supply voltage Vcc
The duty cycle is the ratio of the time t
d
during which the output is low to the total time
period T. This definition is applicable to 555 Astable Multivibrators only; conventionally the duty
cycle ratio is defined as the ratio as the time during which the output is high to the total time
period.
∴ Duty cycle = t
d
T × 100
R
B
+ R
A
+ 2R
B
× 100 ( 5)
Τ ο obtain 50% duty cycle a diode should be connected across R
B
and R
A
must be a
combination of a fixed resistor and a potentiometer. So that the potentiometer can be adjusted for
the exact square waves
DESIGN:
Design an Astable Multivibrators for a frequency of ______KHz with a duty cycle ratio of
D = 50 %
fo = 1/T = 1.45 / (R
A
+2R
B
)C
Choosing C = 1 µ F; R
A
= 560
D = R
B
/ R
A
+2R
B
= 0.5 [50%]
R
B
= ______
Pin diagram:

20
V C C
D i s c h a r g e
T h r e s h o l d
C o n t r o l V o l t a g e
T r i g g e r
O u t p u t
R e s e t
G r o u n d
5 5 5 5
Circuit Diagram
Model Graph
21
V c
t ( m s )
V U T
V U T
t h i g h
t l o w
t ( m s )
V O
V O D
R A
6 . 8 k
V c c
+ 5 V
0 . 0 1 µ F
0 . 1 µ F
R B
3 . 3 k
7
2
6
1 5
8 4
3
5 5 5 5
Procedure:
1. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the designed value of
components.
2. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across
the timing capacitor. Set suitable voltage sensitively and time-base on the CRO.
3. Switch on the power supply to CRO and the circuit.
4. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure the
voltage levels at which the capacitor starts charging and discharging, output high and low
timings and frequency.
5. Switch off the power supply. Connect a diode across R
B
as shown in dashed lines in fig to
make the Astable with 50 % duty cycle ratio. Switch on the power supply. Observe the
output waveform. Draw to scale on a graph sheet.
Monostable Multivibrators using 555
Monostable Multivibrators has one stable state and other is a quasi stable state. The circuit
is useful for generating single output pulse at adjustable time duration in response to a triggering
signal. The width of the output pulse depends only on external components, resistor and a
capacitor.
The stable state is the output low and quasi stable state is the output high. In the stable state
transistor Q1 is ‘on’ and capacitor C is shorted out to ground. However upon application of a
negative trigger pulse to pin2, Q1 is turned ‘off’ which releases the short circuit across the external
capacitor C and drives the output high. The capacitor C now starts charging up towards V
cc
through R
A
. However when the voltage across C equal 2/3 V
cc
the upper comparator output
switches form low to high which in turn drives the output to its low state via the output of the flip
flop. At the same time the output of the flip flop turns Q1 ‘on’ and hence C rapidly discharges
through the transistor. The output remains low until a trigger is again applied. Then the cycle
repeats.
The pulse width of the trigger input must be smaller than the expected pulse width of the
output. The trigger pulse must be of negative going signal with amplitude larger than 1/3 Vcc. The
width of the output pulse is given by,
T = 1.1 R
A
C
22
Design:
Given a pulse width of duration of 100 µ s
Let C = 0.01 mfd; F = _________KHz
Here, T= 1.1 R
A
C
So, R
A
=
Circuit Diagram:

Model Diagram:
23
V O
R A
1 0 k
V c c
+ 5 V
0 . 0 1 µ F
0 . 1 µ F
7
6
1 5
8 4
3
5 5 5
2
T r i g g e r i / p
0 . 0 1 µ F
V c c
0 V
( i ) T r i g g e r i n p u t
( i i ) O u t p u t
( i i ) C a p a c i t o r
V o l t a g e
0 V
0 V
V c c
Procedure:
1. Rig-up the circuit of 555 monostable Multivibrators as shown in fig with the designed
value of components.
2. Connect the trigger input to pin 2 of 555 timer form the function generator.
3. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across
the timing capacitor. Set suitable voltage sensitively and time-base on the CRO.
4. Switch on the power supply to CRO and the circuit.
5. Observe the waveforms on the CRO and draw to scale on a graph sheet. Measure the
voltage levels at which the capacitor starts charging and discharging, output high and low
timings along with trigger pulse.
Questions:
1. What are the features of 555 timer?
2. What are the applications of 555 timer?
3. Define duty cycle ratio.
4. What are the applications of monostable Multivibrators?
5. What is meant by quasi stable state?
6. What should be the amplitude of trigger pulse?
Result:
Thus the Astable Multivibrators and Monostable Multivibrators using 555 timer is designed
and tested.
24
EX.No:6
DAC CONVERTORS
Aim:-
To design R-2R ladder type DAC using op-amp.
Components Required:-
S.No Components Range Quantity
1. Op-amp IC 741 1
2. Resistors
10KΩ ,20KΩ
1
3. DPDT(switch) 1
4. Dual Tracking Supply (0-30)V 1
5. Voltage Source (0-30)V 1
Theory:-
In R-2R ladder type D to A converter, only two values of resistor is used (i.e. R and 2R).
Hence it is suitable for integrated circuit fabrication. The typical values of R are from 2.5KΩ to
10KΩ . In this output voltage is a weighted sum of digital inputs. Since the resistive ladder is a
linear network, the principle of super position can be used to find the total analog output voltage
for a particular digital input by adding the output voltages caused by the individual digital inputs.
Circuit Diagram:-
4-Bit R/2R Ladder DAC:
2 R
R
+
-
L M 7 4 1 C
3
2
6
7 1
4 5
2 R
R
2 R
V R
2 R
R
R f = 1 2 k
R
V o
2 R
25
Design:-
Output voltage,
]
]
]
]

+ + + − ·
4
2
4
3
2
3
2
2
2
1
2
1
b b b b
R
f
R
R
V
o
V
Binary value=1000(given)
Output voltage=6v (given)
Reference resistor =10KΩ (given)
Reference Voltage, V
R
=10V (given)
∴ R
f
=12kΩ
Resolution,

f
R
R
R
V
n
V × × ·
2
1
Ω ×

× · k
k
V
V 12
10
10
4
2
1
75 . 0 · V
Questions:
1. Mention any two specifications of a DAC.
2. Name any two types of ADC.
3. In a binary ladder network of a DAC, the value of the smaller resistance is 10 kΩ .What
is the resistance value of the other set?
4. What output voltage would be produced by a DAC whose output range is 0 to 10V and
whose input binary number is 10 (for a 2 – bit DAC)?
5. What is the range value for resistor (R) in DAC?

Procedure:-
1. Connections are given as per the circuit diagram.
2. The power supply is switched on.
3. Reference voltage is set as 10V.
4. Binary values are applied according to the binary input values.
5. The output voltage is noted down.
6. The output voltage obtained is compared with the given output voltage.
Result:-
Thus the R-2R ladder type DAC was designed using Op-amp.
EX.No:7
26
FREQUENCY RESPONSE OF 2
nd
ORDER LPF & HPF
Aim:-
To design and test the frequency response of a second order LPF and HPF.
Components Required:-
S.No Components Range Quantity
1. Op-amp IC 741 1
2. Resistors
3. Capacitor
O.01µ f
2
4. CRO 1
5. Power Supply ± 15V 1
6. Probe 2
7. Bread Board 1
Theory:-
LPF:-
A LPF allows only low frequency signals up to a certain break-point f
H
to pass through,
while suppressing high frequency components. The range of frequency from 0 to higher cut off
frequency f
H
is called pass band and the range of frequencies beyond f
H
is called stop band.
The following steps are used for the design of active LPF.
1. The value of high cut off frequency f
H
is chosen.
2. The value of capacitor C is selected such that its value is ≤1µ F.
3. By knowing the values of f
H
and C, the value of R can be calculated using
RC
H
f
π 2
1
·
4. Finally the values of R
1
and R
f
are selected depending on the designed pass band gain
by using

,
`

.
|
+ ·
1
1
R
f
R
A
Circuit Diagram:-
27
Second Order LPF:
+ 1 0 V
+
-
L M 7 4 1 C
3
2
6
7 1
4 5
R = 7 . 9 5 k
R f = 1 0 k
R
0 . 0 1 u f
R = 7 . 9 5 k
F u n c t i o n g e n e r a t o r
- 1 0 V
V o
0 . 0 1 u f
R = 1 0 k
Design:-
Second order:-
Given frequency, f
H
= 2 KHz and gain =2
Let C=0.01µ f
The frequency, f
H
=

,
`

.
|

,
`

.
| −
× ×
6
10 01 . 0
3
10 2 2
1
π
Set,
R R R · ·
3 2

C C C · ·
3 2

RC
H
f
π 2
1
· ∴
Tabulation
Second order LPF Vin=1V
S.No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin)
28
Model graph:-
Second order HPF:
Theory:-
The high pass filter is the complement of the low pass filter. Thus the high pass filter can
be obtained by interchanging R and C in the circuit of low pass configuration. A high pass filter
allows only frequencies above a certain bread point to pass through and at terminates the low
frequency components. The range of frequencies beyond its lower cut off frequency f
L
is called
stop band.
Circuit Diagram:-
Second Order HPF:
29
+
-
L M 7 4 1 C
3
2
6
7 1
4 5
F u n c t i o n g e n e r a t o r
R = 1 0 k
0 . 0 1 u f
R f = 1 0 k
R
- 1 0 V
0 . 0 1 u f
R = 7 . 9 5 k R = 7 . 9 5 k
+ 1 0 V
V o
Design:-
) ( 10
1
2
1
1
95 . 7
3 2
2
1
3 2
3 2
3 2
3 2 3 2
2
1
2 ,
01 . 0
2
given k R
f
R
R
f
R
A
k R R
fLC
R R
C C C
R R R Let
C C R R
L
f
Av Gain
F C
HZ
L
f
Ω · · ∴
· + ·
Ω · ·
· ·
· ·
· ·
·
·
·
·
π
π
µ
K
Vin=1V
S.No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin)
30
Model graph:-
Procedure:-
LPF:-
1. Connections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the filter channels 1 and 2 of the CRO are connected.
4. Suitable voltage sensitivity and time-base on CRO is selected.
5. The correct polarity is checked.
6. The above steps are repeated for second order filter.
HPF
1. Connections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the filter channels 1 and 2 of the CRO are connected.
4. Suitable voltage sensitivity and time-base on CRO is selected.
5. The correct polarity is checked.
6. The above steps are repeated for second order filter.
Result:-
Thus the second order Low pass filter and High pass filter were designed using Op-amp
and its cut off frequency was determined.
EX.No:8
FREQENCY RESPONSE OF 2
nd
ORDER BSF & BPF
31
Aim:-
To design and test the frequency response of a second order LPF and HPF.
Components Required:-
S.No Components Range Quantity
1. Op-amp IC 741 3
2. Resistors
3. Capacitor
O.01µ f, O.05µ f
2
4. CRO 1
5. Power Supply ± 15V 1
6. Probe 2
7. Bread Board 1
Theory:-
BSF:-
BSF is the logical inverse of band pass filter which does not allows a specified range of
frequencies to pass through. It has two pass bands in the range of frequencies between 0 to f
L
and
beyond f
H
. The band between f
L
and f
H
is called stop band. BSF is also called Band Reject Filter
(BRF) or Band Elimination Filter (BEF).
BPF:-
The BPF is the combination of high and low pass filters and this allows a specified range of
frequencies to pass through. It has two stop bands in range of frequencies between 0 to f
L
and
beyond f
H
. The band b/w f
L
and f
H
is called pass band. Hence its bandwidth is (f
L
-f
H
). This filter
has a maximum gain at the resonant frequency (f
r)
which is defined as
L H r
f f f ·
The figure of merit (or) quality factor Q is given by
BW
f
f f
f
Q
r
L H
r
·

·
Circuit Diagram:-
BPF
32
C = 0 . 0 1
C
=
0
.
0
1
R f = 1 0
f n g e n
C = 0 . 0 1
R = 7 . 9 5
V o
R = 1 0
C
=
0
.
0
1
R = 1 0
R
=
7
.
9
5
R = 7 . 9 5
+
-
L M 7 4 1
3
2
6
7 1
4 5
R = 1 0
R = 1 0
R
=
7
.
9
5
+
-
L M 7 4 1
3
2
6
7 1
4 5
Design:-
BSF:-
f
H
=200Hz
f
L
=1kHz
Low pass section:-
f
H
=200Hz
Let C
1
=0.05µ f
Then,
f C
K R
R
c f
R
H
µ
π
π
05 . 0
9 . 15
) 10 05 . 0 )( 200 ( 2
1
2
1
1
1
6
1
1
1
·
Ω ·
×
·
·

High Pass Section:-
33
( )
ΚΩ ·
× ×
·
·
·
ΚΗΖ ·

9 . 15
10 01 . 0 10 1 ( 2
1
2
1
01 . 0
1
6 ) 3
R
C f
R
f C
f
L
L
π
π
µ
Gain, Av=2 for each section
ΚΩ · · · · ∴ 10
1 1
1 1 f f
R R R R
Model graph:-
BPF:-
Tabulation:-
BPF Vin=50mv
S.No Frequency (Hz) Vo(volts) Gain=20log(Vo/Vin)
34
Circuit Diagram:-
BSF
+
-
L M 7 4 1
3
2
6
7 1
4 5
+
-
L M 7 4 1
3
2
6
7 1
4 5
C
=
0
.
0
5
R = 1 0
C = 0 . 0 5
R = 1 5 . 9
R f = 1 0
R = 1 5 . 9
R
=
1
5
.
9
f n g e n
C = 0 . 0 1 C = 0 . 0 1
R
L
=
1
0
R = 1 0
R = 1 0
V o
R = 1 0
R = 3 . 3
R f = 1 0
R
=
1
5
.
9
R = 1 0
+
-
L M 7 4 1
3
2
6
7 1
4 5
Model graph:-
BSF:-
35
Tabulation:-
BSF
Vin=50mv
S.No Frequency (Hz) Vo(volts) Gain=20log(Vo/Vin)
Procedure:
BSF,BPF:-
1. The input signal is connected to the circuit from the signal generator.
2. The input and output signals are connected to the filter.
3. The suitable voltage is selected.
4. The correct polarity is checked.
5. The steps are repeated.
Result:-
Thus the frequency response of second order BPF and BSF filter was designed and tested.
EX.No:9
APPLICATION OF MULTIPLIER
36
Aim:-
To test the applications such as Analog divider, Squarer and square rooter using the
multiplier IC.
Components Required:-
S.No Component Range Quantity
1. Multiplier IC AD 633 1
2. Op-amp IC 741 1
3. Resistor
4. Powersupply ± 15V 1
5. Bread Board 1
6. CRO 1
Theory:-
Voltage Squarer:-
The inputs can be positive or negative represented by any corresponding voltage level
between o and 10V. The input voltage V
i
is to be squared is connected to both the input terminals
(ie V
x
=V
y
=V
i
) and the output is V
o
=KV
i
2
.
Voltage Divider:-
The voltage divider circuit is constructed by using a multiplier and an Op-amp. This circuit
produces the ratio of two input signals. The division is achieved by connecting the multiplier in
the feedback loop of an Op-amp. The voltages V
den
and V
num
represent the two input voltages. V
den
form one input of the multiplier and output of Op-amp V
OA
forms the second input. The output
V
om
of the multiplier is connected back to the inverting input terminal of Op-amp in the feedback
loop.
Square Rooter:-
The square root of a signal is determined by connecting both inputs of the multiplier to the
output of the Op-amp. Then, the output voltage of the multiplier V
om
is equal in magnitude but
opposite in polarity to V
i
. The input voltage V
i
must be negative otherwise the Op-amp saturates.
The range of V
i
is b/w-1v and -10v
i o
V V 10 ·
Thus, the V
O
is equal to the square root of 10times the absolute magnitude of V
i
.
Circuit Diagram:-
Voltage squarer:-
37
V o = K V i 2
X 1
f
n

g
e
n
Y 1
Observation:-
Input voltage amp time=
Output voltage amp time=
Voltage divider:-
+
-
-
+

X
X1
Y1
+
-
X2
Y2
38
R
=
1
0
+
-
L M 7 4 1
3
2
6
7 1
4 5
X
R = 1 0
V d e n
X 1
V o m
Y 2
V o
R
L
=
1
0
V m i n
Output VoA=-Vmin/Vden
Observation:-
Vmin voltage amp time=
Vden voltage amp time=
Square rooter:-
R
=
1
0
+
-
L M 7 4 1
3
2
6
7 1
4 5
X
R = 1 0
X 1
V i
Y 2
V o
R
L
=
1
0
| | 10 Vi
o
v ·
Observation:-
Input voltage amp time=
Output voltage amp time=
Procedure:
Voltage Squarer:-
1. Connections are given as per the circuit diagram.
2. Input is connected to the input terminals
3. Supply is connected to the corresponding terminals.
4. Output is noted down.
Voltage Divider:-
1. Connections are given as per the circuit diagram.
39
2. Input is applied to the input terminals.
3. Power supply is connected to the corresponding terminals.
4. Output is noted down.
Square Rooter:-
1. Connections are given as per the circuit diagram.
2. Input is applied to the input terminals.
3. Power supply is connected to the corresponding terminals.
4. Output is noted down.
Result:-
Thus the voltage Squarer, Voltage Divider and Square Rooter were tested using multiplier
IC.
EXP.NO.10:-
40

OSCILLATORS USING OPERATIONAL AMPLIFIER
Aim:
To design the following sine wave oscillators
a) Wein Bridge Oscillator with the frequency of 1 KHz.
b) RC Phase shift oscillator with the frequency of 200 Hz.
Components Required:
S.No Components Range Quantity
1. Op-amp IC 741 1
2. Dual trace supply (0-30) V 1
3. Function Generator (0-2) MHz 1
4. Resistors
5. Capacitors
6 CRO (0-30) MHz 1
7 Probes -- --
Equations Related to the Experiments:
a) Wein Bridge Oscillator
Closed loop gain A
v
= (1+R
f
/R
1
) = 3
Frequency of Oscillation f
a
= 1/(2π RC)
b) RC Phase shift Oscillator:
Gain A
v
= [R
f
/R
1
] = 29
Frequency of oscillation f
a
= 1 6 * 2 * * RC π
1) Wein Bridge Oscillator:
Design:
Gain required for sustained oscillation is A
v
= 1/β = 3
(PASS BAND GAIN) (i.e.) 1+R
f
/R
1
= 3
∴ R
f
= 2R
1
Frequency of Oscillation f
o
= 1/2π R C
Given f
o
= 1 KHz
Let C = 0.05 µ F
∴ R = 1/2 π f
o
C
R = 3.2 KΩ
Let R1 = 10 KΩ ∴ Rf = 2 * 10 KΩ
Model Graph:
41
t
+ V p
V O
– V p
Procedure:
1. Connect the components as shown in the circuit 5.1
Circuit 5.1:
C R O
+

+ 1 0 V
7
6
4
- 1 0 V
2
3
I C Y 4 1
R 1 = 1 0 k Ω
R f = 2 0 k Ω
3 . 2 k Ω
R
C
0 . 0 5 µ f
3 . 2 k Ω R =
C 0 . 0 5 µ f
V O
2. Switch on the power supply and CRO.
3. Note down the output voltage at CRO.
4. Plot the output waveform on the graph.
5. Redesign the circuit to generate the sine wave of frequency 2KHz.
6. Compare the output with the theoretical value of oscillation.
Observation:
Peak to peak amplitude of the output = Volts.
Frequency of oscillation = Hz.
Questions:
1. State the two conditions for oscillations.
42
2. Classify the Oscillators?
3. Define an oscillator?
4. What is the frequency range generated by Wein Bridge Oscillator?
5. What is frequency stability?
2) RC Phase Shift Oscillators:
Design:
Frequency of oscillation fo = 1/(√6*2*Π *RC)
Av = [Rf/R1] = 29
R
1
= 10 R
R
f
= 29 R
1
Given fo = 200 Hz.
Let C = 0.1µ F
( )
( )
6
R 1 / 6 * 2 * fo * C
1/ 6 * 2 * * 200 * 0.1*10
K
To prevent the loading of amplifier by RC network, R1 10R
R1 10 * K
Since Rf 29R1
Rf 29 *
M

· π
· π
· Ω

∴ · − − − − − − · Ω
·
· − − − − − −
· Ω
Model Graph:
V O
t
43
Procedure:
1. Connect the circuits as shown in the circuit 5.2
2. Switch on the power supply.
Circuit 5.2:
C R O
+

+ 1 0 V
7
6
4
- 1 0 V
2
3
I C 7 4 1
R 1
1 m Ω
3 . 3 k Ω
C
V O
0 . 0 1 µ f
C C
R R R 3 . 3 k Ω 3 . 3 k Ω
0 . 0 1 µ f
0 . 0 1 µ f
3 2 k Ω
3 3 k Ω
R f
D R B
3. Note down the output voltage on the CRO.
4. Plot the output waveforms on the graph.
5. Redesign the circuit to generate the sine wave of 1 KHz.
6. Plot the output waveform on the graph.
7. Compare the practical value of the frequency with the theoretical value.
Observation:
Peak to peak amplitude of the sine wave = Volts
Frequency of Oscillation (obtained) = Hz.
Questions:
1. What is the frequency range generated by RC phase shift Oscillator?
2. In RC phase shift oscillator how the total phase shift of 180° around the loop is achieved?
Result:
Thus wien bridge oscillator and RC Phase shift oscillator was designed using op-amp and
tested.
EXP.NO.11:- VOLTAGE REGULATION USING IC LM723
44
AIM :
To design a high current, low voltage and high voltage linear variable dc regulated power
supply and test its line and load regulation.
COMPONENTS REQUIRED :
S.NO COMPONENTS SPECIFICATION QUANTITY
1. Transistors TIP122,2N3055 1 each
2. Integrated Circuit LM723 1
3. Digital Ammeter ( 0 – 10 ) A 1
4. Digital Voltmeter ( 0 – 20 ) V 1
5. Variable Power Supply ( 0 – 30 ) V-2A 1
6. Resistors
300Ω ,430Ω ,1KΩ ,678KΩ ,67
8Ω
1Ω
1 each
2
7. Capacitors
0.1µ F,100pF
1 each
9. Rheostat
( 0 – 350 ) Ω
1
CIRCUIT DIAGRAM : Low Voltage Regulator
4 3 0
1 k
0 . 5
2 N 3 0 5 5
U n r e g u l a t e d
D C P o w e r
S u p p l y 1 2 1 1
6
5
R 1
R 2
V + V c
V o
C L
C S
I N V
C O M P V -
N I
V r e f
0 . 1
U F
T I P 1 2 2
1 0 0 p F
R s c
1 0
2
3
4
1 3 7
L o a d
A
+ -
V
+
-
Fig. 1.1
DESIGN:
Output voltage → V
O
Reference voltage→ Vref
45
LM723
Rprotect → Minimum Resistance to protect the output from short circuit.
Low Voltage Regulator :
Given : Vo=5V, Vref = 7.15 V
To calculate R1, R2 ,R3 and Rsc.
Vo

=

Vref ( R2 / ( R1 + R2 ) )
5 / 7.15 = ( R2 / ( R1 + R2 ) )
( R1 + R2 ) 0.699= R2
0.699R1 = 0.301 R2 , R1 = 0.4306 R2
Select R2 = 1 KΩ
R1 = 1 KΩ * 0.4306 = 430Ω
R1 = 430 Ω
R3 = R1 * R2 / ( R1 + R2) , R3 = 430.6 *1000 /(430.6+1000 )
R3 = 300Ω
Rsc = V
sense
/ I
limit
= 0.5 /1A = 0.5Ω , Rsc = 0.5Ω
CIRCUIT DIAGRAM : High Voltage Regulator :
Fig. 1.2
46
High Voltage Regulator :

Given : Vo=12V, Vref = 7.15 V
To calculate R1, R2 ,R3 and Rsc.
Vo

=

Vref ( 1 + (R1 / R2) )
12 / 7.15 = 1+ (R1 / R2)
(12 / 7.15) - 1 = (R1 / R2)
(R1 / R2) = 0.678
Select R2 = 1 KΩ
R1 = 1 KΩ * 0.678 = 678Ω
R1= 678Ω
Rsc = V
sense
/ I
limit
= 0.5 /1A = 0.5Ω
Rsc = 0.5Ω
Tabulation of the Measurements :
LOW VOLTAGE REGULATOR :
Line Regulation :
S.No. Load Resistance R
L1
= Load Resistance R
L2
= Load Resistance R
L3
=
Input
Voltage
Vin(Volts
)
Output
Voltage
V
L
(Volts)
Input
Voltage
Vin(Volts
)
Output
Voltage
V
L
(Volts)
Input
Voltage
Vin(Volts
)
Output
Voltage
V
L
(Volts)
Load Regulation :
S.No. Input Voltage V
in1
= Input Voltage V
in2
= Input Voltage V
in3
=
Output
Current
I
L
( A )
Output
Voltage
V
L
(Volts)
Output
Current
I
L
( A )
Output
Voltage
V
L
(Volts)
Output
Current
I
L
( A )
Output
Voltage
V
L
(Volts)
47
HIGH VOLTAGE REGULATOR :
Line Regulation :
S.No. Load Resistance R
L1
= Load Resistance R
L2
= Load Resistance R
L3
=
Input
Voltage
Vin(Volts
)
Output
Voltage
V
L
(Volts)
Input
Voltage
Vin(Volts
)
Output
Voltage
V
L
(Volts)
Input
Voltage
Vin(Volts
)
Output
Voltage
V
L
(Volts)
Load Regulation :
S.No. Input Voltage V
in1
= Input Voltage V
in2
= Input Voltage V
in3
=
Output
Current
I
L
( A )
Output
Voltage
V
L
(Volts)
Output
Current
I
L
( A )
Output
Voltage
V
L
(Volts)
Output
Current
I
L
( A )
Output
Voltage
V
L
(Volts)
Calculation of % Voltage Regulation :
% Voltage Regulation = ( V
dc
( NL ) - V
dc
( FL ) ) / V
dc
( FL )
V
dc
( NL ) = D.C. output voltage on no load
V
dc
( FL ) = D.C. output voltage on full load
Model Graph :
Line Regulation : Load Regulation :
Input Voltage Vs Output Voltage : Output Current Vs Output Voltage

I L
V 0 V 0
V
in
Load regulation Line regulation
48
PROCEDURE :
LOW VOLTAGE REGULATOR :
Line Regulation :
1. Give the circuit connection as per the circuit diagram shown in Fig 1.1.
2. Set the load Resistance to give load current of 0.25A.
3. Vary the input voltage from 7V to 18V and note down the corresponding output voltages.
4. Similarly set the load current ( I
L
) to 0.5A & 0.9A and make two more sets of
measurements.
Load Regulation :
1. Set the input voltage to 10V.
2. Vary the load resistance in equal steps from 350Ω to 5Ω and note down the corresponding
output voltage and load current.
3.Similarly set the input voltage ( Vin ) to 14V & 18V and make two more sets of
measurements.
Lab Report :
1.Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage (V
L
)
along Y-axis for various load currents.
2.Plot the load regulation by taking load current (I
L
) along X-axis and Output Voltage (V
L
)
along Y-axis for various input voltages.
3.Calculate its % Voltage Regulation using the formula.
HIGH VOLTAGE REGULATOR :
Line Regulation :
1.Give the circuit connection as per the circuit diagram shown in Fig 1.2.
2.Set the load Resistance to give load current I
L
of 0.25A.
3.Vary the input voltage from 7V to 18V and note down the corresponding output voltages.
4.Similarly set the load current ( I
L
) to 0.5A & 0.9A and make two more sets of
measurements.
49
Load Regulation :
1. Set the input voltage to 10V.
2. Vary the load resistance in equal steps from 350Ω to 15Ω and note down the corresponding
output voltage and load current.
3.Similarly set the input voltage ( Vin ) to 14V & 18V and make two more sets of
measurements.
Lab Report :
1.Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage (V
L
)
along Y-axis for various load currents.
2.Plot the load regulation by taking load current (I
L
) along X-axis and Output Voltage (V
L
)
along Y-axis for various input voltages.
3.Calculate its % Voltage Regulation using the formula.
Result :
Thus the line and load regulation of a high current, low voltage and high voltage linear variable
dc regulated power supply was designed and tested.
S.No Low Voltage Regulator High Voltage Regulator
% Voltage Regulation
Questions :
i) Why minimum protect resistance in load is required? What will happen if it is not there?
ii) Did you short circuit the output and check whether the short circuit protection is working?
iii) What will you do if you are asked to design both high and low voltage regulators in one
circuit?
iv) Give 10 example applications of the above circuits?
v) Why do you use a 100pF capacitor between 13 & 3,4?
50

EX.No:1

LINEAR OP-AMP CIRCUITS
Aim: To design Voltage Follower, Inverting and Non inverting, Differentiator, Integrator, Subtractor, summing amplifier using op-amp and test its performance. Apparatus required: S.No 1. 2. 3. 4. 5. 6 Components Op-amp Dual trace supply Function Generator Resistors Capacitors CRO Range IC 741 (0-30) V (0-1) MHz (0-30) MHz Quantity 1 1 1 1

1) Voltage Follower: Design: Vin = Vout [Unity Gain] & Rin = ∞ & Rf = 0 Circuit Diagram

2 3 I 1 1 V / 1 K H z

+ I C 4

7

+ 1 2 V U 1 6 7 4 V o 1

- 1 2 V

0

2

2) Inverting amplifier: [Closed Loop Configuration] Design: ACL = Vo/Vin = - Rf / Rin; Assume Rin = ______; Gain = _______; Circuit Diagram:
R F

R

+ 1 0 V
in

2 3

– I C +

7 6 7 4 1 4 - 1 0 V C R O v
0

+ F . G ~ –

I n v e r t in g V
i n

a m

p

( V )

t ( s e c )

Vo ( V ) t ( s e c )

3) Non inverting amplifier: [Closed Loop Configuration] Design: ACL = Vo / Vin = 1 + Rf / Rin; Assume Rin = ______; Gain = _______; Circuit Diagram

R

+ 1 0 V
i n

2 3 + F . G ~ –

– +

7 6 4 - 1 0 V C R O v0

3

N V
i n

o n - I n v e r t i n g

a m

p

( V )

t ( s e c )

Vo ( V )

t ( s e c )

4) Differentiator: Design: Step1: Select fa equal to the highest frequency of the input signal to be differentiated. Then assuming a value of C1 < 1µ F. Calculate the value of Rf. Step2: Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf. fa = KHz ; fb = KHz ;C1 = 0.1 µf; RCOMP = Rf ; RL = 10KΩ

fa = 1/ [2πRfC1]; Rf = 1/2π C1 fa ; fb = 1/ [2πR1C1];R1 = 1/2π C1 fb;R1C1 = Rf Cf; Cf = R1C1/ Rf Circuit Diagram
C f

R

1

C

1

R

f

+ 1 2 V V i n 2 3 7 + I C 4 - 1 2 V

6 7 4 1

V o

=

- R f

C 1 [ d V i n / d t ]

RCOM P

R

o m

R

L

0

4

Observation: For sine wave input: Peak to peak amplitude of the input = Frequency of the input Frequency of the output For square wave input: Peak to peak amplitude of the input = Frequency of the input Frequency of the output Model Graph:
V
M Vin I V o d e l g r a p h

volts. Hz volts. Hz volts. Hz volts. Hz
M
in

= =

Peak to peak amplitude of the output =

= =

Peak to peak amplitude of the output =

o d e l g r a p h

I V

t
t

- I V
- I V

2 V
V
o

V

o

t
t

- 2 V

5) Integrator: Design: Generally the value of the fa and in turn R1Cf and Rf Cf values should be selected such that fa < fb. From the frequency response we can observe that fa is the frequency at which the gain is 0 db and fb is the frequency at which the gain is limited. Maximum input signal frequency = 1 KHz. Condition is time period of the input signal is larger than or equal to Rf Cf (i.e.) T ≥ R1Cf fb = KHz ; fa = fb/10; Rf = 10R1; RCOMP = R1; RL & R1 = 10KΩ

fa = 1/ [2πRfCf];

Rf Cf = 1msec &; Cf = 1msec/100K

5

1 2 V 6 7 4 1 R VO = . Hz volts. Hz volts. Hz volts. Hz = = Peak to peak amplitude of the output = = = Peak to peak amplitude of the output = o d e l g r a p h t t V o t t 6 .[1/R1Cf] ∫Vin dt L RCOM RP Observation: For sine wave input: o m = R 0 Peak to peak amplitude of the input = Frequency of the input Frequency of the output For square wave input: Peak to peak amplitude of the input = Frequency of the input Frequency of the output Model Graph: V M i n volts.Circuit Diagram: C f R 1 R f + 1 2 V V i n 2 3 7 + 1 I C 4 .

1 2 V V o 7 4 1 R L = - R f / R [ V 1 + V 2 + V 3 ] RCOMR P o m 0 7) Subtractor: [Differential Configuration] Design: R1=R2=R3=Rf = R = __________ VO = Rf / R [V2 – V1] Circuit Diagram: V 1 R 1 R f + 1 2 V 2 V 2 R 2 3 7 + I C 4 .7KΩ. RL = 10 KΩ.1 2 V 6 7 4 R V o 1 L = V 2 - V 1 R 3 0 7 .6) Summing Amplifier: [Inverting] Design: R1=R2=R3=R & R = Rf = 4.Rf / R [V1+V2+V3] Circuit Diagram R f V 1 V 2 V 3 R R R 1 2 3 2 3 + + 1 2 V 7 6 I C 4 . RCOMP = R1 || R2 || R3 || Rf VO = .

What happens to the output of integrator when input signal frequency goes below fa? Result: Thus Voltage Follower. What are the main applications of the Integrator? 12.6 and measure 0/p voltage and note it down. Is it possible to design an analog computer using integrator and differentiator? 13. How a non-inverting amplifier can be courted into voltage follower? 4. What did you observe at the output when the signal frequency is increased above fa? 10.6 3.G [for 1 to 5]. Plot the output waveforms Viva Question: 1. Connect the components as per the circuit diagram.Procedure: 1. Give the characteristics of an ideal op-amp: 3. What do you mean by unity gain bandwidth? 9. 8 . 2. Integrator. Inverting and Non inverting. What is the necessity of negative feedback? 5. summing amplifier using op-amp was designed and tested. What is an op-amp? 2. Differentiator. and DC Supply [for 6 & 7]}observe the output waveform at Pin no. 4. What are 4 building blocks of an op-amp? 6. How would you eliminate the high frequency noise in integrator? 11. What are the applications of Differentiator? 8. Connect CRO at Pin no. Subtractor. What is the purpose of shunting Cf across Rf and connecting R1 in series with the input signal? 7. Set the input voltage using {F.

1 2 V 0 Model Graph: 9 . 4.2 COMPARATOR CIRCUITS Aim: To design and test the following circuits. 6. 3. 5.Ex. Window detector and Schmitt trigger using Op-amp Apparatus Required.G Resistors CRO DTS Diode Range IC 741 (0-1) MHz (0-30) MHz (0-30) V 1N4007 Quantity 1 1 1 1 2 1) Zero Crossing Detector: [Sine wave to square wave converter] + 1 2 V 1 K 2 D V in 5 V / 1 K H z 1 K 1 D 2 3 + I C 4 7 6 7 V o 4 1 1 0 K .No 1.No. Component Op amp F. 2. S. Zero crossing detector.

2) Window Detector: Condition VTL < Vi > VTH Vi > VTH OR Vi < VTL Output VO= VCC VO = 0 Circuit Diagram: + 1 2 V 1 K VTH 1 K 7 6 3 + L M 12 3 3 9 1 Vi 1 K 0 5 L M 1 K 3 + 1 2 V 3 3 9 2 V o VTL 4 12 1 0 K 0 Model Graph: 10 .

Observation: S.9 VCC.[VSAT R2] / [R1+R2] & HYSTERSIS [H] = VUT .VLT Circuit Diagram VTH 6V 3V 0V VTL 3V 0V 6V Vi 5V/1KHz 5V/1KHz 5V/1KHz Vo + 1 2 2 3 7 V + 4 6 V i n R 1 .No 1 2 3 3) Schmitt Trigger: Design VCC = 12 V. R2 = 120Ω VUT = + [VSAT R2] / [R1+R2] & VLT = . R1= 47KΩ.1 2 V R 2 R L = 1 0 K 0 Model Graph Procedure 11 . VSAT = 0.

= Volts. What is the difference between a basic comparator and the Schmitt trigger? 5. Plot the input and output waveforms on the graph.1. What is a voltage limiting. What is Hysteresis? What parameter determines Hysteresis? 2. Set the input voltage as 5V (p-p) at 1KHz. definite Hysteris in a Schmitt trigger using op-amp? Result: Thus comparator circuits using op-amp was designed & tested. How will you produce. Note down the output voltage at CRO 4. What is the name of the circuit that is used to detect the peak value of the Nonsinusoidal input waveforms? 8. Hz. 5. To observe the phase difference between the input and the output. set the CRO in dual Mode and switch the trigger source in CRO to CHI. Volts. and why is it needed? 7. 12 . Connect the circuit as shown in the circuit 2. Observation: Peak to peak amplitude of the output = Frequency = Upper threshold voltage = Lower threshold voltage Viva Questions: 1. How would you recognize that positive feedback is being used in the Op-amp circuit? 3. What do you mean by upper and lower threshold voltage in Schmitt Trigger? 4. (Input should be always less than Vcc) 3. Volts. What is a sample and hold circuit? Why is it needed? 6.

Ex. 5. 3.1 2 0 4 13 . No 3 SAMPLE AND HOLD CIRCUITS Aim To construct Sample and Hold circuit using op-amp and plot its waveforms. 7. 4. 2.No 1. 6. Circuit Diagram: Component Op amp DTS CRO Resistor Capacitors JFET Function Generator Range IC 741 (0-30) V – BFW 10 (0-1) MHz Quantity 1 1 1 1 – 1 2 B F W 1 0 1 0 K + 1 2 V VO V+ 3 + 7 O 5 V / 1 K H z 0 . 1 m f d V2 - U 6 1 T 1 V 0 K . Apparatus Required: S.

Note down the output voltage at CRO 5. Set the square waveform as 10V/100KHz at FG 2 4. Connect the circuit as shown in the circuit diagram. 2. 14 . Set the input Sine waveform as 5V/1 KHz at FG1 3. Result: Thus the sample and hold circuit using Op-amp was constructed and tested.Model Graph Procedure 1. Plot the input and output waveforms on the graph.

4. Apparatus Required: S.No 1.5 & R1 = 10 K] Find R2 = . R4 = 10K.1mfd Pulse width. 2. 7. No 4 Astable and Monostable Multivibrators using op-amp Aim To design Astable and monostable Multivibrators using op-amp and plot its waveforms. T = 0.1 0 V 1 C R O C V i n 4 D 2 V βs R a t R 2 4 15 . 5. R3 = 1K. Monostable Multivibrators: β = R2/R1+R2 [β = 0. 6. 3. Let F =_____KHz . C4 = 0.69RC Find R = Circuit Diagram R Component Op amp DTS CRO Resistor Capacitors Diode Probes Range IC 741 (0-30) V – IN4001 – Quantity 1 1 1 1 – 2 1 + 1 0 V V D 1 C 2 – I C + 7 7 4 1 4 6 R 3 V O C 3 R .Ex. C= 1mfd. Design: 1.

Astable Multivibrators: Design: T = 2RC R1= 1.16R2 Let R2 = 10 KΩ R1 = 10 ∗ 1.05 µ F R = 1 / 2 fC = 1/ (2 ∗ 1 ∗ 10 ∗ 0.6 using CRO and note down the time period. A trigger pulse is given through differentiator circuit through pin no.16 = 1 1.Model graph: V t i n T P V D V C t V βs a t V s a t t V O – Vs a t T Procedure: 1. 2.16 R2 Given fO = _______KHz Frequency of Oscillation fo = 1 / 2 RC if R1 = 1. Observe the pulse waveform at pin no.6 Κ Ω Let C = 0. 4. 2.05 ∗ 10 ) = 3 −6 16 . Make the connections as shown in circuit diagram.3 3. Plot the waveform on the graph.

Compare with the designed value. 6 V C R O – O R 21 0 Ω k Model graph V o l t a g e in v o l t s vo V o l t a g e a c r o s s t h e c a p a c i t o r t ( m s e ) Procedure: 1. Measure the frequency of oscillation and the amplitude. 5. 0f 5 µ 2 R + 1 0 V 7 6 I C 3 + 7 4 1 4 – 1 0 V R 1 1 1 Ω. Observe the waveform at the output and across the capacitor. 3.Circuit Diagram 1 0 ΩK C 0 . Make the connections as shown in the circuit diagram 2. 4. 17 . 6. Check for the correct polarity of the supply voltage to op-amp and switch on power supply to the circuit. Plot the Waveform on the graph. Select the suitable voltage sensitivity and time base on the CRO. Keep the CRO channel switch in ground and adjust the horizontal line on the x axis so that it coincides with the central line.

Questions: 1. How an Op-amp is used to generate square wave? 3. 18 . What are the changes to be done in a symmetric square wave generator to generate asymmetric square wave? Result: Thus Astable & Monostable Multivibrators were designed using op-amp and the waveforms were plotted. What is other name for Astable Multivibrators? 2.

3K. The capacitor is periodically charged and discharged between 2/3 Vcc and 1/3 Vcc respectively.69 RB C (2) 19 . 3. Apparatus Required: S. Now capacitor C starts discharging through RB and transistor Q1. 8. 5. 7.69(RA+RB)C (1) Where RA and RB are in Ohms and C is in farads. Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by Td = 0. Then the cycle repeats. Initially.EXP. when the output is high. Capacitor C starts charging towards Vcc through RA and RB.No 1.NO: 5 MULTIVIBRATORS USING IC 555 Aim: To design and test an Astable and Monostable Multivibrators using 555 timer with duty cycles ratio. As soon as capacitor voltage equals 2/3 Vcc upper comparator (UC) triggers the flip flop and the output switches low. 6. The time during which the capacitor charges form 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by Tc = 0. 4.01µ F In4001 ± 15 V Quantity 1 1 2 1 1 1 2 1 Astable Multivibrators using 555 Fig shows the 555 timer connected as an Astable Multivibrators.1 µ F. Component 555 TIMER Resistors Capacitors Diode CRO Power supply Probe Bread Board Range 3. 2. 0. output triggers the flipflop and the output goes high. When the voltage across C equals 1/3 Vcc lower comparator (LC). 6.8k 0.

This definition is applicable to 555 Astable Multivibrators only. ∴ Duty cycle Το = td T × 100 (5) RB + RA+ 2RB × 100 obtain 50% duty cycle a diode should be connected across RB and RA must be a combination of a fixed resistor and a potentiometer.69 (RA + 2RB) C (4) (3) The frequency of oscillation fo = 1 / T =1.The total period of the output waveform is T = T c + T d = 0. So that the potentiometer can be adjusted for the exact square waves DESIGN: Design an Astable Multivibrators for a frequency of ______KHz with a duty cycle ratio of D = 50 % fo = 1/T = 1.45 / (RA+2RB)C Eqn (4) shows that fo is independent of supply voltage Vcc The duty cycle is the ratio of the time td during which the output is low to the total time period T.5 [50%] RB = ______ Pin diagram: G r o u n d V D C C T r i g g e r i s c h a r g e 5 5 5 5 O R u t p u t T C h r e s h o o n t r o l l d V o l t a g e e s e t 20 . conventionally the duty cycle ratio is defined as the ratio as the time during which the output is high to the total time period.45 / (RA+2RB)C Choosing C = 1 µ F. RA = 560 D = RB / RA +2RB= 0.

µF 1 0 . 0µ F 1 Model Graph V c V U T V U T t ( m s ) V O t h i g h tl o w t ( m s ) 21 .Circuit Diagram V c c + 5 V R A 6 . 8 k 8 7 D R B 3 . 3 k 3 V O 4 5 5 5 5 2 6 1 5 0 .

Draw to scale on a graph sheet. The circuit is useful for generating single output pulse at adjustable time duration in response to a triggering signal. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across the timing capacitor. 3. T = 1. In the stable state transistor Q1 is ‘on’ and capacitor C is shorted out to ground. Observe the waveforms on the CRO and draw to scale on a graph sheet. The pulse width of the trigger input must be smaller than the expected pulse width of the output. Monostable Multivibrators using 555 Monostable Multivibrators has one stable state and other is a quasi stable state. 5. Set suitable voltage sensitively and time-base on the CRO. Q1 is turned ‘off’ which releases the short circuit across the external capacitor C and drives the output high. output high and low timings and frequency. The capacitor C now starts charging up towards V cc through RA. The output remains low until a trigger is again applied.Procedure: 1. Switch on the power supply to CRO and the circuit. The trigger pulse must be of negative going signal with amplitude larger than 1/3 Vcc. Observe the output waveform. resistor and a capacitor. The width of the output pulse is given by. The stable state is the output low and quasi stable state is the output high.1 RAC 22 . However when the voltage across C equal 2/3 Vcc the upper comparator output switches form low to high which in turn drives the output to its low state via the output of the flip flop. The width of the output pulse depends only on external components. Switch off the power supply. Measure the voltage levels at which the capacitor starts charging and discharging. Connect a diode across RB as shown in dashed lines in fig to make the Astable with 50 % duty cycle ratio. At the same time the output of the flip flop turns Q1 ‘on’ and hence C rapidly discharges through the transistor. 2. However upon application of a negative trigger pulse to pin2. 4. Switch on the power supply. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the designed value of components. Then the cycle repeats.

0µ F 1 Model Diagram: V c c ( i ) T r i g g e r i n p u t 0 V V 0 c c V ( i i ) O u t p u t ( i i ) C a p a c i t o r V o l t a g e 0 V 23 . µF 1 5 i / p 0 .1 RAC So. F = _________KHz Here.01 mfd.Design: Given a pulse width of duration of 100 µ s Let C = 0. T= 1. 0µ F 1 1 0 k 8 7 3 V O 4 5 5 5 2 T r i g g e r 6 1 0 . RA = Circuit Diagram: V c c + 5 V R A 0 .

output high and low timings along with trigger pulse. Connect the trigger input to pin 2 of 555 timer form the function generator. Measure the voltage levels at which the capacitor starts charging and discharging. Observe the waveforms on the CRO and draw to scale on a graph sheet. 4. 24 . 5. Rig-up the circuit of 555 monostable Multivibrators as shown in fig with the designed value of components. Set suitable voltage sensitively and time-base on the CRO.Procedure: 1. Define duty cycle ratio. Switch on the power supply to CRO and the circuit. Connect the CRO probes to pin 3 and 2 to display the output signal and the voltage across the timing capacitor. What are the features of 555 timer? 2. What are the applications of monostable Multivibrators? 5. 2. What should be the amplitude of trigger pulse? Result: Thus the Astable Multivibrators and Monostable Multivibrators using 555 timer is designed and tested. 3. What are the applications of 555 timer? 3. Questions: 1. What is meant by quasi stable state? 6. 4.

The typical values of R are from 2. Since the resistive ladder is a linear network. 2. Components Required:S.No 1.5KΩ to 10KΩ . In this output voltage is a weighted sum of digital inputs. Components Op-amp Resistors DPDT(switch) Dual Tracking Supply Voltage Source Range IC 741 10KΩ . the principle of super position can be used to find the total analog output voltage for a particular digital input by adding the output voltages caused by the individual digital inputs. Circuit Diagram:4-Bit R/2R Ladder DAC: V R R f = 1 2 k 2 R 2 R 2 R 2 R 2 4 5 R L M 7 4 1 2 R R R R 7 1 + 3 6 C V o 25 . 4.No:6 DAC CONVERTORS Aim:To design R-2R ladder type DAC using op-amp.EX. 3.e.20KΩ (0-30)V (0-30)V Quantity 1 1 1 1 1 Theory:In R-2R ladder type D to A converter. 5. Hence it is suitable for integrated circuit fabrication. only two values of resistor is used (i. R and 2R).

The power supply is switched on. The output voltage obtained is compared with the given output voltage.75 1. The output voltage is noted down. In a binary ladder network of a DAC.No:7 26 . 3. What is the range value for resistor (R) in DAC? Procedure:1. 2. Connections are given as per the circuit diagram.Design:- Output voltage. Result:Thus the R-2R ladder type DAC was designed using Op-amp. 3. 2. Vo = −V R R R f  b1 b2 b3 b4    + + +  21 2 2 23 2 4    Binary value=1000(given) Output voltage=6v (given) Reference resistor =10KΩ (given) Reference Voltage. VR=10V (given) ∴ Rf =12kΩ Resolution.What is the resistance value of the other set? 4. 1 VR × ×R f 2n R 1 10V V = × ×12 kΩ 4 10 kΩ 2 V= Questions: V = 0. 6. Reference voltage is set as 10V. EX. the value of the smaller resistance is 10 kΩ . Name any two types of ADC. Binary values are applied according to the binary input values. 4. Mention any two specifications of a DAC. What output voltage would be produced by a DAC whose output range is 0 to 10V and whose input binary number is 10 (for a 2 – bit DAC)? 5. 5.

while suppressing high frequency components. 3.FREQUENCY RESPONSE OF 2nd ORDER LPF & HPF Aim:To design and test the frequency response of a second order LPF and HPF. 4. 3. 1. The range of frequency from 0 to higher cut off frequency fH is called pass band and the range of frequencies beyond fH is called stop band. The value of high cut off frequency fH is chosen.01µ f ± 15V Quantity 1 2 1 1 2 1 f H = 4. The value of capacitor C is selected such that its value is ≤1µ F. By knowing the values of fH and C. 2. The following steps are used for the design of active LPF. Theory:LPF:A LPF allows only low frequency signals up to a certain break-point fH to pass through. 5. 7. Finally the values of R1 and Rf are selected depending on the designed pass band gain R   f  by using A =1 + R   1    1 2πRC Circuit Diagram:27 . 6.No 1. Components Required:S. the value of R can be calculated using Components Op-amp Resistors Capacitor CRO Power Supply Probe Bread Board Range IC 741 O. 2.

1 0 V R = 1 0 k 2 R = 7 .No Frequency (Hz) O/p voltage(v) Vin=1V Gain=Vo/Vin Gain=20log(Vo/Vin) + 28 .01 × −  10  10 6      Set. 0 1 u f 7 1 + 1 0 V Design:Second order:Given frequency. 9 5 kR = 7 .Second Order LPF: R f = 1 0 k . R2 = R3 = R C =C =C 2 3 ∴f H = 1 2πRC Tabulation Second order LPF S. fH = 2 KHz and gain =2 Let C=0.01µ f 1 The frequency. 9 5 f k 3 4 5 L M 7 R 6 4 1 C V o 0 . 0 1 u F u n c t i o n g e n e r a t o r 0 . fH = 2π 2 × 3 0.

Model graph:- Second order HPF: Theory:The high pass filter is the complement of the low pass filter. A high pass filter allows only frequencies above a certain bread point to pass through and at terminates the low frequency components. The range of frequencies beyond its lower cut off frequency fL is called stop band. Thus the high pass filter can be obtained by interchanging R and C in the circuit of low pass configuration. Circuit Diagram:Second Order HPF: 29 .

0 1 u f 0 .01 µ F G ain .95 kΩ 2 3 A =1 + ∴R R f =2 R 1 f = R =10 kΩ given ) ( 1 Vin=1V S. 9 5R k = .R f = 1 0 k .No Frequency (Hz) O/p voltage(v) Gain=Vo/Vin Gain=20log(Vo/Vin) 30 + . 9 5 k + 1 0 V 7 1 Design:- f L = 2KH Z C = 0. 0 1 u f L M 7 4 1 6 C V o F u n c t io n g e n e r a t o r R = 7 . Av = 2 f L = 1 2π R R C C 2 3 2 3 Let R = R = R 2 3 C =C =C 2 3 1 R =R = 2 3 2π fLC R = R = 7.1 0 V R = 1 0 k 2 3 7 4 5 R 0 .

3. EX. The input and output signals of the filter channels 1 and 2 of the CRO are connected. 5. 5. Input signal is connected to the circuit from the signal generator. Suitable voltage sensitivity and time-base on CRO is selected.No:8 FREQENCY RESPONSE OF 2nd ORDER BSF & BPF 31 . The correct polarity is checked. HPF 1. Input signal is connected to the circuit from the signal generator. The correct polarity is checked. The above steps are repeated for second order filter. 4. 2. Connections are given as per the circuit diagram. 3. 6.Model graph:- Procedure:LPF:1. 2. The input and output signals of the filter channels 1 and 2 of the CRO are connected. Suitable voltage sensitivity and time-base on CRO is selected. Connections are given as per the circuit diagram. 6. 4. Result:Thus the second order Low pass filter and High pass filter were designed using Op-amp and its cut off frequency was determined. The above steps are repeated for second order filter.

Components Required:S.01µ f.05µ f ± 15V Quantity 3 2 1 1 2 1 The figure of merit (or) quality factor Q is given by Q= fr f = r f H − f L BW Circuit Diagram:BPF 32 . 4. 6. Theory:BSF:BSF is the logical inverse of band pass filter which does not allows a specified range of frequencies to pass through. 2. The band between fL and fH is called stop band. 5. 7. It has two stop bands in range of frequencies between 0 to fL and beyond fH. Hence its bandwidth is (fL-fH). BPF:The BPF is the combination of high and low pass filters and this allows a specified range of frequencies to pass through. BSF is also called Band Reject Filter (BRF) or Band Elimination Filter (BEF). It has two pass bands in the range of frequencies between 0 to fL and beyond fH .No 1. 3. This filter has a maximum gain at the resonant frequency (fr) which is defined as fr = fH fL Components Op-amp Resistors Capacitor CRO Power Supply Probe Bread Board Range IC 741 O. O. The band b/w fL and fH is called pass band.Aim:To design and test the frequency response of a second order LPF and HPF.

9 KΩ C 1 = 0. 0 3 .R f = 1 0 R = 1 0 R = 1 0 R = 1 0 R = R7 . =9 75 .0 1 7 1 M 2 3 4 5 4 5 6 7 4 R 1 V o = 1 0 C R = 7 . 9 5 + L C = 0 .1 0 L 1 6 M 7 4 1 33 .0 1 + 2 =C 0 = . R1 = R1 = 1 2π H c1 f 1 2π( 200 )( 0.05 ×10 −6 ) R1 =15 .05µ f Then.05 µf High Pass Section:- R = 7 .9 5 7 1 f n g e n C = 0 .9 5 Design:BSF:fH=200Hz fL=1kHz Low pass section:fH=200Hz Let C1=0.

No Frequency (Hz) Vo(volts) Vin=50mv Gain=20log(Vo/Vin) 34 .9ΚΩ ( ) Model graph:BPF:- Tabulation:BPF S. Av=2 for each section 1 ∴R1 = R f = R1 = R1 =10 Κ Ω f 1 2π (1×10 0.01µf R= = 1 2πf L C 3) Gain.01 ×10 −6 R = 15 .f L = 1ΚΗΖ C = 0.

3 7 1 R = 1 0 7 1 R f = 1 0 Model graph:BSF:35 R L=10 + 3 - 2 4 5 + L M + 2 = C . 9 2 C = 0 . 0 5R .0 5 3 4 5 6 L M 7 4 1 R = 1 0 = 3 .9 R = 1 5 .Circuit Diagram:BSF R f = 1 0 R = 1 0 4 5 C 1 R = 1 5 . 9= 1 5 5 . = 0 01 . 0 0 3 6 R 7 4 1 = 1 0 R = 1 0 6 L M 7 V o 4 1 .9 7 1 R f n g e n R C = = 1 0 .

5.No Frequency (Hz) Vo(volts) Vin=50mv Gain=20log(Vo/Vin) Procedure: BSF. 4. Result:Thus the frequency response of second order BPF and BSF filter was designed and tested. The input and output signals are connected to the filter. 2. The correct polarity is checked. The input signal is connected to the circuit from the signal generator.Tabulation:BSF S.No:9 APPLICATION OF MULTIPLIER 36 . 3. The suitable voltage is selected. EX.BPF:1. The steps are repeated.

Aim:To test the applications such as Analog divider. Component Multiplier IC Op-amp Resistor Powersupply Bread Board CRO Range AD 633 IC 741 ± 15V Quantity 1 1 1 1 1 Theory:Voltage Squarer:The inputs can be positive or negative represented by any corresponding voltage level between o and 10V. Squarer and square rooter using the multiplier IC. 5. The output Vom of the multiplier is connected back to the inverting input terminal of Op-amp in the feedback loop. 2. This circuit produces the ratio of two input signals. the output voltage of the multiplier Vom is equal in magnitude but opposite in polarity to Vi. Square Rooter:The square root of a signal is determined by connecting both inputs of the multiplier to the output of the Op-amp. Circuit Diagram:Voltage squarer:- 37 . 4. 6. The input voltage Vi must be negative otherwise the Op-amp saturates. Vden form one input of the multiplier and output of Op-amp VOA forms the second input.No 1. the VO is equal to the square root of 10times the absolute magnitude of Vi. Components Required:S. Then. The division is achieved by connecting the multiplier in the feedback loop of an Op-amp. The range of Vi is b/w-1v and -10v Vo = 1 Vi 0 Thus. Voltage Divider:The voltage divider circuit is constructed by using a multiplier and an Op-amp. The voltages Vden and Vnum represent the two input voltages. 3. The input voltage Vi is to be squared is connected to both the input terminals (ie Vx=Vy=Vi) and the output is Vo=KVi2.

V o = K V i 2 Y 1 X 1 fn g e n X1 X2 + - + X Y1 ∑ + - Y2 Observation:Input voltage amp time= Output voltage amp time= Voltage divider:- 38 .

39 1 + V i R = 1 0 3 - 2 5 1 + L M 7 4 1 6 L M 7 4 1 V m i nR = 1 0 6 V o V o . Connections are given as per the circuit diagram.V d e n V o m X X 1 Y 2 R L = 1 0 4 7 2 3 R =1 0 5 Output VoA=-Vmin/Vden Observation:Vmin voltage amp time= Vden voltage amp time= Square rooter:X X 1 Y 2 R L = 1 0 4 R = 1 0 7 vo = 10 | Vi | Observation:Input voltage amp time= Output voltage amp time= Procedure: Voltage Squarer:1. Supply is connected to the corresponding terminals. 4. Output is noted down. Input is connected to the input terminals 3. 2. Voltage Divider:1. Connections are given as per the circuit diagram.

2. 2. Output is noted down. 4. EXP. 3.10:40 . 3. Power supply is connected to the corresponding terminals. 4. Output is noted down. Square Rooter:1. Input is applied to the input terminals.NO. Voltage Divider and Square Rooter were tested using multiplier IC. Connections are given as per the circuit diagram. Result:Thus the voltage Squarer. Input is applied to the input terminals. Power supply is connected to the corresponding terminals.

OSCILLATORS USING OPERATIONAL AMPLIFIER Aim: To design the following sine wave oscillators a) Wein Bridge Oscillator with the frequency of 1 KHz. Components Required: S.No 1. 6 7 Components Op-amp Dual trace supply Function Generator Resistors Capacitors CRO Probes Range IC 741 (0-30) V (0-2) MHz (0-30) MHz -Quantity 1 1 1 1 -- Equations Related to the Experiments: a) Wein Bridge Oscillator Closed loop gain Av = (1+Rf/R1) = 3 Frequency of Oscillation fa = 1/(2π RC) b) RC Phase shift Oscillator: Gain Av = [Rf/R1] = 29 Frequency of oscillation fa = 1 6 * 2 * π * RC 1) Wein Bridge Oscillator: Design: Gain required for sustained oscillation is Av = 1/β = 3 (PASS BAND GAIN) (i.2 KΩ Let R1 = 10 KΩ ∴ Rf = 2 * 10 KΩ Model Graph: 41 . 4.05 µ F ∴ R = 1/2 π foC R = 3. b) RC Phase shift oscillator with the frequency of 200 Hz.e. 2. 3. 5.) 1+Rf/R1 = 3 ∴ Rf = 2R1 Frequency of Oscillation fo = 1/2π R C Given fo = 1 KHz Let C = 0.

Questions: 1.1 Circuit 5. 6. Compare the output with the theoretical value of oscillation. 42 . 2Ω k R C 0 . Frequency of oscillation = Hz. 2Ω k C R V O O 2 3 – 4 1 6 R C 0 µ. 0 µ f5 2. Note down the output voltage at CRO. Plot the output waveform on the graph. Observation: Peak to peak amplitude of the output = Volts. Connect the components as shown in the circuit 5. Switch on the power supply and CRO. f 0 5 3 . 4. 3. State the two conditions for oscillations.1: R 1 = 1 0Ω k R f = 2 0Ω k + 1 0 V 7 I C + Y 4 . Redesign the circuit to generate the sine wave of frequency 2KHz.V O + V p t – V p Procedure: 1.1 0 V 3 = . 5.

5. R1 ≥ 10R ∴ R1 = 10 * − − − − − − = KΩ Since Rf = 29R1 Rf = 29 * − − − − − − = MΩ Model Graph: V O t 43 .1µ F R =1/ = 1/ ( ( 6 * 2 π * fo * C ) 6 * 2 * π * 200 * 0. 3.1*10−6 ) = KΩ To prevent the loading of amplifier by RC network. Classify the Oscillators? Define an oscillator? What is the frequency range generated by Wein Bridge Oscillator? What is frequency stability? 2) RC Phase Shift Oscillators: Design: Frequency of oscillation fo = 1/(√6*2*Π *RC) Av = [Rf/R1] = 29 R1 = 10 R Rf = 29 R1 Given fo = 200 Hz. Let C = 0. 4.2.

7. Connect the circuits as shown in the circuit 5. Questions: 1. 3Ω k R 3 . EXP.NO.2 2. 3Ω k 3. 3Ω k R 3 . Note down the output voltage on the CRO. µf 1 0 0 . Circuit 5. µf 1 0 C C R V O O 3 2Ωk 2 3 – 6 0 . µf 1 0 C C R 3 . Plot the output waveform on the graph. Compare the practical value of the frequency with the theoretical value. Redesign the circuit to generate the sine wave of 1 KHz.2: R 1 1 R Ω m D R B 3 3Ωk f + 1 0 V 7 I C + 7 4 1 4 . What is the frequency range generated by RC phase shift Oscillator? 2.11:VOLTAGE REGULATION USING IC LM723 44 . 4. Plot the output waveforms on the graph.1 0 V 0 .Procedure: 1. 5. Switch on the power supply. 6. In RC phase shift oscillator how the total phase shift of 180° around the loop is achieved? Result: Thus wien bridge oscillator and RC Phase shift oscillator was designed using op-amp and tested. Observation: Peak to peak amplitude of the sine wave = Frequency of Oscillation (obtained) = Volts Hz.

9.NO 1. 1. COMPONENTS REQUIRED : S. COMPONENTS Transistors Integrated Circuit Digital Ammeter Digital Voltmeter Variable Power Supply Resistors SPECIFICATION TIP122.67 8Ω 7.1µ F.5 + 11 Vc Vo CL CS INV COMP 13 100pF Rsc 10 2 3 4 TIP122 A - + Load V - R1 430 5 0. 5.1KΩ . 4. 2. Capacitors Rheostat 1Ω 0.AIM : To design a high current.100pF ( 0 – 350 ) Ω QUANTITY 1 each 1 1 1 1 1 each 2 1 each 1 CIRCUIT DIAGRAM : Low Voltage Regulator Unregulated DC Power Supply 2N3055 12 6 V+ Vref LM723 0 . low voltage and high voltage linear variable dc regulated power supply and test its line and load regulation.1 DESIGN: Output voltage → VO Reference voltage→ Vref 45 .430Ω .2N3055 LM723 ( 0 – 10 ) A ( 0 – 20 ) V ( 0 – 30 ) V-2A 300Ω . 3.678KΩ .1 UF 1k NI V7 R2 Fig. 6.

R3 = 430.4306 R2 Select R2 = 1 KΩ R1 = 1 KΩ * 0.15 V To calculate R1.6+1000 ) R3 = 300Ω Rsc = Vsense / Ilimit = 0.699= R2 0.4306 = 430Ω R1 = 430Ω R3 = R1 * R2 / ( R1 + R2) .699R1 = 0.2 46 . Rsc = 0.Rprotect → Minimum Resistance to protect the output from short circuit. R2 . Vo = Vref ( R2 / ( R1 + R2 ) ) 5 / 7. Low Voltage Regulator : Given : Vo=5V. R1 = 0.5 /1A = 0.6 *1000 /(430. 1.R3 and Rsc.15 = ( R2 / ( R1 + R2 ) ) ( R1 + R2 ) 0. Vref = 7.301 R2 .5Ω CIRCUIT DIAGRAM : High Voltage Regulator : Fig.5Ω .

No.No. Load Resistance RL1 = Input Output Voltage Vin(Volts ) Voltage VL(Volts) Load Resistance RL2 = Input Output Voltage Vin(Volts ) Voltage VL (Volts) Load Resistance RL3 = Input Output Voltage Vin(Volts ) Voltage VL (Volts) Load Regulation : S.15 = 1+ (R1 / R2) (12 / 7. R2 .R3 and Rsc.15) . Input Voltage Vin1 = Output Output Current IL ( A ) Voltage VL (Volts) Input Voltage Vin2 = Output Output Current IL ( A ) Voltage VL (Volts) Input Voltage Vin3 = Output Output Current IL ( A ) Voltage VL (Volts) 47 .678 = 678Ω R1= 678Ω Rsc = Vsense / Ilimit = 0.High Voltage Regulator : Given : Vo=12V. Vo = Vref ( 1 + (R1 / R2) ) 12 / 7.15 V To calculate R1.5Ω Rsc = 0. Vref = 7.5Ω Tabulation of the Measurements : LOW VOLTAGE REGULATOR : Line Regulation : S.678 Select R2 = 1 KΩ R1 = 1 KΩ * 0.1 = (R1 / R2) (R1 / R2) = 0.5 /1A = 0.

No. Load Resistance RL1 = Input Output Voltage Vin(Volts ) Voltage VL(Volts) Load Resistance RL2 = Input Output Voltage Vin(Volts ) Voltage VL (Volts) Load Resistance RL3 = Input Output Voltage Vin(Volts ) Voltage VL(Volts) Load Regulation : S.HIGH VOLTAGE REGULATOR : Line Regulation : S.Vdc ( FL ) ) / Vdc ( FL ) Vdc ( NL ) = D. output voltage on full load Model Graph : Line Regulation : Input Voltage Vs Output Voltage : V0 Load Regulation : Output Current Vs Output Voltage V0 Line regulation Load regulation Vin IL 48 . output voltage on no load Vdc ( FL ) = D. Input Voltage Vin1 = Output Output Current IL ( A ) Voltage VL(Volts) Input Voltage Vin2 = Output Output Current IL ( A ) Voltage VL(Volts) Input Voltage Vin3 = Output Output Current IL ( A ) Voltage VL(Volts) Calculation of % Voltage Regulation : % Voltage Regulation = ( Vdc ( NL ) .C.No.C.

Calculate its % Voltage Regulation using the formula. Set the load Resistance to give load current of 0.Similarly set the load current ( IL ) to 0.Plot the load regulation by taking load current (IL) along X-axis and Output Voltage (VL) along Y-axis for various input voltages. Similarly set the load current ( IL ) to 0. Lab Report : 1.9A and make two more sets of measurements. 2. 3. Vary the load resistance in equal steps from 350Ω to 5Ω and note down the corresponding output voltage and load current. Load Regulation : 1.5A & 0. 2.Vary the input voltage from 7V to 18V and note down the corresponding output voltages. HIGH VOLTAGE REGULATOR : Line Regulation : 1.Similarly set the input voltage ( Vin ) to 14V & 18V and make two more sets of measurements.25A. 3. 2. Vary the input voltage from 7V to 18V and note down the corresponding output voltages. 3. 4.PROCEDURE : LOW VOLTAGE REGULATOR : Line Regulation : 1.Set the load Resistance to give load current IL of 0. 2. 3.1.Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage (VL) along Y-axis for various load currents.9A and make two more sets of measurements. Give the circuit connection as per the circuit diagram shown in Fig 1. 4.Give the circuit connection as per the circuit diagram shown in Fig 1.25A.2. Set the input voltage to 10V. 49 .5A & 0.

Load Regulation : 1. 2. Set the input voltage to 10V.Similarly set the input voltage ( Vin ) to 14V & 18V and make two more sets of measurements. Lab Report : 1. low voltage and high voltage linear variable dc regulated power supply was designed and tested.4? Low Voltage Regulator High Voltage Regulator 50 . Vary the load resistance in equal steps from 350Ω to 15Ω and note down the corresponding output voltage and load current. 3. 3.Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage (VL) along Y-axis for various load currents.No % Voltage Regulation Questions : i) Why minimum protect resistance in load is required? What will happen if it is not there? ii) Did you short circuit the output and check whether the short circuit protection is working? iii) What will you do if you are asked to design both high and low voltage regulators in one circuit? iv) Give 10 example applications of the above circuits? v) Why do you use a 100pF capacitor between 13 & 3.Plot the load regulation by taking load current (IL) along X-axis and Output Voltage (VL) along Y-axis for various input voltages. 2.Calculate its % Voltage Regulation using the formula. Result : Thus the line and load regulation of a high current. S.

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