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1 Basic Physics and Band Diagrams for MOS Capacitors

Fig.4.1 (a) The schematic of a two-terminal MIS structure. (b) Band diagram of a two-terminal MIS structure at zero gate voltage, showing accumulation of holes near the surface. VFB is the flatband voltage, Xm is the metal work function, Xi is the electron affinity of the insulator, Xs is the electron affinity of the semiconductor, and Eg is the band gap of the semiconductor.

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Two-terminal metal-insulator-semiconductor (MIS) structure: characteristic crucial to understand the operation of MOSFETs. Assumptions: -Ideal MIS structure with no charges in the insulator layer and no surface states at the semiconductor-insulator interface.

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-The insulator layer has infinite resistivity, thus there is no current across the insulator when a bias voltage is applied => Fermi level constant across the device. Some definitions: -Work function: energy required to remove an electron from the Fermi level to the vacuum level (free space). -Electron affinity: energy required to remove an electron from the conduction band to the vacuum level. At zero bias voltage, the band bending in the semiconductor layer is determined by the work function difference between the metal and the semiconductor, and it can be compensated by applying a voltage VFB to the gate

where VFB is called the flat-band voltage, Xm is the metal work function, and Xs is the semiconductor electron affinity.

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Note: this equation for VFB is applicable for an ideal MIS structure; however, if there are charges in the insulator or at the insulator-semiconductor interface, then the gate voltage required to obtain flatband condition would change.

Fig.4.2 The band diagram of the two-terminal MIS structure under the flatband condition. Vg is the applied gate voltage.

EXAMPLE 4.1: A two-terminal Si MIS structure has a substrate doping of Calculate the flatband voltage VFB of the structure if it employs (a) Al gate (Xm =

(p-type).

-poly gate. Assume that there is no charge in the oxide, Xs(Si) = 4.05 eV, and Eg(Si) = 1.12 eV. SOLUTION: Ei EF = kT ln(NA/ni) = 0.026 ln[1016/(1.5 1010)] = 0.35 eV Therefore, Si work function s = Xs + (Eg/2) + (Ei EF) = 4.05 + 0.56 + 0.35 = 4.96 eV (a) For Al gate, VFB = 4.1 4.96 = 0.86 V Note: all these numbers can be equivalently represented either in volts or in electron-volts, depending on whether potential or energy is represented. (b) -poly gate, hence, Xm = Xs = 4.05 eV

It is assumed here that the Fermi level of the n+-poly gate is coincident with the conduction band. Therefore, VFB = 4.05 4.96 = 0.91 V

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In Fig.4.1(b), note that Ev has come closer to EF near the semiconductor-insulator interface => hole concentration is greater near the interface than that in the bulk => this is referred to as the accumulation regime. In Fig.4.2, note that after the application of a positive VFB to the gate, the bands in the semiconductor become flat => uniform concentration of holes throughout the semiconductor. If the gate voltage is further increased, the holes near the insulator-semiconductor interface are pushed back deep into the bulk, leaving behind ionized acceptors near the surface and the bands bend downwards => formation of depletion region near the surface starts => referred to as the depletion regime [Fig.4.3(a)]. For even larger positive gate voltage, the band bending near the surface becomes so large that EF becomes closer to EC than to EV => the surface behaves like an n-type material => referred to as the inversion regime [Fig.4.3(b)]. Note: the increase in the band bending leads to an exponential increase in the electron concentration near the surface, e.g., an increase in the band bending by the amount of the thermal voltage VTH (= kT/q 26 mV at room temperature), increases the electron concentration by Thus, a large change in the electron concentration near the surface can be accommodated by a small change in the surface potential Vs, and since the induced charge is proportional to the gate voltage Vg, hence, the derivative dVs/dVg becomes small in the inversion regime, whereas this derivative has a large value in the depletion regime. When the difference between EF and Ei at the interface becomes equal and opposite of the bulk potential [ =(Ei EF)bulk = VTHln(NA/ni), where NA is the substrate doping concentration and ni is the intrinsic carrier concentration], i.e., it is referred to as the onset of strong inversion. The surface potential Vs is defined as (Ei,bulk Ei,interface)/q.

we would stick to the standard definition of strong inversion. for the time being. and strong inversion actually takes place when Vs is greater than by several (3-5) VTH. whereas it becomes relatively small in the strong inversion region. The surface electron and hole concentrations are given by where pp0 = NA. y Fig. the value of Vs does not change any more and it becomes pegged at . However.5 V or more) is extremely important for low power device applications in analog circuits. An alternate definition has been proposed by Tsividis.4. It is assumed that beyond strong inversion. he defines Vs = as the onset of moderate inversion.3 The band diagram of a two-terminal MIS structure at (a) depletion and (b) inversion. which states that = |dVs/dVg| is quite large in the weak inversion regime. the moderate inversion region (which can extend by 0. and would discuss about moderate inversion later. are the equilibrium hole and electron concentrations in the . and np0 = substrate respectively. y y y y Thus. In today's context.y y Operating regions: o VS < 0 => accumulation o > Vs > 0 => depletion o => weak inversion o => strong inversion.

Thus. and also. that nsps = => consequence of zero current in the semiconductor (perpendicular to the semiconductor-insulator interface) => corresponds to constant (as a function of distance) EF in the semiconductor.2 Surface Charge y The potential distribution in the semiconductor is described by the Poisson equation where the space charge density and p(x) expressed respectively as with n(x) where V(x) (Ei. y Using the definition of the electric field F = dV(x)/dx.y Note: at the onset of strong inversion Vs = . the above equation can be rewritten as . 4. NA = pp0 np0.bulk Ei(x))/q. from charge neutrality condition. y y Note: deep into the bulk.

for a two-terminal MIS structure having 30 nm thick oxide and substrate doping of 1015 cm 3 (p-type).5 1010)] = 0. including the flatband capacitance. SOLUTION: The oxide capacitance per unit area The bulk potential = (kT/q) ln(NA/ni) = 0. clearly showing all the relevant points.29 V The threshold voltage . Assume VFB = 1 V. y Introducing the Debye length the equation for F become where EXAMPLE 4.026 ln[1015/(1. one gets y Thus.and high-frequency C-V characteristics.3: Draw the low.y Integrating this equation with respect to V.

The maximum width of the depletion region The semiconductor capacitance per unit area at threshold Therefore. the total capacitance per unit area at threshold The Debye length The flatband capacitance per unit area .

and o Rgen (= dVs/dIgen) is a differential resistance. Thus. the electron moves towards the surface and the hole moves towards the bulk => thus the rate of electron build-up near the surface proceeds at a rate limited by the rate of thermal EHP generation. and is the hole mobility] is the resistance of the quasi-neutral p-region. given by generation time constant. Note: the electrons.y y y The capacitance Csc becomes dominant in the strong inversion region. is an effective y y . which create the inversion region near the surface.9 (a) The exact high-frequency equivalent circuit of a two-terminal MIS structure. for gate voltages smaller than the threshold voltage VT.4. are actually generated in the bulk due to thermal EHP generation. which is a characteristic of the EHP generation process. y Two new components in the equivalent circuit: o where T is the thickness of the semiconductor layer. and (b) its simplified equivalent. Due to the electric field near the surface (recall that electric field points uphill in the band diagram). the electron and hole of the generated EHP are separated. since the band bending is largest at the surface. Igen is the generation current. when the surface electron concentration is appreciable. Fig.

and in the other limiting case of Fig. .y In the small-signal equivalent circuit.10 The C-V characteristics for a two-terminal MIS structure at different frequencies. the parameters Ceq and Req are given by where and y Note: both Ceq and Req are frequency dependent: in the limiting case of + Cdep.4.

recalculate .4. 0. Steps: o First.4. From a knowledge of di and NA. determine the depletion capacitance Cdep in the strong inversion region from 1/Cdep = 1/Cmin 1/Cmax. obtain NA.3 V). obtain the depletion region thickness from And. and repeat the process until the desired accuracy is achieved. obtain another fine tuned value of NA. y y The maximum measured capacitance Cmax in the accumulation region gives the dielectric thickness The minimum measured capacitance Cmin at high frequency gives the doping concentration (assumed uniform) in the substrate. finally. o o Then. Steps: o The device capacitance CFB under flatband condition can be given by CFB = o CiCs0/(Ci + Cs0) = o o Thus. calculate the doping concentration from the following two equations: y These two equations need to be solved by iteration: first choose a suitable value for (say. . The parallel shift in the characteristic after the bias-temperature stress test (described later) is also shown.11 Parameter extraction from the C-V characteristic for a two-terminal MIS structure.1 Extraction of Parameters from the C-V Characteristic Fig. CFB/Cmax can be obtained. It also gives the information about the flatband voltage VFB. and the intercept can be found on the C-V curve to yield VFB.4.

5.4. Si being a crystalline material and SiO2 being an amorphous material. and significant studies have been made on this structure.4. 4. there is a sudden discontinuity in the lattice structure at the Si-SiO2 interface. y y This interface has attracted considerable interest over the last few decades.5 Non-ideality in an MIS Structure: Oxide Charges y y In most of the commercially available MOS capacitors and MOSFETs. silicon (Si) is used as the semiconductor and silicon dioxide (SiO2) is used as the insulator. which can be broadly categorized into the following: o Charges due to fast surface states (or interface trapped charges) the interface. however. located at Charges due to mobile impurity ions o Charges due to traps ionized by radiation o o located in SiO2. a detailed understanding of many of its features is still lacking. The interface and the oxide contains various types of charges. Fixed surface state charges located at the interface.12 Different types of charges in the Si-SiO2 interface and in the SiO2 layer. within SiO2.1 Fast Surface States . Fig.

depending on the position of the Fermi level at the surface and the amount of band bending. one fast surface state is assigned for every surface atom. When the surface potential changes. y y Fig. MOSFETs are universally fabricated on (100) oriented Si). and an additional resistance Rss. y y There is a shift of the C-V curve towards the left due to the fast surface states.y y y y y These are also referred to as Tamm and Shockley states. These states behave acceptor-like or donor-like. resulting in a density Proper cleaving of the surface and consequent heat treatment with H2 drastically reduces the density of these states to or so. These are created at the interface due to the sudden termination of the crystal periodicity. with the time constant RssCss representing the time response of the surface states. In the equivalent circuit of an MIS structure. and leads to a shift in VT and a change in the C-V characteristics.13 The experimental C-V characteristics showing the difference between them due to the presence of fast surface states. since they capture and release the carriers at a fast rate. since all the bonds of the atoms at the surface are not fulfilled these unfulfilled bonds are referred to as the dangling bonds. Roughly. which changes the flatband voltage.4. after their inventors. since H2 compensates some of these dangling bond by the formation of SiH. the charges in the surface states change as well. . Obviously. the density of these states is a function of the crystal orientation (since (100) planes have lower atom density than (111) planes. and these are referred to as fast states. the fast surface states can be represented by an additional series combination of an equivalent capacitance Css of the surface states.

which are introduced into the oxide from the furnace walls during oxidation. i.Fig. it used to vary with bias under elevated temperatures.e.15 Shift in the C-V characteristic after the bias-temperature stress test due to ionic contamination in the oxide..4.5. . y Measurements of frequency-dependent MIS capacitance and conductance give information about the density of the surface states. 4.4. Fig. and its partial recovery after annealing with gate-substrate shorted.2 Ionic Contamination y y A major difficulty with early MOS devices was the instability of the threshold voltage VT. This happens due to the rearrangement of the mobile ions within the oxide.14 The overall high-frequency equivalent circuit for a two-terminal MIS structure showing the additional components Css-Rss to account for the effects of fast surface states.

4. y y y Initially. y The menace created by mobile ions is reduced to a large extent in today's technology due to the improvements in the fabrication process.16 Charge distribution during the various stages of the bias-temperature stress test and post annealing. EXAMPLE 4.4: In a two-terminal MIS structure having 40 nm thick oxide. the shift in the flatband voltage after a bias-temperature stress test was found to be 10 mV. Determine the mobile ionic contamination per unit area in the oxide in numbers per unit area.this experimental procedure is known as the bias-temperature stress test. Fig. For any arbitrary distribution of the oxide charges (x). the ions create an arbitrary distribution (x) within the oxide. inducing image charges in both the gate and the semiconductor. and after heating the device for 30 minutes at the same temperature with the gate shorted to the substrate yields characteristic marked by (3). finally after recovery. all the positive ionic charges are located at the metal-SiO2 interface. the shift in the flatband voltage can be given by where di is the oxide thickness. all these ionic charges cluster near the Si-SiO2 interface and induce all the image charges in Si. while those observed after 30 minutes at 127 C with VG = +10 V applied is marked by (2).y The initial C-V characteristic is marked by (1). exerting no influence on Si. SOLUTION: The oxide capacitance per unit area . after positive gate bias at high temperature.

with the electron moving towards the metal-SiO2 interface.5. o Its density is a strong function of the oxidation and annealing conditions.. the mobile ionic contamination per unit area in the 4. 4. etc.5. (110). In the absence of any electric field within the oxide. which results in a parallel translation in the C-V characteristics along the voltage axis these charges are called the surface state charges.. EHPs will be generated within the SiO2. VT. X-ray. The physical origin of this charge is completely different from the ionic contamination. the generated electrons and holes would separate. low. o o y y The ratio o f in (111).The shift in the flatband voltage due to the mobile ionic contamination after bias-temperature stress test is given by oxide Thus. These charges can be eliminated by thermal annealing.e. gamma ray. and (100) Si are in the ratio 3:2:1. and is a strong function of the oxidation condition. o Unchanged under bias-temperature stress test and thermal annealing. due to the electric field within the SiO2. Due to irradiation. e. its charge states cannot be changed over a wide variation in the band bending. and. thus. or by the type or concentration of impurities in Si.4 Surface State Charges y A fixed charge is seen to exist within the oxide very near the Si-SiO2 interface. and the hole moving towards the SiO2-Si interface. and the density of these charges per unit area is denoted by These surface states have the following properties: o It is fixed. . these carriers will immediately recombine. Its density is not significantly altered by the oxide thickness. Thus. thus creating an electric field within the oxide.g. which is opposite to that of the applied field => changes VFB.and high-energy electron irradiation. i. however. and the orientation of the Si crystal. under a positive applied gate bias. It is located within 200 of the Si-SiO2 interface.3 Radiation-Induced Space Charge y y y y y y A positive space charge is seen to build up in SiO2 films when it is irradiated by ionizing radiation of various kinds. (potential danger during ion implantation). a space charge layer starts to build up within the oxide due to these charges.

This correction is dependent on the interface electron density. in the depletion and weak inversion regions). but fails for applied voltages near and below VT (i.7.y Popular theory: originates from the excess ionic Si in the oxide. y y Note: Eq.e. however. and is given as: where is the permittivity of the gate insulator. di is the thickness of the gate insulator. which moves into the growing SiO2 layer during the oxidation process. A new model has recently been proposed which has been shown to model the device behavior adequately both in the weak and strong inversion regions.7 Some Advanced Models 4. is the oxide charges lumped at the Si-SiO2 interface. however. and arbitrary distribution of charges within the oxide.24) does not describe the mobile charge in the accumulation region.(4. it can be approximately taken to be a constant for typical values of the interface electron density.6 General Expression for the Flatband Voltage VFB y The general expression for the flatband voltage VFB can be given by where where m is the metal work function and is the semiconductor is any work function. This model is an adequate description of the strong inversion region of the MIS capacitor.1 Unified Charge Control Model (UCCM) for MIS Capacitors y y y The standard charge control model (SCCM) postulates that the interface inversion charge of electrons qns is proportional to the applied voltage swing VGT = VG -VT. this region is not important for MOSFET operation. 4. is an ideality factor.. and is a correction to the insulator thickness related to the shift in the Fermi level in the inversion layer with respect to the bottom of the conduction band. can be reduced by a large extent by H2 heat treatment y 4. .

Cdep can be estimated as follows: is an average width of the depletion region.24)] seems reasonable. Usually. and at low substrate doping levels. this extraction of parameters is based on the C-V characteristics.24) is an empirical equation. The voltage at which the derivative of the MIS capacitance reaches its maximum value is very close to the threshold voltage VT. the surface potential Vs has the value Below threshold. is dependent on VGT. it predicts that the inversion charge is an exponential function of the applied voltage. we have the following approximate relationship: y y Note: in general.(4. . while in the subthreshold region. Since UCCM is an empirical model.e. it is especially important to have a clear and unambiguous procedure for extracting model parameters from experimental data. which can be justified by comparing the calculation results with experiments and more precise calculations. it can usually be assumed that The ideality factor reflects the gate voltage division between the insulator layer capacitance Ci and the depletion layer capacitance Cdep. In the subthreshold regime. as expected. For the MIS structure. At the onset of strong inversion (VGT = 0). Intuitively. which shows a sharp increase in the capacitance (at low frequencies) during the transition from the depletion to the strong inversion region.y y y y y For Si-SiO2 MOS capacitors hence. y y y y y Equation (4. since in the strong inversion region. is close to unity near threshold where the gate depletion width is large (corresponding to Cdep << Ci).. it reverts to the simple charge control model [i. the structure of the UCCM expression [Eq.

.(4. the following sheet inversion charge density at threshold is obtained: and the value for the unified capacitance per unit area at threshold becomes y y Here.y The first derivative of Eq.33) serves as the basis for a very convenient and straightforward technique for determining the threshold voltage from experimental data. is the maximum value of Equation (4.24) with respect to VGT yields the following unified expression for the metal-channel capacitance per unit area applied bias voltage: valid for all values of y The first derivative of this capacitance reaches its maximum value for y Hence.

from a plot of versus and a can be found. Fig.17 Measured gate-channel capacitance as a function of gate-source voltage for an nchannel MOSFET for different values of substrate bias.(4. while the intercept with yields a.4. . The slope of this plot gives . y From the experimentally determined gate-channel capacitance.18 Inverse gate-channel capacitance plotted as a function of the inverse mobile sheet charge density (data obtained from Fig.29).4. this should agree with Eq. the inversion carrier sheet density can be calculated as y According to UCCM.17).Fig. which can be written as y y Hence.4.

4.1.1 Analytical Unified MIS Capacitance Model y Note: the UCCM does not have an exact analytical solution for the inversion charge in terms of the applied voltage even though an accurate approximate solution can be obtained. In Fig. The threshold voltages determined by the two methods are also indicated. symbols) ns versus VGS characteristics for different values of Vsub in (a) semilog scale and (b) linear scale. y y Fig.4.19 Measured dependence of (curves to the left) and 1 V (curves to the right). the results obtained from the simple charge control model (SCCM) are also shown.19. .7. the agreement between the measured and the calculated data is excellent for the entire range of gate bias. At deep subthreshold. In Fig.20 Measured (solid lines) and calculated (UCCM.20. y y The deviation in the measured curves found in the deep subthreshold region is due to two reasons: one is the C-V measurement error. y The values of obtained from the slopes in Fig. 4. and the other is the leakage current. the channel offers a large series resistance compared with the reactance of the capacitance. the value of VGS corresponding to the peak value of should coincide with the value of VGS at which the gate-channel capacitance has dropped to onethird of its maximum value. which dominates deep subthreshold operation.4. In (b).4. and the value of di calculated from a is in excellent agreement with that measured by ellipsometry.18 agree very well with those determined directly from the subthreshold I-V characteristics.Fig.4.

this thickness d can be estimated as where Fs is the surface electric field.40) is similar to an interpolation formula.37).. the electrons induced at the semiconductor-insulator interface of an MIS capacitor form a classical electron gas and behave essentially in the same way as electrons in a bulk semiconductor. the following expression is obtained for the subthreshold differential channel capacitance per unit area y An approximate. For the classical electron gas. i. unified expression for the effective differential metal-channel capacitance per unit area is obtained by representing it as a series connection of the above threshold and the subthreshold capacitances.(4.e. y Hence.y Above threshold. and using Gauss' law. 4. This assumption is only correct if the thickness of the inversion layer is much larger than the deBroglie wavelength for electrons. the electron sheet density in the channel can be written as y From Eq. the sheet density of carriers in the inversion layer can be given as y Below threshold. this field can be approximated as .8 Quantum Theory of the Two Dimensional Electron Gas (2DEG) y y y Classically. and calculations show that it is in excellent agreement with UCCM. the unified carrier sheet charge density becomes y Equation (4.

. and the deBroglie wavelength. Ej is the energy level of the jth subband.21 Schematic diagram of energy subbands at the semiconductor-insulator interface (assuming constant effective field approximation).y In this estimate. the number of subbands is large and the energy difference between the bottoms of the subbands is small (<< kT). Fig. e. only the lowest few subbands are important for electron occupation. and the energy difference between the bottoms of the subbands may become large compared to the thermal energy kT. and it is assumed that almost all of the applied voltage drops across the insulator. and ky and kz are the wave vector components parallel to the interface..g. For a relatively thin electron gas layer. di can be well below 100 . Hence. the quantization of the energy levels in the potential well at the semiconductor-insulator interface in the direction perpendicular to the interface must be taken into account. then the dispersion (E-k) relation in the direction parallel to the interface is given by: where En is the electron energy. In modern day MOSFETs. y y For a relatively thick electron gas layer.4. Once quantization of energy levels take place. for di = 100 may become smaller than y y y y In this case. the condition of continuity of electric displacement across the semiconductor-insulator interface is used.

y After evaluating this integral and adding the contribution from all subbands. However. «. 2.e. which is characteristic for the semiconductor-insulator interface of an MIS structure.22 Energy levels (bottoms of subbands) and density of states for a triangular quantum well structure (j = 1.y y In this case. the electron gas is often referred to as a two-dimensional electron gas (2DEG). one obtains y y y The quantized energy levels for the subbands can be found using a numerical selfconsistent solution of the dinger and Poisson's equations. The density of states D for each subband is given by which is a constant and independent of the subband energy Ej => the overall density of states has a staircase dependence on energy for a triangular quantum well. The number of electrons occupying a given subband j can be found by multiplying the density of states D for a single subband by the F-D distribution function. the energy levels are given by .. constant effective field Feff) in the semiconductor and close to the semiconductor-insulator interface.4. an excellent approximation for the exact solution can be found by assuming a linear potential profile (i. and integrating from Ej to infinity: y Fig. correspond to the different subbands). In this case.

and qnB (= qNAddep(av)) is the sheet density of depletion charge. FB. Similarly. one can obtain the relation between ns and the Fermi level [EF Ec(0)]. FS = q(ps + where ps is the interface hole sheet density. for holes. . y y y y y The effective field Feff is expressed through the surface field FS and the bulk field FB. and Ec(0) is the minimum conduction band energy at the Si-SiO2 interface. it has been found that a slightly different form of the effective field Feff1 = (FS + 2FB)/3 gives a better fit to the measured data. Solving these equations iteratively. and qpB (= qNDddep(av)) is the sheet density of depletion charge. In reality. where ns is the interface electron sheet density. giving the best fit to the selfconsistent solution of dinger and Poisson's equation is given by and Feff = (FS + FB)/2.where is the effective mass for electron motion perpendicular to the (100) surface. the relationship linking Feff. For electrons. and FS.

the slope gives y In the calculation. solid lines: charge sheet model.23. the dependence of ns on EF in the above threshold regime can be approximated by a straight line: where EF0 is the intercept of this linear approximation with ns = 0. Symbols: calculations based on a 2DEG formulation.4. the calculation agrees reasonably well with the classical charge sheet model (CCSM) given by Brews: especially at low levels of substrate doping. it can be assumed that the maximum value of nB is given by y In the subthreshold region. However.4. the difference between the charge sheet model and the 2DEG formulation is large. As can be seen from Fig.Fig.23 Comparison of the interface carrier density versus EF Ec(0) characteristics for different substrate doping densities in (a) semilog plot and (b) linear plot. straight line in b): linear approximation to 2DEG formulation. y y y The difference between the curves at high substrate doping levels is caused by the fact that the large bulk field quantizes the energy levels even in the subthreshold region. . at strong inversion.

What is the status of the surface? 4. is obtained. show that at flatband (i. Practice Problems 4.3 Continuing with the derivation given in Section 4.4 Sketch the electric field and voltage distribution in an MOS structure at the threshold gate voltage.23b).1 Clearly draw the band diagrams for an ideal MOS structure and no oxide charge) on n-type Si for i) accumulation.6 Starting from Eqn. which makes quantum effects much less pronounced. ii) depletion.y y This approximation means that a fraction of the applied voltage. compute its magnitudes for substrate 4. Compute the threshold voltage VTH from the voltage distribution. show that the electric field E in the semiconductor in an MIS capacitor can be given by carry their usual meanings. 4. The shift in the Fermi level with respect to the bottom of the conduction band changes the above-threshold capacitance from to be interpreted as a correction to the insulator thickness.. where all the notations 4. where the parameter can y From the straight-line approximation in Fig. equal to is accommodated by a shift in the Fermi level with respect to the bottom of the conduction band. If the oxide thickness tox = 40 nm and VG = 1 V.(4. and is defined by = [Ei(bulk) Ei(x)]/q. the electron and hole concentrations as functions of position are given by where n0 and p0 are the equilibrium electron and hole concentrations respectively.2. the flatband capacitance per unit area dopings of Hence.16). which is much y smaller than that of This difference is caused by o a much larger effective mass in the conduction band in Si. and VFB = 0.5 Calculate and plot the semiconductor surface charge a function of the surface potential per unit area for an MIS structure as 4. Assume symmetric bands with . 4.7 Consider the energy band diagram of a metal-SiO2-Si-SiO2-metal structure as shown in Fig.P7. Data: substrate voltage = 0.4.e. and o the large difference in the dielectric constants between the insulator and the semiconductor for the MOS system. and iii) inversion. when Vs = 0). determine the magnitude and sign of the charge density in the semiconductor.2 Show that for an MOS structure on p-type Si.

ii) the charge distribution is linear with the peak at the metal-SiO2 interface and zero at the Si-SiO2 interface. 4. and VTH.9 Charge density of is distributed in the oxide (d = 40 nm) in a Si MOS capacitor. Neglect induced charges in Si.11 Find VTH for an MOS structure in Si with p-type substrate and d = 80 nm. with the same parameters . 4.(a) What is the flatband voltage for this structure? (b) Sketch the band diagram of the structure when the left metal plat is at 2 V and the right metal plate is grounded. in the oxide.8 (a) Find the voltage VFB required to reduce to zero the negative charge induced at the semiconductor surface by a sheet of positive charge (b) In the case of an arbitrary distribution of charge located below the metal. 4. The SiO2 thickness d = 50 nm.10 An Al-gate structure is made on p-type where m is the Al work function to vacuum) MOS % where is electron affinity for Si) substrate. and the effective oxide interface charge Find Wmax. VFB. 4. Assume Find the flatband voltage required to be applied at the gate to compensate these charges if: i) the charges are uniformly distributed in the oxide. Repeat for n-substrate (note: the new can be calculated from the change in EF). show that where = oxide capacitance per unit area = where d = oxide thickness. all the appropriate voltage levels must be specified. Physically justify the answers. Assume What is the strength of the electric field in Si? What are the positions of the Imrefs in Si? In the band diagram. Sketch the C-V curve for this device giving all relevant details. and iii) same as ii) but now with the peak at the Si-SiO2 interface and zero at the metal-SiO2 interface.

with the magnitude shown. 4. and strong inversion).17 As a practice problem. moderate inversion. v) flatband voltage. Data: ni = 4. and the strong inversion regions in the plot (as per Tsividis). determine the expression for the impedance across its two terminals as a function of frequency.13 Calculate and plot the surface potential as a function of the gate voltage VG in depletion and inversion for a two-terminal MIS structure.20 Derive Eqn.19 Derive Eqn. Mark Cso in the plot. calculate and plot the effective capacitance of the structure as a function of the gate voltage VG (varying from -5 V to +5 V) for frequencies of 4. 4. weak inversion.e. iii) substrate doping. Can the plot be really linearized in subthreshold? Determine an effective value of in subthreshold from the plot. 4. .4.(4. Also. accumulation.15 Calculate and plot the temperature dependence of the surface charge per unit area for the surface potential i) in the temperature range between 150 K and 450 K. Data: effective densities of states in conduction and valence bands and respectively at 300 K (with both of them having a dependence).12 eV (the variation of the energy gap with temperature may be neglected). Identify the weak inversion. and the surface state density is determine the oxide fixed charges.4. and the capacitance of the structure at low and high frequencies for V >> VT for Vsub = 0.18 The C-V curve of a two-terminal MIS structure shows a shift of 10 mV in the flatband voltage after a bias-temperature stress test.40). If the flatband voltage before the stress test is -1 V. Assume that the voltage difference between the inversion layer at the interface and the gate contact is maintained constant when the substrate potential is changed (charge screening).1. depletion. and the energy gap Eg = 1.. and vi) fixed oxide charges.1 V.14 Calculate and plot the gate-to-substrate capacitance Cmis as a function of the gate voltage VG for a two-terminal MIS structure with area = The plot should show all the regions of operation (i. and following the parameter extraction algorithm discussed in Section 4. 4.43). iv) flatband capacitance. draw any arbitrary C-V curve of your choice.. Calculate and plot the maximum width of the depletion region for an ideal (i. obtain the i) oxide thickness.e.12. so that the substrate voltage reverse biases the inversion layer/p-type substrate junction. 4. calculate the threshold voltage VT. VFB = 0) MIS capacitor on p-type Si with as a function of the substrate bias Vsub for -2 V < Vsub < 0. ii) threshold voltage. Hence. 4.16 From the equivalent circuit for an MIS structure. (Note: the externally measured capacitance includes the oxide capacitance).(4.

Ej Ej 1 << kT). For {100} direction four of these ellipsoids will lye on the surface and two ellipsoids will be perpendicular.46).4.EC(0)] under the 2DEG approximation for (b) Repeat part (a) under the 3D approximation (i. Note: the effective mass mpi is mt for two valleys.(4.. where mt and ml is the transverse and lateral effective mass respectively. which is derived using a conventional 3D electron gas approach.21 (a) Compute and plot the surface electron concentration ns as a function of [EF . METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS (MOSFETs) Principle of Operation .(4. the 3D charge sheet model as given by Brews). and for four valleys.e. Refer to Problem 22 also.. In the above equation. given by Eqn. Show that in this limit (i.46). In this case. Data: (Note: the constant energy surface for Si consists of six ellipsoids of revolution. the equation reduces to Eqn. and Eji is the energy level of the jth subband in valley i.22 In the classical limit. mpi is the parallel effective mass for the valley i.e.) 4. the separation of the energy subbands in a 2D electron gas is small compared to the thermal energy kT. and ml ( ) and mt ( ) represents the lateral and transverse effective mass respectively. the sheet density of the 2D electron gas is given by the classical charge sheet model.

a thin channel of electrons is created near the Siinterface. When a positive voltage is applied to the gate. and a fourth contact (body or bulk or substrate) is connected to the substrate. source. gate. an applied drain-to-source bias creates a drift field in the channel. In the on state of the device. A thin layer separates the third contact (gate) from the channel region of the device. from which the carriers can move into the channel. which provides a conducting link between the source and the drain => on state of the device. The depletion regions between the p-type substrate and n+ regions and n-channel provide the required isolation from other devices fabricated on the same substrate. and electrons move from the source to the drain => thus a current is established. In the absence of a conducting channel. where two n+ source and drain regions are diffused into a p-type substrate. and substrate) device. the channel conductance and device current) can be modulated by a variation in the gate voltage. thus. since the heavily doped source/drain regions provide an infinite reservoir. y y y y y y y A four-terminal device obtained from an extension of the two-terminal MIS structure by diffusing or implanting two n+ regions into the p-type substrate in order to form two ohmic contacts called the source and the drain. Note: the C-V characteristic of this device shows low-frequency behavior (of the twoterminal MIS structure) up to a fairly high frequency (of the order of the inverse transit time of the carriers across the channel). no electrical continuity between the drain and the source exists => off state of the device. The electron concentration in the channel (and.Schematic diagram of an n-channel MOSFET. making it a four terminal (drain. or to which they can escape from the channel. .

where L is the channel length. the charge induced at any position along the channel can be determined from the formulas derived for the MIS structure. modern MOSFETs have extremely short channel lengths. this requires << L. is used in order to calculate the I-V characteristic of the device. Note: This approximation actually states that the channel potential varies very little along the channel over a distance of the order of the insulator thickness . and Fig (b) qualitative potential profile in the channel. thus.e. . y electric fields in y However. . the GCA fails for most of modern MOSFETs. and this requirement is not often met. According to GCA. nevertheless its discussion is important. i.e. y The gradual channel approximation (GCA): Fig (a) schematic comparison of the parallel and perpendicular the channel.The I-V Characteristic The Gradual Channel Approximation (GCA) y y The GCA. This approximation states that the rate of variation of the lateral field within the channel is much smaller than the rate of variation of the vertical field.. and the channel potential is assumed to be a gradually changing function of position. proposed by Shockley. i.. provided the constant surface potential for an MIS structure is replaced by a variable channel potential in the expression for the surface charge density per unit area in the semiconductor.

all the results are also applicable for a p-channel device. y between the total surface charge density . the gate voltage is sufficiently large to create strong inversion throughout the channel..e. the drain is connected to a potential . i.. y Assume that the source is grounded .Assumption: The device is operating in the above threshold regime. however. provided appropriate sign changes are made. y Band diagrams at Fig (a) the source side and Fig (b) the drain side of the channel for the direction perpendicular to the Siinterface.e. Note: here we are considering an n-channel device. i. y The induced surface charge density is then given by where is the insulator capacitance per unit area. and the substrate is connected to the source The density of the free electrons in the channel can be found from the difference and the depletion charge density . and the term within the square brackets is the voltage drop across the insulator.

since the induced n-channel/p-substrate junction is reverse biased by the . i. thus. the exact expression for can be given by y Since the drain current is carried entirely due to drift. Thus. Note: for short channel devices. . it is assumed that the electron drift velocity is proportional to the component of the electric field parallel to the Siinterface. which leads to an increase in the width of the depletion layer and of the depletion charge density. elsewhere in the channel. y The band bending increases in the channel as one moves from the source to the drain. y Note: at the source side of the gate where = 0.. is given by however.Qualitative two-dimensional plot of the conduction band edge for an n-channel MOSFET.e. the total band bending between the substrate and the surface is . and W is the channel width. this electric field may be sufficiently high to cause velocity saturation in the channel. the drain current equation can be rewritten as . In writing this equation. its expression can be given by where is the low-field electron mobility.

. thus.x = 0 ( = 0) to the drain. i.. the expression for gets modified to . where is the threshold voltage corresponding to the onset of strong inversion. and integrating it from the source. and is given by y In the presence of a substrate bias . the following I-V characteristic is obtained: y y y This model is known as the Shockley model.e. x = L .Note: is a function of . substituting the expression for in the above equation.. The condition is referred to as the pinch-off condition.e. i. This expression for is valid only if the inversion layer exists even at the drain side of the gate. noting that is a constant throughout the channel. and it occurs at the drain side of the gate when y As (first-order approximation). i.e.

y If the inversion layer-substrate (or the source-substrate or the drain-substrate) junction ever gets forward bias.(5. which would hamper normal MOSFET operation. For both n. much less than may be allowed in certain cases). one gets : y . a large leakage current would result. the magnitude of the threshold voltage VT increases with an increase in |Vsub|. and its sign should be such that it never forward biases the inversion layer-substrate junction (a small forward bias. Note: is the voltage difference between the inversion layer at the source end and the substrate contact. y Physical Understanding of Saturation y A physical insight into the phenomenon of saturation may be obtained by analyzing the electric field distribution under the gate.The band diagram of an n-channel MOSFET along the direction perpendicular to the Siinterface for a negative substrate bias.and p-channel MOSFETs.6) from 0 to x. Integrating Eq.

Fig.(5.(5. .12) and (5.6 The variation of the electric field along the channel for drain voltage nearly equal to the saturation voltage for gate voltages y Note: from the constancy of the drain current throughout the device.5.13) together.5) : y Solving Eqs.or y The electric field in the channel in the direction parallel to the semiconductor-insulator interface can be found from Eq. it can be seen that as and the electric field F(L) diverges. the field profiles can be calculated.

(5.7). Note: modern day MOSFETs have extremely small gate lengths. and the channel has high electric fields (more than the critical electric field required for velocity saturation).y The differential drain conductance tends to zero when voltage region y and the I-V characteristics may be extrapolated in the assuming a constant (independent of drain current may be found by substituting from Eq. which results in a highly complicated expression. which creates the velocity saturation effects for the channel electrons. .(5. it can be simplified for gate voltages close to the threshold voltage y y Note: this approach is only valid when the channel electrons do not suffer any velocity saturation due to high electric fields.8) into Eq. however.

7 The I-V characteristics of an n-channel MOSFET for different values of gate voltage .5.(5. Fig.Fig. The dashed line represents the drain-to-source saturation voltage.8 The variation of the drain saturation current with gate voltage for three different values of substrate doping. y For very small the terms under the curly brackets in Eq. leading to the following simplified expression for the I-V characteristics in the linear region: .15) can be expanded in Taylor series.5.

16) can be given as follows: At very small the charge induced in the channel is. In this model.5). it is assumed that the concentration of free carriers induced in the channel is given by y Compare Eq.2): in Eq.(5.(5.y y A physical justification of Eq. can now be given by y The drain current y y Compare Eq.(5.20) can be rewritten as . for small the electric field F in the channel is nearly constant. and is given by The drain current is entirely due to drift.20) with Eq.(5.2. independent of the channel potential.17) y y Now. the variation of the depletion charge density with the channel potential has been neglected. Equation (5.(5. to the first order.(5.19) with Eq.19). and is given by the electrons in transit model: since 5. (5. thus.3 The Charge Control Model y y A simplified description of the I-V characteristics of a MOSFET can be obtained by using the charge control model.

y The differential transconductance is defined as y From Eqs.(5.21) from x = 0 (source side) to x = L (drain side).(5. .5.y Integrating Eq.9 The I-V characteristics of an n-channel MOSFET calculated using the charge control model (solid curve) and the Shockley model (dashed curve).22) and (5.23). which corresponds to a change in from the following expressions for the I-V characteristics are obtained: Fig.

the transconductance is biased at and the drain conductance Determine SOLUTION: i) . which in turn gives large values for the insulator capacitance per unit area Large widths (W) and short lengths (L). with is referred to as the process transconductance parameter. the following steps may be taken. Higher value of low field electron mobility Thinner gate dielectric layers. y y y y y Thus. the dependence of transconductance on the low-field electron mobility and the gate length gets strongly affected. EXAMPLE 5. in order to achieve a high value for the transconductance gm. Note: for short channel devices.where is referred to as the device transconductance parameter. where velocity saturation effects are important.1: An n-channel MOSFET with the process transconductance parameter the threshold voltage the drain current ID.

the device is under linear mode of operation . Note the huge change in transconductance in saturation as compared to the linear region: this is due to the square law dependence of current on the gate voltage in the saturation region (as against the linear variation in the linear region). However.Hence. due to smaller diffusion cross-sections and smaller drain currents. Drain Conductance This is due to the independence of the saturation drain current on the drain voltage. and finite drain conductance Effect of Source and Drain Series Resistance y y y The analysis so far neglects the effects of the source/drain series resistance. for modern day MOSFETs. channel length modulation creates a change in drain current with respect to the drain voltage in saturation. this effect cannot be ignored. In reality. The extrinsic (measured) voltages can be related to the intrinsic (device) voltages by the following equations: . and the entire voltage is assumed to drop along the channel.

where y are the source and drain resistances respectively. is related to the intrinsic drain Similarly. the extrinsic drain conductance conductance . is related to the intrinsic transconductance The extrinsic transconductance where y is the intrinsic drain conductance.

5. and the velocity saturation effects are very important. in reality. and the series drain resistance increases the drain-to-source saturation voltage. thus. Both series source resistance and series drain resistance reduce the drain conductance at low drain-to-source voltages.10 The variation of the drain saturation current as a function of the gate voltage for three different values of the series source resistance Fig.Fig. and the other directed laterally along the length of the channel.11 The drain current drain-to-source voltage characteristics for different values of y y The series source resistance reduces the drain current. and vice versa. one directed longitudinally from the gate to the substrate. Velocity Saturation Effects in MOSFETs y y y In modern day MOSFETs. Note: the channel. the channel length is very small.5. The measured electron and hole mobilities in the inversion layer may be quite different than those measured in the bulk. the electric field in the channel is very high. is under a two-dimensional electric field. y . The effective inversion layer thickness is approximately given by a large vertical field creates a narrow inversion layer.

Fig. which increases for narrow channels thus their mobility drops.13 The variation of the electron and hole mobilities in the channel as a function of the gate electric field.5. y Electrons in the channel move in random directions. which is more intense in narrow channels.5. Fig.12 The random path of electrons in the channel. undergoing surface scattering. y The dependence of the electron and hole mobilities on the gate field approximated by can be crudely where n0 and p0 are the electron and hole mobilities for . undergoing surface scattering.

and is exploited in high electron mobility transistors (HEMTs) or modulation-doped field effect transistors (MODFETs). the electron motion in the direction perpendicular to the interface gets quantized.(5. and the channel electrons behave like a two-dimensional electron gas (2DEG). This is a much more realistic assumption than the Shockley model. the I-V characteristic can be given by: where y y y y The saturation current can now be found by assuming that the current saturation occurs when the electric field at the drain side of the channel exceeds the critical field required for velocity saturation. and the impurity scattering is screened by a high density of electrons in the channel. and limited thermal velocity. which assumes saturation occurs when The constant mobility model is still used for drain voltages below the saturation voltage. This is because for these cases. the surface scattering is not that important.y y It is very interesting to note that in highly constricted channels or at low temperatures. y y Effects of Velocity Saturation on the I-V Characteristic y For this derivation. Such enhancement of electron mobility was observed in GaAs. Thus.21): . the carrier mobility is seen to get enhanced. The absolute value of the electric field in the channel at drain voltages below the saturation voltage can be obtained from Eq. y is the saturation Recall: in the linear region. a simple two-piece linear approximation for the electron velocity is used: where is the electric field required for velocity saturation.

(5.35). y From the condition the drain saturation current can now be found as y At very large values of the term in the brackets in Eq.35) from 0 to x.(5.(5.(5. which gives the following expression for the saturation drain current for long channel devices: the velocity saturation effects. the following expression for the electric field as a function of distance is obtained: and the electric field F(L) at the drain side of the channel (where it is the largest). . which does not take into account .40) may be expanded into Taylor series. the following equation for the channel potential obtained for drain voltages below the saturation voltage: is y The solution of this equation is given by y Substituting Eq.y Integrating Eq.37) into Eq.

for modern day MOSFETs.y y y y For long channel devices. Example: assume then for channel length velocity saturation effects on the drain saturation current may be neglected. the typical gate length is much smaller than (recently.14 The variation of the drain saturation current as a function of the gate length for three different values of the gate voltage (3 V. when from Eqs. 5 V.5. In the limiting case for short channel devices. it shows a significant departure from linearity a measure of whether the device is a short-channel or a long-channel device. where the velocity saturation effects are extremely important. shows a linear behavior.(5. hence. The drain saturation current predicted by the constant mobility model (shown by the dashed line) is also shown for comparison. y y y Fig. the drain saturation current is times smaller than the value predicted by the constant mobility model. however. and it becomes linearly dependent on instead of the familiar square law relation. and 7 V). Intel has introduced processors using technology). However. for short channel devices. the velocity saturation effects are not too important for long channel devices. . while plotted as a function of for a long channel device.41). The drain saturation voltage is also much smaller than that predicted by the constant mobility model. as predicted by the constant mobility model.40) and (5. it is seen that Note: for short channel device.

which describes both limiting cases correctly: y y This was one of the earlier formulas. can be accounted for (as done earlier for long channel devices). and a huge amount of work has been done in this area for the last ten years or so. for short channel devices. whereas. the drain current increases continuously with the drain-to-source voltage. the I-V characteristics do not completely saturate at large drain-tosource voltages. for these cases. In practical devices. the following modification to the drain current expression has been proposed: y where is referred to as the channel-length modulation parameter (an extremely important parameter for short channel device a measure of the nonidealities present in the device) Short Channel and Nonideal Effects in MOSFETs y For long channel devices. in order to further refine the description of the behavior of short-channel MOSFETs. and the following expressions for the drain saturation current and the drain saturation voltage are obtained: Interpolated Relation y The following interpolation formula for the MOSFET I-V characteristic has been proposed by Shur. and this is related to the short channel and other nonideal effects in MOSFETs.y The effects of source/drain series resistance. . the drain current becomes constant in saturation. In order to account for the finite slope of the output characteristics in saturation.

75 (solid lines). Fig.5. (dashed lines). Now. which states that it is independent of the device length this behavior cannot be explained. based on the existing model for the threshold voltage.16 The variation of the threshold voltage with the effective channel length.5. and it actually decreases with a decrease in the channel length. which explains the reason behind the larger saturation current. The Charge Sharing Model .15 I-V characteristics of two n-channel MOSFETs: (i) L = 0.Fig. it has been shown that the threshold voltage is a strong function of the channel length (for short channel devices). y y y Another interesting feature seen in short channel devices is that the saturation current increases as the device length is reduced.5 and (ii) L = 0. In reality.

Note: essentially. . However. thus. and (b) a short channel device. and. the depletion layer thickness at the source end of the channel and at the drain end of the channel are much less than the channel length L. y y y For a long channel device. Fig.17 The depletion charge profiles for (a) a long channel device. for a short channel device. the depletion regions near the source and the drain are contributed by the source-substrate and the drain-substrate bias.y The reduction of the threshold voltage with a reduction in the channel length can be explained by the charge sharing model. the depletion charge enclosed by these sections are much smaller than the total depletion charge under the gate. the widths of these depletion regions are a nonnegligible fraction of the total depletion charge under the gate. and gate has no role to play.5.

and finite output conductance in the saturation region. and the voltage dropped along this section is assumed to be equal to the drain saturation voltage . which qualitatively explains the reduction of the threshold voltage with a reduction in the channel length. the depletion region thickness near the drain will obviously be larger than that at the source side.e. however.. it is assumed that the effect of the depletion width at the drain side of the channel is to reduce the effective channel length in the saturation region from L to where y y y y Here.y y y Under an applied drain-source bias. to the first order. The exact analysis of the charge sharing effects requires a two-dimensional analysis. and is length of the pinched-off portion of the channel (related to the drain depletion width). and this effect leads to a higher drain saturation current. where the excess drain voltage beyond . A very crude estimate of the pinch-off length (also referred to as the drain region length) can be obtained from the solution of the one-dimensional Poisson's equation: . leading to a reduction in the effective channel length . The net effect is that the gate now has to compensate for a lower depletion charge density than that for a long channel device. i. This effect is called the channel length modulation effect. where is the applied drain voltage. is dropped. With an increase in the length of the pinch-off region also increases. is the effective channel length.

leading to the current density y Here. and they spread uniformly.y A more accurate and realistic expression for may be obtained by assuming that the electrons are injected from the inversion layer into the drain depletion region. thus their volume density can be given by Now. this expression may be simplified to give . and drain-to-source voltages smaller than or about 10 V. and is the thickness of the y y inversion layer It is also assumed that the velocity of electrons in this region is saturated. is the diffusion depth of the drain region. the one-dimensional Poisson's equation can be rewritten as: y The solution of this equation leads to the following complicated expression for : y For gate lengths larger than or about 1 .

y

y

In short channel devices, the depletion charge under the channel [dependent on the channel potential and has been represented by the second term within the brackets in the right-hand side of Eq.(5.7)], which has been neglected in the charge control model [Eq.(5.19)], has to be accounted for. This effect may be taken into account by introducing an additional parameter a into the equations of the charge control model, with the resulting equations given by Linear Region

y

y

Saturation Region

y

For Si, the (empirical and fitting) parameter a describes the influence of the bulk substrate depletion layer on the device characteristics, and can be approximated by the following expression

y y

The threshold voltage and the parameter K can be determined from the experimentally measured data for a given device. In addition, the dependence of electron mobility on the longitudinal and transverse electric field in the channel should be included for a more realistic device modeling, however, this simple empirical model gives adequately good fit with the measured data.

**Fig.5.18 The measured and calculated I-V characteristics for a Si n-channel MOSFET.
**

y

Similar to the short channel device, the threshold voltage of a narrow channel (along the width) device increases with a reduction in the effective device width Weff due to the fringing fields outside the gate region, and the change in the threshold voltage as a function of Weff can be given by

where

is a constant.

**Fig.5.19 Variation of the threshold voltage with the channel width.
**

y

y

y y y

y

Another non-ideal effect that may be especially important for short-channel devices is the injection of electrons from the channel directly to the gate dielectric, where these electrons get trapped => hot electron effect. This phenomenon takes place because the carriers gain sufficient energy while traversing the drain depletion region, which contains a high electric field, and has been used to advantage in the FAMOS (Floating gate avalanche MOS) structures used in memories. Avalanche breakdown of the drain-substrate junction can cause a sharp increase in the drain current, and can damage the device unless it is controlled by some external means. Typically, avalanche breakdown for a heavily doped drain-moderately doped substrate junction takes place at approximately 8 to 10 V. Another very important nonideal and potentially hazardous situation may arise due to punchthrough, where the drain and source depletion regions touch each other and cause abnormally large current to flow through the device: this effect is particularly severe for short channel devices. Punchthrough effect creates a superlinear increase in the drain current with the drain voltage, even at gate voltages below the threshold voltage.

Subthreshold Conduction

y y

y

y

So far, we have considered current flow in a MOSFET only when the gate voltage exceeds the threshold voltage. However, in reality, a finite (nonzero) current does flow in a MOSFET even for gate voltages below the threshold voltage, and this effect is more marked for short channel length devices than their long channel counterparts. This current is referred to as the subthreshold current, and it flows for when the surface potential lies between the ranges of the onset of weak inversion and the onset of strong inversion. The mechanism responsible for subthreshold current is quite different for long-channel and short-channel devices. 5.6.1 Subthreshold Current in a Long Channel Device

and the subthreshold current is contributed primarily by diffusion.20 The depletion regions associated with a (a) long channel and (b) short channel device. The drain voltage drops almost entirely across the drain-substrate depletion region. and the substrate is the base. is the region where most electrons are located) is the effective .5. where the source plays the role of the emitter. Thus.y y y In a long channel device. Fig. the component of the electric field parallel to the interface is small. y Thus. the drain is equivalent to the collector. the situation is similar to a BJT. just as the case for BJTs. the subthreshold current can be evaluated as where cross-sectional area.

If the diffusion length of electrons in the substrate is much greater than the channel length L. and Also. the effective depth where most of the electrons are concentrated. the subthreshold current for a long channel MOSFET can be given by y The surface potential by noting that at the source can be expressed as a function of the gate voltage thus. and it decreases with y y y Thus. note that since Using all the relations given above. . given by . y y y is the length of the undepleted For long channel devices. it is assumed that the depletion widths at the source and the drain sides of the channel are small compared to the channel length L. can be estimated as where y = 0 corresponds to the interface. then the electron density n should be a linear function of x.y The electron density n at the surface is proportional to (perpendicular to the where interface) proportionally to is the vertical electric field. decreasing from the source towards the drain (just like the linear distribution of minority carriers in the base of a BJT): where the volume concentrations for electrons sides of the channel are given by at the source and the drain where V(y) is the potential given by portion of the channel.

where y y y y y Note: For the subthreshold current becomes independent of the drain voltage. and.(5. Fig. and since the current is diffusive in nature. and thus the subthreshold current changes. To account for this effect.21 The subthreshold characteristics for a long channel device as a function of the gate voltage for different values of drain and substrate voltages. can not be neglected.67) is replaced by another term Leff. the source and drain depletion widths may be a significant portion of the channel length L. for large since the gradient of n is not affected by the drain voltage: a situation similar to BJTs. Also. Subthreshold Current in a Short Channel Device y y In a short channel device.5. where the collector current in the forward active mode is independent of the collector-to-emitter voltage. hence. there is no change in the current with the drain voltage. most of the applied drain voltage drops at the drain-substrate depletion region. affects the surface potential. Note: the subthreshold current is almost independent of the drain voltage The substrate bias shifts the threshold voltage to a more positive value. This is expected since in a long channel device. the term L in Eq. where where .

.5. a characteristic typical of short channel devices.where is the built-in voltage of the source/drain-substrate junction. and the surface potential is now found from the solution of the following equation: where y y The curves clearly show shifts in the subthreshold current for different values of drain voltages.22 The subthreshold characteristics for a short channel device as a function of gate voltage for different values of drain and substrate voltages. The subthreshold current is a strong function of temperature as well Fig.

Fig. and the derivatives of these charges with respect to the terminal voltages give rise to MOSFET capacitances. the charges in the depletion region and the inversion layer depend on the gate. source. and it contains: the drain-to-source current source IDS. two resistances (due to the quasi-neutral region resistances of the source and drain respectively) The gate-to-drain capacitance The gate-to-body capacitance The source-to-substrate capacitance The drain-to-substrate capacitance . The small signal equivalent circuit shown in Fig. drain.23 The subthreshold characteristics as a function of gate voltage for two different temperatures (77 K and 300 K).5.24 is the one used by the popular circuit simulation package called SPICE.5. MOSFET Capacitances and Equivalent Circuit y y y y Note: in a MOSFET. and substrate potentials.

3: An n-channel MOSFET has Determine SOLUTION: The intrinsic body transconductance The coefficient .y Note: in the presence of series source/drain resistances the intrinsic (internal to the device) conductance and transconductances are related to the extrinsic (measured) transconductances and conductance by the following equation: EXAMPLE 5.

is shown in Fig. Therefore. suitable for the calculation of the current gain.5. significant degradation in the transconductances and drain conductance may take place for large values of source/drain series resistances.5. Another simplified equivalent circuit. . the small signal voltage gain expression can be given by: y y Note: at low frequencies.5.5. For the circuit shown in Fig.26(b).26(a) are the reverse-bias conductances of the source-substrate and drain-substrate diodes.5. Thus.26(b) The simplified equivalent circuit of a MOSFET. and their values are very small (tending to zero).26(c). Fig. y The two conductance terms appearing in the equivalent circuit shown in Fig. the voltage gain can be given by as expected.26(b). y y A simplified equivalent circuit is shown in Fig.and respectively. when the effects of the capacitances can be neglected.

the drain current Thus. in the strong inversion region. This equation gives the theoretical maximum value for Assuming the characteristic switching time for a MOSFET is obtained as .26(c) The alternate simplified equivalent circuit for a MOSFET suitable for the calculation of the short circuit current gain.e. the frequency at which the absolute value of the short circuit current gain is equal to unity) can be given by where y y y y Now.26(c). note that Also. y From Fig..Fig. Hence. where y y is the transit time of electrons in the channel. the short circuit current gain can be easily found to be: y Thus.5.5. the unity gain cutoff frequency (i.

the actual unity-gain cutoff for the device considered in Example 5.2 would be 2. and. an n-channel enhancement type device has a positive . The threshold voltage can be changed either by doping or by ion implantation. the threshold voltage.. whereas an nchannel depletion type device has a negative .2. depletion type devices are normally on. the measured switching times for MOSFETs are at least several times larger than that predicted above due to the parasitic and fringing capacitances that has to be added to the gate capacitance leading to the following modified expression for : EXAMPLE 5. Similarly. assuming Example 5. i. To put it simply. Compare this value with theoretical maximum value for SOLUTION: The unity-gain cutoff frequency The theoretical maximum value for = = 7. thus. a p-channel enhancement type device has a negative . they can change the charge state of the surface.82 GHz. which is smaller of the two.e. MOSFETs can be categorized into two types: enhancement and depletion. On the other hand. Enhancement type devices are normally off. Types of MOSFETs y y y Broadly. y y y ..y In reality.e.96 GHz. An actual device would show a cutoff frequency. where high energy ions are made to bombard the surface and get embedded into it: since these are charged. hence. i. channel does exist even for and the applied must be reduced below for the device to turn off. channel does not exist for and the applied must be greater than for the device to turn on.4: Calculate the unity-gain cutoff frequency for the MOSFET considered in . whereas a p-channel depletion type device has a positive .

). etc. As.(4. the type of implant required is positive ions (e.24)] has to be modified to account for the channel potential. y In order to get a better understanding of the term the charge control model. however.y The shift in the threshold voltage is related to the ion density by the relation: eg. thus. the inversion charge is related to the gate-source and channel potential as follows: where is the quasi-Fermi (electrochemical) potential measured relative to the Fermi potential at the source side of the channel. P. on the position along the channel. given by first consider the simplified version of .. the UCCM equation for MIS capacitors [Eq.5: An n-channel MOSFET with has a threshold voltage Determine the type and dose of ion implantation required to make it a depletion mode device with SOLUTION: The oxide capacitance per unit area The dose of ion implantation required Since the threshold voltage is shifting towards negative value. which would compensate the negative depletion charge of the substrate and push the threshold voltage towards negative direction. and. Some Advanced Models Unified Charge Control Model for MOSFETs y For MOSFETs. note the same ions would shift the threshold voltage to more positive for n-channel (p-substrate) device. Sb. negative ions (like Boron) implanted in a p-channel (n-substrate) device will compensate some of the positive depletion charges and make the threshold voltage less negative. obviously. hence. hence. and the parameter accounts for the dependence of the threshold voltage on the channel potential in strong inversion.g. EXAMPLE 5..

Another important parameter is the channel potential at the boundary point . The intrinsic saturation voltage can be defined as the intrinsic drain-source voltage for which the longitudinal electric field at the drain end of the channel just becomes equal to the saturation field For the location in the channel where marks the boundary between the saturated and the non-saturated regions.y y Now. one obtains A generalized solution for ns is used in UCCM. if Eq. given by y This equation allows the direct determination of the carrier distribution along the channel as a function of Saturation Region: The Region of the Channel with Velocity Saturation y y y y y y y y Of late. Another assumption made is that the substrate is lowly doped: this assumption oversimplifies the true physics of the saturation region. However. the threshold voltage depends on the depletion charge. however. which implies that the carrier sheet density in the saturated part of the channel is also constant. since an accurate modeling of the pinch-off region is essential in order to obtain an exact drain current model in saturation. Thus. one can write where now is the value of the threshold voltage at the source side of the channel. which gives a fairly good fit to experimental data with a judicious choice of parameters such as the saturation velocity and the effective channel thickness. Taking into account the dependence of this charge on the channel potential. The boundary point moves towards the source with increasing drain-source voltage: this effect is called the channel length modulation. Important to find a solution for the longitudinal field in the channel. in reality. one can write the corresponding position dependent threshold voltage as y y y y This makes the charge control equation nonlinear and difficult to use in device modeling. it also leads to a manageable theory with qualitatively correct features.90) is linearized with respect to V. The model relies on the fundamental assumption that the carrier velocity in the saturated part of the channel is constant and equal to the saturation velocity.(5. area of considerable interest.

it is necessary to consider a two-dimensional Poisson's equation of the form y . and the velocity be continuous at For a description of the saturated region.y The two parameters and on the intrinsic gate-source voltage and have to be determined self-consistently using the models for the two regions with the requirement that the potential. the electric field.

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