M.E.

(E&TC)

Review of High Frequency PLL

Chapter 1 Introduction
1.1 Background:Phase locked loops (PLLs) are an essential component in many wireline and wireless applications for clocking and frequency synthesis. The challenges of developing stable, low jitter clock sources become greater as the operating frequency is increased. With the integration of digital and analog circuits CMOS technologies are a preferred solution because of their documented high frequency performance and well established manufacturing base. The generation of higher frequency clock signals continues to be driven by wireless applications and high - speed digital links. There is an advantage from a phase noise perspective to generate multiplied clock frequencies using a low - order multiple instead of the lager multiplication factors commonly used. This low multiplication factor requires that the components of the phase locked loop (PLL) be able to operate at higher frequencies. A phase locked loop, or more commonly abbreviated as PLL is basically a closed loop feedback system. The action of the PLL is to lock the output frequency and phase to the frequency and phase of an input signal. The input signal can be sinusoidal or digital. Phase locking is not a new principle. Synchronous reception of radio signals using PLL technique was described as early as in 1932. The implementation of PLL with discrete components involves circuits of considerable cost and complexity. For this reason, the use in the past has been limited to specialized measurements. The development of monolithic PLL now makes it highly economical as well as reliable. The early applications of PLL were the synchronous detection of radio signals. Starting in the 1960s' the NASA satellite programmers used the PLL technique to determine the frequency of the signals transmitted by satellite. However, there was an uncertainty of several kHz in the received signal due to oscillator drift and Doppler shift. The transmitted signal was of very narrow bandwidth, but because of the frequency drifts it was necessary that the receiver bandwidth be much wider, with a resultant increase in noise, as receiver noise

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SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010

M.E. (E&TC)

Review of High Frequency PLL

power is proportional to the bandwidth. However, the satellite communication system was improved by using a phase - locked loop to lock onto the transmitted frequency, and thus permit a much narrower bandwidth with much less output noise content. 1.2 Relevance:The digital phase - locked loop, DPLL, is a circuit that is used frequently in modern integrated circuit design.In fact, the PLL is used in communication system in two fundamentally different ways : (i) as a demodulator, where it is used to follow phase or frequency modulation, and (ii) to track a carrier or synchronizing signal which may vary in frequency with time. When operating as a demodulator, the PLL may be thought of as a matched filter operating as a coherent detector. When used to track a carrier, it may be thought of as a narrow - band filter for removing noise from a signal. This session presents current trends in PLLs that explore innovations in all optical and high frequency PLLs. A common theme in all high frequency PLLs to improve the locking range, gain, noise. Seven of the eight papers in this session address this issue as follows: 1. This paper focused on locking range, noise, line width. The requirement for narrow linewidth lasers or short - loop propagation delay makes the realization of optical phase - lock loops using semiconductor lasers difficult. 2. This paper focused on Gain, Optical Phase lock. This paper describes inline optical phase sensitive amplifier (PSA) with a pump laser whose optical phase is locked to that of a randomly modulated signal by using an optical phase - lock loop (OPLL). 3. This paper focused on SSB noise locking bandwidth. We report the first experimental demonstration of millimeter - wave modulated optical signal generation by an optical injection phase - lock loop. 4. This paper focused on Phase Noise analysis.

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SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010

lock loop (PLL) clock multiplier using a 0. Comparison table. 6. Literature survey. This paper focused SSB Noise density Locking range.18 . (E&TC) Review of High Frequency PLL 5. Conclusion. 3 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . Review of high frequency PLL.M.3 Organization of seminar report:This seminar report consists of Introduction.µ m CMOS process. This paper will present an investigation into the phase detector of a 27 GHz phase .E. 1.

defined amplitudes) after passing through the communication channel.recovery circuit or bit synchronization circuit. Consider the waveform and block diagram of a communication system shown in Fig.M. However.E. The data is shifted out sequentially to the transmitter output driver. DPLL. is a circuit that is used frequently in modern integrated circuit design. The next logical step in this sequence is to shift the data back into a shift register at the receiver and process the received data. The generated clock signal of the receiver clocks the shift register and thus recovers the data. without well .1 Block diagram of a communication system using A DPLL for the generation of a clock signal. thus. The DPLL performs the function of generating a clock signal which is locked or synchronized with the incoming signal. 2. At the receiving end. The possible clock signals are labeled 4 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . the absence of a clock signal makes this difficult.Locked Loops:The digital phase .locked loop.2. where the data may be analog (and. Figure 2. the receiver amplifies and changes the data back into digital logic levels. 2.1 Digital Phase . A more detailed picture of the incoming data and possible clock signals out of the DPLL are shown in Fig.1 Digital data is loaded into the shift register at the transmitting end. This application of a DPLL is often termed a clock . (E&TC) Review of High Frequency PLL Chapter 2 Literature Survey 2.

This signal is filtered by a loop filter. corresponding to the type of phase detector (PD) used. the rising edge of the clock occurs in the center of the data. The PD generates an output signal proportional to the time difference between the Data in and the divided down clock. the resting edge occurs at the beginning of the data. For the XOR PD.3. V is connected to the input of a voltage .E. 2. while for the PFD. Figure 2. Figure 2.2 Data input to DPLL in lack and possible clock outputs using the XOR phase detector and PFD.controlled oscillator (VCO). The filtered signal. 5 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .M.The lock range of the PLL is the range of loop frequency about the central frequency for which the loop maintains lock. The phase of the clock signal is determined by the PD used. 2.2 1. Important Parameters:Lock Range . A block diagram of a DPLL is shown in Fig.3 Block diagram of a digital phase .locked loop. (E&TC) Review of High Frequency PLL XOR clock and PFD (phase frequency detector) clock. Locking range is limited by phase comparison range. dclock.

E. 2. In the section following this one.4 shows the idealized case when the clock doesn't jitter. (E&TC) Review of High Frequency PLL 2.recovery and synchronization circuits.In the most general sense. This is always less than lock range. This is always less than lock range.loop gain affects the phase errors between the input signal and the VCO for a given frequency shift of 6 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . we neglect power supply and oscillator noise. Capture Range . we assume that the oscillator frequency is an exact number that is directly related to the VCO input voltage. 4.The capture range is the range of input frequency for which the initially unlocked loop will lock all an input signal. that is. we cover delay . while shows the actual situation where the clock .locked loops and further discuss the limitations of the VCO. Figure 2. In the following discussion.4 a) Idealized view of clock and data without Jitter and b) with jitter. Loop gain & Natural frequency .M. Capture Range . Figure 2.The capture range is the range of input frequency for which the initially unlocked loop will lock all an input signal. 3. can be defined as the amount of time the regenerated clock varies once the loop is locked.rising edge moves in time (jitters). for clock . the oscilloscope is triggered by the rising edge of the data. In these figures. jitter .

Noise will show up in the input signal as both amplitude and phase modulation. 5.M. This is because the loop will remain in lock as long as phase errors θ e is less than + 900. 6. R2 and C (in case of lag . and the loop gain. and the noise appears as phase modulation. (E&TC) Review of High Frequency PLL input signal. a limiter should be used ahead of the phase detector.in time and lock range. the further the input can change in frequency before the 900 phase errors is reached. When designing the loop filter components. enough bandwidth in the loop must be allowed for instantaneous phase change due to input noise. pull . Requirements that will have an effect on loop bandwidth: i) ii) Loop bandwidth must be as narrow as possible to minimize output phase jitter due to external noise. and to obtain best tracking and capture or acquisition properties.E. 7 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . To obtain optimum performance. The loop bandwidth should be made as large as possible to minimize transient error due to signal modulation. amplitude modulation of the input signal by noise is removed. Since the loop gain is normally selected by the criteria as discussed above. With the use of a limiter. output jitter due to internal oscillator (VCO) noise. It also determines the lock range of the loop providing no components of the loop go into limiting or saturation. The higher loop then. it is helpful to look at how noise affects the operation of the loop. the filter components are used to select the bandwidth.Since on of the main uses of PLL is to demodulate or track signals in noise. The selection of loop bandwidth may be governed by several things noise bandwidth. The same result is obtained if the phase detector itself is allowed to operate in limiting. Noise .The bandwidth of the loop is determined by the filter components R1. Loop Bandwidth . modulation rates if the loop is to be used as an FM demodulator.lead filter).

noise. Theoretical and experimental results for a system which combines both techniques so as to overcome these limitations.lock loops using semiconductor lasers difficult. Phase error variance values as low as 0. a mean time to cycle slip of 3 x 1010 s and SSB noise density of .M. Although optical injection locking can provide low phase error variance for wide line width lasers.003 rad in bandwidth of 100 MHz. gain.1)High-Performance Phase Locking of Wide Line width Semiconductor Lasers by Combined Use of Optical Injection Locking and Optical PhaseLock Loop : This paper focused on locking range. This paper describes in-line optical phase sensitive amplifier (PSA) with a pump laser whose optical phase is locked to that of a randomly modulated signal by using an optical phase . are reported. Optical Phase lock.[1] 3.94 dBc/Hz at 10 kHz offset were obtained for the same lasers in an heterodyne OIPLL configuration with loop propagation delay of 20 ns and injection ratio of 30 dB. Phase error variance values as low as 0. the optical injection phase . noise. These papers in this session address this issue.30 dB.lock loop (OIPLL).006 rad (500 MHz bandwidth) and locking ranges exceeding 26 GHz were achieved in homodyne OIPLL systems using DFB lasers of summed line width 36 MHz. the locking range is restricted by stability considerations. line width.2) In-Line Optical Phase-Sensitive Amplifier with Pump Light Source Controlled by Optical Phase-Lock Loop: This paper focused on Gain. The OPLL is designed with the capability of optical phase locking at an arbitrary relative phase. The requirement for narrow linewidth lasers or short .lock loop (OPLL).loop propagation delay makes the realization of optical phase . Experimental evaluation is presented of the OPLL employing a 8 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .optical and high frequency PLLs. loop propagation delay of 15 ns and injection ratio less than . 3.E. A common theme in all high frequency PLLs is to improve the locking range. (E&TC) Review of High Frequency PLL Chapter 3 Review of High Frequency PLL In this session presents 7 papers that explore innovations in all .

18 .wave modulated optical signal generation by an optical injection phase .M. (E&TC) Review of High Frequency PLL newly developed external cavity semiconductor ring laser with a spectrum linewidth of less than 20 kHz.E.lock loop. The locking bandwidth exceeded 30 GHz.conversion module allows the use of lower frequency components in the control circuits with a reduced cost. [4] 3. and phase error variance lower than 0.tunable microwave signal is proposed and demonstrated. An OPLL based on the proposed configuration is implemented. A 36 . the new design allows continuous frequency tuning of the generated microwave signal.4) Discriminator-Aided Optical Phase-Lock Loop Incorporating a Frequency Down-Conversion Module:This paper focused on Phase Noise analysis. Employing this pump laser with the OPLL in conjunction with a 44 . highly frequency . A new discriminator .lock loop (PLL) clock multiplier using a 0.conversion concept is presented. The phase noise performance.stable.92 dBc/Hz at 10 kHz offset. 3. along with a phase noise analysis detailing the contributions to the phase noise from the reference sources. We report the first experimental demonstration of millimeter .lock loop (OPLL) incorporating a frequency down . A randomly modulated signal is successfully amplified and confirmed offering a clear eye-opening[2]. Single sideband noise spectral density of . In addition.aided optical phase .5) A 27 Ghz Phase-Lock Loop Phase Detector This paper will present an investigation into the phase detector of a 27 GHz phase .GHz signal was generated by combining optical sideband injection locking with optical phase . The inclusion of the frequency down .005 rad2 in a 100 MHz bandwidth were measured.conversion module to generate a low phase noise. 9 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .µ m CMOS process. as well as the frequency stability is experimentally studied. [3] 3.lock loop techniques for two fibers .km long nonlinear fiber Sagnac interferometer (NFSI) yields optical phase-sensitive gain of up to 11 dB. The down .coupled DFB lasers. and frequency .3) Millimeter-Wave Modulated Optical Signal Generation with High Spectral Purity and Wide-Locking Bandwidth Using a Fiber Integrated Optical Injection Phase-Lock Loop :This paper focused on SSB noise locking bandwidth.

M.kHz offset and mean time to cycle slip of 3 x 1010 s have been achieved using DFB lasers of 36 . A low multiplication factor has been selected that provides a benefit in the multiplicative phase noise contribution. with it.) non . requiring a high .75 GHz are presented.94 dBc / Hz at 10 . 3.lock reliability with semiconductor lasers. The requirements for narrow line width lasers or short .error variance as low as 0. the offset may be lessened with an increase in the local oscillator switching core gate source voltage.6) High-Performance Heterodyne Optical Injection Phase-Lock Loop Using Wide Line width Semiconductor Lasers :This paper focused SSB Noise density Locking range. Although optical injection locking can provide low phase . [5] 3.loop propagation delay limit optical phase .e.CMOS process and operating at 6.900 phase offset for a 0 V control voltage output in the phase detector) has been undertaken. its locking range is limited by stability considerations.18µ m . The first experimental results for a heterodyne optical injection phase .speed frequency divider and phase detector.7 ) A 3. Simulated and measured result for a Gilbert cell phase detector realized in the TSMC 0. single .ideal performance (i. The objective is to study the various synchronizers output jitter UIRMS (Unit Interval Root Mean Squared as function of the input SNR (Single to Noise Ratio). a loop propagation delay of 20 ns and an injection ratio of .E.5GHz Wideband ADPLL with Fractional Spur Suppression Through TDC Dithering and Feed forward Compensation :This paper focused jitters.30 Db[6].003 rad2 in a bandwidth of 100 MHz. Phase .error variance. (E&TC) Review of High Frequency PLL The phase detector is one part of a multi faceted project involving the development and verification of the various components composing the phase lock loop. A study of the non .[7] 10 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .lock loop are reported. samples and retains the data. The symbol synchronizer recoveries the clock and after.MHz summed line width.sideband (SSB) noise density of .

Walton. Low SSB noise 2) April 99 In-Line Optical Phase-Sensitive Wataru Imajuku and density This paper describes an in-line optical However. C. Seeds. (E&TC) Review of High Frequency PLL Chapter 4 Comparison of High Frequency PLL In this chapter we compare the different high frequency PLLs . 99 Topic High-Performance Phase Locking of Wide Line width Semiconductor Lasers by Combined Use of Optical Injection Locking and Optical PhaseLock Loop Author A. Phase error Variance very low 3. Year of publishing 1) Feb. Low injection ratio 7. and Alwyn J. IEE Work done Describes optical having: 1. The work done by the author and work yet to be done is presented in the tabular form as follows : Table No.1 Comparison of High Frequency PLLs with Different Parameters. Fellow.E. Locking range 2. Bordonalli. C. Line width low 5. pump leakage was Yet to be done The amount of power injected into the Slave laser cavity (injection ratios 40 dB) to provide low phase noise leads to limitation in the stable locking range of Such systems.M. phase-lock loops 11 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . 4. Locking range exceeds 4. Low loop propagation delay 6.

M. 3) June 2000 Millimeter-Wave Modulated Optical Signal Generation with High Spectral Purity and WideLocking Bandwidth Using a Fiber Integrated Optical Injection Phase-Lock Loop . A.E. Report the first experimental demonstration of millimeter-wave modulated optical signal generation by an optical injection phase-lock loop SSB noise density -92db at 10khZ offset Locking bandwidth >30GHZ Large locking range Excellent locking 12 considerable and degraded the extinction ratio of the optical phase is locked output signal. Johansson and A. (E&TC) Review of High Frequency PLL Amplifier with Pump Light Source Controlled by Optical PhaseLock Loop Atsushi Takada phase sensitive amplifier (PSA) with a pump laser whose to that of a randomly modulated signal by using an optical phase-lock loop (OPLL) Gain Employing this pump laser with the OPLL in conjunction with a 4. J.4-km long nonlinear fiber Signal interferometer (NFSI) yields optical phasesensitive gain of up to 11 dB. SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . L. as the slave laser output power varied. Seeds Loss of lock occurred due to limitations of the current tuning range of The slave laser and changes in the injection ratio.

Senior Member. 13 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .M. The majority of the testing was carried out using single-ended RF and LO excitation because of equipment It is possible to reduce the zero voltage crossing error by The histogram plot of the stability data an almost Gaussian distribution of the peak frequency about the mean During this period. Carr Brian M. Ride out. Seregelyi. (E&TC) Review of High Frequency PLL bandwidth Long term 4) Nov 2006 DiscriminatorAided Optical Phase-Lock Loop Incorporating a Frequency DownConversion Module Howard R. Stéphane Paquet. and Jianping Yao. along with a phase noise analysis detailing the contributions to the phase noise from 5) May 2006 A 27 Ghz PhaseLock Loop Phase Detector John P. (PLL) clock multiplier limitations. and frequency-tunable microwave signal is proposed and demonstrated The down-conversion concept is presented.E. Frank the reference sources This paper will present an investigation into the phase detector of a 27 GHz phase-lock loop using a 0. Further trials over longer intervals are required to confirm this distribution. IEEE stability A new discriminatoraided optical phaselock loop (OPLL) incorporating a frequency downconversion module to generate a low phase noise.18−μm CMOS process. Joe S. highly frequency-stable.

Bordonalli. variance Dithering and Feed Marco 14 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . Cusmai2. A.2. as long term fluctuations can be compensated electronically by the OPLL path while fast fluctuations can be followed by the OIL path. Francesco Svelto2 We present a 3.M. C.E.5GHz Wideband ADPLL with Fractional Spur Suppression Through TDC forward Compensation Colin WeltinWu1. at the expense of increased circuit 6) March 98 High-Performance Heterodyne Optical Injection PhaseLock Loop Using Wide Line width Semiconductor Lasers C. J. Enrico Temporiti3. Daniele Baldi3. Seeds Low phase error Locking range limited by stability considerations SSB noise density -94db/Hz The first experimental results for an heterodyne optical injection phase-lock loop are reported 7) Feb2010 A 3. Using a dithering algorithm and feed forward compensation around the TDC results in spurious performance complexity and power Tracking capability of the combined OIPLL system is improved Compared with the equivalent OPLL and OIL systems.4MHz bandwidth operating from a 35MHz reference. (E&TC) Review of High Frequency PLL increasing the gate-source voltage at the LO switching core. Walton. and A.5GHz fractional-N ADPLL with a 3.

Japan 2.2V supply Low phase noise 15 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 Although there is no spurious noise due to modulator periodicity of cycles.8 GHz A 2. and in-band phase noise of -101dBc/Hz. TDC is presented. This is caused by insufficient isolation between the logic-gates driven by the reference signal. the reference spur of observed. and can be Improved in a redesign.M. and consumes 8.1mA from a 1. The chip draws 8. Low in phase noise Low power supply PLL range 8]Feb2010 A 2. NEC. The IC with fully integrated calibration logic occupies 0. Tokairin.44mm2 in 65nm CMOS.7mW.8 GHz to 3.1-to-2.8GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC T. (E&TC) Review of High Frequency PLL better than -58dBc. The 40dBc spurs was in-band phase noise of DCO and the digital . Kawasaki.1-to-2.8GHz lowpower all-digital PLL with a time-windowed single-shot pulsecontrolling 2-step test-chip is implemented in 90nm CMOS and exhibits -105dBc/Hz with 500kHz loopbandwidth and out-ofband noise of -115dBc/Hz at 1MHz offset.E.

the DPLLperformance parameters are as follows: Table No.99 [1] >26 GHz NA NA 36 MHz 94dBc/ Hz April99 [2] NA 11dB NA <20KHz 90dBc/ Hz June2000 Nov2006 May2006 March98 [3] >30 GHz NA NA 30GHz -92 dBc / Hz [4] NA 3dB 11.3 summarizes the performance of the ADPLL IC and compares with that of other previously reported works.75 GHz NA NA [6] >24GHz NA NA 36MHz 94dBc / Hz Table No.7 dBc/Hz [5] NA NA 6.2 GHz NA -64. (E&TC) Review of High Frequency PLL Low power consumption In short. This is caused by insufficient isolation between the DCO and the 16 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .1mA from 1. 4. Although there is no spurious noise due to ΔΣ modulator periodicity of cycles.2V supply.E. This table indicates that our ADPLL IC has low in-band phase-noise of -105dBc/Hz with low power consumption of 8. the reference spur of 40dBc spurs was observed. 4.M.2 DPLL Performance Parameters Parameter s Locking Range Loop gain Natural Frequency Loop Bandwidth Noise Feb.

and can be improved in a redesign.M. 4.E. Table No. (E&TC) Review of High Frequency PLL digital logic-gates driven by the reference signal.3 DPLL Performance Parameters [7] 17 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .

18 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .E.M.4 DPLL Performance Parameters [8] This table 4. (E&TC) Review of High Frequency PLL Table No.4 describe the ADPLL Performance parameters. 4.

jitters and delay are the parameters taking into consideration form the study of IEEE papers and books. A common theme in all high frequency PLLs is to improve the locking range. 19 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 .3. (E&TC) Review of High Frequency PLL Chapter 5 Conclusion This review helps to study the Digital PLL. locking range.1 and 4. Future DPLLS will have much greater performance as mention in Table no 4. Noise. gain and noise.E.M.

Ottawa. Senior Member. 17. 18. (E&TC) Review of High Frequency PLL REFERENCES 1) Bordonalli.8 ghz All – Digital Frequency Synthesizer With A Time-Windowed TDC ” 2010 IEEE International SolidState Circuits Conference. 2. IEEE "Millimeter-Wave Modulated Optical Signal Generation with High Spectral Purity and WideLocking Bandwidth Using a Fiber-Integrated Optical Injection Phase-Lock Loop" Ieee Photonics Technology Letters. 12. Walton. and Simulation 6) 7) John P. 17. November 15.R.Tenth Edition. A. 6. Botkar “Integrated Circuits “Khanna Publication. No. J. Francesco Svelto ” A 3.. Seeds. C. Mitsuji Okada 2. Seeds.1 –To -2. No. 22.E. Frank. Marco Detector" IEEE Ccece/Ccgei. Through TDC Dithering and Feedforward Compensation ” 2010 IEEE International Solid – State Circuits Conference. 9) K.M. June 2000. 20 SCOE ELECTRONICS & TELECOMMUNICATION ENGINEERING – 2009-2010 . Rideout. and Jianping Yao. 2. Vol. IEEE “HighPerformance Phase Locking of Wide Linewidth Semiconductor Lasers by Combined Use of Optical Injection Locking and Optical Phase-Lock Loop Journal Of Lightwave Technology Vol. Joe S. Stéphane Paquet. Carr. Daniele Baldi 3. Layout. Fellow. Masaki Kitsunezuka 1. IEEE "Discriminator-Aided Optical Phase-Lock Loop(Incorporating a Frequency Down-Conversion Module" Ieee Photonics Technology Letters. No. No. 4) Howard R. Brian M. Seregelyi. February 1999 2) Wataru Imajuku and Atsushi Takada "In-Line Optical Phase-Sensitive Amplifier with Pump Light Source Controlled by Optical Phase-Lock Loop" Journal Of Lightwave Technology. 4.Muneo Fukaishi “ A 2. April 1999 637 3) L. Vol. "A 27 Ghz Phase-Lock Loop Phase Colin Weltin-Wu1. May 2006 Cusmai 2. and Alwyn J. Johansson and A. Tadashi Maed 1.5 GHz Wideband ADPLL with Fractional Spur Suppression . Fellow. Enrico Temporiti 3. Vol. 8) Takashi Tokairin 1. 2006 5) CMOS Circuit design.