Intro to System Generator

This material exempt per Department of Commerce license exception TSU

© 2007 Xilinx, Inc. All Rights Reserved

Objectives
After completing this module, you will be able to:

Explain why there is a need for an integrated flow from system design to implementation Describe System Generator and the tools with which it interfaces

Intro to System Generator - 02 - 3

© 2006 Xilinx, Inc. All Rights Reserved

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All Rights Reserved MATLAB • The MathWorks MATLAB provides a technical computing environment that facilitates rapid exploration of mathematical solutions to systems problems – – Extensive libraries for math functions.02 . Inc. Inc.4 © 2006 Xilinx.02 .5 © 2006 Xilinx. DSP.Outline • • • Introduction System Generator Design Flow Summary Intro to System Generator . All Rights Reserved 2 . and much more Visualization: Large array of functions to plot and visualize your data and system and design Intro to System Generator . signal processing. communications.

including quantization and overflow Simulation of double precision as well as fixed point © 2006 Xilinx. Inc. for example Communications blockset: modulation or DPCM. for example © 2006 Xilinx. logic operators.6 Overview of System Generator for DSP • The industry’s system-level design environment (IDE) for FPGAs – – Integrated design flow from the Simulink™ software to the BIT file Leverages existing technologies • • • • MATLAB .Simulink Visual data flow tool • The MathWorks Simulink provides a modelbased design environment for the development of executable specs of dynamic systems – – – – – Fully integrated with the MATLAB engine Graphical block editor Event-driven simulator Models parallelism Extensive library of parameterizable functions • • • Simulink blockset: math. and sources DSP blockset: filters or transforms. All Rights Reserved Intro to System Generator . All Rights Reserved • Arithmetic abstraction – – Intro to System Generator . Simulink HDL synthesis IP Core libraries FPGA implementation tools • Simulink library of arithmetic.02 . sinks. Inc.02 . and DSP functions (Xilinx blockset) – BIT and cycle-true to FPGA implementation Arbitrary precision fixed-point.7 3 .

Spartan-3.8 © 2006 Xilinx. Inc. Virtex-E. simulation DO file generation HDL co-simulation via HDL C-simulation • Verification acceleration by using hardware-in-the-loop through Parallel Cable IV.5. Virtex-II Pro. Virtex. Inc.9 © 2006 Xilinx. Virtex-II. All Rights Reserved 4 . Spartan™-3E. Spartan-IIE. All Rights Reserved System Generator for DSP Platform Designs ISIM Intro to System Generator . and Spartan-II devices – – – – – – – – Hardware expansion and mapping Synthesizable VHDL and Verilog with model hierarchy preservation Mixed-language support for VHDL/Verilog Automatic invocation of the CORE Generator™ software to utilize IP cores ISE project generation to simplify the design flow HDL testbench and test vector generation Constraint file (XCF). Platform Cable USB. and Network-based as well as Point-toPoint Ethernet connections Intro to System Generator .Overview of System Generator for DSP • VHDL and Verilog code generation for Virtex™. Virtex-4.02 .02 .

02 .02 . Inc.11 © 2006 Xilinx.Outline • • • Introduction System Generator Design Flow Summary Intro to System Generator . All Rights Reserved Model Based Design using System Generator • Develop an executable spec using Simulink • Refine the hardware algorithm using System generator – Verify hardware against executable spec Intro to System Generator . All Rights Reserved 5 .10 © 2006 Xilinx. Inc.

13 © 2006 Xilinx. All Rights Reserved 6 . Inc.12 © 2006 Xilinx.02 .The SysGen Design Flow Develop Executable Spec in Simulink System Generator Develop System Generator representation Xilinx DSP Blockset Xilinx CoreGen Automatic RTL generation Testbench Generation RTL Xilinx Implementation Flow Bitstream RTL Verification with ModelSim Download to FPGA Intro to System Generator . All Rights Reserved SysGen-Based Design Flow Simulink Verification MATLAB/Simulink HDL System Generator System Verification Synthesis Functional Simulation Implementation Timing Simulation Download In-Circuit Verification Intro to System Generator .02 . Inc.

02 .SysGen-Based Design Flow HDL-CoSim Verification MATLAB/Simulink HDL System Generator System Verification Synthesis Functional Simulation Files Used • Configuration file • HDL • IP • Constraints File HDL Co-Simulation* Implementation Timing Simulation Download * In-Circuit Verification ModelSim helper block not needed when ISIM simulator is used Intro to System Generator . Inc.14 © 2006 Xilinx.15 © 2006 Xilinx. All Rights Reserved SysGen-Based Design Flow HWIL Verification MATLAB/Simulink HDL System Generator System Verification Files Used • Configuration file • HDL • IP • Constraints File HWIL Co-Simulation Synthesis Functional Simulation Implementation Timing Simulation Download In-Circuit Verification Intro to System Generator . All Rights Reserved 7 .02 . Inc.

16 © 2006 Xilinx. Inc. Inc.02 . All Rights Reserved Knowledge Check Intro to System Generator .02 . All Rights Reserved 8 .Outline • • • Introduction System Generator Design Flow Summary Intro to System Generator .17 © 2006 Xilinx.

02 . This toolbox provides an integrated design flow by leveraging existing technologies. All Rights Reserved 9 .Knowledge Check • Describe System Generator and the tools with which it interfaces • Describe how System Generator helps in DSP System Design Intro to System Generator . All Rights Reserved Answers • Describe System Generator and the tools with which it interfaces – System Generator is a toolbox running under the Simulink environment.19 © 2006 Xilinx. Inc. and FPGA implementation tools • Describe how System Generator helps in DSP System Design – It provides a simple push-button flow for design and development under Simulink environment and provides HDL co-simulation and hardware-in-theloop acceleration verification capability Intro to System Generator . such as HDL synthesis.18 © 2006 Xilinx. IP Core libraries. Inc.02 .

xilinx.com/dsp Intro to System Generator .Summary • • • Traditional system design using Simulink left gap between system designer and FPGA designer System Generator toolbox fills that gap so a system designer can design a DSP system in FPGA System Generator uses Simulink toolbox.21 © 2006 Xilinx. Xilinx HDL synthesis.02 . and FPGA implementation tools Intro to System Generator . All Rights Reserved 10 .02 . Inc.20 © 2006 Xilinx. IP Core libraries. Inc. All Rights Reserved Where Can I Learn More? • Software documentation – Simulink Browser → Help → Simulink Help → Xilinx System Generator • • • Hardware Design Using System Generator → Design Flows Using System Generator Hardware Design Using System Generator → System Level Modeling Hardware Design Using System Generator → Automatic Code Generation • Support Website – DSP Website: http://www.

xilinx.com/support → Answer Browser (under Support Quicklinks) • www.Where Can I Learn More? • Answer Record database: Search by FPGA family or software tool – www.com/xlnx/xil_ans_browser. All Rights Reserved 11 .jsp Note for instructor: Take a moment to click the link above and browse through the Records. Intro to System Generator .02 .xilinx.22 © 2006 Xilinx. Inc.