© 2010 Microchip Technology Inc.

DS41190G
PIC12F629/675
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
DS41190G-page 2 © 2010 Microchip Technology Inc.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC
32
logo, rfPIC and UNI/O are registered trademarks of
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
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All other trademarks mentioned herein are property of their
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© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-160-4
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, KEELOQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2010 Microchip Technology Inc. DS41190G-page 3
PIC12F629/675
High-Performance RISC CPU:
• Only 35 Instructions to Learn
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect, and Relative Addressing modes
Special Microcontroller Features:
• Internal and External Oscillator Options
- Precision Internal 4 MHz oscillator factory
calibrated to ±1%
- External Oscillator support for crystals and
resonators
- 5 us wake-up from Sleep, 3.0V, typical
• Power-Saving Sleep mode
• Wide Operating Voltage Range – 2.0V to 5.5V
• Industrial and Extended Temperature Range
• Low-Power Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Detect (BOD)
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Multiplexed MCLR/Input Pin
• Interrupt-on-Pin Change
• Individual Programmable Weak Pull-ups
• Programmable Code Protection
• High Endurance Flash/EEPROM Cell
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years
Low-Power Features:
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
- 8.5 uA @ 32 kHz, 2.0V, typical
- 100 uA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current
- 300 nA @ 2.0V, typical
• Timer1 Oscillator Current:
- 4 uA @ 32 kHz, 2.0V, typical
Peripheral Features:
• 6 I/O Pins with Individual Direction Control
• High Current Sink/Source for Direct LED Drive
• Analog Comparator module with:
- One analog comparator
- Programmable on-chip comparator voltage
reference (CVREF) module
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
• Analog-to-Digital Converter module (PIC12F675):
- 10-bit resolution
- Programmable 4-channel input
- Voltage reference input
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTOSC mode
selected
• In-Circuit Serial Programming
TM
(ICSP
TM
) via
two pins
* 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
Device
Program
Memory
Data Memory
I/O
10-bit A/D
(ch)
Comparators
Timers
8/16-bit
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC12F629 1024 64 128 6 — 1 1/1
PIC12F675 1024 64 128 6 4 1 1/1
8-Pin Flash-Based 8-Bit CMOS Microcontroller
PIC12F629/675
DS41190G-page 4 © 2010 Microchip Technology Inc.
Pin Diagrams
VSS VDD
GP5/T1CKI/OSC1/CLKIN
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
1
2
3
4 5
6
7
8
P
I
C
1
2
F
6
7
5
VSS VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
1
2
3
4 5
6
7
8
P
I
C
1
2
F
6
2
9
8-pin PDIP, SOIC, DFN-S, DFN
© 2010 Microchip Technology Inc. DS41190G-page 5
PIC12F629/675
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 7
2.0 Memory Organization.................................................................................................................................................................. 9
3.0 GPIO Port ................................................................................................................................................................................. 21
4.0 Timer0 Module.......................................................................................................................................................................... 29
5.0 Timer1 Module with Gate Control ............................................................................................................................................. 32
6.0 Comparator Module .................................................................................................................................................................. 37
7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ................................................................................................... 43
8.0 Data EEPROM Memory ............................................................................................................................................................ 49
9.0 Special Features of the CPU .................................................................................................................................................... 53
10.0 Instruction Set Summary ........................................................................................................................................................... 71
11.0 Development Support ............................................................................................................................................................... 81
12.0 Electrical Specifications ............................................................................................................................................................ 85
13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 107
14.0 Packaging Information ............................................................................................................................................................ 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 127
Appendix B: Device Differences ....................................................................................................................................................... 127
Appendix C: Device Migrations ......................................................................................................................................................... 128
Appendix D: Migrating from other PIC
®
Devices .............................................................................................................................. 128
Index ................................................................................................................................................................................................. 129
On-Line Support ................................................................................................................................................................................ 133
Systems Information and Upgrade Hot Line ..................................................................................................................................... 133
Reader Response ............................................................................................................................................................................. 134
Product Identification System ........................................................................................................................................................... 135
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PIC12F629/675
DS41190G-page 6 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 7
PIC12F629/675
1.0 DEVICE OVERVIEW
This document contains device specific information for
the PIC12F629/675. Additional information may be
found in the PIC
®
Mid-Range Reference Manual
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this Data
Sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
The PIC12F629 and PIC12F675 devices are covered
by this Data Sheet. They are identical, except the
PIC12F675 has a 10-bit A/D converter. They come in
8-pin PDIP, SOIC, MLF-S and DFN packages.
Figure 1-1 shows a block diagram of the PIC12F629/
675 devices. Table 1-1 shows the pinout description.
FIGURE 1-1: PIC12F629/675 BLOCK DIAGRAM
Flash
Program
Memory
1K x 14
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
64 x 8
Direct Addr
7
Addr
(1)
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT VDD, VSS
8
8
Brown-out
Detect
8
3
Timing
Generation
GP5/T1CKI/OSC1/CLKIN
Internal
4 MHz
RAM
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT
GP1/AN1/CIN-/VREF
GP0/AN0/CIN+
Oscillator
Note 1: Higher order bits are from STATUS register.
Analog
Timer0 Timer1
DATA
EEPROM
128 bytes
EEDATA
EEADDR
Comparator
Analog to Digital Converter
(PIC12F675 only)
AN0 AN1 AN2 AN3
CIN- CIN+ COUT
T0CKI
T1CKI
VREF
and reference
T1G
8
PIC12F629/675
DS41190G-page 8 © 2010 Microchip Technology Inc.
TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION
Name Function
Input
Type
Output
Type
Description
GP0/AN0/CIN+/ICSPDAT GP0 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN0 AN A/D Channel 0 input
CIN+ AN Comparator input
ICSPDAT TTL CMOS Serial programming I/O
GP1/AN1/CIN-/VREF/
ICSPCLK
GP1 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN1 AN A/D Channel 1 input
CIN- AN Comparator input
VREF AN External voltage reference
ICSPCLK ST Serial programming clock
GP2/AN2/T0CKI/INT/COUT GP2 ST CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN2 AN A/D Channel 2 input
T0CKI ST TMR0 clock input
INT ST External interrupt
COUT CMOS Comparator output
GP3/MCLR/VPP GP3 TTL Input port w/ interrupt-on-change
MCLR ST Master Clear
VPP HV Programming voltage
GP4/AN3/T1G/OSC2/
CLKOUT
GP4 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN3 AN A/D Channel 3 input
T1G ST TMR1 gate
OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
T1CKI ST TMR1 clock
OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/RC oscillator connection
VSS VSS Power Ground reference
VDD VDD Power Positive supply
Legend: Shade = PIC12F675 only
TTL = TTL input buffer, ST = Schmitt Trigger input buffer
© 2010 Microchip Technology Inc. DS41190G-page 9
PIC12F629/675
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F629/675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC12F629/675 devices is physically imple-
mented. Accessing a location above these boundaries
will cause a wrap-around within the first 1K x 14 space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
DSTEMP/675
2.2 Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers and the Special Function Registers. The
Special Function Registers are located in the first 32
locations of each bank. Register locations 20h-5Fh are
General Purpose Registers, implemented as static
RAM and are mapped across both banks. All other
RAM is unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
• RP0 = 0 Bank 0 is selected
• RP0 = 1 Bank 1 is selected
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F629/675 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
PC<12:0>
13
000h
0004
0005
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Note: The IRP and RP1 bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
PIC12F629/675
DS41190G-page 10 © 2010 Microchip Technology Inc.
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
FIGURE 2-2: DATA MEMORY MAP OF
THE PIC12F629/675
Indirect addr.
(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented data memory locations, read as ‘0’.
1: Not a physical register.
2: PIC12F675 only.
CMCON VRCON
General
Purpose
Registers
accesses
20h-5Fh
64 Bytes
EEDATA
EEADR
EECON2
(1)
5Fh
60h
File
Address
File
Address
WPU
IOC
Indirect addr.
(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
DFh
E0h
ADRESH
(2)
ADCON0
(2)
EECON1
ADRESL
(2)
ANSEL
(2)
© 2010 Microchip Technology Inc. DS41190G-page 11
PIC12F629/675
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Page
Bank 0
00h INDF
(1)
Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61
01h TMR0 Timer0 Module’s Register xxxx xxxx 29
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19
03h STATUS
IRP
(2)
RP1
(2)
RP0 TO PD Z DC C
0001 1xxx 14
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 20
05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 21
06h — Unimplemented — —
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 19
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 17
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 32
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 32
10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 35
11h — Unimplemented — —
12h — Unimplemented — —
13h — Unimplemented — —
14h — Unimplemented — —
15h — Unimplemented — —
16h — Unimplemented — —
17h — Unimplemented — —
18h — Unimplemented — —
19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 38
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH
(3)
Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 44
1Fh ADCON0
(3)
ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 45,61
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
PIC12F629/675
DS41190G-page 12 © 2010 Microchip Technology Inc.
Bank 1
80h INDF
(1)
Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14,31
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19
83h STATUS
IRP
(2)
RP1
(2) RP0 TO PD Z DC C 0001 1xxx 14
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 20
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 21
86h — Unimplemented — —
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 19
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 16
8Dh — Unimplemented — —
8Eh PCON — — — — — — POR BOD ---- --0x 18
8Fh — Unimplemented — —
90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 18
91h — Unimplemented — —
92h — Unimplemented — —
93h — Unimplemented — —
94h — Unimplemented — —
95h WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 21
96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 23
97h — Unimplemented — —
98h — Unimplemented — —
99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 42
9Ah EEDATA Data EEPROM Data Register 0000 0000 49
9Bh EEADR — Data EEPROM Address Register -000 0000 49
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 50
9Dh EECON2
(1)
EEPROM Control Register 2 ---- ---- 50
9Eh ADRESL
(3)
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 44
9Fh ANSEL
(3)
— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 46,61
Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Page
© 2010 Microchip Technology Inc. DS41190G-page 13
PIC12F629/675
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits, see the “Instruction Set Summary”.
REGISTER 2-1: STATUS: STATUS REGISTER (ADDRESS: 03h OR 83h)
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12F629/675 and should
be maintained as clear. Use of these bits
is not recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: This bit is reserved and should be maintained as ‘0’
bit 6 RP1: This bit is reserved and should be maintained as ‘0’
bit 5 RP0: Register Bank Select bit (used for direct addressing)
0 = Bank 0 (00h - 7Fh)
1 = Bank 1 (80h - FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT Time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
PIC12F629/675
DS41190G-page 14 © 2010 Microchip Technology Inc.
2.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
• TMR0/WDT prescaler
• External GP2/INT interrupt
• TMR0
• Weak pull-ups on GPIO
REGISTER 2-2: OPTION_REG: OPTION REGISTER (ADDRESS: 81h)
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION<3>). See
Section 4.4 “Prescaler”.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
© 2010 Microchip Technology Inc. DS41190G-page 15
PIC12F629/675
2.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GIE PEIE T0IE INTE GPIE T0IF INTF GPIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3 GPIE: Port Change Interrupt Enable bit
(1)
1 = Enables the GPIO port change interrupt
0 = Disables the GPIO port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0 GPIF: Port Change Interrupt Flag bit
1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0 = None of the GP5:GP0 pins have changed state
Note 1: IOC register must also be enabled to enable an interrupt-on-change.
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
PIC12F629/675
DS41190G-page 16 © 2010 Microchip Technology Inc.
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIE ADIE — — CMIE — — TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only)
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4 Unimplemented: Read as ‘0’
bit 3 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
© 2010 Microchip Technology Inc. DS41190G-page 17
PIC12F629/675
2.2.2.5 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
EEIF ADIF — — CMIF — — TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4 Unimplemented: Read as ‘0’
bit 3 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 2-1 Unimplemented: Read as ‘0’
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIC12F629/675
DS41190G-page 18 © 2010 Microchip Technology Inc.
2.2.2.6 PCON Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Detect (BOD)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6: PCON: POWER CONTROL REGISTER (ADDRESS: 8Eh)
2.2.2.7 OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to
calibrate the internal 4 MHz oscillator. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7: OSCCAL: OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x
— — — — — — POR BOD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOD: Brown-out Detect Status bit
1 = No Brown-out Detect occurred
0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111 = Maximum frequency
100000 = Center frequency
000000 = Minimum frequency
bit 1-0 Unimplemented: Read as ‘0’
© 2010 Microchip Technology Inc. DS41190G-page 19
PIC12F629/675
2.3 PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0> ÷ PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3> ÷
PCH).
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the PC (ADDWF PCL). When performing a table read
using a computed GOTO method, care should be
exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the
Application Note, “Implementing a Table Read”
(AN556).
2.3.2 STACK
The PIC12F629/675 family has an 8-level deep x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the
Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed, or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PC
12 8 7 0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12 11 10 0
11 PCLATH<4:3>
PCH PCL
8 7
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PIC12F629/675
DS41190G-page 20 © 2010 Microchip Technology Inc.
2.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-2.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
FIGURE 2-2: DIRECT/INDIRECT ADDRESSING PIC12F629/675
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
Data
Memory
Indirect Addressing Direct Addressing
Bank Select Location Select
RP1
(1)
RP0 6 0
From Opcode
IRP
(1)
FSR Register
7 0
Bank Select Location Select
00 01 10 11
180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Not Used
© 2010 Microchip Technology Inc. DS41190G-page 21
PIC12F629/675
3.0 GPIO PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
3.1 GPIO and the TRISIO Registers
GPIO is an 6-bit wide, bidirectional port. The
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISIO
bit (= 0) will make the corresponding GPIO pin an
output (i.e., put the contents of the output latch on the
selected pin). The exception is GP3, which is input-only
and its TRISIO bit will always read as ‘1’. Example 3-1
shows how to initialize GPIO.
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the
PORT data latch. GP3 reads ‘0’ when MCLREN = 1.
The TRISIO register controls the direction of the
GP pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
EXAMPLE 3-1: INITIALIZING GPIO
3.2 Additional Pin Functions
Every GPIO pin on the PIC12F629/675 has an
interrupt-on-change option and every GPIO pin, except
GP3, has a weak pull-up option. The next two sections
describe these functions.
3.2.1 WEAK PULL-UP
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 3-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>).
REGISTER 3-1: GPIO: GPIO REGISTER (ADDRESS: 05h)
Note: Additional information on I/O ports may be
found in the PIC
®
Mid-Range Reference
Manual, (DS33023).
Note: The ANSEL (9Fh) and CMCON (19h)
registers (9Fh) must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’. The ANSEL register is defined for
the PIC12F675.
BCF STATUS,RP0 ;Bank 0
CLRF GPIO ;Init GPIO
MOVLW 07h ;Set GP<2:0> to
MOVWF CMCON ;digital IO
BSF STATUS,RP0 ;Bank 1
CLRF ANSEL ;Digital I/O
MOVLW 0Ch ;Set GP<3:2> as inputs
MOVWF TRISIO ;and set GP<5:4,1:0>
;as outputs
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— —
GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 GPIO<5:0>: General Purpose I/O pin
1 = Port pin is >VIH
0 = Port pin is <VIL
PIC12F629/675
DS41190G-page 22 © 2010 Microchip Technology Inc.
REGISTER 3-2: TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h)
REGISTER 3-3: WPU: WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
— —
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
Note: TRISIO<3> always reads ‘1’.
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — WPU5 WPU4 — WPU2 WPU1 WPU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
© 2010 Microchip Technology Inc. DS41190G-page 23
PIC12F629/675
3.2.2 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of GPIO. This will end the
mismatch condition.
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
REGISTER 3-4: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOC<5:0>: Interrupt-on-Change GPIO Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
PIC12F629/675
DS41190G-page 24 © 2010 Microchip Technology Inc.
3.3 Pin Descriptions and Diagrams
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this Data Sheet.
3.3.1 GP0/AN0/CIN+
Figure 3-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• an analog input to the comparator
3.3.2 GP1/AN1/CIN-/VREF
Figure 3-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
• as a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• an analog input to the comparator
• a voltage reference input for the A/D (PIC12F675
only)
FIGURE 3-1: BLOCK DIAGRAM OF GP0
AND GP1 PINS
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPU
RD
WPU
RD PORT
RD
PORT
WR
PORT
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-Change
To Comparator
To A/D Converter
Analog
Input Mode
GPPU
Analog
Input Mode
© 2010 Microchip Technology Inc. DS41190G-page 25
PIC12F629/675
3.3.3 GP2/AN2/T0CKI/INT/COUT
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from the comparator
FIGURE 3-2: BLOCK DIAGRAM OF GP2
3.3.4 GP3/MCLR/VPP
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset
FIGURE 3-3: BLOCK DIAGRAM OF GP3
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-Change
To A/D Converter
0
1 COUT
COUT
Enable
To INT
To TMR0
Analog
Input Mode
GPPU
RD PORT
Analog
Input
Mode
I/O pin
VSS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORT
RD
PORT
WR
IOC
RD
IOC
Interrupt-on-Change
Reset
MCLRE
RD
TRISIO
VSS
D
EN
Q
MCLRE
PIC12F629/675
DS41190G-page 26 © 2010 Microchip Technology Inc.
3.3.5 GP4/AN3/T1G/OSC2/CLKOUT
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-4: BLOCK DIAGRAM OF GP4
3.3.6 GP5/T1CKI/OSC1/CLKIN
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 3-5: BLOCK DIAGRAM OF GP5
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-Change
FOSC/4
To A/D Converter
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog
Input Mode
GPPU
RD PORT
To TMR1 T1G
INTOSC/
RC/EC
(2)
CLK
Modes
(1)
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPU
RD
WPU
RD
PORT
WR
PORT
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-Change
To TMR1 or CLKGEN
INTOSC
Mode
RD PORT
INTOSC
Mode
GPPU
Oscillator
Circuit
OSC2
Note 1: Timer1 LP Oscillator enabled
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
(2)
TMR1LPEN
(1)
© 2010 Microchip Technology Inc. DS41190G-page 27
PIC12F629/675
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOD
Value on all
other
Resets
05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
95h WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111
96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000
9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.
PIC12F629/675
DS41190G-page 28 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 29
PIC12F629/675
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
4.1 Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
by the source edge (T0SE) control bit
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
4.2 Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut-
off during Sleep.
FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note: Additional information on the Timer0
module is available in the PIC
®
Mid-Range
Reference Manual, (DS33023).
Note: Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the PIC
®
Mid-Range Reference Manual,
(DS33023).
T0CKI
T0SE
pin
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-out
PS0 - PS2
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
PSA
PSA
PIC12F629/675
DS41190G-page 30 © 2010 Microchip Technology Inc.
4.3 Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
REGISTER 4-1: OPTION_REG: OPTION REGISTER (ADDRESS: 81h)
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CK pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
© 2010 Microchip Technology Inc. DS41190G-page 31
PIC12F629/675
4.4 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
4.4.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 4-
1) must be executed when changing the prescaler
assignment from Timer0 to WDT.
EXAMPLE 4-1: CHANGING PRESCALER
(TIMER0÷WDT)
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 4-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 4-2: CHANGING PRESCALER
(WDT÷TIMER0)
TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0
BCF STATUS,RP0 ;Bank 0
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
; prescaler
BSF STATUS,RP0 ;Bank 1
MOVLW b’00101111’ ;Required if desired
MOVWF OPTION_REG ; PS2:PS0 is
CLRWDT ; 000 or 001
;
MOVLW b’00101xxx’ ;Set postscaler to
MOVWF OPTION_REG ; desired WDT rate
BCF STATUS,RP0 ;Bank 0
CLRWDT ;Clear WDT and
; postscaler
BSF STATUS,RP0 ;Bank 1
MOVLW b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
MOVWF OPTION_REG ;
BCF STATUS,RP0 ;Bank 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on
all other
Resets
01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Shaded cells are not used by the Timer0 module.
PIC12F629/675
DS41190G-page 32 © 2010 Microchip Technology Inc.
5.0 TIMER1 MODULE WITH GATE
CONTROL
The PIC12F629/675 devices have a 16-bit timer.
Figure 5-1 shows the basic block diagram of the Timer1
module. Timer1 has the following features:
• 16-bit timer/counter (TMR1H:TMR1L)
• Readable and writable
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt on overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input (T1G)
• Optional LP oscillator
The Timer1 Control register (T1CON), shown in
Register 5.1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
FIGURE 5-1: TIMER1 BLOCK DIAGRAM
Note: Additional information on timer modules is
available in the PIC
®
Mid-Range Refer-
ence Manual, (DS33023).
TMR1H TMR1L
LP Oscillator
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
0
1
Synchronized
Clock Input
2
OSC1
OSC2
Set Flag bit
TMR1IF on
Overflow
TMR1
TMR1ON
TMR1GE
TMR1ON
TMR1GE
INTOSC
T1OSCEN
LP
w/o CLKOUT
T1G
© 2010 Microchip Technology Inc. DS41190G-page 33
PIC12F629/675
5.1 Timer1 Modes of Operation
Timer1 can operate in one of three modes:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is
incremented on the rising edge of the external clock
input T1CKI. In addition, the Counter mode clock can
be synchronized to the microcontroller system clock
or run asynchronously.
In counter and timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
5.2 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• Timer1 interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
5.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
FIGURE 5-2: TIMER1 INCREMENTING EDGE
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
Note: The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
PIC12F629/675
DS41190G-page 34 © 2010 Microchip Technology Inc.
REGISTER 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if T1G pin is low
0 = Timer1 is on
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1OSO/T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
© 2010 Microchip Technology Inc. DS41190G-page 35
PIC12F629/675
5.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer
(Section 5.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
5.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PIC
®
Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in
Asynchronous mode.
5.5 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator rated up to 37 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. Table 9-2 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the system clock is derived from the internal oscillator.
As with the system LP oscillator, the user must provide
a software time delay to ensure proper oscillator
start-up.
While enabled, TRISIO4 and TRISIO5 are set. GP4
and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read
‘1’.
5.6 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine on an overflow.
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
Note: The oscillator requires a start-up and stabi-
lization time before use. Thus, T1OSCEN
should be set and a suitable delay
observed prior to enabling Timer1.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
PIC12F629/675
DS41190G-page 36 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 37
PIC12F629/675
6.0 COMPARATOR MODULE
The PIC12F629/675 devices have one analog
comparator. The inputs to the comparator are
multiplexed with the GP0 and GP1 pins. There is an
on-chip Comparator Voltage Reference that can also
be applied to an input of the comparator. In addition,
GP2 can be configured as the comparator output.
The Comparator Control Register (CMCON), shown
in Register 6-1, contains the bits to control the
comparator.
REGISTER 6-1: CMCON: COMPARATOR CONTROL REGISTER (ADDRESS: 19h)
U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— COUT — CINV CIS CM2 CM1 CM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 COUT: Comparator Output bit
When CINV = 0:
1 = VIN+ > VIN-
0 = VIN+ < VIN-
When CINV = 1:
1 = VIN+ < VIN-
0 = VIN+ > VIN-
bit 5 Unimplemented: Read as ‘0’
bit 4 CINV: Comparator Output Inversion bit
1 = Output inverted
0 = Output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM2:CM0 = 110 or 101:
1 = VIN- connects to CIN+
0 = VIN- connects to CIN-
bit 2-0 CM2:CM0: Comparator Mode bits
Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings
PIC12F629/675
DS41190G-page 38 © 2010 Microchip Technology Inc.
6.1 Comparator Operation
A single comparator is shown in Figure 6-1, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 6-1 represent
the uncertainty due to input offsets and response time.
The polarity of the comparator output can be inverted
by setting the CINV bit (CMCON<4>). Clearing CINV
results in a non-inverted output. A complete table
showing the output state versus input conditions and
the polarity bit is shown in Table 6-1.
TABLE 6-1: OUTPUT STATE VS. INPUT
CONDITIONS
FIGURE 6-1: SINGLE COMPARATOR
Note: To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be
programmed in the CMCON (19h) register.
Input Conditions CINV COUT
VIN- > VIN+ 0 0
VIN- < VIN+ 0 1
VIN- > VIN+ 1 1
VIN- < VIN+ 1 0
Output
VIN-
VIN+
Output
+

VIN+
VIN-
Note: CINV bit (CMCON<4>) is clear.
© 2010 Microchip Technology Inc. DS41190G-page 39
PIC12F629/675
6.2 Comparator Configuration
There are eight modes of operation for the comparator.
The CMCON register, shown in Register 6-1, is used to
select the mode. Figure 6-2 shows the eight possible
modes. The TRISIO register controls the data direction
of the comparator pins for each mode. If the
Comparator mode is changed, the comparator output
level may not be valid for a specified period of time.
Refer to the specifications in Section 12.0 “Electri-
cal Specifications”.
FIGURE 6-2: COMPARATOR I/O OPERATING MODES
Note: Comparator interrupts should be disabled
during a Comparator mode change. Other-
wise, a false interrupt may occur.
Comparator Reset (POR Default Value - low power) Comparator Off (Lowest power)
CM2:CM0 = 000 CM2:CM0 = 111
Comparator without Output Comparator w/o Output and with Internal Reference
CM2:CM0 = 010 CM2:CM0 = 100
Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output
CM2:CM0 = 011 CM2:CM0 = 101
Comparator with Output Multiplexed Input with Internal Reference
CM2:CM0 = 001 CM2:CM0 = 110
A = Analog Input, ports always reads ‘0’
D = Digital Input
CIS = Comparator Input Switch (CMCON<3>)
GP1/CIN-
GP0/CIN+
Off (Read as ‘0’)
A
A
GP2/COUT D
GP1/CIN-
GP0/CIN+
Off (Read as ‘0’)
D
D
GP2/COUT D
GP1/CIN-
GP0/CIN+
COUT
A
A
GP2/COUT D
GP1/CIN-
GP0/CIN+
COUT
A
D
GP2/COUT D
From CVREF Module
GP1/CIN-
GP0/CIN+
COUT
A
D
GP2/COUT D
From CVREF Module
GP1/CIN-
GP0/CIN+
COUT
A
A
GP2/COUT D
From CVREF Module
CIS = 0
CIS = 1
GP1/CIN-
GP0/CIN+
COUT
A
A
GP2/COUT D
GP1/CIN-
GP0/CIN+
COUT
A
A
GP2/COUT D
From CVREF Module
CIS = 0
CIS = 1
PIC12F629/675
DS41190G-page 40 © 2010 Microchip Technology Inc.
6.3 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 6-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kO is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 6-3: ANALOG INPUT MODE
6.4 Comparator Output
The comparator output, COUT, is read through the
CMCON register. This bit is read-only. The comparator
output may also be directly output to the GP2 pin in
three of the eight possible modes, as shown in
Figure 6-2. When in one of these modes, the output on
GP2 is asynchronous to the internal clock. Figure 6-4
shows the comparator output block diagram.
The TRISIO<2> bit functions as an output enable/
disable for the GP2 pin while the comparator is in an
Output mode.
FIGURE 6-4: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
VA
Rs < 10K
AIN
CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
Leakage
±500 nA
Vss
Legend: CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to Various Junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
Note 1: When reading the GPIO register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
TTL input specification.
2: Analog levels on any pin that is defined as
a digital input, may cause the input buffer
to consume more current than is
specified.
To GP2/T0CKI pin
RD CMCON
Set CMIF bit
Reset
To Data Bus
CINV
CVREF
D
EN
Q
D
EN
Q
RD CMCON
GP1/CIN-
GP0/CIN+
CM2:CM0
© 2010 Microchip Technology Inc. DS41190G-page 41
PIC12F629/675
6.5 Comparator Reference
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The internal reference signal is
used for four of the eight Comparator modes. The
VRCON register, Register 6-2, controls the voltage
reference module shown in Figure 6-5.
6.5.1 CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
The following equations determine the output voltages:
6.5.2 VOLTAGE REFERENCE
ACCURACY/ERROR
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 6-5) keep CVREF from approaching VSS or
VDD. The Voltage Reference is VDD derived and there-
fore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 12.0
“Electrical Specifications”.
FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
6.6 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-7).
6.7 Operation During Sleep
Both the comparator and voltage reference, if enabled
before entering Sleep mode, remain active during
Sleep. This results in higher Sleep currents than shown
in the power-down specifications. The additional cur-
rent consumed by the comparator and the voltage ref-
erence is shown separately in the specifications. To
minimize power consumption while in Sleep mode, turn
off the comparator, CM2:CM0 = 111, and voltage refer-
ence, VRCON<7> = 0.
While the comparator is enabled during Sleep, an inter-
rupt will wake-up the device. If the device wakes up
from Sleep, the contents of the CMCON and VRCON
registers are not affected.
6.8 Effects of a Reset
A device Reset forces the CMCON and VRCON
registers to their Reset states. This forces the
comparator module to be in the Comparator Reset
mode, CM2:CM0 = 000 and the voltage reference to its
off state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD
VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x
VDD / 32)
VRR 8R
VR3:VR0
16-1 Analog
8R R R R R
CVREF to
16 Stages
Comparator
Input
VREN
VDD
MUX
PIC12F629/675
DS41190G-page 42 © 2010 Microchip Technology Inc.
REGISTER 6-2: VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
6.9 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CMIE bit (PIE1<3>) and the PEIE bit (INT-
CON<6>) must be set to enable the interrupt. In addi-
tion, the GIE bit must also be set. If any of these bits are
cleared, the interrupt is not enabled, though the CMIF
bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN — VRR — VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VREN: CVREF Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain
bit 6 Unimplemented: Read as ‘0’
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as ‘0’
bit 3-0 VR3:VR0: CVREF value selection 0 s VR [3:0] s 15
When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD
Note: If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on
all other
Resets
0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
© 2010 Microchip Technology Inc. DS41190G-page 43
PIC12F629/675
7.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
The Analog-to-Digital converter (A/D) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. The PIC12F675 has four
analog inputs, multiplexed into one sample and hold
circuit. The output of the sample and hold is connected
to the input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
VDD or a voltage applied by the VREF pin. Figure 7-1
shows the block diagram of the A/D on the PIC12F675.
FIGURE 7-1: A/D BLOCK DIAGRAM
7.1 A/D Configuration and Operation
There are two registers available to control the
functionality of the A/D module:
1. ADCON0 (Register 7-1)
2. ANSEL (Register 7-2)
7.1.1 ANALOG PORT PINS
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high-impedance state. Likewise, set the
corresponding ANS bit to disable the digital input
buffer.
7.1.2 CHANNEL SELECTION
There are four analog channels on the PIC12F675,
AN0 through AN3. The CHS1:CHS0 bits
(ADCON0<3:2>) control which channel is connected to
the sample and hold circuit.
7.1.3 VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either VDD is used, or an analog voltage
applied to VREF is used. The VCFG bit (ADCON0<6>)
controls the voltage reference selection. If VCFG is set,
then the voltage on the VREF pin is the reference;
otherwise, VDD is the reference.
7.1.4 CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
• FRC (dedicated internal RC oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 us. Table 7-1 shows a few TAD calculations for
selected frequencies.
GP0/AN0
ADC
GP1/AN1/VREF
GP2/AN2
GP4/AN3
VDD
VREF
ADON
GO/DONE
VCFG = 1
VCFG = 0
CHS1:CHS0
ADRESH ADRESL
10
10
ADFM
VSS
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
PIC12F629/675
DS41190G-page 44 © 2010 Microchip Technology Inc.
TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES
7.1.5 STARTING A CONVERSION
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D conversion sample. Instead, the
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
7.1.6 CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 7-2 shows the output formats.
FIGURE 7-2: 10-BIT A/D RESULT FORMAT
A/D Clock Source (TAD) Device Frequency
Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 000 100 ns
(2)
400 ns
(2)
500 ns
(2)
1.6 us
4 TOSC 100 200 ns
(2)
800 ns
(2)
1.0 us
(2)
3.2 us
8 TOSC 001 400 ns
(2)
1.6 us 2.0 us 6.4 us
16 TOSC 101 800 ns
(2)
3.2 us 4.0 us 12.8 us
(3)
32 TOSC 010 1.6 us 6.4 us 8.0 us
(3)
25.6 us
(3)
64 TOSC 110 3.2 us 12.8 us
(3)
16.0 us
(3)
51.2 us
(3)
A/D RC x11 2 - 6 us
(1,4)
2 - 6 us
(1,4)
2 - 6 us
(1,4)
2 - 6 us
(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 us for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
Note: The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
ADRESH ADRESL
(ADFM = 0) MSB LSB
Bit 7 Bit 0 Bit 7 Bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB
Bit 7 Bit 0 Bit 7 Bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
© 2010 Microchip Technology Inc. DS41190G-page 45
PIC12F629/675
REGISTER 7-1: ADCON0: A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG — — CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Result Formed Select bit
1 = Right justified
0 = Left justified
bit 6 VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5-4 Unimplemented: Read as ‘0’
bit 3-2 CHS1:CHS0: Analog Channel Select bits
00 = Channel 00 (AN0)
01 = Channel 01 (AN1)
10 = Channel 02 (AN2)
11 = Channel 03 (AN3)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: A/D Conversion Status bit
1 = A/D converter module is operating
0 = A/D converter is shut-off and consumes no operating current
PIC12F629/675
DS41190G-page 46 © 2010 Microchip Technology Inc.
REGISTER 7-2: ANSEL: ANALOG SELECT REGISTER (ADDRESS: 9Fh)
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
— ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = Fosc/2
001 = Fosc/8
010 = Fosc/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = Fosc/4
101 = Fosc/16
110 = Fosc/64
bit 3-0 ANS3:ANS0: Analog Select bits
(Between analog or digital function on pins AN<3:0>, respectively.)
1 = Analog input; pin is assigned as analog input
(1)
0 = Digital I/O; pin is assigned to port or special function
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter-
rupt-on-change. The corresponding TRISIO bit must be set to Input mode in order to allow external control
of the voltage on the pin.
© 2010 Microchip Technology Inc. DS41190G-page 47
PIC12F629/675
7.2 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 7-3. The maximum recommended imped-
ance for analog sources is 10 kO. As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time,
Equation 7-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D).
The 1/2 LSb error is the maximum error allowed for
the A/D to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC
®
Mid-Range Reference Manual (DS33023).
EQUATION 7-1: ACQUISITION TIME

FIGURE 7-3: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
2us + TC + [(Temperature -25°C)(0.05us/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kO + 7kO + 10kO) In(0.0004885)
16.47us
2us + 16.47us + [(50°C -25°C)(0.05us/°C)
19.72us
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kO. This is required to meet the pin
leakage specification.
CPIN
VA
RS
ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V
I LEAKAGE
RIC s 1K
Sampling
Switch
SS
RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
5 6 7 8 9 1011
(kO)
VDD
= 120 pF
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
PIC12F629/675
DS41190G-page 48 © 2010 Microchip Technology Inc.
7.3 A/D Operation During Sleep
The A/D converter module can operate during Sleep.
This requires the A/D clock source to be set to the
internal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from Sleep. If
the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4 Effects of Reset
A device Reset forces all registers to their Reset state.
Thus the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TABLE 7-2: SUMMARY OF A/D REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOD
Value on
all other
Resets
05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx --uu uuuu
0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO ADON 00-- 0000 00-- 0000
85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for A/D converter module.
© 2010 Microchip Technology Inc. DS41190G-page 49
PIC12F629/675
8.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
• EECON1
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC12F629/675 devices have 128
bytes of data EEPROM with an address range from 0h
to 7Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC Specifications for
exact limits.
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
this memory.
Additional information on the data EEPROM is
available in the PIC
®
Mid-Range Reference Manual,
(DS33023).
REGISTER 8-1: EEDAT: EEPROM DATA REGISTER (ADDRESS: 9Ah)
REGISTER 8-2: EEADR: EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEDATn: Byte value to write to or read from data EEPROM
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Should be set to ‘0’
bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
PIC12F629/675
DS41190G-page 50 © 2010 Microchip Technology Inc.
8.1 EEADR
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR<6:0>) are required. The
MSb (bit 7) is ignored.
The upper bit should always be ‘0’ to remain upward
compatible with devices that have more data EEPROM
memory.
8.2 EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
implemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it, and rewrite the
location. The data and address will be cleared,
therefore, the EEDATA and EEADR registers will need
to be re-initialized.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
REGISTER 8-3: EECON1: EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
— — — — WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal
operation or BOD detect)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set, not cleared, in software).
0 = Does not initiate an EEPROM read
© 2010 Microchip Technology Inc. DS41190G-page 51
PIC12F629/675
8.3 Reading the EEPROM Data
Memory
To read a data memory location, the user must write
the address to the EEADR register and then set
control bit RD (EECON1<0>), as shown in
Example 8-1. The data is available, in the very next
cycle, in the EEDATA register. Therefore, it can be
read in the next instruction. EEDATA holds this value
until another read, or until it is written to by the user
(during a write operation).
EXAMPLE 8-1: DATA EEPROM READ
8.4 Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
EXAMPLE 8-2: DATA EEPROM WRITE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-3: WRITE VERIFY
8.5.1 USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specifications D120 or
D120A. If this is not the case, an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
8.6 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
BSF STATUS,RP0 ;Bank 1
MOVLW CONFIG_ADDR ;
MOVWF EEADR ;Address to read
BSF EECON1,RD ;EE Read
MOVF EEDATA,W ;Move data to W
BSF STATUS,RP0 ;Bank 1
BSF EECON1,WREN ;Enable write
BCF INTCON,GIE ;Disable INTs
MOVLW 55h ;Unlock write
MOVWF EECON2 ;
MOVLW AAh ;
MOVWF EECON2 ;
BSF EECON1,WR ;Start the write
BSF INTCON,GIE ;Enable INTS
R
e
q
u
i
r
e
d
S
e
q
u
e
n
c
e
BCF STATUS,RP0 ;Bank 0
: ;Any code
BSF STATUS,RP0 ;Bank 1 READ
MOVF EEDATA,W ;EEDATA not changed
;from previous write
BSF EECON1,RD ;YES, Read the
;value written
XORWF EEDATA,W
BTFSS STATUS,Z ;Is data the same
GOTO WRITE_ERR ;No, handle error
: ;Yes, continue
PIC12F629/675
DS41190G-page 52 © 2010 Microchip Technology Inc.
8.7 Data EEPROM Operation During
Code Protect
Data memory can be code protected by programming
the CPD bit to ‘0’.
When the data memory is code protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code protect the program memory
when code protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which outputs the contents of data memory.
Programming unused locations to ‘0’ will also help
prevent data memory code protection from becoming
breached.
TABLE 8-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on all
other
Resets
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
9Ah EEDATA EEPROM Data Register 0000 0000 0000 0000
9Bh EEADR — EEPROM Address Register -000 0000 -000 0000
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000
9Dh EECON2
(1)
EEPROM Control Register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
Note 1: EECON2 is not a physical register.
© 2010 Microchip Technology Inc. DS41190G-page 53
PIC12F629/675
9.0 SPECIAL FEATURES OF THE
CPU
Certain special circuits that deal with the needs of real
time applications are what sets a microcontroller apart
from other processors. The PIC12F629/675 family has
a host of such features intended to:
• maximize system reliability
• minimize cost through elimination of external
components
• provide power saving operating modes and offer
code protection
These features are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Detect (BOD)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
The PIC12F629/675 has a Watchdog Timer that is
controlled by Configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can provide at least
a 72 ms Reset. With these three functions on-chip,
most applications need no external Reset circuitry.
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 9.2).
PIC12F629/675
DS41190G-page 54 © 2010 Microchip Technology Inc.
9.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations, as shown in Register 9.2. These
bits are mapped in program memory location 2007h.
REGISTER 9-1: CONFIG: CONFIGURATION WORD (ADDRESS: 2007h)
Note: Address 2007h is beyond the user program
memory space. It belongs to the special con-
figuration memory space (2000h-3FFFh),
which can be accessed only during program-
ming. See PIC12F629/675 Programming
Specification for more information.
R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
BG1 BG0 — — — CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0
bit 13 bit 0
Legend:
P = Programmed using ICSP™
R = Readable bit Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
bit 13-12 BG1:BG0: Bandgap Calibration bits for BOD and POR voltage
(1)
00 = Lowest bandgap voltage
11 = Highest bandgap voltage
bit 11-9 Unimplemented: Read as ‘0’
bit 8 CPD: Data Code Protection bit
(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 7 CP: Code Protection bit
(3)
1 = Program Memory code protection is disabled
0 = Program Memory code protection is enabled
bit 6 BODEN: Brown-out Detect Enable bit
(4)
1 = BOD enabled
0 = BOD disabled
bit 5 MCLRE: GP3/MCLR Pin Function Select bit
(5)
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as spec-
ified in the PIC12F629/675 Programming Specification. These bits are reflected in an export of the Configuration Word.
Microchip Development Tools maintain all Calibration bits to factory settings.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased, including OSCCAL value, when the code protection is turned off.
4: Enabling Brown-out Detect does not automatically enable Power-up Timer.
5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
© 2010 Microchip Technology Inc. DS41190G-page 55
PIC12F629/675
9.2 Oscillator Configurations
9.2.1 OSCILLATOR TYPES
The PIC12F629/675 can be operated in eight different
oscillator option modes. The user can program three
Configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
• LP Low-Power Crystal
• XT Crystal/Resonator
• HS High-Speed Crystal/Resonator
• RC External Resistor/Capacitor (2 modes)
• INTOSC Internal Oscillator (2 modes)
• EC External Clock In
9.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (see Figure 9-1). The PIC12F629/675
oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may yield a
frequency outside of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source to drive the
OSC1 pin (see Figure 9-2).
FIGURE 9-1: CRYSTAL OPERATION (OR
CERAMIC RESONATOR)
HS, XT OR LP OSC
CONFIGURATION
FIGURE 9-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT, EC,
OR LP OSC
CONFIGURATION)
TABLE 9-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 9-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Note: Additional information on oscillator config-
urations is available in the PIC
®
Mid-
Range Reference Manual, (DS33023).
Note 1: See Table 9-1 and Table 9-2 for recommended
values of C1 and C2.
2: A series resistor may be required for AT strip cut
crystals.
3: RF varies with the Oscillator mode selected
(Approx. value = 10 MO).
C1
(1)
C2
(1)
XTAL
OSC2
OSC1
RF
(3) Sleep
To Internal
PIC12F629/675
Logic
RS
(2)
Ranges Characterized:
Mode Freq. OSC1(C1) OSC2(C2)
XT 455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS 8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external
components.
Mode Freq. OSC1(C1) OSC2(C2)
LP 32 kHz 68-100 pF 68-100 pF
XT 100 kHz
2 MHz
4 MHz
68-150 pF
15-30 pF
15-30 pF
150-200 pF
15-30 pF
15-30 pF
HS 8 MHz
10 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid
overdriving crystals with low drive level
specification. Since each crystal has its
own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external
components.
Clock from
External System
PIC12F629/675
OSC1
OSC2
(1)
Open
Note 1: Functions as GP4 in EC Osc mode.
PIC12F629/675
DS41190G-page 56 © 2010 Microchip Technology Inc.
9.2.3 EXTERNAL CLOCK IN
For applications where a clock is already available
elsewhere, users may directly drive the PIC12F629/
675 provided that this external clock source meets the
AC/DC timing requirements listed in Section 12.0
“Electrical Specifications”. Figure 9-2 shows how
an external clock circuit should be configured.
9.2.4 RC OSCILLATOR
For applications where precise timing is not a
requirement, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
dependent upon a number of variables. The RC
oscillator frequency is a function of:
• Supply voltage
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature.
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 9-3 shows how the R/C combination is
connected.
Two options are available for this Oscillator mode
which allow GP4 to be used as a general purpose I/O
or to output FOSC/4.
FIGURE 9-3: RC OSCILLATOR MODE
9.2.5 INTERNAL 4 MHZ OSCILLATOR
When calibrated, the internal oscillator provides a fixed
4 MHz (nominal) system clock. See Electrical
Specifications, Section 12.0 “Electrical Specifica-
tions”, for information on variation over voltage and
temperature.
Two options are available for this Oscillator mode
which allow GP4 to be used as a general purpose I/O
or to output FOSC/4.
9.2.5.1 Calibrating the Internal Oscillator
A calibration instruction is programmed into the last
location of program memory. This instruction is a
RETLW XX, where the literal is the calibration value.
The literal is placed in the OSCCAL register to set the
calibration of the internal oscillator. Example 9-1
demonstrates how to calibrate the internal oscillator.
For best operation, decouple (with capacitance) VDD
and VSS as close to the device as possible.
EXAMPLE 9-1: CALIBRATING THE
INTERNAL OSCILLATOR
9.2.6 CLKOUT
The PIC12F629/675 devices can be configured to
provide a clock out signal in the INTOSC and RC
oscillator modes. When configured, the oscillator
frequency divided by four (FOSC/4) is output on the
GP4/OSC2/CLKOUT pin. FOSC/4 can be used for test
purposes or to synchronize other logic.
GP4/OSC2/CLKOUT
CEXT
VDD
REXT
VSS
PIC12F629/675
GP5/OSC1/
FOSC/4
Internal
Clock
CLKIN
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration value
must be saved prior to erasing part as
specified in the PIC12F629/675 Program-
ming specification. Microchip Develop-
ment Tools maintain all Calibration bits to
factory settings.
BSF STATUS, RP0 ;Bank 1
CALL 3FFh ;Get the cal value
MOVWF OSCCAL ;Calibrate
BCF STATUS, RP0 ;Bank 0
© 2010 Microchip Technology Inc. DS41190G-page 57
PIC12F629/675
9.3 Reset
The PIC12F629/675 differentiates between various
kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Detect (BOD)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• WDT Reset
• WDT Reset during Sleep
• Brown-out Detect (BOD) Reset
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations as indicated in Table 9-4. These bits are
used in software to determine the nature of the Reset.
See Table 9-7 for a full description of Reset states of all
registers.
A simplified block diagram of the on-chip Reset Circuit
is shown in Figure 9-4.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 12-4 in Electrical
Specifications Section for pulse-width specification.
FIGURE 9-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R Q
External
Reset
MCLR/
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip
(1)
RC OSC
WDT
Time-out
Power-on Reset
OST
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the INTOSC/EC oscillator.
Brown-out
Detect
BODEN
CLKIN
pin
VPP pin
10-bit Ripple Counter
Q
PIC12F629/675
DS41190G-page 58 © 2010 Microchip Technology Inc.
9.3.1 MCLR
PIC12F629/675 devices have a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 9-5, is suggested.
An internal MCLR option is enabled by setting the
MCLRE bit in the Configuration Word. When enabled,
MCLR is internally tied to VDD. No internal pull-up
option is available for the MCLR pin.
FIGURE 9-5: RECOMMENDED MCLR
CIRCUIT
9.3.2 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details (see
Section 12.0 “Electrical Specifications”). If the BOD
is enabled, the maximum rise time specification does
not apply. The BOD circuitry will keep the device in
Reset until VDD reaches VBOD (see Section 9.3.5
“Brown-Out Detect (BOD)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
9.3.3 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates on an internal
RC oscillator. The chip is kept in Reset as long as
PWRT is active. The PWRT delay allows the VDD to
rise to an acceptable level. A Configuration bit, PWRTE
can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should always be enabled when Brown-out
Detect is enabled.
The Power-up Time delay will vary from chip to chip
and due to:
• VDD variation
• Temperature variation
• Process variation.
See DC parameters for details (Section 12.0 “Electri-
cal Specifications”).
9.3.4 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
Note: The POR circuit does not produce an
internal Reset when VDD declines.
VDD
PIC12F629/675
MCLR
R1
1 kO (or greater)
C1
0.1 uf
(optional, not critical)
© 2010 Microchip Technology Inc. DS41190G-page 59
PIC12F629/675
9.3.5 BROWN-OUT DETECT (BOD)
The PIC12F629/675 members have on-chip Brown-out
Detect circuitry. A Configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below VBOD for
greater than parameter (TBOD) in Table 12-4 (see
Section 12.0 “Electrical Specifications”), the
Brown-out situation will reset the device. This will occur
regardless of VDD slew-rate. A Reset is not guaranteed
to occur if VDD falls below VBOD for less than parameter
(TBOD).
On any Reset (Power-on, Brown-out, Watchdog, etc.),
the chip will remain in Reset until VDD rises above
BVDD (see Figure 9-6). The Power-up Timer will now
be invoked, if enabled, and will keep the chip in Reset
an additional 72 ms.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-up Timer will execute a
72 ms Reset.
FIGURE 9-6: BROWN-OUT SITUATIONS
9.3.6 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-
out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC12F629/675 device
operating in parallel.
Table 9-6 shows the Reset conditions for some special
registers, while Table 9-7 shows the Reset conditions
for all the registers.
9.3.7 POWER CONTROL (PCON) STATUS
REGISTER
The power CONTROL/STATUS register, PCON
(address 8Eh) has two bits.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a brown-out has occurred. The BOD Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration Word).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (i.e., VDD may
have gone too low).
Note: A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
Configuration Word is set.
72 ms
(1)
VBOD
VDD
Internal
Reset
VBOD
VDD
Internal
Reset
72 ms
(1)
<72 ms
72 ms
(1)
VBOD
VDD
Internal
Reset
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.
PIC12F629/675
DS41190G-page 60 © 2010 Microchip Technology Inc.
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Oscillator Configuration
Power-up Brown-out Detect
Wake-up
from Sleep
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1
XT, HS, LP TPWRT +
1024•TOSC
1024•TOSC TPWRT +
1024•TOSC
1024•TOSC 1024•TOSC
RC, EC, INTOSC TPWRT — TPWRT — —
POR BOD TO PD
0 u 1 1 Power-on Reset
1 0 1 1 Brown-out Detect
u u 0 u WDT Reset
u u 0 0 WDT Wake-up
u u u u MCLR Reset during normal operation
u u 1 0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on all
other
Resets
(1)
03h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu
8Eh PCON — — — — — — POR BOD ---- --0x ---- --uq
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
Condition
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during Sleep 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 uuuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Detect 000h 0001 1uuu ---- --10
Interrupt Wake-up from Sleep PC + 1
(1)
uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the
interrupt vector (0004h) after execution of PC + 1.
© 2010 Microchip Technology Inc. DS41190G-page 61
PIC12F629/675
TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS
Register Address
Power-on
Reset
• MCLR Reset during
normal operation
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Detect
(1)
• Wake-up from Sleep
through interrupt
• Wake-up from Sleep
through WDT Time-out
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h — — —
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h 0000 0000 0000 0000 PC + 1
(3)
STATUS 03h/83h 0001 1xxx 000q quuu
(4)
uuuq quuu
(4)
FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu
GPIO 05h --xx xxxx --uu uuuu --uu uuuu
PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh 0000 0000 0000 000u uuuu uuqq
(2)
PIR1 0Ch 00-- 0--0 00-- 0--0 qq-- q--q
(2,5)
T1CON 10h -000 0000 -uuu uuuu -uuu uuuu
CMCON 19h -0-0 0000 -0-0 0000 -u-u uuuu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu
OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu
TRISIO 85h --11 1111 --11 1111 --uu uuuu
PIE1 8Ch 00-- 0--0 00-- 0--0 uu-- u--u
PCON 8Eh ---- --0x ---- --uu
(1,6)
---- --uu
OSCCAL 90h 1000 00-- 1000 00-- uuuu uu--
WPU 95h --11 -111 --11 -111 uuuu uuuu
IOC 96h --00 0000 --00 0000 --uu uuuu
VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu
EEDATA 9Ah 0000 0000 0000 0000 uuuu uuuu
EEADR 9Bh -000 0000 -000 0000 -uuu uuuu
EECON1 9Ch ---- x000 ---- q000 ---- uuuu
EECON2 9Dh ---- ---- ---- ---- ---- ----
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 9-6 for Reset value for specific condition.
5: If wake-up was due to data EEPROM write completing, Bit 7 = 1; A/D conversion completing, Bit 6 = 1;
Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a
wake-up will cause these bits to = u.
6: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
PIC12F629/675
DS41190G-page 62 © 2010 Microchip Technology Inc.
FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
© 2010 Microchip Technology Inc. DS41190G-page 63
PIC12F629/675
9.4 Interrupts
The PIC12F629/675 has 7 sources of interrupt:
• External Interrupt GP2/INT
• TMR0 Overflow Interrupt
• GPIO Change Interrupts
• Comparator Interrupt
• A/D Interrupt (PIC12F675 only)
• TMR1 Overflow Interrupt
• EEPROM Data Write Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR) record individual interrupt
requests in flag bits. The INTCON register also has
individual and Global Interrupt Enable (GIE) bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register and PIE register. GIE is cleared on
Reset.
The return from interrupt instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT pin interrupt
• GP port change interrupt
• TMR0 overflow interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in special register PIE1.
The following interrupt flags are contained in the PIR
register:
• EEPROM data write interrupt
• A/D interrupt
• Comparator interrupt
• Timer1 overflow interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is pushed onto the stack
• The PC is loaded with 0004h
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid GP2/
INT recursive interrupts.
For external interrupt events, such as the INT pin, or
GP port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 9-11). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
PIC12F629/675
DS41190G-page 64 © 2010 Microchip Technology Inc.
FIGURE 9-10: INTERRUPT LOGIC
TMR1IF
TMR1IE
CMIF
CMIE
T0IF
T0IE
INTF
INTE
GPIF
GPIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
EEIE
EEIF
ADIF
ADIE
(1)
Note 1: PIC12F675 only.
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
© 2010 Microchip Technology Inc. DS41190G-page 65
PIC12F629/675
9.4.1 GP2/INT INTERRUPT
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, the INTF bit (INT-
CON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from Sleep if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 9.7 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 9-13 for timing of wake-up from
Sleep through GP2/INT interrupt.
9.4.2 TMR0 INTERRUPT
An overflow (FFh ÷ 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0 “Timer0 Module”.
9.4.3 GPIO INTERRUPT
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
9.4.4 COMPARATOR INTERRUPT
See Section 6.9 “Comparator Interrupts” for
description of comparator interrupt.
9.4.5 A/D CONVERTER INTERRUPT
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 “Analog-to-Digital Converter (A/D)
Module (PIC12F675 only)” for operation of the A/D
converter interrupt.
FIGURE 9-11: INT PIN INTERRUPT TIMING
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC) Inst (PC+1)
Inst (PC - 1)
Inst (0004h)
Dummy Cycle Inst (PC)

1
4
5
1
2
3
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
PIC12F629/675
DS41190G-page 66 © 2010 Microchip Technology Inc.
TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS
9.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
STATUS register). This must be implemented in
software.
Example 9-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 9-2:
• Stores the W register
• Stores the STATUS register in Bank 0
• Executes the ISR code
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 9-2: SAVING THE STATUS AND
W REGISTERS IN RAM
9.6 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a SLEEP instruction). During normal
operation, a WDT Time-out generates a device Reset.
If the device is in Sleep mode, a WDT Time-out causes
the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by
programming the Configuration bit WDTE as clear
(Section 9.1 “Configuration Bits”).
9.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer Time-out.
9.6.2 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst-
case conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT Time-out occurs.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on all
other
Resets
0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u
0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0
8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
MOVWF W_TEMP ;copy W to temp register,
could be in either bank
SWAPF STATUS,W ;swap status to be saved into W
BCF STATUS,RP0 ;change to bank 0 regardless of
current bank
MOVWF STATUS_TEMP ;save status to bank 0 register
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS ;move W into STATUS register
SWAPF W_TEMP,F ;swap W_TEMP
SWAPF W_TEMP,W ;swap W_TEMP into W
© 2010 Microchip Technology Inc. DS41190G-page 67
PIC12F629/675
FIGURE 9-12: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOD
Value on all
other
Resets
81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
2007h Config. bits CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
T0CKI
T0SE
pin
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-out
PS0 - PS2
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
PSA
PSA
PIC12F629/675
DS41190G-page 68 © 2010 Microchip Technology Inc.
9.7 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running
• PD bit in the STATUS register is cleared
• TO bit is set
• Oscillator driver is turned off
• I/O ports maintain the status they had before
Sleep was executed (driving high, low, or
high-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators and CVREF should be disabled. I/O pins that
are high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on GPIO should be considered.
The MCLR pin must be at a logic high level (VIHMC).
9.7.1 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from GP2/INT pin, GPIO change, or a
peripheral interrupt.
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
FIGURE 9-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note: It should be noted that a Reset generated
by a WDT Time-out does not drive MCLR
pin low.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST
(2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 us delay will be there for RC Osc mode. See Section 12 for wake-up from
Sleep delay in INTOSC mode.
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.
© 2010 Microchip Technology Inc. DS41190G-page 69
PIC12F629/675
9.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
9.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
9.10 In-Circuit Serial Programming
The PIC12F629/675 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for:
• power
• ground
• programming voltage
This allows customers to manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see Programming
Specification). GP0 becomes the programming data
and GP1 becomes the programming clock. Both GP0
and GP1 are Schmitt Trigger inputs in this mode.
After Reset, to place the device into Programming/
Verify mode, the PC is at location 00h. A 6-bit
command is then supplied to the device. Depending on
the command, 14-bits of program data are then
supplied to or from the device, depending on whether
the command was a load or a read. For complete
details of serial programming, please refer to the
Programming Specifications.
A typical In-Circuit Serial Programming connection is
shown in Figure 9-14.
FIGURE 9-14: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
9.11 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock,
data and MCLR pins, MPLAB
®
ICD 2 development with
an 8-pin device is not practical. A special 14-pin
PIC12F675-ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user.
This special ICD device is mounted on the top of the
header and its signals are routed to the MPLAB ICD 2
connector. On the bottom of the header is an 8-pin
socket that plugs into the user’s target via the 8-pin
stand-off connector.
When the ICD pin on the PIC12F675-ICD device is
held low, the In-Circuit Debugger functionality is
enabled. This function allows simple debugging
functions when used with MPLAB ICD 2. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 9-10
shows which features are consumed by the
background debugger:
TABLE 9-10: DEBUGGER RESOURCES
For more information, see 8-Pin MPLAB ICD 2 Header
Information Sheet (DS51292) available on Microchip’s
web site (www.microchip.com).
Note: The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. The INTOSC
calibration data is also erased. See
PIC12F629/675 Programming Specifica-
tion for more information.
I/O pins ICDCLK, ICDDATA
Stack 1 level
Program Memory Address 0h must be NOP
300h-3FEh
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC12F629/675
VDD
VSS
GP3/MCLR/VPP
GP1
GP0
+5V
0V
VPP
CLK
Data I/O
VDD
PIC12F629/675
DS41190G-page 70 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 71
PIC12F629/675
10.0 INSTRUCTION SET SUMMARY
The PIC12F629/675 instruction set is highly orthogonal
and is comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC12F629/675 instruction is a 14-bit word
divided into an opcode, which specifies the instruction
type, and one or more operands, which further specify
the operation of the instruction. The formats for each of
the categories is presented in Figure 10-1, while the
various opcode fields are summarized in Table 10-1.
Table 10-2 lists the instructions recognized by the
MPASM
TM
assembler. A complete description of
each instruction is also available in the PIC
®
Mid-
Range Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operations, ‘k’ represents an 8-
bit or 11-bit constant, or literal value.
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 us. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
10.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a CLRF GPIO instruction will read GPIO,
clear all the data bits, then write the result back to
GPIO. This example would have the unintended result
that the condition that sets the GPIF flag would be
cleared.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future products, do not use the OPTION
and TRISIO instructions.
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC12F629/675
DS41190G-page 72 © 2010 Microchip Technology Inc.
TABLE 10-2: PIC12F629/675 INSTRUCTION SET
Mnemonic,
Operands
Description Cycles
14-Bit Opcode
Status
Affected
Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PIC
®
Mid-Range MCU Family Ref-
erence Manual (DS33023).
© 2010 Microchip Technology Inc. DS41190G-page 73
PIC12F629/675
10.2 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [label] ADDLW k
Operands: 0 s k s 255
Operation: (W) + k ÷ (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [label] ADDWF f,d
Operands: 0 s f s 127
d e |0.1|
Operation: (W) + (f) ÷ (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is 0, the
result is stored in the W register. If
‘d’ is 1, the result is stored back in
register ‘f’.
ANDLW AND Literal with W
Syntax: [label] ANDLW k
Operands: 0 s k s 255
Operation: (W) .AND. (k) ÷ (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
ANDWF AND W with f
Syntax: [label] ANDWF f,d
Operands: 0 s f s 127
d e |0.1|
Operation: (W) .AND. (f) ÷ (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is 0, the result is stored in
the W register. If ‘d’ is 1, the result
is stored back in register ‘f’.
BCF Bit Clear f
Syntax: [label] BCF f,b
Operands: 0 s f s 127
0 s b s 7
Operation: 0 ÷ (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [label] BSF f,b
Operands: 0 s f s 127
0 s b s 7
Operation: 1 ÷ (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSS Bit Test f, Skip if Set
Syntax: [label] BTFSS f,b
Operands: 0 s f s 127
0 s b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
2TCY instruction.
PIC12F629/675
DS41190G-page 74 © 2010 Microchip Technology Inc.
BTFSC Bit Test, Skip if Clear
Syntax: [label] BTFSC f,b
Operands: 0 s f s 127
0 s b s 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 s k s 2047
Operation: (PC)+ 1÷ TOS,
k ÷ PC<10:0>,
(PCLATH<4:3>) ÷ PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
CLRF Clear f
Syntax: [label] CLRF f
Operands: 0 s f s 127
Operation: 00h ÷ (f)
1 ÷ Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h ÷ (W)
1 ÷ Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h ÷ WDT
0 ÷ WDT prescaler,
1 ÷ TO
1 ÷ PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) ÷ (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is 0, the
result is stored in W. If ‘d’ is 1, the
result is stored back in register ‘f’.
DECF Decrement f
Syntax: [label] DECF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) - 1 ÷ (destination)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is 0,
the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.
© 2010 Microchip Technology Inc. DS41190G-page 75
PIC12F629/675
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) - 1 ÷ (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead,
making it a 2TCY instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 s k s 2047
Operation: k ÷ PC<10:0>
PCLATH<4:3> ÷ PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) + 1 ÷ (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) + 1 ÷ (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is executed instead, making
it a 2TCY instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 s k s 255
Operation: (W) .OR. k ÷ (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (W) .OR. (f) ÷ (destination)
Status Affected: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is 0, the result is
placed in the W register. If ‘d’ is 1,
the result is placed back in
register ‘f’.
PIC12F629/675
DS41190G-page 76 © 2010 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) ÷ (dest)
Status Affected: Z
Description: The contents of register f is
moved to a destination dependent
upon the status of d. If d = 0,
the destination is W register. If d =
1, the destination is file register f
itself. d = 1 is useful to test a file
register since status flag Z is
affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W = value in FSR
register
Z = 1
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 s k s 255
Operation: k ÷ (W)
Status Affected: None
Description: The eight-bit literal ‘k’ is loaded into
W register. The “don’t cares” will
assemble as ‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 s f s 127
Operation: (W) ÷ (f)
Status Affected: None
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example: MOVWF OPTION
Before Instruction
OPTION= 0xFF
W = 0x4F
After Instruction
OPTION= 0x4F
W = 0x4F
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
© 2010 Microchip Technology Inc. DS41190G-page 77
PIC12F629/675
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS ÷ PC,
1 ÷ GIE
Status Affected: None
Description: Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 s k s 255
Operation: k ÷ (W);
TOS ÷ PC
Status Affected: None
Description: The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words: 1
Cycles: 2
Example:
TABLE
CALL TABLE;W contains
table
;offset value
• ;W now has table value


ADDWF PCL ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;



RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS ÷ PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
PIC12F629/675
DS41190G-page 78 © 2010 Microchip Technology Inc.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry
Flag. If ‘d’ is 0, the result is placed in
the W register. If ‘d’ is 1, the result is
stored back in register ‘f’.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
SLEEP
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h ÷ WDT,
0 ÷ WDT prescaler,
1 ÷ TO,
0 ÷ PD
Status Affected: TO, PD
Description: The power-down Status bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Register f C
Register f C
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 s k s 255
Operation: k - (W) ÷ (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f) - (W) ÷ (destination)
Status
Affected:
C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
0, the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (f<3:0>) ÷ (destination<7:4>),
(f<7:4>) ÷ (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
0, the result is placed in the W
register. If ‘d’ is 1, the result is
placed in register ‘f’.
© 2010 Microchip Technology Inc. DS41190G-page 79
PIC12F629/675
XORLW Exclusive OR Literal with W
Syntax: [label] XORLW k
Operands: 0 s k s 255
Operation: (W) .XOR. k ÷ (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [label] XORWF f,d
Operands: 0 s f s 127
d e [0,1]
Operation: (W) .XOR. (f) ÷ (destination)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
0, the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.
PIC12F629/675
DS41190G-page 80 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 81
PIC12F629/675
11.0 DEVELOPMENT SUPPORT
The PIC
®
microcontrollers and dsPIC
®
digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB
®
IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASM
TM
Assembler
- MPLINK
TM
Object Linker/
MPLIB
TM
Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
11.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows
®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC12F629/675
DS41190G-page 82 © 2010 Microchip Technology Inc.
11.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
11.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
11.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel
®
standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
11.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
11.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
© 2010 Microchip Technology Inc. DS41190G-page 83
PIC12F629/675
11.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC
®
DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
11.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC
®
Flash MCUs and dsPIC
®
Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
11.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip’s most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC
®
Flash microcon-
trollers and dsPIC
®
DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
11.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and
programming of PIC
®
and dsPIC
®
Flash
microcontrollers at a most affordable price point using
the powerful graphical user interface of the MPLAB
Integrated Development Environment (IDE). The
MPLAB PICkit 3 is connected to the design engineer’s
PC using a full speed USB interface and can be
connected to the target via an Microchip debug (RJ-11)
connector (compatible with MPLAB ICD 3 and MPLAB
REAL ICE). The connector uses two device I/O pins
and the reset line to implement in-circuit debugging and
In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
PIC12F629/675
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11.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows
®
programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC
®
microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
11.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
11.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ
®
security ICs, CAN,
IrDA
®
, PowerSmart battery management, SEEVAL
®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2010 Microchip Technology Inc. DS41190G-page 85
PIC12F629/675
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Ambient temperature under bias........................................................................................................... -40 to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V
Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation
(1)
............................................................................................................................... 800 mW
Maximum current out of VSS pin ..................................................................................................................... 300 mA
Maximum current into VDD pin ........................................................................................................................ 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by all GPIO................................................................................................................ 125 mA
Maximum current sourced all GPIO................................................................................................................ 125 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ¯ IOH} + ¯ {(VDD-VOH) x IOH} + ¯(VOl x IOL).
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 O should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
PIC12F629/675
DS41190G-page 86 © 2010 Microchip Technology Inc.
FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,
-40°C s TA s +125°C
FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
-40°C s TA s +125°C
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4
Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
8 16 12 20 10
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4
Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
8 16 12 20 10
© 2010 Microchip Technology Inc. DS41190G-page 87
PIC12F629/675
FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
0°C s TA s +125°C
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4
Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
8 16 12 20 10
2.2
PIC12F629/675
DS41190G-page 88 © 2010 Microchip Technology Inc.
12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +85°C for industrial
-40°C s TA s +125°C for extended
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
D001
D001A
D001B
D001C
D001D
VDD Supply Voltage
2.0
2.2
2.5
3.0
4.5





5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
FOSC < = 4 MHz:
PIC12F629/675 with A/D off
PIC12F675 with A/D on, 0°C to +125°C
PIC12F675 with A/D on, -40°C to +125°C
4 MHZ < FOSC < = 10 MHz
D002 VDR RAM Data Retention
Voltage
(1)
1.5* — — V Device in Sleep mode
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
— VSS — V See section on Power-on Reset for details
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05* — — V/ms See section on Power-on Reset for details
D005 VBOD — 2.1 — V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
© 2010 Microchip Technology Inc. DS41190G-page 89
PIC12F629/675
12.2 DC Characteristics: PIC12F629/675-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +85°C for industrial
Param
No.
Device Characteristics Min Typ† Max Units
Conditions
VDD Note
D010 Supply Current (IDD) — 9 16 uA 2.0 FOSC = 32 kHz
LP Oscillator Mode
— 18 28 uA 3.0
— 35 54 uA 5.0
D011 — 110 150 uA 2.0 FOSC = 1 MHz
XT Oscillator Mode
— 190 280 uA 3.0
— 330 450 uA 5.0
D012 — 220 280 uA 2.0 FOSC = 4 MHz
XT Oscillator Mode
— 370 650 uA 3.0
— 0.6 1.4 mA 5.0
D013 — 70 110 uA 2.0 FOSC = 1 MHz
EC Oscillator Mode
— 140 250 uA 3.0
— 260 390 uA 5.0
D014 — 180 250 uA 2.0 FOSC = 4 MHz
EC Oscillator Mode
— 320 470 uA 3.0
— 580 850 uA 5.0
D015 — 340 450 uA 2.0 FOSC = 4 MHz
INTOSC Mode
— 500 700 uA 3.0
— 0.8 1.1 mA 5.0
D016 — 180 250 uA 2.0 FOSC = 4 MHz
EXTRC Mode
— 320 450 uA 3.0
— 580 800 uA 5.0
D017 — 2.1 2.95 mA 4.5 FOSC = 20 MHz
HS Oscillator Mode
— 2.4 3.0 mA 5.0
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
PIC12F629/675
DS41190G-page 90 © 2010 Microchip Technology Inc.
12.3 DC Characteristics: PIC12F629/675-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +85°C for industrial
Param
No.
Device Characteristics Min Typ† Max Units
Conditions
VDD Note
D020 Power-down Base Current
(IPD)
— 0.99 700 nA 2.0 WDT, BOD, Comparators, VREF,
and T1OSC disabled
— 1.2 770 nA 3.0
— 2.9 995 nA 5.0
D021 — 0.3 1.5 uA 2.0 WDT Current
(1)
— 1.8 3.5 uA 3.0
— 8.4 17 uA 5.0
D022 — 58 70 uA 3.0 BOD Current
(1)
— 109 130 uA 5.0
D023 — 3.3 6.5 uA 2.0 Comparator Current
(1)
— 6.1 8.5 uA 3.0
— 11.5 16 uA 5.0
D024 — 58 70 uA 2.0 CVREF Current
(1)
— 85 100 uA 3.0
— 138 160 uA 5.0
D025 — 4.0 6.5 uA 2.0 T1 OSC Current
(1)
— 4.6 7.0 uA 3.0
— 6.0 10.5 uA 5.0
D026 — 1.2 775 nA 3.0 A/D Current
(1)
— 0.0022 1.0 uA 5.0
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral A current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
© 2010 Microchip Technology Inc. DS41190G-page 91
PIC12F629/675
12.4 DC Characteristics: PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +125°C for extended
Param
No.
Device Characteristics Min Typ† Max Units
Conditions
VDD Note
D010E Supply Current (IDD) — 9 16 uA 2.0 FOSC = 32 kHz
LP Oscillator Mode
— 18 28 uA 3.0
— 35 54 uA 5.0
D011E — 110 150 uA 2.0 FOSC = 1 MHz
XT Oscillator Mode
— 190 280 uA 3.0
— 330 450 uA 5.0
D012E — 220 280 uA 2.0 FOSC = 4 MHz
XT Oscillator Mode
— 370 650 uA 3.0
— 0.6 1.4 mA 5.0
D013E — 70 110 uA 2.0 FOSC = 1 MHz
EC Oscillator Mode
— 140 250 uA 3.0
— 260 390 uA 5.0
D014E — 180 250 uA 2.0 FOSC = 4 MHz
EC Oscillator Mode
— 320 470 uA 3.0
— 580 850 uA 5.0
D015E — 340 450 uA 2.0 FOSC = 4 MHz
INTOSC Mode
— 500 780 uA 3.0
— 0.8 1.1 mA 5.0
D016E — 180 250 uA 2.0 FOSC = 4 MHz
EXTRC Mode
— 320 450 uA 3.0
— 580 800 uA 5.0
D017E — 2.1 2.95 mA 4.5 FOSC = 20 MHz
HS Oscillator Mode
— 2.4 3.0 mA 5.0
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
PIC12F629/675
DS41190G-page 92 © 2010 Microchip Technology Inc.
12.5 DC Characteristics: PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +125°C for extended
Param
No.
Device Characteristics Min Typ† Max Units
Conditions
VDD Note
D020E Power-down Base Current
(IPD)
— 0.00099 3.5 uA 2.0 WDT, BOD, Comparators, VREF,
and T1OSC disabled
— 0.0012 4.0 uA 3.0
— 0.0029 8.0 uA 5.0
D021E — 0.3 6.0 uA 2.0 WDT Current
(1)
— 1.8 9.0 uA 3.0
— 8.4 20 uA 5.0
D022E — 58 70 uA 3.0 BOD Current
(1)
— 109 130 uA 5.0
D023E — 3.3 10 uA 2.0 Comparator Current
(1)
— 6.1 13 uA 3.0
— 11.5 24 uA 5.0
D024E — 58 70 uA 2.0 CVREF Current
(1)
— 85 100 uA 3.0
— 138 165 uA 5.0
D025E — 4.0 10 uA 2.0 T1 OSC Current
(1)
— 4.6 12 uA 3.0
— 6.0 20 uA 5.0
D026E — 0.0012 6.0 uA 3.0 A/D Current
(1)
— 0.0022 8.5 uA 5.0
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral A current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
© 2010 Microchip Technology Inc. DS41190G-page 93
PIC12F629/675
12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +85°C for industrial
-40°C s TA s +125°C for extended
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
Input Low Voltage
VIL I/O ports
D030 with TTL buffer VSS — 0.8 V 4.5V s VDD s 5.5V
D030A VSS — 0.15 VDD V Otherwise
D031 with Schmitt Trigger buffer VSS — 0.2 VDD V Entire range
D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V
D033 OSC1 (XT and LP modes) VSS — 0.3 V (Note 1)
D033A OSC1 (HS mode) VSS — 0.3 VDD V (Note 1)
Input High Voltage
VIH I/O ports —
D040
D040A
with TTL buffer 2.0
(0.25 VDD+0.8)


VDD
VDD
V
V
4.5V s VDD s 5.5V
otherwise
D041 with Schmitt Trigger buffer 0.8 VDD — VDD entire range
D042 MCLR 0.8 VDD — VDD V
D043 OSC1 (XT and LP modes) 1.6 — VDD V (Note 1)
D043A OSC1 (HS mode) 0.7 VDD — VDD V (Note 1)
D043B OSC1 (RC mode) 0.9 VDD — VDD V
D070 IPUR GPIO Weak Pull-up Current 50* 250 400* uA VDD = 5.0V, VPIN = VSS
Input Leakage Current
(3)
D060 IIL I/O ports — ± 0.1 ± 1 uA VSS s VPIN s VDD,
Pin at high-impedance
D060A Analog inputs — ± 0.1 ± 1 uA VSS s VPIN s VDD
D060B VREF — ± 0.1 ± 1 uA VSS s VPIN s VDD
D061 MCLR
(2)
— ± 0.1 ± 5 uA VSS s VPIN s VDD
D063 OSC1 — ± 0.1 ± 5 uA VSS s VPIN s VDD, XT, HS and
LP osc configuration
Output Low Voltage
D080 VOL I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)
D083 OSC2/CLKOUT (RC mode) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
Output High Voltage
D090 VOH I/O ports VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.)
D092 OSC2/CLKOUT (RC mode) VDD - 0.7 — — V IOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
PIC12F629/675
DS41190G-page 94 © 2010 Microchip Technology Inc.
12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C s TA s +85°C for industrial
-40°C s TA s +125°C for extended
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin — — 15* pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101 CIO All I/O pins — — 50* pF
Data EEPROM Memory
D120 ED Byte Endurance 100K 1M — E/W -40°C s TA s +85°C
D120A ED Byte Endurance 10K 100K — E/W +85°C s TA s +125°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write cycle time — 5 6 ms
D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
D124 TREF Number of Total Erase/Write
Cycles before Refresh
(1)
1M 10M — E/W -40°C s TA s +85°C
Program Flash Memory
D130 EP Cell Endurance 10K 100K — E/W -40°C s TA s +85°C
D130A ED Cell Endurance 1K 10K — E/W +85°C s TA s +125°C
D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 2 2.5 ms
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Section 8.5.1 “Using the Data EEPROM” for additional information.
© 2010 Microchip Technology Inc. DS41190G-page 95
PIC12F629/675
12.8 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with
one of the following formats:
FIGURE 12-4: LOAD CONDITIONS
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-Impedance) V Valid
L Low Z High-Impedance
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL = 464O
CL = 50 pF for all pins
15 pF for OSC2 output
Load Condition 1 Load Condition 2
PIC12F629/675
DS41190G-page 96 © 2010 Microchip Technology Inc.
12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED)
FIGURE 12-5: EXTERNAL CLOCK TIMING
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
FOSC External CLKIN Frequency
(1)
DC — 37 kHz LP Osc mode
DC — 4 MHz XT mode
DC — 20 MHz HS mode
DC — 20 MHz EC mode
Oscillator Frequency
(1)

5 — 37 kHz LP Osc mode
— 4 — MHz INTOSC mode
DC — 4 MHz RC Osc mode
0.1 — 4 MHz XT Osc mode
1 — 20 MHz HS Osc mode
1 TOSC External CLKIN Period
(1)
27 — · us LP Osc mode
50 — · ns HS Osc mode
50 — · ns EC Osc mode
250 — · ns XT Osc mode
Oscillator Period
(1)
27 200 us LP Osc mode
— 250 — ns INTOSC mode
250 — — ns RC Osc mode
250 — 10,000 ns XT Osc mode
50 — 1,000 ns HS Osc mode
2 TCY
Instruction Cycle Time
(1)
200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH
External CLKIN (OSC1) High
External CLKIN Low
2* — — us LP oscillator, TOSC L/H duty cycle
20* — — ns HS oscillator, TOSC L/H duty
cycle
100 * — — ns XT oscillator, TOSC L/H duty cycle
4 TosR,
TosF
External CLKIN Rise
External CLKIN Fall
— — 50* ns LP oscillator
— — 25* ns XT oscillator
— — 15* ns HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is “DC” (no clock)
for all devices.
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3 3 4 4
© 2010 Microchip Technology Inc. DS41190G-page 97
PIC12F629/675
TABLE 12-2: PRECISION INTERNAL OSCILLATOR PARAMETERS
Param
No.
Sym Characteristic
Freq.
Tolerance
Min Typ† Max Units Conditions
F10 FOSC Internal Calibrated
INTOSC Frequency
±1 3.96 4.00 4.04 MHz VDD = 3.5V, 25°C
±2 3.92 4.00 4.08 MHz 2.5V s VDD s 5.5V
0°C s TA s +85°C
±5 3.80 4.00 4.20 MHz 2.0V s VDD s 5.5V
-40°C s TA s +85°C (IND)
-40°C s TA s +125°C (EXT)
F14 TIOSCST Oscillator Wake-up from
Sleep start-up time*
— — 6 8 us VDD = 2.0V, -40°C to +85°C
— — 4 6 us VDD = 3.0V, -40°C to +85°C
— — 3 5 us VDD = 5.0V, -40°C to +85°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC12F629/675
DS41190G-page 98 © 2010 Microchip Technology Inc.
FIGURE 12-6: CLKOUT AND I/O TIMING
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
10 TosH2ckL OSC1| to CLOUT| — 75 200 ns (Note 1)
11 TosH2ckH OSC1| to CLOUT| — 75 200 ns (Note 1)
12 TckR CLKOUT rise time — 35 100 ns (Note 1)
13 TckF CLKOUT fall time — 35 100 ns (Note 1)
14 TckL2ioV CLKOUT| to Port out valid — — 20 ns (Note 1)
15 TioV2ckH Port in valid before CLKOUT| TOSC + 200
ns
— — ns (Note 1)
16 TckH2ioI Port in hold after CLKOUT| 0 — — ns (Note 1)
17 TosH2ioV OSC1| (Q1 cycle) to Port out valid — 50 150 * ns
— — 300 ns
18 TosH2ioI OSC1| (Q2 cycle) to Port input
invalid (I/O in hold time)
100 — — ns
19 TioV2osH Port input valid to OSC1|
(I/O in setup time)
0 — — ns
20 TioR Port output rise time — 10 40 ns
21 TioF Port output fall time — 10 40 ns
22 Tinp INT pin high or low time 25 — — ns
23 Trbp GPIO change INT high or low time TCY — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
OSC1
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
22
23
19 18
15
11
12
16
Old Value New Value
© 2010 Microchip Technology Inc. DS41190G-page 99
PIC12F629/675
FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
BVDD
Reset (due to BOD)
VDD
(Device in Brown-out Detect)
(Device not in Brown-out Detect)
72 ms time-out
(1)
35
Note 1: 72 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.
PIC12F629/675
DS41190G-page 100 © 2010 Microchip Technology Inc.
TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT DETECT REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
30 TMCL
MCLR Pulse Width (low)
2
TBD

TBD

TBD
us
ms
VDD = 5V, -40°C to +85°C
Extended temperature
31 TWDT Watchdog Timer Time-out
Period
(No Prescaler)
10
10
17
17
25
30
ms
ms
VDD = 5V, -40°C to +85°C
Extended temperature
32 TOST Oscillation Start-up Timer
Period
— 1024TOSC — — TOSC = OSC1 period
33* TPWRT Power-up Timer Period 28*
TBD
72
TBD
132*
TBD
ms
ms
VDD = 5V, -40°C to +85°C
Extended Temperature
34 TIOZ I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
— — 2.0 us
BVDD Brown-out Detect Voltage 2.025 — 2.175 V
Brown-out Hysteresis TBD — — —
35 TBOD Brown-out Detect Pulse Width 100* — — us VDD s BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
© 2010 Microchip Technology Inc. DS41190G-page 101
PIC12F629/675
FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* Tt0P T0CKI Period Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with Prescaler
15 — — ns
Asynchronous 30 — — ns
46* Tt1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with Prescaler
15 — — ns
Asynchronous 30 — — ns
47* Tt1P T1CKI Input
Period
Synchronous Greater of:
30 or TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Asynchronous 60 — — ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
DC — 200* kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2 TOSC* — 7
TOSC*

* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
T0CKI
T1CKI
40 41
42
45 46
47 48
TMR0 or
TMR1
PIC12F629/675
DS41190G-page 102 © 2010 Microchip Technology Inc.
TABLE 12-6: COMPARATOR SPECIFICATIONS
TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Comparator Specifications
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Sym Characteristics Min Typ Max Units Comments
VOS Input Offset Voltage — ± 5.0 ± 10 mV
VCM Input Common Mode Voltage 0 — VDD - 1.5 V
CMRR Common Mode Rejection Ratio +55* — — db
TRT Response Time
(1)
— 150 400* ns
TMC2COV Comparator Mode Change to
Output Valid
— — 10* us
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD - 1.5V.
Voltage Reference Specifications
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Sym Characteristics Min Typ Max Units Comments
Resolution —

VDD/24*
VDD/32


LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy —



± 1/2
± 1/2*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R) — 2k* — O
Settling Time
(1)
— — 10* us
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
© 2010 Microchip Technology Inc. DS41190G-page 103
PIC12F629/675
TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS:
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
A01 NR Resolution — — 10 bits bit
A02 EABS Total Absolute
Error*
— — ±1 LSb VREF = 5.0V
A03 EIL Integral Error — — ±1 LSb VREF = 5.0V
A04 EDL Differential Error — — ±1 LSb No missing codes to 10 bits
VREF = 5.0V
A05 EFS Full Scale Range 2.2* — 5.5* V
A06 EOFF Offset Error — — ±1 LSb VREF = 5.0V
A07 EGN Gain Error — — ±1 LSb VREF = 5.0V
A10 — Monotonicity — guaranteed
(3)
— — VSS s VAIN s VREF+
A20
A20A
VREF Reference Voltage 2.0
2.5
— —
VDD + 0.3
V
Absolute minimum to ensure 10-bit
accuracy
A21 VREF Reference V High
(VDD or VREF)
VSS — VDD V
A25 VAIN Analog Input
Voltage
VSS — VREF V
A30 ZAIN Recommended
Impedance of
Analog Voltage
Source
— — 10 kO
A50 IREF VREF Input
Current
(2)

10



1000
10
uA
uA
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
PIC12F629/675
DS41190G-page 104 © 2010 Microchip Technology Inc.
FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE)
TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D Clock Period 1.6 — — us TOSC based, VREF > 3.0V
3.0* — — us TOSC based, VREF full range
130 TAD A/D Internal RC
Oscillator Period 3.0* 6.0 9.0* us
ADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0* 4.0 6.0* us At VDD = 5.0V
131 TCNV Conversion Time
(not including
Acquisition Time)
(1)
— 11 — TAD Set GO bit to new data in A/D result
register
132 TACQ Acquisition Time (Note 2)
5*
11.5



us
us The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
voltage (as stored on CHOLD).
134 TGO Q4 to A/D Clock
Start
— TOSC/2 — — If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
9 8 7 3 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
6
134 (TOSC/2)
(1)
1 TCY
© 2010 Microchip Technology Inc. DS41190G-page 105
PIC12F629/675
FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D Clock Period 1.6 — — us VREF > 3.0V
3.0* — — us VREF full range
130 TAD A/D Internal RC
Oscillator Period 3.0* 6.0 9.0* us
ADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0* 4.0 6.0* us At VDD = 5.0V
131 TCNV Conversion Time
(not including
Acquisition Time)
(1)

— 11 — TAD
132 TACQ Acquisition Time (Note 2)
5*
11.5



us
us The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
134 TGO Q4 to A/D Clock
Start
— TOSC/2 + TCY — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
9 7 3 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
134
6 8
132
1 TCY (TOSC/2 + TCY)
(1)
1 TCY
PIC12F629/675
DS41190G-page 106 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 107
PIC12F629/675
13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. “Typical” represents the mean of the distribution at 25°C. “Max” or “min” represents
(mean + 3o) or (mean - 3o) respectively, where o is standard deviation, over the whole temperature range.
FIGURE 13-1: TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C)
FIGURE 13-2: TYPICAL IPD vs. VDD OVER TEMP (+85°C)
Typical Baseline IPD
0.0E+00
1.0E-09
2.0E-09
3.0E-09
4.0E-09
5.0E-09
6.0E-09
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
A
)
-40
0
25
Typical Baseline IPD
0.0E+00
5.0E-08
1.0E-07
1.5E-07
2.0E-07
2.5E-07
3.0E-07
3.5E-07
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
A
)
85
PIC12F629/675
DS41190G-page 108 © 2010 Microchip Technology Inc.
FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C)
FIGURE 13-4: MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Typical Baseline IPD
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
3.0E-06
3.5E-06
4.0E-06
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
A
)
125
Maximum Baseline IPD
0.0E+00
1.0E-08
2.0E-08
3.0E-08
4.0E-08
5.0E-08
6.0E-08
7.0E-08
8.0E-08
9.0E-08
1.0E-07
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
A
)
-40
0
25
© 2010 Microchip Technology Inc. DS41190G-page 109
PIC12F629/675
FIGURE 13-5: MAXIMUM IPD vs. VDD OVER TEMP (+85°C)
FIGURE 13-6: MAXIMUM IPD vs. VDD OVER TEMP (+125°C)
Maximum Baseline IPD
0.0E+00
1.0E-07
2.0E-07
3.0E-07
4.0E-07
5.0E-07
6.0E-07
7.0E-07
8.0E-07
9.0E-07
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
A
)
85
Maximum Baseline IPD
0.0E+00
1.0E-06
2.0E-06
3.0E-06
4.0E-06
5.0E-06
6.0E-06
7.0E-06
8.0E-06
9.0E-06
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
A
)
125
PIC12F629/675
DS41190G-page 110 © 2010 Microchip Technology Inc.
FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
FIGURE 13-8: TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical BOD IPD
50
60
70
80
90
100
110
120
130
3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
u
A
)
-40
0
25
85
125
Typical Comparator IPD
0.0E+00
2.0E-06
4.0E-06
6.0E-06
8.0E-06
1.0E-05
1.2E-05
1.4E-05
1.6E-05
1.8E-05
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
A
)
-40
0
25
85
125
© 2010 Microchip Technology Inc. DS41190G-page 111
PIC12F629/675
FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)
FIGURE 13-10: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)
Typical A/D IPD
0.0E+00
5.0E-10
1.0E-09
1.5E-09
2.0E-09
2.5E-09
3.0E-09
3.5E-09
4.0E-09
4.5E-09
5.0E-09
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
A
)
-40
0
25
Typical A/D IPD
0.0E+00
5.0E-08
1.0E-07
1.5E-07
2.0E-07
2.5E-07
3.0E-07
3.5E-07
2 2.5 3 3.5 4 4.5 5 5.5
V
DD (V)
I
P
D

(
A
)
85
PIC12F629/675
DS41190G-page 112 © 2010 Microchip Technology Inc.
FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)
FIGURE 13-12: TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),
32 kHZ, C1 AND C2=50 pF)
Typical A/D IPD
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
3.0E-06
3.5E-06
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
A
)
125
Typical T1 IPD
0.00E+00
2.00E-06
4.00E-06
6.00E-06
8.00E-06
1.00E-05
1.20E-05
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
I
P
D

(
A
)
-40
0
25
85
125
© 2010 Microchip Technology Inc. DS41190G-page 113
PIC12F629/675
FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
FIGURE 13-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical CVREF IPD
40
60
80
100
120
140
160
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
u
A
)
-40
0
25
85
125
Typical WDT IPD
0
2
4
6
8
10
12
14
16
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
I
P
D

(
u
A
)
-40
0
25
85
125
PIC12F629/675
DS41190G-page 114 © 2010 Microchip Technology Inc.
FIGURE 13-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1uF AND
0.01uF DECOUPLING (VDD = 3.5V)
FIGURE 13-16: MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1uF AND 0.01uF
DECOUPLING (+25°C)
Internal Oscillator
Frequency vs Temperature
3.80E+06
3.85E+06
3.90E+06
3.95E+06
4.00E+06
4.05E+06
4.10E+06
4.15E+06
4.20E+06
-40°C 0°C 25°C 85°C 125°C
Temperature (°C)
F
r
e
q
u
e
n
c
y

(
H
z
)
-3sigma
average
+3sigma
Internal Oscillator
Frequency vs VDD
3.80E+06
3.85E+06
3.90E+06
3.95E+06
4.00E+06
4.05E+06
4.10E+06
4.15E+06
4.20E+06
2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
VDD (V)
F
r
e
q
u
e
n
c
y

(
H
z
)
-3sigma
average
+3sigma
© 2010 Microchip Technology Inc. DS41190G-page 115
PIC12F629/675
FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C)
WDT Time-out
0
5
10
15
20
25
30
35
40
45
50
2 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
T
i
m
e

(
m
S
)
-40
0
25
85
125
PIC12F629/675
DS41190G-page 116 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 117
PIC12F629/675
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
XXXXXNNN
8-Lead PDIP (Skinny DIP) Example
XXXXXXXX
YYWW
/017
12F629-I
0215
XXXXYYWW
8-Lead SOIC
XXXXXXXX
NNN
/0215
Example
12F629-E
017
8-Lead DFN-S
XXXXXXX
NNN
XXXXXXX
XXYYWW
-E/021
017
12F629
0215
Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3 e
3 e
3 e
3 e
3 e

XXXXXX
8-Lead DFN (4x4 mm)
YYWW
NNN
Example
XXXXXX
XXXXXX
0610
017
XXXX
3 e
PIC12F629/675
DS41190G-page 118 © 2010 Microchip Technology Inc.
14.2 Package Details
The following sections give the technical details of the packages.
8-Lead PIastic DuaI In-Line (P) - 300 miI Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units ÌNCHES
Dimension Limits MÌN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A ÷ ÷ .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 ÷ ÷
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB ÷ ÷ .430
N
E1
NOTE 1
D
1 2 3
A
A1
A2
L
b1
b
e
E
eB
c
Microchip Technology Drawing C04-018B
© 2010 Microchip Technology Inc. DS41190G-page 119
PIC12F629/675

8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MÌLLÌMETERS
Dimension Limits MÌN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A ÷ ÷ 1.75
Molded Package Thickness A2 1.25 ÷ ÷
Standoff § A1 0.10 ÷ 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 ÷ 0.50
Foot Length L 0.40 ÷ 1.27
Footprint L1 1.04 REF
Foot Angle I 0° ÷ 8°
Lead Thickness c 0.17 ÷ 0.25
Lead Width b 0.31 ÷ 0.51
Mold Draft Angle Top D 5° ÷ 15°
Mold Draft Angle Bottom E 5° ÷ 15°
D
N
e
E
E1
NOTE 1
1 2 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
Microchip Technology Drawing C04-057B
PIC12F629/675
DS41190G-page 120 © 2010 Microchip Technology Inc.
8-Lead PIastic SmaII OutIine (SN) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2010 Microchip Technology Inc. DS41190G-page 121
PIC12F629/675
8-Lead PIastic DuaI FIat, No Lead Package (MF) - 6x5 mm Body [DFN-S]

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MÌLLÌMETERS
Dimension Limits MÌN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A 0.80 0.85 1.00
Standoff A1 0.00 0.01 0.05
Contact Thickness A3 0.20 REF
Overall Length D 5.00 BSC
Overall Width E 6.00 BSC
Exposed Pad Length D2 3.90 4.00 4.10
Exposed Pad Width E2 2.20 2.30 2.40
Contact Width b 0.35 0.40 0.48
Contact Length L 0.50 0.60 0.75
Contact-to-Exposed Pad K 0.20 ÷ ÷
NOTE 2
A1
A
A3
NOTE 1
1 2
E
N
D
EXPOSED PAD
NOTE 1
2 1
E2
L
N
e
b
K
BOTTOM VIEW
TOP VIEW
D2
Microchip Technology Drawing C04-122B
PIC12F629/675
DS41190G-page 122 © 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2010 Microchip Technology Inc. DS41190G-page 123
PIC12F629/675
8-Lead Plastic DuaI Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
PIC12F629/675
DS41190G-page 124 © 2010 Microchip Technology Inc.
8-Lead Plastic DuaI Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
© 2010 Microchip Technology Inc. DS41190G-page 125
PIC12F629/675
8-Lead PIastic DuaI FIat, No Lead Package (MD) - 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC12F629/675
DS41190G-page 126 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 127
PIC12F629/675
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
Revision B
Added characterization graphs.
Updated specifications.
Added notes to indicate Microchip programmers
maintain all Calibration bits to factory settings and the
PIC12F675 ANSEL register must be initialized to
configure pins as digital I/O.
Updated MLF-S package name to DFN-S.
Revision C
Revision D (01/2007)
Updated Package Drawings; Replace PICmicro with
PIC; Revised Product ID example (b).
Revision E (03/2007)
Replaced Package Drawings (Rev. AM); Replaced
Development Support Section.
Revision F (09/2009)
Updated Registers to new format; Added information to
the “Package Marking Information” (8-Lead DFN) and
“Package Details” sections (8-Lead Dual Flat, No Lead
Package (MD) 4X4X0.9 mm Body (DFN)); Added Land
Patterns for SOIC (SN) and DFN-S (MF) packages;
Updated Register 3-2; Added MD Package to the
Product identification System chapter; Other minor
corrections.
Revision G (03/2010)
Updated the Instruction Set Summary section, adding
pages 76 and 77.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC12F629/675 devices
listed in this data sheet are shown in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Feature PIC12F629 PIC12F675
A/D No Yes
PIC12F629/675
DS41190G-page 128 © 2010 Microchip Technology Inc.
APPENDIX C: DEVICE MIGRATIONS
This section is intended to describe the functional and
electrical specification differences when migrating
between functionally similar devices (such as from a
PIC16C74A to a PIC16C74B).
Not Applicable
APPENDIX D: MIGRATING FROM
OTHER PIC
®

DEVICES
This discusses some of the issues in migrating from
other PIC devices to the PIC12F6XX family of devices.
D.1 PIC12C67X to PIC12F6XX
TABLE 1: FEATURE COMPARISON
Feature PIC12C67X PIC12F6XX
Max Operating Speed 10 MHz 20 MHz
Max Program Memory 2048 bytes 1024 bytes
A/D Resolution 8-bit 10-bit
Data EEPROM 16 bytes 64 bytes
Oscillator Modes 5 8
Brown-out Detect N Y
Internal Pull-ups GP0/1/3 GP0/1/2/4/5
Interrupt-on-change GP0/1/3 GP0/1/2/3/4/5
Comparator N Y
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
Note: The user should verify that the device
oscillator starts and performs as expected.
Adjusting the loading capacitor values and/
or the oscillator mode may be required.
© 2010 Microchip Technology Inc. DS41190G-page 129
PIC12F629/675
INDEX
A
A/D...................................................................................... 43
Acquisition Requirements ........................................... 47
Block Diagram............................................................. 43
Calculating Acquisition Time....................................... 47
Configuration and Operation....................................... 43
Effects of a RESET..................................................... 48
Internal Sampling Switch (Rss) Impedance................ 47
Operation During SLEEP............................................ 48
PIC12F675 Converter Characteristics ...................... 103
Source Impedance...................................................... 47
Summary of Registers ................................................ 48
Absolute Maximum Ratings ................................................ 85
AC Characteristics
Industrial and Extended .............................................. 96
ADCON0
A/D Control register (ADDRESS
1Fh) .................................................................... 45
Additional Pin Functions ..................................................... 21
Interrupt-on-Change.................................................... 23
Weak Pull-up............................................................... 21
Analog Input Connection Considerations............................ 40
Analog-to-Digital Converter. See A/D
Assembler
MPASM Assembler..................................................... 82
B
Block Diagram
TMR0/WDT Prescaler................................................. 29
Block Diagrams
Analog Input Mode...................................................... 40
Analog Input Model ..................................................... 47
Comparator Output ..................................................... 40
Comparator Voltage Reference .................................. 41
GP0 and GP1 Pins...................................................... 24
GP2............................................................................. 25
GP3............................................................................. 25
GP4............................................................................. 26
GP5............................................................................. 26
On-Chip Reset Circuit ................................................. 57
RC Oscillator Mode..................................................... 56
Timer1......................................................................... 32
Watchdog Timer.......................................................... 67
Brown-out
Associated Registers .................................................. 60
Brown-out Detect (BOD) ..................................................... 59
Brown-out Detect Timing and Characteristics..................... 99
C
C Compilers
MPLAB C18 ................................................................ 82
Calibrated Internal RC Frequencies.................................... 97
CLKOUT ............................................................................. 56
Code Examples
Changing Prescaler .................................................... 31
Data EEPROM Read .................................................. 51
Data EEPROM Write .................................................. 51
Initializing GPIO.......................................................... 21
Saving STATUS and W Registers in RAM ................. 66
Write Verify ................................................................. 51
Code Protection .................................................................. 69
Comparator ......................................................................... 37
Associated Registers .................................................. 42
Configuration............................................................... 39
Effects of a RESET..................................................... 41
I/O Operating Modes................................................... 39
Interrupts .................................................................... 42
Operation.................................................................... 38
Operation During SLEEP............................................ 41
Output......................................................................... 40
Reference................................................................... 41
Response Time .......................................................... 41
Comparator Specifications................................................ 102
Comparator Voltage Reference Specifications................. 102
Configuration Bits ............................................................... 54
Configuring the Voltage Reference..................................... 41
Crystal Operation................................................................ 55
Customer Change Notification Service............................. 133
Customer Notification Service .......................................... 133
Customer Support............................................................. 133
D
Data EEPROM Memory
Associated Registers/Bits........................................... 52
Code Protection.......................................................... 52
EEADR Register......................................................... 49
EECON1 Register ...................................................... 49
EECON2 Register ...................................................... 49
EEDATA Register....................................................... 49
Data Memory Organization................................................... 9
DC Characteristics
Extended and Industrial .............................................. 93
Industrial ..................................................................... 88
Development Support ......................................................... 81
Device Differences............................................................ 127
Device Migrations ............................................................. 128
Device Overview................................................................... 7
E
EEADR — EEPROM Address Register (ADDRESS
9Bh) ............................................................................ 49
EECON1 — EEPROM Control register (Address
9Ch)............................................................................ 50
EEPROM Data Memory
Reading ...................................................................... 51
Spurious Write............................................................ 51
Write Verify................................................................. 51
Writing ........................................................................ 51
Electrical Specifications...................................................... 85
Errata.................................................................................... 5
F
Firmware Instructions ......................................................... 71
G
General Purpose Register File ............................................. 9
GPIO
Associated Registers.................................................. 27
GPIO — GPIO register (ADDRESS
05H)............................................................................ 21
GPIO Port ........................................................................... 21
GPIO, TRISIO Registers..................................................... 21
I
ID Locations........................................................................ 69
In-Circuit Debugger............................................................. 69
In-Circuit Serial Programming............................................. 69
Indirect Addressing, INDF and FSR Registers ................... 20
Instruction Format............................................................... 71
Instruction Set..................................................................... 71
ADDLW....................................................................... 73
ADDWF ...................................................................... 73
ANDLW....................................................................... 73
ANDWF ...................................................................... 73
MOVF......................................................................... 76
PIC12F629/675
DS41190G-page 130 © 2010 Microchip Technology Inc.
BCF............................................................................. 73
BSF............................................................................. 73
BTFSC ........................................................................ 74
BTFSS ........................................................................ 73
CALL........................................................................... 74
CLRF........................................................................... 74
CLRW......................................................................... 74
CLRWDT..................................................................... 74
COMF ......................................................................... 74
DECF .......................................................................... 74
DECFSZ...................................................................... 75
GOTO ......................................................................... 75
INCF............................................................................ 75
INCFSZ....................................................................... 75
IORLW........................................................................ 75
IORWF........................................................................ 75
MOVLW...................................................................... 76
MOVWF ...................................................................... 76
NOP............................................................................ 76
RETFIE ....................................................................... 77
RETLW....................................................................... 77
RETURN..................................................................... 77
RLF ............................................................................. 78
RRF............................................................................. 78
SLEEP ........................................................................ 78
SUBLW....................................................................... 78
SUBWF....................................................................... 78
SWAPF ....................................................................... 78
XORLW....................................................................... 79
XORWF....................................................................... 79
Summary Table........................................................... 72
Internal 4 MHz Oscillator..................................................... 56
Internal Sampling Switch (Rss) Impedance ........................ 47
Internet Address................................................................ 133
Interrupts............................................................................. 63
A/D Converter ............................................................. 65
Comparator ................................................................. 65
Context Saving............................................................ 66
GP2/INT...................................................................... 65
GPIO........................................................................... 65
Summary of Registers ................................................ 66
TMR0 .......................................................................... 65
IOC — INTERRUPT-ON-CHANGE GPIO register
(ADDRESS 96h) ................................................................. 23
M
MCLR.................................................................................. 58
Memory Organization
Data EEPROM Memory.............................................. 49
Microchip Internet Web Site.............................................. 133
Migrating from other PICmicro Devices ............................ 128
MPLAB ASM30 Assembler, Linker, Librarian ..................... 82
MPLAB Integrated Development Environment Software .... 81
MPLAB PM3 Device Programmer....................................... 84
MPLAB REAL ICE In-Circuit Emulator System................... 83
MPLINK Object Linker/MPLIB Object Librarian .................. 82
O
OPCODE Field Descriptions............................................... 71
Oscillator Configurations..................................................... 55
Oscillator Start-up Timer (OST) .......................................... 58
P
Packaging ......................................................................... 117
Details ....................................................................... 118
Marking ..................................................................... 117
PCL and PCLATH............................................................... 19
Computed GOTO........................................................ 19
Stack........................................................................... 19
Pin Descriptions and Diagrams .......................................... 24
Pinout Descriptions
PIC12F629 ................................................................... 8
PIC12F675 ................................................................... 8
Power Control/Status Register (PCON).............................. 59
Power-Down Mode (SLEEP) .............................................. 68
Power-on Reset (POR)....................................................... 58
Power-up Timer (PWRT) .................................................... 58
Prescaler............................................................................. 31
Switching Prescaler Assignment ................................ 31
Program Memory Organization............................................. 9
Programming, Device Instructions...................................... 71
R
RC Oscillator....................................................................... 56
Reader Response............................................................. 134
READ-MODIFY-WRITE OPERATIONS............................. 71
Registers
ANSEL (Analog Select) .............................................. 46
CONFIG (Configuration Word) ................................... 54
EEADR (EEPROM Address) ...................................... 50
EECON1 (EEPROM Control) ..................................... 51
EEDAT (EEPROM Data) ............................................ 49
INTCON (Interrupt Control)......................................... 15
IOCB (Interrupt-on-Change GPIO) ............................. 24
Maps
PIC12F629 ......................................................... 10
PIC12F675 ......................................................... 10
OPTION_REG (Option) .................................. 14, 30, 31
OSCCAL (Oscillator Calibration) ................................ 18
PCON (Power Control) ............................................... 18
PIE1 (Peripheral Interrupt Enable 1)........................... 16
PIR1 (Peripheral Interrupt 1)....................................... 17
STATUS ..................................................................... 14
T1CON (Timer1 Control) ............................................ 34
VRCON (Voltage Reference Control) ......................... 42
WPU (Weak Pull-up)................................................... 23
RESET................................................................................ 57
Revision History................................................................ 127
S
Software Simulator (MPLAB SIM) ...................................... 83
Special Features of the CPU.............................................. 53
Special Function Registers................................................. 10
Special Functions Registers Summary............................... 11
STATUS — STATUS Register (ADDRESS
03h or 83h) ................................................................. 13
T
Time-out Sequence ............................................................ 59
Timer0................................................................................. 29
Associated Registers.................................................. 31
External Clock............................................................. 30
Interrupt ...................................................................... 29
Operation.................................................................... 29
T0CKI ......................................................................... 30
Timer1
Associated Registers.................................................. 35
Asynchronous Counter Mode..................................... 35
Reading and Writing........................................... 35
Interrupt ...................................................................... 33
Modes of Operations .................................................. 33
Operation During SLEEP............................................ 35
Oscillator..................................................................... 35
Prescaler .................................................................... 33
Timer1 Module with Gate Control ....................................... 32
Timing Diagrams
© 2010 Microchip Technology Inc. DS41190G-page 131
PIC12F629/675
CLKOUT and I/O......................................................... 98
External Clock............................................................. 96
INT Pin Interrupt.......................................................... 65
PIC12F675 A/D Conversion (Normal Mode)............. 104
PIC12F675 A/D Conversion Timing
(SLEEP Mode) .......................................................... 105
RESET, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer .................................................. 99
Time-out Sequence on Power-up (MCLR not Tied to
VDD)/
Case 1 ................................................................ 62
Case 2 ................................................................ 62
Time-out Sequence on Power-up
(MCLR Tied to VDD).................................................... 62
Timer0 and Timer1 External Clock ........................... 101
Timer1 Incrementing Edge.......................................... 33
Timing Parameter Symbology............................................. 95
TRISIO — GPIO Tri-state REGISTER (Address
85H) ............................................................................ 22
V
Voltage Reference Accuracy/Error ..................................... 41
W
Watchdog Timer
Summary of Registers ................................................ 67
Watchdog Timer (WDT) ...................................................... 66
WPU — Weak pull-up Register (ADDRESS
95h)............................................................................. 22
WWW Address.................................................................. 133
WWW, On-Line Support ....................................................... 5
PIC12F629/675
DS41190G-page 132 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS41190G-page 133
PIC12F629/675
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
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Customers should contact their distributor,
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Technical support is available through the web site
at: http://support.microchip.com
PIC12F629/675
DS41190G-page 134 © 2010 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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DS41190G PIC12F629/675
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2010 Microchip Technology Inc. DS41190G-page 135
PIC12F629/675
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
PART NO. X /XX XXX
Pattern Package Temperature
Range
Device

Device: PIC12F6XX: Standard VDD range
PIC12F6XXT: (Tape and Reel)
Temperature
Range:
I = -40°C to +85°C (Industrial)
E = -40°C to +125°C (Extended)
Package: P = PDIP
SN = SOIC (Gull wing, 3.90 mm body)
MF = MLF-S
MD = 8-Lead Plastic Dual Flat, No Lead (4X4) (DFN)
Pattern: 3-Digit Pattern Code for QTP (blank otherwise)
Examples:
a) PIC12F629 - E/P 301 = Extended Temp., PDIP
package, 20 MHz, QTP pattern #301.
b) PIC12F675 - I/SN = Industrial temp., SOIC
package, 20 MHz.
DS41190G-page 136 © 2010 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
01/05/10

Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

• •

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

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DS41190G-page 2

 2010 Microchip Technology Inc.

PIC12F629/675
8-Pin Flash-Based 8-Bit CMOS Microcontroller
High-Performance RISC CPU:
• Only 35 Instructions to Learn - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect, and Relative Addressing modes

Low-Power Features:
• Standby Current: - 1 nA @ 2.0V, typical • Operating Current: - 8.5 A @ 32 kHz, 2.0V, typical - 100 A @ 1 MHz, 2.0V, typical • Watchdog Timer Current - 300 nA @ 2.0V, typical • Timer1 Oscillator Current: - 4 A @ 32 kHz, 2.0V, typical

Special Microcontroller Features:
• Internal and External Oscillator Options - Precision Internal 4 MHz oscillator factory calibrated to ±1% - External Oscillator support for crystals and resonators - 5 s wake-up from Sleep, 3.0V, typical • Power-Saving Sleep mode • Wide Operating Voltage Range – 2.0V to 5.5V • Industrial and Extended Temperature Range • Low-Power Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Detect (BOD) • Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation • Multiplexed MCLR/Input Pin • Interrupt-on-Pin Change • Individual Programmable Weak Pull-ups • Programmable Code Protection • High Endurance Flash/EEPROM Cell - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM Retention: > 40 years

Peripheral Features:
• 6 I/O Pins with Individual Direction Control • High Current Sink/Source for Direct LED Drive • Analog Comparator module with: - One analog comparator - Programmable on-chip comparator voltage reference (CVREF) module - Programmable input multiplexing from device inputs - Comparator output is externally accessible • Analog-to-Digital Converter module (PIC12F675): - 10-bit resolution - Programmable 4-channel input - Voltage reference input • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator, if INTOSC mode selected • In-Circuit Serial ProgrammingTM (ICSPTM) via two pins

Device

Program Memory Flash (words) 1024 1024

Data Memory SRAM (bytes) 64 64 EEPROM (bytes) 128 128 I/O

10-bit A/D (ch) — 4

Comparators

Timers 8/16-bit 1/1 1/1

PIC12F629 PIC12F675

6 6

1 1

* 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.

 2010 Microchip Technology Inc.

DS41190G-page 3

PIC12F629/675 Pin Diagrams 8-pin PDIP. SOIC. . DFN-S. DFN VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/VPP 1 8 VSS GP0/CIN+/ICSPDAT GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT 2 3 4 PIC12F629 7 6 5 GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/VPP PIC12F675 VDD 1 2 3 4 8 7 6 5 VSS GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT DS41190G-page 4  2010 Microchip Technology Inc.

...............com to receive the most current information on all of our products................................................................................................................................. 32 6............................0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) .............................................................................microchip..........................................0 Electrical Specifications ............................................................................................................... we will continue to improve our publications to better suit your needs........microchip.... Our publications will be refined and enhanced as new volumes and updates are introduced........................................................... 7 2........ revision of silicon and data sheet (include literature number) you are using............................................................................................. may exist for current devices............................................................. 9 3............................................................................................................................... 29 5...........0 Special Features of the CPU ......................................... To this end.....................................0 Device Overview ..........0 Instruction Set Summary ............................................................. 117 Appendix A: Data Sheet Revision History .. describing minor operational differences from the data sheet and recommended workarounds........................................................................................................ 71 11. http://www.................................................................................................................................................................................... The last character of the literature number is the version number................. 43 8..................................................................................................................................................................0 Development Support ...... 49 9............................................0 DC and AC Characteristics Graphs and Tables ..................................... To determine if an errata sheet exists for a particular device.microchip............. 85 13.................................................................................................................................................... 128 Appendix D: Migrating from other PIC® Devices .................com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150................... please register at our Worldwide Web site at: http://www...................................................................... 127 Appendix C: Device Migrations ........................................................................ DS41190G-page 5 .......................0 Comparator Module ..................com • Your local Microchip sales office (see last page) When contacting a sales office... we will publish an errata sheet............................................................................................................... 133 Reader Response ............... If you have any questions or comments regarding this publication....................................................................  2010 Microchip Technology Inc..............................................g....................................................... 133 Systems Information and Upgrade Hot Line ........... 127 Appendix B: Device Differences ......................................... As device/documentation issues become known to us...........................................................................................................................0 Data EEPROM Memory .................................0 Timer1 Module with Gate Control ............................................................................................................. 21 4..................... The errata will specify the revision of silicon and revision of document to which it applies...........................................PIC12F629/675 Table of Contents 1................................0 Memory Organization................ please contact the Marketing Communications Department via E-mail at docerrors@microchip........... 53 10.................................................................................................................................................................... 107 14.... We welcome your feedback................................................................................................ 129 On-Line Support ........... Customer Notification System Register on our web site at www....... 128 Index ................ 134 Product Identification System .................... please check with one of the following: • Microchip’s Worldwide Web site......................................... 135 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products.................. (e......................................................................................... Most Current Data Sheet To obtain the most up-to-date version of this data sheet....................................0 Timer0 Module .......... DS30000A is version A of document DS30000)........................................................................................................... 81 12........... Errata An errata sheet......................... please specify which device............................................ 37 7..............................0 Packaging Information ......................................................................................................com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.....................................................................................................................0 GPIO Port ...............................

.PIC12F629/675 NOTES: DS41190G-page 6  2010 Microchip Technology Inc.

except the PIC12F675 has a 10-bit A/D converter. Additional information may be found in the PIC® Mid-Range Reference Manual (DS33023). FIGURE 1-1: PIC12F629/675 BLOCK DIAGRAM 13 Flash Program Memory 1K x 14 Program Counter Data Bus 8 GP0/AN0/CIN+ GP1/AN1/CIN-/VREF GP2/AN2/T0CKI/INT/COUT GP3/MCLR/VPP GP4/AN3/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN 8-Level Stack (13-bit) Program Bus RAM File Registers 64 x 8 9 RAM Addr(1) 14 Instruction Reg Direct Addr 7 Addr MUX 8 Indirect Addr FSR Reg Internal 4 MHz Oscillator Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT VDD. Figure 1-1 shows a block diagram of the PIC12F629/ 675 devices. and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.PIC12F629/675 1.  2010 Microchip Technology Inc. The PIC12F629 and PIC12F675 devices are covered by this Data Sheet. DS41190G-page 7 .CIN+ COUT VREF AN0 AN1 AN2 AN3 Note 1: Higher order bits are from STATUS register. MLF-S and DFN packages. Table 1-1 shows the pinout description. The Reference Manual should be considered a complementary document to this Data Sheet.0 DEVICE OVERVIEW This document contains device specific information for the PIC12F629/675. which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. They come in 8-pin PDIP. VSS 8 3 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Detect 8 W Reg STATUS Reg MUX ALU T1G T1CKI Timer0 T0CKI Timer1 Analog to Digital Converter (PIC12F675 only) Analog Comparator and reference EEDATA 8 128 bytes DATA EEPROM EEADDR CIN. They are identical. SOIC.

.PIC12F629/675 TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION Function GP0 AN0 CIN+ ICSPDAT GP1 AN1 CINVREF ICSPCLK GP2 AN2 T0CKI INT COUT GP3/MCLR/VPP GP3 MCLR VPP GP4/AN3/T1G/OSC2/ CLKOUT GP4 AN3 T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 Input Type TTL AN AN TTL TTL AN AN AN ST ST AN ST ST CMOS TTL ST HV TTL AN ST XTAL CMOS TTL CMOS CMOS Output Type CMOS Description Bidirectional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 0 input Comparator input Serial programming I/O Bidirectional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 1 input Comparator input External voltage reference Serial programming clock Bidirectional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 2 input TMR0 clock input External interrupt Comparator output Input port w/ interrupt-on-change Master Clear Programming voltage Bidirectional I/O w/ programmable pull-up and interrupt-on-change A/D Channel 3 input TMR1 gate Crystal/resonator FOSC/4 output Bidirectional I/O w/ programmable pull-up and interrupt-on-change TMR1 clock Crystal/resonator External clock input/RC oscillator connection Ground reference Positive supply Name GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/VREF/ ICSPCLK CMOS CMOS GP2/AN2/T0CKI/INT/COUT CMOS VSS VDD Legend: T1CKI ST OSC1 XTAL CLKIN ST VSS Power VDD Power Shade = PIC12F675 only TTL = TTL input buffer. ST = Schmitt Trigger input buffer DS41190G-page 8  2010 Microchip Technology Inc.

• RP0 = 0 Bank 0 is selected • RP0 = 1 Bank 1 is selected Note: The IRP and RP1 bits STATUS<7:6> are reserved and should always be maintained as ‘0’s.PIC12F629/675 2. implemented as static RAM and are mapped across both banks.4 “Indirect Addressing. Only the first 1K x 14 (0000h-03FFh) for the PIC12F629/675 devices is physically implemented.2 Data Memory Organization The PIC12F629/675 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space.0 2.2. either directly or indirectly. FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE DSTEMP/675 PC<12:0> 13 CALL. which contain the General Purpose Registers and the Special Function Registers. Register locations 20h-5Fh are General Purpose Registers.1 MEMORY ORGANIZATION Program Memory Organization 2. through the File Select Register FSR (see Section 2. DS41190G-page 9 .1 GENERAL PURPOSE REGISTER FILE Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h The register file is organized as 64 x 8 in the PIC12F629/675 devices. Interrupt Vector On-chip Program Memory 0004 0005 03FFh 0400h 1FFFh  2010 Microchip Technology Inc. RETURN RETFIE. RP0 (STATUS<5>) is the bank select bit. The Special Function Registers are located in the first 32 locations of each bank. Each register is accessed. The data memory (see Figure 2-2) is partitioned into two banks. INDF and FSR Registers”). The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). All other RAM is unimplemented and returns ‘0’ when read. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space. RETLW 2.

Not a physical register. The special registers can be classified into two sets: core and peripheral. PIC12F675 only. . DATA MEMORY MAP OF THE PIC12F629/675 File Address File Address Indirect addr.(1) TMR0 PCL STATUS FSR GPIO 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h PCLATH INTCON PIR1 TMR1L TMR1H T1CON PCLATH INTCON PIE1 PCON OSCCAL WPU IOC CMCON ADRESH(2) ADCON0(2) VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL(2) ANSEL(2) General Purpose Registers 64 Bytes accesses 20h-5Fh 5Fh 60h DFh E0h 7Fh Bank 0 Bank 1 FFh 1: 2: Unimplemented data memory locations. The Special Function Registers associated with the “core” are described in this section. DS41190G-page 10  2010 Microchip Technology Inc.(1) OPTION_REG PCL STATUS FSR TRISIO 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h Indirect addr. read as ‘0’.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2: The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. Those related to the operation of the peripheral features are described in the section of that peripheral feature.2.PIC12F629/675 2.

DS41190G-page 11 . 3: PIC12F675 only.PIC12F629/675 TABLE 2-1: Address Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF(1) TMR0 PCL STATUS FSR GPIO — — — — PCLATH INTCON PIR1 — TMR1L TMR1H T1CON — — — — — — — — CMCON — — — — ADRESH(3) ADCON0(3) Addressing this Location uses Contents of FSR to Address Data Memory Timer0 Module’s Register Program Counter’s (PC) Least Significant Byte IRP(2) — Unimplemented Unimplemented Unimplemented Unimplemented — GIE EEIF — PEIE ADIF — T0IE — Write Buffer for Upper 5 bits of Program Counter INTE — GPIE CMIF T0IF — INTF — GPIF TMR1IF RP1(2) — RP0 GPIO5 TO GPIO4 PD GPIO3 Z GPIO2 DC GPIO1 C GPIO0 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx — — — — ---0 0000 0000 0000 00-. x = unknown. u = unchanged. 2: These bits are reserved and should always be maintained as ‘0’.61 SPECIAL FUNCTION REGISTERS SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR.  2010 Microchip Technology Inc. q = value depends on condition.0--0 — xxxx xxxx xxxx xxxx TMR1CS TMR1ON -000 0000 — — — — — — — — — 20.61 29 19 14 20 21 — — — — 19 15 17 — 32 32 35 — — — — — — — — 38 — — — — 44 45.0000 Legend: — = unimplemented locations read as ‘0’. shaded = unimplemented Note 1: This is not a physical register. BOD Page Indirect Data Memory Address Pointer Unimplemented Holding Register for the Least Significant Byte of the 16-bit Timer1 Holding Register for the Most Significant Byte of the 16-bit Timer1 — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented — COUT CINV CIS CM2 CM1 CM0 -0-0 0000 — — — — xxxx xxxx Unimplemented Unimplemented Unimplemented Unimplemented Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-.

2: These bits are reserved and should always be maintained as ‘0’. q = value depends on condition. x = unknown.61 14.PIC12F629/675 TABLE 2-1: Address Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh WPU IOC — — VRCON EEDATA EEADR EECON1 EECON2(1) ADRESL(3) ANSEL(3) PCON — OSCCAL — — — — INDF(1) OPTION_REG PCL STATUS FSR TRISIO — — — — PCLATH INTCON PIE1 — Addressing this Location uses Contents of FSR to Address Data Memory GPPU (2) SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR.--0x — 1000 00-— — — — --11 -111 --00 0000 — — Unimplemented VRR — VR3 VR2 VR1 VR0 0-0. 3: PIC12F675 only.0--0 — ---.61 INTEDG (2) T0CS RP0 T0SE TO PSA PD PS2 Z Program Counter’s (PC) Least Significant Byte IRP RP1 0001 1xxx xxxx xxxx Indirect Data Memory Address Pointer — Unimplemented Unimplemented Unimplemented Unimplemented — GIE EEIE — Unimplemented CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — Unimplemented Unimplemented Unimplemented Unimplemented — — Unimplemented Unimplemented VREN — — — — — WPU5 IOC5 WPU4 IOC4 — IOC3 WPU2 IOC2 WPU1 IOC1 WPU0 IOC0 — PEIE ADIE — — T0IE — — Write Buffer for Upper 5 bits of Program Counter INTE — — GPIE CMIE — T0IF — — INTF — POR GPIF TMR1IE BOD — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 — — — — ---0 0000 0000 0000 00-.31 19 14 20 21 — — — — 19 15 16 — 18 — 18 — — — — 21 23 — — 42 49 49 50 50 44 46. BOD Page 0000 0000 PS1 DC PS0 C 1111 1111 0000 0000 20. u = unchanged. DS41190G-page 12  2010 Microchip Technology Inc.x000 ---.0000 0000 0000 -000 0000 Data EEPROM Data Register Data EEPROM Address Register — — — WRERR WREN WR RD ---.---xxxx xxxx EEPROM Control Register 2 Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 Legend: — = unimplemented locations read as ‘0’. shaded = unimplemented Note 1: This is not a physical register. .

respectively. SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For borrow the polarity is reversed. SUBLW.1 STATUS Register The STATUS register. CLRWDT instruction. CLRF STATUS will clear the upper three bits and set the Z bit. since this may affect upward compatibility with future products. that only BCF. or SLEEP instruction 0 = A WDT Time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF. Use of these bits is not recommended. For example. SWAPF and MOVWF instructions are used to alter the STATUS register. bit 4 bit 3 bit 2 bit 1 bit 0 Note:  2010 Microchip Technology Inc.2. See the SUBLW and SUBWF instructions for examples. ADDLW. the result of an instruction with the STATUS register as destination may be different than intended. the polarity is reversed. BSF. RLF) instructions. DC or C bits. like any other register.SUBLW. REGISTER 2-1: Reserved IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 STATUS: STATUS REGISTER (ADDRESS: 03h OR 83h) Reserved RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. in subtraction. For other instructions not affecting any Status bits. A subtraction is executed by adding the two’s complement of the second operand. These bits are set or cleared according to the device logic.PIC12F629/675 2.7Fh) 1 = Bank 1 (80h . 2: The C and DC bits operate as a Borrow and Digit Borrow out bit. It is recommended. then the write to these three bits is disabled. If the STATUS register is the destination for an instruction that affects the Z. shown in Register 2-1. This leaves the STATUS register as 000u u1uu (where u = unchanged). For rotate (RRF.2. this bit is loaded with either the high or low order bit of the source register. 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF.SUBWF instructions) For borrow. contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction. Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC12F629/675 and should be maintained as clear. the TO and PD bits are not writable. DS41190G-page 13 . because these instructions do not affect any Status bits. therefore. see the “Instruction Set Summary”. ADDLW.FFh) TO: Time-out bit 1 = After power-up. Therefore. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IRP: This bit is reserved and should be maintained as ‘0’ RP1: This bit is reserved and should be maintained as ‘0’ RP0: Register Bank Select bit (used for direct addressing) 0 = Bank 0 (00h . Furthermore.

2.PIC12F629/675 2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for TMR0. . See Section 4. which contains various control bits to configure: • • • • TMR0/WDT prescaler External GP2/INT interrupt TMR0 Weak pull-ups on GPIO REGISTER 2-2: R/W-1 GPPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 OPTION_REG: OPTION REGISTER (ADDRESS: 81h) R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 6 bit 5 bit 4 bit 3 bit 2-0 DS41190G-page 14  2010 Microchip Technology Inc.2. The OPTION register is a readable and writable register.4 “Prescaler”. assign the prescaler to the WDT by setting PSA bit to ‘1’ (OPTION<3>).

DS41190G-page 15 . read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt GPIE: Port Change Interrupt Enable bit(1) 1 = Enables the GPIO port change interrupt 0 = Disables the GPIO port change interrupt T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur GPIF: Port Change Interrupt Flag bit 1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software) 0 = None of the GP5:GP0 pins have changed state IOC register must also be enabled to enable an interrupt-on-change. which contains the various enable and flag bits for TMR0 register overflow.3 INTCON Register Note: Interrupt flag bits are set when an interrupt condition occurs. GIE (INTCON<7>). The INTCON register is a readable and writable register. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2:  2010 Microchip Technology Inc. GPIO port change and external GP2/INT pin interrupts. TIMER0 is unchanged on Reset and should be initialized before clearing T0IF bit.PIC12F629/675 2. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. T0IF bit is set when TIMER0 rolls over. regardless of the state of its corresponding enable bit or the global enable bit.2.2. REGISTER 2-3: R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh) R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 GPIE R/W-0 T0IF R/W-0 INTF R/W-0 GPIF bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.

PIC12F629/675 2. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only) 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt Unimplemented: Read as ‘0’ CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt Unimplemented: Read as ‘0’ TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt bit 6 bit 5-4 bit 3 bit 2-1 bit 0 DS41190G-page 16  2010 Microchip Technology Inc. The PIE1 register contains the interrupt enable bits.2. .4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. as shown in Register 2-4.2. REGISTER 2-4: R/W-0 EEIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 ADIE U-0 — U-0 — R/W-0 CMIE U-0 — U-0 — R/W-0 TMR1IE bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.

2. GIE (INTCON<7>). DS41190G-page 17 . User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits. REGISTER 2-5: R/W-0 EEIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch) R/W-0 ADIF U-0 — U-0 — R/W-0 CMIF U-0 — U-0 — R/W-0 TMR1IF bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. regardless of the state of its corresponding enable bit or the global enable bit.2.PIC12F629/675 2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt condition occurs. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only) 1 = The A/D conversion is complete (must be cleared in software) 0 = The A/D conversion is not complete Unimplemented: Read as ‘0’ CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as ‘0’ TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow bit 6 bit 5-4 bit 3 bit 2-1 bit 0  2010 Microchip Technology Inc. as shown in Register 2-5.

6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset The PCON Register bits are shown in Register 2-6. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CAL5:CAL0: 6-bit Signed Oscillator Calibration bits 111111 = Maximum frequency 100000 = Center frequency 000000 = Minimum frequency Unimplemented: Read as ‘0’ bit 1-0 DS41190G-page 18  2010 Microchip Technology Inc.2.PIC12F629/675 2. It contains 6 bits to adjust the frequency up or down to achieve 4 MHz.2.7 OSCCAL Register The Oscillator Calibration register (OSCCAL) is used to calibrate the internal 4 MHz oscillator.2. . REGISTER 2-6: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 PCON: POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 POR R/W-x BOD bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. REGISTER 2-7: R/W-1 CAL5 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 OSCCAL: OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h) R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 U-0 — U-0 — bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.2. The OSCCAL register bits are shown in Register 2-7. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOD: Brown-out Detect Status bit 1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs) bit 0 2.

The PC is PUSHed onto the stack when a CALL instruction is executed. the PC is cleared.PIC12F629/675 2.3. RETLW or a RETFIE instruction execution. The PIC12F629/675 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1).3 PCL and PCLATH 2. The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3>  PCH). Figure 2-3 shows the two situations for the loading of the PC.2 STACK The Program Counter (PC) is 13-bits wide. The tenth push overwrites the second push (and so on). RETLW and RETFIE instructions. The stack is POPed in the event of a RETURN. The low byte comes from the PCL register. 2: There are no instructions/mnemonics called PUSH or POP. or the vectoring to an interrupt address. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the PC (ADDWF PCL).3.  2010 Microchip Technology Inc. PCLATH is not affected by a PUSH or POP operation. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0>  PCH). On any Reset. the ninth push overwrites the value that was stored from the first push. Note 1: There are no Status bits to indicate Stack Overflow or Stack Underflow conditions. The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. CALL 2. which is a readable and writable register. When performing a table read using a computed GOTO method. “Implementing a Table Read” (AN556). Refer to the Application Note. These are actions that occur from the execution of the CALL. or an interrupt causes a branch. FIGURE 2-3: PCH 12 PC 5 8 7 LOADING OF PC IN DIFFERENT SITUATIONS PCL 0 Instruction with PCL as Destination ALU result PCLATH<4:0> 8 PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO. The stack operates as a circular buffer. RETURN. care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). This means that after the stack has been PUSHed eight times. DS41190G-page 19 .

The INDF register is not a physical register. Note 1: The RP1 and IRP bits are reserved.4 NEXT . Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR).inc pointer . Indirect addressing is possible by using the INDF register. always maintain these bits clear. Bank 1 Bank 2 Bank 3 1FFh DS41190G-page 20  2010 Microchip Technology Inc.PIC12F629/675 2. Addressing the INDF register will cause indirect addressing. as shown in Figure 2-2. EXAMPLE 2-1: MOVLW MOVWF CLRF INCF BTFSS GOTO INDIRECT ADDRESSING 0x20 FSR INDF FSR FSR. .initialize pointer . An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>).clear INDF register . Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected).no clear next .4 Indirect Addressing.yes continue NEXT CONTINUE FIGURE 2-2: DIRECT/INDIRECT ADDRESSING PIC12F629/675 Indirect Addressing 0 IRP(1) 7 FSR Register 0 Direct Addressing RP1(1) RP0 6 From Opcode Bank Select Location Select 00 00h 01 10 11 Bank Select 180h Location Select Data Memory Not Used 7Fh Bank 0 For memory map detail see Figure 2-2.to RAM . INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1.all done? .

Set GP<3:2> as inputs .RP0 GPIO 07h CMCON STATUS. has an individually configurable weak internal pull-up.Bank 1 .Bank 0 . except GP3. the associated pin may not be used as a general purpose I/O pin. The user must ensure the bits in the TRISIO 3.e. (DS33023). register are maintained set when using them as analog inputs. whereas writing to it will write to the PORT latch. except GP3. The pull-ups are disabled on a Power-on Reset by the GPPU bit (OPTION<7>).2 Additional Pin Functions Every GPIO pin on the PIC12F629/675 has an interrupt-on-change option and every GPIO pin.RP0 ANSEL 0Ch TRISIO INITIALIZING GPIO .1 WEAK PULL-UP Each of the GPIO pins. some or all of the pins may not be available as general purpose I/O. put the contents of the output latch on the selected pin).PIC12F629/675 3. Reading the GPIO register reads the status of the pins.Init GPIO .Set GP<2:0> to . has a weak pull-up option.and set GP<5:4. which is input-only and its TRISIO bit will always read as ‘1’. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i. All write operations are read-modify-write operations. 3. Depending on which peripherals are enabled. a write to a port implies that the port pins are read. DS41190G-page 21 . REGISTER 3-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 GPIO: GPIO REGISTER (ADDRESS: 05h) U-0 — R/W-x GPIO5 R/W-x GPIO4 R/W-x GPIO3 R/W-x GPIO2 R/W-x GPIO1 R/W-x GPIO0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The ANSEL register is defined for the PIC12F675.1 GPIO and the TRISIO Registers GPIO is an 6-bit wide. this value is modified.0 GPIO PORT There are as many as six general purpose I/O pins available. The TRISIO register controls the direction of the GP pins.. Note: The ANSEL (9Fh) and CMCON (19h) registers (9Fh) must be initialized to configure an analog channel as a digital input.as outputs 3.Digital I/O . Each weak pull-up is automatically turned off when the port pin is configured as an output. when a peripheral is enabled.digital IO . Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i. The exception is GP3.1:0> . Therefore.. put the corresponding output driver in a High-Impedance mode).e. Example 3-1 shows how to initialize GPIO. EXAMPLE 3-1: BCF CLRF MOVLW MOVWF BSF CLRF MOVLW MOVWF STATUS. Pins configured as analog inputs will read ‘0’. The corresponding data direction register is TRISIO. and then written to the PORT data latch. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ GPIO<5:0>: General Purpose I/O pin 1 = Port pin is >VIH 0 = Port pin is <VIL  2010 Microchip Technology Inc. GP3 reads ‘0’ when MCLREN = 1. Note: Additional information on I/O ports may be found in the PIC® Mid-Range Reference Manual. even when they are being used as analog inputs.2. Refer to Register 3-3. bidirectional port. In general. I/O pins configured as analog inputs always read ‘0’. Control bits WPUx enable or disable each pull-up. The next two sections describe these functions.

Note: REGISTER 3-3: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 WPU: WEAK PULL-UP REGISTER (ADDRESS: 95h) U-0 — R/W-1 WPU5 R/W-1 WPU4 U-0 — R/W-1 WPU2 R/W-1 WPU1 R/W-1 WPU0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. . read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 — R/W-1 TRISIO5 R/W-1 TRISIO4 R-1 TRISIO3 R/W-1 TRISIO2 R/W-1 TRISIO1 R/W-1 TRISIO0 bit 0 Unimplemented: Read as ‘0’ TRISIO<5:0>: General Purpose I/O Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output TRISIO<3> always reads ‘1’. bit 3 bit 2-0 Note 1: 2: DS41190G-page 22  2010 Microchip Technology Inc. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ WPU<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Unimplemented: Read as ‘0’ WPU<2:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Global GPPU must be enabled for individual pull-ups to be enabled.PIC12F629/675 REGISTER 3-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.

Refer to Register 3-4. the values are compared with the old value latched on the last read of GPIO. The interrupt-on-change is disabled on a Power-on Reset. can clear the interrupt in the following manner: a) b) Any read or write of GPIO. Clear the flag bit GPIF. Control bits IOC enable or disable the interrupt function for each pin. This will end the mismatch condition. For enabled interrupt-on-change pins. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle). A mismatch condition will continue to set flag bit GPIF. the GP Port Change Interrupt flag bit (GPIF) in the INTCON register. in the Interrupt Service Routine.2 INTERRUPT-ON-CHANGE Each of the GPIO pins is individually configurable as an interrupt-on-change pin. REGISTER 3-4: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h) U-0 — R/W-0 IOC5 R/W-0 IOC4 R/W-0 IOC3 R/W-0 IOC2 R/W-0 IOC1 R/W-0 IOC0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. The ‘mismatch’ outputs of the last read are OR’d together to set.2. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The user. then the GPIF interrupt flag may not get set. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ IOC<5:0>: Interrupt-on-Change GPIO Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.PIC12F629/675 3. This interrupt can wake the device from Sleep. DS41190G-page 23 . Note 1:  2010 Microchip Technology Inc.

3. The GP1 pin is configurable to function as one of the following: • • • • as a general purpose I/O an analog input for the A/D (PIC12F675 only) an analog input to the comparator a voltage reference input for the A/D (PIC12F675 only) D WR IOC RD IOC CK Q Q Q D EN Q D EN Interrupt-on-Change RD PORT To Comparator To A/D Converter DS41190G-page 24  2010 Microchip Technology Inc.1 GP0/AN0/CIN+ Figure 3-1 shows the diagram for this pin.3.2 GP1/AN1/CIN-/VREF WR TRISIO RD TRISIO RD PORT I/O pin D CK Q Q Analog Input Mode VSS Figure 3-1 shows the diagram for this pin. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D. refer to the appropriate section in this Data Sheet.3 Pin Descriptions and Diagrams FIGURE 3-1: Data Bus WR WPU RD WPU Each GPIO pin is multiplexed with other functions.PIC12F629/675 3. BLOCK DIAGRAM OF GP0 AND GP1 PINS Q Q GPPU Analog Input Mode VDD Weak D CK 3. The GP0 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D (PIC12F675 only) • an analog input to the comparator D WR PORT CK Q Q VDD 3. .

DS41190G-page 25 . The GP2 pin is configurable to function as one of the following: • • • • • a general purpose I/O an analog input for the A/D (PIC12F675 only) the clock input for TMR0 an external edge triggered interrupt a digital output from the comparator Figure 3-3 shows the diagram for this pin.3.PIC12F629/675 3.3.4 GP3/MCLR/VPP Figure 3-2 shows the diagram for this pin.3 GP2/AN2/T0CKI/INT/COUT 3. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: Data Bus Reset BLOCK DIAGRAM OF GP3 MCLRE VSS MCLRE VSS I/O pin FIGURE 3-2: Data Bus WR WPU RD WPU D CK Q Q BLOCK DIAGRAM OF GP2 Analog Input Mode VDD Weak GPPU COUT Enable Analog Input Mode WR IOC RD IOC RD TRISIO RD PORT D CK Q Q Q D EN D WR PORT CK Q Q COUT 1 0 VDD Q D EN Interrupt-on-Change I/O pin RD PORT D WR TRISIO RD TRISIO RD PORT D WR IOC RD IOC CK CK Q Q Analog Input Mode VSS Q Q Q D EN Q D EN Interrupt-on-Change RD PORT To TMR0 To INT To A/D Converter  2010 Microchip Technology Inc.

PIC12F629/675 3. 2: With CLKOUT option. The GP4 pin is configurable to function as one of the following: • • • • • a general purpose I/O an analog input for the A/D (PIC12F675 only) a TMR1 gate input a crystal/resonator connection a clock output Figure 3-5 shows the diagram for this pin. HS. LP.3. . the Schmitt Trigger is by-passed.6 GP5/T1CKI/OSC1/CLKIN Figure 3-4 shows the diagram for this pin.3. The GP5 pin is configurable to function as one of the following: • • • • a general purpose I/O a TMR1 clock input a crystal/resonator connection a clock input FIGURE 3-5: BLOCK DIAGRAM OF GP5 INTOSC Mode FIGURE 3-4: BLOCK DIAGRAM OF GP4 Analog Input Mode CLK Modes(1) VDD Weak GPPU Oscillator Circuit VDD WR PORT I/O pin WR TRISIO RD TRISIO RD PORT D WR IOC Q D EN RD IOC CK Q Q Data Bus WR WPU RD WPU TMR1LPEN(1) D CK Q Q GPPU Oscillator Circuit OSC2 D CK Q Q I/O pin D CK Q Q INTOSC Mode (2) VSS VDD VDD Weak Data Bus WR WPU RD WPU D CK Q Q OSC1 CLKOUT Enable D WR PORT CK Q Q CLKOUT Enable D WR TRISIO RD TRISIO RD PORT D WR IOC RD IOC CK Q Q CK Q Q FOSC/4 1 0 VSS INTOSC/ RC/EC(2) CLKOUT Enable Analog Input Mode Q D EN Q D EN Q D EN Interrupt-on-Change Interrupt-on-Change RD PORT RD PORT To TMR1 or CLKGEN To TMR1 T1G To A/D Converter Note 1: CLK modes are XT. LPTMR1 and CLKOUT Enable.5 GP4/AN3/T1G/OSC2/CLKOUT 3. DS41190G-page 26  2010 Microchip Technology Inc. Note 1: Timer1 LP Oscillator enabled 2: When using Timer1 with LP oscillator.

= unimplemented locations read as ‘0’.  2010 Microchip Technology Inc. . DS41190G-page 27 . u = unchanged.PIC12F629/675 TABLE 3-2: Address 05h 0Bh/8Bh 19h 81h 85h 95h 96h 9Fh SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Name Bit 7 — GIE — GPPU — — — — Bit 6 — PEIE COUT INTEDG — — — ADCS2 Bit 5 GP5 T0IE — T0CS TRISIO5 WPU5 IOC5 ADCS1 Bit 4 GP4 INTE CINV T0SE TRISIO4 WPU4 IOC4 ADCS0 Bit 3 GP3 GPIE CIS PSA TRISIO3 — IOC3 ANS3 Bit 2 GP2 T0IF CM2 PS2 TRISIO2 WPU2 IOC2 ANS2 Bit 1 GP1 INTF CM1 PS1 TRISIO1 WPU1 IOC1 ANS1 Bit 0 GP0 GPIF CM0 PS0 TRISIO0 WPU0 IOC0 ANS0 Value on POR. Shaded cells are not used by GPIO. BOD --xx xxxx 0000 0000 -0-0 0000 1111 1111 --11 1111 --11 -111 --00 0000 -000 1111 Value on all other Resets --uu uuuu 0000 000u -0-0 0000 1111 1111 --11 1111 --11 -111 --00 0000 -000 1111 GPIO INTCON CMCON OPTION_REG TRISIO WPU IOC ANSEL Legend: x = unknown.

.PIC12F629/675 NOTES: DS41190G-page 28  2010 Microchip Technology Inc.

Additional information on these requirements is available in the PIC® Mid-Range Reference Manual. PS0-PS2 are bits in the OPTION register. If TMR0 is written. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). A Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION_REG<4>).  2010 Microchip Technology Inc. The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module Interrupt Service Routine before reenabling this interrupt. the Timer0 module will increment every instruction cycle (without prescaler). The user can work around this by writing an adjusted value to the TMR0 register. T0CS.PS2 Watchdog Timer 1 0 PSA WDT Time-out WDTE Note 1: T0SE. Figure 4-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. This overflow sets the T0IF bit. the increment is inhibited for the following two instruction cycles. In Timer mode.0 TIMER0 MODULE The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting the T0CS bit (OPTION_REG<5>).2 Timer0 Interrupt 4. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shutoff during Sleep. 4. PSA. Note: Additional information on the Timer0 module is available in the PIC® Mid-Range Reference Manual. Clearing the T0SE bit selects the rising edge. the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI.PIC12F629/675 4.1 Timer0 Operation Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>). In this mode. (DS33023). FIGURE 4-1: CLKOUT (= FOSC/4) BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus 0 1 1 T0CKI pin T0SE T0CS SYNC 2 Cycles 8 TMR0 Set Flag bit T0IF on Overflow 0 8-bit Prescaler 0 PSA 1 PSA 8 PS0 . Note: Counter mode has specific external clock requirements. DS41190G-page 29 . (DS33023).

is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.3 Using Timer0 with an External Clock a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). The ANSEL register is defined for the PIC12F675. Note: The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input.PIC12F629/675 4. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CK pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 6 bit 5 bit 4 bit 3 bit 2-0 DS41190G-page 30  2010 Microchip Technology Inc. Pins configured as analog inputs will read ‘0’. The synchronization of T0CKI. the external clock input is the same as the prescaler output. with the internal phase clocks. When no prescaler is used. . Refer to the electrical specification of the desired device. it is necessary for T0CKI to be high for at least 2TOSC (and REGISTER 4-1: R/W-1 GPPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 OPTION_REG: OPTION REGISTER (ADDRESS: 81h) R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Therefore.

. prescale.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.g.RP0 . The prescaler is not readable or writable.RP0 .Clear WDT .) will clear the prescaler. use the sequence shown in Example 4-2. read as ‘0’. EXAMPLE 4-2: CLRWDT BSF MOVLW CHANGING PRESCALER (WDTTIMER0) .Set postscaler to MOVWF OPTION_REG . The prescaler assignment is controlled in software by the control bit PSA (OPTION_REG<3>). STATUS. Clearing the PSA bit will assign the prescaler to Timer0.Required if desired MOVWF OPTION_REG .Bank 0 4. This precaution must be taken even if the WDT is disabled. PS2:PS0 is CLRWDT . the following instruction sequence (Example 41) must be executed when changing the prescaler assignment from Timer0 to WDT.  2010 Microchip Technology Inc.. CHANGING PRESCALER (TIMER0WDT) . 000 or 001 . BOD xxxx xxxx INTE T0SE GPIE PSA T0IF PS2 INTF PS1 GPIF PS0 0000 0000 1111 1111 Value on all other Resets uuuu uuuu 0000 000u 1111 1111 --11 1111 TMR0 INTCON OPTION_REG TRISIO Timer0 Module Register GIE GPPU — PEIE INTEDG — T0IE T0CS TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 Legend: — = Unimplemented locations. For simplicity. it can be changed “on the fly” during program execution). prescaler . MOVWF 1.Select TMR0. Shaded cells are not used by the Timer0 module. u = unchanged.RP0 MOVWF BCF b’xxxx0xxx’ . When assigned to the Timer0 module. To avoid an unintended device Reset. desired WDT rate BCF STATUS.Bank 0 TABLE 4-1: Address 01h 0Bh/8Bh 81h 85h REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR.Bank 0 . a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. DS41190G-page 31 ..4.RP0 CLRWDT CLRF TMR0 BSF STATUS.Clear TMR0 and . x = unknown..Clear WDT and . CLRF 1.PIC12F629/675 4. or as a postscaler for the Watchdog Timer. Prescale values are selectable via the PS2:PS0 bits (OPTION_REG<2:0>). this counter will be referred to as “prescaler” throughout this Data Sheet. and . postscaler . x.RP0 MOVLW b’00101111’ . BSF 1.etc.4 Prescaler EXAMPLE 4-1: An 8-bit counter is available as a prescaler for the Timer0 module. all instructions writing to the TMR0 register (e. To change prescaler from the WDT to the TMR0 module.Bank 1 BCF STATUS.. clock source OPTION_REG .. When assigned to WDT.e. MOVLW b’00101xxx’ .Bank 1 STATUS.

1.PIC12F629/675 5. Timer1 has the following features: • • • • • • • • 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation Interrupt on overflow from FFFFh to 0000h Wake-up upon overflow (Asynchronous mode) Optional external enable input (T1G) Optional LP oscillator FIGURE 5-1: TIMER1 BLOCK DIAGRAM TMR1ON TMR1GE TMR1ON TMR1GE T1G Set Flag bit TMR1IF on Overflow TMR1 TMR1H TMR1L 0 1 Synchronized Clock Input LP Oscillator OSC1 FOSC/4 Internal Clock 1 0 TMR1CS T1SYNC Prescaler 1. . 8 2 T1CKPS<1:0> Synchronize Detect Sleep Input OSC2 INTOSC w/o CLKOUT T1OSCEN LP DS41190G-page 32  2010 Microchip Technology Inc. 4.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 Control register (T1CON). shown in Register 5. Note: Additional information on timer modules is available in the PIC® Mid-Range Reference Manual. 2. Figure 5-1 shows the basic block diagram of the Timer1 module. (DS33023). is used to enable/disable Timer1 and select the various features of the Timer1 module. The PIC12F629/675 devices have a 16-bit timer.

5. Timer1 is incremented on every instruction cycle. The T1CKPS bits (T1CON<5:4>) control the prescale counter. In counter and timer modules. In addition. however. Timer1 can use the LP oscillator as a clock source. a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1. The prescale counter is not directly readable or writable. the Timer1 interrupt flag bit (PIR1<0>) is set. If an external clock oscillator is needed (and the microcontroller is using the INTOSC w/o CLKOUT). The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. a falling edge must be registered by the counter prior to the first incrementing rising edge. DS41190G-page 33 . The interrupt is cleared by clearing the TMR1IF in the Interrupt Service Routine. the counter/timer clock can be gated by the T1G input. FIGURE 5-2: T1CKI = 1 when TMR1 Enabled TIMER1 INCREMENTING EDGE T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. Note: In Counter mode. or 8 divisions of the clock input. the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter mode. To enable the interrupt on rollover.1 Timer1 Modes of Operation 5. Timer1 is incremented on the rising edge of the external clock input T1CKI. Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. 2: In Counter mode. the prescaler counter is cleared upon a write to TMR1H or TMR1L. 4. you must set these bits: • Timer1 interrupt Enable bit (PIE1<0>) • PEIE bit (INTCON<6>) • GIE bit (INTCON<7>).PIC12F629/675 5.  2010 Microchip Technology Inc.2 Timer1 Interrupt Timer1 can operate in one of three modes: • 16-bit timer with prescaler • 16-bit synchronous counter • 16-bit asynchronous counter In Timer mode. When Timer1 rolls over.

Timer1 uses the internal clock. .PIC12F629/675 REGISTER 5-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1OSO/T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS41190G-page 34  2010 Microchip Technology Inc. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h) R/W-0 TMR1GE R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 Unimplemented: Read as ‘0’ TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if T1G pin is low 0 = Timer1 is on T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored.

poses certain problems. since the timer may overflow between the reads. Timer1 can use this mode only when the system clock is derived from the internal oscillator. . Shaded cells are not used by the Timer1 module. GP4 and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read ‘1’. the external clock input is not synchronized. Note: The oscillator requires a start-up and stabilization time before use. DS41190G-page 35 . which will wake-up the processor. The timer will continue to run during Sleep and can generate an interrupt on overflow. 5. For writes. A write contention may occur by writing to the timer registers. an external crystal or clock source can be used to increment the counter. The timer continues to increment asynchronous to the internal phase clocks. However. u = unchanged. Examples 12-2 and 12-3 in the PIC® Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode. It will continue to run during Sleep. In this mode.  2010 Microchip Technology Inc. The ANSEL register is defined for the PIC12F675.0--0 Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — EEIE ADIE — — CMIE — — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu TMR1IE 00-. TABLE 5-1: Address 0Bh/8Bh 0Ch 0Eh 0Fh 10h 8Ch Name INTCON PIR1 TMR1L TMR1H T1CON PIE1 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 GIE EEIF Bit 6 PEIE ADIF Bit 5 T0IE — Bit 4 INTE — Bit 3 GPIE CMIF Bit 2 T0IF — Bit 1 INTF — Bit 0 GPIF Value on POR.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”).= unimplemented. Thus.0--0 Legend: x = unknown. Table 9-2 shows the capacitor selection for the Timer1 oscillator. This may produce an unpredictable value in the timer register. the user must provide a software time delay to ensure proper oscillator start-up. while the register is incrementing. Reading the 16-bit value requires some care. BOD Value on all other Resets 0000 0000 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1IF 00-. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE 5. Note: The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. will ensure a valid read (taken care of in hardware). To setup the timer to wake the device: • Timer1 must be on (T1CON<0>) • TMR1IE bit (PIE1<0>) must be set • PEIE bit (INTCON<6>) must be set The device will wake-up on an overflow. special precautions in software are needed to read/write the timer (Section 5. If control bit T1SYNC (T1CON<2>) is set.1 Reading TMR1H or TMR1L. TRISIO4 and TRISIO5 are set.4. while the timer is running from an external asynchronous clock.4 Timer1 Operation in Asynchronous Counter Mode 5. While enabled. Thus. If the GIE bit (INTCON<7>) is set. the device will wake-up and jump to the Interrupt Service Routine on an overflow.4. The Timer1 oscillator is shared with the system LP oscillator. It is enabled by setting control bit T1OSCEN (T1CON<3>). the user should keep in mind that reading the 16-bit timer in two 8-bit values itself.6 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. However.0--0 00-. It is primarily intended for a 32 kHz crystal. The oscillator is a low-power oscillator rated up to 37 kHz.0--0 00-. it is recommended that the user simply stop the timer and write the desired values. As with the system LP oscillator. T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.PIC12F629/675 5.5 Timer1 Oscillator A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output). Pins configured as analog inputs will read ‘0’. read as ‘0’.

PIC12F629/675 NOTES: DS41190G-page 36  2010 Microchip Technology Inc. .

connects to CINCM2:CM0: Comparator Mode bits Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings bit 5 bit 4 bit 3 bit 2-0  2010 Microchip Technology Inc. shown in Register 6-1. GP2 can be configured as the comparator output. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CINV = 1: 1 = VIN+ < VIN0 = VIN+ > VINUnimplemented: Read as ‘0’ CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110 or 101: 1 = VIN. In addition. DS41190G-page 37 . The inputs to the comparator are multiplexed with the GP0 and GP1 pins. REGISTER 6-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 CMCON: COMPARATOR CONTROL REGISTER (ADDRESS: 19h) R-0 COUT U-0 — R/W-0 CINV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.PIC12F629/675 6. There is an on-chip Comparator Voltage Reference that can also be applied to an input of the comparator.0 COMPARATOR MODULE The PIC12F629/675 devices have one analog comparator.connects to CIN+ 0 = VIN. contains the bits to control the comparator. The Comparator Control Register (CMCON).

along with the relationship between the analog input levels and the digital output.pins as analog inputs.> VIN+ VIN.1 Comparator Operation TABLE 6-1: A single comparator is shown in Figure 6-1. . Clearing CINV results in a non-inverted output.< VIN+ VIN. INPUT CONDITIONS CINV 0 0 1 1 COUT 0 1 1 0 Input Conditions VIN.> VIN+ VIN.PIC12F629/675 6.< VIN+ FIGURE 6-1: VIN+ VIN- SINGLE COMPARATOR + – Output The polarity of the comparator output can be inverted by setting the CINV bit (CMCON<4>). the output of the comparator is a digital low level. the output of the comparator is a digital high level. VINVIN+ Output Note: CINV bit (CMCON<4>) is clear. Note: To use CIN+ and CIN. When the analog input at VIN+ is greater than the analog input VIN-. the appropriate bits must be programmed in the CMCON (19h) register. DS41190G-page 38  2010 Microchip Technology Inc. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 6-1. When the analog input at VIN+ is less than the analog input VIN-. The shaded areas of the output of the comparator in Figure 6-1 represent the uncertainty due to input offsets and response time. OUTPUT STATE VS.

The TRISIO register controls the data direction of the comparator pins for each mode.0 “Electrical Specifications”. Otherwise. Refer to the specifications in Section 12. shown in Register 6-1. FIGURE 6-2: CM2:CM0 = 000 GP1/CINGP0/CIN+ GP2/COUT A A D COMPARATOR I/O OPERATING MODES Comparator Off (Lowest power) CM2:CM0 = 111 GP1/CINOff (Read as ‘0’) GP0/CIN+ GP2/COUT D D D Off (Read as ‘0’) Comparator Reset (POR Default Value . ports always reads ‘0’ D = Digital Input CIS = Comparator Input Switch (CMCON<3>)  2010 Microchip Technology Inc.PIC12F629/675 6.low power) Comparator without Output CM2:CM0 = 010 GP1/CINGP0/CIN+ GP2/COUT A A D COUT Comparator w/o Output and with Internal Reference CM2:CM0 = 100 GP1/CINGP0/CIN+ GP2/COUT A D D From CVREF Module COUT Comparator with Output and Internal Reference CM2:CM0 = 011 GP1/CINGP0/CIN+ GP2/COUT A D D From CVREF Module COUT Multiplexed Input with Internal Reference and Output CM2:CM0 = 101 GP1/CINGP0/CIN+ GP2/COUT A A D From CVREF Module CIS = 0 CIS = 1 COUT Comparator with Output CM2:CM0 = 001 GP1/CINGP0/CIN+ GP2/COUT A A D COUT Multiplexed Input with Internal Reference CM2:CM0 = 110 GP1/CINGP0/CIN+ GP2/COUT A A D From CVREF Module CIS = 0 CIS = 1 COUT A = Analog Input. The CMCON register. DS41190G-page 39 . Figure 6-2 shows the eight possible modes.2 Comparator Configuration There are eight modes of operation for the comparator. If the Comparator mode is changed. Note: Comparator interrupts should be disabled during a Comparator mode change. the comparator output level may not be valid for a specified period of time. is used to select the mode. a false interrupt may occur.

FIGURE 6-4: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM GP0/CIN+ To GP2/T0CKI pin To Data Bus RD CMCON Q D EN CINV GP1/CINCVREF CM2:CM0 Set CMIF bit Q D EN Reset RD CMCON DS41190G-page 40  2010 Microchip Technology Inc. all pins configured as analog inputs will read as a ‘0’. Figure 6-4 shows the comparator output block diagram. should have very little leakage current.PIC12F629/675 6. Since the analog pins are connected to a digital output. the output on GP2 is asynchronous to the internal clock. such as a capacitor or a Zener diode. When in one of these modes.6V Leakage ±500 nA Vss Legend: CPIN VT ILEAKAGE RIC RS VA = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to Various Junctions = Interconnect Resistance = Source Impedance = Analog Voltage The TRISIO<2> bit functions as an output enable/ disable for the GP2 pin while the comparator is in an Output mode. A maximum source impedance of 10 k is recommended for the analog sources. 6. Note 1: When reading the GPIO register. The analog input. COUT.6V RIC VA CPIN 5 pF VT = 0. as shown in Figure 6-2. If the input voltage deviates from this FIGURE 6-3: ANALOG INPUT MODE VDD Rs < 10K AIN VT = 0. Any external component connected to an analog input pin. This bit is read-only. may cause the input buffer to consume more current than is specified.6V in either direction.4 Comparator Output The comparator output. . one of the diodes is forward biased and a latch-up may occur. A simplified circuit for an analog input is shown in Figure 6-3. 2: Analog levels on any pin that is defined as a digital input.3 Analog Input Connection Considerations range by more than 0. The comparator output may also be directly output to the GP2 pin in three of the eight possible modes. Pins configured as digital inputs will convert an analog input according to the TTL input specification. must be between VSS and VDD. is read through the CMCON register. they have reverse biased diodes to VDD and VSS. therefore.

 2010 Microchip Technology Inc. FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input VRR VR3:VR0 6. The transistors on the top and bottom of the resistor ladder network (Figure 6-5) keep CVREF from approaching VSS or VDD. DS41190G-page 41 . Register 6-2. VRCON<7> = 0. remain active during Sleep. While the comparator is enabled during Sleep. The VRCON register. if enabled before entering Sleep mode. Otherwise. 6. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 12. CM2:CM0 = 111. This forces the comparator module to be in the Comparator Reset mode. before the comparator output is ensured to have a valid level. CM2:CM0 = 000 and the voltage reference to its off state. and voltage reference.PIC12F629/675 6. an interrupt will wake-up the device. after selecting a new reference voltage or input source. This results in higher Sleep currents than shown in the power-down specifications. The Voltage Reference is VDD derived and therefore. all potential inputs are analog inputs with the comparator and voltage reference disabled to consume the smallest current possible. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. turn off the comparator. the CVREF output changes with fluctuations in VDD. the maximum delay of the comparators should be used (Table 12-7). If the internal reference is changed. If the device wakes up from Sleep. To minimize power consumption while in Sleep mode. Thus.5.5.7 Operation During Sleep Both the comparator and voltage reference. 6.0 “Electrical Specifications”.8 Effects of a Reset 6. The full range of VSS to VDD cannot be realized due to the construction of the module. 16 in a high range and 16 in a low range. the contents of the CMCON and VRCON registers are not affected.5 Comparator Reference The following equations determine the output voltages: VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x VDD / 32) The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs.6 Comparator Response Time Response time is the minimum time.1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels. The internal reference signal is used for four of the eight Comparator modes. controls the voltage reference module shown in Figure 6-5. the maximum delay of the internal voltage reference must be considered when using the comparator outputs. A device Reset forces the CMCON and VRCON registers to their Reset states.2 VOLTAGE REFERENCE ACCURACY/ERROR 6.

Since it is also possible to write a ‘1’ to this register. and allow flag bit CMIF to be cleared. . The CMIF bit. then the CMIF (PIR1<3>) interrupt flag may not get set.0--0 --11 1111 0-0. u = unchanged.0--0 -0-0 0000 00-. BOD 0000 0000 00-. the GIE bit must also be set.0--0 -0-0 0000 00-. This will end the mismatch condition. TABLE 6-2: Address 0Bh/8Bh 0Ch 19h 8Ch 85h 99h Legend: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 GIE EEIF — EEIE — VREN Bit 6 PEIE ADIF COUT ADIE — — Bit 5 T0IE — — — Bit 4 INTE — CINV — Bit 3 GPIE CMIF CIS CMIE Bit 2 T0IF — CM2 — Bit 1 INTF — CM1 — Bit 0 GPIF TMR1IF CM0 TMR1IE Value on POR. in the Interrupt Service Routine. to determine the actual change that has occurred. A mismatch condition will continue to set flag bit CMIF. Software will need to maintain information about the status of the output bits. Clear flag bit CMIF.PIC12F629/675 REGISTER 6-2: R/W-0 VREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit.0--0 --11 1111 0-0. DS41190G-page 42  2010 Microchip Technology Inc. This bit must be reset in software by clearing it to ‘0’. can clear the interrupt in the following manner: a) b) Any read or write of CMCON.9 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of the comparator.0000 Name INTCON PIR1 CMCON PIE1 TRISIO VRCON TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 VRR — VR3 VR2 VR1 VR0 x = unknown. Reading CMCON will end the mismatch condition. Note: If a change in the CMCON register (COUT) should occur when a read operation is being executed (start of the Q2 cycle). Shaded cells are not used by the comparator module.0000 Value on all other Resets 0000 000u 00-. If any of these bits are cleared. is the comparator interrupt flag.= unimplemented. the interrupt is not enabled. The user. The CMIE bit (PIE1<3>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. read as ‘0’. a simulated interrupt may be initiated. . no IDD drain Unimplemented: Read as ‘0’ VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as ‘0’ VR3:VR0: CVREF value selection 0  VR [3:0]  15 When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD bit 6 bit 5 bit 4 bit 3-0 6. though the CMIF bit will still be set if an interrupt condition occurs. as read from CMCON<6>. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) U-0 — R/W-0 VRR R/W-0 — R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down. In addition. PIR1<3>.

PIC12F629/675 7. If VCFG is set. The CHS1:CHS0 bits (ADCON0<3:2>) control which channel is connected to the sample and hold circuit. set the corresponding ANS bit to disable the digital input buffer. Figure 7-1 shows the block diagram of the A/D on the PIC12F675. multiplexed into one sample and hold FIGURE 7-1: A/D BLOCK DIAGRAM VDD VCFG = 0 VREF VCFG = 1 GP0/AN0 GP1/AN1/VREF GP2/AN2 GP4/AN3 CHS1:CHS0 GO/DONE ADFM ADON ADRESH VSS 10 ADRESL ADC 10 7.4 CONVERSION CLOCK 7.6 s. Set the corresponding TRISIO bits to set the pin output driver to its high-impedance state.2 CHANNEL SELECTION There are four analog channels on the PIC12F675.1 ANALOG PORT PINS The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO bits control the operation of the A/D port pins. There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal RC oscillator) 7. Likewise. Table 7-1 shows a few TAD calculations for selected frequencies. The PIC12F675 has four analog inputs. The source of the conversion clock is software selectable via the ADCS bits (ANSEL<6:4>). or an analog voltage applied to VREF is used. then the voltage on the VREF pin is the reference. The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by the VREF pin. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register.1. 2.1.1. The A/D conversion cycle requires 11 TAD. VDD is the reference. DS41190G-page 43 . 7. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.1. ADCON0 (Register 7-1) ANSEL (Register 7-2) controls the voltage reference selection. 7. the A/D conversion clock (1/TAD) must be selected to ensure a minimum TAD of 1. otherwise.1 A/D Configuration and Operation There are two registers available to control the functionality of the A/D module: 1. The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representation of that signal. AN0 through AN3.3 VOLTAGE REFERENCE There are two options for the voltage reference to the A/D converter: either VDD is used.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE (PIC12F675 ONLY) circuit. For correct conversion. The VCFG bit (ADCON0<6>)  2010 Microchip Technology Inc.

.6 CONVERSION OUTPUT The A/D conversion can be supplied in two formats: left or right shifted.0 s 25. Following the delay. When the conversion is complete.6 s 4 TOSC 100 200 ns(2) 800 ns(2) 1. an input acquisition is automatically started on the selected channel.4) Legend: Shaded cells are outside of recommended range.0 s 6. the ADRESH:ADRESL registers will retain the value of the previous conversion. a 2 TAD delay is required before another acquisition can be initiated.6 s(3) (3) (3) 64 TOSC 110 3.2 s 001 400 ns(2) 1.8 s(3) (3) 32 TOSC 010 1.1. 7. 3: For faster conversion times. Figure 7-2 shows the output formats.6 s(1. 2: These values violate the minimum required TAD time.6 s 6.1.PIC12F629/675 TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES Device Frequency A/D Clock Source (TAD) Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.5 STARTING A CONVERSION The A/D conversion is initiated by setting the GO/DONE bit (ADCON0<1>). the selection of another clock source is recommended.6 s(1. the A/D RC clock source is only recommended if the conversion will be performed during Sleep.2 s(3) A/D RC x11 2 .0 s(2) 3.25 MHz 2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1. Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3. After an aborted conversion.4) 2 .4) 2 . 7. the GO/DONE bit can be cleared in software. FIGURE 7-2: 10-BIT A/D RESULT FORMAT ADRESH ADRESL LSB Bit 0 10-bit A/D Result Bit 7 Bit 0 Unimplemented: Read as ‘0’ LSB Bit 0 Bit 7 10-bit A/D Result Bit 0 (ADFM = 0) MSB Bit 7 (ADFM = 1) Bit 7 Unimplemented: Read as ‘0’ MSB DS41190G-page 44  2010 Microchip Technology Inc.4) 2 .0 s 51. the A/D module: • Clears the GO/DONE bit • Sets the ADIF flag (PIR1<6>) • Generates an interrupt (if enabled) If the conversion must be aborted.8 s 16.0 s 12.2 s 4.0V. Note: The GO/DONE bit should not be set in the same instruction that turns on the A/D. The ADFM bit (ADCON0<7>) controls the output format.4 s 8. Instead. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion sample.6 s 2.6 s(1.2 s 12.6 s(1.4 s 8 TOSC (2) 16 TOSC 101 800 ns 3. 4: When the device frequency is greater than 1 MHz.

PIC12F629/675 REGISTER 7-1: R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. This bit is automatically cleared by hardware when the A/D conversion has completed. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ADCON0: A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 VCFG U-0 — U-0 — R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD Unimplemented: Read as ‘0’ CHS1:CHS0: Analog Channel Select bits 00 = Channel 00 (AN0) 01 = Channel 01 (AN1) 10 = Channel 02 (AN2) 11 = Channel 03 (AN3) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. 0 = A/D conversion completed/not in progress ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current bit 6 bit 5-4 bit 3-2 bit 1 bit 0  2010 Microchip Technology Inc. Setting this bit starts an A/D conversion cycle. DS41190G-page 45 .

.PIC12F629/675 REGISTER 7-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. weak pull-ups. respectively. The corresponding TRISIO bit must be set to Input mode in order to allow external control of the voltage on the pin.) 1 = Analog input. pin is assigned to port or special function Setting a pin to an analog input automatically disables the digital input circuitry. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ANSEL: ANALOG SELECT REGISTER (ADDRESS: 9Fh) R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0 Unimplemented: Read as ‘0’ ADCS<2:0>: A/D Conversion Clock Select bits 000 = Fosc/2 001 = Fosc/8 010 = Fosc/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = Fosc/4 101 = Fosc/16 110 = Fosc/64 ANS3:ANS0: Analog Select bits (Between analog or digital function on pins AN<3:0>. and interrupt-on-change. bit 3-0 Note 1: DS41190G-page 46  2010 Microchip Technology Inc. pin is assigned as analog input(1) 0 = Digital I/O.

47s 2s + 16.0004885) 16. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The sampling switch (RSS) impedance varies over the device voltage (VDD). As the impedance is decreased.05s/C) 19. FIGURE 7-3: ANALOG INPUT MODEL VDD RS VA ANx CPIN 5 pF VT = 0. The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. The analog input model is shown in Figure 7-3. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD.47s + [(50°C -25C)(0. see Figure 7-3.05s/°C)] CHOLD (RIC + RSS + RS) In(1/2047) . EQUATION 7-1: TACQ ACQUISITION TIME = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = = = = = = = TAMP + TC + TCOFF 2s + TC + [(Temperature -25°C)(0. This is required to meet the pin leakage specification. since it cancels itself out. the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. 3: The maximum recommended impedance for analog sources is 10 k. DS41190G-page 47 .2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy. Equation 7-1 may be used. this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time.PIC12F629/675 7. see the PIC® Mid-Range Reference Manual (DS33023).72s TC TACQ Note 1: The reference voltage (VREF) has no effect on the equation.120pF (1k + 7k + 10k) In(0. the acquisition time may be decreased. TACQ.6V Sampling Switch RIC  1K SS RSS I LEAKAGE ± 500 nA CHOLD = DAC capacitance = 120 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I LEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k) VT = 0. After the analog input channel is selected (changed).6V  2010 Microchip Technology Inc. To calculate the minimum acquisition time. The maximum recommended impedance for analog sources is 10 k.

0000 --11 1111 00-. the GO/DONE bit is cleared. the device awakens from Sleep. The ADON bit remains set. thus eliminating much of the switching noise from the conversion. a SLEEP instruction causes the present conversion to be aborted.4 Effects of Reset A device Reset forces all registers to their Reset state. When the A/D clock source is something other than RC. DS41190G-page 48  2010 Microchip Technology Inc. and the A/D module is turned off. 8Bh INTCON ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result TRISIO2 TRISIO1 TRISIO0 Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result Legend: x = unknown. Thus the A/D module is turned off and any pending conversion is aborted. BOD --xx xxxx 0000 0000 00-.PIC12F629/675 7. u = unchanged.0000 --11 1111 00-.0--0 xxxx xxxx 00-.0--0 uuuu uuuu -000 1111 0Bh. Shaded cells are not used for A/D converter module. and the result is loaded into the ADRESH:ADRESL registers.0--0 xxxx xxxx -000 1111 Value on all other Resets --uu uuuu 0000 000u 00-. although the ADON bit remains set.3 A/D Operation During Sleep The A/D converter module can operate during Sleep. If the A/D interrupt is not enabled. 7. the A/D waits one instruction before starting the conversion. The ADRESH:ADRESL registers are unchanged. This requires the A/D clock source to be set to the internal RC oscillator. When the conversion is complete. TABLE 7-2: Address 05h 0Ch 1Eh 1Fh 85h 8Ch 9Eh 9Fh Name GPIO PIR1 ADCON0 TRISIO PIE1 ADRESL ANSEL SUMMARY OF A/D REGISTERS Bit 7 — GIE EEIF ADFM — EEIE — Bit 6 — PEIE ADIF VCFG — ADIE ADCS2 Bit 5 GPIO5 T0IE — — TRISIO5 — ADCS1 Bit 4 GPIO4 INTE — — TRISIO4 — ADCS0 Bit 3 GPIO3 GPIE CMIF CHS1 TRISIO3 CMIE ANS3 Bit 2 GPIO2 T0IF — CHS0 — ANS2 Bit 1 GPIO1 INTF — GO — ANS1 Bit 0 GPIO0 GPIF TMR1IF ADON TMR1IE ANS0 Value on POR. When the RC clock source is selected. the A/D module is turned off.= unimplemented read as ‘0’.0--0 uuuu uuuu 00-. . This allows the SLEEP instruction to be executed. . If the A/D interrupt is enabled.

EEDATA holds the 8-bit data for read/write. Instead. The write time will vary with voltage and temperature as well as from chip to chip. A byte write automatically erases the location and writes the new data (erase before write). This memory is not directly mapped in the register file space. The write time is controlled by an on-chip timer. REGISTER 8-1: R/W-0 EEDAT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 EEDAT: EEPROM DATA REGISTER (ADDRESS: 9Ah) R/W-0 EEDAT6 R/W-0 EEDAT5 R/W-0 EEDAT4 R/W-0 EEDAT3 R/W-0 EEDAT2 R/W-0 EEDAT1 R/W-0 EEDAT0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. PIC12F629/675 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. (DS33023). the CPU may continue to read and write the data EEPROM memory.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). When the data memory is code-protected.PIC12F629/675 8. There are four SFRs used to read and write this memory: • • • • EECON1 EECON2 (not a physically implemented register) EEDATA EEADR The EEPROM data memory allows byte read and write. The EEPROM data memory is rated for high erase/write cycles. it is indirectly addressed through the Special Function Registers. The device programmer can no longer access this memory. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Should be set to ‘0’ EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation  2010 Microchip Technology Inc. Please refer to AC Specifications for exact limits. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown EEDATn: Byte value to write to or read from data EEPROM REGISTER 8-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-0 EEADR: EEPROM ADDRESS REGISTER (ADDRESS: 9Bh) R/W-0 EADR6 R/W-0 EADR5 R/W-0 EADR4 R/W-0 EADR3 R/W-0 EADR2 R/W-0 EADR1 R/W-0 EADR0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. Additional information on the data EEPROM is available in the PIC® Mid-Range Reference Manual. DS41190G-page 49 . and EEADR holds the address of the EEPROM location being accessed.

not cleared. The upper bit should always be ‘0’ to remain upward compatible with devices that have more data EEPROM memory. therefore. This bit must be cleared in software. following Reset. respectively. the WREN bit is clear. read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset. in software. RD is cleared in hardware. Reading EECON2 will read all ‘0’s. any WDT Reset during normal operation or BOD detect) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. . Interrupt flag bit EEIF in the PIR1 register is set when write is complete. The upper four bits are nonimplemented and read as ‘0’s.PIC12F629/675 8. when set. Only seven of the eight bits in the register (EEADR<6:0>) are required. Control bits RD and WR initiate read and write. only set. or a WDT Time-out Reset during normal operation. The WRERR bit is set when a write operation is interrupted by a MCLR Reset. The EECON2 register is used exclusively in the data EEPROM write sequence. 0 = Does not initiate an EEPROM read bit 2 bit 1 bit 0 DS41190G-page 50  2010 Microchip Technology Inc. The inability to clear the WR bit in software prevents the accidental. These bits cannot be cleared. will allow a write operation. The MSb (bit 7) is ignored. not cleared. premature termination of a write operation. EECON2 is not a physical register.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. clear it. The RD bit can only be set. in software. the EEDATA and EEADR registers will need to be re-initialized. 8. of the read or write operation. in software). The data and address will be cleared. The WR bit can only be set. the user can check the WRERR bit. The WREN bit. and rewrite the location.1 EEADR The EEADR register can address up to a maximum of 128 bytes of data EEPROM. On power-up. They are cleared in hardware at completion REGISTER 8-3: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3 EECON1: EEPROM CONTROL REGISTER (ADDRESS: 9Ch) U-0 — U-0 — U-0 — R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit. In these situations.2 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented.

The user can either enable this interrupt or poll this bit.Bank 0 .e.from previous write . To protect against spurious EEPROM writes.Disable INTs .Address to read .value written .EE Read . We strongly recommend that interrupts be disabled during this code segment.Bank 1 . XORWF EEDATA.RP0 CONFIG_ADDR EEADR EECON1. continue STATUS. an array refresh must be performed.W BTFSS STATUS. EXAMPLE 8-3: BCF : BSF MOVF BSF WRITE VERIFY . the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. write AAh to EECON2. or until it is written to by the user (during a write operation). good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 8-3) to the desired value to be written. At the completion of the write cycle. then set WR bit) for each byte.YES.Enable INTS 8. The user should keep the WREN bit clear at all times.PIC12F629/675 8. IDs. A cycle count is executed during the required sequence. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i. The EEIF bit (PIR<7>) register must be cleared by software. Then the user must follow a specific sequence to initiate the write for each byte..W Depending on the application. variables that change infrequently (such as constants. various mechanisms have been built in.Z GOTO WRITE_ERR : EXAMPLE 8-2: BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF DATA EEPROM WRITE .3 Reading the EEPROM Data Memory After a write sequence has been initiated. the WREN bit in EECON1 must be set to enable write.Yes.) should be stored in Flash program memory.W EECON1. The WR bit will be inhibited from being set unless the WREN bit is set. the Power-up Timer (72 ms duration) prevents EEPROM write.RP0 EEDATA. DS41190G-page 51 . The data EEPROM is a high-endurance.RD 8..5 Write Verify EXAMPLE 8-1: BSF MOVLW MOVWF BSF MOVF DATA EEPROM READ . the user must write the address to the EEADR register and then set control bit RD (EECON1<0>).No. On power-up. WREN is cleared.g. the user must first write the address to the EEADR register and the data to the EEDATA register.Any code . To read a data memory location. Also.1 USING THE DATA EEPROM STATUS. EEDATA holds this value until another read.WREN INTCON.Is data the same .6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. .Bank 1 READ .Bank 1 .RP0 STATUS. etc. calibration.4 Writing to the EEPROM Data Memory To write an EEPROM data location. program variables or other data that are updated often).WR INTCON. Additionally. lost programs).GIE 55h EECON2 AAh EECON2 EECON1.RP0 EECON1. except when updating EEPROM. Read the .Unlock write .Move data to W STATUS.5.GIE The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2. clearing the WREN bit will not affect this write cycle.RD EEDATA. byte addressable array that has been optimized for the storage of frequently changing information (e. Required Sequence 8. handle error . it can be read in the next instruction. For this reason.EEDATA not changed . in the very next cycle.Start the write . Therefore. . in the EEDATA register. The WREN bit is not cleared by hardware. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM.Enable write . as shown in Example 8-2. . The write initiate sequence and the WREN bit together help prevent an accidental write during: • brown-out • power glitch • software malfunction  2010 Microchip Technology Inc. 8. If this is not the case. as shown in Example 8-1. Frequently changing values will typically be updated more often than specifications D120 or D120A. The data is available. .

0--0 0000 0000 0000 0000 -000 0000 -000 0000 EEPROM Data Register EEPROM Address Register — — — WRERR WREN WR RD ---. . Programming unused locations to ‘0’ will also help prevent data memory code protection from becoming breached. TABLE 8-1: Address 0Ch 9Ah 9Bh 9Ch 9Dh REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Name Bit 7 EEIF — — Bit 6 ADIF Bit 5 — Bit 4 — Bit 3 CMIF Bit 2 — Bit 1 — Bit 0 Value on POR. Shaded cells are not used by data EEPROM module. programmed in unused program memory. BOD Value on all other Resets PIR1 EEDATA EEADR EECON1 TMR1IF 00-.x000 ---. DS41190G-page 52  2010 Microchip Technology Inc. u = unchanged. .= unimplemented read as ‘0’.0--0 00-. It is recommended to code protect the program memory when code protecting data memory.---. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine. which outputs the contents of data memory.q000 ---. q = value depends upon condition.---. When the data memory is code protected. the CPU is able to read and write data to the data EEPROM. Note 1: EECON2 is not a physical register.PIC12F629/675 8.---- EECON2(1) EEPROM Control Register 2 Legend: x = unknown.7 Data EEPROM Operation During Code Protect Data memory can be code protected by programming the CPD bit to ‘0’.

DS41190G-page 53 . which provides a fixed delay of 72 ms (nominal) on power-up only. The Sleep mode is designed to offer a very low current Power-down mode. The PIC12F629/675 family has a host of such features intended to: • maximize system reliability • minimize cost through elimination of external components • provide power saving operating modes and offer code protection These features are: • Oscillator selection • Reset . It runs off its own RC oscillator for added reliability. designed to keep the part in Reset while the power supply stabilizes. The INTOSC option saves system cost while the LP crystal option saves power.Power-on Reset (POR) . The other is the Power-up Timer (PWRT). There are two timers that offer necessary delays on power-up.Power-up Timer (PWRT) .PIC12F629/675 9.Brown-out Detect (BOD) • Interrupts • Watchdog Timer (WDT) • Sleep • Code protection • ID Locations • In-Circuit Serial Programming  2010 Microchip Technology Inc. which can provide at least a 72 ms Reset. intended to keep the chip in Reset until the crystal oscillator is stable. With these three functions on-chip. There is also circuitry to reset the device if a brown-out occurs. A set of Configuration bits are used to select various options (see Register 9. The user can wake-up from Sleep through: • External Reset • Watchdog Timer wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. Certain special circuits that deal with the needs of real time applications are what sets a microcontroller apart from other processors. One is the Oscillator Start-up Timer (OST). most applications need no external Reset circuitry.2).Oscillator Start-up Timer (OST) .0 SPECIAL FEATURES OF THE CPU The PIC12F629/675 has a Watchdog Timer that is controlled by Configuration bits.

. when the code protection is turned off. read as ‘0’ 0 = bit is cleared x = bit is unknown BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1) 00 = Lowest bandgap voltage 11 = Highest bandgap voltage Unimplemented: Read as ‘0’ CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program Memory code protection is disabled 0 = Program Memory code protection is enabled BODEN: Brown-out Detect Enable bit(4) 1 = BOD enabled 0 = BOD disabled MCLRE: GP3/MCLR Pin Function Select bit(5) 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O. REGISTER 9-1: R/P-1 BG1 bit 13 Legend: R/P-1 BG0 U-0 — CONFIG: CONFIGURATION WORD (ADDRESS: 2007h) U-0 — U-0 — R/P-1 CPD R/P-1 CP R/P-1 BODEN R/P-1 MCLRE R/P-1 PWRTE R/P-1 WDTE R/P-1 F0SC2 R/P-1 F0SC1 R/P-1 F0SC0 bit 0 P = Programmed using ICSP™ R = Readable bit -n = Value at POR bit 13-12 Writable bit 1 = bit is set U = Unimplemented bit. The Configuration bits can be programmed (read as ‘0’). See PIC12F629/675 Programming Specification for more information. I/O function on GP5/OSC1/CLKIN 011 = EC: I/O function on GP4/OSC2/CLKOUT pin. RC on GP5/OSC1/CLKIN 110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin. CLKIN on GP5/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as specified in the PIC12F629/675 Programming Specification. These bits are mapped in program memory location 2007h. including OSCCAL value.2.PIC12F629/675 9. These bits are reflected in an export of the Configuration Word. The entire program memory will be erased. The entire data EEPROM will be erased when the code protection is turned off. I/O function on GP5/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin. the internal clock oscillator is disabled. bit 11-9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 Note 1: 2: 3: 4: 5: DS41190G-page 54  2010 Microchip Technology Inc. When MCLR is asserted in INTOSC or RC mode. as shown in Register 9.1 Configuration Bits Note: Address 2007h is beyond the user program memory space. Microchip Development Tools maintain all Calibration bits to factory settings. or left unprogrammed (read as ‘1’) to select various device configurations. RC on GP5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin. Enabling Brown-out Detect does not automatically enable Power-up Timer. It belongs to the special configuration memory space (2000h-3FFFh). MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin. which can be accessed only during programming.

the user should consult the crystal manufacturer for appropriate values of external components. HS FIGURE 9-1: CRYSTAL OPERATION (OR CERAMIC RESONATOR) HS. 455 kHz 2.1 Oscillator Configurations OSCILLATOR TYPES FIGURE 9-2: The PIC12F629/675 can be operated in eight different oscillator option modes. the user should consult the resonator manufacturer for appropriate values of external components.2. TABLE 9-2: Mode LP XT CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Freq.2. LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (see Figure 9-1). When in XT. OSC1(C1) 68-100 pF 68-150 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF OSC2(C2) 68-100 pF 150-200 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF C1(1) 32 kHz 100 kHz 2 MHz 4 MHz 8 MHz 10 MHz 20 MHz C2(1) Note 1: 2: 3: RS(2) PIC12F629/675 HS See Table 9-1 and Table 9-2 for recommended values of C1 and C2. Since each crystal has its own characteristics. RF varies with the Oscillator mode selected (Approx. TABLE 9-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Ranges Characterized: OSC1(C1) 68-100 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF OSC2(C2) 68-100 pF 15-68 pF 15-68 pF 10-68 pF 10-22 pF Mode XT Freq. OR LP OSC CONFIGURATION) Clock from External System Open OSC1 PIC12F629/675 OSC2(1) Note 1: Functions as GP4 in EC Osc mode. These values are for design guidance only. (DS33023). These values are for design guidance only.0 MHz 4. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. XT. XT OR LP OSC CONFIGURATION OSC1 To Internal Logic XTAL OSC2 RF(3) Sleep Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. value = 10 M Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. EXTERNAL CLOCK INPUT OPERATION (HS. The user can program three Configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • • • • • • LP Low-Power Crystal XT Crystal/Resonator HS High-Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Oscillator (2 modes) EC External Clock In Note: Additional information on oscillator configurations is available in the PIC® MidRange Reference Manual. Since each resonator has its own characteristics. DS41190G-page 55 . the device can have an external clock source to drive the OSC1 pin (see Figure 9-2).0 MHz 16.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS In XT. EC.  2010 Microchip Technology Inc.2 9.PIC12F629/675 9. Use of a series cut crystal may yield a frequency outside of the crystal manufacturers specifications.0 MHz 9. The PIC12F629/675 oscillator design requires the use of a parallel cut crystal. LP or HS modes. A series resistor may be required for AT strip cut crystals.0 MHz 8.

4 RC OSCILLATOR For applications where precise timing is not a requirement.0 “Electrical Specifications”. where the literal is the calibration value. the oscillator frequency divided by four (FOSC/4) is output on the GP4/OSC2/CLKOUT pin.2. . This instruction is a RETLW XX.Bank 0 PIC12F629/675 GP5/OSC1/ CLKIN Internal Clock STATUS. Microchip Development Tools maintain all Calibration bits to factory settings. For best operation. Section 12. See Electrical Specifications.3 EXTERNAL CLOCK IN 9. 9.1 Calibrating the Internal Oscillator A calibration instruction is programmed into the last location of program memory.Get the cal value . Example 9-1 demonstrates how to calibrate the internal oscillator. The calibration value must be saved prior to erasing part as specified in the PIC12F629/675 Programming specification.Calibrate . When calibrated. Figure 9-3 shows how the R/C combination is connected. the internal oscillator provides a fixed 4 MHz (nominal) system clock.2.6 CLKOUT CEXT VSS FOSC/4 GP4/OSC2/CLKOUT The PIC12F629/675 devices can be configured to provide a clock out signal in the INTOSC and RC oscillator modes. 9.2. The oscillator frequency will vary from unit to unit due to normal process parameter variation. users may directly drive the PIC12F629/ 675 provided that this external clock source meets the AC/DC timing requirements listed in Section 12. The difference in lead frame capacitance between package types will also affect the oscillation frequency.2. EXAMPLE 9-1: BSF CALL MOVWF BCF FIGURE 9-3: VDD REXT RC OSCILLATOR MODE CALIBRATING THE INTERNAL OSCILLATOR . Two options are available for this Oscillator mode which allow GP4 to be used as a general purpose I/O or to output FOSC/4. The operation and functionality of the RC oscillator is dependent upon a number of variables.Bank 1 . Two options are available for this Oscillator mode which allow GP4 to be used as a general purpose I/O or to output FOSC/4. The RC oscillator frequency is a function of: • Supply voltage • Resistor (REXT) and capacitor (CEXT) values • Operating temperature. DS41190G-page 56  2010 Microchip Technology Inc. RP0 3FFh OSCCAL STATUS. Figure 9-2 shows how an external clock circuit should be configured.5 INTERNAL 4 MHZ OSCILLATOR For applications where a clock is already available elsewhere.0 “Electrical Specifications”. The user also needs to account for the tolerance of the external R and C components. for information on variation over voltage and temperature. the RC oscillator option is available.PIC12F629/675 9. FOSC/4 can be used for test purposes or to synchronize other logic. RP0 9. decouple (with capacitance) VDD and VSS as close to the device as possible.5. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The literal is placed in the OSCCAL register to set the calibration of the internal oscillator. especially for low CEXT values. When configured.2.

 2010 Microchip Technology Inc. See Table 9-7 for a full description of Reset states of all registers. Most other registers are reset to a “Reset state” on: • • • • • Power-on Reset MCLR Reset WDT Reset WDT Reset during Sleep Brown-out Detect (BOD) Reset FIGURE 9-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/ VPP pin WDT Module VDD Rise Detect VDD WDT SLEEP Time-out Reset Power-on Reset Brown-out Detect S Q BODEN OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN pin On-chip(1) RC OSC PWRT 10-bit Ripple Counter R Q Chip_Reset Enable PWRT Enable OST See Table 9-3 for time-out situations. TO and PD bits are set or cleared differently in different Reset situations as indicated in Table 9-4. The MCLR Reset path has a noise filter to detect and ignore small pulses.3 Reset The PIC12F629/675 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Detect (BOD) They are not affected by a WDT wake-up. Note 1: This is a separate oscillator from the INTOSC/EC oscillator. DS41190G-page 57 .PIC12F629/675 9. A simplified block diagram of the on-chip Reset Circuit is shown in Figure 9-4. Some registers are not affected in any Reset condition. since this is viewed as the resumption of normal operation. These bits are used in software to determine the nature of the Reset. See Table 12-4 in Electrical Specifications Section for pulse-width specification. their status is unknown on POR and unchanged in any other Reset.

PIC12F629/675
9.3.1 MCLR
PIC12F629/675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 9-5, is suggested. An internal MCLR option is enabled by setting the MCLRE bit in the Configuration Word. When enabled, MCLR is internally tied to VDD. No internal pull-up option is available for the MCLR pin. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting”.

9.3.3

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms (nominal) time-out on power-up only, from POR or Brown-out Detect. The Power-up Timer operates on an internal RC oscillator. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should always be enabled when Brown-out Detect is enabled. The Power-up Time delay will vary from chip to chip and due to: • VDD variation • Temperature variation • Process variation. See DC parameters for details (Section 12.0 “Electrical Specifications”).

FIGURE 9-5:
VDD

RECOMMENDED MCLR CIRCUIT
PIC12F629/675

9.3.4

R1 1 kor greater MCLR C1 0.1 f (optional, not critical)

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from Sleep.

9.3.2

POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details (see Section 12.0 “Electrical Specifications”). If the BOD is enabled, the maximum rise time specification does not apply. The BOD circuitry will keep the device in Reset until VDD reaches VBOD (see Section 9.3.5 “Brown-Out Detect (BOD)”). Note: The POR circuit does not produce an internal Reset when VDD declines.

When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.

DS41190G-page 58

 2010 Microchip Technology Inc.

PIC12F629/675
9.3.5 BROWN-OUT DETECT (BOD)
The PIC12F629/675 members have on-chip Brown-out Detect circuitry. A Configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Detect circuitry. If VDD falls below VBOD for greater than parameter (TBOD) in Table 12-4 (see Section 12.0 “Electrical Specifications”), the Brown-out situation will reset the device. This will occur regardless of VDD slew-rate. A Reset is not guaranteed to occur if VDD falls below VBOD for less than parameter (TBOD). On any Reset (Power-on, Brown-out, Watchdog, etc.), the chip will remain in Reset until VDD rises above BVDD (see Figure 9-6). The Power-up Timer will now be invoked, if enabled, and will keep the chip in Reset an additional 72 ms. Note: A Brown-out Detect does not enable the Power-up Timer if the PWRTE bit in the Configuration Word is set.

If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Detect and the Power-up Timer will be re-initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms Reset.

FIGURE 9-6:
VDD

BROWN-OUT SITUATIONS
VBOD

Internal Reset VDD

72 ms(1)

VBOD

Internal Reset

<72 ms

72 ms(1)

VDD

VBOD

Internal Reset

72 ms(1)

Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.

9.3.6

TIME-OUT SEQUENCE

9.3.7

On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 9-7, Figure 9-8 and Figure 9-9 depict timeout sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC12F629/675 device operating in parallel. Table 9-6 shows the Reset conditions for some special registers, while Table 9-7 shows the Reset conditions for all the registers.

POWER CONTROL (PCON) STATUS REGISTER
register, PCON

The power CONTROL/STATUS (address 8Eh) has two bits.

Bit 0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked on subsequent Resets to see if BOD = 0, indicating that a brown-out has occurred. The BOD Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (by setting BODEN bit = 0 in the Configuration Word). Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Power-on Reset must have occurred (i.e., VDD may have gone too low).

 2010 Microchip Technology Inc.

DS41190G-page 59

PIC12F629/675
TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up Oscillator Configuration XT, HS, LP RC, EC, INTOSC PWRTE = 0 TPWRT + 1024•TOSC TPWRT PWRTE = 1 1024•TOSC — Brown-out Detect PWRTE = 0 TPWRT + 1024•TOSC TPWRT PWRTE = 1 1024•TOSC — Wake-up from Sleep 1024•TOSC —

TABLE 9-4:
POR 0 1 u u u u

STATUS/PCON BITS AND THEIR SIGNIFICANCE
BOD u 0 u u u u TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Detect WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

TABLE 9-5:
Address 03h 8Eh

SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7 IRP — Bit 6 RP1 — Bit 5 RPO — Bit 4 TO — Bit 3 PD — Bit 2 Z — Bit 1 DC POR Bit 0 C BOD Value on POR, BOD Value on all other Resets(1)

Name STATUS PCON

0001 1xxx 000q quuu ---- --0x ---- --uq

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.

TABLE 9-6:

INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1
(1)

STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu

PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu

Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Detect Interrupt Wake-up from Sleep

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

DS41190G-page 60

 2010 Microchip Technology Inc.

= unimplemented bit.0000 0000 0000 -000 0000 ---. .---xxxx xxxx -000 1111 Legend: u = unchanged.---uuuu uuuu -uuu uuuu Register Address W INDF TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 T1CON CMCON ADRESH ADCON0 OPTION_REG TRISIO PIE1 PCON OSCCAL WPU IOC VRCON EEDATA EEADR EECON1 EECON2 ADRESL ANSEL — 00h/80h 01h 02h/82h 03h/83h 04h/84h 05h 0Ah/8Ah 0Bh/8Bh 0Ch 10h 19h 1Eh 1Fh 81h 85h 8Ch 8Eh 90h 95h 96h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh xxxx xxxx — xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --xx xxxx ---0 0000 0000 0000 00-. 6: If Reset was due to brown-out.0000 0000 0000 -000 0000 ---. the PC is loaded with the interrupt vector (0004h). reads as ‘0’.--0x 1000 00---11 -111 --00 0000 0-0.PIC12F629/675 TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS Power-on Reset • MCLR Reset during normal operation • MCLR Reset during Sleep • WDT Reset • Brown-out Detect(1) uuuu uuuu — uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu --uu uuuu ---0 0000 0000 000u 00-. DS41190G-page 61 . Note 1: If VDD goes too low.0--0 -000 0000 -0-0 0000 xxxx xxxx 00-.  2010 Microchip Technology Inc.uuuu ---.uuuu uuuu uuuu --uu uuuu uu-.u--u ---.0--0 ---. q = value depends on condition. Power-on Reset will be activated and registers will be affected differently.x000 ---.5) -uuu uuuu -u-u uuuu uuuu uuuu uu-. 5: If wake-up was due to data EEPROM write completing. x = unknown. 4: See Table 9-6 for Reset value for specific condition. or Timer1 rolling over.uuuu uuuu uuuu -uuu uuuu ---. A/D conversion completing. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).q--q(2. All other Resets will cause bit 0 = u.0--0 -uuu uuuu -0-0 0000 uuuu uuuu 00-. 3: When the wake-up is due to an interrupt and the GIE bit is set. Bit 7 = 1.6) 1000 00---11 -111 --00 0000 0-0.q000 ---.0000 1111 1111 --11 1111 00-.0--0 ---. Bit 6 = 1. bit 0 = 1. All other interrupts generating a wake-up will cause these bits to = u.--uu uuuu uu-uuuu uuuu --uu uuuu u-u. Comparator input changing. then bit 0 = 0. bit 3 = 1.0000 1111 1111 --11 1111 00-.--uu(1.---uuuu uuuu -000 1111 • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT Time-out uuuu uuuu — uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu --uu uuuu ---u uuuu uuuu uuqq(2) qq-.

.PIC12F629/675 FIGURE 9-7: VDD MCLR Internal POR TPWRT PWRT Time-out OST Time-out Internal Reset TOST TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 9-8: VDD MCLR Internal POR TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 TPWRT PWRT Time-out OST Time-out Internal Reset TOST FIGURE 9-9: VDD MCLR Internal POR TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) TPWRT PWRT Time-out OST Time-out Internal Reset TOST DS41190G-page 62  2010 Microchip Technology Inc.

The corresponding interrupt enable bit is contained in special register PIE1. GIE (INTCON<7>) enables (if set) all unmasked interrupts. or GP port change interrupt. 2: When an instruction that clears the GIE bit is executed.PIC12F629/675 9.4 • • • • • • • Interrupts The PIC12F629/675 has 7 sources of interrupt: External Interrupt GP2/INT TMR0 Overflow Interrupt GPIO Change Interrupts Comparator Interrupt A/D Interrupt (PIC12F675 only) TMR1 Overflow Interrupt EEPROM Data Write Interrupt determined by polling the interrupt flag bits. The following interrupt flags are contained in the PIR register: • • • • EEPROM data write interrupt A/D interrupt Comparator interrupt Timer1 overflow interrupt When an interrupt is serviced: • The GIE is cleared to disable any further interrupt • The return address is pushed onto the stack • The PC is loaded with 0004h Once in the Interrupt Service Routine. Once in the Interrupt Service Routine. which re-enables unmasked interrupts. RETFIE. The latency is the same for one or twocycle instructions. Note 1: Individual interrupt flag bits are set. such as the INT pin. any interrupts that were pending for execution in the next cycle are ignored. A Global Interrupt Enable bit. The following interrupt flags are contained in the INTCON register: • INT pin interrupt • GP port change interrupt • TMR0 overflow interrupt The peripheral interrupt flags are contained in the special register PIR1. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. The exact latency depends upon when the interrupt event occurs (see Figure 9-11). the interrupt latency will be three or four instruction cycles. the source(s) of the interrupt can be  2010 Microchip Technology Inc. The INTCON register also has individual and Global Interrupt Enable (GIE) bits. The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits. DS41190G-page 63 . For external interrupt events. exits interrupt routine. The return from interrupt instruction. GIE is cleared on Reset. regardless of the status of their corresponding mask bit or the GIE bit. the source(s) of the interrupt can be determined by polling the interrupt flag bits. as well as sets the GIE bit. Individual interrupts can be disabled through their corresponding enable bits in INTCON register and PIE register. or disables (if cleared) all interrupts. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid GP2/ INT recursive interrupts. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests.

PIC12F629/675 FIGURE 9-10: IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 T0IF T0IE INTF INTE GPIF GPIE PEIE (1) INTERRUPT LOGIC Wake-up (If in Sleep mode) TMR1IF TMR1IE CMIF CMIE ADIF ADIE EEIF EEIE Note 1: PIC12F675 only. Interrupt to CPU GIE DS41190G-page 64  2010 Microchip Technology Inc. .

This interrupt can be disabled by clearing the INTE control bit (INTCON<4>).9 “Comparator description of comparator interrupt. 4: For minimum width of INT pulse. 9. 9.0 “Analog-to-Digital Converter (A/D) Module (PIC12F675 only)” for operation of the A/D converter interrupt.3 GPIO INTERRUPT External interrupt on GP2/INT pin is edge-triggered. See Section 9. The interrupt can be enabled/disabled by setting or clearing ADIE (PIE<6>). For operation of the Timer0 module. see Section 4. The interrupt can be enabled/ disabled by setting/clearing the GPIE (INTCON<3>) bit.  2010 Microchip Technology Inc.4. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. FIGURE 9-11: Q1 OSC1 CLKOUT 3 INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed INT PIN INTERRUPT TIMING Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 4 1 1 5 Interrupt Latency 2 PC PC + 1 Inst (PC+1) Inst (PC) PC + 1 — Dummy Cycle 0004h Inst (0004h) Dummy Cycle 0005h Inst (0005h) Inst (0004h) Inst (PC) Inst (PC . either rising if INTEDG bit (OPTION<6>) is set.1) Note 1: INTF flag is sampled here (every Q1).7 “Power-Down Mode (Sleep)” for details on Sleep and Figure 9-13 for timing of wake-up from Sleep through GP2/INT interrupt.PIC12F629/675 9. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle). then the GPIF interrupt flag may not get set.1 GP2/INT INTERRUPT 9. 2: Asynchronous interrupt latency = 3-4 TCY. The ANSEL register is defined for the PIC12F675.4 COMPARATOR INTERRUPT Interrupts” for See Section 6.4.4. When a valid edge appears on the GP2/INT pin. where TCY = instruction cycle time. Plus individual pins can be configured through the IOC register. Synchronous latency = 3 TCY.0 “Timer0 Module”. An input change on GPIO change sets the GPIF (INTCON<0>) bit. the INTF bit (INTCON<1>) is set.4. of falling. Pins configured as analog inputs will read ‘0’.4.5 A/D CONVERTER INTERRUPT After a conversion is complete. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. the ADIF flag (PIR<6>) is set. 3: CLKOUT is available only in RC Oscillator mode. if INTEDG bit is clear. See Section 7. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. Note: The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. DS41190G-page 65 . refer to AC specs. The GP2/INT interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. 9.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set the T0IF (INTCON<2>) bit.

change to bank 0 regardless of current bank . Temperature = Max.swap W_TEMP into W 9.1 “Configuration Bits”). W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1). q = value depends upon condition. 8Bh INTCON 0Ch 8Ch PIR1 PIE1 0000 0000 0000 000u TMR1IF 00-.. (with no prescaler). The TO bit in the STATUS register will be cleared upon a Watchdog Timer Time-out. Shaded cells are not used by the interrupt module. WDT prescaler) it may take several seconds before a WDT Time-out occurs.0--0 TMR1IE 00-. Thus. must be defined in both banks and must be defined at the same offset from the bank base address (i. which requires no external components.swap STATUS_TEMP register into W. time-out periods up to 2. W register and STATUS register).. VDD = Min.0--0 Legend: x = unknown. This RC oscillator is separate from the external RC oscillator of the CLKIN pin and INTOSC. a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. The CLRWDT and SLEEP instructions clear the WDT and the prescaler.copy W to temp register.move W into STATUS register SWAPF W_TEMP.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worstcase conditions (i.6 Watchdog Timer (WDT) During an interrupt.0--0 00-. The WDT can be permanently disabled by programming the Configuration bit WDTE as clear (Section 9. only the return PC value is saved on the stack.e. 9. The time-out periods vary with temperature.RP0 SAVING THE STATUS AND W REGISTERS IN RAM . could be in either bank . MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP.swap W_TEMP SWAPF W_TEMP. If longer time-out periods are desired.W. BOD Value on all other Resets 0Bh. 9. During normal operation. users may wish to save key registers during an interrupt (e.g.e. This must be implemented in software. must be defined in Bank 0. If the device is in Sleep mode.6.W STATUS. a WDT Time-out causes the device to wake-up and continue with normal operation. The Example 9-2: • • • • Stores the W register Stores the STATUS register in Bank 0 Executes the ISR code Restores the STATUS (and bank select bit register) • Restores the W register The Watchdog Timer is a free running.swap status to be saved into W . Typically. STATUS_TEMP.W .5 Context Saving During Interrupts 9.3 seconds can be realized. . The user register. by execution of a SLEEP instruction). and prevent it from timing out and generating a device Reset. That means that the WDT will run. sets bank to original state MOVWF STATUS ..F . VDD and process variations from part to part (see DC specs). a WDT Time-out generates a device Reset.6.= unimplemented read as ‘0’. if assigned to the WDT. Example 9-2 stores and restores the STATUS and W registers. on-chip RC oscillator.. u = unchanged. W_TEMP.save status to bank 0 register The WDT has a nominal time-out period of 18 ms.0--0 00-.1 WDT PERIOD EXAMPLE 9-2: MOVWF SWAPF BCF W_TEMP STATUS.. even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example. DS41190G-page 66  2010 Microchip Technology Inc. The user register. Max. .PIC12F629/675 TABLE 9-8: Address Name SUMMARY OF INTERRUPT REGISTERS Bit 7 GIE EEIF EEIE Bit 6 PEIE ADIF ADIE Bit 5 T0IE — — Bit 4 INTE — — Bit 3 GPIE CMIF CMIE Bit 2 T0IF — — Bit 1 INTF — — Bit 0 GPIF Value on POR.

PS0-PS2 are bits in the OPTION register. T0CS. DS41190G-page 67 .PIC12F629/675 FIGURE 9-12: CLKOUT (= FOSC/4) WATCHDOG TIMER BLOCK DIAGRAM Data Bus 0 1 1 T0CKI pin T0SE T0CS SYNC 2 Cycles 8 TMR0 Set Flag bit T0IF on Overflow 0 8-bit Prescaler 0 PSA 1 PSA 8 PS0 . PSA.PS2 Watchdog Timer 1 0 PSA WDT Time-out WDTE Note 1: T0SE. BOD Value on all other Resets OPTION_REG GPPU INTEDG Config.  2010 Microchip Technology Inc. TABLE 9-9: Address 81h 2007h SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 T0CS Bit 4 T0SE Bit 3 PSA Bit 2 PS2 F0SC2 Bit 1 PS1 F0SC1 Bit 0 PS0 F0SC0 Value on POR. bits CP 1111 1111 1111 1111 uuuu uuuu uuuu uuuu BODEN MCLRE PWRTE WDTE Legend: u = Unchanged. shaded cells are not used by the Watchdog Timer.

For the device to wake-up through an interrupt event. or a peripheral interrupt. The PD bit. The contribution from on-chip pull-ups on GPIO should be considered. In this case after wake-up. The WDT is cleared when the device wakes up from Sleep. If GIE = 0. then branches to the interrupt address (0004h). . or VSS. low. execution will continue in-line. For lowest current consumption in this mode. The T0CKI input should also be at VDD or VSS for lowest current consumption. LP or EC Osc modes.1) Dummy cycle Dummy cycle XT. The two latter events are considered a continuation of program execution. If the GIE bit is clear (disabled). DS41190G-page 68  2010 Microchip Technology Inc. See Section 12 for wake-up from Sleep delay in INTOSC mode. all I/O pins should be either at VDD. HS or LP Oscillator mode assumed. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running PD bit in the STATUS register is cleared TO bit is set Oscillator driver is turned off I/O ports maintain the status they had before Sleep was executed (driving high. The MCLR pin must be at a logic high level (VIHMC). 2. TOST = 1024TOSC (drawing not to scale).7 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. FIGURE 9-13: OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Interrupt Latency (Note 2) Processor in Sleep PC + 1 Inst(PC + 1) Sleep PC + 2 PC + 2 Inst(PC + 2) Inst(PC + 1) PC + 2 0004h Inst(0004h) 0005h Inst(0005h) Inst(0004h) Inst(PC) = Sleep Inst(PC . TO bit is cleared if WDT Wake-up occurred.PIC12F629/675 9. but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set. the user should have an NOP after the SLEEP instruction. HS. GIE = 1 assumed. External Reset input on MCLR pin Watchdog Timer Wake-up (if WDT was enabled) Interrupt from GP2/INT pin. is cleared when Sleep is invoked. 9.7. GPIO change. CLKOUT is not available in XT. with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. the corresponding interrupt enable bit must be set (enabled). 3. The SLEEP instruction is completely executed. Note: If the global interrupts are disabled (GIE is cleared). The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. Note: It should be noted that a Reset generated by a WDT Time-out does not drive MCLR pin low. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. In cases where the execution of the instruction following SLEEP is not desirable. the next instruction (PC + 1) is pre-fetched. the device continues execution at the instruction after the SLEEP instruction. which is set on power-up. Wake-up is regardless of the state of the GIE bit. but shown here for timing reference. the processor jumps to the interrupt routine. regardless of the source of wake-up. the device will immediately wake-up from Sleep. the device executes the instruction after the SLEEP instruction. Approximately 1 s delay will be there for RC Osc mode. If the GIE bit is set (enabled).1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. The first event will cause a device Reset. When the SLEEP instruction is being executed. or high-impedance).

Both GP0 and GP1 are Schmitt Trigger inputs in this mode. This function allows simple debugging functions when used with MPLAB ICD 2. Table 9-10 shows which features are consumed by the background debugger: TABLE 9-10: I/O pins Stack DEBUGGER RESOURCES ICDCLK. data and MCLR pins and frees all normally available pins to the user. On the bottom of the header is an 8-pin socket that plugs into the user’s target via the 8-pin stand-off connector. External Connector Signals +5V 0V VPP CLK Data I/O TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections PIC12F629/675 VDD VSS GP3/MCLR/VPP GP1 GP0 9. the on-chip program memory can be read out for verification purposes.  2010 Microchip Technology Inc. DS41190G-page 69 . the In-Circuit Debugger functionality is enabled. VDD To Normal Connections 9. some of the resources are not available for general use. A special 14-pin PIC12F675-ICD device is used with MPLAB ICD 2 to provide separate clock. while raising the MCLR (VPP) pin from VIL to VIHH (see Programming Specification). the PC is at location 00h. These locations are not accessible during normal execution but are readable and writable during Program/Verify. The INTOSC calibration data is also erased. ICDDATA 1 level Address 0h must be NOP 300h-3FEh Program Memory For more information.PIC12F629/675 9. MPLAB® ICD 2 development with an 8-pin device is not practical.microchip. Only the Least Significant 7 bits of the ID locations are used. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off.10 In-Circuit Serial Programming 9.11 The PIC12F629/675 microcontrollers can be serially programmed while in the end application circuit. GP0 becomes the programming data and GP1 becomes the programming clock.9 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. In-Circuit Debugger Since in-circuit debugging requires the loss of clock. to place the device into Programming/ Verify mode. When the ICD pin on the PIC12F675-ICD device is held low. When the microcontroller has this feature enabled. and three other lines for: • power • ground • programming voltage This allows customers to manufacture boards with unprogrammed devices. depending on whether the command was a load or a read. This special ICD device is mounted on the top of the header and its signals are routed to the MPLAB ICD 2 connector. A 6-bit command is then supplied to the device.8 Code Protection FIGURE 9-14: If the code protection bit(s) have not been programmed. 14-bits of program data are then supplied to or from the device. This is simply done with two lines for clock and data. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low. After Reset. For complete details of serial programming. A typical In-Circuit Serial Programming connection is shown in Figure 9-14.com). data and MCLR pins. and then program the microcontroller just before shipping the product. Depending on the command. please refer to the Programming Specifications. This also allows the most recent firmware or a custom firmware to be programmed. see 8-Pin MPLAB ICD 2 Header Information Sheet (DS51292) available on Microchip’s web site (www. See PIC12F629/675 Programming Specification for more information.

PIC12F629/675 NOTES: DS41190G-page 70  2010 Microchip Technology Inc. .

constant data or label Don’t care location (= 0 or 1). When this occurs. For literal and control operations. where ‘h’ signifies a hexadecimal digit. or literal value. TABLE 10-1: Field f W b k x OPCODE FIELD DESCRIPTIONS Description Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field. ‘k’ represents an 8bit or 11-bit constant. this gives a normal instruction execution time of 1 s. clear all the data bits. If ‘d’ is one. Note: To maintain upward compatibility with future products. Destination select. which specifies the instruction type. ‘b’ represents a bit field designator. All instructions are executed within a single instruction cycle. d = 0: store result in W. For bit-oriented instructions. 0 k = 11-bit immediate value  2010 Microchip Technology Inc. then write the result back to GPIO.0 INSTRUCTION SET SUMMARY The PIC12F629/675 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC12F629/675 instruction is a 14-bit word divided into an opcode. This example would have the unintended result that the condition that sets the GPIF flag would be cleared. which further specify the operation of the instruction.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. for an oscillator frequency of 4 MHz. the result is placed in the W register. Table 10-2 lists the instructions recognized by the MPASM TM assembler. ‘f’ represents a file register designator and ‘d’ represents a destination designator. the data is modified. or the program counter is changed as a result of an instruction. A read operation is performed on a register even if the instruction writes to that register. The assembler will generate code with x = 0. while the various opcode fields are summarized in Table 10-1. unless a conditional test is true. The file register designator specifies which file register is to be used by the instruction.PIC12F629/675 10. One instruction cycle consists of four oscillator periods. while ‘f’ represents the address of the file in which the bit is located. and the result is stored according to either the instruction. d = 1: store result in file register f. A complete description of each instruction is also available in the PIC ® MidRange Reference Manual (DS33023). The formats for each of the categories is presented in Figure 10-1. The register is read. with the second cycle executed as a NOP. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero. Default is d = 1. For byte-oriented instructions. It is the recommended form of use for compatibility with all Microchip software tools. or the destination designator ‘d’. 0 10. For example. DS41190G-page 71 . do not use the OPTION and TRISIO instructions. Program Counter Time-out bit Power-down bit d PC TO PD FIGURE 10-1: GENERAL FORMAT FOR INSTRUCTIONS 0 Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal) 0 All instruction examples use the format ‘0xhh’ to represent a hexadecimal number. which selects the bit affected by the operation. the execution takes two instruction cycles. a CLRF GPIO instruction will read GPIO. the result is placed in the file register specified in the instruction. and one or more operands.

d f. d f.2 1. d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f. if the data latch is ‘1’ for a pin configured as input and is driven low by an external device.Z Z Note 1: When an I/O register is modified as a function of itself (e. 2: If this instruction is executed on the TMR0 register (and.DC.2 1.2 1.DC. Note: Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Reference Manual (DS33023).PIC12F629/675 TABLE 10-2: Mnemonic. Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C.2 C C C. the value used will be that value present on the pins themselves.2.2 3 3 LITERAL AND CONTROL OPERATIONS TO. b f. where applicable. MOVF GPIO. d f.2 1. d f. d f f. d f.2. Operands PIC12F629/675 INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f.Z Z TO. b k k k k k k k k k Bit Clear f Bit Set f Bit Test f. d f.PD Z 1.2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f.2 1. or a conditional test is true. b f.g.PD C.Z Z Z Z Z Z Z Z Z 1.. Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C. d f. the prescaler will be cleared if assigned to the Timer0 module. d f.2 1.3 1.Z Z 1.DC. DS41190G-page 72  2010 Microchip Technology Inc. For example.2 1. Skip if Clear Bit Test f. the data will be written back with a ‘0’. the instruction requires two cycles.3 1. d f f. Skip if 0 Increment f Increment f.2 2 1. d f. b f. 3: If Program Counter (PC) is modified. .DC.2 1. d f. d f.2 1.2 1. 1). d = 1). The second cycle is executed as a NOP.

the result is stored back in register ‘f’. the next instruction is executed. f. making this a 2TCY instruction. f. DS41190G-page 73 . AND Literal with W [label] ANDLW 0  k  255 (W) . the result is stored back in register ‘f’.d  2010 Microchip Technology Inc.AND. If ‘d’ is 1.d BSF Syntax: Operands: Operation: Status Affected: Description: Bit Set f [label] BSF 0  f  127 0b7 1  (f<b>) None Bit ‘b’ in register ‘f’ is set. the result is stored in the W register.2 ADDLW Syntax: Operands: Operation: Status Affected: Description: Instruction Descriptions Add Literal and W [label] ADDLW 0  k  255 (W) + k  (W) C. ANDWF Syntax: Operands: Operation: Status Affected: Description: AND W with f [label] ANDWF 0  f  127 d  (W) . DC. (k)  (W) Z The contents of W register are AND’ed with the eight-bit literal ‘k’. DC.AND. the result is stored in the W register. k f. then the next instruction is discarded and a NOP is executed instead.b ANDLW Syntax: Operands: Operation: Status Affected: Description: BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f.b ADDWF Syntax: Operands: Operation: Status Affected: Description: Add W and f [label] ADDWF 0  f  127 d  (W) + (f)  (destination) C. Z The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. f. If ‘d’ is 1.b 0  f  127 0b<7 skip if (f<b>) = 1 None If bit ‘b’ in register ‘f’ is ‘0’.PIC12F629/675 10. (f)  (destination) Z AND the W register with register ‘f’. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [label] BCF 0  f  127 0b7 0  (f<b>) None Bit ‘b’ in register ‘f’ is cleared. Z Add the contents of the W register with register ‘f’. The result is placed in the W register. Skip if Set [label] BTFSS f. If ‘d’ is 0. If ‘d’ is 0. If bit ‘b’ is ‘1’.

If ‘d’ is 1. CALL is a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h  WDT 0  WDT prescaler. The eleven-bit immediate address is loaded into PC bits <10:0>.1  (destination) Z Decrement register ‘f’. the result is stored in the W register. CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0  k  2047 (PC)+ 1 TOS. k  PC<10:0>. If ‘d’ is 0. (PCLATH<4:3>)  PC<12:11> None Call Subroutine. COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0  f  127 d  [0. It also resets the prescaler of the WDT.b 0  f  127 0b7 skip if (f<b>) = 0 None If bit ‘b’ in register ‘f’ is ‘1’. f DECF Syntax: Operands: Operation: Status Affected: Description: Decrement f [label] DECF f. CLRW Syntax: Operands: Operation: Status Affected: Description: Clear W [ label ] CLRW None 00h  (W) 1Z Z W register is cleared. the next instruction is discarded. the result is stored back in register ‘f’. Zero bit (Z) is set. First.d 0  f  127 d  [0. The upper bits of the PC are loaded from PCLATH. the result is stored in W. the next instruction is executed.1] (f) .d Status Affected: Description: CLRF Syntax: Operands: Operation: Status Affected: Description: Clear f [label] CLRF 0  f  127 00h  (f) 1Z Z The contents of register ‘f’ are cleared and the Z bit is set. If ‘d’ is 0. making this a 2TCY instruction. Status bits TO and PD are set. 1  TO 1  PD TO. is ‘0’. Skip if Clear [label] BTFSC f. If ‘d’ is 1. If bit ‘b’.PIC12F629/675 BTFSC Syntax: Operands: Operation: Status Affected: Description: Bit Test. the result is stored back in register ‘f’. return address (PC + 1) is pushed onto the stack. PD CLRWDT instruction resets the Watchdog Timer. DS41190G-page 74  2010 Microchip Technology Inc. .1] (f)  (destination) Z The contents of register ‘f’ are complemented. in register ‘f’. f. and a NOP is executed instead.

1] (f) + 1  (destination) Z The contents of register ‘f’ are incremented. skip if result = 0 None The contents of register ‘f’ are decremented. a NOP is executed instead. If ‘d’ is 1. making it a 2TCY instruction. The eleven-bit immediate value is loaded into PC bits <10:0>. skip if result = 0 None The contents of register ‘f’ are incremented. IORWF Syntax: Operands: Operation: Status Affected: Description: Inclusive OR W with f [ label ] IORWF f. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f. DS41190G-page 75 . the result is placed back in register ‘f’. the next instruction is executed. If the result is 1. the next instruction is executed.d 0  f  127 d  [0. (f)  (destination) Z Inclusive OR the W register with register ‘f’. the result is placed in the W register. Skip if 0 [ label ] INCFSZ f.PIC12F629/675 DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f. making it a 2TCY instruction.OR. then a NOP is executed instead. If ‘d’ is 1. If the result is 1. the result is placed in the W register. the result is placed back in register ‘f’. GOTO is a twocycle instruction. If ‘d’ is 0.d 0  f  127 d  [0.1] (f) .OR.1] (f) + 1  (destination). The result is placed in the W register. the result is placed back in register ‘f’.  2010 Microchip Technology Inc. k  (W) Z The contents of the W register are OR’ed with the eight-bit literal ‘k’. If ‘d’ is 1. the result is placed in the W register. If ‘d’ is 1. IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR Literal with W [ label ] IORLW k 0  k  255 (W) . If ‘d’ is 0. If ‘d’ is 0.1  (destination). The upper bits of PC are loaded from PCLATH<4:3>. If the result is 0. GOTO Syntax: Operands: Operation: Status Affected: Description: Unconditional Branch [ label ] GOTO k 0  k  2047 k  PC<10:0> PCLATH<4:3>  PC<12:11> None GOTO is an unconditional branch. the result is placed in the W register. Skip if 0 [ label ] DECFSZ f. If the result is 0.d 0  f  127 d  [0. the result is placed back in register ‘f’.d 0  f  127 d  [0. If ‘d’ is 0.1] (W) . INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] INCF f.

the destination is W register. the destination is file register f itself. 1 1 MOVLW 0x5A No Operation [ label ] None No operation None No operation. 1 1 MOVF FSR. The “don’t cares” will assemble as ‘0’s. If d = 1. . d = 1 is useful to test a file register since status flag Z is affected.PIC12F629/675 MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f. 0 MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: Move W to f [ label ] (W)  (f) None Move data from W register to register ‘f’. 1 1 NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: NOP MOVLW k 0  k  255 Words: Cycles: Example: After Instruction W = 0x5A DS41190G-page 76  2010 Microchip Technology Inc. 1 1 MOVWF OPTION 0xFF 0x4F 0x4F 0x4F Before Instruction OPTION = W = After Instruction OPTION = W = MOVWF f 0  f  127 Words: Cycles: Example: After Instruction W = value in FSR register Z = 1 NOP MOVLW Syntax: Operands: Operation: Status Affected: Description: Move literal to W [ label ] k  (W) None The eight-bit literal ‘k’ is loaded into W register. If d = 0.1] (f)  (dest) Z The contents of register f is moved to a destination dependent upon the status of d.d 0  f  127 d  [0.

PIC12F629/675
RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS  PC, 1  GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE

RETLW Syntax: Operands: Operation: Status Affected: Description:

Return with literal in W [ label ] RETLW k 0  k  255 k  (W); TOS  PC None The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table
;offset value • ;W now has table value • • ADDWF PCL ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table

RETFIE

Words: Cycles: Example:

Words: Cycles: Example:

After Interrupt PC = GIE =

TABLE TOS 1

Before Instruction W = 0x07 After Instruction W = value of k8

RETURN Syntax: Operands: Operation: Status Affected: Description:

Return from Subroutine [ label ] None TOS  PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN

 2010 Microchip Technology Inc.

DS41190G-page 77

PIC12F629/675
RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0  f  127 d  [0,1] See description below C The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.
C Register f

SUBLW Syntax: Operands: Operation: Description:

Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) W) The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register.

f,d

Status Affected: C, DC, Z

SUBWF Syntax: Operands: Operation: Status Affected: Description:

Subtract W from f [ label ] SUBWF f,d 0 f 127 d  [0,1] (f) - (W) destination) C, DC, Z Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.

RRF Syntax: Operands: Operation: Status Affected: Description:

Rotate Right f through Carry [ label ] RRF f,d 0  f  127 d  [0,1] See description below C The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is placed back in register ‘f’.
C Register f

SWAPF Syntax: Operands:

Swap Nibbles in f [ label ] SWAPF f,d 0  f  127 d  [0,1] (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) None The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is placed in register ‘f’.

SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h  WDT, 0  WDT prescaler, 1  TO, 0  PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.

Operation: Status Affected: Description:

Status Affected: Description:

DS41190G-page 78

 2010 Microchip Technology Inc.

PIC12F629/675
XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR Literal with W [label] XORLW k 0 k 255 (W) .XOR. k W) Z The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Operation: Status Affected: Description: XORWF Syntax: Operands: Exclusive OR W with f [label] XORWF f,d 0  f  127 d  [0,1] (W) .XOR. (f) destination) Z Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.

 2010 Microchip Technology Inc.

DS41190G-page 79

PIC12F629/675 NOTES: DS41190G-page 80  2010 Microchip Technology Inc. .

In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools.MPLAB® IDE Software • Compilers/Assemblers/Linkers .MPLAB ICD 3 .0 DEVELOPMENT SUPPORT 11. to full-featured emulators.MPLAB C Compiler for Various Device Families .1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment .MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators . and download to emulator and simulator tools (automatically updates all project information) • Debug using: .MPLINKTM Object Linker/ MPLIBTM Object Librarian .  2010 Microchip Technology Inc.Simulator .PICkit™ 3 Debug Express • Device Programmers . This eliminates the learning curve when upgrading to tools with increased flexibility and power. Evaluation Kits. through low-cost in-circuit debuggers. from the cost-effective simulators.Mixed C and assembly . and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. DS41190G-page 81 . The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools .MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers .Programmer (sold separately) .MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards.MPLAB SIM Software Simulator • Emulators .Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm.In-Circuit Emulator (sold separately) .PIC12F629/675 11.MPASMTM Assembler . such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble.PICkit™ 2 Programmer .HI-TECH C for Various Device Families .Source files (C or assembly) .

linker. The compilers include a macro assembler. only the modules that contain that routine will be linked in with the application. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24. the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. omniscient code generation and ease of use. preprocessor. MPLAB C Compiler uses the assembler to produce its object file. superior code optimization and ease of use. Linker and Librarian for Various Device Families 11.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing. Intel® standard HEX files. deletion and extraction 11. MAP files to detail memory usage and symbol reference. universal macro assembler for PIC10/12/16/18 MCUs. the compilers provide symbol information that is optimized to the MPLAB IDE debugger. . The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker. PIC32 and dsPIC devices.2 MPLAB C Compilers for Various Device Families 11. These compilers provide powerful integration capabilities. This allows large libraries to be used efficiently in many different applications. PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS41190G-page 82  2010 Microchip Technology Inc. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. For easy source level debugging. and one-step driver.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers.6 MPLAB Assembler. 11.PIC12F629/675 11. These compilers provide powerful integration capabilities. For easy source level debugging. absolute LST files that contain source lines and generated machine code and COFF files for debugging. replacement. It can link relocatable objects from precompiled libraries.4 MPASM Assembler The MPASM Assembler is a full-featured. and can run on multiple platforms. using directives from a linker script. When a routine from a library is called from a source file.

lessons. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost. complex breakpoints.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and and dsPIC® Flash programming of PIC® microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). full-speed emulation. The emulator is field upgradable through future firmware downloads in MPLAB IDE.PIC12F629/675 11.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. MPLAB ICD 3 supports all MPLAB ICD 2 headers. On any given instruction. The PICkit 3 Debug Express include the PICkit 3. yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers. and the MPASM and MPLAB Assemblers. trace analysis. DS41190G-page 83 . Registers can be logged to files for further run-time analysis. The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The emulator is connected to the design engineer’s PC using a high-speed USB 2. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. hookup cables and CDROM with user’s guide. most peripherals and internal registers. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment. 11. The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). a ruggedized probe interface and long (up to three meters) interconnection cables. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2. noise tolerant. run-time variable watches. actions on I/O. the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. compiler and MPLAB IDE software. and new features will be added. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use. making it an excellent. Low-Voltage Differential Signal (LVDS) interconnection (CAT5). new devices will be supported.  2010 Microchip Technology Inc. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful.7 MPLAB SIM Software Simulator 11. In upcoming releases of MPLAB IDE.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution. demo board and microcontroller. tutorial.8 MPLAB REAL ICE In-Circuit Emulator System 11. economical software development tool. included with each kit. powerful graphical user interface of the MPLAB Integrated Development Environment (IDE).

detachable socket assembly to support various package types. 16-bit. halts and single steps the program while the PIC microcontroller is embedded in the application.com) for the complete list of demonstration. plus many more. CAN.microchip. and 32-bit microcontrollers. hookup cables and CDROM with user’s guide. The boards support a variety of features. Evaluation Kits. the MPLAB PM3 Device Programmer can read. SEEVAL® evaluation system. The PICkit 2 Debug Express include the PICkit 2. potentiometers and additional EEPROM memory. PIC24. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. tutorial.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal. and Starter Kits A wide variety of demonstration. PIC16F). lessons. In Stand-Alone mode. RS-232 interfaces. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits. demo board and microcontroller. for prototyping custom circuits and for learning about various microcontroller applications. development and evaluation kits. PowerSmart battery management. 11. The full featured Windows® programming interface supports baseline (PIC10F. The demonstration and development boards can be used in teaching environments. Sigma-Delta ADC. PIC18F. Also available are starter kits that contain everything needed to experience the specified device. CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. PIC12F5xx. PIC16F5xx). When halted at a breakpoint. and many Microchip Serial EEPROM products. and PIC32 families of 8-bit. It can also set code protection in this mode. In-Circuit-Debugging runs. flow rate sensing. dsPIC30. LCD displays. It features a large LCD display (128 x 64) for menus and error messages and a modular.PIC12F629/675 11. DS41190G-page 84  2010 Microchip Technology Inc. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. . including LEDs.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. Microchip has a line of evaluation kits and demonstration software for analog filter design. dsPIC33. Check the Microchip web page (www. all on one board. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. speakers. IrDA®. midrange (PIC12F6xx. compiler and MPLAB IDE software. development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. KEELOQ® security ICs. The ICSP™ cable assembly is included as a standard item. verify and program PIC devices without a PC connection. 11. switches.13 Demonstration/Development Boards. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. This usually includes a single application and debug capability. temperature sensors. the file registers can be examined and modified.

.... -65°C to +150°C Voltage on VDD with respect to VSS .............. 25 mA Maximum output current sourced by any I/O pin ............ 250 mA Input clamp current..................... Exposure to maximum rating conditions for extended periods may affect device reliability.................................................. DS41190G-page 85 ................. rather than pulling this pin directly to VSS.................... 300 mA Maximum current into VDD pin ......................................................5V Voltage on MCLR with respect to Vss ....................................... -0............ inducing currents greater than 80 mA.................3V) Total power dissipation(1) ........ 125 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD .......................................................... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied...... a series resistor of 50-100  should be used when applying a “low” level to the MCLR pin.......................................... IOK (Vo < 0 or Vo >VDD)20 mA Maximum output current sunk by any I/O pin...............................................  2010 Microchip Technology Inc........................................................................................................ † NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device..............................................................................-0...........5V Voltage on all other pins with respect to VSS ......... Thus... 25 mA Maximum current sunk by all GPIO ..................................0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings† Ambient temperature under bias..................... IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL). 125 mA Maximum current sourced all GPIO .................3V to (VDD + 0.............. 800 mW Maximum current out of VSS pin ................................................. IIK (VI < 0 or VI > VDD)20 mA Output clamp current......3 to +6........................................................ may cause latch-up.......................................................................................................................... -40 to +125°C Storage temperature ........................................................................ Note: Voltage spikes below VSS at the MCLR pin.........................................................................................3 to +13.......... -0..............................................................PIC12F629/675 12..............................................................................................................................

0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.0 3.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.5 5.5 3.5 2.5 VDD (Volts) 4.5 VDD (Volts) 4. DS41190G-page 86  2010 Microchip Technology Inc.0 2. FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH.0 3.0 4. . -40°C  TA  +125°C 5.5 5.0 2.PIC12F629/675 FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH.5 2.0 4. -40°C  TA  +125°C 5.5 3.

DS41190G-page 87 .0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.0 2.0 4. 0°C  TA  +125°C 5.2 2.5 2.5 3.  2010 Microchip Technology Inc.5 VDD (Volts) 4.0 3.PIC12F629/675 FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH.5 5.

5 5. These parameters are for design guidance only and are not tested. 25°C unless otherwise stated.5 — — V V V V V V V Conditions FOSC < = 4 MHz: PIC12F629/675 with A/D off PIC12F675 with A/D on. 0°C to +125°C PIC12F675 with A/D on. PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Min 2.2 2. D001 D001A D001B D001C D001D D002 D003 Sym VDD Characteristic Supply Voltage D004 SVDD 0.5 3. † Data in “Typ” column is at 5.1 DC Characteristics: PIC12F629/675-I (Industrial). -40°C to +125°C 4 MHZ < FOSC < = 10 MHz Device in Sleep mode See section on Power-on Reset for details DC CHARACTERISTICS Param No.5 5. .5 5. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.5 5.0 4.PIC12F629/675 12.1 — V * These parameters are characterized but not tested.5 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal 1. DS41190G-page 88  2010 Microchip Technology Inc.0V.5* — Typ† Max Units — — — — — — VSS 5.0 2.05* — — V/ms See section on Power-on Reset for details D005 VBOD — 2.

0 3.0 2.0 4.0 2.1 2.2 DC Characteristics: PIC12F629/675-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +85C for industrial Param No. oscillator type.0 5.6 70 140 260 180 320 580 340 500 0. Other factors such as I/O pin loading and switching rate.  2010 Microchip Technology Inc.0 FOSC = 20 MHz HS Oscillator Mode FOSC = 4 MHz EXTRC Mode FOSC = 4 MHz INTOSC Mode FOSC = 4 MHz EC Oscillator Mode FOSC = 1 MHz EC Oscillator Mode FOSC = 4 MHz XT Oscillator Mode FOSC = 1 MHz XT Oscillator Mode Note FOSC = 32 kHz LP Oscillator Mode † Data in “Typ” column is at 5.0 3.0 5.0 5.1 250 450 800 2. D010 Device Characteristics Supply Current (IDD) Min — — — D011 — — — D012 — — — D013 — — — D014 — — — D015 — — — D016 — — — D017 — — Typ† 9 18 35 110 190 330 220 370 0.0 2.0V.0 5.0 5.0 2.8 180 320 580 2.0 5. 25C unless otherwise stated.PIC12F629/675 12. internal code execution pattern.0 5.0 3.4 110 250 390 250 470 850 450 700 1.4 Max 16 28 54 150 280 450 280 650 1.0 2. DS41190G-page 89 .0 3. all I/O pins tri-stated.0 2. 2: The supply current is mainly a function of the operating voltage and frequency. and temperature also have an impact on the current consumption.5 5.0 Units A A A A A A A A mA A A A A A A A A mA A A A mA mA Conditions VDD 2. from rail-to-rail.95 3. These parameters are for design guidance only and are not tested.0 3.0 3.0 3. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave. WDT disabled. pulled to VDD. MCLR = VDD.

2 2.0 3. These parameters are for design guidance only and are not tested.0 10. Power-down current is measured with the part in Sleep mode.0 3.5 16 70 100 160 6.2 0. with all I/O pins in high-impedance state and tied to VDD.0 3.0V.99 1.0 3.0 2.5 58 85 138 4.8 8. and T1OSC disabled † Data in “Typ” column is at 5. 25C unless otherwise stated. .0 4.0 2.0 3. VREF.0 1.3 1.3 DC Characteristics: PIC12F629/675-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +85C for industrial Param No. Comparators. DS41190G-page 90  2010 Microchip Technology Inc.0 2.0 A/D Current(1) T1 OSC Current(1) CVREF Current(1) Comparator Current(1) BOD Current(1) WDT Current(1) Note WDT.0 5.0 3.0022 Max 700 770 995 1.6 6.5 775 1.0 5. Max values should be used when calculating total current consumption.0 Units nA nA nA A A A A A A A A A A A A A A nA A Conditions VDD 2. D020 Device Characteristics Power-down Base Current (IPD) Min — — — D021 — — — D022 D023 — — — — — D024 — — — D025 — — — D026 — — Typ† 0.PIC12F629/675 12.9 0.5 7. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit.5 17 70 130 6.3 6.0 5.0 5.0 5. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. BOD.1 11. 2: The power-down current in Sleep mode does not depend on the oscillator type.4 58 109 3.5 3.0 2.0 5.5 8.0 3.0 5.

0 2. Other factors such as I/O pin loading and switching rate.8 180 320 580 2.0 2.1 2.0 FOSC = 20 MHz HS Oscillator Mode FOSC = 4 MHz EXTRC Mode FOSC = 4 MHz INTOSC Mode FOSC = 4 MHz EC Oscillator Mode FOSC = 1 MHz EC Oscillator Mode FOSC = 4 MHz XT Oscillator Mode FOSC = 1 MHz XT Oscillator Mode Note FOSC = 32 kHz LP Oscillator Mode † Data in “Typ” column is at 5. pulled to VDD. These parameters are for design guidance only and are not tested.0 2. and temperature also have an impact on the current consumption.0 3. MCLR = VDD.6 70 140 260 180 320 580 340 500 0.1 250 450 800 2. all I/O pins tri-stated.0 5.0 3.0 3.0 5.0 5. internal code execution pattern.0 2. D010E Device Characteristics Supply Current (IDD) Min — — — D011E — — — D012E — — — D013E — — — D014E — — — D015E — — — D016E — — — D017E — — Typ† 9 18 35 110 190 330 220 370 0.0 5. 2: The supply current is mainly a function of the operating voltage and frequency.0 2.4 Max 16 28 54 150 280 450 280 650 1.95 3.0 4.0 5.  2010 Microchip Technology Inc. DS41190G-page 91 .5 5.0 3.0 3. 25C unless otherwise stated.4 110 250 390 250 470 850 450 780 1. oscillator type. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave.PIC12F629/675 12.0 3.0 3.0 2. from rail-to-rail.0 5.0 5.0V.0 Units A A A A A A A A mA A A A A A A A A mA A A A mA mA Conditions VDD 2. WDT disabled.4 DC Characteristics: PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +125C for extended Param No.

D020E Device Characteristics Power-down Base Current (IPD) Min — — — D021E — — — D022E D023E — — — — — D024E — — — D025E — — — D026E — — Typ† 0.0 2.0 5. Comparators.0 2. 25C unless otherwise stated.5 4.0 5.0022 Max 3.PIC12F629/675 12.0 3. DS41190G-page 92  2010 Microchip Technology Inc.0 3.0 8. 2: The power-down current in Sleep mode does not depend on the oscillator type.0 A/D Current(1) T1 OSC Current(1) CVREF Current(1) Comparator Current(1) BOD Current(1) WDT Current(1) Note WDT. BOD.5 58 85 138 4. Max values should be used when calculating total current consumption. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled.0 3.0 3.0012 0.0 8.0 9.0 3.0 5.0029 0.0 20 70 130 10 13 24 70 100 165 10 12 20 6.0 6.0 5.3 1.4 58 109 3.00099 0.0 5. VREF.5 Units A A A A A A A A A A A A A A A A A A A Conditions VDD 2.0 5.0V.3 6.0 5. These parameters are for design guidance only and are not tested.0012 0.8 8.0 3. and T1OSC disabled † Data in “Typ” column is at 5. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Power-down current is measured with the part in Sleep mode. .5 DC Characteristics: PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +125C for extended Param No.0 2.6 6.0 2.0 0.0 4. with all I/O pins in high-impedance state and tied to VDD.0 3.1 11.

5V  VDD 5.2 VDD 0. These parameters are for design guidance only and are not tested.5V otherwise entire range (Note 1) (Note 1) VDD = 5. HS and LP osc configuration IOL = 8.5V (Ext. VIL D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B D070 IPUR D060 D060A D060B D061 D063 IIL Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR.0 (0.7 — — — — V V * These parameters are characterized but not tested.5V (Ind.2 mA. Pin at high-impedance VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD VSS VPIN VDD.5V (Ind.25 VDD+0.5V (Ext.0V.6 DC Characteristics: PIC12F629/675-I (Industrial).) IOH = -3.) IOH = -1. Note 1: In RC oscillator configuration. 3: Negative current is defined as current sourced by the pin.5V (Ind.3 0.9 VDD GPIO Weak Pull-up Current 50* Input Leakage I/O ports Analog inputs VREF MCLR(2) OSC1 Output Low Voltage I/O ports OSC2/CLKOUT (RC mode) Output High Voltage I/O ports OSC2/CLKOUT (RC mode) Current(3) — — — — — 250 01 01 01 01 01 VDD VDD VDD VDD VDD VDD VDD 400* 1 1 1 5 5 V V V V V V A A A A A A 4. It is not recommended to use an external clock in RC mode.6 OSC1 (HS mode) 0.) D080 D083 VOL — — — — 0.3 mA. VPIN = VSS VSS VPIN VDD.2 VDD 0.0V.  2010 Microchip Technology Inc.8) with Schmitt Trigger buffer 0. The specified levels represent normal operating conditions.8 0. VDD = 4.6 mA. VDD = 4. VDD = 4.7 VDD .15 VDD 0. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level.PIC12F629/675 12. † Data in “Typ” column is at 5.0.8 VDD MCLR 0. VDD = 4.6 0.) IOH = -1.8 VDD OSC1 (XT and LP modes) 1. VDD = 4. XT. 25C unless otherwise stated.) IOL = 1. OSC1 (RC mode) OSC1 (XT and LP modes) OSC1 (HS mode) Input High Voltage I/O ports with TTL buffer VSS VSS VSS VSS VSS VSS — — — — — — — — — — — — — — 0.5V (Ind. PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Min Typ† Max Units Conditions DC CHARACTERISTICS Param Sym No. DS41190G-page 93 .5 mA.0.6 V V D090 D092 VOH VDD .0 mA.0 mA.3 VDD V V V V V V 4. VDD = 4.) IOL = 1. the OSC1/CLKIN pin is a Schmitt Trigger input. Higher leakage current may be measured at different input voltages.7 VDD OSC1 (RC mode) 0.5V  VDD  5.5V Otherwise Entire range (Note 1) (Note 1) 2.

5 2. These parameters are for design guidance only and are not tested. Sym D100 COSC2 — — 15* pF In XT.0V. HS and LP modes when external clock is used to drive OSC1 D101 D120 D120A D121 CIO ED ED VDRW All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write — 100K 10K VMIN — 1M 100K — 50* — — 5.5 — VPEW VDD for Erase/Write TPEW Erase/Write cycle time TRETD Characteristic Retention E/W -40C  TA +85°C E/W +85°C  TA +125°C V VMIN = Minimum operating voltage V ms Year Provided no other specifications are violated * These parameters are characterized but not tested.5 — 40 100K 10K — — 2 — — — 5. . † Data in “Typ” column is at 5. Note 1: See Section 8.1 “Using the Data EEPROM” for additional information.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Characteristic Capacitive Loading Specs on Output Pins OSC2 pin Min Typ† Max Units Conditions DC CHARACTERISTICS Param No.7 DC Characteristics: PIC12F629/675-I (Industrial).PIC12F629/675 12.5 5. DS41190G-page 94  2010 Microchip Technology Inc.5.5 pF E/W -40C  TA +85°C E/W +85°C  TA +125°C V Using EECON to read/write VMIN = Minimum operating voltage ms Year Provided no other specifications are violated E/W -40C  TA +85°C D122 D123 D124 TDEW Erase/Write cycle time TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(1) Program Flash Memory Cell Endurance Cell Endurance VDD for Read — 40 1M 5 — 10M 6 — — D130 D130A D131 D132 D133 D134 EP ED VPR 10K 1K VMIN 4. 25C unless otherwise stated. PIC12F629/675-E (Extended) (Cont.

8 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created with one of the following formats: 1. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-Impedance) L Low T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-Impedance FIGURE 12-4: LOAD CONDITIONS Load Condition 1 VDD/2 RL Load Condition 2 Pin VSS RL = 464 CL = 50 pF 15 pF CL Pin VSS CL for all pins for OSC2 output  2010 Microchip Technology Inc.PIC12F629/675 12. TppS2ppS 2. DS41190G-page 95 .

† Data in “Typ” column is at 5V. TosF External CLKIN Rise External CLKIN Fall Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. TOSC L/H duty cycle HS oscillator. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL. When an external clock input is used. TOSC L/H duty cycle LP oscillator XT oscillator HS oscillator Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period(1) 2 3 TCY TosL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. the ‘max’ cycle time limit is “DC” (no clock) for all devices. TosH Instruction Cycle Time(1) External CLKIN (OSC1) High External CLKIN Low 4 100 * — — ns — — 50* ns — — 25* ns — — 15* ns * These parameters are characterized but not tested. TosR. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin.1 1 27 50 50 250 27 — 250 250 50 200 2* 20* Typ† — — — — — 4 — — — — — — — 250 — — — TCY — — Max 37 4 20 20 37 — 4 4 20     200 — — 10.000 1. EXTENDED) EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 FIGURE 12-5: OSC1 1 2 CLKOUT 3 3 4 4 TABLE 12-1: Param No.PIC12F629/675 12. DS41190G-page 96  2010 Microchip Technology Inc. These parameters are for design guidance only and are not tested. 25°C unless otherwise stated. Sym FOSC EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKIN Frequency(1) Min DC DC DC DC 5 — DC 0. . TOSC L/H duty cycle XT oscillator.000 DC — — Units kHz MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns ns s ns Conditions LP Osc mode XT mode HS mode EC mode LP Osc mode INTOSC mode RC Osc mode XT Osc mode HS Osc mode LP Osc mode HS Osc mode EC Osc mode XT Osc mode LP Osc mode INTOSC mode RC Osc mode XT Osc mode HS Osc mode TCY = 4/FOSC LP oscillator.

These parameters are for design guidance  2010 Microchip Technology Inc.5V VDD  5.5V. F10 Sym FOSC PRECISION INTERNAL OSCILLATOR PARAMETERS Characteristic Internal Calibrated INTOSC Frequency Freq. -40C to +85C s VDD = 3.5V -40C  TA  +85C (IND) -40C  TA  +125C (EXT) s VDD = 2.00 4.PIC12F629/675 TABLE 12-2: Param No. -40C to +85C s VDD = 5. TIOSCST Oscillator Wake-up from 6 4 3 8 6 5 MHz VDD = 3.0V.92 3. † Data in “Typ” column is at 5.80 Typ† 4.5V 0C  TA  +85C MHz 2.0V VDD  5.00 4. Min Tolerance 1 2 5 3.08 4.0V.04 4.96 3.0V. 25C unless otherwise only and are not tested. 25C MHz 2.0V.20 Units Conditions F14 — — — — Sleep start-up time* — — * These parameters are characterized but not tested.00 Max 4. -40C to +85C stated. DS41190G-page 97 .

DS41190G-page 98  2010 Microchip Technology Inc. Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.0V. . 10 11 12 13 14 15 16 17 18 19 20 21 22 23 * † CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic Min — — — — — TOSC + 200 ns 0 — — TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) 100 0 — — 25 TCY Typ† 75 75 35 35 — — — 50 — — — 10 10 — — Max 200 200 100 100 20 — — 150 * 300 — — 40 40 — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) TosH2ckL OSC1 to CLOUT TosH2ckH OSC1 to CLOUT TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid TioV2osH Port input valid to OSC1 (I/O in setup time) TioR TioF Tinp Trbp Port output rise time Port output fall time INT pin high or low time GPIO change INT high or low time These parameters are characterized but not tested. Data in “Typ” column is at 5. 21 15 New Value 19 22 23 18 12 16 Q1 Q2 11 Q3 TABLE 12-3: Param No.PIC12F629/675 FIGURE 12-6: CLKOUT AND I/O TIMING Q4 OSC1 10 CLKOUT 13 14 I/O pin (Input) 17 I/O pin (Output) Old Value 20. 25C unless otherwise stated.

PIC12F629/675 FIGURE 12-7: RESET. WATCHDOG TIMER. OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins 33 32 30 31 34 FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD BVDD (Device not in Brown-out Detect) (Device in Brown-out Detect) 35 Reset (due to BOD) 72 ms time-out(1) Note 1: 72 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.  2010 Microchip Technology Inc. DS41190G-page 99 .

These parameters are for design guidance only and are not tested. -40°C to +85°C Extended temperature TOSC = OSC1 period VDD = 5V. 25°C unless otherwise stated.025 TBD 100* — — — 2. .PIC12F629/675 TABLE 12-4: Param No. WATCHDOG TIMER. † Data in “Typ” column is at 5V. AND BROWN-OUT DETECT REQUIREMENTS Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Detect Voltage Brown-out Hysteresis Brown-out Detect Pulse Width Min 2 TBD 10 10 — 28* TBD — Typ† — TBD 17 17 1024TOSC 72 TBD — Max — TBD 25 30 — 132* TBD 2. POWER-UP TIMER. -40°C to +85°C Extended Temperature TMCL TWDT 32 33* 34 TOST TPWRT TIOZ BVDD 35 TBOD 2. -40°C to +85°C Extended temperature VDD = 5V.175 — — V — s VDD  BVDD (D005) * These parameters are characterized but not tested.0 Units s ms ms ms — ms ms s Conditions VDD = 5V. 30 31 RESET. DS41190G-page 100  2010 Microchip Technology Inc. OSCILLATOR START-UP TIMER.

DS41190G-page 101 . 25°C unless otherwise stated.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0. with Prescaler Asynchronous 47* Tt1P T1CKI Input Period Synchronous Asynchronous Ft1 48 * † Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN) — — — — 200* 7 TOSC* ns kHz — TCKEZtmr1 Delay from external clock edge to timer increment These parameters are characterized but not tested. with Prescaler Asynchronous — — — — — — — — — — — — — — ns ns ns ns ns ns ns N = prescale value (1.5 TCY + 20 10 0. Data in “Typ” column is at 5V. 256) 45* Tt1H T1CKI High Time Synchronous.PIC12F629/675 FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 42 41 T1CKI 45 47 TMR0 or TMR1 46 48 TABLE 12-5: Param No. No Prescaler Synchronous.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 DC 2 TOSC* Typ† Max Units — — — — — — — — — — ns ns ns ns ns Conditions N = prescale value (2. 4. 40* 41* 42* TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Sym Tt0H Tt0L Tt0P Min 0. 4... .  2010 Microchip Technology Inc. 2. 8) 46* Tt1L T1CKI Low Time Synchronous.. No Prescaler Synchronous.5 TCY + 20 15 30 0. These parameters are for design guidance only and are not tested.

DS41190G-page 102  2010 Microchip Technology Inc.5 — 400* 10* Units mV V db ns s Comments Comparator Specifications Sym VOS VCM CMRR TRT Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time (1) TMC2COV Comparator Mode Change to Output Valid * These parameters are characterized but not tested. TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions -40°C to +125°C (unless otherwise stated) Min — — — — — — Typ VDD/24* VDD/32 — — 2k* — Max — —  1/2 1/2* — 10* Units LSb LSb LSb LSb  s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0) Voltage Reference Specifications Sym Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time (1) * These parameters are characterized but not tested.1.1. . Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.5)/2 while the other input transitions from VSS to VDD .PIC12F629/675 TABLE 12-6: COMPARATOR SPECIFICATIONS Standard Operating Conditions -40°C to +125°C (unless otherwise stated) Min — 0 +55* — — Typ  5.0 — — 150 — Max  10 VDD .5V. Note 1: Response time measured with one comparator input at (VDD .1.

5 VSS VSS — Typ† — — — — — — — guaranteed(3) Max 10 bits 1 1 1 5. † Data in “Typ” column is at 5. During A/D conversion cycle. it will not consume any current other than leakage current.0V Conditions LSb No missing codes to 10 bits VREF = 5.0V — V Absolute minimum to ensure 10-bit accuracy V V k VSS  VAIN  VREF+ — VREF VAIN ZAIN Reference V High (VDD or VREF) Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF Input Current(2) — — — A50 IREF 10 — — — 1000 10 A A During VAIN acquisition.PIC12F629/675 TABLE 12-8: Param No.0V V LSb VREF = 5. Based on differential of VHOLD to VAIN. A01 A02 A03 A04 A05 A06 A07 A10 A20 A20A A21 A25 A30 Sym NR EABS EIL EDL EFS EOFF EGN — VREF PIC12F675 A/D CONVERTER CHARACTERISTICS: Characteristic Resolution Total Absolute Error* Integral Error Differential Error Full Scale Range Offset Error Gain Error Monotonicity Reference Voltage Min — — — — 2.3 VDD VREF 10 Units bit LSb VREF = 5. * These parameters are characterized but not tested.0V LSb VREF = 5.0V.0 2. The power-down current spec includes any such leakage from the A/D module.0V LSb VREF = 5. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. DS41190G-page 103 .  2010 Microchip Technology Inc. 2: VREF current is from External VREF or VDD pin. whichever is selected as reference input. 25C unless otherwise stated. Note 1: When A/D is off. These parameters are for design guidance only and are not tested.5* 1 1 — — VDD + 0.2* — — — 2.

This allows the SLEEP instruction to be executed. VREF 3. These parameters are for design guidance only and are not tested. GO 134 Q4 (TOSC/2)(1) Note 1: If the A/D clock source is selected as RC.PIC12F629/675 FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE) 1 TCY 131 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0..0V Set GO bit to new data in A/D result register 131 TCNV 132 TACQ (Note 2) 5* 11. † Data in “Typ” column is at 5.6 3.0V TOSC based.0* 6.0* 3.1 “A/D Configuration and Operation” for minimum conditions. Note 1: ADRES register may be read on the following TCY cycle. This allows the SLEEP instruction to be executed. a time of TCY is added before the A/D clock starts. 25C unless otherwise stated.5 — — — s s The minimum time is the amplifier settling time.0 11 Max — — 9. VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2. 134 TGO Q4 to A/D Clock Start — TOSC/2 — — * These parameters are characterized but not tested.096V) from the last sampled voltage (as stored on CHOLD).5V At VDD = 5. If the A/D clock source is selected as RC.0V. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e.0* — Typ† — — 6. 2: See Section 7. TABLE 12-9: Param No. .0 4. 4.0* 2. DS41190G-page 104  2010 Microchip Technology Inc. 130 130 Sym TAD TAD PIC12F675 A/D CONVERSION REQUIREMENTS Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.0* — Units s s s s TAD Conditions TOSC based. a time of TCY is added before the A/D clock starts.1 mV @ 4.

2: See Section 7.1 mV @ 4. This may be used if the “new” input voltage has not changed by more than 1 LSb (i. TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param No.PIC12F629/675 FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0.0V. This allows the SLEEP instruction to be executed. Note 1: ADRES register may be read on the following TCY cycle. GO 134 Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE 132 SAMPLING STOPPED 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY)(1) 131 130 1 TCY OLD_DATA Note 1: If the A/D clock source is selected as RC. 134 TGO Q4 to A/D Clock Start — TOSC/2 + TCY — — * † These parameters are characterized but not tested.6 3.1 “A/D Configuration and Operation” for minimum conditions. If the A/D clock source is selected as RC.0* 6. 4.0* 2.5 — — — s s The minimum time is the amplifier settling time. 25C unless otherwise stated. a time of TCY is added before the A/D clock starts. These parameters are for design guidance only and are not tested..0V VREF full range ADCS<1:0> = 11 (RC mode) At VDD = 2.0V 132 TACQ (Note 2) 5* 11.  2010 Microchip Technology Inc. This allows the SLEEP instruction to be executed. 130 130 Sym TAD TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period Conversion Time (not including Acquisition Time)(1) Acquisition Time Min 1.096V) from the last sampled voltage (as stored on CHOLD).0* 3.e.0 11 Max — — 9. Data in “Typ” column is at 5.0* — Units s s s s TAD Conditions VREF 3.0 4. a time of TCY is added before the A/D clock starts. DS41190G-page 105 .5V At VDD = 5.0* 131 TCNV — Typ† — — 6.

.PIC12F629/675 NOTES: DS41190G-page 106  2010 Microchip Technology Inc.

5 4 4. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples.5 5.5 VDD (V) FIGURE 13-2: TYPICAL IPD vs. VDD OVER TEMP (+85°C) Typical Baseline IPD 3.0E-09 IPD (A) -40 0 25 3. the data presented are outside specified operating range (i. “Typical” represents the mean of the distribution at 25°C.0E-09 0. In some graphs or tables.5 VDD (V)  2010 Microchip Technology Inc.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. outside specified VDD range).0E+00 2 2. “Max” or “min” represents (mean + 3) or (mean ..0E-09 4.5 4.0E-09 1.0E-09 2.0 2.0E-09 5. over the whole temperature range.0E-07 5.0E-08 0.0E-07 85 1. FIGURE 13-1: TYPICAL IPD vs. DS41190G-page 107 .5E-07 1.0E+00 2.5 3.e. VDD OVER TEMP (-40°C TO +25°C) Typical Baseline IPD 6.0 4.0 5.0E-07 2.5E-07 IPD (A) 2.3) respectively.0 3. where  is standard deviation.PIC12F629/675 13.5 5 5. This is for information only and devices are ensured to operate properly only within the specified range.5 3 3.5E-07 3.

PIC12F629/675 FIGURE 13-3: TYPICAL IPD vs.5 -40 0 25 VDD (V) DS41190G-page 108  2010 Microchip Technology Inc.5 3 3.0E+00 2 2.5 4.0E-06 1.5 4 4.5E-06 2.0E-08 2.5 3.0E-08 5.5 5 5. VDD OVER TEMP (-40°C TO +25°C) Maximum Baseline IPD 1.0E+00 2.0E-08 4.0E-07 0.0E-06 3.5E-06 3.5 5. .0E-08 0.0E-06 IPD (A) 2.0 4.0E-06 5.0E-08 3.0E-07 9.0E-08 1. VDD OVER TEMP (+125°C) Typical Baseline IPD 4.0E-08 7.5E-06 1.0 3.5 125 VDD (V) FIGURE 13-4: MAXIMUM IPD vs.0E-08 IPD (A) 6.0E-08 8.0 5.0 2.

0 4.0E-07 7.5 4.0 4.0E-06 1.0E+00 2.0E+00 2.5 5.0E-06 6.PIC12F629/675 FIGURE 13-5: MAXIMUM IPD vs.0E-07 1. VDD OVER TEMP (+85°C) Maximum Baseline IPD 9.0E-06 5.5 125 IPD (A) VDD (V)  2010 Microchip Technology Inc.0E-06 3.0E-07 8.0 2.0E-07 0.0E-07 3.5 5.0E-07 6.0 3.0E-06 4.0 5.0 2.0 3.5 3. VDD OVER TEMP (+125°C) Maximum Baseline IPD 9.0E-06 8.0E-06 2.0 5. DS41190G-page 109 .0E-07 2.5 3.0E-07 5.5 85 IPD (A) VDD (V) FIGURE 13-6: MAXIMUM IPD vs.0E-07 4.0E-06 0.0E-06 7.5 4.

5 VDD (V) DS41190G-page 110  2010 Microchip Technology Inc.5 3. VDD OVER TEMP (-40°C TO +125°C) Typical BOD IPD 130 120 110 -40 0 25 85 125 IPD (uA) 100 90 80 70 60 50 3 3.6E-05 1.0E-06 2.8E-05 1.5 5.0 3.4E-05 1.0 5.5 4 4.5 VDD (V) FIGURE 13-8: TYPICAL IPD WITH CMP ENABLED vs.0E-06 6.0 2.5 5 5.0 4.0E-06 4.0E+00 2.2E-05 -40 0 25 85 125 IPD (A) 1.5 4.0E-06 0. .0E-05 8.PIC12F629/675 FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical Comparator IPD 1.

PIC12F629/675 FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs.5 5 5.5 4 4.5 5 5.5 VDD (V)  2010 Microchip Technology Inc. VDD OVER TEMP (-40°C TO +25°C) Typical A/D IPD 5.5E-09 1.5 IPD (A) -40 0 25 VDD (V) FIGURE 13-10: TYPICAL IPD WITH A/D ENABLED vs.5 3 3.0E-08 0.5E-09 2.5E-09 3.5E-07 1.0E-07 85 1.0E+00 2 2.0E-09 3.0E-07 5.0E-07 2.0E-09 4.0E-09 5.5 4 4. DS41190G-page 111 .5 3 3.0E-09 1.0E-10 0. VDD OVER TEMP (+85°C) Typical A/D IPD 3.5E-09 4.0E+00 2 2.5E-07 IPD (A) 2.0E-09 2.5E-07 3.

C1 AND C2=50 pF) Typical T1 IPD 1.00E-06 -40 0 25 85 125 IPD (A) 6.00E+00 2.5 3.5E-06 3. .5E-06 1.0E-07 0.00E-06 4.5 5.5 5 5.00E-06 2.0 2. VDD OVER TEMP (+125°C) Typical A/D IPD 3. 32 kHZ.0E+00 2 2.5 4 4.0E-06 IPD (A) 2.00E-06 0.5 4.5 VDD (V) FIGURE 13-12: TYPICAL IPD WITH T1 OSC ENABLED vs.00E-05 8.0E-06 5. VDD OVER TEMP (-40°C TO +125°C).5 VDD (V) DS41190G-page 112  2010 Microchip Technology Inc.20E-05 1.0 3.PIC12F629/675 FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs.0 5.0E-06 125 1.5 3 3.0 4.5E-06 2.

DS41190G-page 113 .5 5 5.5 3 3.5 4 4. VDD OVER TEMP (-40°C TO +125°C) Typical WDT IPD 16 14 12 -40 0 25 85 125 IPD (uA) 10 8 6 4 2 0 2 2.5 3 3.5 4 4.5 -40 0 25 85 125 VDD (V) FIGURE 13-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical CVREF IPD 160 140 IPD (uA) 120 100 80 60 40 2 2.5 5 5.PIC12F629/675 FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs.5 V DD (V)  2010 Microchip Technology Inc.

5V 4.90E+06 3.05E+06 4.01F DECOUPLING (VDD = 3.95E+06 3. .1F AND 0.10E+06 4.0V 5.0V 4.5V 5.5V 3.85E+06 3.00E+06 3.95E+06 3.80E+06 -40°C 0°C 25°C 85°C 125°C -3sigma average +3sigma Temperature (°C) FIGURE 13-16: MAXIMUM AND MINIMUMINTOSC FREQ vs.80E+06 2.05E+06 4.85E+06 3.5V) Internal Oscillator Frequency vs Temperature 4.1F AND 0.5V -3sigma average +3sigma VDD (V) DS41190G-page 114  2010 Microchip Technology Inc.00E+06 3. VDD WITH 0. TEMPERATURE WITH 0.15E+06 4.20E+06 4.10E+06 4.01F DECOUPLING (+25°C) Internal Oscillator Frequency vs VDD 4.0V 3.15E+06 Frequency (Hz) 4.20E+06 Frequency (Hz) 4.PIC12F629/675 FIGURE 13-15: MAXIMUM AND MINIMUMINTOSC FREQ vs.90E+06 3.0V 2.

5 5 5.PIC12F629/675 FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40C TO +125C) WDT Time-out 50 45 40 35 30 25 20 15 10 5 0 2 2.5 4 4.5 -40 0 25 85 125 Time (mS) V DD (V)  2010 Microchip Technology Inc.5 3 3. DS41190G-page 115 .

PIC12F629/675 NOTES: DS41190G-page 116  2010 Microchip Technology Inc. .

 2010 Microchip Technology Inc.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (Skinny DIP) XXXXXXXX XXXXXNNN YYWW Example 12F629-I /017 e3 0215 8-Lead SOIC XXXXXXXX XXXXYYWW NNN Example 12F629-E /0215 e3 017 8-Lead DFN-S XXXXXXX XXXXXXX XXYYWW NNN Example 12F629 -E/021 e3 0215 017 8-Lead DFN (4x4 mm) XXXXXX XXXXXX YYWW NNN Example XXXXXX XXXX 0610 017 e3 Legend: XX.PIC12F629/675 14. In the event the full Microchip part number cannot be marked on one line. thus limiting the number of available characters for customer-specific information.0 14.X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. it will be carried over to the next line.. DS41190G-page 117 .. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.

/HDG 3ODVWLF 'XDO .PIC12F629/675 14.Q/LQH 3.2 Package Details The following sections give the technical details of the packages.

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No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings. please see the Microchip Packaging Specification located at http://www.PIC12F629/675 8-Lead Plastic Dual Flat.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2  2010 Microchip Technology Inc. DS41190G-page 123 .

com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 DS41190G-page 124  2010 Microchip Technology Inc.microchip. . No Lead Package (MD) – 4x4x0.PIC12F629/675 8-Lead Plastic Dual Flat.9 mm Body [DFN] Note: For the most current package drawings. please see the Microchip Packaging Specification located at http://www.

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DS41190G-page 125 . ± [[ PP %RG\ >')1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ  2010 Microchip Technology Inc.

.PIC12F629/675 NOTES: DS41190G-page 126  2010 Microchip Technology Inc.

 2010 Microchip Technology Inc. Revision F (09/2009) Updated Registers to new format. Added information to the “Package Marking Information” (8-Lead DFN) and “Package Details” sections (8-Lead Dual Flat. TABLE B-1: Feature DEVICE DIFFERENCES PIC12F629 PIC12F675 A/D No Yes Revision C Revision D (01/2007) Updated Package Drawings. Revision G (03/2010) Updated the Instruction Set Summary section. Revision B Added characterization graphs. Revised Product ID example (b). DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1. adding pages 76 and 77. Replaced Development Support Section. Replace PICmicro with PIC. Revision E (03/2007) Replaced Package Drawings (Rev. AM). Added MD Package to the Product identification System chapter. Updated MLF-S package name to DFN-S. Other minor corrections. Updated specifications. Updated Register 3-2. Added notes to indicate Microchip programmers maintain all Calibration bits to factory settings and the PIC12F675 ANSEL register must be initialized to configure pins as digital I/O. Added Land Patterns for SOIC (SN) and DFN-S (MF) packages.9 mm Body (DFN)). DS41190G-page 127 . No Lead Package (MD) 4X4X0.PIC12F629/675 APPENDIX A: Revision A This is a new data sheet.

D. Due to process differences in the manufacture of this device. Note: The user should verify that the device oscillator starts and performs as expected.PIC12F629/675 APPENDIX C: DEVICE MIGRATIONS APPENDIX D: This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). It has been tested to an electrical specification designed to determine its conformance with these parameters. These differences may cause this device to perform differently in your application than the earlier version of this device.1 PIC12C67X to PIC12F6XX FEATURE COMPARISON PIC12C67X PIC12F6XX TABLE 1: Feature Max Operating Speed Max Program Memory A/D Resolution Data EEPROM Oscillator Modes Brown-out Detect Internal Pull-ups Interrupt-on-change Comparator Note: 10 MHz 2048 bytes 8-bit 16 bytes 5 N GP0/1/3 GP0/1/3 N 20 MHz 1024 bytes 10-bit 64 bytes 8 Y GP0/1/2/4/5 GP0/1/2/3/4/5 Y This device has been designed to perform to the parameters of its data sheet. DS41190G-page 128  2010 Microchip Technology Inc. . Adjusting the loading capacitor values and/ or the oscillator mode may be required. this device may have different performance characteristics than its earlier version. Not Applicable MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F6XX family of devices.

...................................................................................... 69 Indirect Addressing.............................. 71 Instruction Set............. 26 On-Chip Reset Circuit ............................................................................. 69 In-Circuit Serial Programming............. 47 Configuration and Operation................ 47 Comparator Output .......................................................................................................... 21 Saving STATUS and W Registers in RAM ............................................. 56 Code Examples Changing Prescaler ............................................................................................................. 128 Device Overview...................... 51 Data EEPROM Write ............. 69 In-Circuit Debugger....................................... 60 Brown-out Detect (BOD) ........... 21 C C Compilers MPLAB C18 ........................................................................... 69 Comparator ................................................................ 41 Response Time ........................................................ 47 Block Diagram...............................PIC12F629/675 INDEX A A/D .............. 43 Acquisition Requirements ....... 48 Absolute Maximum Ratings .................... 49 EEDATA Register.......................... 41 Output................. 51 Writing ..... 93 Industrial ............................................................................................................................................................... 9 GPIO Associated Registers...................... 21 GPIO....................................... 51 Code Protection . 21 Analog Input Connection Considerations.................................................................................................. 52 Code Protection................. TRISIO Registers... 7 B Block Diagram TMR0/WDT Prescaler.............................................................. 41 Comparator Specifications.................................................. 41 Crystal Operation..................................................... 67 Brown-out Associated Registers .............. 21 GPIO Port ................ 88 Development Support ............................ 25 GP3... 85 AC Characteristics Industrial and Extended .......................... 39 I ID Locations.......................................... 9 DC Characteristics Extended and Industrial............................... INDF and FSR Registers .............................. 49 EECON1 Register ........................................................... 20 Instruction Format....... 56 Timer1...................................................... 73 ANDWF ........................... 23 Weak Pull-up.............................................. DS41190G-page 129 ........................................................................... 49 Data Memory Organization............................ 32 Watchdog Timer....................... 127 Device Migrations ...... 24 GP2............................................................................................................. 57 RC Oscillator Mode........................ 43 Calculating Acquisition Time................................................................................................................................................................................................................................................... 51 Electrical Specifications ......................................... 42 Configuration......................................... 47 Summary of Registers ............ 51 Write Verify .......... 51 Initializing GPIO ................................... 133 Customer Notification Service ................................... 39 Effects of a RESET .................................................................. 29 Block Diagrams Analog Input Mode................... 103 Source Impedance......... 41 GP0 and GP1 Pins............................................................................................................................... 71 ADDLW.................................. 40 Analog-to-Digital Converter.......................................................................................................................................................................... 40 Comparator Voltage Reference .................................... 43 Effects of a RESET ............. 42 Operation...... 97 CLKOUT ........................................................................................................................................................................... 76  2010 Microchip Technology Inc....................... 40 Reference ........................................................................... 81 Device Differences............................................................................................................................................................ 73 ADDWF .................................................................................................................................................................................. 27 GPIO — GPIO register (ADDRESS 05H)....................................... 66 Write Verify ......... 59 Brown-out Detect Timing and Characteristics....................................................................................................................................................................................................................... 49 EECON2 Register ........... 49 EECON1 — EEPROM Control register (Address 9Ch).......................................... 82 Calibrated Internal RC Frequencies.... 38 Operation During SLEEP......................... 47 Operation During SLEEP . 133 Customer Support................ 85 Errata ..... 99 E EEADR — EEPROM Address Register (ADDRESS 9Bh) ......................... 37 Associated Registers ................. 31 Data EEPROM Read .................. 102 Comparator Voltage Reference Specifications....................................... 73 ANDLW.......................................................................................................................................................................................................... 48 PIC12F675 Converter Characteristics ..................................... 51 Spurious Write ................................. 50 EEPROM Data Memory Reading ......... 96 ADCON0 A/D Control register (ADDRESS 1Fh) ........................................................................................................... 102 Configuration Bits .................................................................................................................................................................................................... 55 Customer Change Notification Service.......................... 25 GP4.......................................................................................................................................................................................... 52 EEADR Register.. 26 GP5............... 82 Interrupts .............................................................................................................................. 5 F Firmware Instructions ............................................................... 40 Analog Input Model ....................................................................................................................................................................................................... See A/D Assembler MPASM Assembler............................... 45 Additional Pin Functions .......................................................................................... 21 Interrupt-on-Change............... 48 Internal Sampling Switch (Rss) Impedance .............. 73 MOVF .................................................................................. 41 I/O Operating Modes................................................................................................................................................ 133 D Data EEPROM Memory Associated Registers/Bits..................................................................................................................................................... 71 G General Purpose Register File ........... 54 Configuring the Voltage Reference..........................

............................................................................................ 35 Prescaler ............................................................................. 9 Programming.... 58 Power-up Timer (PWRT) .................................................................................. 19 Computed GOTO ..................................................... 23 Stack........................... 18 PCON (Power Control) .............. 49 Microchip Internet Web Site .......... 75 INCFSZ ........ 65 IOC — INTERRUPT-ON-CHANGE GPIO register (ADDRESS 96h) ............. 133 Interrupts .......................... 74 BTFSS ..................... 66 GP2/INT ............................................. 78 SUBWF ......................................... 71 Registers ANSEL (Analog Select) ..................... 19 DS41190G-page 130  2010 Microchip Technology Inc............................................................................................................ 77 RETLW ......... 58 Memory Organization Data EEPROM Memory.................................................... 57 Revision History............................ 24 Pinout Descriptions PIC12F629 .................................. 75 IORWF ......... 33 Operation During SLEEP....................................................................................................................................................................................................... 77 RLF ............................................................................................................................................................... 65 GPIO ................................. 78 SWAPF .... 18 PIE1 (Peripheral Interrupt Enable 1)................................................. 30..... 24 Maps PIC12F629 ..................................................................................................... 19 Pin Descriptions and Diagrams ...................................................................................................................................... 71 Oscillator Configurations ................................................................. 79 XORWF................... 76 RETFIE . 58 P Packaging ................................................................ 75 MOVLW ................................. 82 MPLAB Integrated Development Environment Software ................................ 117 PCL and PCLATH .............................................. 10 Special Functions Registers Summary........ 75 GOTO ........................................................ 118 Marking ............................. 34 VRCON (Voltage Reference Control) ....... 35 Asynchronous Counter Mode ........................... Linker. 73 BSF .............. 55 Oscillator Start-up Timer (OST) ...........................................................................PIC12F629/675 BCF ........................................... 78 SUBLW .......................... 74 DECFSZ. 82 T Time-out Sequence ............................................................................................... 35 Interrupt ......................................................................... 73 CALL ...................... 31 External Clock............................................................................................................................................................. 74 CLRW ................ 23 RESET............................................................................................. 72 Internal 4 MHz Oscillator...................................... 29 Associated Registers .................................................................................................................. 117 Details ............................................................... 65 Context Saving...................................... 10 PIC12F675 ........................................... 13 M MCLR ..... 73 BTFSC ............................... 31 Program Memory Organization.................................. 133 Migrating from other PICmicro Devices ............................ 68 Power-on Reset (POR).......................................................................................................................................... 14................................................................................................................................................................................................................................................................................. 59 Power-Down Mode (SLEEP) .............................................................................. 76 NOP .......... 74 CLRF........................................... 66 TMR0 ............................................ 42 WPU (Weak Pull-up)............................................ .................................................................. 134 READ-MODIFY-WRITE OPERATIONS .............. 78 XORLW ................................................................... 33 Modes of Operations .................................................................................... 127 S Software Simulator (MPLAB SIM) ................................................................................................................................................... 56 Internal Sampling Switch (Rss) Impedance ...................................................... 65 Comparator ........ 31 OSCCAL (Oscillator Calibration) .................................................................. 74 COMF .. Device Instructions............................................................................................................ 128 MPLAB ASM30 Assembler................. 14 T1CON (Timer1 Control) ......................... 49 INTCON (Interrupt Control)..................... 31 Switching Prescaler Assignment .......................................... 71 R RC Oscillator.. 78 RRF........................................................................................ 10 OPTION_REG (Option) ............................. 11 STATUS — STATUS Register (ADDRESS 03h or 83h) ............................................................................................................................................ 83 MPLINK Object Linker/MPLIB Object Librarian ............................................................................. 8 PIC12F675 .................................................................................. 78 SLEEP .................................................................................. 75 IORLW ......................................... 35 Reading and Writing ................................................................ 47 Internet Address.................................. 53 Special Function Registers ................... 81 MPLAB PM3 Device Programmer........ 65 Summary of Registers ...................................... 74 CLRWDT................................. 51 EEDAT (EEPROM Data) ................................ 83 Special Features of the CPU ............ 8 Power Control/Status Register (PCON)............ 58 Prescaler................................................................................................................................................................................... 32 Timing Diagrams O OPCODE Field Descriptions ................................................................................. 77 RETURN .............................................................................. 75 INCF.............................................. 63 A/D Converter .................................. 29 T0CKI ................................................................................ 33 Timer1 Module with Gate Control ..... 76 MOVWF ............................... 84 MPLAB REAL ICE In-Circuit Emulator System..................... 56 Reader Response........................................... 79 Summary Table....................................................................................................................................................................... 74 DECF ............................................................................................................................................................................................................................................................................................................................................................................................................................................ 46 CONFIG (Configuration Word) ............................ 54 EEADR (EEPROM Address) ......... 17 STATUS ... 15 IOCB (Interrupt-on-Change GPIO) ................................. Librarian ............................................................ 59 Timer0........................................................................ 50 EECON1 (EEPROM Control) ............ 29 Operation ............................................. 30 Timer1 Associated Registers ......................................... 16 PIR1 (Peripheral Interrupt 1)......................................... 35 Oscillator.............. 30 Interrupt .....................................................

.......... On-Line Support ......................................... Watchdog Timer................................................................................ 95 TRISIO — GPIO Tri-state REGISTER (Address 85H) ................................................................................ 62 Case 2 ...................................................................................................................................................... 33 Timing Parameter Symbology.. 96 INT Pin Interrupt............................................................ 101 Timer1 Incrementing Edge................................................ 62 Time-out Sequence on Power-up (MCLR Tied to VDD)........... 22 WWW Address..... 99 Time-out Sequence on Power-up (MCLR not Tied to VDD)/ Case 1 ....................................................... 62 Timer0 and Timer1 External Clock ................ 105 RESET............................................................................................................................. Oscillator Start-up Timer and Power-up Timer ............................................ DS41190G-page 131 ....... 65 PIC12F675 A/D Conversion (Normal Mode)............................................................. 104 PIC12F675 A/D Conversion Timing (SLEEP Mode) ...................... 41 W Watchdog Timer Summary of Registers ............................... 67 Watchdog Timer (WDT) .................... 5  2010 Microchip Technology Inc...........................PIC12F629/675 CLKOUT and I/O..... 98 External Clock....................................... 133 WWW............................. 22 V Voltage Reference Accuracy/Error ...................... 66 WPU — Weak pull-up Register (ADDRESS 95h)...................

.PIC12F629/675 NOTES: DS41190G-page 132  2010 Microchip Technology Inc.

the web site contains the following information: • Product Support – Data sheets and errata. Accessible by using your favorite Internet browser. This web site is used as a means to make files and information easily available to customers. Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides. listing of seminars and events. latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ). latest Microchip press releases. A listing of sales offices and locations is included in the back of this document. Subscribers will receive e-mail notification whenever there are changes. distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor. DS41190G-page 133 . online discussion groups. design resources. technical support requests.com. click on Customer Change Notification and follow the registration instructions. Local sales offices are also available to help customers.microchip.microchip. user’s guides and hardware support documents. application notes and sample programs. representative or field application engineer (FAE) for support. revisions or errata related to a specified product family or development tool of interest. updates.  2010 Microchip Technology Inc. access the Microchip web site at www. Technical support is available through the web site at: http://support.PIC12F629/675 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.com. To register. listings of Microchip sales offices.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products.microchip.

What are the best features of this document? Y N Literature Number: DS41190G FAX: (______) _________ . Do you find the organization of this document easy to follow? If not. How does this document meet your hardware and software development needs? 3. please FAX your comments to the Technical Publications Manager at (480) 792-4150. Is there any incorrect or misleading information (what and where)? 7. What deletions from the document could be made without affecting the overall usefulness? 6. and use this outline to provide us with your comments about this document. and ways in which our documentation can better serve you._________ Application (optional): Would you like a reply? Device: PIC12F629/675 Questions: 1. If you wish to provide your comments on organization. How would you improve this document? DS41190G-page 134  2010 Microchip Technology Inc.PIC12F629/675 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. . subject matter. why? 4. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ . Please list the following information._________ 2. clarity. What additions to the document do you think would enhance the structure and subject? 5.

E/P 301 = Extended Temp.PIC12F629/675 PRODUCT IDENTIFICATION SYSTEM To order or obtain information. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) PIC12F629 . Device: PIC12F6XX: Standard VDD range PIC12F6XXT: (Tape and Reel) I E P SN MF MD = -40C to +85C = -40C to +125C = = = = (Industrial) (Extended) Temperature Range: Package: PDIP SOIC (Gull wing.  2010 Microchip Technology Inc. QTP pattern #301. 20 MHz..I/SN = Industrial temp.90 mm body) MLF-S 8-Lead Plastic Dual Flat. e. 20 MHz. refer to the factory or the listed sales office. No Lead (4X4) (DFN) Pattern: 3-Digit Pattern Code for QTP (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. PART NO. PDIP package. SOIC package. 3. PIC12F675 . on pricing or delivery..g. JW Devices meet the electrical requirement of each oscillator type. DS41190G-page 135 ..

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