CSUS COLLEGE OF ENGINEERING AND COMPUTER SCIENCE
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EEE 102L – Analog/Digital Electronics Laboratory Laboratory Manual
Table of Contents
EEE 102L Analog/Digital Electronics Laboratory – Course Outline EEE 102L Parts Kit – Fall 2004 Objectives and Goals of the Laboratory Laboratory 1 – Introductory PSpice Programming Assignment Laboratory 2 – Introduction to LabVIEW Notes Concerning the Operation of the HP Signal Generators Laboratory 3 – Exploration of Diode Characteristics Laboratory 4 – Diode Circuits Laboratory 5 – MOSFET Transistor Characteristics Laboratory 6 – BJT Transistor Characteristics Laboratory 7 – Common-Emitter Amplifier Design Laboratory 8 – OP Amp Instrumentation Amplifiers and First Order Filters Appendix 3 5 6 9 10 19 20 24 27 31 35 37 41
EEE 102L Analog/Digital Electronics Laboratory
Service Course 2006 – 2008 Catalog Data: EEE 102L. Analog/Digital Electronics Laboratory. Introduction to analog/digital
electronics, diodes, FET's, BJT's, DC biasing, VI characteristics, single stage amplifiers, power supplies and voltage regulators, power electronic devices, OP-amps, active filters, A/D and D/A converters. PSPICE used extensively. Note: Cannot be taken for credit by E&EE Majors. Prerequisite: ENGR 017. Corequisite: EEE 102. 1 unit.
Text: Jaeger, R.C., Microelectronic Circuit Design, 2nd Edition, McGraw-Hill, 2004, ISBN 0-07-232099-0 Support Software: Herniter, M.E., Schematic Capture with Cadence PSpice, Prentice-Hall, 2nd Edition, 2003,
1. 2. To reinforce learning in the accompanying EEE 102 course through hands-on experience with electronic circuit analysis, design, construction, and testing. To provide the student with the capability to use LabVIEW and PSpice software as tools in electronic circuit analysis and design, and in future courses, design projects, and professional work assignments.
Prerequisites by Topic:
1. 2. 3. General knowledge of a structured programming language (i.e. C++). Basic physical concepts of electricity and magnetism. Basic circuit analysis concepts and procedures.
Topics Covered/Class Schedule/Evaluation: Topics
1. 2. 3. 4. 5. 6. Introduction to Software Tools and Workstation Equipment: Introduction to PSpice Schematic Circuit Construction and Analysis; Introduction to LabVIEW Virtual Instrument Workstation Operation and A/D Conversion Solid State Diodes and Diode Circuits: Diode Characteristics in Forward and Reverse Bias Conditions; Power Supplies and Wave Shaping Circuits Field Effect Transistors: FET Characteristics; Operating Regions and Characteristics of NMOS Devices; MOSFET Biasing Circuits, Analysis, Design, Construction, Testing, and Simulation Bipolar Junction Transistors: Operating Regions and Characteristics of the BJT; Forward-Active Region Analysis and Design; BJT Biasing Circuits, Analysis, Design, Construction, Testing, and Simulation Small-Signal Modeling and Linear Amplification: The BJT Common-Emitter Amplifier Analysis, Design, Construction, Testing and Simulation Operational Amplifiers: The Differential Amplifier; Frequency Response; Input/Output Impedance; Instrumentation Amplifiers; Common Mode Signal Analysis; Active Filters
Week 1 2 Topic Introduction to the Lab Introduction to PSpice Lab # none 1 Report Due
3 Introduction to LabVIEW VI Operations 2 _____________________________________________________________________________________________ 4 Diode Characteristics 1 3 R (Labs 1 & 2) 5 Diode Characteristics 2 3 6 Diode Circuits 1 4 7 Diode Circuits 2 4 8 Field Effect Transistor Characteristics 5 R (Labs 3 & 4) 9 FET Bias Circuits 5 10 Bipolar Junction Transistor Characteristics 6 11 BJT Bias Circuits 6 -------------------------------------------------------------------------------------------------------------------------------------------12 C-E Amplifier Design and Simulation 7 R (Labs 5 & 6) 13 C-E Amplifier Construction & Testing 7 14 Op-Amp Instrumentation Amplifier 8 15 Op-Amp Bandpass Filter 8 Exam Week R (Labs 7 & 8) --------------------------------------------------------------------------------------------------------------------------------------------
Laboratory Reports: Eight formal laboratory reports are required. Note that they are due two at a time according to the schedule above. The first six count 10 points each; the last two count 20 points each for a total of 100 points. Reports will be graded based upon written quality, format, content, and correct data analysis. Late reports will have 1 point deducted for the first week that they are late, and will NOT be accepted for credit after that week. Plagiarized reports will NOT be accepted.
Science and Design Content Distribution:
Design – 1 unit or 100%
Contribution of Course to the Professional Education Component:
1. 2. Laboratory exercises include practical electronic circuit design and analysis problems with realistic source and load constraints. Actual circuit construction and testing are emphasized equally with simulation LabVIEW and PSpice analysis and design applications introduce students to major professional engineering software tools.
Relationship of Course to Program Outcomes:
1. 2. #4 Knowledge of Engineering core: This course adds electronic circuit analysis and design applications to fundamental concepts of circuit analysis, and computer programming. #7 Use of contemporary tools for analysis and design: This course applies computer methods using PSpice and LabVIEW software tools to electronic circuit analysis and design.
Course Coordinator: John Oldenburg, EEE
Date: January 15, 2007
but not included in the kit.2Κ Ω 1.1 µF Ceramic Disc.8Κ Ω 8. 250 V (Digikey P10979-ND) 10 µF Metallized Poly Film. 1 1 Description 2N2222A NPN Transistor (TO-9) IRF630A NMOS FET Power Transistor
Integrated Circuits Qty. 500 V 2200 pF Ceramic Disc.2Κ Ω 3. 1 1 3 1 Description 1N4001 Si Rectifier W005G Bridge Rectifier 1N914 Si Switching Diode 1N4734A 5.01 µF Ceramic Disc. 5' 5' 2 Description 22AWG Hook-up Wire. 500 V 0.1Κ Ω 6. 100 0. 25 V 1000 µF Radial Electrolytic. 5% Qty. 50 V 1 µF Metallized Poly Film.EEE 102L Parts Kit – Spring 2005 Resistors 1/4 W. 16 V
Diodes/Rectifiers Qty. Newark or Fry’s Electronics
. 1W Zener Diode
Transistors Qty. 2 1 1 2 2 1 1 1 2 1 1 2 1 4 1 1 2 1 1 6 1 6 2 2 2 1 1 4 1 4 2 2 2 1 1 2 2 2 Value 10 Ω 15 Ω 22 Ω 33 Ω 51 Ω 100 Ω 150 Ω 220 Ω 330 Ω 510 Ω 680 Ω 820 Ω 1K Ω 1.1Μ Ω 10Μ Ω
Capacitors Qty. A small one costing $5-$7 is sufficient and available at Radio Shack. 25 V 100 µF Radial Electrolytic.5Κ Ω 2. 1 1 1.6V. 500 V 220 pF Ceramic Disc. Carbon Film. Yellow 9V Battery Clip
Note: A Standard pin-socket protoboard is required. 100 V (Digikey EF1106-ND) 47 µF Radial Electrolytic. 2 2 2 1 1 1 1 Value Description 22 pF Ceramic Disc. 25 V 220 µF Radial Electrolytic. Blue 22AWG Hook-up Wire. 3.3Κ Ω 5. 1 2 1 Description Burr-Brown INA118P Instrumentation Amplifier LM741N Operational Amplifier CD4007 CMOS Dual Complementary Pair/Inverter
Miscellaneous Qty.2Κ Ω 10Κ Ω 12Κ Ω 15Κ Ω 20Κ Ω 30Κ Ω 51Κ Ω 68Κ Ω 82Κ Ω 100Κ Ω 120Κ Ω 150Κ Ω 200Κ Ω 300Κ Ω 510Κ Ω 680Κ Ω 820Κ Ω 1.0Μ Ω 5. 2.
you will need this knowledge in order to efficiently plan your methods of investigation and finish the lab in the time allotted. c. All laboratory work will be done in student pairs or a group of three. you should have acquired knowledge of the fundamental principles of electronic circuits and gained considerable facility in making time and frequency domain measurements using modern electronic instrumentation. The laboratory instructions will specify the information required in the laboratory report. Describe your results and answer any specific questions asked in the handout in this section. you may insert them directly as figures in a Microsoft Word laboratory report document. Procedure Notes -. 2. 3. You don't need to repeat procedures described in the laboratory instructions. Use tables and graphs where appropriate. Each student will be required to submit an individual laboratory report.two paragraph overview. You may choose to include analytical work in an appendix to support your results. tables. At the end of the course. in your own words. In many cases. and 2) to introduce you to the simulation and physical circuit behavior of basic electronic devices and circuits. In cases where “pictures” of VI front panels have been taken to document results. State results CLEARLY. GENERAL LABORATORY POLICIES 1. You are strongly urged to read the reference material and perform any pre-lab work specified in the laboratory handout before you come to the lab. graphs. you are not restricted to providing only this information and the inclusion of comments about the validity of the data and an appendix of relevant analytical work is strongly encouraged.give a one . etc. b. which describes the topic covered in the laboratory. Introduction -. This should be complete and concise.CSUS College of Engineering and Computer Science Department of Electrical & Electronic Engineering EEE 102L Analog/Digital Electronics Laboratory OBJECTIVES AND GOALS OF THE LABORATORY The laboratory for this course has two major objectives: 1) To acquaint you with virtual instrument technology for electronic circuit design and testing.) should each have a complete figure "legend" which briefly describes the relevant information in the figure.include all data specified in the handout. Data and Results -. Figures (pictures. however.
. Laboratory Report Format a. which you feel may have had a significant bearing on the results.note any changes (voluntary or required by circumstance) from the procedure in the handout.
may be requested from the instructor (only during scheduled laboratory periods). Laboratory reports must be “hard copy” format and will be due one week following the end of the scheduled laboratory exercise (see the schedule of laboratories in the EEE 102L Course Outline). as part of your conclusions. You may share the cost of one kit with your lab partner(s). Open Laboratory Rules for RVR-5017 1. etc. You are also free to purchase what you need from suppliers such as Radio Shack. You will find that having your own protoboard will be helpful in many other laboratories in the CpE program.$7 at the electronics suppliers mentioned above). 6. Reports will have one point deducted for the first week that they are late. A selection of electronic parts that you will need is available as an EEE 102L Parts Kit. You and your lab partner(s) should also purchase a suitable (two strips of terminals are sufficient) protoboard if you don't already own one (estimated cost is $5 . Plagiarized reports will NOT be accepted. op-amps. or as determined by your instructor. Resistors. Conclusions -.include relevant analytical calculations and any miscellaneous additions. 4. Your open access to this laboratory is being granted under the assumption that you will conduct your activities there as a professional engineer and according to the following rules. and 9V battery clips are included. Almost all necessary equipment will be found at the computer workstations in the laboratory. if not provided already at the lab station. diodes. Reports more than one week late will NOT be accepted.d.). hook-up wire. Give your receipt to the lab instructor in exchange for a parts kit. They will be graded based upon completeness and the quality of both the analysis and documentation. Appendix -.
. you will be issued the undergraduate student lock code to RVR-5017. As a registered EEE 102L student. and may be obtained from your Laboratory Instructor. Any other equipment of a general nature that you may desire (DVMs. you will be required to have the Parts Kit for circuit construction. Capacitance Checkers. Starting in week 3.did your results agree with or differ from what you might have expected from lecture and/or your readings? Comment. and will be well worth the expense. You must pay for the parts kit and get a receipt at the Cashier’s Window in Lassen Hall. e. capacitors. 7. potentiometers. You have priority use of workstations in the VI Laboratory during the scheduled hours for the laboratory portion of the course. Transformers. or to use any applicable electronics parts that you may already own. transistors. Fry or Newark Electronics in town. and two 9V alkaline batteries to use as a power supply in the last lab exercise. ICs. Obtain a Parts Kit Purchase Form from the EEE 102L Web page. about the value of the laboratory exercise with respect to its improvement of your understanding of the subject material. the lab is not crowded and you should have good access to the equipment at other times. In general however. You have the responsibility to keep that code to yourself and to use the laboratory only for the purposes of the course. 5.
The Macintosh workstations are primarily for support of LabVIEW and PSpice programming/applications. Please act professionally and responsibly!
. No equipment. please leave the desktop of the workstation with all icons in the default condition when you are finished with your work. Please empty your trash! 5. Peripheral equipment (PARTICULARLY TEST CABLES AND CONNECTORS) associated with each workstation MUST remain with that station. manuals. etc. Instructor help will be available in the lab only during scheduled hours for the course. You should not admit anyone except yourself to the laboratory. may be removed from the laboratory without approval of the instructor. and other workstation needs should be met using your own personal computer or those in “open” laboratories on the campus. Computers are very sensitive to spills! 4. They also have Microsoft Office available for laboratory document preparation. To be courteous to other students who will follow you.2. Violation of the lab rules may result in our having to close the laboratory and restrict your use of it only to scheduled laboratory hours. 6. Surfing the Net. E-mail and Instant Messaging. Report any equipment malfunctions to your instructor as soon as it is practical to do so. It is for your use for the purposes of the course you are taking and for no other purpose. 3. No eating or drinking in RVR-5017. 7. Times for use of RVR-5017 are posted on the door of the laboratory. 8.
2003 as your guide. M. There is a shortcut icon on the desktop that will get you to the software very quickly. is required as a “report” for this first laboratory exercise. You will score 10 points for successful completion of the PSpice assignment. which accompanies the Herniter text. When you are finished.E. self-instructional introduction to PSpice programming during this laboratory. Follow the circuit schematic creation and dc nodal analysis instructions provided in chapters 1 and 3 (up to but not including Exercise 3-1). No plagiarized work will be accepted.) 3. save it (the entire project partition with all supporting files) as an appropriately named file on your personal USB Flash Drive (highly recommended). and section M on creating hierarchical designs in chapter 1. If the monitor is off. do not neglect to use the lab period to become familiar with the Macintosh workstations. since you will be using them in subsequent laboratory sessions. Files can be moved to different workstations in the laboratory by placing them in the Voyager Temporary server partition. Alternately.Laboratory 1 – Introductory PSpice Programming Assignment Your goal is to complete a brief. No work will be accepted which is more than 1 week late. Schematic Capture with Cadence PSpice. turn it on before you boot up the workstation. You may skip the section J on formatting the title block. as it stands at the end of the chapter 3 section of the Herniter text. on or before the due date for the first report (R) on the schedule. and to become familiar with the Macintosh workstations and the operation of the software under VirtualPC. When Virtual PC is fully loaded you will see a window on the Macintosh desktop that looks like a familiar Windows 2000 Professional desktop. One point will be deducted during the first week after the date due for late submissions. This will save the current state of the VirtualPC and allow it to be quickly started again. 2.. You may FTP your file to a secure personal account using the FETCH utility under the Apple menu or transfer it to the Voyager Temporary partition and access it from any networked workstation. on your home workstation and complete this introduction as described. When your project is complete. Prentice Hall. 2nd Edition. you will find the Cadence PSpice Software organized as described in Chapter 1 of the Herniter text. That partition is accessible from virtually any computer connected to the ECS network. Check to see that your workstation monitor is on standby (yellow light on). Under Start/Programs/. select Save All and Quit from the Macintosh File menu. Your file should be submitted to your instructor. (and highly preferred) you may install the Cadence Pspice. Only a hard copy picture of your final circuit schematic. 1. Please read this material carefully before the lab period so that you can minimize the time required to complete the work. Open Virtual PC by double clicking on its icon. Find Virtual PC under the Apple Menu (). However. 4. Cadence PSpice software is installed on the Virtual PC partition on the Macintosh workstations. Best of luck!
. You will use chapters 1 and 3 of Herniter. (See “Procedure for Taking Pictures of the Active Window on Macintosh Workstations in the appendix of this lab manual. Start up your Macintosh workstation by pressing the gray power button on the front of the chassis.
if you are not familiar with the Macintosh operating system.CSUS College of Engineering and Computer Science Department of Electrical & Electronic Engineering EEE 102L Analog/Digital Electronics Laboratory Laboratory 2 – Introduction to LabVIEW Pre-lab Work Your goal is to complete a brief. Notice that the keyboard has a convenient USB port in the top left corner. 2. On the Macintosh workstations. Consequently. the LabVIEW Student Edition is Version 7 and our LabVIEW Professional Edition on the Macintoshes is still Version 6. and Mac OS X compatible. at home to repeat lab work if necessary and to help solve some problems in the lecture portion of the course. Most of the exercises/problems in the Student Edition are designed to be completed without an I/O (analog-to-digital and digital-to-analog converter) board. You will probably need a USB Flash Drive to temporarily store your work and/or to keep safe copies of submitted work. 3. they will have to be done on the Macintosh workstations. Although the MAC OS 9. and select Shut Down from the Special menu when you are finished working with the
. Having the software will allow you to use the virtual instruments (VIs). the Voyager server Temporary partition on the ECS network can be accessed from the desktop icon on the lab workstations. EEE 102L laboratory exercises in the last 13 weeks of the course will use LabVIEW I/O. Notes on Workstation and File Operations 1. you may want to take some time to follow the Macintosh Tutorial that you can access from the Help menu in the top menu bar of the monitor screen. The Getting Started with LabVIEW PDF file on the EEE 102L Web site will be your reference for this lab. unless you choose to purchase a suitable I/O board or USB peripheral for your "home" computer (about $125 $650). The software is Windows 98 and higher. introduction to LabVIEW operations during this week of the course. The computers available to you in RVR-5017 are Power Macintosh G4s with the Macintosh version of the LabVIEW software loaded on the hard drive of each station. from the lab.2.2 is very similar to current versions of Windows OS. which do not require I/O. Also. however this is NOT required. you will need to become familiar with use of the Macintosh computers. Unfortunately. if desired. even if you choose to purchase the LabVIEW Student Edition software for your home computer. Double click on its icon to open it. files can be transferred between two computers via this partition. These workstations are also equipped with National Instruments 6024E data acquisition (I/O) boards for "real world" interfacing. You may choose to purchase the LabVIEW Student Edition software for use on your home computer. Thus. turn it on. Start up a Macintosh by pressing the gray button on the front of the chassis. If the workstation monitor is not on standby (yellow light on). VIs created under Version 6 can be read and saved by Version 7. LabVIEW will be found under the Apple menu. Please appropriately Quit all open programs from the File menu. but Version 6 cannot read Version 7 files. Therefore.
and save any changes to that device or account. Word files. If you return to a workstation to resume your work. Unless otherwise specified by your lab instructor. No work will be accepted which is more than 1 week late. One point will be deducted during the first week after the date due for late submissions. you should open your personal files from your storage device or account. Good luck!
. 7. which includes all graphics. A formal report from this Lab 2 should be submitted to your instructor on or before the due date (R). If you have multiple programs open you may find that command execution time is significantly prolonged. you should copy any LabVIEW files. Closing an application window in Mac OS does NOT automatically quit a program. This report should follow the report format described in the Lab Goals & Policies section of this manual.Macintoshes. You will score a maximum of 10 points for successful completion of Lab 2. Be aware that files stored on temporary partitions are NOT secure and should be transferred to a secure disk or account ASAP. Leave the monitor on standby. These are your personal files. (Alternately. 4. you may create a folder with your name on it on a "Temporary" partition (on Voyager or on the workstation) and store your files temporarily there. These workstations are normally kept off when not in use so Shut Down when you are finished working. it should be prepared in hard-copy form. or Picture files (see the appendix) that you create to one of your personal data storage devices or server accounts. At the end of a workstation session.) 5.
the A/DresCheck2.vi will allow you to measure the "rise time" and "slew rate" of simulated logic gate signals.vi will allow you to examine the effects of different digital sampling rates on the recorded analog signal. the WaveAnal3. EEE102L Lab_2 -. examine both its front panel and its wiring diagram. REFERENCES Jaeger. 5. 1. sections 1.2. to introduce some common time and frequency domain signal measurements. Ch.6 and 6. And finally.5. The GDAnal2.Introduction to LabVIEW VI Operations OBJECTIVES To become familiar with Virtual Instrument operation for the digital recording of analog signals and with the important phenomena of amplitude resolution and aliasing. [Path – hard drive/Applications(OS9)/LabVIEW 6/User/Virtual Instruments S06].3. Ask the instructor for help if you have any questions about the use of a VI. Before you use a VI. 4.DIGITAL RECORDING OF ANALOG SIGNALS AND MEASUREMENTS IN THE TIME AND FREQUENCY DOMAINS Laboratory 2 -. A printout of the front panel and descriptions of each VI that will be used in this course will be found in the appendix at the end of this lab manual.vi will allow you to observe the amplitude resolution characteristics of the 6024E A/D converter board in each workstation. 3. Within the Lab_2 folder. 1. Click on it and a window will open that will allow you to conveniently navigate to the desired folder of lab exercises. The LabVIEW startup screen will have an option to Open VI.LabVIEW Virtual Instruments HP Signal generator 1 µF Capacitor and 10 KΩ Resistor (RC circuit) from your Parts Kit Protoboard for circuit construction Miscellaneous patch cords and connectors
There are four Virtual Instruments (VIs) available for this lab exercise in a folder labeled EEE102L Lab_2 on the computer at your workstation. Look at the description of each VI contained under File/VI Propertie/Documentation (accessed from the LabVIEW menu bar). The Alias3. 2. and to examine the effect of lowpass filtering on that signal.
. 1. Double click your mouse on the LabVIEW icon under the Apple menu.vi will allow you to see the amplitude frequency spectrum (Fourier Series Analysis) of a signal. and the attached handout on Fourier Series Square Wave Analysis EQUIPMENT 1.
23 V. IS designed to accurately measure the generator output.A/D CONVERTER AMPLITUDE RESOLUTION Analog-to-Digital converters typically have an analog amplitude resolution of ±VFSV/2(n+1). The National Instruments 6024E A/D board in your workstation contains a 12-bit converter. will NOT be accurate at low output levels.ALIASING The phenomenon of aliasing occurs when you attempt to digitally sample a signal at a sampling rate that is too slow for "faithful reproduction" of its full frequency content. Before you begin.) Set the generator to deliver a 100 mV DC output signal.PART I -. A famous mathematical theorem. and that its actual waveform shape is distorted. Nyquist’s Sampling Theorem.vi PART II -. The result is a recorded signal that contains unexpected lower frequency Fourier series components. typically. Use an appropriate calculation to determine the expected Boolean conversion value of the 12-bit A/D converter. using the DC offset control to set DC amplitude. Set the HP signal generator to deliver a DC output voltage of 4. Connect the HP signal generator to the channel 0 input of the VI system. Make sure that the front panel controls on this VI are set to measure a DC signal. How does your value compare with the value predicted by the formula given at the beginning of PART I? 3. Press the RUN button in the menu bar of the VI to have it record the 4-Digit Voltmeter reading and the Boolean Conversion value of the A/D converter for each increment in generator voltage. Look at the Documentation (File/VI Properties/Documentation) under the LabVIEW menu bar to get a full description of this VI. 2. The figure below will serve as an example of aliasing for a signal containing a single sinusoidal frequency. 1. refer to the “Notes Concerning the Operation of the HP Signal Generators” attached at the end of this laboratory exercise. Record the 4-Digit Voltmeter reading and the Boolean conversion value of the A/D converter as measured on the VI front panel. You will explore the relationship between aliasing and digital sampling frequency using the following study protocol:
. which is set for an amplitude range of -10 V to +10 V. (Note that the offset setting on the HP generator numerical display. Close A/DResCheck2. Open the A/DResCheck2. Note how the apparent frequency of the “undersampled” signal is significantly lower than expected. (See the appendix for I/O connections. and therefore represents a distortion of that signal. 4. states that the sampling rate must be greater than two times the highest significant signal frequency in order to avoid aliasing.vi in the EEE102L Lab_2 folder. estimate the amplitude resolution of the A/D converter. however. The 4-Digit Voltmeter on the VI. and compare the expected and measured values.) From your measured data. You will start at 100 mV and increase the DC output of the HP signal generator in 1 mV increments until you reach 110 mV.
which is inside the EEE102L Lab_2 folder. Consider both the waveform shape and the apparent frequency. 200/s. Repeat the recording of the signals and.vi. Open the Alias3. What can you conclude from your data about the relationship between digital sampling rate and faithful reproduction of the signal frequency? 6. (See the appendix for information about taking "pictures" on the Macs. the instrument will record the generator signal as waveform 1 at a sampling rate of 1000 samples/second (Hz). It might help if you first calculate the expected alias frequency using the formula given in lecture. 3. If you click the RUN button on the Alias3.vi.vi front panel. Use the mouse and the VI “hand tool” to rotate the switch on the front panel of the VI so that waveform 2 is now recorded by sampling the generator signal at 150 samples/second.Time Domain
. Close Alias3. 225/s and 250/s 4. calculate the recorded (apparent) frequency of waveform 2 at each sampling rate. measure the waveform period and take a "picture" of the front panel to document your results. Connect the HP signal generator to the channel 0 input of the VI system and adjust its settings to produce a 100 Hz sine wave with 10 V p-p amplitude and zero DC offset. Describe the differences between the six recorded waveforms produced by the six different sampling rates. Which ones are aliased? 5.) 2. PART III – RISE TIME AND GATE DELAY TIME MEASUREMENTS -. again. Repeat 2 above for sampling rates of 175/s. Click on the red and blue chart measurement cursors and drag (manually adjust) them to measure the period of waveform 2.1. Using the waveform 2 period measurements. Take a "picture" of the front panel to document your results. Look at the Documentation (File/VI Properties/Documentation) under the menu bar to get a full description of this VI. Note that the waveform 2 sampling rate is set using the rotary switch on the front panel of the VI. and as waveform 2 at the sampling rate of 125/s.
since it contains some important information regarding signal recording.) Connect the output of the signal generator to channel 0 of the VI system and across the RC circuit. These are common measures of “gate dynamic response” in digital circuits. in this virtual instrument. 3. Then take a picture of the front panel of the instrument to document this result for your lab report.Since digital gates don’t respond instantaneously to changes in their input signals. Close GDAnal2. Note that.vi. it is often desirable to measure the “rise time” of an electronic gate. The slew rate is the voltage rise divided by the rise time. Open WavAnal3. The gate delay time is the time differential between the 50% amplitude points on the input and output waveforms. until you are satisfied with your measurement results. 100 Hz. Make sure to review the Documentation of this VI. "slew rate" and "delay time" of the simulated gate input signal. 2. Use a 1. if necessary.5 V DC offset. wiring diagram and documentation. Open GDAnal2. 1. the cursors are automatically placed at the appropriate points on the waveform in order to make the desired measurements – a great convenience. and compare those calculations with the three automatic measurements made by the VI in part 3 above. slew rate and delay time. Calculate the expected rise time. In this part of the laboratory you will be recording the response of an RC circuit (simulating a logic gate connection) to a square wave signal. Connect channel 1 of the VI system across the capacitor in the circuit. slew rate and delay time for the capacitor voltage in this RC circuit.0 µF capacitor and 10 ΚΩ resistor from your Parts Kit to construct a series RC circuit.vi to record a 2V p-p. This VI will automatically measure the "rise time". (See the circuit diagram below for reference. wouldn’t you agree? 4. Repeat the procedure.vi PART IV -.
R + V0 HP (channel 0) C + V1 (channel 1) -
2. Note that rise time of the signal is defined as the time it takes the signal to go from 10% to 90% of its peak-to-peak amplitude. Now click the RUN button on the VI to record the two signals.FOURIER SERIES AMPLITUDE SPECTRUM OF A SQUARE WAVE -Frequency Domain 1. Use the WavAnal3. Note that the upper waveform graph is the time domain signal with the time
. 5.vi and review its panel. and measuring its rise time. its “slew rate” and its "delay time". square wave with zero DC offset from the signal generator. Set the signal generator to produce a 5 Hz square wave with 5 V p-p amplitude and 2.
will allow you to record the input square wave signal after it is sharply low-pass filtered with adjustable cutoff frequencies from 0 . Manually adjust the position of the red chart cursor (click on and drag it using the mouse) to measure the peak height at each harmonic frequency in the amplitude spectrum display.00 and measures the other peak heights “relative” to that one. Record the values of peak height and frequency. The lower waveform graph is the frequency domain signal (Fourier Amplitude Spectrum) with the frequency axis displayed in Hertz. sets the height of the fundamental frequency peak at 1. Take a picture of your front panel results as documentation for your report. Describe the effects of the filtering in both the time and frequency domains. Take pictures of your front panel results as documentation for your report.axis displayed in seconds. as calculated in the handout. Notice the effects of filtering on the time domain waveform and the loss of particular harmonic components in the Amplitude Spectrum at each filter cutoff frequency setting. 4. and adjusting the slider switch on the VI front panel. Pressing the Lowpass Filter button. Fourier Series Representation for a Square Wave of Period T and Amplitude 1
.1000 Hz.) Justify your answer. Are the fundamental and harmonic frequencies of the square wave consistent with the values predicted from a Fourier series expansion (see attached handout) for the square wave? Are the measured peak heights of the fundamental frequency and the next four harmonics in the square wave consistent with the values predicted from the Fourier series expansion? (Note: relative peak height. 3.
2 + 1 = 0 0 T T 2
T T 2 T
an = 2 T
V(t)cos (nωοt)dt = 2 T
an = 2 T sin n2π t T n2π T
cos (n 2π t)dt .2 T sin n2π t T n2π T
(Remember that n is an integer and sin (n2π) = 0. If we define the fundamental radian frequency of the periodic function as: ωo = 2πfο.2 T T
T 2 0
sin (n 2π t)dt T
T T 2
bn = 2 T -cos n2π t T n2π T
+ 2 T cos n2π t T n2π T
bn = 1 -cos nπ + 1 + 1 cos n2π . any periodic function of time can be represented as an infinite series of sine and cosine terms that have arguments that are integral multiples of the "fundamental frequency" of the periodic function.)
bn = 2 T
V(t)sin (n ωοt)dt = 2 T
sin (n 2π t)dt . bn = 2 T
V(t)sin (n ωot)dt
We evaluate the above constants as follows:
ao = 2 T
V(t)dt = 2 T
1dt + 2 T
T ao = 2 [t]2 + 2 [-t]T = 1 . an = 2 T
V(t)cos (nωot)dt . the Fourier Series may be written as follows:
V(t) = ao + ∑ ancos nωot + ∑ bnsin nω ot 2 n=1 n=1
ao = 2 T
V(t)dt .According to the theory of Fourier Series.cos nπ nπ nπ
.2 T T
cos (n 2π t)dt T
T T 2
T 2 0
. The fundamental frequency (fo) is defined as: fo = 1/T where (T) is the period of the function.
. substituting these constants into the Fourier Series expression.. we have:
n = 1...
4 sin (2 πnfot) nπ
V(t) = 4 sin (2 πfot) + 1 sin (6 πfot) + 1 sin (10 πfot) + 1 sin (14 πfot) + 1 sin (18 πfot) + .. and bn = 4 for n = 1.14 0. 6.00 0.. . nπ
Therefore. 3.33 0..20 0. 5..bn = 0 for n = 2.. 5. 4. 3. . . π 3 5 7 9
The relative amplitudes of the harmonic (multiples of fo) frequency components [V(t)/(4/π)] are: Frequency fo 3fo 5fo 7fo 9fo Amplitude 1.
4. If you connect using a feedthru adapter. suppose you want to generate an 8 V p-p amplitude sine wave with a 5 V dc offset.
. they are kept locked up in RVR-5017A except during scheduled lab hours for the course. as is usually presented when they are attached directly to other pieces of HP instrumentation. If you use the signal generators during “open time” in the lab.Notes Concerning the Operation of the HP Signal Generators
1. For example. the generator display will read one half the actual voltage output of the generator. Always remember to press the green signal button in the lower right corner of the front panel of the generator so that its associated green LED is on. As another example. Therefore. you should use a 50 Ω ”feedthru” adapter to connect your test cable. Only then will the digital output voltage indicated on the generator’s display closely match the actual voltage output of the generator. You will need to set the generator controls to display a 2. Notice that you are asking for a maximum +13 volts from the generator at the positive peak of the sine wave. you won’t be able to generate anything greater than a 10 V p-p amplitude sine wave. These generators have a nominal 50 Ω output impedance over all frequencies of operation. Suppose you want to generate an 18 V p-p amplitude sine wave with 0 V dc offset. you must connect without the feedthu adapter and set the generator to display a 9 V p-p amplitude sine wave. This limitation needs to be considered when you are setting up the generator to deliver a specified output voltage. you will not get a signal output from the front panel cable connector! 2.5 volts p-p sine wave – one half of the actual (desired) generator output voltage under this condition. Think carefully about generator voltage set up and you’ll avoid significant frustration! If you are confused about how to produce a particular generator voltage. If you were using the feedthru adapter. ask your instructor for help. The controls on the HP signal generators in the laboratory are quite intuitive and should present only a minor challenge to you as you learn to operate them. When connected to a high impedance load without the adapter. Since these feedthru adapters are quite expensive and easily “disappear” from the lab. you would simply set the generator controls to display the desired 5 volts p-p sine wave. Since you will generally be using these generators with very high impedance loads during your laboratory exercise. 3. you will not have a feedthru adapter to use. The maximum output voltage of the generator cannot exceed a value of ± 5 V with a feedthru adapter (± 10 V without the adapter). They are designed to be used with a matched load of 50 Ω. and there is no way this generator can accomplish that! 5. Otherwise. let’s say you want to output a sine wave of 5 volts p-p (peak-to-peak) amplitude without using the feedthru adapter.
Laboratory 3 – Exploration of Diode Characteristics Objective: To explore the characteristics of signal and Zener diodes through the use of mathematical modeling. Isref is diode reverse saturation current at a specified temperature Tref.64V . Part I -.4V . wiring diagram.85V .0 except when we consider exceptionally high diode current conditions in this exercise.60V . diagram and documentation. n will be equal to 1.vi. Examine its front panel. From your graph. A set of default input parameters is present at startup.vi.3V . Notice that Isref is 1e-13 A for this diode at "room" temperature (290 °K).56V . 3.46V . Note that this diode equation model has been accurately corrected for changes in Is due to changes in temperature. RD is the effective DC diode resistance at the operating point.) Compare your value with the prediction of example 3. VD is the diode voltage.Mathematical Models of Forward and Reverse Bias Diodes 1.50V .vi.1V .75V . VT is the thermal voltage at temperature T.70V . Is is diode reverse saturation current at temperature T.80V . Open the Diode Current Analyzer. and Diode Junction Analyzer.2V . and n is the nonideality factor. use the chart measurement cursors to estimate the change in VD (ΔVD) per decade change (x10 change) in ID at VD = 0. (Hint: Use the “editing tool” [arrow] to change the low and high limits on your graph axes in order to magnify the measurement region of the graph for better measurement precision. Diode Graph.44V . and documentation.7 V. ID characteristic of your default diode on the semi-log graph of this VI.54V . Use the model to complete the following data table for this "default conditions" diode: VD ID VD ID .52V . Plot the data in part 3 above for the forward-bias VD vs.62V .4 in your EEE 102 class text. Inside you will find three VIs necessary for this part of the lab: Diode Current Analyzer. T is absolute temperature.vi.9V
4.48V . and examine its panel. 2.58V . you should have a good understanding of the electrical characteristics and the parameters affecting the design of semiconductor junction diodes.vi.
. Upon completion of this laboratory exercise. Open Diode Graph. and PSpice simulation. Note that the following symbols are used for the diode equation quantities: ID is the diode current. protoboard circuit testing. Open LabVIEW and navigate to open the EEE102L Lab_3 folder.
Emax is the maximum electric field intensity across the junction. Apply increasing amounts of reverse bias voltage (increase VR) until you just achieve dielectric (avalanche) “breakdown” in this diode.) What value of VR is barely sufficient to cause breakdown? What happens to the width of the depletion zone as reverse bias voltage is increased? What happens to the breakdown voltage if the temperature (T) is increased to 25 °C? 10. Do this by trial-and-error variation of the diode design parameters.vi and open the Diode Junction Analyzer. (Check the relevant equations in your text and in the VI's documentation!) Recall that Zener diodes are characterized by high doping levels. NA is electron acceptor concentration. What ID does the model predict? What does your text say about the value of n at high current? What can you conclude about the accuracy of the diode model predictions at high current if n is not precisely known? 7. however do not exceed a maximum doping level of 1E20/cm3. and Cj is the junction capacitance. (Hint: Use a “trial-and-error” method with the VI model here. Notice that diode current at VD = 0. NA. Now decrease the operating temperature by 25 °C from room temperature and again determine the VD required to produce this same diode current. At an operating temperature of 25 °C. (Hint: Remember that the electric field strength Emax at which silicon breaks down is 300.15 in your text.7 V at breakdown.vi. and ND. The default parameters represent the characteristics of a moderately “doped” signal diode under conditions of zero volts of reverse bias voltage (VR). φj is the junction barrier voltage. when operating at 30 °C. This means determining the reference specification of saturation current (Isref) for this diode design at room temperature (Tref).0 pF at this temperature and breakdown voltage.5. it should have a reverse bias voltage of 4. How do these two calculations compare? 6.) 8. VT is the thermal voltage at temperature T. Note the diode current at VD = 0. Examine its front panel. wiring diagram. wd is the width of the space charge or depletion zone. Now calculate dVD/dT for this diode at VD = 0. Note this value of VD. Use the model to design a Zener diode. Report your final design values for the three diode parameters. Close the Diode Current Analyzer. will have an ID = 15 mA at a VD = 0.000 V/cm. A.vi. Now use this VI model to "design" a diode which. VR is reverse bias voltage across the junction. T is absolute temperature.vi and return to Diode Current Analyzer. ND is electron donor concentration.1 under that condition. Note that the following symbols are used for the junction equation quantities: A is the crossectional area of the diode junction.6 V from equation 3. Calculate ΔVD/ΔT using the data from the two temperature extremes above.
.6 V.9V is quite high. In addition. Suppose the non-ideality factor n = 1. and documentation. Adjust the value of VD by trial-and-error until you achieve the same (to 3 significant figures) diode current. Close Diode Graph. “design” your diode to have a junction capacitance of 12.6 V and “room” temperature. 9. Increase the operating temperature (T) by 25 °C.
00 V DC. 3. Part III – Prototype Diode Circuit Construction and Testing 1. Explain the characteristics of the waveform you observe on the Voltage Stability/Waveform Monitor. Return the generator Offset voltage to 0 V and reverse the ± voltage polarity of the generator in your circuit. Again. Switch your VI to AC measurement (p-p) and measure the generator voltage (V1). Examine the front panel. Now set the generator voltage (V1) to 1. Replace
. Record the generator source voltage (V1) and then measure the diode voltage (Vd). (Remember that this is necessary to match the actual generator voltage output with its digital display. 206) of the Herniter text on your protoboard. Complete sections 3C (skip Exercise 3-5) and 4. wiring diagram.B (include Exercises 4. Use a 1N914 (or equivalent) signal diode from your parts kit. When you are satisfied with your measurement stability of Vd. Use a D1N914 diode (because there is one in your parts kit which you will be using in Part III) in place of the D1N5401 diode specified in the text for the 4B circuit. Now set the HP generator Offset voltage so that the voltage you measure across the resistor is 1.vi.2 and 4. Take “pictures” of the schematics and probe graph windows to document your results here. Now measure Vd.) Begin with a setting of 0 V DC Offset. current characteristic of the diode. 5. Use the HP signal generator for the DC voltage source. 2. Construct the circuit shown in Exercise 4-3 (p. Set the DC/AC switch on the VI front panel to DC and RUN the VI. measure Vd and then the voltage across the resistor. Now set the HP generator to deliver a sine wave of 10 Hz frequency and 2 V p-p amplitude. Use sections 3C and 4.00 V. On your protoboard.C of the Herniter text. Use the 1N4734A Zener diode from your parts kit in this circuit. Can you explain any differences between measurement and PSpice prediction? 4. in terms of the voltage vs. press the stop button on the VI front panel and take a "picture" of the panel window to document your result.B of the Herniter text as a guide to examine the characteristics of both signal and Zener diodes using PSpice simulation.3). Select a 1 kΩ resistor from your parts kit and measure its actual resistance to 3 significant digits using a bench ohmmeter. Using the Fluke RTD Thermometer in the Lab. construct the circuit shown in the section 3. and documentation to become familiar with this VI. How do the diode voltage and current measured under each of the two conditions in part 2 above compare with what you would predict from your PSpice simulation in Part II. Open LabVIEW and navigate once again to the folder EEE102L Lab_ 3. Connect the channel 0 (+ and -) input leads of your VI workstation to measure voltage across the resistor in your circuit. This time open the Filtered DC/AC Voltmeter. Make sure you attach a 50 Ω feed-through connector to the output of the generator.Part II – PSpice Analysis of Simple Diode Circuits 1. measure the room temperature in °C.
the DC voltage source shown in that circuit with your HP generator. press the stop button on the VI front panel and take a picture of the panel window to document your result. the actual output voltage of the HP generator is twice the value of its digital readout. Explain the characteristics of the waveform you observe on the Voltage Stability/Waveform Monitor in terms of the voltage vs.) When you are satisfied with your measurement stability of Vz. (Note: To achieve 18 V p-p output. Note that you have two weeks to do this laboratory exercise and prepare the formal report. Adjust generator voltage (V1) to 18 V p-p at 10 Hz and then use the VI to measure Vz.
. current characteristic of the Zener diode. With no feed thru adapter connected. Check the (R) date on your course outline. you must remove the feed thru adapter from the output of the generator and adjust Amplitude to 9 V p-p on the digital display.
Laboratory 4 – Diode Circuits Objectives: 1) To compare the characteristics of a half-wave and a full-wave rectified power supply.vi. Zener diode-regulated power supply. Notice that the operating frequency is defaulted to 60 Hz for obvious reasons. dT is the diode conduction time. Upon completion of this laboratory exercise. Open LabVIEW and navigate to open the EEE102L Lab_4 folder. T is the period of the source voltage.3%. 2) to construct and test a full-wave. 3) to examine the characteristics of a diode wave shaping circuit. (Appendix A in your text may be helpful for identifying resistor color band codes. From your EEE 102L Lab Kit.
. PRV is the percent ripple voltage. Determine (if you can) PIV. and 4) to simulate the piecewise linear VTC of a diode circuit using PSpice. wiring diagram. Compare the components required in this design with those required for a full-wave rectified power supply design with the same constraints. and Testing of a Half-wave Rectified Power Supply 1. and PD is the nominal power dissipation of the diode. w is the radian frequency of the source. R is the load resistance. Vr is the ripple voltage. you should have a good understanding of the design and function of these basic diode circuits. C is the capacitance. Open Rectifier Supply. and documentation. bridge-rectified. Ip is the peak diode current. 3. Part I – Design.67 of your text. select components to implement the full-wave rectifier design shown in Figure 3.8 V(rms) source voltage. Explain (using appropriate equations from circuit theory) the reason for the differences. A set of “zero” default input parameters is present at startup. Use this design VI to determine the necessary components for a half-wave rectified power supply. Use a W005G bridge rectifier chip.vi. Vdc is the nominal dc output voltage of the power supply. 4. CVD is the constant voltage drop across a diode. operating with a 17. 2. required to produce a dc output current of 10 mA with a percent output voltage ripple of 4. Inside you will find the VIs necessary for this part of the lab: Rectifier Supply. PIV is the diode peak inverse voltage. and Filtered DC/AC Voltmeter. Construction. Does it have an adequate power rating for use in this application? Justify your answer. Ip and Isc specifications for the W005G rectifier diode from its data sheet. Vp is the peak amplitude of the source voltage.) Is this chip adequate for this application? Justify your answer.vi. Idc is the nominal dc output current of the power supply. (See the Data Sheets folder in the Documents folder under your hard drive icon.) Your resistor will be a 1/4 W carbon film type. Examine its front panel. Note that the following symbols are used for the rectifier design equation quantities: Vrms is the RMS voltage of the sinusoidal source. Take a picture of the front panel of your VI to document your results.
vi if necessary. Plugged into our power lines in the lab. See below:
Vp . Now switch your VI to AC (p-p) and measure the output voltage waveform. press the Stop button on the VI front panel to freeze your measurement. If it isn’t the value indicated for default in the design VI. Vr.vi and proceed to make the following measurements. Using Figure 3.8 V(rms). so you have no earth ground reference in this circuit unless you connect the white wire.5 kΩ. Use the VI’s chart cursors to measure Vdc.5. Connect the channel 0 input lead wires of your VI to measure the output voltage (Vo) across the RL resistor in your circuit.2V on C
Let Rs be 1. You can’t measure this with our VI systems because the voltage amplitude is larger than the full-scale range of our A/D converter boards (± 10 V).67 in your text as a guide. Use the ac measurement setting for rms voltage readings. wire your circuit on your protoboard using the step-down transformer provided. the output voltage is around 17. open Filtered DC/AC Voltmeter. and dT on the Voltage
. after your circuit is constructed and working. Also. When you are satisfied with your wiring job. In order to keep your measurements inside the VI full-scale range. Go back and change this value in your Rectifier Supply. The transformer that your lab instructor will provide you with for this laboratory exercise has a nominal secondary output voltage Vs = 16 V (rms). the transformer secondary is entirely isolated from ground. which will be available in the lab. When you are satisfied with your signal. 8. make a voltage divider out of your calculated load resistor. Note: You must connect the white ground wire from the green connector block to an appropriate location on your circuit to provide a reference ground for your measurements. Check and confirm the output voltage (rms) of your transformer using the hand-held or bench-top voltmeters. Unlike the HP signal generator. 7. it will be a good idea to use your VI voltmeter to measure the Von of one of the diodes in your bridge rectifier chip. Calculate the required RL so that the sum of the two resistors is equal to the value specified in your design VI. consider that fact in your theoretical calculation of what you should expect for output voltage here 6.
Now measure Vo across the diode.
. Part III – PSpice Simulation of the Piecewise Linear Voltage Transfer Characteristic of a Diode Circuit. Part II – DC Restoring Circuit Evaluation 1. Again. Save a Probe window “picture” file to include in your report.vi (AC p-p setting) and take a picture of the Voltage Stability/Waveform Monitor to document your results. Calculate Idc and PRV for your circuit and compare these. Select a 1 µF metalized polymer film capacitor and a 1N914 switching diode from your parts kit. (May be done in the lab or at home on your own workstation.79b in your text. use the HP signal generator for the voltage source in the diagram. Note that a formal laboratory report on this lab should be included with the report of Lab 3. Both reports are due on the lab day specified in the course outline.78b in your Jaeger class text. Take a picture of your front panel for documentation of your results. When you are satisfied with the signal. Record the generator output voltage using Filtered DC/AC Voltmeter. push the Stop button on the VI and use cursors to measure the maximum and minimum peak voltages. Use a 1N914 signal diode from your parts kit for each of the three identical diodes in this circuit.) 1. Push the Stop button on the VI and take a picture of the front panel to document this input signal. Open PSpice Capture and construct the circuit shown in Figure 3.Stability/Waveform Monitor. construct the positive dc restoring circuit diagramed in figure 3. Can you explain any differences between your measurements and the predictions of that figure? Take a picture of the VI front panel to document your results. When you are satisfied with your wiring job. 2. with their predicted values from part 3 above. and the three measured values from 8 above. Can you offer explanations for any differences between these measured/calculated values and the design values? 10.vi. Run the simulation and display a plot of Vo versus Vs in the Probe window.140. 9.119 on page 174 in your Jaeger text. Compare your measurements to the predictions of Figure 3. Measure the key break points and slopes in the PSpice-simulated VTC for this circuit and compare them with the corresponding “ideal” diode model predictions illustrated in problem 3. On your protoboard. Measure Vdc again using the Filtered DC/AC Voltmeter. Now find the 1N4734A Zener diode in your parts kit and figure out how to add it to your circuit to clamp the voltage across the load resistor to 5. Setup a Simulation to run a DC Sweep on Vs between –15 and +15 volts.6 V and to significantly reduce the ripple. 2. set the generator to deliver a 100 Hz triangle wave of 8 V p-p output and zero V dc offset. which was done as an example in class. Identify and explain the differences.
Laboratory 5 – MOSFET Transistor Characteristics Objectives: 1) To examine the characteristics of a MOSFET transistor by means of a mathematical VI model. λ is the channel length modulation parameter. Examine its front panel. NMOSFET_LL2. NMOSFETAnalMeas4. VGS is the gate-source voltage. start with the default parameter set (Use the Reinitialize All to Default command under the Operate menu) and change only the parameter indicated by the protocol. 2) to design a single-supply dc biasing circuit for operation of an NMOS device in the saturation region. A set of default input parameters is present at startup. This parameter set is constructed based upon data used for NMOS device problems in Chapter 4 of your Jaeger class text. 2. and/or saturation region of the characteristic. Open LabVIEW and navigate to open the EEE102_Lab 5 folder. Describe any significant changes to the cutoff. γ is the body effect parameter. W/L is the channel aspect ratio. Note that the following symbols are used for the NMOS transistor model parameters: Kn’ is the transconductance parameter.Refer to the data sheet for the Motorola MC14007UB IC.vi. In each case. wiring diagram. Upon completion of this laboratory exercise. Your description of the changes you observe will be sufficient for your report. Pre-lab Work -. Clicking on File/Open should take you to the Data
.vi and Filtered DC/AC Voltmeter. VSB is the sourcebody voltage. VDS is the drain-source voltage. (Use Adobe Acrobat Reader under the Apple menu. 3. and IDS is the drain-source current. Explore how these parameters affect the IDS vs. 3 4 5 6 7 8 9 10 Increase Kn’ by a factor of 10 Increase W/L by a factor of 10 Increase λ by a factor of 10 Increase VT0 to 4 volts Decrease VT0 to –2 volts Increase VGS to 6 volts Decrease VGS to 0. and documentation. pinchoff point. you should have a good understanding of MOSFET transistor characteristics and the dc biasing of such devices.vi. The “pinchoff point” is defined as the Q point drainsource voltage where VDS = (VGS-VTN). Inside you will find the VIs necessary for this part of the lab: NMOSFET.vi. VT0 is the “standard” threshold voltage with a grounded body. 2φf is the surface potential parameter. NMOSFETBias3. Open NMOSFET. It is not necessary to take pictures of the front panel results for each case.5 volts Increase VSB to 5 volts
4.vi.vi. VDS characteristic of the NMOS transistor using the following protocol. linear or triode region. Part I – Examining the Electrical Characteristics of MOSFET Transistors 1. and 3) to simulate a CMOS inverter circuit using PSpice.
Notice that these characteristics vary with temperature over the rated operating range of the chip.5 V. This VI uses the example 4-R bias circuit design done in class as a guide. It also uses a white wire to identify “system ground” for the differential voltage measurements. Pick one of the NMOS devices on the IC and use the diagram on the lower portion of the front panel of the VI to design a test circuit (as shown on the VI front panel) for that chosen device on your protoboard. Kn and λ from Part I above. Estimate the values of Kn = Kn’(W/L) and VT0 = VTN for VSB = 0.B.Sheets folder on your workstation. Now open NMOSFET_LL2. Notice that this VI will plot the characteristic of your device as well as the load line equation for your biasing circuit. Follow the documentation for this VI. Use 12 V as your VDD supply voltage.) Figure 3 (attached at the end of this lab for easy reference) in the data sheet for the MC14007UB gives “typical” IDS vs. Design for a Q point (VDS.) Make sure (if necessary for your transistor choice) to wire a "jumper" between the Base and the Source of the transistor to set VSB = 0 V. wiring diagram and documentation. (N. and λ parameters of your chosen transistor. Assume W/L=10 for your transistor and your best estimates for VT0. VT0 and λ for your transistor. examine its front panel. to measure Kn. Such a connection is NOT appropriate for single transistor operation here. wiring diagram and documentation. Notice that λ is very small for these devices and may be approximated as λ = 0 for our estimation purposes. Leave all gate pins on the unused devices of the IC in an open circuit condition. Consider using the pinchoff point where VDS = (VGS-VTN) and the saturation region where IDS = (Kn/2)(VGS-VTN)2 to calculate the two parameter values.vi. Notice that this VI allows you to use a test circuit to directly measure the Kn. that Kn' is entered in A/V2 in this VI. It will also determine the Q point (Q-VDS. IDS) of (3. Determine values of R1. and RS for a four-resistor biasing network for the selected NMOS device on your MC14007UB IC.) Note that you will have to choose available 5% 28
.vi and examine its front panel. Take a picture of your front panel as documentation for your report once you are satisfied with your measurements. R2. which is conveniently listed with the front panel figure in the appendix of this lab manual. 5. Note that this VI uses three simultaneous input channels to obtain necessary circuit voltages. (Adjust the "Gate Margin" parameter to give you 5% resistor values close to those available in your parts kit. How do your measured values for Kn.) Make sure your Q point will be in the saturation region of the device [VDS > (VGS-VTN) > 0]. VDS characteristics for the transistors on the chip. as indicated in the Schematic Figure.vi. examine its front panel. VT0. 2. Enter YOUR device and circuit design data (not the default values). Open NMOSFETAnalMeas4. Use the characteristic for VGS = 5 V and TA = 25 °C. VT0 and λ compare with the ones calculated in part 4 above? Which set of values will you choose to rely upon for Part II? Why? Part II – Single Supply DC Biasing Circuit Design and Prototype Construction 1. and will adversely affect your circuit operation. QIDS) for your device. RD. 5 mA) in the saturation region of the device. (Do NOT connect pin 14 to your VDD source or pin 7 to your VSS source. for the NMOS devices on the chip. You will use the bench power supplies and the HP generator for the necessary voltage sources. wiring diagram and documentation. Open NMOSFETBias3.
Follow the directions for section 4. Take a picture of the probe window results as documentation for your report. On your protoboard. Use the later to calculate IDS. you may choose to make modest "trial-and-error" adjustments to your resistor choices in order to achieve a better match to your design Q point.D. can you offer an explanation as to why? Part III – PSpice CMOS Inverter Circuit Simulation. 1. 3. When you are satisfied with your circuit wiring. open Filtered DC/AC Voltmeter.tolerance resistor values for your simulation here. Use “generic” NMOS/PMOS enhancement mode transistors in your Parts list. however. and measure the voltage across RS. take a picture of the front panel of this VI for documentation. Use a 12V power supply for VDD and selected resistors from your parts kit. The CMOS transistors on the MC14007UB are typically used to construct digital inverter circuits. measure the voltage across drain and source (VDS). mount the MC14007UB IC and wire the selected NMOS transistor according to your dc biasing circuit design.3 in the Herniter text and perform Exercise 4-7 to create the voltage transfer characteristic (VTC) for a CMOS inverter. When you are satisfied with your result. Using DC measurement mode. Simulate the circuit and display the voltage transfer characteristic (VTC) in the Probe window. How does your measured Q point compare with your design target? If it isn't close.
Inside you will find the VIs necessary for this part of the lab: NPNBE. Explore how these parameters affect the IB vs.1 V Increase T by 30 °C Decrease T by 30 °C 5. IS is saturation current.1 Increase VCE to 10 V Decrease VCE to 0. VBE characteristic of the NPN transistor using the following protocol.vi. Upon completion of this laboratory exercise. (Use the Reinitialize All to Default command under the Operate menu.vi. NPNBE_LL. start with the default parameter set and change only the parameter indicated by the protocol. In each case.vi.vi. VCE is collector-emitter voltage.Laboratory 6 – BJT Transistor Characteristics Objectives: 1) To examine the characteristics of a BJT transistor by means of a mathematical VI model.vi. wiring diagram and documentation. Open LabVIEW and navigate to open the EEE102L Lab_6 folder.) Describe any significant changes to the characteristic. BF is forward (ce) current gain. you should have a good understanding of BJT transistor characteristics and the dc biasing of such devices.vi. BR is reverse (ce) current gain. Increase IS by a factor of 10 Decrease IS by a factor of 10 Increase BF to 200 Decrease BF to 20 Increase BR to 5 Decrease BR to 0. Examine its front panel. NPNCE. and 3) to simulate this circuit using PSpice. 2) to design a single-supply dc biasing circuit for operation of an NPN BJT device in the forward active region. Open NPNBE.vi. Note that the following symbols are used for the NPN BJT transistor model parameters: 3. Your description of the changes you observe will be sufficient for your report. It is not necessary to take pictures of the front panel results for each case.vi. This parameter set is constructed based upon data used for NPN BJT device problems in Chapter 4 of your text. Examine its front panel. 4. and Filtered DC/AC Voltmeter. IB is base current and VBE is base-emitter voltage. 2. wiring diagram and documentation. NPNBFISAnalMeas.
.vi. A set of default input parameters is present at startup. Open NPNCE. Note that the same symbols are used for the NPN BJT transistor model parameters as were used in NPNBE. Part I – Examining the Electrical Characteristics of BJT Transistors 1. T is absolute temperature. NPNCE_LL.
What value would you estimate to be appropriate to use for VBE in your bias circuit design? Part II – Single Supply DC Biasing Circuit Design and Prototype Construction 1. some different notation is used in the data sheet for the transistor parameters. 5 mA). and RE for a fourresistor biasing network for the 2N2222A. Your description of the changes you observe will be sufficient for your report. VCE characteristic of the NPN transistor using the following protocol.) Open NPNBias. Notice that these characteristics vary with temperature over the rated range of the collector current. (Be sure to read the Documentation window before you begin. Use the characteristic for T = 25 °C in your design work. 5 mA) in the forward active region of the device.5V.39 in your Jaeger text as a design guide. VBE and IC vs.87 was done as an example for you in class. IC) = (3. you may find βF to be as low as 50% of the nominal value found in figure 3. iC characteristics for the transistor. you may assume βR = 1. but adjust the Base Margin to yield acceptable resistor values. with these measured BF and IS values. Increase IS by a factor of 10 Decrease IS by a factor of 10 Increase BF to 200 Decrease BF to 20 Increase BR to 5 Decrease BR to 0. Figure 3 (attached at the end of this lab for easy reference) in the data sheet gives “typical” hFE vs.vi and read its documentation window. R2.87 and Figure 5. You will have to choose the nearest 5% resistor values in your parts kit for your actual circuit design. 32
. Leave C-E Vdrops = 2. to plot the expected IB vs. As usual. Use 12 V for VCC. Here hFE = β F in our textbook notation. Because we usually buy cheap grades of these transistors for the parts kits. Estimate the value of βF for this transistor for a bias operating Q-point (VCE. start with the default parameter set and change only the parameter indicated by the protocol. Since it is not very significant in forward active region operation of the transistor. VCE characteristics for this transistor. and use their values in the following circuit verification VIs. In each case.) Use the previous two VIs.1 Increase IB by a factor of 10 Decrease IB by a factor of 10 Increase T by 30 °C Decrease T by 30 °C 7. This parameter set is constructed based upon data used for NPN BJT device problems in Chapter 4 of your text. Explore how these parameters affect the IC vs. Describe any significant changes to the characteristic. Use it to determine values of R1. IC) of (3.6. Use NPNBFISAnalMeas. Refer to your data sheet on the Motorola 2N2222A NPN BJT transistor. (Note that problem 5. Use problem 5. Choose these now. It is not necessary to take pictures of the front panel results for each case. A set of default input parameters is present at startup.vi to measure the βF and IS values for your transistor under the specified bias conditions. Design for a Q point (VCE.5 V. RC.
and documentation. 1. open Filtered DC/AC Voltmeter. wiring diagram and Documentation. Take a picture of the schematic with the I and V data displayed as documentation of your results.vi. Notice that this VI will plot the IB vs. wiring diagram. Simulate the circuit and display VBE. Close NPNBE_LL. Use a 12 V power supply as your protoboard VCC supply voltage. Is it what you expected for your design? Part III – PSpice Single Supply DC Biasing Circuit Simulation. they determine the Q point (Q-VCE. VCE. Again. Using DC measurement mode. mount the 2N2222A transistor from your parts kit and wire it according to your dc biasing circuit design. Enter your device and circuit design parameters and RUN the VI to verify your Q point design. Together.
. This VI will plot the IC vs. Note that a formal laboratory report on this lab should be included with the one for Lab 5. and IC to confirm the Q point. When you are satisfied with your circuit wiring. Use the later to calculate IC. Q-IB) for your device. measure the voltage across collector and emitter (VCE). It will also determine the Q point (Q-VBE. QIC) for your device. measure VBE. as well as the collector-emitter sub-circuit load line equation for your biasing circuit.vi and open NPNCE_LL. VCE characteristic of your device. You may choose to make slight adjustments to your resistor values (5% values) to achieve a better match to your design Q point. Take pictures of the front panels of these two design verification VIs to document your final result. How does your measured Q point compare with your design target? If it’s not too close. examine front panel.vi. Open NPNBE_LL.2.vi and examine its front panel. and measure the voltage across RC. Enter your device and circuit design parameters and RUN the VI to examine your Q point. On your protoboard. 4. 3. Open PSpice Capture and construct the schematic of your 2N2222A transistor biasing circuit. Is it what you expected for FAR operation of the transistor? Note the Q point value of IB because you will need it for input in the next design verification VI. VBE characteristic of your device as well as the base-emitter sub-circuit load line equation for your biasing circuit.
2N2222A NPN Bipolar Junction Transistor – Forward (ce) Current Gain as a function of Collector Current
and C3 are the ac coupling and by-pass capacitors Frequency is the frequency of the input signal in Hz R1. and C3) and appropriate dc biasing resistors (R1. common-emitter amplifier using an NPN BJT transistor and a single-supply dc biasing circuit. Your circuit design should use appropriate available coupling capacitors (C1. you should have a good understanding of common-emitter amplifier design and requirements for the dc biasing of such circuits. Note that the ac model parameters for the transistor are added as a calculation to this bias circuit designer. What factors must you consider in determining them? 2. RUN the VI to calculate your dc bias circuit design values. if necessary.vi and NPNCE_LL. wiring diagram. and Rc are the relevant bias circuit and ac load resistances
.Laboratory 7 – Common-Emitter Amplifier Design Objectives: 1) To design a high voltage gain. and documentation window to learn about its functions and operation. 4. Examine its front panel. This one you have not seen before. Note that you will have to determine appropriate dc bias values of VCE and IC for your amplifier. Upon completion of this laboratory exercise. open LabVIEW and navigate to the EEE102L Lab_7 folder. Open NPNCEBias. R2.vi. R3. R2.vi. Use these VIs to enter the 5% resistor design values for your dc biasing circuit. Take pictures of the front panels of these VIs to document your results. C2. β and IS should be set to simulate what you have measured in Lab 6 for your 2N2222A transistor. Examine the documentation window again. Close NPNCEBias. C2. On your VI workstation. 3. You have also seen these VIs before in Lab 6. 2) to construct a prototype of the design and test it for ac voltage gain. Design a common-emitter amplifier that will employ a 2N2222A NPN BJT as the active device.vi and open both NPNBE_LL. and 3) to simulate this circuit using PSpice. and RUN the VIs to verify the dc Q points of your design. Enter the absolute temperature (T) of the room (check the Fluke RTD by the door to RVR-5017A). examine its front panel. and RC. if necessary. You may adjust C-E Vdrops and Base Margin to yield reasonable 5% resistor values. Part I – Circuit Design and Verification Using LabVIEW 1.vi. Inside are all the VIs you will need for this laboratory. Your amplifier should have an ac voltage gain (|AV| ≥ 100) at a frequency (f = 100 Hz) with load resistance R3 = 100 KΩ. RE) from your parts kit. Close these two VIs and open CEAmpAnal. Use a 12V power supply as your VCC supply voltage. Although you have seen this VI before in Lab 6. power supply voltage (VCC) and your desired dc bias values for VCE and IC. The following circuit design parameters are required as inputs for this VI: Rs is the equivalent voltage source resistance Vsp is the peak input source voltage C1. and documentation once again. Your design will employ an ac voltage source (vs) with RS = 15 Ω. wiring diagram.
rπ . Using a signal generator set to deliver a 20 V p-p sinusoidal output signal at a frequency of 100 Hz. Part III – PSpice Common-Emitter Amplifier Simulation. construct the resistive voltage divider circuit shown in Figure 1. 1. Note that peak input signal amplitude (Vsp) will be 5 mV. How do these two compare with your design values? Take a picture of the front panel of this VI to document your results.005sin(2πft) V -
Figure 1. Introduction to Probe. Transistor Bias Point Detail.
+ vss =10sin(2πft) V -
R=30 KΩ R=15 Ω
+ vs =0. If your gain is not sufficient. mount the 2N2222A transistor and wire the transistor and appropriate passive components according to your common-emitter amplifier circuit design. and calculate the ac voltage gain (AV). Prepare pictures of your Schematic and Probe results to include in your lab report as documentation of your simulation. and ro are the respective small-signal ac input resistance. When you are satisfied with your design and its verification by the LabVIEW VIs. and review Ch 2. It will deliver a Thevenin equivalent sinusoidal voltage (vs) of approximately 5 mV peak amplitude to C1 through an equivalent source resistance (RS) of 15 Ω. open Filtered DC/AC Voltmeter. Refer to sections 3. RUN the VI to calculate the expected peak ac output voltage (Vop) and ac voltage gain (Av). When you are satisfied with your circuit wiring. transconductance. construct the circuit on your protoboard. gm. Part II – Common-Emitter Amplifier Prototype Construction and Testing 1. Using AC measurement mode. 2. consider redesigning the circuit with a different value of IC. Open PSpice Capture and construct your 2N2222 transistor common-emitter amplifier circuit and voltage divider source.vi.E. 5. and output resistance of the transistor at the design Q-point. On your protoboard. Simulate the amplifier circuit and use Probe to display vo(t). measure the voltage (vo(t)) across load resistor R3. Notice that a representation of the expected ac output voltage is displayed on the VI waveform graph. Enter the appropriate input parameters for your common-emitter amplifier circuit design. Signal Generator Voltage Divider Circuit
. Consider the size of the coupling and bypass capacitors that you will need.. RUN the VI.
2) to construct a prototype of the design and test it for overall ac voltage gain and CMRR. 3. Pre-laboratory preparation: Inspect the data sheet for the Burr Brown INA118 in the EEE 102L Data Sheets folder on your workstation.3.Laboratory 8 – OP Amp Instrumentation Amplifiers and First Order Filters Objectives: 1) To design a high voltage gain instrumentation amplifier using the Burr Brown INA118 IC and to design a cascaded first order bandpass filter using two LM741 operational amplifiers. along with design information presented in class. Determine appropriate external components for use with the INA118 to achieve an instrumentation amplifier with differential voltage gain of 1000 at a frequency of 100 Hz. Part I – Circuit Design and Verification Using LabVIEW 1. and examine its I/O impedance. Similarly. and 3) to simulate this circuit using PSpice.vi in the EEE102L Lab_8 folder. Note particularly the circuit design of the IC and how its differential gain is determined by selection of a single external circuit component. determine appropriate external components for use with a second LM741 op amp to construct a low-pass first order filter with a -3dB cutoff frequency of 1000 Hz and a voltage gain of 1 in the 'low-pass" frequency region. and enter the data required for this
. so choose available R and C values for your designs that will achieve the desired specifications. Upon completion of this laboratory exercise.12 in your text.
Amplifier/Bandpass Filter Block Diagram INA 118
2. review the data sheet for the LM741 Op Amp in the Data Sheets folder on the workstation. Compare its circuit with the example in figure 11. Note that you will need two 9 V alkaline batteries with battery clips to construct ± 9 V power supplies to power your circuits in this laboratory. Similarly. Open this VI. Open LabVIEW on your workstation and navigate to Amp/Filter.7 in the Jaeger text. read its documentation. you should have a good understanding of instrumentation amplifier/filter design and the electrical characteristics of such circuits. This pdf file may be copied to a storage device and printed outside of the lab if you desire. Consider the Low-Pass Filter description in section 11. and determine appropriate external components for use with a LM741 op amp to construct a high-pass first order filter with a -3db cutoff frequency of 10 Hz and a voltage gain of 1 in the "high-pass" frequency region. Remember that these circuits will be using components from your parts kit. 4.
it is almost impossible to measure it using general-purpose test instruments such as we have in the laboratory. connect the instrumentation amplifier inputs across the 15 Ω resistor of the voltage divider. 4. RUN the VI and measure the voltage at the output pin of the IC. Set the 38
. Now place a 2. 2. Measure the voltage across the resistor and compare it to the "open circuit" output voltage. Note that this circuit is slightly different from the one used in the previous laboratory in that the voltage (vs) is not referenced directly to "ground". The ground side of the HP generator. If it doesn't check out.inputs of the instrumentation amplifier directly to the + output terminal of the signal generator to produce a “common mode” input signal.vi. construct the resistive voltage divider circuit shown in Figure 1 below. It should deliver a Thevenin equivalent sinusoidal voltage (vs) of approximately 5 mV peak amplitude through an equivalent source resistance (RS) of 15 Ω to the differential input pins of the INA118. Using AC measurement mode. Using a signal generator set to deliver a 20 V p-p sinusoidal output signal at a frequency of 100 Hz. Again. Does the 51 KΩ resistor make any difference? Consider the high input impedance of the INA118 circuit design and explain why. Is there a difference? Try this again with a 1 KΩ resistor. How does it compare with your design value? Take a picture of the front panel of this VI to document your results. If there is still no difference. must all be connected together (common ground). Calculate the ac voltage gain (AV). pin 5 (ref) of the INA118. go back and re-analyze your design. Because this instrumentation amplifier has such a high differential input impedance. 3. insert a 51 KΩ resistor from your parts kit in series with the + input of the instrumentation amplifier. When you are satisfied with your wiring. Repeat this for frequencies of 10 Hz and 1000 Hz. RUN the VI and compare both peak output voltage and gain to your predicted design values. If your design checks out ok. mount the INA118 and wire it according to your design. measure the voltage at the output pin of the IC. In order to get an impression for how large this input impedance really is. take pictures of the front panel for each of the 3 frequencies as documentation for your report and proceed to Part II below. and the ground terminal of your battery supplies. Open Filtered DC/AC Voltmeter. Part II – Instrumentation Amplifier/Bandpass Filter Prototype Construction and Testing 1. Make sure both battery power supplies are connected as required. Remove the load resistor. Make sure you have a common reference ground in your circuit. Disconnect the signal generator from the voltage divider and connect BOTH the + and . Remove the 51 kΩ resistor and reconnect the + input of the instrumentation amplifier directly to the voltage divider. At one end of your protoboard.2 KΩ resistor between the output pin of the IC and ground (output load resistor). try a 510 Ω resistor.VI to verify your design values at a frequency of 100 Hz. What do these measurements indicate about the output current limit for your IC? What is the minimum load impedance you should design for if you expect to achieve the desired 10 V peak-topeak output voltage swing? 5.
. 7. Part III – PSpice Filter Simulation 1. Nominally.vi to measure the filter output voltage. Calculate the common mode rejection ratio in decibels (CMRR in dB). Prepare pictures of your Schematic and Probe windows to include in your lab report as documentation of your results. Use Probe to display the final output voltage vo amplitude as a function of frequency for the frequency sweep from 5Hz to 5 kHz. Connect the filter input to the instrumentation amplifier output. measure the voltage at the output pin of the IC. Right next to the high-pass filter mount another LM741 op amp and wire it according to your low-pass filter design. return your input connections to the voltage divider as before. it should be 5 V peak. 100 Hz. Measure the output voltage of the low-pass filter at 100 Hz. Is the amplitude of the output voltage reduced by -3dB (a factor of . Use a VSIN sine wave voltage source (at 100 Hz and 5 mV peak amplitude) from the Parts library as input to your filter. Again. Next to the INA118 on your protoboard. How does it compare to the instrumentation amplifier output voltage measured in part 2 above? Now change the signal generator frequency to 10 Hz and measure the filter output voltage again. (Note you may have to edit the voltage scale after recording in order to magnify the signal and measure the small common mode output voltage. Measure the output voltage of your low-pass filter at 100 Hz. and reset your signal generator amplitude to 20 V p-p. Set up a simulation to examine the circuit using an AC frequency sweep from 5 Hz to 5 kHz.generator to produce a 5 V p-p sine wave. Open PSpice Capture and construct the bandpass filter section (only) of your circuit using LM741 op-amps from the parts library. and use the Filtered DC/AC Voltmeter. take pictures of the front panel of your VI that show your completed circuit output at frequencies of 10 Hz. and 1000 Hz.707) at this frequency as predicted by your design? Explain. 6.) Determine the common mode gain for your amplifier. Ignore any "spike" noise that may be present and measure (estimate) the p-p amplitude of the 100 Hz sinusoidal signal. Is it greater or less than you expected? What instrumentation amplifier and/or filter circuit modifications could you make to achieve an output voltage closer to this design expectation? For report documentation. Is it what you expected? Change the signal generator to a frequency of 1000 Hz and measure the low-pass filter output voltage. mount one LM741 op amp and wire it according to your high-pass filter design. When you are finished. Is the amplitude reduced by -3dB at this frequency as predicted by your design? Explain.
+ vss =10sin(2πft) V -
R=15 KΩ R=15 Ω
+ vs =0.005sin(2πft) V -
Figure 1. Signal Generator Voltage Divider Circuit Note that a formal laboratory report on this lab. is due on your lab day in the 16th week (finals week) of the semester. along with the one for Lab 7.
TAKING PICTURES OF THE ACTIVE WINDOW ON MACINTOSH WORKSTATIONS 2. NATIONAL INSTRUMENTS 6024E DAQ BOARD I/O PIN CONNECTIONS
1. EEE 102 L VIRTUAL INSTRUMENT DOCUMENTATION 3.
7. This format is easily handled by word processors. and selecting Finder. Click the STOP button again (white) to reset the VI for the next continuous RUN. Specifically. You'll find the Picture # document in the window that opens. Then double-click on the hard drive icon that should now be visible just below the menu bar on the right side of the desktop.Procedure for taking a "Picture" of the active window on Macintosh workstations
1. 6. That document will be located inside the hard drive partition (icon) on the desktop. 4. Set the caps lock key and press Shift 4 (three keys) simultaneously. Save your desired Word (preferred) or picture files to your personal storage device or account. 2.
Please remember to drag all picture files into the trash and Empty the trash (find the Empty Trash command under the Special menu) before you finish your session on the workstation.vi
This is a high precision DC/AC voltmeter that incorporates a forth-order Butterworth antialiasing filter to provide high noise immunity and high measurement precision in DC mode. Click the RUN (arrow) button to start measuring continuously.pict format. Monitor voltage stability using the monitor graph. (Note: You may take single voltage samples (one sampling
. These documents are saved on the Macintosh in a . Microsoft Word can insert these files directly into a document file using the Insert/Picture/From File command. 5.
EEE 102L Virtual Instrument Documentation
A/DResCheck2. Click the mouse in the active window. or simply by dragging the picture document into the open word document page. Repeat this mouse click and select Hide Others from the sub-menu. 3. Make sure the window is active by executing a single mouse click somewhere inside the window. and you can usually insert these pictures directly into a word processing document. The mouse pointer will change to a camera shutter. where # is the number of the picture taken. you can get to the hard drive partition most easily by executing a mouse click on the program icon in the upper right-hand corner of the Macintosh menu bar. If the hard drive icon is obscured on your desktop. The "picture" of the window will be found as a document labeled Picture #. You will hear the sound of a camera shutter from your workstation. Click the STOP button on the VI front panel to stop (red) and hold the data on the graph for the current sampling period.
Click on the RUN button in the menu bar to start the VI.vi
This VI allows you to record both time and frequency (amplitude spectrum) domain signals using channel 0. The VI retrieves the data that matches the trigger condition.period) by clicking RUN with the STOP button depressed (red). LOOK AT BOTH THE SHAPE AND THE APPARENT FREQUENCY OF THE WAVEFORM 2 SINE WAVES AS COMPARED TO WAVEFORM 1. This VI is configured for measuring National Instruments 6024E board A/D converter amplitude resolution using a variety of measurement protocols. and to use a Property Node to automatically position the waveform graph cursors. The VI has been configured to measure Rise Time. and Delay Time for acquired logic gate waveforms on two channels. Click this button to RESET the VI before you RUN it again.
Alias3. displays it and stops the acquisition.vi
This Conditional Trigger Data Acquisition VI acquires specified data from one or more analog input channels. There are two AC modes of recording: RMS reading and Peak-to-Peak reading that are set by the AC Mode switch when the AC/DC slide switch is in the AC position. Slew Rate. The 10% and 90% points on the output waveform. Waveform 1 is sampled at a fixed rate of fs = 1000 samples/s. Clicking the red STOP button on the front panel (NOT the menu bar) will hold the data from the next sampling period. and the 50% points (TI and TO) on both waveforms are displayed for reference. A hardware clock is used to control the acquisition rate for fast and accurate timing. X is time in seconds and Y is amplitude in volts. (0 and 1).
WavAnal3. Frequency = 1/period. Pushing the Filter button will cause the signal to be sharply lowpass filtered with a
. The Boolean Conversion display records the binary output (12-bit) of the converter for the measured analog voltage.
GDAnal2. Clicking RUN in RESET mode will allow you to record single records. Click RESET then RUN (arrow) to resume continuous recording. You can measure waveform periods using the cursors.) Click and drag the red and blue cursors on the waveform graph to measure time (X) in seconds and amplitude (Y) in volts. Click and drag the center of a cursor with the mouse to position it on the waveform graph.vi
This VI is designed to illustrate the phenomenon of aliasing using a 100 Hz sine wave signal as input to channel 0. You can move the cursors by clicking and dragging with the mouse in order to make detailed measurements of amplitude (Y) in volts in either the time or frequency domain (X). The digital sampling rate is designed to accommodate a signal with a fundamental frequency on the order of 100 Hz. Click on the STOP button on the front panel (NOT the menu bar) to hold the next record. The data is stored in an intermediate memory buffer after it is acquired from the analog input channels. You may switch Waveform 2 in five steps between sampling frequencies of 125 samples/s and 250 samples/s using the Sampling Frequency switch.
The effects of temperature (T). Edit the input data as required and click on the RUN (arrow) button to operate the VI.vi
This VI allows you to create a convenient graph of the forward ID vs.vi
This VI allows you to simply solve the "diode equation" under a variety of input conditions. to make desired measurements of this characteristic. Notice that saturation current (Is) has been corrected for temperature variation to make the calculation of diode current even more realistic.vi
This is a high precision DC/AC voltmeter that incorporates a forth-order Butterworth antialiasing filter to provide high noise immunity and high measurement precision in DC mode. (Note: You may take single 1 second voltage samples by clicking RUN with the STOP button depressed (red). Click the STOP button on the VI front panel to stop (red).. non-ideality factor (n) and diode voltage (VD) on diode current (ID) can be observed. You can easily explore the effect of your input choices on the diode current. Click the RUN button to start measuring continuously. Click the STOP button again (white) to reset the VI for the next continuous RUN. is set using the slide switch in increments of 200 Hz from 0 to 1000 Hz. and junction capacitance.vi. Cursors can be dragged to make differential measurements on the monitor graph.
Diode Junction Analyzer. Be sure to look at the Wiring Diagram to appreciate the critical formulas that govern these phenomena. fc.
Diode Graph.fc Hz. along with appropriate expansions of the axis scales. Have fun!
Filtered DC/AC Voltmeter.passband from 0 .vi
This VI is designed to allow you to explore the diode junction conditions that will produce "breakdown" under reverse voltage bias. Use the text tool to enter the corresponding ID array values obtained from the Diode Current Analyzer. VD characteristic of a diode.
Diode Current Analyzer. You can use measurement cursors. You can "zoom" in on a data point on the graph by simply editing the axis limit values with the text tool. The set of diode voltages (VD) specified for the diode problem in lab 3 have been entered as default values in the graph array. RMS reading and Peak-to-Peak reading that are set by the AC Mode switch when the AC/DC switch is in the AC position. where the cutoff frequency. You can change the properties of the diode as input variables and explore the consequences of those changes on the breakdown voltage. depletion zone width.) There are two AC modes. Use of this VI simply requires a known saturation current (Isref) at a known reference temperature (Tref) for the diode to be modeled . Then RUN the VI to see your graph. Monitor voltage stability using the monitor graph.
. Be sure to check out the wiring Diagram to see how this VI is implemented. You can perform measurements using the red and green cursors.
The user must then determine the "pinchoff point" (VDS. It then uses a formula node to calculate the required component parameters for the design after the RUN button is pressed. Default parameters are from the instructor’s personal NMOSFET circuit. VDS characteristic of an enhancement mode (VT0 > O) or depletion mode (VT0 < 0) NMOS field effect transistor.
NMOSFETBias3. It then uses a formula node to calculate the required component parameters for the design of the biasing circuit.
NMOSFETAnalMeas4.VRD (voltage across resistor RD). Note that the VTO.VDS. The modeling includes both channel length modulation effects and body voltage effects.1V is a good estimate for operation at a peak current on the order of 100 mA. you will have to refrain from using the 50-ohm feedthrough connector and set the generator to 2. a CVD = 1. Required Resistances: R1 = 100 K ohms R2 = 200 K ohms.5 V DC offset. Note that Gate Margin is the selected source-to-ground voltage (difference between gate-to-ground and gate-to-source
. without the 50-ohm feedthrough connector. and to calculate the threshold voltage (VT0). RD = 1 K ohms. It requires two RUN cycles to calculate these parameters. in order to produce VDD with the HP Signal Generator.VGS.
NMOSFET. For the W005G Bridge Rectifier used in the lab. Required Voltage Sources: VSS -. Channel 2 -. after the RUN button is pressed. Channel 1 -. In the first RUN cycle.vi
This NMOS FET analyzer VI is designed to simulate the IDS vs. and input them under "Graph Measurement" on the panel.5 + 5 sin 2(pi)t V (5 V peak amplitude sine wave with 5 V DC offset and frequency of 1 Hz). Remember. Enter the appropriate input parameters for the device and press the RUN button. the VDS vs. Note that the Constant Voltage Drop (CVD) for the diode(s) used must be estimated. Required Input Voltages: Channel 0 -. and 5 V PP amplitude sine wave at a frequency of 1 Hz.vi
This VI is designed to allow the user to input three channels of specified voltage measurements from the NMOS transistor test circuit shown in the diagram below the front panel. IDS at pinchoff) from the graph (drag the cursor). all offset and peak-to-peak amplitude readings are effectively doubled at the output. VDD -. It also calculates the VDS at "pinchoff".12 V DC. IDS characteristic at measured VGS will be graphed.vi
This VI is designed to allow the user to input specified parameters for design of a four-resistor dc biasing circuit for an NMOS FET. Special note: Because of maximum voltage output limitations. Kn and lambda output parameters will not necessarily be accurate at this point. Clicking on the RUN arrow a second time will calculate accurate VTO and Kn values for the device. transconductance (Kn) and channel width modulation (lambda) of the transistor.Rectifier Supply.vi
This VI is designed to allow the user to input specified parameters for a simple half wave or full wave rectified power supply.
This NPN BJT analyzer VI is designed to simulate the IB vs. C-E V Drops is a parameter that sets the distribution of voltage drop between RC and RE. The circuit load line is calculated for verification of the Q point.
NMOSFET_LL2. VCE is collector-emitter voltage. Default parameters are from the instructors personal 2N2222A BJT. Q point calculation is precisely valid only for zero channel length modulation.voltages). VBE (first quadrant) characteristic of an NPN transistor. T is absolute temperature. but does not include the Early effect. DC biasing using a four-resistor. BR is the reverse (ce) current gain. a 46
. Other parameters are those commonly associated with NMOS devices and the biasing circuit. BF is the forward (ce) current gain.vi
This NPN BJT analyzer VI is designed to simulate the IC vs VCE characteristic in the first quadrant of an NPN transistor. A factor of 2 divides the drop evenly. IS is saturation current.
NPNBE. The modeling is based upon the Gummel-Poon description of the transistor. The modeling is based upon a modified Gummel-Poon description of the transistor. IC is collector current. VCE is the collector-emitter voltage.vi
This VI is designed to allow the user to input specified parameters for design of a four-resistor dc bias circuit using an NPN BJT.vi
This NMOS FET analyzer VI is designed to simulate the IDS vs. Note also that there is NO correction of IS in this model for changes in temperature. T is absolute temperature. Input the appropriate parameters and press the RUN button. The modeling includes both channel length modulation effects and body voltage effects.vi
This VI is designed to allow the user to input specified and measured parameters from the NPN BJT transistor circuit shown. Parameters follow standard definitions for the NPN BJT. Note that IS is NOT corrected for changes in temperature T. BF is forward (ce) current gain. IB is base current. single supply circuit sets the Q point for the device in the saturation region. and calculate the BF and IS of the transistor. IB is base current. Assumptions are that the biasing setup operates the transistor in the forward active region and that VA (Early Voltage) is very large.
NPNBias. however small values of lambda may be accommodated with good result. Channel 0 is designed to measure VBE in the circuit. IS is the saturation current at temperature T. and VBE is the base-emitter voltage.
NPNBFISAnalMeas. It uses a formula node to calculate the required parameters after the RUN button is pressed. BR is reverse (ce) current gain. It then uses a formula node to calculate the required component parameters for the design after the RUN button is pressed. Gate Fraction is the ratio of gate-to-ground voltage/VDD. VDS characteristic of an enhancement mode (VT0 > O) or depletion mode (VT0 < 0) NMOS field effect transistor. The "Betometer" provides a graphic display of forward current gain. and channel 1 is designed to measure VCE. so corrections to BF can be neglected.
R1.87 in your text. R3. BR is the reverse (ce) current gain (default 1. gm. transconductance. BF is the forward (ce) current gain of the transistor. Other parameters follow standard definitions for the NPN BJT and biasing circuit. The default parameters correspond to the solution to problem 5. etc. reducing the Base Margin will help. single voltage supply dc biasing circuit. Note also that there is NO correction of IS in this model for changes in temperature. T is absolute temperature. frequency is the frequency of the input signal in Hz.vi
This VI is designed to allow the user to input specified parameters for small-signal ac analysis of a CE BJT amplifier circuit. RC. It uses a formula node to calculate the peak output voltage and ac voltage gain parameters for the design when the RUN button is pressed. and R2 are the relevant biasing circuit resistances. and Q-VCE and Q-IC are the calculated VCE and IC Q point solution set. VCC is the supply voltage. If it isn't. and output resistance of the transistor at the design Q-point. Input parameters: Rs is the equivalent voltage source resistance. VCC is the supply voltage. and ro are the respective small-signal ac input resistance.
NPNBE_LL. IS is the saturation current.87 in the text. The default parameters correspond to the solution to problem 5. T is absolute temperature. single voltage supply dc biasing circuit.vi
This Q-point analyzer VI is designed to simulate the IB vs VBE characteristic of an NPN transistor. R2. Larger Base Margin values give more power-efficient circuit performance. C2 is the emitter bypass capacitor and C3 is the output coupling capacitor.
NPNCE_LL.factor of 3 divides the drop 1/3 to RC and 2/3 to RE. and ICEQ is the Q-point collector current. f is the base voltage divider fraction. A default value of 5 is used to be consistent with the text.)
. VCEQ is collector-emitter Q-point voltage.vi
This Q-point analyzer VI is designed to simulate the IC vs. R1. VCE is collector-emitter voltage. and RE are the biasing circuit resistances. (See Circuit Diagram below the front panel. RE and RC are the relevant bias circuit and ac load resistances.
CEAmpAnal. Default parameters are those from problem 5. R1. RE. Q-IC) for forward active region operation in a four-resistor. rp. Q-IB) for forward active region operation in a four-resistor. The VI calculates the BE circuit load line equation and plots it to help you graphically visualize the Q point solution.0). and calculate the Q point (Q-VBE. BR is the reverse (ce) current gain. BF is the forward (ce) current gain of the transistor. The VI calculates the CE circuit load line equation and plots it to help you graphically visualize the Q point solution. and calculates the Q point (Q-VCE. C1 is the input ac coupling capacitance.87 in your text. It also displays a representation of the sinusoidal output voltage as a function of time. Vsp is the peak input source voltage. IS is the saturation current at temperature T. IC is collector current. VCE characteristic of an NPN transistor. Base Margin sets the ratio of Collector to Base bias supply current. r is the (BF+1)RE/REQ ratio and should be >> 1. R2.
and CH2 are the relevant circuit components for the first-order high-pass filter. A default value of 5 is used to be consistent with the text.NPNCEBias. It uses a formula node to calculate the peak output voltage (Vop) and ac voltage gain (Av) for the design when the RUN button is pressed. RG is the gain control resistor for the Burr Brown INA 118 instrumentation amplifier. RH1. Base Margin sets the ratio of Collector to Base bias supply current. RL1.vi
This VI is designed to allow the user to input specified parameters for design of an instrumentation amplifier and first-order bandpass filter. and CL1 are the relevant circuit components for the first-order low-pass filter. RL2. If it isn't. It then uses a formula node to calculate the required component parameters for the design after the RUN button is pressed. It also displays a representation of the sinusoidal output voltage as a function of time.
Green Connector Block Analog Channel Input Connections
Amp/Filter. A factor of 2 divides the drop evenly. etc. Other parameters follow standard definitions for the NPN BJT. Larger Base Margin values give more power-efficient circuit performance. f is the base voltage divider fraction. r is the (BF+1)RE/REQ ratio and should be >> 1. Input parameters: Vsp is the peak input source voltage. frequency is the frequency of the input signal in Hz. RH2. C-E V Drops is a parameter that sets the distribution of voltage drop between RC and RE. biasing circuit and small-signal transistor model. reducing the Base Margin will help. a factor of 3 divides the drop 1/3 to RC and 2/3 to RE.vi
This VI is designed to allow the user to input specified parameters for design of a four-resistor dc bias circuit using an NPN BJT in a Common Emitter amplifier design. Default parameters are from the instructor’s personal BJT and design choices.