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Basic SRAM Cell and Operation Type of SRAM Cells Scaling in SRAM Technology Advanced SRAM Technology Race between 4T and 6T
Read-Write Memories (RAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
A SRAM is a matrix of static, volatile memory cells and address decoding functions to allow access to each cell for read and write operations Use positive feedback in form of cross-coupled inverters to store logic data in “one” or ‘zero” state. The active elements in a memory cell require a constant power source to remain latched in the desired state. The basic SRAM Cell made up of cross-coupled inverter has several variations with tradeoffs between cell size, noise immunity and standby power.
6-transistor CMOS SRAM Cell WL V DD M2 M5 Q M1 BL M4 Q M6 M3 BL Semiconductor Memories 5 2007/4/29 .
CMOS SRAM Analysis (Read) WL V DD BL Q= 0 M5 V DD Cbit M4 Q= 1 V DD M6 V DD Cbit BL M1 Semiconductor Memories 6 2007/4/29 .
8 0.5 1 1.6 0.2 0 0 0.5 3 Semiconductor Memories .5 2 Cell Ratio (CR) 7 2007/4/29 2.CMOS SRAM Analysis (Read) 1.2 1 Voltage Rise (V) 0.4 V o l t a g e r i s e [ V ] 0.2 1.
CMOS SRAM Analysis (Write) WL V DD M4 M5 Q= 0 Q= 1 M1 BL = 1 V DD BL = 0 M6 Semiconductor Memories 8 2007/4/29 .
CMOS SRAM Analysis (Write) Semiconductor Memories 9 2007/4/29 .
6T-SRAM — Layout VDD M2 M4 Q M1 M3 Q GND M5 M6 WL BL Semiconductor Memories 10 BL 2007/4/29 .
Resistance-load SRAM Cell WL V DD RL M3 BL Q RL Q M4 BL M1 M2 Static power dissipation -.Want R L large Bit lines precharged to V DD to address t p problem Semiconductor Memories 11 2007/4/29 .
SRAM Characteristics Semiconductor Memories 12 2007/4/29 .
General SRAM Schematic The load devices can be depletion mode transistors or PMOS transistor or resistors. Write Sequence Semiconductor Memories 13 2007/4/29 .
C6 is at Vss Logic “0” when T3 is off and T4 is on. C5 is at Vss . T5 and T6 is on and the level stored in C5 and C6 are passed to the bitlines Semiconductor Memories 14 2007/4/29 . C5 is at Vdd.Data Storage in SRAM Storage Basic six-transistor SRAM cell and its layout Logic “1” when T1 is off and T2 is on.C6 is at Vdd When the wordline is selected.
Write Operation: Data are place in B and B-bar lines When the wordline is raised. T5 and T6 is on. B-bar is then lower then B. T1 is off and T2 is on When wordline is selected.6-T SRAM Operation Scheme Read operation: B and B-bar are set to high At state “1. the differential signal between the two bitlines is detected by the sense amplifier. causing the cell to flip into the desired state Semiconductor Memories 15 2007/4/29 . C2 is then pull down by discharging through T6 and T2.
CMOS SRAM Cell CMOS 6-T Cell Larger cell size Lower standby leakage current ~ nA Better Static Noise Margin Semiconductor Memories 16 2007/4/29 .
no n-well needed Higher standby leakage current ~ µA Depletion-mode NMOS Semiconductor Memories 17 2007/4/29 .N-SRAM with Depletion-Load Smaller cell size.
p+ diffusion Issues High resistance needed for low static current Typical RL=1GΩ Write Sequence Current in 1MB SRAM @ 3V I=1M*3V/1GΩ=3mA Cell high node time constant T=RL*C=1G*10fF=10µsec Semiconductor Memories 18 2007/4/29 .Resistor-Load SRAM Cell Smaller Cell area Cell Schematics No n-well and pMOSFET Poly resistors lay on top of other transistors No contact to join n+.
Poly PMOS Load Cell Features Standby leakage < pA R~80MΩ Cell high node time constant ~0.8µsec p+ poly / n+ poly diode Semiconductor Memories 19 2007/4/29 .
.Comparison of Various Cells In CMOS SRAM cell. R-load NMOS SRAM cell combined with CMOS peripheral circuits allowed the benefit of lower standby power consumption while retaining a smaller chip area of NMOS SRAMs. there is essentially no current flow through the cell except during switching The depletion load and resistive load have a nonzero static current. hence the standby power dissipation is always higher than that of a CMOS cell Semiconductor Memories 20 2007/4/29 R-load cell with poly-silicon resistors allows up at a 30% reduction in cell size in double poly-silicon technology using buried contacts.
Memory Scaling Trend Density increase as a result of line width reduction. novel cell size. enhance process technology and circuit innovations Semiconductor Memories 21 2007/4/29 .
SRAM Technology Evolution Semiconductor Memories 22 2007/4/29 .
1Mb SRAM Technology Semiconductor Memories 23 2007/4/29 .1st Gen.
Scaling Parameters in SRAM Semiconductor Memories 24 2007/4/29 .
CS ↓. QS ↓. VDD ↓. more vulnerable to soft error induced by alpha particles Increased CS can be improve SER Semiconductor Memories 25 2007/4/29 .Cell Design Considerations Cell ratio = driver transistor current/ access transistor current Cell ratio↑⇒ Static Noise Margin↓ Access transistor current↓ ⇒ Static Noise Margin↑ ⇒ read time↓ At same cell ratio Access transistor current ↑ ⇒ read speed ↑ ⇒ driver transistor size ↑ ⇒ cell size ↑ Storage node capacitance design As technology scales.
Scaling of R-load SRAM Polysilicon load resistors are commonly used in < 1Mb SRAM designs R-load cell are hard to design to achieve both high density and low power Small cell size limit the sized of the polyresistors The standby power on the other hand set a minimum value of the load resistor Density↑⇒ Cell size ↓ ⇒ Resistor size ↓ ⇒ Standby leakage ↑ Semiconductor Memories 26 2007/4/29 .
Noise Margins for Full CMOS and R-load Cells Bitline Voltage (V) Semiconductor Memories 27 Supply Voltage (V) 2007/4/29 .
gates Poly2: R-load and Vdd M1: bitlines M2: wordlines Semiconductor Memories 28 2007/4/29 .1MB Poly-load SRAM Cell Layout Features 2P2M Process Cell size 6x11µm2 Poly1: Vss.
load current is set at about 30pA R ↑ ⇒ Standby Power ↓ ⇒ SER ↑ Memory size 256k 1M 4M 16M Feature size (µm) 1.2 3/0.25 R (GΩ/ ) 47 26 24 12 Tpoly (nm) 70 50 30 30 Silicon Processing For The VLSI ERA – Vol II Semiconductor Memories 29 2007/4/29 .2 0.5 Load current (pA) 30 30 30 30 Standby current (µA) 8 33 130 520 RL (GΩ) 164 97 97 48 L/W of RL 4/1.5 1/0.High-Valued Poly-Si Load Resistor To minimize power consumption and maintain an optimum soft-rate.8 0.8 2/0.25 VDD (V) 5 3 3 1.5 0.
The resistor are normally formed by poly2 layer. Semiconductor Memories 30 2007/4/29 .Poly-Resistor Engineering To maintain small cell size. high sheet resistance polyfilm must be used. The remainder of the layer ( not for high resistive poly ) is implanted with a much higher dose so form ohmic contact or served as interconnect path.
Poly-Resistor Engineering Undoped polysilicon film with implant doses from 1x1013 to 1x1015/cm2 can from 104Ω/ to 1012Ω/ Adjacent higher-doped regions can significantly alter the resistance value if lateral diffusion take place over a large enough fraction of the resistor Oxygen implant to reduce lateral diffusion Tpoly ↓ & Implant dose↓⇒ R ↑ Semiconductor Memories 31 2007/4/29 .
Cell Layout Comparison Depletion-Mode Load Single Poly Memory Double Poly Memory Semiconductor Memories 32 2007/4/29 .
Layout of Full CMOS Cells Single Aluminum Interconnect Semiconductor Memories Double Aluminum Interconnect 33 2007/4/29 .
Buried Contact Schemes Layout Rules Cross-sectional View : Connection of Diffusion and Poly-layer Semiconductor Memories 34 2007/4/29 .
Butting Contact metal Semiconductor Memories 35 2007/4/29 .
Shared Contact Using Poly2 Allows Further Reduction of SRAM Cell Size Semiconductor Memories 36 2007/4/29 .
Area Reduction by Local TiN Interconnect TiN Conventional Cell Size : 160F2 Semiconductor Memories 37 TiN Interconnect Cell Size : 120F2 2007/4/29 .
TiN Local Interconnect in SRAM Semiconductor Memories 38 2007/4/29 .
Titanium Silicide Process Titanium Deposition Ti/Si Reaction & Nitridation of Ti Interconnect Patterning Etch TiN TiN/TiSi2 Annealing Advantage: Better compatibility with CMOS process Problem: TiN has lower conductivity Semiconductor Memories 39 2007/4/29 .
Cell size 5x12µm2 Semiconductor Memories 40 2007/4/29 .Advanced CMOS Cell Layout Reduce Contact Number by location interconnects Silicide straps to connect poly-line and diffused region 1P2M Process.
local interconnect 41 Semiconductor Memories Ref: IEDM 1996 – p.The Race Between 4T and 6T Major tradeoffs in SRAM design: size & process complexity 4T cells dominates the stand-alone SRAM market due to its small size 6T cells are typically used in on-chip storage is MPUs 4T cells Smaller Complex process Poor stability at low VDD Simple 6T: basic logic process Advanced 6T: self-aligned contact.271 2007/4/29 .
Estimated Processing Cost Comparison A more complex process can still produce a cheaper product when the increase number of die can compensate for the increase wafer cost The reason why all manufacturers are pushing for smaller cell size Semiconductor Memories 42 2007/4/29 .
SRAM Cell Comparison SAC : self-aligned contact are used in both 4T and 6T cells to reduce cell size Semiconductor Memories 43 2007/4/29 .
allows for smaller size Semiconductor Memories 44 2007/4/29 .SNM Comparison 6T cells have much better stability. especially at low supply voltage Better SNM in 6T allows for low cell ratio. β.
Enhanced 4T Designs Resistor using LDD region increase SNR without increase cell ratio Boosted WL improves read current and and SNM TFT load improve cell stability and reduce SER Diode inherited in the cell need to be optimized to improved on current Supply voltage > 1.8 can still provide reasonable SNM Semiconductor Memories 45 2007/4/29 .
Summary 4T SRAM enjoys smaller size but the supply voltage cannot be scaled too low 6T SRAM allows for low supply voltage and provide better SNR Further enhancement in process and device structure can further scaled the SRAM cell for high density memories Semiconductor Memories 46 2007/4/29 .