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Telephone : PABX : 9661920-73/4980

**dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
**

XvKv-1000, evsjv‡`k

**DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
**

DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

September 28, 2010 Dated, the………………………….

BCD Adder: A BCD adder is used to perform addition of BCD numbers. A BCD adder circuit must be able to do the following – 1) Add two four-bit BCD code groups, using straight binary addition. 2) Determine if the sum of this addition is greater than 10012=910. If it is, add 0110 (decimal 6) to this sum and generate a carry to the next decimal position. If the two BCD code groups represented by A3A2A1A0 and B3B2B1B0 are applied to a four-bit parallel adder, the adder will perform the following operation – A3A2A1A0 BCD code group + B3B2B1B0 BCD code group S4S3S2S1S0 straight binary sum S4 is actually C4, the carry out of the MSB. The sum outputs S4S3S2S1S0 can range anywhere from 00000 to 10010. These cases where the sum is greater than 01001 are listed below. S4 S3 S2 S1 S0 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 (10) (11) (12) (13) (14) (15) (16) (17) (18)

Let’s define X as a logic output that will go HIGH only when the sum is greater than 01001. Therefore, X will be HIGH for either of the following conditions – (I) whenever S4=1, sums greater than 15. (II) whenever S3=1 and either S2 or S1 or both are 1, sums are between 10 to 15. This can be expressed as – X=S4+S3(S2+S1) Whenever X=1, it is necessary to add the correction 0110 to the sum bits and to generate a carry. Figure below shows the complete circuitry for a BCD adder including the logic circuit implementation for X. The circuit consists of three basic parts – (I) The two code groups A3A2A1A0 and B3B2B1B0 are added together in the upper four-bit adder to produce the sum S4S3S2S1S0. (II) The logic gates implement the expression for X. (III) The lower four-bit adder will add the correction 0110 to the sum bits only when X=1, producing the final BCD sum output represented by Σ3Σ2Σ1Σ0. X is also the carry output that is produced when the sum is greater than 01001. When X=0, there is no carry and no addition of 0110 and Σ3Σ2Σ1Σ0=S3S2S1S0.

Lec-27, Pg-01

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980

Telephone : PABX : 9661920-73/4980

**dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
**

XvKv-1000, evsjv‡`k

**DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
**

DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

**September 28, 2010 Dated, the………………………….
**

B1 B0 BCD code group

B3 B 2

4-bit parallel adder 74HC283 Carry to next BCD adder X 74HC32 74HC08 Correction logic S3 S2 S1 S0 A3 A2

C0, carry from lower position adder A1 A0 BCD code group

74HC32 B 3 B2 4-bit parallel adder 74HC283 A3 A2 B 1 B0 A1 A0 C0=0

C4 (not used)

Σ3 Σ 2

Σ1 Σ0 BCD sum

Correction adder

**Fig.: A BCD adder contains two four-bit adders and a correction-decoder circuit.
**

BCD codes for 3-digit number MSD A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 LSD A1 A0

CARRY

BCD adder

CARRY

BCD adder

CARRY

BCD adder

CARRY IN

Σ11 Σ10 Σ9 Σ8

Σ7 Σ6 Σ5 Σ4

Σ3 Σ2 Σ 1 Σ 0

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

BCD codes for 3-digit number

Fig.: Cascading BCD adders to add two three-digit decimal numbers. When decimal numbers with several digits are to be added together, it is necessary to use a separate BCD adder for each digit position. The above figure shows a block diagram of a circuit for the addition of two three-digit decimal numbers. The A register contains 12 bits, which are the three BCD code groups for one of the three-digit decimal numbers. The B register contains the BCD representation of the other three-digit decimal number.

Lec-27, Pg-02

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

`~ivjvcbx t wc,G,we,G·, 9661920-73/4980

Telephone : PABX : 9661920-73/4980

**dwjZ c`v_© weÁvb, B‡jKUªwb· I KwgDwb‡Kkb BwÄwbqvwis wefvM XvKv wek¦we`¨vjq
**

XvKv-1000, evsjv‡`k

**DEPT. OF APPLIED PHYSICS, ELECTRONICS & COMMUNICATION ENGINEERING UNIVERSITY OF DHAKA
**

DHAKA-1000, BANGLADESH FAX: 880-2-8615583 E-MAIL: APECE@univdhaka.edu

Ref. No............................

September 28, 2010 Dated, the………………………….

The code groups A3-A0 and B3-B0 representing the least significant digits are fed to the first BCD adder. This first BCD adder produces sum outputs Σ3Σ2Σ1Σ0, which is the BCD code for the LSD of the sum. It also produces a carry output that is sent to the second BCD adder. The second BCD adder adds A7-A4 and B7-B4, the BCD code groups for the second-decimal-digit position. It produces Σ7Σ6Σ5Σ4, the BCD code for the second digit of the sum. It also produces a carry output that is sent to the next BCD adder. [Ref.: Digital Systems Principles and Applications, R.J. Tocci and N.S. Widmer] Multipliers: Multiplication of binary numbers is usually implemented in microprocessors and microcomputers by using repeated addition and shift operations. Instead of adding all the partial products at the end, they are added two at a time and their sum is accumulated in a register called the accumulator register. When the multiplier bit is 0, that very partial product is ignored. The basic hardware arrangement of such a binary multiplier would comprise – (I) shift registers for the multiplicand and multiplier bits, (II) an accumulator register for storing partial products, (III) a binary parallel adder and (IV) a clock pulse generator to time various operations. The result of multiplication at the most can be equal to the sum of the number of bits in the multiplier and multiplicand. Figure below shows logic circuit of a 2x2 bit binary multiplier using a 4-bit adder.

B4 A4 B3 A3 B2 A2 B1 A1 CIN 74283 4-bit adder C0 SUM1 SUM2 SUM3 SUM4 COUT C1 C2 C3

A0 A1 B0 B1

Fig.: 2x2 bit binary multiplier. Binary multipliers are also available in IC form. Some of the popular type numbers in the TTL family include – (I) 74261 – 2x4 bit multiplier and (II) 74284 and 74285 – 4x4 bit multiplier. [Ref.: Digital Electronics Principles, Devices and Applications, Anil K. Maini]

Lec-27, Pg-03

In case of any query or suggestion please contact Sazzad, Lecturer, APECE, DU (url: sazzadmsi.webs.com)

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