P C C A R D S TA N D A R D

Volume 1 Overview and Glossary

PCMCIA JEIDA ©1999, PCMCIA/JEIDA All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, mechanical, electronic, photocopying, recording or otherwise, without prior written permission of PCMCIA and JEIDA. Printed in the United States of America. PCMCIA (Personal Computer Memory Card International Association) 2635 North First Street, Suite 209 San Jose, CA 95134 USA +1-408-433-2273 +1-408-433-9558 (Fax) http://www.pc-card.com JEIDA (Japan Electronic Industry Development Association) Kikai Shinko Kaikan, 3-5-8, Shibakoen Minato-ku, Tokyo 105, JAPAN +81-3-3433-1923 +81-3-3433-6350 (Fax) http://www.pc-card.gr.jp The PC Card logo and PC Card are trademarks of PCMCIA, registered in the United States. The PC Card logo and PC Card are trademarks of JEIDA, registered in Japan. Cover Design: Greg Barr PCMCIA HAS BEEN NOTIFIED BY CERTAIN THIRD PARTIES THAT THE IMPLEMENTATION OF THE STANDARD WILL REQUIRE A LICENSE FROM THOSE THIRD PARTIES TO AVOID INFRINGEMENT OF THEIR RIGHTS. PCMCIA HAS OBTAINED FROM SOME, BUT NOT ALL, OF THOSE PARTIES A GRANT OF IMMUNITY THAT PCMCIA WILL EXTEND TO YOU, CONTINGENT UPON YOUR ENTERING INTO AND DELIVERING TO PCMCIA THE RECIPROCAL GRANT OF IMMUNITY AGREEMENT CONTAINED ELSEWHERE IN THIS STANDARD. IMPORTANT: In order to receive the Grant of Immunity, the owner of this Standard must sign and return the enclosed Registration Card to: PCMCIA 2635 North First Street, Suite 209 San Jose, CA 95134 USA NEITHER PCMCIA NOR JEIDA MAKES ANY WARRANTY, EXPRESS OR IMPLIED, WITH RESPECT TO THE STANDARD, INCLUDING AS TO NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. THIS STANDARD IS PROVIDED TO YOU ÒAS IS.Ó OS/2 is a trademark of IBM Coporation. Intel and Pentium are registered trademarks of Intel Corporation. MS-DOS, OnNow and Windows NT are trademarks and Microsoft, Windows and Win32 are registered trademarks of Microsoft Corporation. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

Document No. 0299-01-2000 First Printing, February 1999

OVERVIEW AND GLOSSARY

CONTENTS
1. Introduction____________________________________________1
1.1 PC Card Standard Overview ..............................................................................................1 1.2 History .................................................................................................................................2
1.2.1 History of the PC Card Standard ........................................................................................................................................2 1.2.2 PCMCIA Standard Release 1.0/JEIDA 4.0 (June 1990)...............................................................................................3 1.2.3 PCMCIA Standard Release 2.0/JEIDA 4.1 (September 1991)..................................................................................3 1.2.4 PCMCIA Standard Release 2.01 (November 1992) ......................................................................................................3 1.2.5 PCMCIA Standard Release 2.1/JEIDA 4.2 (July 1993) ...............................................................................................3 1.2.6 PC Card Standard February 1995 (Release 5.0) ............................................................................................................3 1.2.6.1 PC Card Standard March 1995 Update............................................................................................................4 1.2.6.2 PC Card Standard May 1995 Update................................................................................................................4 1.2.6.3 PC Card Standard November 1995 Update.....................................................................................................4 1.2.6.4 PC Card Standard March 1996 Update............................................................................................................4 1.2.7 PC Card Standard March 1997 (Release 6.0) .................................................................................................................4 1.2.8 PC Card Standard 6.1 Update (April 1998)....................................................................................................................4 1.2.9 PC Card Standard Release 7.0 (February 1999) ............................................................................................................5

1.3 Uses......................................................................................................................................6 1.4 Future Trends ......................................................................................................................6 1.5 The PC Card Standard ¾ A PCMCIA and JEIDA Joint Release......................................7

2. Definitions and Terminology ____________________________9 3. Compatibility _________________________________________11 4. Technical Descriptions _________________________________13
4.1 Electrical Specification.......................................................................................................13 4.2 Physical Specification........................................................................................................14 4.3 Metaformat Specification..................................................................................................15 4.4 Card Services Specification ...............................................................................................16 4.5 Socket Services Specification.............................................................................................17 4.6 Media Storage Formats Specification ...............................................................................18 4.7 PC Card ATA Specification..............................................................................................19 4.8 XIP (eXecute In Place) Specification .................................................................................20 4.9 Guidelines ..........................................................................................................................21 4.10 Host System Specification...............................................................................................22 4.11 Specific Extensions ..........................................................................................................23
4.11.1 PCMCIA Specific Extensions ............................................................................................................................................2 3

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CONTENTS
4.11.1.1 Auto-Indexing Mass Storage (AIMS).............................................................................................................2 3 4.11.1.2 15 Position Shielded Latching I/O Connector ............................................................................................2 3 4.11.1.3 Modem I/O Connector for Open Systems.....................................................................................................2 3 4.11.1.4 Recommended Extensions..................................................................................................................................2 3 4.11.2 JEIDA Specific Extensions .................................................................................................................................................2 3 4.11.2.1 Small Block FLASH Format ..............................................................................................................................2 3 4.11.2.2 Still Image, Sound and Related Information Format for PC Card Digital Still Camera (DSC) 68-Pin Standards.........................................................................................................................................................2 3 4.11.2.3 DRAM Card Specifications................................................................................................................................2 3

5. Glossary______________________________________________ 25

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1. I N T R OD U C T ION
This Overview describes the Personal Computer Memory Card International Association (PCMCIA) and the Japan Electronic Industry Development Association (JEIDA) PC CardÔ Standard which is the result of countless hours of effort by the members of JEIDA and PCMCIA. PCMCIA and JEIDA are grateful for and acknowledge the dedicated efforts of the PCMCIA and JEIDA staff and volunteer members in the creation and production of this Standard.

1.1 PC Card Standard Overview
The Personal Computer Memory Card International Association has an international membership comprising hundreds of member companies from all disciplines: computer manufacturers, semiconductor companies, peripheral vendors, software developers, and more. The Japan Electronic Industry Development Association was established in 1958 as a non-profit organization interested in contributing to JapanÕs economic prosperity by stimulating development in the electronics industry. PCMCIA and JEIDA have developed a standard for a credit card-sized adapter, called a ÔPC CardÕ that does for notebook and other portable computers what the AT bus did for desktop PCs ¾ provide universal, non-proprietary expansion capability. The Physical Specification defines a 68-pin interface between the peripheral card and the PC Card ÔsocketÕ into which it gets inserted. It also defines two standard form factors, full-size and Small PC Cards, each in three thicknesses, called Type I, Type II and Type III. Type I, the smallest form factor, often used for memory cards, measures 3.3 mm in thickness. Type II, available for those peripherals requiring taller components such as LAN cards and modems, measures 5 mm thick. Type III is the tallest form factor and measures 10.5 mm thick. Type III PC Cards can support small rotating disks and other tall components. Smaller size cards can always fit into larger sockets but the reverse is not true. The Electrical Specification defines three basic classes of PC Cards: 16-bit PC Cards, 32-bit CardBus PC Cards, and Custom Interface PC Cards. Defined are characteristics of each interface including power, signaling, configuration, and timing requirements. Also, the PC Card Host System Specification describes host-side power management and a thermal ratings system. In addition to specifying electrical and physical requirements, the PC Card Standard has also defined a software architecture to provide Òplug and playÓ capability across the widest possible range of products. The Socket Services Specification defines a BIOS level interface that masks the hardware implementation from card vendorsÕ drivers. It identifies how many sockets are in the host and when a card is inserted or removed from a socket. It prevents the card driver from having to talk directly to a specific chip. The Card Services Specification defines an Application Programming Interface that interfaces to Socket Services and automatically provides management of system resources, such as interrupt assignments and memory windows, for cards as they become active in the system. Also, the Metaformat Specification defines the structure and contents of card description information called the Card Information Structure. The PC Card Standard also includes three application specific specifications. The Media Storage Formats Specification defines how data are to be formatted on some PC Card storage devices. The PC Card ATA Specification defines the operation of mass storage devices using the ANSI ATA Interface for Disk Drives in the PC Card environment. The XIP Specification defines a method to directly execute applications from ROM without loading the image into RAM. Also included is a set of Guidelines intended to assist developers with implementation examples along with further explanations of the PC Card Standard.

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INTRODUCTION

1.2 History
1.2.1 History of the PC Card Standard
In 1985, the standardizing activity of PC Card Technology began with the Japan Electronic Industry Development Association (JEIDA). The organization was formed to promote memory cards, personal computers and other portable information products, and by 1990, JEIDA had released four specifications. The Personal Computer Memory Card International Association (PCMCIA) was founded in 1989 by a small group of companies that wanted to standardize memory cards for the classic reasons behind standardization ¾ multiple sources, lower and shared risks, and larger markets. At that time a company called Poqet Computer had designed a computer that used only memory cards as removable storage. Poqet needed software application developers to put their products on memory cards. At the same time there were ten different types of memory cards sold by different manufacturers and no real effort at standardizing them. An initial group of about 25 companies met in San Jose, California and agreed on the need for memory card standardization. This was the birth of PCMCIA. From the beginning, there have been two primary committees within PCMCIAÑthe Technical and Marketing committees. These committees have worked together to develop the PC Card standards based not only on what was technologically feasible but also on what the market demanded. These two committees quickly recognized that the same slot in a host system and the same form factor card could be used for I/O capabilities such as fax/modem in addition to memory cards. The ability to put I/O capabilities on a card soon became the main attraction for the adoption of the technology in the rapidly expanding mobile computing market. The addition of a PC Card slot would allow mobile computers to have an easily accessible bus expansion capability. PCMCIA and JEIDA also expanded their mission and purpose to embrace any technology that would work in a PC Card form factor rather than restricting it to silicon-based technology. This allowed for the development of high capacity rotating storage cards. Today, virtually every type of card imaginable is available, including fax/modems, audio, SCSI, video, LAN adapter, and global positioning system cards. Almost all mobile computers shipped today have PC Card sockets which support 16-bit PC Cards along with the latest 32-bit CardBus technology. JEIDA and PCMCIA have ensured that PC Card technology has kept pace with industry trendsÑallowing for lower voltage and higher performance cards. PC Card technology has fast become the preferred bus expansion interface in mobile computing and is a growing force in the mobile computing and consumer electronics markets. PCMCIA and JEIDA are both standards setting bodies and trade associations. PCMCIAÕs mission is ÒTo develop standards for modular peripherals and promote their worldwide adoption.Ó There have been various revisions of the PC Card Standard as described in the following section.

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OVERVIEW AND GLOSSARY

1.2.2 PCMCIA Standard Release 1.0/JEIDA 4.0 (June 1990)
The first release of the Standard defined the 68-pin interface and both the Type I and Type II PC Card form factors. The Integrated Circuit card form factor which utilized the 68-pin and socket connectors was originally defined by the Japan Electronic Industry Development Association (JEIDA) in 1985. The initial release of the PCMCIA Standard also specified all the electrical and physical requirements for memory cards. It defined the Metaformat or Card Information Structure (CIS) that is critical to interoperability and plug-andÐplay for PC Cards. There was no concept of input/output (I/O) cards in the first release of the PC Card Standard.

1.2.3 PCMCIA Standard Release 2.0/JEIDA 4.1 (September 1991)
The second release of the standard defined an I/O interface for the same 68Ðpin interface as was used for the PCMCIA memory cards in the first release of the Standard. The second release of the Standard also added various clarifications to the first release, support for dualÐvoltage memory cards, and sections dealing with card environmental requirements and test methods. The initial version of the software Application Programming Interface (API) embodied in the BIOSÐtype Socket Services Specification was published in Release 2.0. Many additions were made to enhance the Card Information Structure (CIS) definitions, including the addition of geometry and interleaving tuples. Support for eXecute In Place (XIP) was also added in this release.

1.2.4 PCMCIA Standard Release 2.01 (November 1992)
The initial version of the PC Card ATA Specification defining an interface for PC Cards using the AT Attachment Standard was defined in this release. To accommodate rotating media PC Cards, the Type III PC Card was added with this release. The Auto-Indexing Mass Storage (AIMS) Specification, geared toward digital images, was also added. The initial version of the Card Services Specification was published with this release. This part of the standard PC Card software API defined the operating system extensions required for resource management of cards, sockets and drivers. Socket Services was enhanced to accommodate the requirements of the new Card Services interface. Additional changes were made to the Metaformat (CIS) definitions to accommodate new PC Card functionality.

1.2.5 PCMCIA Standard Release 2.1/JEIDA 4.2 (July 1993)
The Card and Socket Services software specifications were enhanced based on implementations done in compliance with the previous Standard to form a complete and robust software architecture and API necessary for compatible implementations. The Electrical and Physical sections of the standard were updated with corrections and additions, and the CIS was again improved with additional definition information.

1.2.6 PC Card Standard February 1995 (Release 5.0)
The PC Card Standard February 1995 Release added information to improve compatibility with the Standard by requiring a Card Information Structure (CIS) on every PC Card, extending the amount of information within the CIS, adding a Guidelines volume to help developers implement the Standard, and defining common media storage formats. Ó 1999 PCMCIA/JEIDA 3

INTRODUCTION The Standard was also enhanced to support the following optional features: · · · · · Low-voltage-only operation (3.3 volt) Hardware Direct Memory Access (DMA) Multiple-function cards Industry standard power management interface (APM) A high throughput 32Ðbit bus mastering interface (CardBus)

1.2.6.1 PC Card Standard March 1995 Update
Included as an errata to the First Printing of the February 1995 Release. Included general editorial changes.

1.2.6.2 PC Card Standard May 1995 Update
Included along with the March 1995 Update in the Second Printing. Included change to Power Waveforms at Power-on in the Electrical Specification.

1.2.6.3 PC Card Standard November 1995 Update
Included along with the March 1995 & May 1995 Updates in the Third Printing. Included Custom Interfaces and other updates.

1.2.6.4 PC Card Standard March 1996 Update
Released only as errata. Included Flash Translation Layer, Zoomed Video Port and other updates.

1.2.7 PC Card Standard March 1997 (Release 6.0)
The PC Card Standard March 1997 Release provided a variety of compatibility and functionality features. All of the Updates to the February 1995 release, including Custom Interfaces and the Zoomed Video (ZV) Port Custom Interface were incorporated into this release. A Thermal Ratings system was added that allows cards and hosts to be rated for thermal output, providing an interface to warn users of a potentially damaging thermal condition. The following features were also added: · · · · · · Power Management ISDN Function Extension Tuples Security and Instrumentation Card Function ID Tuples Physical Socket Naming Hot Dock/Undock Software Support Streamlined PC Card Software Configuration

1.2.8 PC Card Standard 6.1 Update (April 1998)
The PC Card Standard 6.1 Update added the following features: · 4 PCI/CardBus Power Management Ó1999PCMCIA/JEIDA

OVERVIEW AND GLOSSARY · · · · Small PC Card Form Factor Socket Services Packet Interface Win32 Bindings Editorial changes to the Electrical Specification, Metaformat Specification, Card Services Specification, Media Storage Formats Specification (FTL), PC Card ATA Specification, and PCMCIA Specific Extensions (Modem I/O Unshielded Connector)

1.2.9 PC Card Standard Release 7.0 (February 1999)
The PC Card Standard Release 7.0 added the following features: · · · · · DVB Custom Interface Windows NT 4.0 Kernel Mode Bindings PC Card Memory Paging Serial Bus Adapter Function Extension Tuples Editorial changes to the Electrical Specification, Metaformat Specification, Card Services Specification, and Host System Specification

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INTRODUCTION

1.3 Uses
PC Card technology is used in a wide variety of products including notebook computers, subnotebook computers, palmtop computers, pen computers, desktop computers, cameras, printers, telephones, medical instruments, television set-top boxes and other embedded application hosts. PC Cards supporting storage and I/O applications for the host systems mentioned above also incorporate PC Card technology as does the system and application software required to operate the cards and hosts. The PC Card Standard is aimed at developers of the above mentioned PC Card-based products and is designed for the technical audience. The Standard is used by technical developers to create standard PC Card products such as cards, hosts, silicon, and software.

1.4 Future Trends
The future holds great promise for the PC Card technology which has been widely adopted by the mobile computer industry. We can look forward to the continuing acceptance of this technology by the computing industry in desktops, printers, and other computer peripherals as well as products that are the result of the merging of computers with other technologies such as telephones and television set-top boxes. The future will also see the PC Card interface evolve to include high speed serial buses to support high speed networking, video and other applications. Any applications that require a small, portable and rugged industry standard interface to a system bus will find PC Card technology and the PC Card Standard suitable to their needs. PCMCIA and JEIDA will continue to maintain, enhance, and extend the PC Card Standard to accommodate the ever-changing technological and market requirements.

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OVERVIEW AND GLOSSARY

1.5 The PC Card Standard ¾ A PCMCIA and JEIDA Joint Release
This PC Card Standard had its early roots in technical organizations and volunteers in Japan and in the United States. The more recent activities creating the PC Card Standard have been worldwide. The Japan Electronic Industry Development Association, JEIDA, recognized the importance of integrated circuit memory cards back in 1985 and has standardized a wide range of card interfaces and form factors since that time. This work included publication of the JEIDA Version 3 IC Memory Card Specifications; one of which, the 68-pin version, served as the starting point for the PC Card Standard. The Personal Computer Memory Card International Association, PCMCIA, was founded in Silicon Valley, California in 1989 to promote the development and standardization of memory cards for mobile computers. PCMCIA grew quickly to encompass a worldwide membership with chapters and local host offices on several continents. Beginning in 1989, JEIDA and PCMCIA worked closely together to develop the similar documents of the JEIDA IC Memory Card Specification and the PCMCIA Standards. While these documents and their later enhancements were similar, they were not identical and in some cases there were discrepancies both in language and content between the documents. TodayÕs PC Card Standard is the unified result of a joint effort between PCMCIA and JEIDA to enhance the clarity and scope of the documents as well as to resolve the differences between the specifications. The PC Card Standard is published jointly by PCMCIA and JEIDA. Thousands of hours contributed by corporations and individuals from all around the globe have supplemented the efforts of the professional staffs of JEIDA and PCMCIA in creating this worldwide PC Card Standard.

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OVERVIEW AND GLOSSARY

2. DE F IN IT ION S

AN D

TE R MIN OL OGY

There are many terms and conventions used in the PC Card Standard and a good understanding of them will make reading and working with the Standard much easier. General terms and conventions that can be broadly applied will be described in this section. Specific terms and conventions that relate to individual sections of the Standard will be described at the beginning of each section. The term ÔPCMCIAÕ is an abbreviation for Personal Computer Memory Card International Association, and is used to refer to the organization itself. The term ÔPC CardÕ is used to refer to the technology as well as being a generic term for any products based upon the PC Card Standard. ÔPC CardÕ is used as a generic term to refer to both 16-bit PC Cards and 32-bit CardBus PC Cards. The term ÔPC Card StandardÕ is the official name of the set of specifications produced jointly by PCMCIA and JEIDA. The term ÔStandardÕ, with a capital ÔSÕ, is a proper name used as a short form replacement for the complete term: the PC Card Standard. When referring to products (both card and sockets) that support 16-bit operation, the terms Ô16-bit PC CardÕ or Ô16-bit PC Card socketÕ should be used. ÔCardBus PC CardÕ is the correct term that can be used when referring to the 32-bit bus master specification of the PC Card Standard. Note that both the ÒCÓ and the ÒBÓ are capitalized. The terms ÔPCMCIA CardsÕ and ÔPCMCIA socketÕ should never be used.

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OVERVIEW AND GLOSSARY

3 . C O M P AT I B I L I T Y
Over time, PC Cards containing new technologies have been introduced, and significant new capabilities have been added to the Standard. At the same time, considerable experience has been gained by card, host and software vendors, and opportunities to improve compatibility have been recognized. The goal remains to make PC Card technology as easy to use as possible with the ideal scenario being that the customer takes the PC Card out of its box, plugs it into the system and begins to use it. It is recommended that in order to support PC Card technology, developers keep the goal of compatibility in mind and use the areas of the Standard designed to support compatibility and interoperability. Also, there is opportunity within the PCMCIA organization meetings to discuss compatibility and share information. The Standard encompasses many capabilities and optional features. Due to this complexity, manufacturers can choose different feature sets or even have different interpretations. Therefore, development planned for flexibility and adaptability will allow for the greatest compatibility. One way to be prepared for the variety of the real world is to perform exhaustive testing of designs with all of the significant components: from software functions and modules to entire platforms. On a very general level, the following describes how a card and system interact when they are Òcompatible:Ó For a card to operate properly, the host must first be able to provide adequate power at the correct voltage(s) to identify and operate the card. It must successfully identify the card by reading its Card Information Structure (CIS), and, in some cases, by sensing several pins on the interface. These pins are important in systems mechanically able to accept CardBus or other low voltage cards. The CIS contains detailed information on a card including its allowed ÒconfigurationsÓ which tell the host system the various ways that the card can be set up and what system resources are required. Once the card has been identified, the system must determine if the card requires a user-installed Card Services client driver (typically LAN cards, SCSI cards, audio cards or CardBus cards). If no user installed driver software is found, the system then determines whether the card can be supported by the hostÕs built-in ÒSuper ClientÓ driver (typically memory cards, ATA devices or Fax/Modems). The host then links the card with the appropriate driver and configures the card and the socket. In the case of a data storage device such as a memory card or disk drive, the file system must be able to access the data on the card. This sometimes requires a link to be established with a specific installable file system. A user may want to ÒsuspendÓ and ÒresumeÓ the operation of notebook or other system with PC Cards in the slots. To do this successfully, a card-specific routine must communicate with advanced power management software, which must then access the card through Card and Socket Services. Lastly, Card Services Client Drivers must operate consistently from one card supplier to the next, and be as flexible as possible to accommodate varying system configurations automatically. Also, Òcard-awareÓ application programs, like communications programs, need to coexist with older applications programs.

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OVERVIEW AND GLOSSARY

4 . TE C H N IC AL DE S C R IP T ION S
4.1 Electrical Specification
The Electrical Specification specifies the connector pinout, interface protocol, signaling environment, interface timings, programming model, and specifics of card insertion, removal, power up, and configuration. The Electrical Specification describes three basic classes of PC Cards: 16Ðbit PC Cards, CardBus PC Cards, and Custom Interface PC Cards. The 16-bit PC Card interface provides an ISA compatible interface for full-size and Small PC Cards. This interface supports standard ISA interrupts, and is intended to support both memory and I/O applications. The 16-bit PC Card interface also supports advanced features such as DMA. To address the class of applications which require higher performance and to take advantage of host systems that implement the PCI system bus, a 32-bit interface was developed known as CardBus. This interface provides 32-bit bandwidth, reduced latency via bus master capability, or both. CardBus hosts are required to support 16-bit PC Cards. The Small PC Card form factor does not support the CardBus interface. Custom Interface PC Cards allow the PC Card interface to be tailored to specific applications. The PC Card Custom Interface has been used to provide a high speed video path through the Zoomed Video (ZV) Port Custom Interface and to provide security to television set-top boxes through the Digital Video Broadcasting (DVB) Custom Interface. PC Cards which implement Custom Interfaces must include CIS information to allow a compatible host to identify and configure the card for operation.

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TECHNICAL DESCRIPTIONS

4.2 Physical Specification
The Physical Specification specifies the PC CardÕs physical outline dimensions, basic mechanical capabilities and the environmental conditions under which the PC Cards are expected to operate. Information is provided for Type I, II, and III full-size and Small PC Cards, for 5 volt and low voltage equivalents, and CardBus (the 32-bit PC Card interface). Interface dimensions for the 68-position host connectors (with pin contacts) and the mating card connectors (with female socket contacts) are provided. The specification, in consideration of EMI issues, also presents a method for grounding the PC Card along with applicable material and electrical considerations helpful to both system designers and card users. Connectors for CardBus applications are included. A special host/header connector is required that will assure proper grounding. This host will also accept standard low voltage Type I, II and III PC Cards. Host PCB board layout dimensions are provided for various footprint options, for both SMT (Surface Mount Technology) and through-hole mounting. The PC Cards are intended to function in both office and harsh environments. These environments are defined. Test criteria are provided using industry MIL, ISO and JIS Standard specifications. This provides manufacturers with quantitative data to help confirm expected application performance. It is up to the individual suppliers to qualify their parts to this, and any other manufacturerÕs specification. Separate criteria are defined for PC Cards involving SRAM and rotating memory components. Where applicable, the specificationÕs requirements include considerations for PC Cards incorporating write-protect switches and batteries.

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OVERVIEW AND GLOSSARY

4.3 Metaformat Specification
The Metaformat Specification specifies the structure and contents of card description information. This card description information is stored on the card and is commonly called the Card Information Structure or CIS. As is done with networking standards, the Metaformat is a hierarchy of layers. Each layer has a number, which increases as the level of abstraction gets higher. Below the Metaformat is the physical layer: the electrical and physical interface characteristics of PC Cards. The Metaformat layers include the Basic Compatibility Layer, the Data Recording Format Layer, the Data Organization Layer, and the System-Specific Layer. The benefits of using Metaformat include flexibility in describing configuration options, ability to handle numerous somewhat incompatible data recording formats and data organizations.

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The main purpose behind the Card Services (CS) API is to provide a universal software interface that is independent from the hardware that manipulates PC Cards and PC Card Sockets. The Card Services interface has two goals. sockets and host system resources. Software applications and device drivers that utilize PC Cards are the clients. Card Services is the server providing services requested by the clients. there are bindings included that describe the detail of how to access a Card Services implementation in a particular environment.TECHNICAL DESCRIPTIONS 4. Card Services is the middle layer in a multiple layer software architecture. Clients register with Card Services and are notified of PC Card events synchronously via a Callback.4 Card Services Specification The Card Services Specification specifies a software Application Programming Interface (API). Card Services is very closely related to Socket Services. The Card Services interface is structured in a client/server model. Clients use Card Services to allocate system resources to a PC Card function and to configure the PC Card. the interface provides a centralized location for common functionality required by PC Card software. The API is specified in a host system/operating system-independent format. The first is to promote sharing of PC Cards. The clients make up the top layer of the architecture. 16 Ó1999PCMCIA/JEIDA . Second. However.

Windows provide access via host system memory or I/O address space to PC Card address space. Some services allow software to inquire about the capabilities for a specified object. Each object type has a particular area of functionality. The main purpose behind the Socket Services (SS) API is to provide a universal software interface to the hardware that controls sockets for PC Cards.5 Socket Services Specification The Socket Services Specification specifies a software Application Programming Interface (API). a Socket Services implementation is invoked via a software interrupt with commands and data passed in CPU registers. Sockets are the receptacles for PC Cards. Individual services of Socket Services provide certain functionality. The interface masks the details of the hardware used to implement these sockets. Socket Services manages the hardware by utilizing it as a number of object types. windows and EDC generators. Other services return the current settings of a specified object. In addition. Ó 1999 PCMCIA/JEIDA 17 . These requests are made in a host system processor and operating environment-specific manner. EDC Generators calculate error detection codes by monitoring data transfers. Also. Socket Services is the lowest layer in a multiple layer software architecture.OVERVIEW AND GLOSSARY 4. This masking allows the development of higher-level software that is able to utilize PC Cards without any detailed knowledge of the actual hardware interface. Adapters connect a host systemÕs bus to PC Card sockets and provide the sockets. on x86 architecture platforms running DOS. For example. there are services that report on current card status and provide indirect access to PC Cards for socket controllers that cannot map PC Card address space into host system address space. the settings for a specified object are updated using other services. Socket Services is very closely related to the Card Services Specification. Socket Services performs all of these services when software requests them.

PCMCIA and JEIDA are only acknowledging this information has been used to record data on a PC Card and.6 Media Storage Formats Specification The Media Storage Formats Specification specifies how data are formatted on PC Card storage devices to promote the exchange of these cards among different host systems. The Media Storage Formats Specification is intended to provide enough information to allow software developers to use data stored on PC Cards by other host systems using potentially different operating and file systems. Each of these storage technologies have unique characteristics which may benefit from different storage techniques and handling. for both silicon and rotating media. translation layer or media type information in this document does not constitute an endorsement by PCMCIA or JEIDA.TECHNICAL DESCRIPTIONS 4. algorithms for updating the data on the PC Card are not specified. only the storage format. Unless required to understand the data structures used on the PC Card. This has resulted in the development of different storage formats and/or partitioning for PC Cards using these devices. file format. NOTE: The inclusion of partition. These include memory cards using various types of volatile and non-volatile devices and ATA disk drives. 18 Ó1999PCMCIA/JEIDA . in some cases. that PCMCIA and JEIDA members have agreed that using the documented implementation may reduce problems encountered when attempting to interchange data between host systems.

and IREQ# signals depending on whether memory mapped or I/O mode addressing is used. READY. both Cylinder-Head-Sector as well as Logical Block addressing are supported. Since both the PC Card ATA Specification and the ANSI ATA Standard define resets. block I/O. detailing the operation required since inter-card communication is not provided. Ó 1999 PCMCIA/JEIDA 19 . The method for implementing ANSI ATA Master/Slave devices is described as the Twin Card option in the PC Card ATA Specification.221-1994) in the PC Card environment. In addition. The PC Card ATA Specification defines four mappings of the ANSI ATA Command/Control Registers into host memory and I/O space: memory mapped. This definition includes how the 8-bit ANSI ATA registers are accessed and the use of the RESET. the effects and protocols associated with the different reset methods are described. This standard includes both the usage of the ANSI ATA-defined protocols and the differences required due to conflicts between the PC Card and ANSI ATA Standards.7 PC Card ATA Specification The PC Card ATA Specification specifies the operation of mass storage PC Cards using the protocol of the ANSI AT Attachment (ATA) Interface for Disk Drives (X3. Finally.OVERVIEW AND GLOSSARY 4. mandatory and optional CIS tuples for PC Card ATA mass storage devices are defined to ensure that PC Card ATA implementations are consistent from vendor to vendor. ANSI ATA Primary and ANSI ATA Secondary.

in the non-XIP world. a program is loaded from a disk (or ROMDISK) and essentially copied into system RAM.e. pages not in memory must be explicitly paged in by software at some level). SXIP applications comprise an execution image of at most 64K of code and/or read-only data. data structures. only the data is stored in RAM. The current PC Card specification for XIP is designed primarily for low-end real mode x86 type systems. EXIP is for those systems with very large address spaces or with implicit paging (i. The XIP Specification describes the Metaformat tuples. and are monolithic in nature. Under the XIP scheme.. similar to an Intel 80386 extended-addressing-mode-execution environment.e. The benefit of XIP is savings of both system RAM and system ROM. EXIP applications are structured to operate in an environment where no paging is necessary. SXIP and EXIP. where price sensitivity is high and system RAM is a precious resource.. there is an immediate waste of space since two images of the program exist: one in RAM and one on the disk. Usually. and the Application Programming Interface (API) for XIP. 20 Ó1999PCMCIA/JEIDA . These applications do no overlaying of any sort. code is left executing from the original instance in ROM. LXIP Applications are structured to operate in a 16 KB pagedexecution environment. Thus. pages not in memory when accessed are placed into memory without intervention at a software level). as well as the architecture and load format of XIPcompliant applications. SXIP is for those systems which have only very limited paging mechanisms. from where it is executed. LXIP is for systems where demand-paging is required (i. Three types of XIP support are defined in order to support three real-world architectures: LXIP. driver architecture.TECHNICAL DESCRIPTIONS 4.8 XIP (eXecute In Place) Specification The XIP (eXecute In Place) Specification specifies a method to directly execute applications from ROM without loading the image of the application into RAM prior to execution.

9 Guidelines The Guidelines document provides implementation examples and further explanations of the PC Card Standard to: · · Enhance the interoperability of PC Card components. Facilitate the development of PC Card technology by increasing the understanding of the Standard by PC Card Implementation community. they are implementation examples.OVERVIEW AND GLOSSARY 4. Rather. and applications. Electrical Guidelines · · CardBus/PCI Common Silicon Thermal Logo Usage Physical Guidelines · · · · Modem I/O Unshielded Connector for Open Systems 15 Position Shielded Latching I/O Connector Maximum I/O Connector Dimensions Extended Card Dimensions Software Guidelines · · · · Enabler Capabilities and Behavior Card-Application Interaction CardBus Operational Scenarios CIS Design for Several Common Implementations Ó 1999 PCMCIA/JEIDA 21 . system hardware and software. The Guidelines included are described below. suggestions and hints. including card hardware and software. These guidelines are not requirements made by the PCMCIA or JEIDA Standards organizations.

22 Ó1999PCMCIA/JEIDA . The device described is a bridge between a PCI bus and two CardBus/16-bit PC Card sockets. The PCI Bus Power Management Interface Specification for PCI-to-CardBus Bridges establishes a standard set of PCI peripheral power management hardware interfaces and behavioral policies.TECHNICAL DESCRIPTIONS 4. this infrastructure enables an operating system to intelligently manage the power of PCI functions and buses. Once established.10 Host System Specification The PC Card Host System Specification specifies requirements for host systems containing a PC Card socket. The PCI-to-CardBus Bridge Register Description section is provided to aid in development of CardBus bridges that have some level of software interface commonality. The purpose of determining the thermal rating is to ensure that the heat generated and dissipated within the body of the PC Card does not thermally exceed the capabilities of the host system to remove excessive heat in order to maintain the PC Card at an acceptable temperature limit. The System Thermal and Power section defines a method which can be used in determining the host platform thermal rating.

2. Please refer to previous releases of the PC Card Standard or contact PCMCIA for the AIMS Specification.2 15 Position Shielded Latching I/O Connector This section has been moved to the Guidelines.11.1.2.2 Still Image. Please refer to previous releases of the PC Card Standard or contact JEIDA for this specification. As of the current release.1 Auto-Indexing Mass Storage (AIMS) The AIMS Specification has been removed from the PC Card Standard.11.1.2.11.1. Sound and Related Information Format for PC Card Digital Still Camera (DSC) 68-Pin Standards This specification is maintained independently by JEIDA.11.11. 4.1 Small Block FLASH Format This specification has been extended and included as the Physical Format Specification of the SmartMedia Standard.1 PCMCIA Specific Extensions 4.2 JEIDA Specific Extensions 4.11.11. 4. These two volumes allowed each organization to provide specifications unique to its respective clientele.4 Recommended Extensions This section has been moved to the Guidelines. 4. Please refer to previous releases of the PC Card Standard or contact JEIDA for this specification.11. 4.3 Modem I/O Connector for Open Systems This section has been moved to the Guidelines. while maintaining all other features under a common standard release.OVERVIEW AND GLOSSARY 4. Ó 1999 PCMCIA/JEIDA 23 . The following sections explain the disposition of the previous Specific Extensions. there are no unique specifications. 4.11.11 Specific Extensions Prior releases of the PC Card Standard included two additional volumes: PCMCIA Specific Extensions and JEIDA Specific Extensions. 4.1.3 DRAM Card Specifications This specification is maintained independently by JEIDA. 4.

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Ó These registers include the Cylinder High.OVERVIEW AND GLOSSARY 5 .0/JEIDA 4. The time that the master waits after having asserted CREQ# until it receives CGNT#. Except for reflecting the state of the Busy condition and Interrupt condition.221-1994. Disk drives adhering to the ATA protocol are commonly referred to as IDE interfaced drives for PC compatible host systems. and configuration. Drive/Head. These are the Common Memory space. G L OS S AR Y Combined Terms and Abbreviations 16-bit PC Card access latency PC Cards using the PC Card Standard 16-bit interface originally defined in PCMCIA 1.0/JEIDA 4. There are three separate address spaces possible for a card. A reference to any of the CardBus PC Card card's physical address spaces. A function interface provided by one level of software to the level above it. Sector Number. Device Control. These terms refer to the state of a signal on the clock (CCLK) rising edge. This condition directly affects only the ATA registers and protocol.1 publications. Access latency consists of three parts: arbitration latency. They are defined in the ÒANSI ATA Standard. A reference to the three separate physical address spaces of CardBus PC Card: memory. Feature. See memory area. deasserted AT ATA six spaces which may map the card I/O or memory into the host system address space one space which may map the card expansion ROM into the host system address space the card's configuration spaces (one for each function) A logical entity that operates on a host system bus. ANSI X3.0 and PCMCIA 2. Drive Address. Acronym for Advanced Technology. a bus slave or to a combination of both. This space is the primary location for the Card Information Structure and for the Configuration registers on the card. bus acquisition latency and target latency. and Data registers. Refers to a 16-bit host system architecture using the 80x86 processor family which formed the basis for the ISA Bus definition. The time between a master requesting access to CardBus PC Card and the completion of the first data phase. The first component of access latency. See Command Block registers. Error. Opposite of Negated. A text string in ASCII format terminated with a byte of zero. The hardware which connects a host system bus to 68-pin PC Card sockets. the Configuration registers are unaffected. An address space is a collection of registers and storage locations contained on a PC Card which are distinguished from each other by the value of the Address Lines applied to the Card. the Attribute Memory space and the I/O space. not to signal transitions. This address space is defined only for bytes located on even byte addresses. Refers to the interface and protocol used to access a hard disk in AT compatible host systems. The I/O and memory address decoding options for these registers are defined in the PC Card ATA Specification The condition of the PC Card ATA mass storage card when the SRST bit in the Device Control register is set. control and status information to and from the PC Card. ATA Command Block ATA Registers ATA Soft Reset Attribute Memory Attribute Memory Space Ó 1999 PCMCIA/JEIDA 25 . A signal is asserted when it is in the state which is indicated by the name of the signal. The term applies collectively to functions of a bus master. which include: Adapter Address Space Address Space(s). 16-bit PC Card memory region selected by the REG pin for storage of CIS data and card configuration registers. Cylinder Low. One of the three address spaces available on a PC Card. Sector Count. Status. Acronym for AT Attachment. This address space is accessed by memory read and memory write operations which occur while the REG# signal is asserted. These registers are accessed by a host to implement the ATA protocol for transferring data. I/O. CardBus · · · agent ANSI ATA Standard Application Program Interface (API) arbitration latency area ASCIIZ Asserted asserted.

The Logical Block Address protocol uses sequential block addresses to access the media.selected by its address in the I/O address space. Each block of data represents one sector of data using the ATA Cylinder-Head-Sector address protocol. When BIOS is in Read-Only Memory devices it may be referred to as ROM BIOS. and Power Down Request. Acronym for BIOS Parameter Block. For example the Bus Segment Reset signal for a PCI to CardBus bridge component is RST# as defined in the PCI Local Bus Specification. Software which configures and/or accesses the card.GLOSSARY Audio Device Average Current backoff Base Address Register Window BIOS BIST register bit field Block A device that normally provides both a speaker and microphone for input/output of audio. Optionally. A Client routine to which Card Services may transfer control when events requiring Client notification occur. A data structure used by the Microsoft BPB/FAT File System to describe the size and format of storage media. Used to indicate to a target. Bus Segment Reset is defined as the hardware reset signal that is taken as actual physical input to a given component within a system. This may include: Block Allocation Map (BAM) BPB bridge BSY (ATA Busy bit) burst transfer bus acquisition latency bus commands bus master Bus Segment Reset bus slave Callback Handler Card Configuration and Status Register Card Enumeration Card Information Structure (CIS) Card software · · · CardBus Function device drivers applications generic enablers In PC Card parlance. the device can be limited to only output (speaker) capability. Refer to the PC Card Standard Electrical Specification for detailed information about this register. It provides status information about Status Changed state and Interrupt Request state. The process performed by the host to provide a unique card identification number to each drive when the Twin Cards option is used. Each CardBus function within a device generally has a separate software driver. Maximum current required averaged over 1 second. this is the CRST# signal. The basic data transfer mechanism of CardBus PC Cards. The type of transaction the master is requesting. An FTL control structure that is used to store Erase Unit block allocation information when hidden areas are not used to store this information. An agent which has an ability to obtain control of the interface and perform memory or I/O reads and writes to system resources. Audio Signal. An agent that sends or receives data under control of a bus master. A memory or I/O space mapping supported by a Base Address Register in the card's configuration space. The amount of time that a requesting device waits for the bus to become free after CGNT# has been asserted. card software is that software which could be a Card Services client. For CardBus cards. In addition. 26 Ó1999PCMCIA/JEIDA . Acronym for Basic Input/Output System. The host writes a unique number to the Copy field in the Socket and Copy register of each card sharing the same configuration. There are two types of slaves: I/O slave . A bit in the ATA Status register which is used by the ATA protocol to indicate that the ATA registers on the card are not available for use by the host. A block is the basic 512 byte region of storage into which the storage media is divided. It is used for control and status of built-in self tests. An optional register in the header region of the CardBus Configuration Space. also referred to as bus target or a bus transaction target. This Configuration register provides the host control for the following functions: Status Changed Signal. it can be used to advise the card that all I/O to the card will be eight bits wide. Addressing in the ATA protocol is performed on block boundaries. such as a CardBus controller. A burst is comprised of an address phase and one or more data phases. The logic that connects one computer bus to another. The second component of access latency. if the application allows. A set of functionality inside a CardBus card represented by one 256 byte configuration space. A field containing only 1 bit. A data structure which is stored on a PC Card in a standard manner which contains information about the capabilities of the card as well as the formatting and organization of data on the card. A directive to terminate the current transaction and retry it at a later time. See the Media Storgage Formats Specification. The master initiates a bus transaction.selected by its address in the memory address space. memory slave . allowing an agent on one bus to access an agent on the other. also referred to as retry.

Configuration is a process by which a host initializes or alters its socket operation and the Configuration registers on a PC Card to match the PC Card's capabilities to the host's capabilities and available system resources. These registers are: Feature register. this might be a set of electrical buffers or it may be a complete bus bridge. Cylinder Low register. A receptacle into which a CardBus PC Card can be inserted. A CardBus PC Card address space. CardBus PC Card. A PC Card bus multiplexing protocol is used to ensure that the odd bytes of this space can be accessed by both eight and 16 bit hosts. The ATA registers are located in this space when Memory Mapped ATA registers are supported. This is the traditional method for addressing a block of data on rotating media using the ATA protocol. its Interrupt Mode in bit 6 (Pulsed = 0 or Level =1) and the PC Card Soft Reset in bit 7 (Soft Reset asserted = 1). Sector Count register. This address space is accessed by memory read and memory write operations which occur while the REG# signal is negated. A single CardBus PC Card may contain up to eight CardBus Functions. Acronym for Card Information Structure.g. An I/O address decoding in which the Card decodes address lines (example A[3::0]). e.. Custom Interfaces support enhanced features. defined by the PC Card Standard. A bit is Cleared when its value is set to "0. or customized signals not applicable across architectures. Refers to the rising edge of the clock (CCLK). Depending on the definition of the system bus. Drive/Head register. Cylinder Low register. Sector Number register. but can apply to either 16-bit PC Card. utility program or application program. Seven of the Command Block registers are written by the host to provide a command and its parameters." A user of Card Services. A set of registers. A function which controls access to the CardBus PC Card interface. The term socket has similar meaning. Command register. Error register. or both types of sockets. The ATA Control Block registers include the following ATA registers: Alternate Status register. The chip(s) that isolate(s) the CardBus PC Cards from the rest of the system. This method partitions an address into a cylinder portion. The interface support functions supplied by the host system which is typically in a host CardBus PC Card adapter. The sequencer guarantees that the CardBus PC Card protocol is not violated. one or more heads within each cylinder and one or more sectors within each cylinder-head combination. It is used by the host to control the PC Card's Configuration Index in bits 5 to 0. Feature register. Acronym for Cylinder-Head-Sector addressing. An expansion connector that conforms to the electrical and mechanical requirements of the PC Card Standard for CardBus PC Cards. Sector Count register. Conventional memory area on 16-bit PC Cards when REG# is negated. a state machine. or XIP functions. which consists of a 64byte header space and a 192-byte device-dependent space. which are used by the host to control the operational configuration of the card.OVERVIEW AND GLOSSARY CardBus PC Card CardBus PC Card adapter PC Cards which use the 32-bit interface defined in the PC Card Standard. while the Socket is responsible for decoding all other address lines to produce the Card Enable signals for I/O cycles to the card. This 16 bit wide. Socket Services. or could be distributed in the system. such as internal bus extensions. An entity which performs the actual CardBus PC Card operations in a device. Drive/Head register. The only time that the signals have any significance on the CardBus PC Card interface is at the rising edge of the clock. and Status register. May be a device driver. but not the Alternate Status register. Sector Number register. Device Control register and Drive Address register. used for configuration and error handling. CardBus PC Card arbiter CardBus PC Card connector CardBus PC Card sequencer CardBus PC Card socket central resource CHS CIS Clear (a bit) Client clock edge (or edge) Cluster Command Block Registers Common Memory Common Memory Space Configuration configuration address space configuration cycle Configuration Option Register Configuration Registers Configuration Space Contiguous I/O Addresses Control Block Registers Custom Interface Cylinder Cylinder-Head-Sector Address Ó 1999 PCMCIA/JEIDA 27 . This is the same as the host CardBus PC Card adapter. Group of tracks accessed without moving the head used to read or write rotating media. Another term for a block. This register is the first of the Card Configuration registers located in the Attribute Memory Space of a PC Card. and Command register. This address space is defined both for bytes located at even and odd byte addresses. Cylinder High register. See configuration space A CardBus PC Card cycle used for system configuration via the configuration address space. memory space is one of the three address spaces available on the 16-bit PC Card. A method for specifying the location of a block of data on a mass storage device. The ATA Command Block registers include the following ATA registers: Data register(s).

for example. More specifically. a field is a distinct area in a register. the other as the ATA Slave. Refers to an expansion bus promoted by manufacturers of IBM-compatible personal computers that feature 32-bit addressing and bus-mastering capabilities. FTL Function function X (X is a number) 28 Ó1999PCMCIA/JEIDA . In this context. When DMA is performed by a DMA controller as opposed to having an I/O device become a master on the bus and move the data to/from memory on its own. In a multifunction PC Card. An access to a target's address range which is guaranteed to complete without being interrupted by an access to the same target by another bus master. A type of non-volatile media that may allow byte read and write access. The area of flash media that is handled as a single erasable unit by the FTL. Acronym for Direct Memory Access Acronym for Disk Operating System. and all cards will therefore have a function 0. a European television standardization body See Double Word. One device acts as the ATA Master. May be limited or optimized to one type of media.GLOSSARY DAA Device Dependent Space Digital Video Broadcasting Port Direct Memory Access (DMA) Direct Memory Access. Device Under Test. An FTL data structure that describes an Erase Unit. An internal host Bus which is available in some hosts and can be used to connect PC Card sockets to the host CPU. edge sensitive. Acronym for Flash Translation Layer. All Erase Units in an FTL partition are the same size. May be determined from DGTPL_BUS and DGTPL_EBS in the Device Geometry Info field of the Device Geometry tuple. (See Guidelines) The last 192 bytes of the CardBus PC Card Configuration Space. Part or extension of an operating system that manages files on a host system. A device that provides electrical protection to telecommunications medium. ÒdeviceÓ is synonymous to Òfunction. Acronym for Extended Industry Standard Architecture. An area of flash media that must be erased as a single unit due to the characteristics of the media. interrupts (IRQn#). Numbering begins at 0. In the context of configuration and memory space. and all cards will therefore have a function 1. An EISA bus can program each interrupt request line for either positive-true. Depending on context. DR DOS. Novell DOS. The size of an Erase Unit is set when the FTL partition is formatted and the Erase Unit Headers written to the media. Also known as atomic operation. each function is numbered uniquely. Not compatible with Micro Channel. See the Media Storgage Formats Specification. but requires the media to be erased before it is written. field may have different meanings. An interrupt detected by the host system based upon the transition of the signal from negated to asserted. A PC Card capability. Datalight ROM DOS. also known as Quadlet. The process of moving data from I/O to memory or vice versa without the intervention of the processor. See the Media Storgage Formats Specification. EISA Bus End-user Erase Unit Erase Unit Header Erase Zone exclusive access FFS field · · File File System Flash In the context of a tuple.Ó A PC Card Custom Interface which provides a bi-directional video and audio bus and a command control interface providing a DVB compliant Conditional Access system. A related unit of information stored on media. An Erase Unit may be one (1) or more Erase Zones. A person who uses a host system. A 32-bit block of data. Commonly used in ISA Bus machines. See the Media Storgage Formats Specification. The host must see the edge to latch this type of interrupt. erase operations are required to be performed on a block of contiguous bytes. a modem or LAN function. the term refers to MS-DOS. It may be internal or external to a Modem I/O Card. if present in the Card Information Structure. An acronym for Digital Video Broadcasting. Acronym for Flash File System. functions are numbered 1 to n. interrupts (IRQn) or negative-true. From the Card Services' client point of view. a field is the smallest readable unit which has a distinct meaning. In addition. The Dual Drive option defines a single PC Card ATA mass storage card that contains two separate and distinct logical ATA devices. Compatible with ISA 8-bit and 16-bit adapter cards. third party Directory DMA DOS Double Word Dual Drive DUT DVB DWORD Edge Sensitive Interrupt EISA Direct Access Attachment. level sensitive. A system file used to maintain the structure of a file system. et al.

Refers to an IBM-compatible expansion bus of the type incorporated in IBM-AT compatible personal computers. It may or may not have other capabilities such as: · · providing an alternate interface to Card Services providing the user information about the installed cards This type of enabler is not custom designed for configuring specific cards. The Interrupt Request signal between a PC Card and a socket when the I/O interface is active. REG#. and for the device initialization. no data corruption and no physical. using the CIS and the Card Services interface. or Initialization IREQ# IRQn ISA ISA Bus Ó 1999 PCMCIA/JEIDA 29 . This interface is not active at power up or following a PC Card reset. An internal host Bus which is available in some hosts and can be used to connect PC Card sockets to the host CPU. The host configures a PC Card for the I/O interface using the Configuration Option register. Acronym for Industry Standard Architecture Bus. Depending upon the host system implementation the IRQn signal may be either IRQn or IRQn#. The register or storage location might also be accessible using memory cycles. the device must allow access to its Configuration Space. A signal is in the high logic state when it is above VIH level. Disk storage devices with IDE are often referred to as ATA drives. An abbreviation for Input / Output. The first 64 bytes of the CardBus PC Card Configuration Space. In this state. PC Card Standard compliant card used for I/O (input/output) operations and connected internally to medium via a Medium Access Device. Selection of the specific Interrupt Request Signal which is used to carry an Interrupt Request from a PC Card to the Host's CPU is controlled by hardware associated with the socket. Arbitration that occurs during a previous access so that no CardBus PC Card bus cycles are consumed by arbitration. IORD#. Acronym for Industry Standard Architecture. or functional damage is caused to the system or card. One of the Interrupt Request Signals between a socket and the host's CPU. or mechanical keying. Uses 16-bit addressing. but. The state that a device must enter immediately following the Reset state. This interface is permitted to be enabled when both the PC Card socket and PC Card installed in the socket support the I/O interface. A 16-bit PC Card physical window (either memory or I/O). A Card Services assigned identifier associated with Card Services managed system resources. in which case it would also be memory mapped. either through a message (visual or audio). electrical. In addition. CE1# or CE2# are asserted. and at least one Card Enable. while the Attribute Memory Select Signal. It must draw a minimum current/power necessary for accessing its Configuration Space. (See Guidelines) An I/O cycle is an Input operation(I/O Read) or Output operation (I/O Write) which accesses the PC Card's I/O address space. The I/O address space is one of the three address spaces available on a PC Card. Acronym for the Institute for Electrical and Electronic Engineers A high speed serial bus that supports both arbitrated asynchronous communications and high-priority isochronous transmissions necessary for real-time full motion video and other high-speed data transfer. Any clock period that the bus is idle (CFRAME# and CIRDY# are deasserted). The Header Space consists of fields which allow a CardBus PC Card function to be generically controlled. The I/O Interface is an interface supporting both memory cycles and I/O cycles. A storage location or register is I/O mapped when it is available to be accessed using I/O cycles.OVERVIEW AND GLOSSARY generic enabler A Card Services client which is capable of configuring a variety of cards. This is an area in a host systemÕs memory or I/O address space through which a 16-bit PC Card may be addressed. except when the bus is idle. or the I/O Write signal. PC Cards which support the I/O interface must indicate their support in the CIS on the card. Same as host The ability to insert or remove a PC Card without cycling the system power or re-booting the system. it can configure many different kinds of cards. The I/O address space is accessed by asserting the I/O Read signal. See also Device Dependent Space. Acronym for Integrated Drive Electronics. IOWR#. See the PC Card Standard Electrical Specification for the precise electrical definition. While serving the same basic purpose as Handle Hardware Reset Hardware Window Header Space Hidden Arbitration High (Logic Level) Host Host System hot swapping I/O I/O Address Space I/O Card I/O Cycle I/O Interface I/O Mapped IDE idle state IEEE IEEE 1394 Init. A computer system or other equipment which contains hardware (a Socket) and software for utilizing a PC Card. graceful rejection It is made clear to the user that the PC Card is not usable in that socket. See PC Card Hardware Reset.

Associating a given card address space with a host system address space. commonly used to refer to an Expanded Memory Specification. A class of devices built before the PCI Bus Power Management Interface Specification for PCI-toCardBus Bridges was added to the PC Card Standard and are PC Card Standard. A device that provides access to a communications medium. Material used to store data. May be silicon. February 1995 compliant. CISTPL_LONGLINK_CB. write. in this instance through a Data Access Arrangement (Modem or Modem-FAX). Acronym for Least Significant Bit and Least Significant Byte. for page swapping and memory management on DOS-based computers (LIMÊ4. The memory interface is the default interface after power up. copy. A logical block address is a sequential address for accessing the blocks on the storage media. An MBR is a specially formatted first physical sector on block storage media. A logical number assigned to an Erase Unit by the FTL. (See Guidelines) Acronym for Master Boot Record. A memory cycle is a memory read operation (using Output Enable) or memory write operation (using Write Enable) which accesses the PC Card's common memory or attribute memory address space. magnetic oxide or any other material that can retain information for later retrieval. and erase memory functions. See Bus Master A termination mechanism that allows a master to terminate a transaction when no target responds.0). A LONGLINK is a pointer from one tuple chain to another. It may be part of a single memory region or span two or more memory regions. See access latency. Acronym for Lotus/Intel/Microsoft. Acronym for Japan Electronic Industry Development Association. interrupt request lines (IRQn). See the Electrical Specification for the precise electrical definition. A mechanism for ensuring that a bus master does not extend the access latency of other masters beyond a specified value. An address based on accessing the media in Logical Erase Unit order. Another name for pull-up resistors that are only used to sustain a signal state. See the Media Storgage Formats Specification. (See Guidelines) An area of the card memory addressed by a memory handle. Legacy PCI to CardBus bridge and CardBus card devices are assumed to be in the D0 power management state whenever power is applied to them. A host system interrupt based upon the logic level of the signal which causes repeated interrupts as long as the interrupt request signal is in the asserted state. connected to DAA. A condition in which two or more operations require completion of another operation before they can complete. and the interrupt request is not disabled. some bus protocols and signals are different. Contrast with I/O interface. Acronym for Logical Block Address. Used to access memory on a card with the Card Services read. A Card Services-assigned identifier for a card memory area. CISTPL_LONGLINK_C. JEDEC JEIDA keepers latency latency timer LBA legacy PCI devices Acronym for Joint Electronic Device Engineering Council. A storage location or register is memory mapped when it is available to be accessed using memory Level Sensitive Interrupt LIM livelock Logical Address Logical Block Address Logical Erase Unit Number (LogicalEUN) LONGLINK Low (Logic Level) LSB Mandatory mapping master master-abort Maximum Interface MBR Media Medium Access Device memory area Memory Cycle memory handle Memory Interface Memory Mapped 30 Ó1999PCMCIA/JEIDA . See the Media Storgage Formats Specification. PC Card Hardware Reset and PC Card Soft Reset for both PC Card cards and sockets. An ISA bus uses positive-true. This interface supports memory operations only. That portion of a number. A 7 position connector interface on the I/O Modem PC Card.GLOSSARY a Micro Channel bus or an EISA bus. Used in Micro Channel Architecture bus hosts and available in EISA bus hosts. edge sensitive. The FTL assigns logical numbers to Erase Units to remap the ordering of the physical media and simplify recovering superseded areas. address or field which occurs rightmost when its value is written as a single number in conventional hexadecimal or binary notation. See Metaformat Specification A signal is in the low logic level when it is below or equal to the VIH level. The first block of the media is addressed as block 0 and succeeding blocks are numbered sequentially until the last block is encountered. The portion of the number having the least weight in a mathematical calculation using the value. Such a link is described by one of the LONGLINK tuples: CISTPL_LONGLINK_A. A characteristic or feature which must be present in every implementation of the standard.

but is specifically permitted. Features 32-bit addressing and bus-mastering capabilities.g. memory region Metaformat Micro Channel Minimum Interface motherboard MSB MTD Negated NMI Offset Open System Cards Operating System optional Ó 1999 PCMCIA/JEIDA 31 . See the Conventions section. (See Guidelines) A circuit board containing the basic functions (e. A characteristic or feature which is not mandatory. That portion of a number. Without memory paging. Acronym for Non-Maskable Interrupt (usually caused by a catastrophic error). user mode services. It is also used when identifying the location of memory mapped registers with respect to the base address of the memory window. The portion of the number having the most weight in a mathematical calculation using the value. memory. and/or kernel mode services. If an optional characteristic or feature is present. Acronym for Most Significant Bit and Most Significant Byte. Not compatible with ISA or EISA. Refers to an IBM expansion bus of the type incorporated in some of the personal computers in the PS/2 line. I/O. Embedded or installable component of Card Services that contains device-specific read. A signal is negated when it is in the state opposed to that which is indicated by the name of the signal. copy and erase algorithms. write. Optional characteristics or features are specifically identified. and expansion connectors) of a host system. Cards which contain selected I/O connectors and electrical-performance components. such that cables using connector plugs described herein can be used interchangeably with similar function cards regardless of supplier. device drivers. including power management services. A 4 position connector interface on the I/O Modem PC Card. it must be implemented as described in this the PC Card Standard. Low level format standard of a PC Card. Acronym for Memory Technology Driver. A Micro Channel Bus uses negative-true. (See Guidelines) Software on a host system that manages resources and provides services. The register or storage location might also be accessible using I/O cycles. Micro Channel Architecture. memory paging A method of extending PC Card memory space to contain as many as 242 Common Memory locations. connected to DAA..OVERVIEW AND GLOSSARY cycles. in which case it would also be I/O mapped. level sensitive. A homogeneous card memory area using one type of memory device. This term is used when identifying the locations of registers located with respect to the base address of a block of contiguous I/O ports. address or field which occurs leftmost when its value is written as a single number in conventional hexadecimal or binary notation. CPU. interrupt request lines (IRQn#). the 26 address signals at the PC Card connector allow 64Mbytes of Common Memory. Opposite of Asserted. The offset of a port or a memory location is the difference between the address of the specific port or memory address and the address of the first port or memory address within a contiguous group of ports or a memory window.

This single PCI Device may contain up to 8 PCI Functions. typically formatted for use with a single type of file system. The PC Card Standard. During PC Card Hardware Reset. what is being addressed are those characteristics common to both 16-bit PC Cards and CardBus PC Cards. the originating device is the PCI to CardBus bridge controlling its bus (see figure below). and the Configuration Option register is set to 00H. all pages are 16 KBytes in size. Other configuration registers and the READY signal are also affected as detailed in the PC Card Standard. Because the other bits of the Configuration Option are written at the same time as the PC Card Soft Reset bit. When cards are referred to as PC Cards. and a secondary bus interface and are always a PCI bus and a CardBus card bus. the PC Card interface is set to be the Memory Only Interface. Often used to refer to an 80x86 based computer system. For a CardBus card. The effect of PC Card Soft Reset is identical to the effect of PC Card Hardware Reset except that bit 7 of the Configuration Option register is not cleared by the reset condition. it is recommended that the PC Card Soft Reset bit be cleared by writing a 00H to the Configuration Option register. Acronym for the Peripheral Component Interface bus PCI to CardBus bridges couple two independent buses together. A subdivision of a 16-bit PC Card window. They are characterized by a primary bus interface. PC Card Hardware Reset PC Card Soft Reset PC Card Standard PCI PCI to CardBus bridge PCI device 32 Ó1999PCMCIA/JEIDA . If there is more than one page in a window. See memory paging A subdivision of a storage device. A memory or I/O card compatible with the PC Card Standard. Acronym for Personal Computer. PC Card Soft Reset is asserted while bit 7 of Configuration Option register is set. PC Card Hardware Reset is caused when the socket asserts the RESET signal to the PC Card. PC Card Soft Reset is caused when the host sets bit 7 of a PC Card's Configuration Option register. the first bridge component encountered with a PCI bus downstream of it is defined as the Originating Device for that PCI bus segment. CPU Host Bus I/F Host Bridge PCI Bus I/F Originating Device for bus(0) PCI Bus(0) Primary Bus I/F PCI to CardBus Bridge Secondary Bus I/F Originating Device for CardBus bus CardBus bus output driver page Paging partition PC PC Card An electrical drive element (transistor) for a single signal on a CardBus PC Card device.GLOSSARY originating device From the perspective of the operating system (Host CPU). The applicable revision is given in the Related Documents section. A physical device consisting of one load on the PCI bus and having only one IDSEL input.

The number assigned to an Erase Unit based on its location on the physical media. As applicable to PC Card ATA mass storage cards. the IREQ# signal is asserted momentarily when the Card initiates an interrupt and is then negated regardless of whether or not the interrupt is acknowledged. Power management involves tradeoffs among system speed. report PME status. The FTL maintains the allocation state of each Read/Write Block. READY signal and Pin Replacement Register plug-n-play PME Context positive decoding POST power management Power Management Event (PME) primary (ordinate) bus/side Primary I/O Addresses Pull-ups Pulse Mode Interrupt Read/Write Block READY Ó 1999 PCMCIA/JEIDA 33 . See the Media Storgage Formats Specification. usually volatile. The negated state of the READY signal is used by a PC Card to indicate that it is busy with an internal operation and access to the card may be restricted. A subdivision of an Erase Unit. and AC power consumption. or remove a PC Card without cycling the system power. Acronym for Power-On Self Test. An ability to insert and put into operation. In this mode. A power management event is the process by which a PCI or CardBus function can request a change of its power consumption state. a device could use a PME to request a change to a lower power state. The method of acknowledgment is specific to devices on the PC Card. execution stack (in some cases). Used by the FTL to track media allocation. One or more clocks in which a single unit of information is transferred. A method of transmitting an Interrupt Request from a PC Card to a socket using the IREQ# signal. If the partition begins at physical address zero (0). noise. It is used to retrieve status information from the PC Card about Battery. Use of these addresses allows emulation of the first ATA or IDE disk controller at its standard addresses. rebooting the system. The Pin Replacement register is the third Card Configuration register.OVERVIEW AND GLOSSARY PCI or CardBus function PCI Function Context A set of functionality inside a PCI or CardBus Device represented by one 256 byte configuration space. The variable data held by the PCI function. Busy and Write Protect while the card has the I/O interface active. A method of address decoding in which a device responds to accesses only within an assigned address range. The primary bus of a PCI to CardBus bridge or CardBus PC Card refers to the bus that is topologically closest to the CPU that is running the operating system. the internal status and mask registers and the VCC control signals would be a special case of Function Context which must be preserved. it is the set of addresses 1F0H-1F7H and 3F6H-3F7H at which the first fixed disk controller is located in a PC/AT computer system. this signal Indicates that the PC Card is completely available for use. the First Physical Erase Unit is number zero (0). or requiring a manual user intervention for configuration. Power Management Event Context is defined as the functional state information and logic required to generate Power Management Events (PMEs). Acronym for the Personal Computer Memory Card International Association. and enable PMEs. The host socket must use an "open-collector" non-inverting output to drive the ISA bus IRQn signal when it is expecting to share pulse mode interrupts from the PC Card. It is used to specify the rules of changing the master/slave relationships between such agents. consisting of: PCMCIA peer-to-peer phase · · Physical Address Physical Erase Unit Number (PhysicalEUN) an address phase (a single address transfer) a data phase (one transfer state plus zero or more wait states) An address based on accessing the media in Physical Erase Unit order. This number never changes and is implied by the Erase Unit's position on the media. The pulse mode interrupt is designed to be used with the ISA bus (and the EISA bus when ISA bus interrupt emulation is being performed). but rather refers also to the operational states of the function including state machine context. This term is used to describe data transfers between two agents which are both capable of gaining the bus mastership. Function context refers to small amounts of information held internal to the function. See the Media Storgage Formats Specification. For a PCI to CardBus Bridge. In the case of a PC Card ATA mass storage card. manage system thermal limits and maximize system battery life. Refer to the Electrical Specification. See also subtractive decoding. power state. A series of diagnostic routines performed when a system is powered up. See the Media Storgage Formats Specification. The power management policies of the system ultimately dictate what action is taken as a result of a power management event. acknowledgment takes place when the ATA Status register is read. When asserted. However. Each PCI and CardBus function within a device generally has a separate software driver. battery life. A power management event is requested via the assertion of the PME# signal for a PCI-to-CardBus Bridge. etc. Resistors used to insure that signals maintain stable values when no agent is actively driving the bus. Typically a device uses a PME to request a change from a power savings state to the fully operational (and fully powered) state. Function Context is not limited only to the contents of the functionÕs PCI registers. The Erase Unit at the beginning of an FTL partition is known as the First Physical Erase Unit. Mechanisms in software and hardware to minimize system power consumption. assertion of CSTSCHG for a CardBus card and STSCHG# for a PC Card.

One use of this Configuration register allows the host to configure a PC Card ATA mass storage card to respond as either Drive 0 or Drive 1. The system must be restarted to return to the Working state. etc. The Registered READY Status Bit. Acronym for Static Random Access Memory. A method of address decoding in which a device accepts all accesses not positively decoded by other agents. The smallest unit of information that may be stored on a block device. It is not safe to disassemble the machine. Set is equivalent to on or one(1). No user mode or system mode code is run. This signal replaces the BVD1 signal of the Memory-Only interface when the I/O Interface is configured. but may be other powers of two in size (128. A message broadcast mechanism for communicating processor status and/or (optionally) logical sideband signaling between CardBus PC Card agents. Any signal that is not part of the CardBus PC Card that connects two or more CardBus PC Card compliant agents. The secondary bus of a PCI to CardBus bridge or CardBus PC Card refers to the bus that is topologically farthest from the CPU that is running the operating system. The socket is the hardware. It is not safe to disassemble the machine in this state.00 mm by 42. Region Replacement Page See memory region. The systemÕs context will not be preserved by the hardware. See also positive decoding. Restore time is defined as the time required to fully restore a PCI or CardBus function to its fully operational state from a power saving mode of operation. in the host which is responsible for accepting a PC Card into the host and mapping the host's internal bus signals to the PC Card interface signals. Refers to the state of a bit within a register or variable. 256. The ATA Soft Reset Bit. A function which controls access to the system bus. user mode threads are not being executed.80 mm in various heights. This bit provides the ATA Soft Reset Function but does not cause the PC Card interface to perform PC Card Reset processing. and the system ÒappearsÓ to be off (from an end userÕs perspective. It is asserted when any of the four Changed Status bits in the Pin Replacement register are set while the Enable Status Changed bit is set in the Card Configuration and Status register. See the Media Storgage Formats Specification. 2048. The bit is provided to indicate the state of the READY function while the READY signal is unavailable because the Memory-Only Interface is not currently configured on the card. is located in the Device Control register of a PC Card ATA mass storage card. 68 pin socket.). It is measured as the total elapsed time between when the system software request for restoration occurs to when the function is fully configured and activated. The Socket and Copy register is the fourth Card Configuration register located on a PC Card.). should the system answer phone calls. 1024. Reset is equivalent to off or zero(0). Refers to the state of a bit within a register or variable. The Status Changed Signal is present at the PC Card interface only when the I/O Interface is enabled. is located in the Pin Replacement register if that register is present on the PC Card. It is the deviceÕs default state after Power-up or reset. the logical address is retrieved from the corresponding entry on the Replacement Page. Latency for returning to the Working state varies on the wakeup environment selected prior to entry of this state (for example. Any memory accessible by more than one agent. and has meaning only to those agents. Use of these addresses allows emulation of the second ATA or IDE disk controller at its standard addresses. A directive to terminate the current transaction and retry it at a later time. etc. As applicable to a PC Card ATA mass storage card. it is the set of addresses 170H-177H and 376H-377H at which the second fixed disk controller is located in a PC/AT computer system. Work can be resumed without rebooting the OS because large elements of system context are saved by the hardware and the rest by system software. Typically 512 bytes. A computer state where the computer consumes a minimal amount of power. Values in a Replacement Page override values in the original page of the Virtual Map as follows: If an entry in an original page is zero (0). The Small PC Card form factor does not support the CardBus interface. The ability of an agent to spread assertion of qualified signals over several clocks.). Replacement pages delay the need to reallocate a Page in the Virtual Map when an entry in the page is updated. This state requires a large latency in order to return to the Working state. the display is off. RREADY. A computer state where the computer consumes a small amount of power. also referred to as backoff. A PC Card form factor measuring 45. Reset restore time Retry RREADY secondary (subordinate) bus/side Secondary I/O Addresses Sector Set Shared memory Sideband signal sleeping state Small PC Card Socket Socket and Copy Register soft off state Special Cycle SRAM SRST (Soft Reset Bit) Status Changed Signal (STSCHG#) stepping subtractive decoding system bus arbiter 34 Ó1999PCMCIA/JEIDA .GLOSSARY RREADY bit for detailed information about this signal. SRST. etc.

An agent that responds (with a positive acknowledgment by asserting CDEVSEL#) to a bus transaction initiated by a master. Space is always reserved on the media to store the entire VBM.the amount of time that the target takes to assert CTRDY# for the first data transfer. See the Media Storgage Formats Specification.5 Mbps. Tuples located in the CIS of a PC Card are examined by host software to determine the capabilities of the card. a tuple length which specifies the amount of space occupied by the tuple. A transaction termination brings the bus transaction to an orderly and systematic conclusion. A termination mechanism that allows a target to terminate a transaction in which a catastrophic error has occurred.Ó A CardBus PC Card cycle used to prevent contention when one agent stops driving a signal and another agent begins. Any CardBus PC Card clock. This action is best performed by Card Services for a client. in which data is transferred. A linked set of tuples which is parsed completely before any LONGLINK is followed to another tuple chain. and an information area which contains the content of the tuple. A tuple is an element of a Card Information Structure. The FirstVMAddress field describes how much of the VBM is maintained on the media by the FTL. An Erase Unit reserved for storing Read/Write Blocks from an Erase Unit being emptied by the FTL prior to erasure. An array of 32-bit entries used to map Pages of the Virtual Block Map to a logical address on the media. or to which the target will never be able to respond. In obsolete versions of the ATA Specification. The FTL uses Virtual Block sizes that are a logical power of two of 128 bytes or larger. This is also referred to as "tuple walking" or "walking the CIS. See the Media Storgage Formats Specification. Includes Socket Services. The Virtual Block size is set when the FTL partition is formatted. The cards are uniquely labeled by the host using the Copy Number field of the Socket and Copy register. All transactions are concluded when CFRAME# and CIRDY# are deasserted (an idle cycle). An optional field in a Configuration Entry tuple which permits configurations to be described in which several cards share the same system resources such as I/O ports. A turnaround cycle must last one clock and is required on all signals that may be driven by more than one agent. Locating and reading in sequence all of the tuples on the card. Support for the Twin Cards Option is optional in PC Card ATA mass storage cards. For PC Card ATA.OVERVIEW AND GLOSSARY system master system software target target abort target latency Task File Registers termination An agent or a group of agents which controls system configuration and resource management. This is the same as host from the CardBus PC Card point of view. during a data phase. The unit of information used by the file system layer above the FTL to read and write data to the media. Group of sectors all accessed by a single head on one cylinder of a rotating media storage device. typically a higher-level software layer such as a client. The VPM is never stored on the media. ATA Command Block registers were referred to as the Task File. Thermal Rating Track transaction transfer state Transfer Unit Tuple tuple chain tuple parsing tuple traversal turnaround cycle Twin Cards Universal Serial Bus USB User Virtual Address Virtual Block Virtual Block Map (VBM) Virtual Page Map (VPM) wait state Wakeup Event Ó 1999 PCMCIA/JEIDA 35 . A number representing the heat generated by PC Cards (see the Physical Specification) or the ability of PC Card hosts to remove heat (see the PC Card Host System Specification). An address phase plus one or more data phases. in which no transfer occurs. A CardBus PC Card clock. The action performed by a client whereby a CIS is interpreted into configuration requests and other useful information. An event which can be enabled to wake the system from a Sleeping or Soft Off state to a Working state to allow some task to be performed. The third component of access latency . There is at most one LONGLINK per tuple chain. See Command Block registers. Each tuple has a tuple code which identifies the type of tuple which is present. Card Services and generic enablers. See Universal Serial Bus Within this document. this feature is used to permit a Drive 0 and a Drive 1 to coexist at the same Primary or Secondary I/O addresses. The address recorded in a Read/Write Block's allocation information representing where the stored data appears in the virtual image presented to the host system. Transfer Units are not included in the formatted size of the FTL partition presented to the host file system. A serial bus standard which allows operation at 12 Mbps with a low speed un-shielded sub-channel operating at 1. and offers both asynchronous and isochronous data transfer. the term ÒuserÓ refers to the user of Card Services. An array of 32-bit entries used to map a Virtual Block number to a logical address on the media. and not the end-user of the host computer. during a data phase. Termination may be initiated by the master or the target.

Any of a number of CPU chips compatible with the Intel iAPX8086.GLOSSARY Window working state An area in a host computer's memory or I/O port space through which a PC Card may be addressed. Acronym for eXecute-In-Place. The user will be able to select (through some user interface) various performance/power characteristics of the system to have the software optimize for performance or battery life. the Intel iAPX80386. A PC Card Custom Interface which provides a single-source uni-directional video bus between a PC Card socket and a VGA controller. Refers to specification for directly executing code from a PC Card. It is not safe to disassemble the machine in this state. A computer state where the system dispatches user mode (application) threads and they execute. devices (peripherals) are dynamically having their power state changed. The system responds to external events in real time. or the Intel Pentium. In this state. the Intel iAPX80286. See Zoomed Video Port X86 XIP Zoomed Video Port ZV Port 36 Ó1999PCMCIA/JEIDA . the Intel iAPX80486.

P C C A R D S TA N D A R D Volume 2 Electrical Specification .

Shibakoen Minato-ku. Printed in the United States of America. recording or otherwise. registered in the United States. registered in Japan. the owner of this Standard must sign and return the enclosed Registration Card to: PCMCIA 2635 North First Street. 0299-02-2000 First Printing. Tokyo 105. PCMCIA HAS OBTAINED FROM SOME. Suite 209 San Jose. THIS STANDARD IS PROVIDED TO YOU ÒAS IS. stored in a retrieval system. without prior written permission of PCMCIA and JEIDA. EXPRESS OR IMPLIED. MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PCMCIA HAS BEEN NOTIFIED BY CERTAIN THIRD PARTIES THAT THE IMPLEMENTATION OF THE STANDARD WILL REQUIRE A LICENSE FROM THOSE THIRD PARTIES TO AVOID INFRINGEMENT OF THEIR RIGHTS. photocopying. or transmitted. OF THOSE PARTIES A GRANT OF IMMUNITY THAT PCMCIA WILL EXTEND TO YOU. PCMCIA/JEIDA All rights reserved. electronic. INCLUDING AS TO NONINFRINGEMENT. CA 95134 USA NEITHER PCMCIA NOR JEIDA MAKES ANY WARRANTY. 3-5-8. CONTINGENT UPON YOUR ENTERING INTO AND DELIVERING TO PCMCIA THE RECIPROCAL GRANT OF IMMUNITY AGREEMENT CONTAINED ELSEWHERE IN THIS STANDARD. WITH RESPECT TO THE STANDARD. The PC Card logo and PC Card are trademarks of JEIDA. BUT NOT ALL. February 1999 . No part of this publication may be reproduced. JAPAN +81-3-3433-1923 +81-3-3433-6350 (Fax) The PC Card logo and PC Card are trademarks of PCMCIA. PCMCIA (Personal Computer Memory Card International Association) 2635 North First Street. Suite 209 San Jose. IMPORTANT: In order to receive the Grant of Immunity. mechanical.PCMCIA JEIDA ©1999. in any form or by any means.Ó Document No. CA 95134 USA +1-408-433-2273 +1-408-433-9558 (Fax) JEIDA (Japan Electronic Industry Development Association) Kikai Shinko Kaikan.

............5 2.........1..................................................6 2..................................................................................1........................................2........................................................................2 1...1 Card Detect Pins (CD[2::1]# and CCD[2::1]#)...........................1 Compatibility Issues ....................2 VS1# replaces RFSH (pin 43)..................................................................................4 2...............2) ............8 3.......6 3...............................................4 1.............6 2..............................................1 Release (April 1998).........7 3..................................02)......................................6 PC Card Standard November 1995 Update (Release 5.................................................................................................................................................................................................1...........1 Signal Naming... 16-bit PC Card Electrical Interface _______________________11 4..........................................3 1.....................14 © 1999 PCMCIA/JEIDA iii ...........................................................................................................................2 PCMCIA 2.................................2 VPP1 and VPP2 Pins..............................9 4.............................3 1..4 PC Card Standard March 1995 Update (Release 5............................11 4.............................................1 1 4.................................1 PC Card Encodings ...................................................................................................................................1 Power and Ground Pins ........2 1...........2 1................3 1...............................................1 PCMCIA 2.........1)...................................................................8 3...................................... Card Type Detection Mechanism _________________________7 3..........................1 RESET and WAIT# Support..............................................................................................................1 1 4............2.................3 Graceful Rejection in 16Ðbit PC Card Only Sockets...................4 Signal Summary ............................................1..........................................................9 PC Card Standard 6..............................ELECTRICAL SPECIFICATION CONTENTS 1..................2 Pin Assignments................0 Release (February 1999)...........4 1...3 1.............................3 PC Card Standard February 1995 Release (Release 5..............................................5 PC Card Standard May 1995 Update (Release 5.................5 2...............2...................3 1....1................................1.2...1 (September 1991)..................................................................................................1................7 PC Card Standard May 1996 Update (Release 5...............................0 Release (March 1997) ............1 Summary of Electrical Specification Changes........................................................................................2 Conventions ..........3 1.............................................................................................................................................................4 Determining Card Type in CardBus PC Card Capable Sockets........11 4...................... Common Pin Description ________________________________5 2.............................1..............1...............................................................................................................................................2 (July 1993).......................1....................1..............10 PC Card Standard 7..................3 16-bit PC Card Features...................................2 Interface Configuration Pins .............................................................................1 VCC and GND Pins.................................1...........................2 Numeric Representation................................2.2 Socket Key Selection ..4 1..........2 1.......3 Bit Action Representation...............................1.................................8 PC Card Standard 6..........................................3 1................. Overview ______________________________________________1 1....................................................5 2..........................01).....................................................................1/JEIDA 4...1..............2 Voltage Sense Pins (VS[2::1]# and CVS[2::1]) .....................................................................................................................................................................................................2......0/JEIDA 4..................3 1............................................................................................................0) .........................

...............................................1 Interrupt Request Routing.................................................................................................................1 Common Memory Function........................4...2 4 4..............................................................................................................................................................................................................1 8 4...............................................................................1 6 4.........................1 7 4....................................................1 8 4................................................................4................................................................................................................................................................2 Data BUS (D[15::0]) ................................................2 1 4.................2 1 4.........5 Terminal Count (TC#).................18 I/O Read (IORD#) [I/O and Memory Interface] ....................................................................3...................................5...................................................................7.2 4 4........1 6 4........................7..................3......................................19 I/O Write (IOWR#) [I/O and Memory Interface] ............................26 4................2 7 4....4...5 Write Enable (WE#).........................................................................................2 0 4........................................................2 3 4....................CONTENTS 4..............................................15 Program and Peripheral Voltages (VPP[2::1]) ....11 Attribute Memory Select (REG#).......................3..................................................................................................................................................4........................................4...........................................................................4................4..............................................................................................................................................2 0 4...............4 Signal Description................................................4.........................................................................................4...........................................................................................................6 Ready (READY) ...................2 5 4....................................................................................1 Socket VCC for CIS Read.....4..............4.........................................7....................................2....................................16...................................................................6..........................1 Memory Address Space...............4..........................................................5.......................................................................................................4.................................................................................................................................................................................................................3 I/O Address Space.......4 Output Enable (OE#) ....................................4 DMA Write (IORD#) ...........................................................3......16...............6 Configurable Cards ................................................10 I/O Is 16 Bit Port (IOIS16#) [I/O and Memory Interface]...............................2 3 4.......1 7 4...........................4.......................................................2 7 iv ©1999 PCMCIA/JEIDA ................................5 Custom Interfaces ...................................................................................................................................2 4 4...........2 6 4.......2 DMA Acknowledge (DACK) [replaces REG#].2 7 4............4.1 7 4...............22 Input Port Acknowledge (INPACK#) [I/O and Memory Interface] ..................1 8 4...........4...................................2 PC Card VCC for CIS Read................................................................................................................................................................................16 Voltage and Ground (VCC & GND) ...........4....8 Card Detect (CD[2::1]#) .......4..16...........................................................................14 Audio Digital Waveform (SPKR#) [I/O and Memory Interface]..........................................................................2 2 4........................2 6 4...1 DMA Request (DREQ#)..........................2 7 4......4....13 Status Changed (STSCHG#) [I/O and Memory Interface] .3 DMA Read (IOWR#) .......2 6 4....................1 5 4.......................................................1 5 4.2 Pulsed Mode Interrupt Signal.........................................................................................................................................................................................................................................................9 Write Protect (WP) [Memory Only Interface]..................4.......................................................2 1 4....................2 2 4......12 Battery Voltage Detect (BVD[2::1]) [Memory Only Interface]..................................................4...................................................4..............4............................................................................................................20 Card Reset (RESET) ...........................................7 Interrupt Request (IREQ#) [I/O and Memory Interface]...................................4 I/O Interface ...........................1 9 4...............2....4.......................................................3........................................................................................2 7 4.....................................................17 4..................................5...5.................................................4...............................2 Level and Pulsed Mode Interrupt Support...1 9 4..........................................2 1 4...................................................................................................................................2 5 4..............................................2 3 4......................................5 DMA Signals Replacing I/O Interface Signals..............................................4.........................................................17 Voltage Sense (VS[2::1]#) .................5...........................................................................27 4.....................1 4 4...........................................1 7 4...................................2 0 4......................................3......................................................................1 Address BUS (A[25::0])..................................4.................................4...............................6 Memory Function...3 Changing PC Card VCC........2 Memory Only Interface ..............2 2 4.........................................2 6 4...........21 Extend Bus Cycle (WAIT#).......4...3 Card Enable (CE[2::1]#)...................................7......................1 Level Mode Interrupt Signal ............................

.................3 7 4...............................................................................................................................................Memory Write)..............3 Attribute Memory Read Timing Specification....................................................2..................13................3 4 4...............................................................................Memory Write) ...........................................................................................................................................2 9 4.............4 DMA Write Timing (I/O Read ...............................................................3 I/O Address Space Decoding ............................3 6 4..................8 DMA Function.........................1...................9.....1 DMA Read Function (Memory Read ......................ELECTRICAL SPECIFICATION 4...................................6................12.........................2 DMA Read Timing (Memory Read ....................................................8....4 6 4.....................................2 8 4....................................1.....3 6 4.............5 1 © 1999 PCMCIA/JEIDA v ................................4 Attribute Memory Write Timing Specification.............2 9 4............................................................................12....................6.................4 4 4..............2 8 4................................... EPROM and Flash Memory.................3 DMA Write Function (I/O Read ......................7.................................................................................................3..............................................................4 5 4.........................7...................................4 6 4..............................2 I/O Input Function for I/O Cards .................7........................13....................................................I/O Write) ........................................12.............................9 Electrical Interface ...........................................3 8 4.......................51 4.............................. EPROM and Flash Memory............................39 4..1 Signal Interface............2 Memory Address Decoding..................................................10 Card Detect...........................................................12 Power-up and Power-down........................................5 1 4............1 Attribute Memory Read Function ......................................................................4 0 4.........3 Common Memory Write Function for OTPROM..2 Single Function PC Cards..........................4 6 4..............................................................................9.....................4 1 4..........43 4............................................................7...........................................................1 Function Configuration Registers Address Decoding.............5 Memory Timing Diagrams ...........................2...........................................................................................................................................................4 2 4....................2....................................9..............................8....................3 3 4..............................4 1 4...........1 I/O Transfer Function ....................................................................................................................................44 4.........................................................................13...........2 Attribute Memory Function...3 I/O Output Function for I/O Cards...................................................................................................................................................................I/O Write)..3 9 4.......................................................................3 3 4......2 7 4..13.............1 Common Memory Read Timing......3 Data Retention...........................7 Timing Functions..3 2 4.................4 6 4...14 Function Configuration ....2 Overlapping I/O Address Window......................4 8 4...............2 Common and Attribute Memory Write Timing..............................................................................................9........................................................................................................7.......................................................................................6..6............1 Power-up/Power-down Timing .......7..........................................11 Battery Voltage Detect .....................................3 Write Protect Function ...6.........................................................................................................................3 Attribute Memory Write Function for Dual Supply OTPROM..............................................3 0 4......1 Common Memory Write Timing.........2 Average Current During Card Configuration.............................................................................................................................2 Attribute Memory Write Function ..................................................................6............................................14..................5 0 4......................2 9 4..................2 8 4..............6..5 I/O Write (Output) Timing Specification......................2 Common Memory Write Function for PC Cards ................................................................2......30 4.........13 I/O Function..8..................3 3 4..............................................................................................................................................................................6.8...................................................43 4........................................4 1 4....................................................................................................................................................4 I/O Read (Input) Timing Specification .....................................................2.........................................1 Common Memory Read Function for PC Cards ....................................................................35 4...........................................14.....................................................................................................3.................................................................................1 Independent I/O Address Window .........................................................4 7 4.................................................46 4.................................4 Supplement .............13.....9..........................1......12.................1 Overview..........9...........3 0 4....................................

6 0 4..................... 3) .................................7 4 5...............................................................................................1.......................2.....................................................................1.......................................................................1.................................2 Command Usage Rules...................................7 4 5.....9 3 vi ©1999 PCMCIA/JEIDA ....................................5 Arbitration Signaling Protocol ...................................................................................................................................................................................................4 Bus Driving and Turnaround........7 9 5........................6 1 4................................................2..............5 4 4..........6 Interrupt Request Pin .........................................................................1.........................................2 Write Transaction ...................................................1 Basic Transfer Control ...2 Address and Data Pins .........................3 Bus Transactions ...................8 2 5.............................................................................1...3................................1..5 Extended Status Register .......................................1 System Pins ................................15 Card Configuration ...1............2 Addressing ....................5 9 4..............................................................................53 4....8 7 5.....2..........................................................................................3...................................2...2...................................................................................6 0 4.............................2....................................................................7 8 5......................................................................6 2 4.............................................2.................................................................................4 Arbitration...................................3 Interface Control Pins..........................................................................................................................................................................................................3..............................................................2 Signal/Pin Description.............................................................1 CardBus PC Card Signal Description..............................................................................................................................................................................................................3 Byte Alignment..3...............................................................................................................2..7 7 5.............1 Master Initiated Termination....................................14......................................................CONTENTS 4.......................................5 1 4.......1............................................................15......................1..........................................................................................................5 8 4.......................................................................................................................................................1 Bus Commands .................................................................15................7 3 5....................................................................................................7 5 5.......4 Arbitration Pins (Bus Masters Only) ...............................7 I/O Limit Register .......................2............................2..................................................8 4 5........................................2 CardBus PC Card Operation............................................................................3 Transaction Termination ....................................................................................................................................................2........5 6 4...................................................................................2.....................................4 Function Configuration Registers (FCRs).....................2....9 Address Extension Registers................................................................................................................................................6 I/O Base Registers (0 ............5......3.................................................................7 5 5........................8 4 5...............................................................................................................................................2...........................15................................................................................................2......3 Central Resource Functions...............2 CardBus PC Card Protocol Fundamentals...............................8 1 5........................3 Multiple Function PC Cards.........5 Error Reporting Pins.......................................................................................15.....................75 5....................................2............8 5 5................................1 Fast Back-to-Back Transactions...........................7 Additional Signals .......6 8 5..........15.........................................2.................1 Configuration Option Register............... CardBus PC Card Electrical Interface ____________________ 67 5................1...........4 Socket and Copy Register................................................................................................2.......................9 1 5......................................2........................................................7 4 5.........................................................................2.....................................1 Read Transaction ..............................................................................................................................................2.............2 Target Initiated Termination..................................2....15......................................8 2 5.......7 3 5..................................................7 2 5...2 Configuration and Status Register ..........................................................................................8 Power Management Support Register..................................64 5..................3 Pin Replacement Register .............................................67 5...........3............................5 9 4......2..3.....2............16 Indirect Access to PC Card Memory ....7 2 5................9 1 5....................................1 Pin Assignments...................................................15.............7 9 5......2.................8 1 5.......7 2 5..............................15..............................................15...................................................................14.....1 Command Definition ................1...5 2 4.............................2...1.............7 5 5.......................2......2.................

..3...............................2...............................................................2.......123 5.3.......................................1.......................................................................3 Address/Data Stepping....................................................................................129 © 1999 PCMCIA/JEIDA vii ..4 Completing an Exclusive Access...........................................................................................2..........................................................7................2 System and Interface Wake up .............................................................................2...............................................116 5...........................2............................................................................3 Function Present State Register .5 Supporting CBLOCK# and Write-back Cache Coherency...................................................9 6 5..........5 Default Field Values ......2...................................................9 5 5..................3 Latency ......128 5.............................................9 5 5..11.......................................................................................1 Generating Configuration Cycles..2..113 5.1 Clock Frequency........................ELECTRICAL SPECIFICATION 5..............................................5.........10......................................2..125 5..................................................................................2.....................................................2...........................2 Clock Restart or Speed up .................4........................................2 Function Event Mask Register.........................................................9 5 5...........................112 5......................105 5..............................................10...........................................................................................1 Overview ..................................................................................................................2..121 5...121 5..........................................................2 Generating Special Cycles with the Configuration Mechanism ...........................................................8 Error Functions ..............6...........................................................................1 Parity..............2.................5.................................119 5...................................2.....................119 5..................6 Exclusive Access ..........................11....6 Complete Bus Lock........................................112 5....................................................................................2.......................2.................................................1 Function Event Register ............................................................................4 Configuration Cycle...2.................................................................................2.........................................................2.........................................................................................1 Managing Latency on CardBus PC Card..................................................2.............2 Clock Control Protocol..............................2 Special Cycle..117 5........2..................................................9 9 5.......................................................2........13..................................................9 Cache Support ............................................................................8......................................110 5............................2.....................................1 Parity Error Response and Reporting on CPERR#.........102 5..........102 5.............4.2....................................................................................................3 Maintaining the Interface Clock.................10.4 Force Event Capability.......................3 CardBus PC Card Electrical Specification......................................................2.................3...................................11.........4.........11...3.......108 5.2...............................119 5..................2 Low Latency Design Guidelines.....7 Other Bus Operations................................................................................................................................................................129 5.................................................2...1 Configuration Mechanism.............1 Device Selection..........2............................2...............11................6..........................................................................................6....................................................128 5.........11........................................118 5.......................................9 7 5..........................5..............11...............................2.................12 Card Audio ...........13 Special Design Considerations..................2......................116 5..............................7........................................................................1 Clock Stop or Slow down ................................2..8....................2.....................7..................110 5......................1 Card Status Changed.....................126 5...2...................................11 Status Changed Notification.........................................................5...........10 Clock Control..........104 5...............2...........106 5...............................2.........................103 5.............................................................1 Starting an Exclusive Access..........2............................................................110 5........................................2.................................................129 5.......7.......1 Multiple Retry Termination......2.................................................3........2 Continuing an Exclusive Access..............100 5.....................2...............................8.....................................117 5.........................7............7...............................................................................103 5..2.................................2.................................................2.........................................................................................................................................................2...10.........................3.................8.............................................................129 5...................................103 5...............3...6....101 5.................2 Error Response and Reporting on CSERR#...........2..........3 Register Descriptions.....................2 CardBus PC Card Idle Condition....................108 5.........................................................................6...........10........2....................................................................2................3.......3 Accessing a Locked Agent................................................6.....................11......7..................2........................114 5.............116 5......................................................1...............................................2..2 Error Reporting............................

..............1 Routing and Layout of Four Layer Boards ..............3.............................................1 Configuration Space ....146 5.........4.............................2........................3.........................155 5.......2.............................3......................................135 5.......................................................................................................133 5................1...........................1......3...6...........................146 5...................................................3 Vendor Provided Specifications.3.............138 5................................................................................2................................................7 Base Address Register............3.............................3 Pull-up Resistor Requirements..........................................................4..3...2 Timing Parameters ...........................................145 5...CONTENTS 5...........................................4.3.............................................................................................. 159 viii ©1999 PCMCIA/JEIDA ....................................................4...........................................................................132 5......................3....4...........................4 CardBus PC Card Specifications ........3.........................146 5................2....146 5........................2......................137 5.....................2 Status...................1 Clock Specifications.....................................................3 V Signaling Environment.............1..............................................................................147 5....1 Trace Length Limits ...3.................1 3.................................1 Clock Skew...........................................................1 DC Specifications.................................................................................................4........................2.........................................................6 Noise Considerations........2 Physical Requirements......3.........3..............3..................135 5..................................2............................................2................................2..................................................................2...............15 9 5................................................................132 5...3...............5 Maximum AC Ratings and Device Protection (CCLK) .....1...........2 Impedance .........................5 Header Type ...........146 5.........................................................................................2 Motherboard Impedance.............................145 5.3................................4...................................2..................2.......131 5........2..............3 Cache Line size ..146 5...2....................................................................3.....1......146 5.3.......3..................................132 5..............3.............................4........2...............................................4...................................................................................................................................142 5.........................................1 Decoupling ...............147 5........................................3 Pull-ups.................4 Latency Timer.....3......134 5.........1.......................3.............................................................................................136 5......................................................158 5......................................................................4 Power Sequencing...............................4..............................................................................................140 5.................................1 Overview ......3......4....145 5.......................3 System (Motherboard) Specifications ..............................................................................................159 5..........................................................................................................6 Built-in Self Test (BIST)..............2 Card Organization ...141 5...............................3............................................................3.........138 5........1....................3....................3................2 Timing Specification .......................................4 CardBus PC Card Programming Model.......................................158 5............................................................................................3.....................3 Measurement and Test Conditions...........3....3...........................3........................................2......................................3.1 Power Requirements.......................................1 Command.........3 CSTSCHG Buffer Specification....................................2 Component Specifications ........................156 5..................................................................1....3................2...........147 5........................................................1..................138 5..................130 5...............................................3............. Static Drive Specification ..............................................................................................1...................3...............................................2............................................................................................................................2...............130 5...................6.............141 5.................1.....................4..152 5...3.....2..3..3..................................2..........................................................2...........................4....................................................................139 5...........................2 AC Specifications...................3...4.........2 Pull-up Values for Card Detect and Voltage Sense Pins ........................1 Pull-up Values for Control Signals ...................................3.......................................................................................................................................................5 System Timing Budget ..............................................6 Physical Requirements...............................................................................3........................................................145 5....................1.....2......3...............................................................1 Dynamic vs........................3.....................2 Reset.....2.............1......................................................................147 5.2...........4.3.....3 Signal Loading......131 5....................................3.....................................3...................3..4 CCLK AC Specifications .............................................4.......2 External Power Supplies..................................4...................................................1......................................................................................................................................................................1......145 5................2.............3...............................................................................1...

......183 5....5.....................................................................5...................175 5.............................................4 FORCE Event Capability ..........................................................4...................2...............168 5..................................4 Pull-up/Pull-down Resistors .....................................5...................3 ISA Support Implications.......................................................................5...........................18 4 5......4.........5 Enabler Support ..........................4............................................................................................................166 5...............................2...............................2...............................................4................175 5.....2.................................................170 5.......2.................................1 Card Insertion............................................11 Interrupt Pin ...............4............................178 5...............4...............2 Required CIS............................................................3............................2...........172 5.......13 Register Summary .......................................................................................168 5........2.......2............2.......ELECTRICAL SPECIFICATION 5....................................................................5..6.......................5....161 5.......................4..3..163 5......164 5.............................163 5..................4.........................................170 5...........................................4 Socket Requirements..........................................................................181 5...............................3 Required Signals.......................................................5........5...........170 5........................................2 Memory Space ..............................1 16-bit PC Card Support .168 5..........184 © 1999 PCMCIA/JEIDA ix .........................171 5............................................4...................................................................................................12 Tuple Space.5.................................................................................................................4.....................5................................................5..........................................4 System Resource Determination .....5...............5...........4....................................162 5......................................175 5........5 CONTROL Register ..2.....3....1 Functional Interrupts (CINT#) ...............................5..............4..............................3 Card Requirements ..............................5...........................172 5..5.176 5......................174 5.............169 5.....................................5 VPP[2::1] Power Requirements ..............4....175 5..........................................................5.......................................................................5......................................183 5...........................................4...............................................2................................................5................2............................................2..........2....2..........................6 Power Consumption ........170 5..5.....................................1 Configuration Space ..5... 177 5...................4..2 Card Services .......163 5..............................................................................................2...........................17 6 5.............................4.............4...................................3 System Resource Availability.............................................5.............5...........................................................................174 5...........................................................................................169 5..................................................................................4....................1.........................................................................................174 5....................6 Card Insertion and Removal..........4....................5......173 5..........1...........................171 5.........5.......5...4................4.....................................4...........................4.......................................3...............1.......4.............2.................................................................................169 5...........................................3..............................................7 I/O Space Support .165 5............................2 Socket MASK Register.4 Register Descriptions ..............4...................................................................................................................................4.....................4..........5 Requirements For CardBus PC Cards and Sockets.................................................1..........3............2........5 CSTSCHG Support ...............................................................................................................................5...............................5..................................................................................................2 Address Spaces ................................................................2............................2 Status Change Events ............................................2...........................10 Cap_Ptr ....................1 Overview .......4...................................................................5....5..........................................172 5.........................................3.....3 Interrupt Handling and Routing......................................1 Memory Space ................5.........................1................................................................................................................................................................................................................................................171 5..................................4 Expansion ROM...............................................1 Socket EVENT Register.........................2 Software Requirements ............................4.............173 5...........4........3 Socket PRESENT STATE Register .....................................................................................8 CIS Pointer....................................9 Expansion ROM Base Address Register ..............1 CardBus PC Card with Memory Mapped I/O...............................1.................................5.......................................................................................4...............................2...2 CardBus PC Card with I/O Space .................4..........................168 5....................5....................5............................................................................................................................................................................................................................................................................................172 5..............2 I/O Support.....5...............166 5............................................3..............................4..........3.....1 Socket Services.2.....................................3 I/O Space ...........

..................................Reserved................................4.....................4 Glossary of Terms.........................................................................8 Required Pins ...........................4 PMCSR .....................................................2.................209 6.........................7 Control/Status of CardBus Bus Power Management States......................................................3.3.................................................1 Control of Secondary Bus Power Source and Clock.............................2...................................................................186 5.........................................................................................................................................................5 Related Documents ............................6 CardBus Clocking Considerations ........................................................................185 5..5 PMCSR_BSE ........210 x ©1999 PCMCIA/JEIDA ...................................................186 5.........1 Signal Requirements......................................2....190 6.............................4 CardBus B3 State ...........4.............4...................................................1...............200 6........................................................11 Actions When Adapter Is Reset....................1 CardBus B0 State ..4 Bus Support for CardBus Function Power Management......2 Target Audience...4................................205 6.........................................................................................5.......... PCI Bus Power Management Interface for CardBus Cards 189 6........1...............................1 Capability Identifier ....................................................................................................7 Power Cycling the Interface ................189 6.......187 5....4...........................3 PMC .......4.....4.....................................2 Card Removal......................1 Goals of this Specification............................................................2 CardBus B1 State...............209 6.............................3 CardBus Power Management Interface .................... 186 5.......2..........................................................................................4...2 Bus Power States..............................................................2..........................................................6.....................1.........................................................4.... 195 6....................................198 6..............................6 Data (Offset = 7) .....199 6.......2................CONTENTS 5..........................................................................195 6.................207 6...207 6.....................3 Device-Class Specifications .....................3 In-Rush Current ......4....................................................4.3 CardBus B2 State........Fully On..........................................................208 6......196 6.................................201 6...........................................210 6.....................19 4 6..................5 CardBus Bus Power State Transitions ................................................................192 6.............194 6.......................197 6.....1 CardBus Function Power States....................................................................3..........................................................Off..............................................................................2......................................................................................................................................1..................4 CardBus Bus Power States .........2 Next Item Pointer ..........1.......................................................................................................................1..................................190 6.Power Management Capabilities (Offset = 2).1 Capabilities List Cap_Ptr Location....1 Capabilities List Data Structure ........3..7.......................7........................................................................Next_Item_Ptr (Offset = 1) .....1................204 6..2..4..................................................................................................................201 6.....................................................................................2 Power Management Register Block Definition .........5...............................................................................202 6...............3...................................................................4..................................6 Conventions Used in this Chapter ..............................................................................................................................................................2 CardBus Power Management Overview....................5.....................................208 6....1...................4....................................................9 Clock Stopping Support....3..............................................................187 5.............................5...........3 Overview/Scope ...........................5.............................................1 Introduction......3....................................4.....................................................................10 Special Cycle Support ....5...........................................208 6..................195 6...................................................5..........................2...............3....................................................187 5......................5..........5....................................2.......................................................2 CSTSCHG Requirements..............................................................1.....................Power Management Control/Status (Offset = 4) ......1 CardBus Power Management States................................................................................4...PMCSR PCI-to-PCI Bridge Support Extensions (Offset=6) Ð Not Used in CardBus Cards .....................................................................194 6...193 6.....200 6...................................................3....189 6........4.............2..................186 5.................1........................................Cap_ID (Offset = 0).....................................1.......................................7....................................................................................................................................................................................................................................7..............187 6.................................

................................1 Message Encodings......2 Test Hardware Recommendations.........................3...............................................................................................................231 8...............................................ELECTRICAL SPECIFICATION 6...............................................1 CardBus Card Context ..........................223 6....1 Buses........2 Use of Specific Encodings ..........................4...........................................................................2 CardBus Function D1 State.............6 CardBus Cards and Power Management............226 6.....................232 © 1999 PCMCIA/JEIDA xi ....8..........212 6......228 7.....................................4..........................8 Software Support for PCI Power Management..............3............................................................219 6.........................................................4 Measurement Equipment Recommendations ..............................................................................................5.....1 Identifying CardBus Function Capabilities.........................................226 6...............................6 CardBus Card Function Power Management Policies ..................................................226 6..........................232 8.........................................................................................213 6..........8..........................5.......................................................2............7 Power Management Events.........................................................2 Host-side Requirements ..........1 Software Accessible D3 (D3hot).........................................................2.................................8........................5....4.....................................................................................................................................225 6....................4.8..........................................................................................................................................................................................2 D1 and D2 States .................................5..........8.............................................................211 6.......................8............................4 CardBus Function D3 State..........5...........................8.........3.............231 8.................................................................2........................................................................................................................................4 Wake Events ...............................229 8....................................225 6..................................8....226 6......................................................224 6..1 General Recommendations.............................226 6..............................................................................................................2..................................................................................5 CardBus Function Power State Transitions ......6....................213 6..........1 Wake Event Support ......................227 6..................................215 6........5..............................................................9 Other Considerations....................................................................................6 Set Power State ..........................................................................................................................1 CardBus Function D0 State......................................7.....................................................3 Restoring PCI Functions From a Low Power State ......................................................212 6............................................1 Auxiliary Power for D3cold Power Management Events ........................................................................................227 6......211 6......................7 Get Power Status..232 8................................................2 Placing CardBus Functions in a Low Power State.............................229 7............................................................5.... Special Cycle Messages________________________________229 7....................................................8..........5 Get Capabilities.............6...............................................6...................219 6...................1 State Transition Recovery Time Requirements ......2..........................................228 6.................8............................................................................3 D3 State .......................231 8........................................................................3 CardBus Function D2 State............8....227 6...................................................3 Card-side Recommendations ..............213 6..........................................................212 6...............................................................226 6...................................................................1 Background........222 6................................5.2 Power Off (D3cold).......................224 6..................................228 6....5.......................2.............................................................228 6........................................8........................................................................1 Dx States and the DSI Bit......................................................................................................................2 The D0 "Initialized" State From a Wake Event.....................................................2 D3 State ................................................................................................................................................8................... CardBus PC Card Connector Test Methodology__________231 8................................................................................................5 CardBus Function Power Management States...............................2 PME_En/PME_Status and CardBus Cards ...................8..................................................................................................................................................226 6.............................................

...............................................................................................................243 9..................................8 Electrical Interface ...........................239 9..........................2...........................................................3.....1..................1 Host-side Implementation.....................................................................................237 9.........................................................................................................2...........................................4..............................................................................................2................................................................................................................3 Pin Assignments.........................................................................................................3..2.2 Compatibility.............................1......................................................................................................................................................................................2.........................2 Compatibility.....................................................................246 9...............................................................................................................................................................................................1 Finding the Worst Case Ground Bounce............................2.............................2....................................................................................................................243 9.....................................................................3 Pin Assignments..........................................................................................................................................237 9...............................244 9.....2........................................................................7 SDATA .........................................................................................................................................................237 9......235 9.....................................................................................................235 8..............................233 8............................................................................5 Signal Description..........................................237 9..................................................................................................................5..238 9....................................................................2 Card-side Implementation...................................................................................................................................................232 8........................................4 Y[7::0] .........................2...234 8...................................................245 9...................5.................................................5........................................................245 9..246 9..5.........................1 PCLK ............1 Video Interface Timing .......................................................243 9.............5..........................................1.239 9...............................238 9..................................................................5..................................3 Test Board Considerations...6 Functions..........................................................2 Audio Interface Timing...............2......................3............................................................238 9.......3.........................................................................243 9...................................................................251 9..2....................................................247 9....................................7..2...2......2.................................................................247 9....1 Purpose/Overview..............7......................................5....237 9...................................................9 MCLK ............ PC Card Custom Interfaces ____________________________ 237 9.......................................250 9........1 Overview ..............................................................................7 Timing ...........................3 Pin Assignments.10 PC Card Connector Test Methodology ...................243 9......................................................................2 Compatibility..............................................................1...........................................................................................................2.............2...............................243 9.......245 9...........................2.......239 9......2.............1....................................1...................................................................5 UV[7::0] ..............................................................................4 Measurement Methodology...........................................................................................................................................1 Overview ....................................................................................................6 Functions....................243 9...........................................244 9...........................................................................249 9.....................................................................................2.................................................................................................................................8 SCLK ..........................................................................4 Features ..........................................................................................................................................................................4 Features .........5.........................5.2..5 Signal Description.............................................................9 Specific Signals and Functions.........................................................238 9..............................2 VSYNC.........................4 Features .3 DVB CI Port Custom Interface (0241h) ..............6 LRCLK............................................243 9..................................................................................1................................................................................................................................249 9...............................1......................................7 Timing ............................................3.....................2......................................................1............................................................................................241 9...................................CONTENTS 8...........................................3..........................................................1 Custom Interface Requirements.........................................3 HREF ..................2 ZV Port Custom Interface (0141H) .....................................................................................................252 xii ©1999 PCMCIA/JEIDA ......................................244 9................................................237 9...9 Specific Signals and Functions....................................8 Electrical Interface ...............................................................................................................................

...........3..253 9.............................................................................................253 9.........................................................................................................................................................6 MOVAL ............3...........3....................................................................3..............5...........................5 Signal Description............2 MISTRT.............................256 9.....................................................................................................8 Electrical Interface ................................3.....3.....................................................254 9...............253 9..............................................................................................................3...........................................254 9...........................................................................................5.............253 9.............7 MCLKI.........................9 Specific Signals and Functions...........................................................................................5.................................................................253 9..................3..................5...........................................................................................................253 9.................................253 9.................................................................3......................................................................................................................................................8 MCLKO........................................................5..............................ELECTRICAL SPECIFICATION 9..3 MIVAL ....5......................7 Timing .........256 © 1999 PCMCIA/JEIDA xiii ...........4 MDO[7::0]..............................................................................5......1 MDI[7::0]..................................6 Functions.................................................................................5............3..3.........................................................................................................................................3.....................................................................................5 MOSTRT..............................................253 9.....253 9................................................3................

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.............................................................................................................................................................137 Figure 5-30 Clock Skew Diagram ...127 Figure 5-25 V/I Curves for 3.........................................................................................................83 Figure 5-2 CardBus PC Card Basic Write Operation..........................................................................123 Figure 5-23: Function Present State Register .............107 Figure 5-15 Layout of CONFIG_ADDRESS Register ....................................3 V Signaling...........................................................................................................101 Figure 5-11 CardBus PC Card Accessing a Locked Agent............85 Figure 5-4 CardBus PC Card Master-abort Termination.......................94 Figure 5-8 Components of Access Latency ................................................................................................................................................................................................................................................125 Figure 5-24: Function Force Event Register.............................................................................................................................................................................................................140 © 1999 PCMCIA/JEIDA xv .........................90 Figure 5-6 CardBus PC Card Basic Arbitration ...................................................................................................................134 Figure 5-27 CardBus PC Card Clock Waveform .................10 Figure 5-1 CardBus PC Card Basic Read Operation .......................................................ELECTRICAL SPECIFICATION FIGURES Figure 3Ð1 CCD[2::1]# and CVS[2::1] Connections...................................................................................................................117 Figure 5-19 CardBus PC Card Clock Start or Speed up........................................................111 Figure 5-18 CardBus PC Card Clock Stop or Slow Down.................122 Figure 5-22: Function Event Mask Register .............137 Figure 5-29 Input Timing Measurement Conditions..............103 Figure 5-13 Address Stepping .....................109 Figure 5-17 Parity Operation ..............................139 Figure 5-31 Reset Timing............119 Figure 5-21: CardBus PC Card Function Event Register ..........................................................................................................................118 Figure 5-20 Maintaining CardBus PC Card Clock..............................................................................3 V Signaling (CCLK) ..................106 Figure 5-14 Type 0 and Type 1 Configuration Accesses ...............84 Figure 5-3 CardBus PC Card Master Initiated Termination..........................................................................................................................................................135 Figure 5-28 Output Timing Measurement Conditions ..............................133 Figure 5-26 Test Waveform for 3...........................................108 Figure 5-16 Bridge Translation for Type 0 Configuration Cycles............................................................................102 Figure 5-12 CDEVSEL# Assertion.................................................100 Figure 5-10 CardBus PC Card Continuing an Exclusive Access..............................................................................87 Figure 5-5 Target Initiated Termination ..........................................................95 Figure 5-9 CardBus PC Card Starting an Exclusive Access ......................................................92 Figure 5-7 Arbitration for Back-to-Back Access..................................................

....216 Figure 6-9: CardBus Card Power Management Diagram.........................................................................................................................................................................................200 Figure 6-6: PCI Bus PM State Transitions ................245 xvi ©1999 PCMCIA/JEIDA .......161 Figure 5-42 CIS POINTER Layout ........................MCLK = 384fs ...........225 Figure 8Ð1 Host-side Test Board Layout .......................197 Figure 6-4: Capabilities Linked List.......................................................................214 Figure 6-8: Non-Bridge CardBus Function Power Management Diagram..................................................................................151 Figure 5-35 Card and Host with All Spaces Described ..........................................................233 Figure 8Ð2 Card-side Test Board Layout ............................................................................220 Figure 6-10: Vcc to VAUX Transitioning .....................................................................................................................................239 Figure 9-2 ZV Port Signals on PC Card Socket ...........................191 Figure 6-2: Example "Originating Devices" .............................................................................................................................................................................154 Figure 5-37 COMMAND Register Layout...............................................159 Figure 5-40 Base Address Register Mapping for Memory Space ...................................................................183 Figure 6-1: Operating System Directed Power Management System Architecture ................................................................................................................................................................................................................................176 Figure 5-45 Socket MASK Register ...................161 Figure 5-43 Expansion ROM Base Address Register Layout .....................234 Figure 9-1 Example ZV Port Implementation .........................................................................244 Figure 9-4: 1B I2S Format ...181 Figure 5-48 Socket CONTROL Register..............177 Figure 5-46 Socket PRESENT STATE Register.......................................................................................................................................................................209 Figure 6-7: PCI Function Power Management State Transitions..........................................................................................................................................................................................................................................................................163 Figure 5-44 Socket EVENT Register.....................................150 Figure 5-34 I/O Space-only Card in a Host System with a Separate I/O Space....................................152 Figure 5-36 CardBus PC Card Configuration Space ............................160 Figure 5-41 Base Address Register Mapping for I/O Space .FIGURES Figure 5-32 Card with Memory and I/O Space in Host System with no Separate I/O Space149 Figure 5-33 Memory-only Card in Host System...............................................................................................244 Figure 9-5 Video Interface Timing ..................................192 Figure 6-3: Standard PCI Configuration Space Header Type 0 .................199 Figure 6-5: Power Management Register Block .............................242 Figure 9-3: 1A I2S Format ................................179 Figure 5-47 Socket FORCE Register.....................................................................................................157 Figure 5-39 BIST Register.........................................................MCLK = 256fs............155 Figure 5-38: STATUS Register Layout ....................................................................................................

...................................................250 Figure 9-10: DVB CI Port Signals on PC Card Socket ..................................................................................................248 Figure 9-8: Example DVB CI Port Implementation ............ELECTRICAL SPECIFICATION Figure 9-6 Audio Interface Timing ...............................................................................................252 Figure 9-11: Transport Data Stream Interface Timing....................................255 © 1999 PCMCIA/JEIDA xvii ..........................................................249 Figure 9-9: Transport Stream Interface Chaining between Modules .............................................246 Figure 9-7 Host-side Test Board Layout.................

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.................71 Table 5Ð4 CardBus PC Card Commands ................3 V signaling)....................................................................................................................................................167 Table 5Ð26 Code Type Descriptions .....................ELECTRICAL SPECIFICATION TABLES Table 3Ð1 Card Detect and Voltage Sense Connections....................................................................................................................................................144 Table 5Ð17 COMMAND Register Field Definitions ....159 Table 5Ð20 Meaning of the Type Fields for a Memory Base Address Register ...............................................................................................131 Table 5Ð8 AC Specifications for 3................................182 Table 5Ð31 Socket CONTROL Register Fields.135 Table 5Ð11 3................................166 Table 5Ð25 CardBus PC Card Data Structure Fields ...........................................................................................................................................................................................................................................................................................................160 Table 5Ð21 Address Space Indicator Values........................................................107 Table 5Ð7 DC Specification for 3.........................................8 Table 5Ð1 CardBus PC Card List of Signals .....................68 Table 5Ð2 PC Card Pin 1 to Pin 34 Assignments.........................162 Table 5Ð22 Address Space Offset Values .........................................................138 Table 5Ð14 Minimum and Maximum Pull-up Resistor Values (3................................................................................................................75 Table 5Ð5 Address Bus Encoding......................70 Table 5Ð3 PC Card Pin 35 to Pin 68 Assignments....................................................133 Table 5Ð10 CardBus PC Card Clock Specifications..............................183 © 1999 PCMCIA/JEIDA xix ................................................................................3 V Signaling........................................3 V Signaling (CCLK).....132 Table 5Ð9 AC Specification for 3.143 Table 5Ð16 Pull-up/Pull-down Resistor Requirements .....................................................................158 Table 5Ð19 BIST Register Fields.........................................178 Table 5Ð29 Socket PRESENT STATE Register Fields.........................................................................................................................................................................................................................136 Table 5Ð12 Measurement and Test Condition Parameters....................................165 Table 5Ð24 Expansion ROM Image Header ...............168 Table 5Ð27 Socket EVENT Register Fields...............................................................................................................................................................................................................................................137 Table 5Ð13 Clock Skew Parameters...............................................................3 V Signaling .......................................3 V Timing Parameters............................141 Table 5Ð15 Pull-up/Pull-down Resistor Requirements .........................................162 Table 5Ð23 Configuration Space Register Usage Summary .........................177 Table 5Ð28 Socket MASK Register Fields ...............................180 Table 5Ð30 Socket FORCE Register Fields.............................................80 Table 5Ð6 Common Access Field Definitions.156 Table 5Ð18 STATUS Register Field Definition................................................................

.........................................................................................................................................................................................................................218 Table 6-19: CardBus Function State Transition Delays.........................................PMCSR_BSE..........................................................................207 Table 6-12: PCI Bus Power and Clock Control ....TABLES Table 6-1: PCI Status Register ..................221 Table 6-21: PME_En / PME_Status Summary in a CardBus Card.................................215 Table 6-14: D0 CardBus Card Power Management Policies .................................................................................................................................................................................................247 Table 9-5: DVB CI Port Interface Pin Assignments ......218 Table 6-18: D3cold CardBus Card Power Management Policies........................................198 Table 6-3: PCI Configuration Space Header Type / Cap_Ptr mappings.............................................219 Table 6-20: CardBus Card Power Management Policies ...........................198 Table 6-2: Capabilities Pointer .................................................................................................255 xx ©1999 PCMCIA/JEIDA .................................Next_Item_Ptr..........................................................................206 Table 6-11: CardBus Bus Power Management States............251 Table 9-6: Timing Relationship Limits............................199 Table 6-4: Capability Identifier .246 Table 9-4 ZV Port Electrical Interface..............................................217 Table 6-16: D2 CardBus Card Power Management Policies .....................................................................................................................223 Table 9-1 ZV Port Interface Pin Assignments ...................................205 Table 6-9: Data Register........205 Table 6-10: Power Consumption/Dissipation Reporting....201 Table 6-6: Power Management Capabilities Ð PMC for CardBus Cards .241 Table 9-2 AC Parameters for Video Signals .........................................................................202 Table 6-7: Power Management Control/Status ............................................................................................................................................................................Cap_ID ................................................................217 Table 6-15: D1 CardBus Card Power Management Policies ..................PMCSR .....204 Table 6-8: PMCSR Bridge Support Extensions ............................................................................................246 Table 9-3 AC Parameters for Audio Signals.................................................................................................Cap_Ptr.........................................................................210 Table 6-13: State Diagram Summary......................................217 Table 6-17: D3hot CardBus Card Power Management Policies.................200 Table 6-5: Next Item Pointer .........

X. and CardBus PC Card interface specifics. This new release of the PC Card Standard has resolved this dilemma by developing the CardBus PC Card interface which enables these new functions and still accepts cards developed to the 16Ðbit PC Card interface.2 and earlier releases and CardBus PC Card Sockets.3 V © 1999 PCMCIA/JEIDA 1 .X V is less than 3. It is organized in three sub-sections dealing with items common to all interfaces. compatibility with PCMCIA 2. operation at 5 V.0 / JEIDA 4. the spectrum of applications which can be supported by PC Cards has again been broadened. Just as PCMCIA 2.either 32Ðbit bandwidth. 132 MBytes/sec peak bandwidth at 33 MHz clock frequency. or both.1 evolved the PCMCIA 1. interface timings. support of 8Ðbit and 16Ðbit Slave DMA. interface protocol. this new release evolves to include the capabilities outlined below.) a specification for current draw and time to READY. This release enables many types of PC Cards ranging from 16Ðbit slave cards to 32Ðbit bus master cards.X1 V). reduced latency via bus master capability. The PC Card Standard continues an evolutionary process by providing additional capabilities thereby expanding the variety of PC Cards that can be supported. As a result. 3.3 V and lower voltage operation. including multiple points in between such as 16Ðbit slave DMA and 32Ðbit slave cards. The capabilities of 16Ðbit PC Cards have been expanded and now provide: • • • • • • • • • 16 bit data / 26 bit addressing.3 V. X. 3.1 / JEIDA 4.0 memory only interface by adding I/O capability. However. support of multiple function cards. and specifics of card insertion. programming model.X V voltage levels. 20 MBytes/sec peak bandwidth at 100 ns cycle rate.3 V and X. hardware detection of card voltage requirements (5 V.0 / JEIDA 4. synchronous interface. removal. a Card Information Structure (CIS) with expanded capabilities to identify functions and data formats. and configuration. power up. signaling environment. The CardBus PC Cards provide: • • • • • 1 32Ðbit multiplexed address/data with parity. These capabilities provide higher performance levels than previously available as well as new features such as card-to-card transfers without intervention by the host CPU. (See the Metaformat Specification. O V E R V IE W The Electrical Specification describes the connector pinout. there still exists a class of applications which remain better suited for the 16Ðbit environment because it already offers sufficient performance. support for Bus Masters on PC Cards. There is an emerging class of applications which require higher performance . 3. 16Ðbit PC Card interface specifics.ELECTRICAL SPECIFICATION 1.

hardware detection of card voltage requirements (5 V. td(WT).X V is less than 3.3 V Y. X.in addition to CardBus PC Cards.1 PCMCIA 2.1.1 (September 1991) • • • added the I/O and Memory interface.1/JEIDA 4. an enhanced 68-pin connector which provides improved signal grounding/noise reduction -.1 Summary of Electrical Specification Changes 1. interface power management.x/JEIDA 4.1. 1.0/JEIDA 4. changed the I/O read (input) timing Ñ data delay from WAIT# rising.x) and new 16-bit PC Cards.Y V is less than X. defined the WAIT# signal. 3. hardware detection of the card type installed (CardBus PC Card vs. Y.1. the socket connector accepts all 16Ðbit PC Cards.2 release provided corrections to PCMCIA 2.X V 2 ©1999 PCMCIA/JEIDA .OVERVIEW • • • • • • • • support for remote system and/or interface wake up even when the interface is powered down. 16Ðbit PC Card). the same PC Card mechanical form factors defined for all PC Cards. (-REG is now REG#).2 PCMCIA 2.Y V3) 1.3 PC Card Standard February 1995 Release (Release 5. X.1/JEIDA 4. 1.X V2. ability to mix CardBus PC Cards and 16Ðbit PC Cards in sockets controlled by the same CardBus PC Card adapter. renamed the RDY/-BSY signal READY (with no change in function). from 35 ns to 0 ns. compatibility with existing (PCMCIA 2. defined the only RFU pin in the I/O and Memory interface as voltage sense two (VS2#). defined the signal OFF states (use of pull-ups and switched VCC). changed the signal naming convention to denote an active-low signal with a Ò#Ó. defined multiple voltage operation with initial operation at voltages other than 5 V.0/JEIDA 4.2 (July 1993) The electrical section of the PCMCIA 2. defined DMA transfer cycles and use of signals for cards and sockets capable of DMA operations.0) • • • • • • • • • • 2 3 added the CardBus PC Card interface. defined Multiple Function 16-bit PC Cards Ñ more than one set of configuration registers. defined the RESET signal.3 V. redefined RFSH as voltage sense one (VS1#).1.

(See also the Overview and Glossary.0 Release (March 1997) • addition of the Thermal Ratings system for PC Cards 1.8 PC Card Standard 6.1. has a name which does not end with a "#" character.) 1.ELECTRICAL SPECIFICATION • specified the Card Configuration Register initialization sequence.1. such as VCC.7 PC Card Standard May 1996 Update (Release 5. addition of a Power Management interface for CardBus cards 1. 1.1.1.2.0 Release (February 1999) • • • addition of the Digital Video Broadcasting (DVB) Port PC Card Custom Interface addition of the PC Card Memory Paging mechanism to extend the size of PC Card common memory space beyond 64 Mbytes corrections to the Power Management interface for CardBus cards 1.1 Signal Naming All signals are named with respect to their asserted state as follows: a) Each signal which is not a logic signal. © 1999 PCMCIA/JEIDA 3 .6 PC Card Standard November 1995 Update (Release 5.01) • general editorial corrections 1.2 Conventions This section is intended to give general descriptions of notation conventions used in this document.2) • addition of the Zoomed Video (ZV) Port PC Card Custom Interface 1.1.1 Release (April 1998) • • The addition of the Small PC Card form factor.10 PC Card Standard 7.5 PC Card Standard May 1995 Update (Release 5.4 PC Card Standard March 1995 Update (Release 5.1. which adheres to the PC Card Standard Electrical Specification except that the CardBus interface is not supported.9 PC Card Standard 6.02) • clarification of Power Waveforms at Power-on 1.1.1) • • • addition of Custom Interfaces for PC Cards addition of Indirect CIS Addressing for PC Cards clarifications for Multifunction PC Cards 1.

c) Each logic signal whose name ends with a "#" character has logic low as the asserted state and logic high as the negated state. and must be provided by the central resource. Each digit represents 4 bits and is indicted by the characters "0" through "9" and "A" through "F" giving each digit a value of 0 to 15 (decimal). Sustained High-Z is an active low High-Z signal owned and driven by one and only one agent at a time. 1. A pull-up is required to sustain the inactive state until another agent drives it. o/d DC 4 ©1999 PCMCIA/JEIDA .2 Numeric Representation Numbers are expressed as follows: a) Individual bits are expressed as "0" for zero.2. or "X" for "any value". b) Groups of bits (fields) are expressed in hexadecimal number which begin with one or more digits and are followed by an "H". "1" for one.3 Bit Action Representation Bits of a register are said to be set when they are made equal to "1" and to be reset when they are made equal to "0" . 1.4 Signal Summary Signal Types: in out i/o h/z s/h/z Input is a standard input-only signal.2. 1. Open Drain allows multiple devices to share a signal as a wire-OR. The agent that drives an s/h/z pin low must drive it high for at least one clock before letting it float. Input/Output is a bi-directional signal. A new agent cannot start driving a s/h/z signal any sooner than one clock after the previous owner places it in a High-Z state. The number of bits in the field determines how many bits in the hexadecimal number are significant. DC refers to power or ground pins which are not used for any information transfer.OVERVIEW b) Each logic signal whose name does not end with a "#" character has logic high as the asserted state and logic low as the negated state. Totem Pole Output is a standard active driver.2. High-Z is an output or I/O pin driver which is in the high impedance state when it is disabled. An "X" is used to indicate a digit of "any value".

the respective planes on the card must never be shorted together or shorted to VCC. VPP[2::1] must be initially powered up at the voltage indicated by the voltage sense pins which means systems are required to be able to supply the VCC level on the VPP[2::1] pins. the voltage applied to the VPP[2::1] pins must not exceed VCC. VPP[2::1]. the host shall direct the socket to discharge the PC Card connectorÕs VCC and VPP[2::1] to ground. or GND. 2. Signals whose function is specific to an interface are described in their respective sections.3 V. The host is not required to account for shorted power planes in the design of its power supplies or power delivery schemes. 2.ELECTRICAL SPECIFICATION 2.1 Power and Ground Pins Power and ground for all PC Card interfaces must be provided by the host system. then power-up the card at the new voltage. the availability of 5 V in the system. The host must recognize that the card will retain no knowledge of the power-up at the previous VCC and all configuration and other initialization must be done following the second power-up. To change VCC. Refer to the Metaformat Specification for information on describing the cardÕs VCC and VPP[2::1] requirements in the Card Information Structure. The voltage level on VPP[2::1] cannot be changed until the Card Information Structure (CIS) of the card has been read and other permissible values have been determined. X. 2. © 1999 PCMCIA/JEIDA 5 .Y V VCC voltages.1 VCC and GND Pins The two 16Ðbit PC Card interfaces support 5 V. PC Cards may not apply any voltage to VCC. If the CIS indicates the card could be operated at a different voltage level. 3. 34.1. Deciding whether the socket hardware must support 5 V is a function of the interfaces being supported. the host can change to the new voltage level. Regardless of how PC Cards use VPP[2::1]. Further.2 VPP1 and VPP2 Pins The VPP[2::1] (pins 18 and 52) supply signals are used optionally on the card for PC Card operation. The connector places the two VCC pins (17 and 51) and four GND pins (1. and which cards need to be enabled. and GND. the host system must recognize that the card may have been replaced and repeat the entire power-up sequence. COMMON PIN DE S C R IP T ION A number of pins have the same function for all three interfaces specified in this release: VCC. and VCC requirements. VPP[2::1]. Sockets are not required to support 5V VCC operation. If the appropriate VPP[2::1] voltage for a card cannot be determined. 35 and 68) at symmetrical positions on the connector. card type.3 V and X.X V and Y.X V VCC voltages while the CardBus PC Card interface supports 3. The voltage applied to the VPP[2::1] pins of a card must never be greater than the VPP[2::1] level appropriate for the card. Several other pins are used for the same purpose in all three interfaces and have similar function in terms of providing information about card presence. care should be taken when dynamically changing the voltage applied to VCC or VPP[2::1] so that power supply shorts do not occur. If any Card Detect pin is negated at any time. The voltage level on VCC cannot be changed until the Card Information Structure (CIS) of the card has been read and other permissible values have been determined.1.

COMMON PIN DESCRIPTION When the VPP[2::1] value required by a card is unavailable in a system.4 Determining Card Type in CardBus PC Card Capable Sockets. These pins are at opposite ends of the connector to ensure a valid insertion (i.they are inputs pulled high through a resistor.2.2 Interface Configuration Pins The Card Detect pins. CardBus PC Cards also use the CCD[2::1]# pins in conjunction with CVS[2::1] to encode card type information. (See 3. Host sockets shall only report valid insertions when both Card Detect pins are detected low (CD[2::1]# or CCD[2::1]#).4 Determining Card Type in CardBus PC Card Capable Sockets.2.2 Voltage Sense Pins (VS[2::1]# and CVS[2::1]) The Voltage Sense signals notify the socket of the cardÕs VCC requirements for initial power up and configuration. For CardBus PC Cards. differences in the usage of these pins exist between the 16Ðbit PC Card and CardBus PC Card interfaces. these pins are also used to distinguish between 16Ðbit PC Card and CardBus PC Cards. The host socket interface circuitry shall provide a 10 K Ω or larger pull-up resistor to VCC on each of these signal pins. Careful attention should be given to the following discussions since subtle. guarantees both sides of the card are firmly seated). and CardBus PC Card) . 2.1 Card Detect Pins (CD[2::1]# and CCD[2::1]#) The Card Detect pins provide a means for sockets to detect PC Card insertion and removal events. (See also 3.3 Graceful Rejection in 16-bit PC Card Only Sockets.) 2. (See also Figure 3Ð1 CCD[2::1]# and CVS[2::1] Connections. VS[2::1]# or CVS[2::1] are used by the host system to establish the presence/absence of a PC Card in a socket and the voltage requirements of the card. 2. Failure to do so may cause electrical damage to PC Cards. the system may reject the card. 16-bit PC Card I/O and Memory.e. Cards implementing the 16Ðbit PC Card interface must connect CD1# and CD2# to ground internally on the PC Card causing the socketÕs inputs to be pulled low whenever a card is inserted. the Card Detect pins function the same for all three interfaces (16-bit PC Card Memory-only. (See also 3. CD[2::1]# or CCD[2::1]# and Voltage Sense pins. but very important. From the socketÕs perspective.) 6 ©1999 PCMCIA/JEIDA .) CardBus PC Cards also use the CVS[2::1] pins in conjunction with CCD[2::1]# to encode card type information.) However. CardBus PC Cards also cause the socketÕs CCD[2::1]# inputs to be pulled low upon insertion.

1 PC Card Encodings This specification provides the ability to support VCC values of 5 V.Y V (where Y. and various combinations of each.X V < 3. 3. To initially power up a PC Card and determine its characteristics.e.X V). and VPP[2::1] accordingly. 5 V or Low Voltage (LV) key. CardBus PC Card) must be detected before the socket notifies Card Services of an insertion event.3 V). Any card not capable of having its CIS read at 5 V shall be keyed with the LV key. VCC and VPP[2::1] must be at a voltage indicated by the Voltage Sense pins.) PC Cards must implement one of two physical keys shown. PC Cards must indicate the voltage(s) at which their CIS can be read by connecting the Card Detect and Voltage Sense pins.Y V operation and the CardBus PC Card interface does not support 5 V CardBus PC Card operation. a CardBus PC Card socket may support 5 V 16-bit PC Card operation.X V (where X. the host system may change the card's VCC. If the Card Information Structure (CIS) indicates that the card can operate at voltages other than the voltage at which it was initially powered up. This section describes how sockets determine the card interface and initial voltage requirements.. Y. CAR D T YP E DE T E C T ION M E C H AN IS M The card interface (16Ðbit PC Card vs.) The CIS on a card shall be capable of being read at the VCC level indicated by the Voltage Sense pins.. © 1999 PCMCIA/JEIDA 7 . 3.) Any card capable of having its CIS read at 5 V shall be keyed with the 5 V key. the 16Ðbit PC Card interface does not support Y. (See 2. (See the Physical Specification. Common Pin Description.ELECTRICAL SPECIFICATION 3 . Any voltage combinations not listed in Table 3Ð1 are not supported (i.Y V < X.3 V. X.

X V 3.Y V 3. ensure that VCC and VPP[2::1] are removed from the socket and signals are placed in the High-Z state. the card inputs shall not be driven. without software intervention. 3. Sockets which provide 3. 3.X V and Y. These sockets may assume that all valid insertions (i.X V 3.e.X V X. the card shall not be powered.) This key allows the insertion of both 5 V keyed and Low Voltage keyed cards..3 V and X.3 V. Failure to require both Card Detect pins to be low may result in falsely decoding a cardÕs VCC requirements.Y V X.3 Graceful Rejection in 16Ðbit PC Card Only Sockets Sockets which do not support the CardBus PC Card interface must tie their VS1# and VS2# inputs high through a pull-up resistor. the socket shall allow the application of that VCC level to the card.3 V and X.e.X V X. Low voltage sockets must only treat the Voltage Sense pins as valid when both Card Detect pins are asserted low.3 V 3.3 V 5 V. before the next PC Card is inserted).3 V and X.CARD TYPE DETECTION MECHANISM Table 3Ð1 Card Detect and Voltage Sense Connections CD2#/CCD2# (pin 67) ground ground ground ground ground ground connect to CVS2 connect to CVS1 ground connect to CVS2 ground connect to CVS1 ground ground CD1#/CCD1# (pin 36) ground ground ground ground connect to CVS1 ground ground ground ground ground connect to CVS2 ground connect to CVS1 connect to CVS2 VS2#/CVS2 (pin 57) open open ground open open ground connect to CCD2# ground ground connect to CCD2# connect to CCD1# open ground connect to CCD1# VS1#/CVS1 (pin 43) open ground ground ground connect to CCD1# ground ground connect to CCD2# open open open connect to CCD2# connect to CCD1# ground Key 5V 5V 5V LV LV LV LV LV LV LV LV LV Card Type Interface 16Ðbit PC Card 16Ðbit PC Card 16Ðbit PC Card 16Ðbit PC Card CardBus PC Card 16Ðbit PC Card CardBus PC Card CardBus PC Card 16Ðbit PC Card CardBus PC Card CardBus PC Card CardBus PC Card reserved reserved Voltage 5V 5 V and 3. X. both Card Detect pins low) are 16Ðbit PC Card interface cards and ignore the interrogation protocol required 8 ©1999 PCMCIA/JEIDA .Y V Y.X V and Y. Such a socket shall always apply initial VCC at 5 V and need not sense the VS[2::1]# signals..X V 3.2 Socket Key Selection A 5 V only socket shall be keyed with the 5 V key which allows only cards with the 5 V key to be inserted. Note that this type of socket is restricted to the 16Ðbit PC Card interface since 5 V only CardBus PC Cards are not supported. A socket capable of accepting a card with a Low Voltage key must implement cold insertion (i.3 V 3.3 V or lower voltage VCC levels must implement the Low Voltage (LV) socket. If Voltage Sense pins indicate values of VCC the socket is not capable of providing. If the Voltage Sense pins indicate a VCC value the socket is capable of providing. and the user may be notified. (See the Physical Specification.

) Note that the CVS[2::1] resistors could be integrated into their drivers so that each only consumes a single pin on the socket controller.1 Card Insertion.e. RCD CCD1# CVS1 RVS CVS1_DRV CVS2 PC CARD SIDE RVS SOCKET STATE MACHINE CVS2_DRV RCD CCD2# CONNECTOR DEBOUNCE Figure 3Ð1 CCD[2::1]# and CVS[2::1] Connections A series of steps is required to identify and configure a card upon insertion into a CardBus PC Card capable socket.ELECTRICAL SPECIFICATION for the CardBus PC Card interface.6. At the completion of this interrogation. the user may be notified that one of the following conditions exists: 1. (See 5.e.4.) © 1999 PCMCIA/JEIDA 9 .. the socket must interrogate the PC Card to determine if it is a CardBus PC Card or 16Ðbit PC Card.4 Determining Card Type in CardBus PC Card Capable Sockets Since a valid CardBus PC Card insertion (i. This is because a CardBus PC Card always ties one Card Detect pin to a Voltage Sense pin instead of to ground causing it to only pull one of the Card Detect inputs low. (See Figure 3Ð1 CCD[2::1]# and CVS[2::1] Connections. the socket must again drive the CVS[2::1] pins low. CCD[2::1]# and CVS[2::1] pins. 3. A card has not been inserted correctly or completely. This means the socket must drive the CVS[2::1] pins low at all times except when determining the card type and VCC requirements. or The card inserted is of a type not supported by this socket (i.5. CCD[2::1]# pins are sampled low at the same time after having been debounced) can only be detected when both CVS[2::1] pins are low. CardBus PC Card). If a 16Ðbit PC Card only socket senses only one Card Detect input low. and the connector might be connected is provided. 2. An example of how the socketÕs state machine. Once a valid insertion is detected and before power is applied. This interrogation consists of determining which CCD[2::1]# and CVS[2::1] pins are shorted to ground or each other and which are not connected by alternately driving each CVS[2::1] output high and monitoring what happens to the CCD[2::1]# and CVS[2::1] inputs. sockets must always drive their CVS[2::1] outputs low when PC Card removal occurs..

CARD TYPE DETECTION MECHANISM 10 ©1999 PCMCIA/JEIDA .

ELECTRICAL SPECIFICATION 4 . Further.0 / JEIDA 4.3 CardBus PC Card Electrical Specification. Powering up such cards to the proper voltage is not defined by this Standard. WP. VPP[2::1]. no signal shall be directly connected between cards other than ground. can subsequently take advantage of the RESET and WAIT# signals employed on the card.0 Standard defined the Memory Only interface without the Card Reset (RESET) input and Extended Bus Cycle (WAIT#) output signals. PC Cards which are not intended for operation in PCMCIA 1. In order to be backward compatible a PCMCIA 2.0 / JEIDA 4.0 / JEIDA 4. I/O cards or mixed I/O and Memory cards) need not present a valid CIS while RESET is asserted.0 host system must appear to the host system on Power-on. Note: Any PC Card that implemented the previously incompletely defined function on pin 43 (as an input) may now be inserted into a socket that implements VS1#.1 / JEIDA 4.) The READY signal shall not be connected between cards when the 16-bit PC Card interface socket supports both I/O and Memory interfaces. VS[2::1]#.1 Pin Assignments and also 5. © 1999 PCMCIA/JEIDA 11 .0 / JEIDA 4.0 / JEIDA 4.1 / JEIDA 4.1 or later PC Card. READY shall not be wire-ORÕd or wire-ANDÕd with any host signals.0 / JEIDA 4. Sockets supporting both 16-bit PC Card and CardBus PC Card interfaces shall further observe CardBus PC Card constraints. which may falsely detect the power-up voltage.B IT PC CAR D EL E C T R IC AL I N T E R F AC E 4.1 Memory Card is inserted into the socket of a PCMCIA 1. after the 20 ms VCC settling time. as a PCMCIA 1. When a PCMCIA 2. 4. Host systems built to the PCMCIA 1. CD[2::1]#. and shall not reply to read commands or act on write commands while RESET is asserted.1.1 Compatibility Issues 4.2 Pin Assignments For 16-bit PC Card interface sockets.0 host system sockets (e.1.0 host system. In systems which switch VCC individually to cards.1 and earlier releases of the Standard named pin 43 RFSH.2 VS1# replaces RFSH (pin 43) PCMCIA 2. 1 6 .0 / JEIDA 4. 4.0 / JEIDA 4.g.1 RESET and WAIT# Support The PCMCIA 1.1.0 interface have the RESET and WAIT# pins as no connects. upon recognizing a PCMCIA 2.1 and later host system sockets.0 compliant card in its initial default power-on state. CE[2::1]#. (See 5.2 Memory Card inserted into the socket of a PCMCIA 1. card outputs must not be wire-ORÕd or wire-ANDÕd with any host signals. PCMCIA 2. the RESET signal will appear asserted continuously.0 / JEIDA 4. These signals that are outputs from the card must not be directly connected to any other signal source within the host. WAIT#. and BVD[2::1] shall not be connected between PC Cards. This pin is now redefined as VS1#.

2. "O" indicates signal is output from PC Card. 12 ©1999 PCMCIA/JEIDA .16-BIT PC CARD ELECTRICAL INTERFACE Table 4Ð1 16-bit PC Card Pin 1 To Pin 34 Assignments Memory Only Card Interface (Always available at card insertion) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 I/O and Memory Card Interface (Available only after card and socket are configured) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Signal GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# READY VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND 1. I/O 2 DC I/O I/O I/O I/O I/O I I I I I I I I I O Function Ground Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Card Enable Address bit 10 Output Enable Address bit 11 Address bit 9 Address bit 8 Address bit 13 Address bit 14 Write Enable Ready Signal GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND I/O 2 DC I/O I/O I/O I/O I/O I I I I I I I I I O DC in DC in I I I I I I I I I I I I/O I/O I/O O DC Function Ground Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Card Enable Address bit 10 Output Enable Address bit 11 Address bit 9 Address bit 8 Address bit 13 Address bit 14 Write Enable Interrupt Request Supply Voltage Programming and Peripheral Supply 1 Address bit 16 Address bit 15 Address bit 12 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 Address bit 0 Data bit 0 Data bit 1 Data bit 2 I/O Port Is 16-bit Ground 17 18 1 DC in Supply Voltage DC in I I I I I I I I I I I I/O I/O I/O O DC Programming Supply Voltage 1 Address bit 16 Address bit 15 Address bit 12 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 Address bit 0 Data bit 0 Data bit 1 Data bit 2 Write Protect Ground 17 18 1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1 34 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1 34 Use of pin changes between the Memory Only and the I/O and Memory interface. "I" indicates signal is input to PC Card.

0 / JEIDA 4. ÒIÓ indicates signal is input to PC Card.1 / JEIDA 4.0 version of the Standard. RESET and WAIT# are RFU in PCMCIA 1. 5.2 and earlier versions of the Standard. © 1999 PCMCIA/JEIDA 13 . These signals are required in PCMCIA 2. VS2# was RFU in PCMCIA 2.0 / JEIDA 4.1 / JEIDA 4. ÒOÓ indicates signal is output from PC Card.1 and all later versions of the Standard. 2. 3.2 and earlier versions of the Standard.ELECTRICAL SPECIFICATION Table 4Ð2 16-bit PC Card Pin 35 To Pin 68 Assignments Memory Only Card Interface (Always available at card insertion) Pin 35 36 37 38 39 40 41 42 43 4 44 1 I/O and Memory Card Interface (Available only after card and socket are configured) Pin 35 36 37 38 39 40 41 42 43 4 44 1 Signal GND CD1# D11 D12 D13 D14 D15 CE2# VS1# RFU RFU A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# RFU REG# BVD2 BVD1 D8 D9 D10 CD2# GND 1. I/O 2 DC O I/O I/O I/O I/O I/O I O Function Ground Card Detect Data bit 11 Data bit 12 Data bit 13 Data bit 14 Data bit 15 Card Enable Voltage Sense 1 Reserved Reserved Signal GND CD1# D11 D12 D13 D14 D15 CE2# VS1# IORD# IOWR# A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND I/O 2 DC O I/O I/O I/O I/O I/O I O I I I I I I I DC in DC in I I I I O I O O I O O I/O I/O I/O O DC Function Ground Card Detect Data bit 11 Data bit 12 Data bit 13 Data bit 14 Data bit 15 Card Enable Voltage Sense 1 I/O Read I/O Write Address bit 17 Address bit 18 Address bit 19 Address bit 20 Address bit 21 Supply Voltage Programming and Peripheral Supply 2 Address bit 22 Address bit 23 Address bit 24 Address bit 25 Voltage Sense 2 Card Reset Extend bus cycle Input Port Acknowledge Register select & I/O Enable Audio Digital Waveform Card Status Changed Data bit 8 Data bit 9 Data bit 10 Card Detect Ground 45 1 46 47 48 49 50 51 52 1 45 1 46 47 48 49 50 51 52 1 I I I I I Address bit 17 Address bit 18 Address bit 19 Address bit 20 Address bit 21 DC in Supply Voltage DC in I I I I O I O Programming Supply Voltage 2 Address bit 22 Address bit 23 Address bit 24 Address bit 25 Voltage Sense 2 Card Reset Extend bus cycle Reserved I O O I/O I/O I/O O DC Register select Battery Voltage Detect 2 Battery Voltage Detect 1 Data bit 8 Data bit 9 Data bit 10 Card Detect Ground 53 54 55 56 575 58 3 53 54 55 56 57 58 59 60 1 59 3 60 1 61 1 62 1 63 1 61 1 62 1 63 1 64 65 66 67 68 64 65 66 67 68 Use of pin changes between the Memory Only and the I/O and Memory interface. 4. VS1# was named RFSH in PCMCIA 2.

With 16-bit Address Extension Registers: 242 bytes with 1 Address Extension Register. A separate memory address space is permitted for each memory card installed in a system. 234 bytes of Common Memory can be addressed. respectively. the Card Services Specification as of the PC Card Standard Release 6. When the card neither contains an Address Extension Register nor uses the Configuration Option Register (COR) for address extension. the system can address 241 and 240 bytes. SRAM Without Address Extension Registers: 64 MBytes A[25::0] maximum With 8-bit Address Extension Registers: 234 bytes with 1 Address Extension Register.1 supports a maximum Common Memory size of 4 Gbytes. of Common Memory. The COR can be used to address up to 232 Common Memory bytes. 4. EEPROM. The exact size of the memory space depends on the number of registers on the card which support address extension.3 16-bit PC Card Features Table 4Ð3 Features of 16-bit PC Card Asynchronous Interface Item Access Data Bus Memory Types Memory Capacity1 Feature Random access Bus 16 bits/8 bits MaskROM. the cardÕs memory size is limited to 64 Mbytes (using signals A[25::0]). With a memory paging architecture based on one or more registers providing an address extension. 242 bytes of Common Memory can be addressed.3. 14 ©1999 PCMCIA/JEIDA . When a single 8-bit Address Extension Register is present on the card. of Common Memory. A host Direct-Memory Access controller may access data using Common Memory read or write cycles when Common Memory is mapped into the host Direct-Memory Access controllerÕs address space. With two and four 16-bit Address Extension Registers present on the card. With two and four 8-bit Address Extension Registers present on the card. respectively. Attribute Memory for storing card identification 64 MBytes A[25::0] maximum (64 KBytes for PC compatible architectures) Overlapping I/O Address Window: card performs partial selection decoding Independent I/O Address Window: system performs entire selection decoding One Interrupt Request signal per card. 233 bytes with 2 Address Extension Registers. 232 bytes with 4 Address Extension Registers. When a single 16-bit Address Extension Register is present on the card. the system can address 233 and 232 bytes.16-BIT PC CARD ELECTRICAL INTERFACE 4. Routed to specific interrupt level by the host system Even though the Address Extension Registers provide for addressing beyond 4 Gbytes of Common Memory. the card can support more than 64 Mbytes of memory. 241 bytes with 2 Address Extension Registers and 240 bytes with 4 Address Extension Registers. EPROM. With the ÒCommon Memory Address ExtensionÓ field of the Configuration Option Register: 232 bytes REG# function I/O Address Space I/O Space Decoding I/O Interrupts 1. The Common Memory may be accessed by a host system for memory read and write operations. Flash-Memory. OTPROM.1 Memory Address Space A Common Memory space as large as 242 bytes can be supported by a PC Card.

and BVD[2::1] are present on the Memory Only interface but replaced by other signals when the I/O interface is selected. The Attribute Memory space may be divided into areas for: 1. © 1999 PCMCIA/JEIDA 15 . This memory space is inappropriate for DMA operations because only even-byte addresses are populated.3. It is recommended that the Card Information Structure and the Function Configuration registers be located at relatively low addresses to ensure their accessibility by all hosts. The signals READY. contiguous region. 4. The Memory Only interface is the default selected in both the socket and the card whenever a card is inserted into a socket. WP.0 / JEIDA 4. Peripheral cards may be designed such that the host system alone determines when the card is selected. if appropriate. Reserved Area Ñ the portion of the Attribute Memory space which has not yet been specified. When a 16-bit operation is attempted to an 8-bit I/O port.ELECTRICAL SPECIFICATION There is an additional 64 MB address space for Attribute Memory which is selected by the REG# signal at the interface. After a PC Card's Card Information Structure has been interpreted. but does not include signals which support I/O Cards. Alternatively. (See 4. 3.2 Memory Only Interface The Memory Only interface supports memory cards. The size of each of these areas is determined by the card vendor.0 release or later compliant systems.0 / JEIDA 4. This interface is required in all PCMCIA 2. (See also the Metaformat Specification. The Card Information Structure must begin at address 0 but need not be a single. This permits hardware in a system to adjust the access width (8 or 16 bits) to match the size of I/O port being addressed. The host then programs the card to perform a particular decoding using the card's Configuration registers.4 I/O Interface. PC Cards and systems which are designed to the PCMCIA 1. I/O registers (ports) may be 8 or 16 bits wide. the card and the socket may be configured.) Configuration Registers Ñ an optional set of registers which allow the card to be configured by the system.3. and immediately following the application of VCC or the RESET signal to a card. The card includes information in the Card Information Structure which tells the host the address decoding the card may be configured to perform. However. the system hardware may divide the operation into two consecutive 8-bit operations as is done in Personal Computer systems (PCÕs) that support the ISA bus structure.0 version of the Standard do not support the RESET or WAIT# signals. 2. The I/O address space is shared and divided among all the cards installed in the system. to use the I/O interface. Card Information Structure Ñ a description of the card's capabilities and specifications and (optionally) its use. both the host and card may play a role in determining when the latter is selected. An IOIS16# signal is activated by each I/O card when the address at the interface corresponds to a 16-bit I/O register.3 I/O Address Space The hardware interface supports a single I/O address space of 64 MB (signals A[25::0]) for peripheral device access. many system architectures (such as the x86 architectures found in many Personal Computers) support only a 64 KByte I/O address space.3.) 4.

Peripheral cards must be configured by the system before their I/O address space becomes accessible. Correspondingly. The I/O interface also supports the following additional signals. I/O Port is 16 bits (IOIS16#). Unless otherwise specified. Custom interfaces are expected to support enhanced features. The Extend Bus Cycle (WAIT#) and Card Reset (RESET) signals. Before configuring a card.3.0 release Memory Only interface. and BVD[2::1] signals.3. and that the Memory Only interface be selected in the socket when no card is inserted and immediately following card reset and the application of VCC to the card. If no card configuration is suitable for the system. A peripheral card drives the Input Port Acknowledge signal (INPACK#) low when an input port on the card is being accessed. Peripheral cards must be configured by the system before their I/O interface becomes active. WP. I/O Write strobe (IOWR#). are required for both the Memory Only and the I/O and Memory interfaces in all systems supporting the PCMCIA 2. or customized signals not applicable across architectures. some of which replace Memory Only signals not supported by the I/O interface: Interrupt Request (IREQ#). The I/O interface contains all the signals in the Memory Only interface with the exception of the READY. thereby eliminating conflicts with other I/O devices. 16 ©1999 PCMCIA/JEIDA . as determined by the system's hardware and software capabilities.1 release or later. a card might decode only A[9::0] and respond only when a range of addresses corresponding to the peripheral's registers are selected. or which have already been assigned by the system to other cards. Furthermore. and other requirements of the possible card configurations. 4. This allows any data buffers in the host between the card and the host's internal bus to be activated during the access. including this version of the PC Card Standard.0 / JEIDA 4. Since systems with 8-bit data buses are not required to implement 16-bit data buses or 16-bit operations.5 Custom Interfaces Systems may provide custom interfaces through a standard socket.4 I/O Interface The I/O interface requires that the Memory Only interface also be implemented within the same socket. the system must examine the card's Card Information Structure to determine the I/O address space. the cards may decode a portion of the address space. such as internal bus extensions. they should allow the system to locate them arbitrarily in the I/O address space. audio digital wave form intended for a speaker (SPKR#). the system could decode address lines A[9::8] and simultaneously select all the appropriately configured peripheral cards only when A[9::8] is asserted. I/O Read strobe (IORD#). interrupt request. It is recommended that new devices which do not require software compatibility with existing drivers decode only enough address lines to address the number of I/O ports implemented. because the card requires resources which are not available in the system. all signals must be implemented by the system to be compliant with the I/O portion of the Standard. The system uses this information to select the best configuration from those available in the card. and a card Status Changed (STSCHG#) signal. For example.16-BIT PC CARD ELECTRICAL INTERFACE To ensure compatibility in peripheral cards which completely emulate existing fixed address peripherals. Input Port Acknowledge (INPACK#). the system may reject the card without configuring it. which are not required in a PCMCIA 1. such 8-bit systems must keep the CE2# signal in the negated state at all times. A card or a socket may support more than one custom interface.0 / JEIDA 4. 4. as well as the requirements of other cards installed concurrently.

(See Table 4Ð18 PC Card Logic Levels. and R (Reserved). Input signals are those driven by the host and output signals are those driven by the PC Card.6 Configurable Cards Certain memory and all peripheral cards may be configured by the system. 4.15 Card Configuration and see also TPCE_IF: Interface Description Field in the Metaformat Specification for the configuration entry tuple [CISTPL_CFTABLE_ENTRY].4. The CE1# input enables even numbered address bytes and CE2# enables odd numbered address bytes.) All signals are grouped under four classifications: I (Input). A multiplexing scheme based on A0 and CE1# allows 8-bit hosts to access all data on D[7::0] if desired. (#).1 Address BUS (A[25::0]) Signals A[25::0] are address bus input lines which enable direct address of up to 64 MB of memory on the card. I/O (Bi-directional). VOH min or above.) 4. During I/O word access cycles A0 must be negated. The system adjusts the card using the Function Configuration registers. The data path to I/O space is 8 or 16 bits.4. input signals.4. are asserted when the line is low. After a card is powered up.2 Data BUS (D[15::0]) Signals D[15::0] constitute the bi-directional data bus. (See 4. These are located in the card's Attribute Memory space. (See 4.) © 1999 PCMCIA/JEIDA 17 .) 4. respectively. 4. O (Output). at the location indicated in the card's Card Information Structure. Signal A0 is not used in memory word access mode.ELECTRICAL SPECIFICATION A custom interface is handled by the system and the card in a manner similar to an I/O and Memory interface. bit number (and significance) decrease to A0. V OH min or above. VOL max or below.3 Card Enable (CE[2::1]#) The CE[2::1]# lines are active low. This is to ensure that cards incompatible with the system. the system reads the card's Card Information Structure. and negated when low. 4. The most significant bit is D15. (See Table 4Ð7 Common Memory Write Function. if a compatible configuration is not available on the card. or rejected. or when power is removed from a card. If the card is found to support a custom interface also supported by the host socket.4 Signal Description Signal names followed by a pound sign. The data path to memory space is 16 bits.3. or with other cards installed in the system. Signal pins identified as RFU in all interface modes supported by a host system or PC Card shall have no connection at the host system or the card. and negated when the line is high. All other signals are asserted when high. Bit number (and significance) decrease downward to D0. the card and the socket may be configured to the custom interface mode. All pins identified as ground shall be connected to signal ground at the host. Signal A25 is the most significant bit. Both the socket and the card must use a Memory Only interface when a card is inserted. The card is configured using the Configuration Index field of the Configuration Option register. are either compatibly reconfigured. VOL max or below. Card Enable.15 Card Configuration.

) 4. A PC Card is permitted to process subsequent operations from the host while the READY signal is negated if its internal circuits allow proper operation. the WAIT# signal is available for that purpose. 4.) 4. and to access I/O. When independent.3 Pin Replacement Register.1 Common Memory Read Function and 4. READY signal shall be negated while any of the unrelated sources of the READY on the card require the blocking of certain host accesses and are indicating busy.16-BIT PC CARD ELECTRICAL INTERFACE To ensure data retention on battery backed-up SRAM cards. input signal used to gate Memory Read data from a memory card.4. It is not intended to delay the completion of a machine cycle at the PC Card interface or on the host's internal bus. It is the responsibility of the card or device vendor to communicate (through CIS descriptions or other means) those operations which are permitted to a card while the READY signal is negated . This line is also used for memory cards employing programmable memory technologies. The READY signal is negated while the card is busy processing a previous command or performing initialization. or used by the socket to generate an interrupt on the Busy-to-Ready transition or on both transitions.6 Ready (READY) The Ready function is provided by the READY signal when the card and the host socket are configured as a Memory Only interface. The signal READY is asserted when the PC Card is ready to accept a new data transfer command.) The READY signal is a status signal polled by the host. the Ready function is continuously in the ready condition.15. 18 ©1999 PCMCIA/JEIDA . Hosts must negate the OE# signal during write operations.4 Output Enable (OE#) The OE# line is an active low.4. When the Pin Replacement register is not implemented on a card configured for the I/O interface.4. or RESET signal negated (in systems which support the RESET signal).5 Write Enable (WE#) The WE# input signal is used for strobing Memory Write data into the memory card.13 I/O Function. (See also the Metaformat Specification. whichever event occurs latest. (See also 4. In the absence of any such knowledge. a minimum of 20 ms must elapse after: 1. and permit power-up initialization of peripheral cards. It is intended to indicate the completion of potentially lengthy operations within a PC Card.1. When a host socket and the card inserted into it are both configured for the I/O interface. (See also 4.6. 2. The READY line is negated by the PC Card to indicate that the PC Card circuits are busy and unable to accept some data transfer operations. The following descriptions of the READY signal apply equally to both the READY signal of the Memory Only interface and to the RREADY bit in the Pin Replacement register of a card configured for the I/O interface. the READY function is provided by the RREADY status bit in the card's Pin Replacement register. The Card Enables are used to access both Common and Attribute Memory. the application of VCC to the card. the host shall not attempt any access to the card while the READY signal is negated. unrelated sources for the READY signal are present on a PC Card. A group of related devices on the card and managed by the same host software shall be treated collectively as a single independent source of READY.

Following card wakeup the host must not access the card until a minimum of 10 µs has passed and the card's READY line is asserted. (See also 4.1 Interrupt Request Routing A general purpose host system should be able to route each card's interrupt request to any of the interrupt request levels used for installable devices within the system. A host system which has dedicated hardware and software may support only a subset of interrupt request levels necessary for the application. Note: a PCMCIA 1. A card that requires more than 20 ms for internal initialization before access shall negate READY until it is ready for initial access. Therefore.0 release required that cards containing battery backed-up SRAM not be accessed before 20 ms after stable power is applied. Driver software customization will be necessary to support I/O cards in a dedicated system environment. the card shall negate READY until the card is ready for operation.0 release system from presuming that the card is an uninitialized SRAM card. This will prevent the PCMCIA 1.0 / JEIDA 4. the card's READY line must be asserted before the initial access.) 4.7. If a card requires more than 10 µs following wakeup. If the card will require more than 10 µs to enter the sleep mode.1 release and later systems.) 4.7 Interrupt Request (IREQ#) [I/O and Memory Interface] Interrupt Request is asserted by an I/O Card to indicate to the host system that a PC Card device requires host software service. VCC is stable). When a card and its socket have been configured for the I/O interface. the READY signal will be negated within 10 µs after the power down bit in the Configuration and Status register is changed.0 release may access a card before the end of the initialization period. for PCMCIA 2. the READY signal will be negated within 10 µs of RESET or application of VCC to the card. or to return to operating condition following card wakeup.4. a period of time which is not to exceed five seconds following the time at which the RESET signal is negated (or if no RESET is implemented. it is recommended that during the initialization period the PC Card's Card Information Structure contain the correct card description. © 1999 PCMCIA/JEIDA 19 .0 / JEIDA 4.0 release system will never remove the reset condition (as RESET is not connected in such a system). In addition.ELECTRICAL SPECIFICATION The host must not access a card until a minimum of 20 ms has passed after VCC is stable.4. the READY status may be available in the Pin Replacement register and the signal is replaced on interface pin 16 with the IREQ# (Interrupt Request) signal. The Interrupt Request signal is available only when the card and the interface are configured for the I/O and Memory interface. If the card will not be initialized and ready for operations at the end of the 20 ms waiting period.7 Interrupt Request (IREQ#) [I/O and Memory Interface]. However. If that is not possible.4.0 / JEIDA 4. some systems otherwise conforming to the PCMCIA 1. then it should contain a valid CIS description of a null or ROM device. The interrupt signal at the interface is routed by the system to one of the interrupt request signals on the system's internal bus. The signal is negated when no interrupt is requested. and before the card is ready for operation. (See also the Metaformat Specification. and.0 / JEIDA 4.0 / JEIDA 4. after the RESET signal is negated. The PCMCIA 1.

2 Pulsed Mode Interrupt Signal A pulsed mode interrupt is asserted by placing a pulse on the interrupt line. Card Configuration. 4.16-BIT PC CARD ELECTRICAL INTERFACE Note: For PC compatible computers it is recommended that IREQ# from the card be able to be routed to at least the interrupt signals shown in Table 4Ð4 and Figure 4-1. for further information.4.4. The interrupt request signal is then held in the negated state.2. as well as in many non-PC-compatible systems. it is recommended that I/O cards support both of these modes. PC Cards must support the level interrupt request mode.2.4. Therefore.7.5 µs. Pulsed mode interrupts are generally utilized by systems using the "ISA" Personal Computer bus architecture in which interrupts are edge sensitive. through the Function Configuration registers. I/O cards designed to operate in a variety of machines should support both level and pulse mode interrupts. Table 4Ð4 IREQ# Interrupt Signals Function Communications 2 (COM2) Communications 1 (COM1) Fixed Disk Floppy Disk Parallel Port (LPT1) Network/Other AT IRQ IRQ3 IRQ4 IRQ14 IRQ6 IRQ7 IRQ10 XT IRQ IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Not Available Interrupt from Card Interrupt Select from System Personal Computer Block Diagram COM2 IRQ COM1 IRQ Fixed Disk IRQ Floppy Disk IRQ Parallel IRQ Network IRQ Figure 4-1 Recommended PC Compatible Interrupt Request Signals 4. 4.15. 20 ©1999 PCMCIA/JEIDA .1 Level Mode Interrupt Signal A level mode interrupt is asserted by placing the Interrupt Request signal in the asserted state until the interrupt has been serviced by the system. The pulse width must be at least 0.2 Level and Pulsed Mode Interrupt Support The Interrupt Request may be either a pulse or a level mode dependent upon the needs of the system. Refer to Section 4. level or pulsed. The host system selects the mode of interrupt. The level mode interrupt is standard in PC-compatible systems using the Micro Channel Architecture.7.7.

4. and the signal is replaced in the interface by the I/O Port is 16 bits (IOIS16#) signal.ELECTRICAL SPECIFICATION Note: The pulsed mode interrupt may be lost when more than one interrupting device shares an interrupt request signal at the system bus. Interrupt requests may be lost if they arrive at the system before a prior request on the shared interrupt request signal has been fully serviced. the pin will be connected to VCC. only data signals D[7::0] are valid and signals D[15::8] shall be ignored. (See 4. For example. If the Write Protect switch is present.11 Attribute Memory Select (REG#) When the REG# signal is asserted.4.10 I/O Is 16 Bit Port (IOIS16#) [I/O and Memory Interface] The IOIS16# output signal is asserted when the address at the socket corresponds to an I/O address to which the card responds. and if the card is permanently Write Protected. When a card or socket is configured for the I/O interface. The REG# signal is kept negated for all Common Memory accesses. and the I/O port addressed is capable of 16-bit access. (See Table 4Ð8 Attribute Memory Read Function. When this signal is not asserted during a 16-bit I/O access.4. the card will connect this line to GND or VCC depending on the condition of the card memory.8 Card Detect (CD[2::1]#) The CD[2::1]# signals provide for proper detection of PC Card insertion. The host socket interface circuitry shall provide 10 KΩ or larger pull-up resistors to VCC on each of these signal pins.e. The CD[2::1]# signals are connected to ground internally on the PC Card and will be forced low whenever a card is placed in a host socket. the WP signal will be asserted by the card when the switch is enabled. Signals CE[2::1]# and A0 are still valid. The signal pins are at opposite ends of the connector to ensure a valid detection (i. Failure to do so may cause electrical damage to PC Cards.) 4. Attribute Memory is also used to access standardized Function Configuration registers. 4. If the memory card has no Write Protect switch. the system will generate 8-bit references to the even and odd byte of the 16-bit port being accessed. but it is only possible to select even numbered addresses. Host sockets shall decode both CD[2::1]# pins when detecting PC Card presence. the Write Protect status may be available in the Pin Replacement register.. Systems which generate the IORD# and IOWR# strobe signals during DMA operations must keep REG# in © 1999 PCMCIA/JEIDA 21 .4. ensuring both sides of the card are firmly inserted). and negated when the switch is disabled.4. access is limited to Attribute Memory (OE# or WE# active) and to the I/O space (IORD# or IOWR# active).9 Write Protect (WP) [Memory Only Interface] The WP output signal is used to reflect the status of the PC Card's Write Protect switch. if the card can always be written to.) I/O space is used to access peripheral devices via the IORD# and IOWR# strobe signals. 4. Attribute Memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. 4. A combination of signals CE[2::1]# and A0 that requests an odd numbered byte will result in invalid data on the bus. The timing of Attribute Memory may be different than that of Common Memory. When Attribute Memory is accessed.10 I/O Is 16 Bit Port (IOIS16#) [I/O and Memory Interface]. and standard system and application software is used. the pin will be connected to GND.

When no audio signal is present.) 4. (See Table 4Ð20 Battery Voltage Detect. The Extended Status register upper four bits [7::4] are only included when the corresponding Extended Status register enable bits. The system mechanism used for BVD1 fail detection may be used to detect a change of status signals. A replacement warning condition is signaled by BVD1 asserted and BVD2 negated. the BVD1 signal is available on this pin. or if the card does not support the Binary Audio function. When the SigChg bit is true (set to 1). If BVD1 is negated.4.4. the lower four bits [3::0] have been set high (logic 1). 22 ©1999 PCMCIA/JEIDA .) 4. and CREADY Ñ in the Pin Replacement register and the upper four bits [7::4] in the optional Extended Status register. and the signal is negated when the Changed bit is false (reset to 0).3 Pin Replacement Register. The battery voltage status information may be available in the card's Pin Replacement register while the I/O interface is configured.14 Audio Digital Waveform (SPKR#) [I/O and Memory Interface]. the battery is no longer providing operational voltage. or Battery Voltage (BVD[2::1]) conditions or a change to a Ò1Ó state of bits [7::4] (when enabled by the respective Enable bit [3::0]) in the Extended Status register of the card while the I/O and Memory interface is configured. Therefore.) When the I/O and Memory interface is selected.(See also 4. Write Protect (WP). The signal to the speaker should be generated by taking the exclusive-OR function of the SPKR# signals from all those cards providing Binary Audio. with BVD2 either asserted or negated.13 Status Changed (STSCHG#) [I/O and Memory Interface] Status Changed (STSCHG#) is an optional signal used to alert the system to changes in the Ready (READY). the SPKR# signal shall be held negated.12 Battery Voltage Detect (BVD[2::1]) [Memory Only Interface] The signals BVD[2::1] are generated by the PC Card as an indication of the condition of its battery. respectively. The Changed bit is the logical OR result of the individual changed bits Ñ CBVD1. the BVD[2::1] signals are replaced at the interface by the card Status Changed (STSCHG#) and the Audio Digital Waveform (SPKR#) signals. CBVD2.) 4. (binary) audio wave form intended to drive the host's loudspeaker. and from the system speaker source. on-off. CWProt.4.14 Audio Digital Waveform (SPKR#) [I/O and Memory Interface] This Binary Audio signal is an optional signal which may be available only when the card and the socket have been configured for the I/O interface. (See 4.15.4. the Status Changed signal is asserted when the Changed bit in the Function Configuration and Status register is true (set to 1).4.5 DMA Signals Replacing I/O Interface Signals. It provides a single amplitude.16-BIT PC CARD ELECTRICAL INTERFACE a negated state during 16-bit PC Card DMA transfers to prevent spurious I/O accesses while a memory address is present on the address lines. The host system will use REG# as DMA acknowledge when the socket and PC Card are configured for 16-bit PC Card DMA I/O operations.13 Status Changed (STSCHG#) [I/O and Memory Interface] and 4. cards which are configured for I/O operation may continue to notify the system of changes of these status signals although the status signals no longer appear as independent signals on the card interface. Both signals are asserted while the battery is in good condition. While the card and socket are configured for the Memory Only interface. (See 4. STSCHG# is held negated if the function is not supported by the card or when the SigChg bit in the Configuration and Status register is false (reset to 0).

If only one of CD[2::1]# pins is asserted.4. This key will only allow the insertion of cards with the 5 V key.15. without software intervention. or card is not inserted correctly or completely. the BVD2 signal is available on this pin. If the appropriate program and peripheral voltage level voltage for a card cannot be determined.16 Voltage and Ground (VCC & GND) The VCC and GND input pins have been placed at symmetrical positions on the memory card. (See also the Metaformat Specification. 34.) Systems are required to be able to supply the VCC level on the VPP[2::1] pins.. the Card Services Specification. the voltage applied to the VPP[2::1] pins must not exceed VCC. the system may reject the card. A socket may be keyed with the Low Voltage key.1 Socket VCC for CIS Read A 5 V only socket shall be keyed with the 5 V key.ELECTRICAL SPECIFICATION PC Cards which supply the Binary Audio function are also required to support the Audio Enable bit in the Function Configuration and Status register. and treat the VS[2::1]# pins as valid when CD[2::1]# are both asserted. It is recommended that systems be able to supply at least the program and peripheral voltage level voltage of +12 V ±5% in addition to the VCC level. Two power pins (17 and 51) and four ground pins (1. before the next PC Card is inserted into the © 1999 PCMCIA/JEIDA 23 .15 Program and Peripheral Voltages (VPP[2::1]) The VPP[2::1] signals supply programming voltages for programmable memory operation. While the card and socket are configured for the Memory Only interface. The voltage applied to the VPP[2::1] pins of a card must never be greater than the program and peripheral voltage level appropriate for the card. and the Socket Services Specification. This key will allow the insertion of both 5 V keyed and Low Voltage keyed cards. 4. (See 4. For low power applications it is recommended that the system be able to apply a low logic level to VPP[2::1].16.) 4.15. When the program and peripheral voltage level required by a card is unavailable in a system. VPP[2::1] voltages are used on the card for Peripheral Card operation and for altering programmable memory on the card. (See 4.e. turn VCC off and switch signals to high impedance or 0 V to empty sockets). These pins are to be connected to the VCC voltage level until the Card Information Structure (CIS) of the card has been read and other permissible values for VPP[2::1] have been determined. Such a socket shall always apply initial VCC at 5 V and need not sense the VS[2::1]# signals. This allows the system to selectively enable or disable the audio function. Power to the card must be off and the card inputs not driven before the card is inserted. or additional supply voltages for peripheral cards.2 Configuration and Status Register. 35 and 68) are employed to reduce the impedance between the memory card and the system. 4.4. All Low Voltage keyed socket hardware shall ensure that voltages on VCC and VPP[2::1] are removed from the socket. the user may be notified that one of the following conditions exists: • • PC Card is of a type not supported by this socket.3 Pin Replacement Register.4. A socket capable of accepting a card with a Low Voltage key shall implement cold insertion (i.) It is recommended that systems support the Binary Audio function. Failure to require both CD[2::1]# pins to be asserted may result in falsely decoding a cardÕs VCC requirements.

If VS[2::1]# indicate a VCC value the socket is capable of providing. 4. The CIS on a PC Card shall be readable at all VCC levels indicated by the CIS and voltage sense pins. the host system must recognize that the card may have been replaced and repeat the entire power-up sequence.16-BIT PC CARD ELECTRICAL INTERFACE socket. Failure to do so can lead to falsely decoding the VCC requirements and signal protocol of PC Cards. care should be taken when dynamically changing the voltage applied to VCC or VPP[2::1] so that power supply shorts do not occur. (See Table 4Ð5 Vcc at Initial Power-Up and CIS Read. the card shall not be powered and the user may be notified.e.2 PC Card VCC for CIS Read Any PC Card capable of having CIS read at 5 V shall be keyed with the 5 V key. VS[2::1]# shall be implemented in the PC Card to indicate the values of VCC at which the PC Card CIS can be read.4. If any Card Detect pin is negated at any time.3 Changing PC Card VCC To change VCC. The host must recognize that the card will retain no knowledge of the power-up at the previous VCC and all configuration and other initialization must be done following the second power-up. the card inputs shall not be driven. 24 ©1999 PCMCIA/JEIDA . if the host system can provide both 5 V and 3.17 Voltage Sense (VS[2::1]#) The Voltage Sense signals are intended to notify the socket of the PC CardÕs CIS VCC requirement.. Further.3 V. the host system can change the card VCC to 5 V.4.) Any PC Card not capable of having CIS read at 5 V shall be keyed with the Low Voltage key. it must set both of them at high-impedance before final determination of a valid card insertion. If VS[2::1]# indicate no value of VCC the socket is capable of providing. the host system shall read the PC CardÕs Card Information Structure to determine the cardÕs characteristics. 4. it shall not apply a voltage other than indicated by the Voltage Sense pins (VS[2::1]#).) WA R N IN G The socket must not actively drive VS1# or VS2# when determining a valid card insertion (i. both CD1# and CD2# pins low). the card is powered at 3. If the socket hardware automatically applies power to a PC Card after insertion.16. the host shall direct the socket to discharge the PC Card connectorÕs VCC and VPP[2::1] to ground. and the cardÕs CIS indicates that the card can also operate at 5 V . Having applied the proper VCC.16. If a socket chooses to drive VS1# or VS2#.4. For example.) 4. (See Table 4Ð5 Vcc at Initial Power-Up and CIS Read and see also Table 4Ð19 Electrical Interface. the socket shall apply that VCC level to the PC Card. VS[2::1]# shall be implemented in the PC Card to indicate the values of VCC at which the PC Card CIS can be read.3 V VCC. (See Table 4Ð5 Vcc at Initial Power-Up and CIS Read. then power-up the card at the new voltage.

X 1 V 3.X V is less than 3.X 1 V or 3.Only 3.3 V available Low Voltage key .19 I/O Write (IOWR#) [I/O and Memory Interface] The IOWR# signal is made active to write data to the card's I/O space.3 V and 5 V available X.no 3.3 V. NC indicates no connection in the card.X 1 and 3.X 1 V Shall not be powered-up . 5 V available Low Voltage key .X V available Low Voltage key .X V available Low Voltage key X.3 V Shall not be powered-up . 4.X 1 V X.3 V and X.3 V available 5 V key 3.3 V X.Only X.X V available Low Voltage key . A PC Card will not respond to the IORD# signal until it has been configured for I/O operation by the system.user may be notified Shall not fit into socket X.3 V Low Voltage key 3. The REG# signal and at least one of CE[2::1]# must also be active for the I/O transfer to take place.3 V and 5 V CIS 1 ground ground 5 V key Low Voltage key .X. A PC Card will not respond to the IOWR# signal until it has been configured for I/O operation by the system. It also signals the beginning of any additional card initialization.20 Card Reset (RESET) The RESET signal clears the Configuration Option register thus placing a card in an unconfigured (Memory Only interface) state.user may be notified Shall not fit into socket X.4.X V available Low Voltage key .3 V available Low Voltage key .3 V and 5 V CIS ground NC 1 5 V key Low Voltage key .3 V available Low Voltage key .no 5 V available VCC at initial power-up and CIS read 5V 5V Shall not be powered-up . 4. 3.3 V.X.3.3. The system must place the RESET signal in a High-Z state during card power-up (including both VCC © 1999 PCMCIA/JEIDA 25 .3 V 5V X. The REG# signal and at least one of CE[2::1]# must also be active for the I/O transfer to take place.18 I/O Read (IORD#) [I/O and Memory Interface] The IORD# signal is made active to read data from the card's I/O space.3 V CIS ground ground 5 V key Low Voltage key .user may be notified 5V 3.4.3 V Shall not be powered-up .4. 3. 1.X V only CIS 1 NC 1 ground 5 V key Low Voltage key .X 1 V or 3.3 V 3.ELECTRICAL SPECIFICATION Table 4Ð5 VCC at Initial Power-Up and CIS Read Card Type 5 V key 5 V only CIS VS1# NC 1 VS2# NC 1 Socket Type 5 V key Low Voltage key .no 3.3 V or 5 V available Low Voltage key X.user may be notified Shall not fit into socket 3.X V available 5 V key X.no X.3 V 3.X V.5 V available Low Voltage key .X V.3 V only CIS ground NC 1 5 V key Low Voltage key .only 3.3. 4.Only X.3 V and 5 V available Low Voltage key .3.

or the RESET signal may be pulled up to VCC through a ≥100 Kê resistor on cards requiring reset.0 / JEIDA 4.16-BIT PC CARD ELECTRICAL INTERFACE turn-on and hot insertion). All configurable cards (including all I/O Cards) must monitor RESET and return to the unconfigured state when RESET is active. PC Cards requiring RESET must enter the unconfigured state each time power is applied.21 Extend Bus Cycle (WAIT#) The WAIT# signal is asserted by a PC Card to delay completion of the memory access or I/O access cycle then in progress. The signal must remain high impedance for at least 1 ms after VCC becomes valid. A PC Card asserts DREQ# to indicate to the host that it is requesting service. Note: In cases where a card is configured to respond to I/O read cycles at all addresses.4.5. INPACK# or IOIS16#.22 Input Port Acknowledge (INPACK#) [I/O and Memory Interface] The Input Acknowledge output signal is asserted when the PC Card is selected and can respond to an I/O read cycle at the address on the address bus. INPACK# or IOIS16#. 4. to be compliant with this specification. The PC Card asserts DREQ# until the host responds by asserting DACK. a PC Card socket supporting DMA operations must be able to receive DREQ# from a PC Card on any of the following three pins: SPKR#.5 DMA Signals Replacing I/O Interface Signals 4. RESET must not be connected between PC Cards unless all PC Cards are reset when any card has VCC power removed. This signal must be inactive until the card is configured. 26 ©1999 PCMCIA/JEIDA . Socket implementations which do not support all three pins for DREQ# are not compliant with this specification's requirements for DMA operations. For example: 1. and the card is reset (continuously) when placed into a PCMCIA 1.) PC Cards and sockets are not required to support DMA operations.1 DMA Request (DREQ#) The DMA Request signal is only available when a PC Card and socket are configured for DMA operations. A PC Card may use any one of the following three pins for DREQ#: SPKR#. This ensures that when a card is inserted into a socket it is reset before the signal pins make contact with the socket. This signal is used by the host to control the enable of any input data buffer between the card and the host system data bus. A PC Card indicates the pin used for DREQ# in the Miscellaneous Features Field of the selected card configuration. However.0 release compatible socket. 4. the card may generate a power-on RESET internally.4. 4. the INPACK# signal may be asserted whenever the Card Enable (CE[2::1]#) inputs are asserted. (See also the Metaformat Specification and the Card Services Specification. A card remains in the unconfigured state until the Configuration Option register has been written with a valid configuration. 2.

1 Common Memory Read Function for PC Cards A memory card can be configured with different types of memory devices (such as SRAM. Byte Access mode is enabled (8-bit transfers). During Word mode. the Read function shares common signal state sequencing.4 DMA Write (IORD#) The host asserts IORD# to read data from a PC Card's I/O space. however. 4. The selection of an even byte or an odd byte is controlled by A0.5. © 1999 PCMCIA/JEIDA 27 . the signal REG# shall be kept inactive. 4. To access Common Memory. both CE1# and CE2# are asserted.5. 4. Signals CE[2::1]# control the activation of the Memory Card and A0 control byte ordering on the data bus lines D[15::0]. When either CE[2::1]# become asserted.ELECTRICAL SPECIFICATION 4. To respond to DMA read requests. 4. 4. and the even-byte data and odd-byte data outputs are valid in data bus lines D[15::0].5. When using word access (16-bit transfers).1. the PC Card must be configured for I/O and DMA operations. A0 is ignored.6.1 Common Memory Function This section describes the functions of the Common Memory area. (See Table 4Ð6 Common Memory Read Function. The host signals terminal count for DMA write operations by asserting OE#. Both the even byte data and odd byte data outputs will be valid in data bus lines D[7::0]. the PC Card must be configured for I/O and DMA operations.5 Terminal Count (TC#) The host signals terminal count for DMA read operations by asserting WE#. MaskROM.). The DMA Acknowledge signal is only available when the PC Card and the socket are configured for DMA operations. the card is in standby mode.6. the memory card is activated and ready for data transfers. During DMA write operations the host asserts DACK and IORD# to transfer data from a PC Card to system memory.2 DMA Acknowledge (DACK) [replaces REG#] A DMA operation is indicated when DACK is active and either IORD# or IOWR# is active.5. When CE1# is active and CE2# is not active. To respond to DMA write requests.) When both CE[2::1]# are inactive. The host asserts DACK during all DMA operations. During DMA read operations the host asserts DACK and IOWR# to transfer data from system memory to a PC Card. and the signal OE# shall be active during the Read cycle.6 Memory Function 4.3 DMA Read (IOWR#) The host asserts IOWR# to write data to a PC Card's I/O space. The host uses REG# for DACK. DACK is not asserted for non-DMA I/O operations. etc.

However.4. Table 4Ð7 Common Memory Write Function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd Byte Only Access REG# X H H H H CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X H H H H WE# X L L L L VPP2 VCC 1 VCC 1 VPP1 VCC 1 VCC 1 D[15::8] X X X Odd-Byte Odd-Byte D[7::0] X Even-Byte Odd-Byte Even-Byte X VCC 1 VCC 1 VCC 1 VCC 1 VCC 1 VCC 1 X indicates any value. During Write mode. signal OE# must be negated. and Odd-Byte-Only access. and does not require a large address space. 1.16-BIT PC CARD ELECTRICAL INTERFACE Odd-Byte-Only access is enabled when CE1# is negated and CE2# asserted.15 Program and Peripheral Voltages (Vpp[2::1]). 28 ©1999 PCMCIA/JEIDA . 1. (See 4.) 4.2 Common Memory Write Function for PC Cards During Write mode.15 Program and Peripheral Voltages (Vpp[2::1]). Refer to the JEDIC ID information for CIS information. A memory card can perform Write operations in three modes: Byte access. no voltage level other than VCC may be applied to the VPP[2::1] pins until a card has been identified as supporting alternate program and peripheral voltage levels by reading its Card Information Structure. and signal WE# is asserted. the function of signals REG#. 4. Word access. Additional VPP[2::1] values for Read Function are permitted when cards use VPP[2::1] voltages as additional power supply levels rather than only for programmable memory. EPROM and Flash Memory OTPROM. EPROM and Flash Memory devices may have additional requirements. (See 4.3 Common Memory Write Function for OTPROM. Table 4Ð6 Common Memory Read Function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd-Byte-Only Access X indicates any value. only data lines D[15::8] contain valid data. However. and A0 is ignored.1.6. no voltage level other than VCC may be applied to the VPP[2::1] pins until a card has been identified as supporting alternate program and peripheral voltage levels by reading its Card Information Structure. CE[2::1]# and A0 are the same as in the Read mode.6. Additional VPP[2::1] values for Write Function are permitted when cards use VPP[2::1] voltages as additional power supply levels rather than only for programmable memory.6. During Odd-Byte-Only access. Attribute Memory is limited to 8-bit wide access for economic reasons.1.4.) REG# X H H H H CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X L L L L WE# X H H H H VPP2 VCC 1 VCC VCC 1 VPP1 VCC 1 VCC VCC 1 D[15::8] High-Z High-Z High-Z Odd-Byte Odd-Byte D[7::0] High-Z Even-Byte Odd-Byte Even-Byte High-Z VCC 1 1 VCC 1 1 VCC 1 VCC 1 4.2 Attribute Memory Function Attribute Memory is an optional space intended for storing PC Card identification and configuration information.

However.2.6.15 Program and Peripheral Voltages (Vpp[2::1]).6. 1.4.4.) 4. EPROM and Flash Memory OTPROM. but only even byte data is valid during the Attribute Memory Read function. no voltage level other than VCC may be applied to the VPP[2::1] pins until a card has been identified as supporting alternate program and peripheral voltage levels by reading its Card Information Structure. Refer to the JEDIC ID information for CIS information.2. (See 4. Additional VPP[2::1] values for Read Function are permitted when cards use VPP[2::1] voltages as additional power supply levels rather than only for programmable memory. (See 4.6. As in the Common Memory Read function.2. Table 4Ð8 Attribute Memory Read Function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd Byte Only Access REG# X L L L L CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X L L L L WE# X H H H H VPP2 VCC 1 VCC VCC 1 VPP1 VCC 1 VCC VCC 1 D[15::8] High-Z High-Z High-Z Not Valid Not Valid D[7::0] High-Z Even-Byte Not Valid Even-Byte High-Z VCC 1 1 VCC 1 1 VCC 1 VCC 1 X indicates any value. signals REG# and WE# must be kept asserted for the entire cycle while the signal OE# is negated for the entire cycle. EPROM and Flash Memory devices may have additional requirements. Table 4Ð9 Attribute Memory Write Function Function Mode Standby Mode Byte Access (8 bits) Word Access (16 bits) Odd Byte Only Access REG# X L L L L CE2# H H H L L CE1# H L L L H A0 X L H X X OE# X H H H H WE# X L L L L VPP2 VCC 1 VCC 1 VPP1 VCC 1 VCC 1 D[15::8] X X X X X D[7::0] X Even-Byte X Even-Byte X VCC 1 VCC 1 VCC 1 VCC 1 VCC 1 VCC 1 X indicates any value.) 4. signals REG# and OE# must be active during the read cycle.2 Attribute Memory Write Function While writing to Attribute Memory. However.3 Attribute Memory Write Function for Dual Supply OTPROM. © 1999 PCMCIA/JEIDA 29 .15 Program and Peripheral Voltages (Vpp[2::1]). Additional VPP[2::1] values for Write Function are permitted when cards use VPP[2::1] voltages as additional power supply levels rather than only for programmable memory. the signals CE[2::1]# control the even byte and odd byte address. 1. no voltage level other than VCC may be applied to the VPP[2::1] pins until a card has been identified as supporting alternate program and peripheral voltage levels by reading its Card Information Structure.1 Attribute Memory Read Function For the Attribute Memory Read function.ELECTRICAL SPECIFICATION 4.

The remaining devices follow the WP signal.6. The remaining devices follow the WP signal and are therefore always write enabled. SRAM.7. Optionally the CIS may specify all devices as never write enabled. and within a memory card. No WP Information Needed .Memory follows WP signal which is always negated (Disabled). The remaining devices follow the WP signal. Never Write Enabled None High Switch Controlled Enabled Disabled High Low Low Always/Never None CIS must specify devices (addresses) which ignore the WP signal and are never write enabled.3 Write Protect Function The following table describes the Write Protection options and corresponding Write Protect (WP) switch and signal states. etc. OTPROM. (See also the Metaformat Specification.1 Common Memory Read Timing There are several types of memory cards. CIS must specify devices (addresses) which ignore the WP signal and are always write enabled.Memory folllows WP signal. To maintain compatibility among several types of memory devices. CIS must specify devices (addresses) which ignore the WP signal and are never write enabled.7 Timing Functions This section describes Common and Attribute Memory Access Timing.16-BIT PC CARD ELECTRICAL INTERFACE 4.) Table 4Ð10 Write Protect Function Memory Write Protect Combinations on Card Always Write Enabled WP Switch None WP Signal Low Minimum Card Information Contents Related to Write Protect No WP Information Needed . 4. The remaining devices follow the WP signal. read timing specifications are common.Memory follows WP signal which is always High (Enabled).. CIS must specify both devices (addresses) which ignore the WP signal and are always write enabled as well as the devices which ignore the WP signal and are never write enabled. 30 ©1999 PCMCIA/JEIDA . Optionally the CIS may specify all devices as always write enabled. Always/Switch Enabled Disabled High Low High Low High Never/Switch Enabled Disabled Always/Never/Switch Enabled Diabled Low 4. No WP Information Needed . several types of memory devices may be mounted.

3. 5. All other parameters are identical. The REG# signal timing is identical to address signal timing. These timings are specified for hosts and cards which support the WAIT# signal.ELECTRICAL SPECIFICATION Table 4Ð11 Common Memory Read Timing Specification for all Types of Memory Speed Version Item Read Cycle Time Address Access Time 4 600 ns 1. 7. These timings specified only when WAIT# is asserted within the cycle. 6. 4. All other parameters are identical.3 V timing for cycles >600 ns are equal to value given + (cycle time-600).3 V operating voltage. Skews and delays from the system driver/receiver to the PC Card must be accounted for by the system. All timings measured at the PC Card.2 Symbol tcR ta(A) ta (CE) ta(OE) tdis(OE) ten(CE) tv(A) tsu(A) th(A) 5 250 ns 3 Min 250 5 Max 200 ns Min 200 Max 150 ns Min 150 Max 100 ns Min 100 Max IEEE Symbol t AVAV t AVQV t ELQV t GLQV t GHQZ t ELQNZ t AXQX t AVGL t GHAX t ELGL t GHEH t GLWTV t WTLWTH t QVWTH Min 600 2 Max 600 600 300 2 2 2 250 250 125 3 3 3 200 200 100 90 5 0 20 20 0 20 5 0 20 20 0 20 35 12 µs 0 0 150 150 75 75 5 0 10 15 0 15 35 12 µs 0 100 100 50 50 Card Enable Access Time Output Enable Access Time Output Disable Time from OE# Output Enable Time from CE# Data Valid from Add Change 4 Address Setup Time 5 Address Hold Time 5 150 5 0 100 35 0 35 100 12 µs 0 0 5 0 30 20 0 20 100 Card Enable Setup Time Card Enable Hold Time WAIT# Valid from OE# WAIT# Pulse Width 6 5 5 tsu(CE) th(CE) tv(WT-OE) tw (WT) tv WT) 35 12 µs 35 12 µs Data Setup for WAIT# Released 6 1. 600 ns cycle times apply for 3. 2. 5 V timing for cycles >250 ns are equal to value given + (cycle time-250). 3. © 1999 PCMCIA/JEIDA 31 .

2 Common and Attribute Memory Write Timing The write timing specifications for Common and Attribute memory are the same. 2. These timings specified only when WAIT# is asserted within the cycle. These timings are specified for hosts and cards which support the WAIT# signal. 5 V timing for cycles >250 ns are equal to value given + (cycle time-250). 32 ©1999 PCMCIA/JEIDA . 3. 3. 6.3 V timing for cycles >600 ns are equal to value given + (cycle time-600).2 Symbol tc W tw(WE) tsu(A) tsu(A-WEH) tsu(CE-WEH) t(D-WEH) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE) tsu(OE-WE) th(OE-WE) tsu(CE) th(CE) tv(WT-WE) tw (WT) tv(WT) IEEE Symbol t AVAV t WLWH t AVWL t AVWH t ELWH t DVWH t WMDX t WMAX t WLQZ t GHQZ t WHQNZ t GLQNZ t GHWL t WHGL t ELWL t GHEH t WLWTV t WTLWTH t WTHWH 0 5 5 35 35 0 35 100 12 µs Min 600 2 300 50 350 2 2 250 ns 3 Min 250 3 150 30 180 3 3 200 ns Min 200 120 20 140 140 60 30 30 Max 150 ns Min 150 80 20 100 100 50 20 20 Max 100 ns Min 100 60 10 70 70 40 15 15 Max Max Max 300 2 150 2 70 70 150 150 180 3 80 3 30 30 100 100 5 5 10 10 0 20 35 12 µs 0 90 90 5 5 10 10 0 20 35 12 µs 0 0 5 5 10 10 0 20 75 75 5 5 10 10 0 15 35 12 µs 0 50 50 35 12 µs 600 ns cycle times apply for 3. Table 4Ð12 Common and Attribute Memory Write Timing Specifications Speed Version Item Write Cycle Time Write Pulse Width Address Setup Time Address Setup Time for WE# 4 Card Enable Setup Time for WE# Data Setup Time for WE# Data Hold Time Write Recover Time Output Disable Time from WE# Output Disable Time from OE# Output Enable Time from WE# Output Enable Time from OE# Output Enable Setup from WE# Output Enable Hold from WE# Card Enable Setup Time 5 Card Enable Hold Time 5 WAIT# Valid from WE# 5 WAIT# Pulse Width 6 WE# High from WAIT# Released 6 1. 7. All other parameters are identical. 4.7. All other parameters are identical. Skews and delays from the system driver/receiver to the PC Card must be accounted for by the system. All timings measured at the PC Card. 5.16-BIT PC CARD ELECTRICAL INTERFACE 4.3 V operating voltage. 4 600 ns 1. The REG# signal timing is identical to address signal timing.

Detailing timing specifications are shown below.1 Common Memory Write Timing The programming specification of various memory devices are not standardized.4 Attribute Memory Write Timing Specification In the absence of other information. 4.7.7. it is not practical to set standardized programming specifications for these memory devices.3 V VCC. programming specifications may vary among different generations of the same device.3 V operation. 4. 2. Attribute Memory Write timing shall be 250 ns SRAM timing for 5 V operation and 600 ns timing for 3.2. Consequently.7.3 Attribute Memory Read Timing Specification The Attribute MemoryÕs access time is defined as 300 ns at 5 V VCC or 600 ns at 3. Moreover.ELECTRICAL SPECIFICATION 4. Table 4Ð13 Attribute Memory Read Timing Specification for all types of Memory Speed Version Item Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from OE# Output Enable Time from OE# Data Valid from Add Change Address Setup Time Address Hold Time 1 1 1 Symbol tcR ta (A) ta (CE) ta (OE) tdis (OE) ten (OE) tv (A) tsu (A) th (A) tsu (CE) th (CE) tv (WT-OE) tw (WT) 2 IEEE Symbol t AVAV t AVQV t ELQV t GLQV t GHQZ t GLQNZ t AXQX t AVGL t GHAX t ELGL t GHEH t GLWTV t WTLWTH t QVWTH 300 ns Min Max 300 300 300 150 100 5 0 30 20 0 20 35 12 us 0 600 ns Min Max 600 600 600 300 150 5 0 100 35 0 35 100 12 us 0 Card Enable Setup Time Card Enable Hold Time WAIT# Valid from OE WAIT# Pulse Width 2 1 1 Data Setup for WAIT# Released 1. tv (WT) These timing are specified for hosts and PC Cards which support the WAIT# signal. © 1999 PCMCIA/JEIDA 33 . These timings specified only when WAIT# is asserted within the cycle.

7.5 Memory Timing Diagrams 34 ©1999 PCMCIA/JEIDA .16-BIT PC CARD ELECTRICAL INTERFACE 4.

ELECTRICAL SPECIFICATION tc(R) ((t A) 2) a © 1999 PCMCIA/JEIDA th(A) 35 .

During a DMA write. Applies to card only when WAIT# is negated by card. 2. When the data I/O pin is in the output state. Minimum write pulse width must be met whether or not WAIT# is asserted by card. 3. The movement of one byte or word of data during a DMA operation. Applies only when WAIT# is asserted by card. DMA operations are described with respect to system memory access. data is transferred from system memory to PC Card I/O space. May be high or low for write timing. Figure 4-2 Read Timing Diagram tcW A[25::0]. is termed a bus cycle. 3. data is transferred from PC Card I/O space to system memory. Shaded areas may be high or low. REG# tsu(CE-WEH) CE# NOTE 1 tsu(CE) tsu(A-WEH) th(CE) NOTE 1 OE# NOTE 4 tsu(A) tw(WE) NOTE 4 trec(WE) WE# NOTE 3 tv(WT-WE) tv(WT) WAIT# tsu(OE-WE) tw(WT) th(OE-WE) tsu(D-WEH) th(D) D[15::0](Din) NOTE 2 DATA INPUT ESTABLISHED tdis(WE) tdis(OE) ten(OE) ten(WE) D[15::0](Dout) 1. the host shall always provide at least this access time before sampling data. 36 ©1999 PCMCIA/JEIDA . Figure 4-3 Write Timing Diagram 4. However.16-BIT PC CARD ELECTRICAL INTERFACE 1. During a DMA read.8 DMA Function This section describes DMA transfer cycles for PC Cards and sockets capable of DMA operations. Several bus cycles make up a DMA transaction. 2. but restrictions on OE# from previous figures apply. no signals shall be applied to the data pins (D[15::0] by the host system. Shaded areas may be high or low. 4. Address lines to the PC Card are ignored during DMA operations.

When the DMA transfer is complete. 4. H L L L X H TC# H L HIGH BYTE DACK X H DREQ# 1 X L CE2# H H CE1# H L A[25::0] X X OE# X H WE# X TC# IORD# X H IOWR# X L D[15::8] X X D[7::0] X BYTE DATA LOW BYTE PC Cards signal DREQ# using one of the following three (3) pins: SPKR#. INPACK# or IOIS16#. the DACK (REG#) signal is used to distinguish between a DMA cycle and a normal I/O cycle. Table 4Ð14 DMA Read (Memory Read .2 DMA Read Timing (Memory Read .I/O Write) Function Standby mode Byte Access (8-bit) Word Access 1.8. the REG# signal is asserted for the complete bus cycle. the host asserts TC#(WE#) during the last bus cycle of the DMA transaction.1 DMA Read Function (Memory Read .I/O Write) td DREQ (DACK) th DREQ (DACK) DREQ# tsu DA(IOWR) DACK (REG#) tsu CE (IOWR) CE# tw (IOWR) IOWR# th CE (IOWR) td DREQ (IOWR) th DA (IOWR) td (IOWR) th (IOWR) D[15::0] tsu (TC) TC# (WE#) tw (TC) th (TC) Figure 4-4 DMA Read Timing Diagram © 1999 PCMCIA/JEIDA 37 .I/O Write) A PC Card requests a DMA read operation by asserting DREQ#. 4. For a normal I/O cycle.ELECTRICAL SPECIFICATION When a PC Card and socket are configured for DMA operations. the REG# signal is negated during the entire DMA bus cycle. The host asserts DACK during the entire DMA bus cycle. For a DMA transfer cycle. The host asserts IOWR# to transfer data.8. The host responds by asserting DACK.

H L L L X TC# H L H HIGH BYTE DACK X H DREQ# 1 X L CE2# H H CE1# H L A[25::0] X X OE# X TC# WE# X H IORD# X L IOWR# X H D[15::8] X X D[7::0] X BYTE DATA LOW BYTE PC Cards signal DREQ# using one of the following three (3) pins: SPKR#. DACK is held high by the host during the entire DMA bus cycle.Memory Write) A PC Card requests a DMA cycle by asserting DREQ#.3 DMA Write Function (I/O Read .000 4. the host acknowledges the request by beginning the DMA cycle.Memory Write) Function Standby mode Byte Access (8-bit) Word Access 1.16-BIT PC CARD ELECTRICAL INTERFACE Table 4Ð15 DMA Read Timing Parameters Item DREQ# active to DACK active DREQ# hold from DACK active DREQ# inactive to IOWR# inactive Data setup to IOWR# inactive Data hold from IOWR# inactive IOWR# Width DACK setup to IOWR# active DACK hold from IOWR# inactive CE# setup to IOWR# active CE# hold from IOWR# inactive IOWR# active to TC# active TC# Width TC# inactive to IOWR# inactive All timing in ns.8. The host asserts IORD# to transfer data. the host asserts TC#(OE#) during the last bus cycle of the DMA transaction. 38 ©1999 PCMCIA/JEIDA . Table 4Ð16 DMA Write (I/O Read . When the DMA transfer is complete. INPACK# or IOIS16#. If the PC Card is granted the DMA request. Symbol td DREQ (DACK) th DREQ (DACK) td DREQ (IOWR) td(IOWR) th(IOWR) tw(IOWR) tsu DA (IOWR) th DA (IOWR) tsu CE (IOWR) th CE (IOWR) tsu (TC) tw (TC) th (TC) 0 0 100 30 165 5 5 5 20 10 40 10 IEEE Min Max 10.

Memory Write) td DREQ (DACK) th DREQ (DACK) DREQ# tsu DA(IORD) DACK (REG#) tsu CE (IORD) CE# tw (IORD) IORD# th CE (IORD) td DREQ (IORD) th DA (IORD) td (IORD) th (IORD) D[15::0] tsu (TC) TC# (OE#) tw (TC) th (TC) Figure 4-5 DMA Write Timing Diagram Table 4Ð17 DMA Write Timing Parameters Item DREQ# active to DACK active DREQ# hold from DACK active DREQ# inactive to IORD# inactive Data Delay from IORD# active Data hold from IORD# inactive IORD# Width DACK setup to IORD# active DACK hold from IORD# inactive CE# setup to IORD# active CE# hold from IORD# inactive IORD# active to TC# active TC# Width TC# inactive to IORD# inactive All timing in ns.8. Symbol td DREQ (DACK) th DREQ (DACK) td DREQ (IORD) td(IORD) th(IORD) tw(IORD) tsu DA (IORD) th DA (IORD) tsu CE (IORD) th CE (IORD) tsu (TC) tw (TC) th (TC) 0 165 5 5 5 20 10 40 10 0 0 100 IEEE Min Max 10.ELECTRICAL SPECIFICATION 4.000 © 1999 PCMCIA/JEIDA 39 .4 DMA Write Timing (I/O Read .

3 V ± 0.25 V 0. This table is for reference only.3 V PC Card logic levels shall be per JEDEC 8-1A.8 V 1 Card TTL or CMOS TTL or CMOS TTL or CMOS TTL or CMOS TTL or CMOS TTL or CMOS TTL or CMOS 0.8 V VCC 0. The 5 V PC Card logic levels shall be per JEDEC 7.5 V (0.3 V ± 0.16-BIT PC CARD ELECTRICAL INTERFACE 4.3 V 2.3 V VCC = 3.1 Signal Interface Electrical specifications must be maintained to ensure data reliability.3 V ± 0.9 Electrical Interface 4.) Table 4Ð18 PC Card Logic Levels DC Levels Parameter VIH VIL VOH VOL VIH VIL VOH VOL Conditions VCC = 5 V ± 5% VCC = 5 V ± 5% VCC = 5 V ± 5% VCC = 5 V ± 5% VCC = 3.0 V -0. For CMOS loads.9 VCC) 0.1 VCC) VCC + 0.3 V Min 2.9. 40 ©1999 PCMCIA/JEIDA .0 V 2.3 V 0.0 V 2.4 V (VCC . (See Table 4Ð18 PC Card Logic Levels.3 V VCC = 3. 1.2 V) 1 1 1 Host Max VCC + 0.4 V 0.3 V VCC = 3. The 3.0.3 V ± 0.2 V) TTL or CMOS Note: All logic levels per JEDEC 7 and 8Ð1A.4 V (0.8 V (0.

Control Signals: Each card shall present a load to the socket no larger than 50 pF at a DC current of 700 µA low state and 150 µA high state. Address bit A0 is ignored when the card is asserted in word access mode.6 mA low state and 300 µA high state. BVD2 was not defined in the JEIDA 3. The socket shall be able to drive at least the following load while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC current 700 µA low state and 150 µA high state per socket). Data Signals: The host and each card shall present a load no larger than 50 pF at a DC current 450 µA low state and 150 µA high state. Status Signals: The socket shall present a load to the card no larger than 50 pF at a DC current of 400 µA low state and 100 µA high state. The card shall be able to drive at least the following load while meeting all AC timing requirements: 50 pF at a DC current of 400 µA low state and 100 µA high state.9. The host and each card shall be able to drive at least the following load while meeting all AC timing requirements: 100 pF with DC current 1. The host shall be able to drive at least the following load while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by ( 100 pF with DC current 450 µA low state and 150 µA high state per socket). 3. 4. However. 2. Address Signals: Each card shall present a load of no more than 100 pF at a DC current of 450A µA low state and 150 µA high state. The PC Card's external address bus is comprised of A[25::0] with A0 being the LSB and A25 the MSB. Minimum memory unit is 16 KBytes Memory address starts from 00H Memory units exist continuously. 4. 5. This permits the host to wire two sockets in parallel without derating the card access speeds. Systems fully supporting JEIDA release 3 SRAM cards must pull-up pin 62 (BVD2) to avoid sensing their batteries as "Low". Resistor is optional. 3 pull-up to VCC R _ 10 KΩ *3 pull-up to VCC R _ 100 KΩ *3 pull-up to VCC R _ 10 KΩ 4 Host Card Output Format Address Data Bus Card Detect Voltage Sense Battery/Detect * 1. 3. including pull-up resistor. pull-up to VCC R _ 10 KΩ pull-up to VCC 10 KΩ ≤ R ≤ 100 KΩ pull-up 1 asserted or negated Card pull-up to VCC R _ 10 KΩ and must be sufficient to keep inputs inactive when the pins are not connected at the host. including pull-up resistor.ELECTRICAL SPECIFICATION Table 4Ð19 Electrical Interface Item Control Signal Signal CE1# CE2# REG# IORD# IOWR# OE# WE# RESET Status Signal READY INPACK# WAIT# WP A[25::0] D[15::0] CD[2::1]# VS1# VS2# BVD[2::1] pull-down R _ 100 KΩ * 5 pull-down R _ 100 KΩ * 2 connected to GND in the card See Table 4Ð5 Vcc at Initial Power-Up and CIS Read. a set of Function Configuration Registers (consisting of four 16-bit Address Extension Registers or the Configuration Option Register) provides the means for an extended PC Card memory space containing as many as 242 PC Card Common Memory locations. 2. In the case of SRAM without Attribute Memory. address decoding is required as follows: 1.2 Memory Address Decoding The 26 address signals at the PC Card connector can directly address only 64 MBytes of memory.0 release. © 1999 PCMCIA/JEIDA 41 .

9. The types of I/O address decoding performed by the card. The location of the Independent I/O Address Window for each PC Card socket may be fixed permanently.1 Function Configuration Registers Address Decoding PC Cards that can be configured by the system. it is recommended that the system reserve 128 contiguous bytes of its I/O space. The Function Configuration registers are a set of numbered. a card will not respond to any I/O read or I/O write cycles until it has been configured.14 Function Configuration and 4. For each PC Card socket. The system must include a software method permitting driver software (or application software.16-BIT PC CARD ELECTRICAL INTERFACE 4. the system must reserve a minimum of 8 contiguous bytes of its I/O address space starting at a Base Address with A0 through A2 all zero. To select a particular card configuration.15 Card Configuration. 4.) In order to be able to accommodate cards which require a higher number of I/O ports.3 I/O Address Space Decoding During I/O operations. contain Function Configuration registers located in the Attribute Memory space.9. the system writes the index number of one table entry into the Function Configuration Index field of the Configuration Option register. the card may permit the system to choose from a selection of addresses to which the card can respond. the Card Services Specification and the Metaformat Specification. Note: This should not be interpreted as preventing a system from actually allocating a smaller or discontiguous space to a particular I/O card whose I/O space requires such configuration.2. Whether a Function Configuration register number N is present on the card or not. and immediately following a card reset. 8-bit registers. These registers are addressed at consecutive even-byte addresses starting at the Base Address indicated in the Configuration Tuple. multi-function cards and game cards. (See also 4. including cards which support I/O and those which exceed nominal system requirements. if I/O is permitted from applications) to determine a card's I/O space Base Address. such as LAN. PC Cards which implement I/O functions may use either an Independent or Overlapping Window or permit selecting between the two methods.9. 42 ©1999 PCMCIA/JEIDA . (See also 4. When the Overlapping window method is used by the card.1 Independent I/O Address Window Independent I/O Address windows for PC Cards provide a straightforward mechanism for I/O space allocation among PC Cards and other system resources installed in the system. The window must begin exactly on an 8-byte boundary. Also with this method.) 4. are described in the Card Configuration Table located within the Card Information Structure.3. the I/O address spaces of each PC Card may be either Independent or Overlapping. as well as the specific range of addresses to which the card will respond (in Overlapping I/O Window mode). Each system must be able to allocate to each card an independent I/O address window of at least 8 bytes of contiguous address space. or may be allocated when an I/O card is detected in the socket. the location of the register is always given by: Base Address + 2 * N. An Overlapping I/O address window is a portion of the system's I/O space which is assigned to any combination of PC Cards and other system resources. standardized.15 Card Configuration. The method can be applied to systems which permit I/O drivers to determine the card's I/O port assignment at execution time. VGA. the card responds to only a limited number of the I/O addresses in the window. During a card reset. An Independent I/O address window is a portion of the system's I/O space which is assigned solely to a single PC Card and not shared with any other system resource.

and may be located anywhere in the I/O space of the system. If the addresses conflict. The expansion cards individually determine to which addresses within that range they will respond. When two identical cards are installed in the system.15 Card Configuration. (See also 4. that no address conflicts will occur. 4. The system assigns the same block(s) of its I/O space to each PC Card using the Overlapping I/O Address Window. during installation. on the expansion card. and the addresses used by other system resources. They rely upon the system to provide sufficient address decoding to prevent conflicts with other installed devices.9. A PC Card may allow operation at several alternative sets of addresses. Each EISA card slot is uniquely assigned the first 256 bytes of a corresponding 1 KByte of I/O space. This mechanism relies on the cards and system resources having non-overlapping subsets of addresses to which they respond. Other resources in the system may also use portions of the block. An example of this concept is used in the EISA bus. Each card and system resource is responsible for decoding addresses within the block and responding to I/O only within a unique subset of those addresses. A service technician is responsible for ensuring. the new card may be gracefully rejected by the system. and those having existing drivers which do not take advantage of execution time binding of I/O addresses. the addresses used by the card must be compared with the addresses used by other installed PC Cards.3. or jumpers. The specific set of addresses is often set by configuration switches. When each PC Card is installed in a system that uses an Overlapping I/O Address Window. In these systems all expansion slots are selected during I/O accesses to the last 768 bytes of each 1 KByte of I/O space.2 Overlapping I/O Address Window The Overlapping I/O Address Window is provided for those systems whose I/O drivers have their I/O addresses bound before execution time. © 1999 PCMCIA/JEIDA 43 . This includes both systems for which execution time binding is not possible. The host selects the desired alternative from the Card Configuration Table and informs the card by writing the configuration entry of the selected entry to the Function Configuration registers.) A desktop personal computer example of Overlapping I/O Address Windows occurs in both ISA and EISA bus-based computers. they automatically reside at different addresses.ELECTRICAL SPECIFICATION Cards which use the Independent I/O Address Window need decode only enough address lines to distinguish among the I/O ports actually implemented on the card.

A Memory card compares the battery voltage with the reference voltages. Battery is not providing operational voltage. A pull-up resistor must be connected to CD[2::1]# on the system side. BVD[2::1]. Battery is not providing operational voltage.10 Card Detect PC Cards provide a means of allowing the system to detect card insertion and removal.16-BIT PC CARD ELECTRICAL INTERFACE 4. Vcc R ≥ 10K Ω A Vcc CD1# R ≥ 10K Ω B CD2# Host System PC Card Figure 4-6 Card Detect 4. 44 ©1999 PCMCIA/JEIDA . A Memory card contains one or two voltage comparators and one or two reference voltages.11 Battery Voltage Detect It is critical for the system's data integrity to be able to determine the status of the on-card battery. COMMENT If BVD2 is not supported. Signal lines CD[2::1]# are connected to GND in the card. The card provides two status signals for this purpose: BVD[2::1]. Table 4Ð20 Battery Voltage Detect BVD1 H H L L 1 BVD2 1 H L H L Battery Operational Battery needs to be replaced. Battery status is expressed on 2 digital signal lines. If signal BVD2 is not supported. BVD2 is held to VCC and only one reference voltage is required. it is held to VCC through a pull-up resistor on the card.

Host platforms that support the full range of PC Cards shall assume a 150 µF maximum capacitance before host access (see Section 4. Since peak current is host platform design specific.0 V. its rising and falling time must be meet this specification. Table 4Ð21 Power-up/Power-down Timing Value Item Card Enable signal level 1 Symbol Vi (CE) Condition 0 V ≤ VCC < 2.0 V ≤ VCC < VIH VIH ≤ VCC Card Enable Setup Time RESET Setup Time Card Enable Recover Time VCC Rising Time VCC Falling Time RESET Width 2 2 Min 0 VCC-0. 2.1 3.0 10 1 0 100 Off time when changing VCC level Off level when changing VCC level 1.1 Power-up/Power-down Timing To retain data in an SRAM Card during power-up or power-down cycles. Even if the wave form is not "linear waveform". toff Voff ViMAX means Absolute Maximum Voltage for Input in the period of 0 V ≤ VCC < 2.001 Max ViMAX ViMAX ViMAX Unit V tsu (VCC) tsu (RESET) trec (VCC) tpr tpf tw (RESET) th (Hi-z RESET) ts (Hi-z RESET) 10% Ñ> 90% of VCC 90% of VCC Ñ> 10% ms ms ms 100 300 ms ms us ms ms ms 0.2 Average Current During Card Configuration). Vi (CE) is only 0 V ~ ViMAX The tpr and tpf are defined as "linear waveform" in the period of 10% to 90% or vice-versa. Peak current at start-up (in-rush current) is determined by ramp time and card capacitance.0 V 2.8 V 0. a timing specification is defined as follows.12.ELECTRICAL SPECIFICATION 4.1 VIH 20 20 0. and to permit peripheral cards to perform power-up initialization.12 Power-up and Power-down 4. © 1999 PCMCIA/JEIDA 45 . the design can be optimized within the range defined in Table 4Ð21 Power-up/Power-down Timing for the capability of the platform.12.

12.3 V VCC or 100 mA average current at 5 V VCC. Each individual function of a Multiple Function PC Card shall return to power-up state when the host system asserts the SRESET bit in the functionÕs Configuration Option register. Therefore.16-BIT PC CARD ELECTRICAL INTERFACE tsu (Vcc) tpr Vcc @ 90% tsu (RESET) VIH Vcc@10% 2V Vcc tsu (RESET) CE1#. a card shall return to the power-up state. CE2# VIH Vcc@10% ts (Hi-z RESET) RESET Hi-z Figure 4-7 Power-Up/Down Timing Vcc Vcc@90% tpf tpr Vcc@90% Voff GND Vcc@10% toff Figure 4-8: Power-Down/Power-Up Timing When Changing Vcc 4. via either the RESET line or the SRESET bit in the Configuration Option register of a single function card.15 Card Configuration. If the card requires more than this initial average current to operate. the card shall not draw its required operational current until after the Configuration Option register has been written by the host system or the first access by the host system requiring operational current occurs. regardless of the current draw required by a card to operate.) When the host system asserts RESET other than at power-up. 46 ©1999 PCMCIA/JEIDA .2 Average Current During Card Configuration A host has no method for determining the current a PC Card will draw before powering up the card. CE2# th (Hi-z RESET) tw (RESET) Hi-z tw(RESET) RESET Vcc Vcc@90% tpf trec (Vcc) 2V CE1#. a card shall not draw more than 70 mA average current at 3. (See average current in the Overview and Glossary and see also 4.

When a 16-bit transfer is attempted from a 16-bit port.13 I/O Function This section describes the operation and configuration of I/O cards inserted into a PC Card socket. and the IOIS16# signal is not asserted by the card.ELECTRICAL SPECIFICATION 4. and CD[2::1]# shall be connected to switched VCC and shall not be active when the socket is powered OFF.g. To prevent the situation wherein the PC Card is inadvertently powered while the socket power is OFF. 4. the PC Card data retention capability will depend on the individual memory card model.3 Data Retention This specification does not guarantee data retention in memory cards that conform to it. 4. When a socketÕs VCC power is switched OFF while a card is in the socket.3 V at all times. The PC Card shall not drive any signals from any other. © 1999 PCMCIA/JEIDA 47 .12. the following requirements shall be fulfilled: 1.2 I/O Input Function for I/O Cards I/O input transfers from I/O cards may be either 8-bit or 16-bit. with power active. 4. data retention during card insertion or removal when under power is implementation dependent. the manufacturer's environmental specifications.4 Supplement During card insertion or removal. the IOIS16# signal must be negated. The conditions in the preceding tables indicate the minimum requirements to ensure data retention. PC Card and system vendors may have to negotiate with each other to determine the detailed method of guaranteeing data retention for specific memory card models. the signal IOIS16# must be asserted by the I/O card. and other conditions. An I/O card may extend the length of an input cycle by asserting the WAIT# signal at the start of the cycle. (This is a concern primarily in the case of BVD[2::1] signals tied directly to an SRAM backup battery. Therefore. backup battery) when the PC Card is powered OFF. 4. All pull-up resisters on the socket signals except VS[2::1]#.1 I/O Transfer Function This section describes the operation of I/O transfer cycles (Input and Output Instructions) on I/O cards. non-VCC. When a 16-bit transfer is attempted. all socket to card signals for that socket shall be less than the voltage presented on the VCC pins on the socket plus +0.13. voltage source (e. 3.12.13.) 2. the system generates a pair of 8-bit references to access the word's even byte and odd byte. Otherwise.

the IOIS16# signal must be negated.13. 48 ©1999 PCMCIA/JEIDA .g. and the IOIS16# signal is not asserted by the card. Otherwise. An I/O card may extend the length of an output cycle by asserting the WAIT# signal at the start of the cycle. If the required voltage levels on VPP[2::1] cannot be provided by the system. If the required voltage levels on VPP[2::1] cannot be provided by the system. the card may be gracefully rejected.g. they may be required to be at other voltage levels for proper card operation as indicated in the Card Information Structure. However. during DMA) High Byte Only REG# X L L L H L CE2# H H H L X L CE1# H L L L X H A0 X L H L X X IORD# X H H H H H IOWR# X L L L L L D[15::8] X X X Odd-Byte X Odd-Byte D[7::0] X Even-Byte Odd-Byte Even-Byte X X Note: The VPP[2::1] signals to the I/O card are not required to be other than VCC specifically for output transfers. the card may be gracefully rejected. they may be required to be at other voltage levels for proper card operation as indicated in the Card Information Structure.3 I/O Output Function for I/O Cards I/O output transfers to I/O cards may be either 8-bit or 16-bit. However. 4. during DMA) High Byte Only L L H X L H Odd-Byte High-Z REG# X L L L H CE2# H H H L X CE1# H L L L X A0 X L H L X IORD# X L L L L IOWR# X H H H H D[15::8] High-Z High-Z High-Z Odd-Byte High-Z D[7::0] High-Z Even-Byte Odd-Byte Even-Byte High-Z Note: The VPP[2::1] signals to the I/O card are not required to be other than VCC specifically for input transfers. the system generates a pair of 8-bit references to access the word's even byte and odd byte. the signal IOIS16# must be asserted by the I/O Card.16-BIT PC CARD ELECTRICAL INTERFACE Table 4Ð22 I/O Input Function for All Cards Function Mode Standby Mode Byte Input (8 bits) Word Access (16 bits) I/O Inhibit (e. When a 16-bit transfer is attempted to a 16-bit port. Table 4Ð23 I/O Output Function for I/O Cards Function Mode Standby Mode Byte Output (8 bits) Word Access (16 bits) I/O Inhibit (e. When a 16-bit transfer is attempted.

D[15::0] signifies data provided by the PC Card to the host system.ELECTRICAL SPECIFICATION 4. Skews and delays from the host system driver/receiver to the PC Card must be accounted for by the system design. Figure 4-9 I/O Read Timing © 1999 PCMCIA/JEIDA 49 .13.4 I/O Read (Input) Timing Specification A[25::0] th A (IORD) REG# tsu REG (IORD) th REG (IORD) CE# tsu CE (IORD) th CE(IORD) tw (IORD) IORD# tsu A (IORD) tdr INPACK(ADR) INPACK# tdf INPACK (IORD) tdr IOIS16(ADR) IOIS16# tdf IOIS16 (ADR) td (IORD) tdr(WT) WAIT# tdf WT (IORD) tw (WT) th (IORD) D[15::0] All timings are measured at the PC Card. but minimum IORD# width must still be met. Minimum time for WAIT# negated to IORD# negated is 0 ns.

50 ©1999 PCMCIA/JEIDA . The maximum load on WAIT#. INPACK# and IOIS16# are 1 LSTTL with 50 pF total load.000 Min Max 100 All timing in ns.16-BIT PC CARD ELECTRICAL INTERFACE Table 4Ð24 I/O Read(Input) Timing Specification for All I/O Cards Item Data Delay after IORD# Data Hold following IORD# IORD# Width Time Address Setup before IORD# Address Hold following IORD# CE# Setup before IORD# CE# Hold following IORD# REG# Setup before IORD# REG# Hold following IORD# INPACK# Delay Falling from IORD# INPACK# Delay Rising from IORD# IOIS16# Delay Falling from Address IOIS16# Delay Rising from Address WAIT# Delay Falling from IORD# Data Delay from WAIT# Rising WAIT# Width Time Symbol td (IORD) th (IORD) tw IORD tsu A (IORD) th A (IORD) tsu CE (IORD) th CE (IORD) tsu REG (IORD) th REG (IORD) tdf INPACK (IORD) tdr INPACK (IORD) tdf IOIS16 (ADR) tdr IOIS16 (ADR) tdfWT (IORD) tdr(WT) tw (WT) IEEE Symbol t IGLQV t IGHQX t IGLIGH t AVIGL t IGHAX t ELIGL t IGHEH t RGLIGL t IGHRGH t IGLIAL t IGHIAH t AVISL t AVISH t IGLWTL t WTHQV t WTLWTH 0 165 70 20 5 20 5 0 0 45 45 35 35 35 0 12.

but minimum IOWR# timing must still be met. Minimum time for WAIT# negated to IORD# negated is 0 ns. Figure 4-10 I/O Write Timing © 1999 PCMCIA/JEIDA 51 . Skews and delays from the host system driver/receiver to the PC Card must be accounted for by the system design.13.ELECTRICAL SPECIFICATION 4.5 I/O Write (Output) Timing Specification A[25::0] th A (IOWR) REG# tsu REG (IOWR) th REG (IOWR) CE# tsu CE (IOWR) th CE(IOWR) tw (IOWR) IOWR# tsu A (IOWR) tdr IOIS16(ADR) IOIS16# tdf IOIS16 (ADR) tdf WT (IOWR) tdr IOWR (WT) WAIT# tw (WT) th (IOWR) D[15::0] tsu (IOWR) All timings are measured at the PC Card. D[15::0] signifies data provided by the host system to the PC Card.

(See the Metaformat Specification. Such PC Cards use Function Configuration registers to control their characteristics and return status. 4.000 Max All timing in ns.16-BIT PC CARD ELECTRICAL INTERFACE Table 4Ð25 I/O Write(Output) Timing Specification for All I/O Cards Item Data Setup before IOWR# Data Hold following IOWR# IOWR# Width Time Address Setup before IOWR# Address Hold following IOWR# CE# Setup before IOWR# CE# Hold following IOWR# REG# Setup before IOWR# REG# Hold following IOWR# IOIS16# Delay Falling from Address IOIS16# Delay Rising from Address WAIT# Delay Falling from IOWR# WAIT# Width Time IOWR# high from WAIT# High Symbol tsu (IOWR) th (IOWR) tw IOWR tsu A (IOWR) th A (IOWR) tsu CE (IOWR) th CE (IOWR) tsu REG (IOWR) th REG (IOWR) tdf IOIS16 (ADR) tdr IOIS16 (ADR) tdf WT (IOWR) tw (WT) tdr IOWR (WT) IEEE Symbol t DVIWL t IWHDX t IWLIWH t AVIWL t IWHAX t ELIWL t IWHEH t RGLIWL t IWHRGH t AVISL t AVISH t IWLWTL t WTLWTH t WTHIWH 0 Min 60 30 165 70 20 5 20 5 0 35 35 35 12.14.14.14. All such registers shall be located on even byte addresses to ensure single cycle access by both eight (8) and sixteen (16) bit host systems. The global CIS describes features that are common to all functions on the card.3 Multiple Function PC Cards Multiple Function PC Cards shall have a separate set of Configuration registers for each function on the card. A CISTPL_LONGLINK_MFC tuple in the global CIS describes the location of a function-specific CIS for each function on the PC Card.2 Single Function PC Cards Single Function PC Cards shall have a single configuration tuple describing a single set of Function Configuration registers.) 52 ©1999 PCMCIA/JEIDA .) All PC Card configuration shall be performed using this set of Function Configuration registers.1 Overview The characteristics of some 16-bit PC Cards are configurable. (See the Metaformat Specification. INPACK# and IOIS16# are 1 LSTTL with 50 pF total load. 4.14 Function Configuration 4. Multiple Function PC Cards shall use a combination of a global CIS common to all functions on the card and a separate function-specific CIS specific to each function on the card. Each function-specific CIS describes features specific to a particular function on the PC Card. The maximum load on WAIT#. All Function Configuration registers shall be read/write and one byte wide. 4.

ELECTRICAL SPECIFICATION Note: A CISTPL_FUNCID with a TPLFID_FUNCTION field reset to zero (0) shall not be placed in the CIS of a Multiple Function PC Card.14. This tuple is reserved for vendor-specific multiple function PC Cards that do not follow the multiple function PC Card definitions in the Standard.4 Function Configuration Registers (FCRs) This section describes a PC Card's Function Configuration registers. with the exact register(s) denoted by the configuration information provided by the CISTPL_EXTDEVICE tuple (described in the Metaformat Specification). All other Function Configuration registers are optional. Table 4Ð26 Function Configuration Registers Offset 0 7 6 5 4 3 2 1 0 Configuration Option Register SRESET LevIREQ Function Configuration Index / Common Memory Address Extension 2 Configuration and Status Register Changed SigChg IOIs8 RFU Audio PwrDwn Intr IntrAck 4 Pin Replacement Register CBVD1 CBVD2 CREADY CWProt RBVD1 RBVD2 RREADY RWProt 6 Socket and Copy Register RFU Copy Number Socket Number 8 Extended Status Register Event3 Event2 Event1 Req Attn Enable3 Enable2 Enable1 Req Attn Enable 10 12 14 16 18 20 Power Management Support Register RFU(0) RFU(0) RFU(0) I/O Base 0 I/O Base 1 I/O Base 2 I/O Base 3 I/O Limit RFU(0) State Restored Begin/Done State Operation Save/ Restore State Stored State Exists 22 24 26 28 30 32 34 36 Address Extension Register 0 Low Address Extension Register 0 High Address Extension Register 1 Low Address Extension Register 1 High Address Extension Register 2 Low Address Extension Register 2 High Address Extension Register 3 Low Address Extension Register 3 High © 1999 PCMCIA/JEIDA 53 . These registers allow the host to configure the function(s) provided by a PC Card. Configurable PC Cards shall implement a Configuration Option register for each function on the card. 4. Memory cards with more than 64 Mbytes of memory must implement either the Configuration Option register or a number of Address Extension Registers.

Card function configuration shall be independent of the manner in which the values were loaded into the registers. With the exception of the transient states occurring during a socket/card configuration and the potential initialization of a Socket and Copy register. The configurable characteristics include the electrical interface. (See 4. (See average current in the Overview and Glossary and see also 4. Table 4Ð27 Card Memory Spaces CE1# H L L L L L REG# X H H L L L OE# X L H L H X WE# X H L H L X Address Offset X X X X X X A0 X X X L L H Selected Register or Space Standby Common Memory Read Common Memory Write CIS or Configuration Register Read CIS or Configuration Register Write Invalid Access 54 ©1999 PCMCIA/JEIDA . All of the Function Configuration registers shall be both readable and writable. 62 and 63 (READY.12. 33.4 Socket and Copy Register. I/O address space. and BVD[2::1]) in Memory Only cards. It may also be used to access status information which appears on pins 16.15. The registers are each one byte in size and located only on even-byte addresses to ensure their single cycle access by both 8-bit and 16-bit systems. the card shall not draw its required operational current until after the Configuration Option register has been written by the host or the first access to other than CIS or Configuration registers by the host requiring operational current occurs.) While in this Power-up state. interrupt request. These cards must have one or more of a set of Function Configuration registers which are used to control the configurable characteristics of the card. and power requirements of the card. the effect of a particular combination of configuration values shall be dependent only on the current values in the registers.) Cards shall respond appropriately regardless of the order in which their registers have been initialized. These registers also provide a method for accessing some status information about a card. a card shall not draw more than 70 mA average current at 3.16-BIT PC CARD ELECTRICAL INTERFACE 4.2 Average Current During Card Configuration.15 Card Configuration Each configurable PC Card is identified by a Card Configuration Table in the card's Card Information Structure. WP. the card shall allow CIS to be read and Configuration registers to be accessed. The information may be used to arbitrate between multiple-interrupt sources on the same interrupt request level. the order of initializing the registers is not restricted. If the card requires more than this initial average current to operate. Regardless of the current draw required by a card to operate. At every moment.3 V VCC or 100 mA average current at 5 V VCC after being initially powered-up.

1 Configuration Option Register The Configuration Option register is used to configure the card. REG# L L L L L L L L L L L L L L L L L L L L L L L L L L L L OE# L H L H L H L H L H L H L H L H L H L H L H L H L H L H WE# H L H L H L H L H L H L H L H L H L H L H L H L H L H L Address Offset 1 NNNN0H NNNN0H NNNN2H NNNN2H NNNN4H NNNN4H NNNN6H NNNN6H NNNN8H NNNN8H NNNN0H + 14H NNNN0H + 14H NNNN0H + 16H NNNN0H + 16H NNNN0H + 18H NNNN0H + 18H NNNN0H + 1AH NNNN0H + 1AH NNNN0H + 1CH NNNN0H + 1CH NNNN0H + 1EH NNNN0H + 1EH NNNN0H + 20H NNNN0H + 20H NNNN0H + 22H NNNN0H + 22H NNNN0H + 24H NNNN0H + 24H A0 L L L L L L L L L L L L L L L L L L L L L L L L L L L L Selected Register Configuration Option Register Read Configuration Option Register Write Configuration and Status Register Read Configuration and Status Register Write Pin Replacement Register Read Pin Replacement Register Write Socket and Copy Register Read Socket and Copy Register Write Extended Status Register Read Extended Status Register Write Power Management Register Read Power Management Register Write Address Extension Register 0 Low Read Address Extension Register 0 Low Write Address Extension Register 0 High Read Address Extension Register 0 High Write Address Extension Register 1 Low Read Address Extension Register 1 Low Write Address Extension Register 1 High Read Address Extension Register 1 High Write Address Extension Register 2 Low Read Address Extension Register 2 Low Write Address Extension Register 2 High Read Address Extension Register 2 High Write Address Extension Register 3 Low Read Address Extension Register 3 Low Write Address Extension Register 3 High Read Address Extension Register 3 High Write Register Num 0 0 1 1 2 2 3 3 4 4 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 NNNN0H is the Configuration registers Base Address specified in the TPCC_RADR field of the Configuration Tuple.) 4. The register is a read/write register which contains three fields. provide an address extension to select a 64 MByte page of Common Memory. © 1999 PCMCIA/JEIDA 55 . (See the Metaformat Specification. and to issue a soft reset to the card.ELECTRICAL SPECIFICATION Table 4Ð28 Function Configuration Registers CE1# L L L L L L L L L L L L L L L L L L L L L L L L L L L L 1.15. The register configures a function on a PC Card and may be used to issue a soft reset to the function or set the interrupt mode (Level or Pulse) used by the function. The Configuration Option register is required on PC Cards using the I/O interface and is optional on PC Cards using the memory interface. The Configuration Option register must be implemented in all configurable cards.

If a PC Card has multiple I/O functions. This field shall be reset to zero (0) by the PC Card when the host sets the SRESET field to one (1) or the host asserts RESET. the function is disabled. would allow for the addressing of as much as 4 Gigabytes of Common Memory for PC Cards employing a 64 MByte paging architecture. the PC Card shall generate Pulse Mode interrupts. If a PC Card is not using the I/O interface. this bit is undefined. The six address extension bits when combined with the PC Cards 26 address signals (A[25::0]). This must be enforced by host software. The Card Information Structure (CIS) must be readable as specified in the Metaformat Specification no matter what interface is in use. The selection of the Common Memory Address Extension field option for use with 64 MByte paging as well as the exact size of Common Memory is specified by the CISTPL_EXTDEVICE tuple. this field is undefined. Common Memory Address Extension R/W For a memory card with > 64 MBytes of Common Memory and using 64 MByte paging this field can be used to provide six address extension bits which select a 64 MByte page within a Common Memory space as large as 4 Gigabytes. When a PC Card configuration requires an interface other than memory (including Custom Interfaces). The CORÕs Common Memory Address Extension field would select the various 64 MByte pages while the A[25::0] signals would select a specific memory location within a selected page. 56 ©1999 PCMCIA/JEIDA . Bit 2 Bit 3 . A PC Card indicates it supports Pulse Mode interrupts in the Interrupt Request Description Structure of a Function Configuration Table Entry Tuple. only I/O addresses that are qualified by the Base and Limit registers are passed to the function. If Bit 0 is reset to zero (0). the PC Card shall use the Memory Only interface and I/O cycles from the host shall be ignored by the card. LevIREQ R/W Function Configuration Index R/W When the host system sets this field to the value of the Configuration Entry Number field of a Configuration Table Entry Tuple the function shall enter the configuration described by that tuple. if they are supported by the card.If this bit is reset to zero (0) and Bit 0 is set to one (1). the function is enabled. reset state as the card does following a power-up and hardware reset. This is equivalent to the host asserting RESET. If a PC card is using the I/O interface and this field is set to zero (0).. If this is set to one (1) and Bit 0 is set to one (1). this function shall not generate interrupt requests on the PC Card's IREQ# line.16-BIT PC CARD ELECTRICAL INTERFACE For memory PC Cards where it is not necessary to configure a function on the PC Card.If this bit is reset to zero (0) and Bit 0 is set to one (1). When the host returns this field to zero (0).If this bit is reset to zero (0). the PC Card shall generate Level Mode interrupts. If Bit 0 is reset to zero (0). the PC Card shall place the function in reset state. the function shall enter the same unconfigured. all I/O addresses on the host system are passed to the function. If this bit is set to one (1). the socket controller must be programmed for that interface before the Configuration Option Register is set. this bit is undefined. If a PC card is using the I/O interface and this field is set to one (1). Enable IREQ# routing . the Configuration Option registerÕs Common Memory Address Extension field can serve to provide six address extension bits. except this field is not reset to zero (0) as it is when the host asserts RESET. all functions using interrupts on the PC Card shall use the same interrupt mode. On multiple function PC Cards. this function shall generate interrupt requests on the PC Card's IREQ# line. The Configuration Option register is organized as follows: Table 4Ð29 Configuration Option Register D7 SRESET D6 LevIREQ D5 D4 D3 D2 D1 D0 Function Configuration Index / Common Memory Address Extension Field SRESET Type R/W Description If the host sets this field to one (1). 5 are reserved for vendor implementation. bits in this field enable the following functionality: Bit 0 Bit 1 Enable Function . Enable Base and Limit Registers . If this field is set to zero (0) explicitly by the host or implicitly by SRESET or RESET. If this is set to one (1) and Bit 0 is set to one (1).

To clear the Soft Reset Bit (1->0) in the Configuration Option register.ELECTRICAL SPECIFICATION The timing of the Soft Reset must meet the same constraints as the timing of hardware reset. If present. the host shall follow the same protocol as is used for hardware reset. The host must observe the Ready condition of the READY signal before proceeding in the re-initialization of the card.2 Configuration and Status Register The Configuration and Status register is an optional register. the register allows additional control over a function's configuration and reports status related to the function's configuration. Table 4Ð30 Configuration and Status Register D7 Changed D6 SigChg D5 IOIs8 D4 RFU D3 Audio D2 PwrDwn D1 Intr D0 IntrAck © 1999 PCMCIA/JEIDA 57 . After clearing the Soft Reset bit. 4. the host shall write a 00H to the register. the host can write the Configuration Option register with the desired configuration value.15. This procedure ensures that the proper final result will occur in the register regardless of whether the card treats the write as occurring during the reset (and clears bits 6-0 regardless of the values written) or treats the write as occurring at the end of the reset (and allows bits 6-0 to be set according to the values written). After the Socket and Copy register has been written.

Must be zero (0). the function shall set this field to one (1). the function shall ignore this field. If a PC Card is not using the I/O interface or the function's Pin Replacement register is not present. IOIs8 R/W The host sets this field to one (1) when it can provide I/O cycles only with an 8-bit D[7::0] data path. writes to the Intr field are ignored. If a PC Card function does not have a power-down state. If a PC Card is using the I/O interface and both the Changed and SigChg fields are set to one (1). the PC Card must create an additional interrupt notification to the host system. or one Event bits in the Extended Status register are set (1) and the corresponding Enable bit is set (1). SigChg R/W This field serves as a gate for STSCHG#. IntrAck R/W Interrupt Acknowledge . The function shall set this field to zero (0) when it is not requesting interrupt service. shares interrupts or requires other status information available in the register. If the IntrAck field of every Configuration and Status Register on a Multiple Function PC Card is reset to zero (0). While this field is one (1). Intr R/O or R/W Interrupt Request/Acknowledge . the function shall assert STSCHG#.This field changes the response characteristics of the Intr field on Multiple Function PC Cards that have multiple sets of configuration registers. If a PC Card is using the I/O interface and this field is reset to zero (0). the function's Pin Replacement register is present and one or more of the state change signals in the Pin Replacement register are set to one (1). Writes to this field are ignored when the IntrAck field of all Configuration and Status Registers on the PC Card are reset to zero (0). the host shall not access the function. the function shall not assert STSCHG#. this field is undefined and should be ignored. Reserved. R/W R/W This bit is set to one (1) to enable audio information on SPKR# when the card is configured. The host shall return this field to zero (0) before attempting to access the function. The card is guaranteed that accesses to 16-bit registers will occur as two byte accesses rather than as a single 16-bit access.This field reports whether the function is requesting interrupt servicing and may be used to acknowledge the host system is ready to process another interrupt request from the PC Card. The Configuration and Status register must be implemented if the card generates audio. If a PC Card is not using the I/O interface or the function's Pin Replacement register is not present. This field is used to enable a hardware/software protocol that permits the PC CardÕs IREQ# signal to be shared by multiple functions on the card. The host shall set this field only if the PC Card is indicating it is ready. the PC Card must create an additional interrupt notification to the host system when the host system writes a zero (0) to the Intr field in any Configuration and Status Register on the PC Card and any function on the PC Card enabled for interrupt reporting and sharing is requesting interrupt service. the function shall enter a power-down state. 58 ©1999 PCMCIA/JEIDA . this field is undefined and should be ignored. Single function PC Cards ignore this field on writes and always return zero (0). RFU Audio PwrDwn • Host software must insure the IntrAck field is set to one (1) for all functions sharing the PC CardÕs IREQ# signal using the above described protocol. When the host sets this field to one (1). If the host system writes a zero (0) to this field in any Configuration and Status Register on the PC Card when the IntrAck field of any Configuration and Status Register is set to one (1) and any function on the PC Card is requesting interrupt servicing. if such a state exists. The function shall set this field to one (1) when it is requesting interrupt service. If the IntrAck field of any Configuration and Status Register on a Multiple Function PC Card is set to one (1): • the host system must acknowledge it is ready to receive additional interrupts from the PC Card by writing a zero (0) to the Intr field of any Configuration and Status Register after the host system has completed an entire interrupt processing cycle.16-BIT PC CARD ELECTRICAL INTERFACE Field Changed Type R/O Description If a PC Card is using the I/O interface.

When this bit is written as 0. changes state. 33. This register. however. The Pin Replacement register must be implemented if the card needs to provide information about READY. Table 4Ð32 Socket and Copy Register Organization D7 Reserved D6 D5 Copy Number D4 D3 D2 D1 D0 Socket Number © 1999 PCMCIA/JEIDA 59 . This bit may also be written by the host. 4. changes state. This bit is set to one when the bit RREADY changes state.3 Pin Replacement Register The Pin Replacement register is used to provide the card status information which was provided on pins 16. When this bit is written as 0. the CBVD1 bit is unaffected. This bit may also be written by the host. When this bit is written as 1 the corresponding CBVD1 bit is also written. This bit is set to one when the bit RWProt changes state. Table 4Ð31 Pin Replacement Register D7 CBVD1 D6 CBVD2 D5 CREADY D4 CWProt D3 RBVD1 D2 RBVD2 D1 RREADY D0 RWProt Field CBVD1 CBVD2 CREADY CWProt RBVD1 Description This bit is set (1) when the corresponding bit. This bit may also be written by the host. RBVD2 When read. When this bit is written as 0. RREADY When read. is always written by the system before writing the card's Function Configuration Index field in the Configuration Option register. When this bit is written as 1 the corresponding "changed" bit is also written. RBVD2.15. 62 and 63 in the Memory Only interface. When this bit is written as 1 the corresponding CBVD2 bit is also written.ELECTRICAL SPECIFICATION 4. if present. The register may be read and written. this bit represents the internal state of the Battery Voltage Detect circuits which would be on the BVD1 pin. This bit may be used to determine the state of READY as that pin has been reallocated for use as Interrupt Request on IO Cards. This bit is set (1) when the corresponding bit.15. when written the lower 4 bits act as mask bits for changing the corresponding bit of the upper 4 bits. This bit may also be written by the host. RWProt This bit represents the state of the WP signal. This signal may be used to determine the state of the Write Protect switch when pin 33 is being used for IOIS16#. the CBVD2 bit is unaffected. this bit represents the internal state of the READY signal. this bit represents the internal state of the Battery Voltage Detect circuits which would be on the BVD2 pin. the corresponding changed bit is unaffected. the corresponding changed bit is unaffected. RBVD1. WP or the BVD[2::1] status when implementing the I/O interface. When read. The upper 4 bits are set when the corresponding bit in the lower 4 bits changes state. When this bit is written as 1 the corresponding "changed" bit is also written. When this bit is written as 0.4 Socket and Copy Register This is an optional read/write register which the PC Card may use to distinguish between similar cards installed in a system.

The Extended Status register bit assignments are defined below: Table 4Ð33 Extended Status Register Organization D7 Event3 D6 Event2 D5 Event1 D4 Req Attn D3 Enable3 D2 Enable2 D1 Enable1 D0 Req Attn Enable Field Event3 Event2 Event 1 Req Attn Description Reserved for future expansion/definition. This bit must be set to zero (0) by software when the register is written. The host writing a one (1) to one of the upper 4 bits will clear that bit. must be reset (0) Setting this bit to a one (1) enables the setting of the Changed bit in the Configuration and Status register when the Req Attn bit is set. The first card installed receives the value 0. Enable3 Enable2 Enable1 Req Attn Enable The register may be read or written. must be reset (0) Reserved for future expansion/definition. (such as the start of each cycle of the ring frequency to indicate the presence of ringing on the phone line in the case of a modem card). Writing a zero (0) to this bit will not have any effect. should have a copy number (0 to MAX twin cards. The state of the Req Attn bit is not affected by the Req Attn Enable bit. and if the SigChg bit in the Configuration and Status register has also been set by the host. the Changed bit in the Configuration and Status register will be set. This permits any cards designed to do so to share a common set of I/O ports while remaining uniquely identifiable. and the Req Attn Enable bit is set to a one (1). This field indicates to the card that it is the n'th copy of the card installed in the system which is identically configured. and if the SigChg bit in the Configuration and Status register is also set.16-BIT PC CARD ELECTRICAL INTERFACE Field Reserved Copy Number Description This bit is reserved for future standardization. must be reset (0) Reserved for future expansion/definition. The lower four bits will return their current state when they are read. Socket Number This field indicates to the PC Card that it is located in the n'th socket. must be reset (0) Reserved for future expansion/definition. MAX = n-1) written back to the Socket and Copy register. All bits of this register are cleared to zero (0) at power-up(VCC). The host writing a one (1) to this bit will reset it to zero (0). When one of these upper four bits is latched and the corresponding enable bit in the lower nibble is also set. PC Cards which indicate in their CIS that they support more than one copy of identically configured cards. and consecutively ordered. 4. When this bit is reset to a zero (0). Reserved for future expansion/definition. by RESET or SRESET. (and the card is configured for I/O mode) then the STSCHG# pin (63) will be asserted. this feature is disabled. then the STSCHG# pin (63) will be asserted. the Changed bit in the Configuration and Status register will also be set to a one (1).15. The upper 4 bits are latched to a one (1) when the corresponding event occurs on the PC Card (for example in the case of the Req Attn bit. Writing a zero to one of the upper 4 bits will have no effect. When this bit is set to a one (1). The first socket is numbered 0.5 Extended Status Register This is an optional register that will be located at offset 08H. The register will contain information about the changes in the cards status. This permits identical cards designed to do so to share a common set of I/O ports while remaining uniquely identifiable. 60 ©1999 PCMCIA/JEIDA . when ringing occurs on the phone line on a modem card). must be reset (0) This bit is latched within one(1) ms of an event occurring on the PC Card. must be reset (0) Reserved for future expansion/definition.

If a bit in the register is set to one (1). It is only implemented on PC Cards that use I/O Base Address registers. 4. 3) The I/O Base registers are optional on single function PC Cards. For example.ELECTRICAL SPECIFICATION Setting one of the lower 4 bits enables the corresponding upper bit to be OR'ed into the Changed bit in the Configuration and Status register. The state of the upper bits is not affected by the value written to the lower bits. (See the Metaformat Specification.) 4.6 I/O Base Registers (0 . Table 4Ð35 I/O Limit Register Offset 18 D7 D6 D5 D4 I/O Limit D3 D2 D1 D0 © 1999 PCMCIA/JEIDA 61 . the setting of the Changed bit is disabled for the corresponding event.. 3) Type R/W Description Base I/O address used by function on PC Card.. This register specifies the number of address lines used by the function. When these lower bits are cleared. Each bit in the register represents an I/O address line. If the function on the PC Card always uses the same number of I/O registers in all configurations. only the first two registers need to be implemented. Table 4Ð34 I/O Base Registers Offset 10 12 14 16 D7 D6 D5 D4 I/O Base 0 I/O Base 1 I/O Base 2 I/O Base 3 D3 D2 D1 D0 Field I/O Base (0 . This allows two (2) to two hundred and fifty-six (256) I/O ports to be used by a function. The I/O Base registers determine the base address of the I/O range used to access function specific registers on the PC Card. The registers are written in little-endian order with the least significant byte of the base I/O address written to I/O Base 0. The host will determine the presence of this register by reading the TPCC_RMSK Configuration register Presence Mask of the Card Configuration Tuple. if the function on the PC Card only decodes sixteen (16) address lines. all bits of lesser significance in the register must also be set to one (1).15. The number of I/O Base Address registers implemented depends on the number of address lines the PC Card decodes. this register may be omitted (even on PC Cards with I/O Base Address registers). These registers allow the PC Card's function specific registers to be placed anywhere in the host system's I/O address space.15.7 I/O Limit Register The I/O Limit register is an optional register. They are required on multiple function PC Cards.

the PC Card function stores state information on the card and indicates that the function has stored a valid state by setting the Stored State Exists field to one (1). the function shall clear the Stored State Exists field to zero (0). When set to one (1) by the host. the host commands the PC Card function to perform a save state operation by first setting the Save/Restore state field to one (1) and the Begin/Done State Operation field to one (1). cleared to zero Reserved. the host shall assume the operation has failed.8 Power Management Support Register The Power Management Support Register is used in conjunction with the CISTPL_PWR_MGMNT tuple (see the Metaformat Specification) by host software to preserve the state of a PC Card function when power is removed from a socket and then later power is restored. Save/Restore State Begin/Done State Operation When commanded by the host to begin a Save/Restore State operation. cleared to zero There are two methods of PC Card function state preservation defined: one method stores state information within the card. This field is cleared to zero (0) by the PC Card function when a state is saved or the function is configured. In the first method (when the CISTPL_PWR_MGMNT tuple PWR_METHOD field is 80H). this field is cleared to zero (0) by the PC Card function. The host responsibility is limited to indicating when to save state and when to restore state. The PC Card function indicates the operation is complete by clearing the Begin/Done State Operation field to zero (0).15. the PC Card function restores a saved state within the period of time indicated by the PWR_TIME field in the CISTPL_PWR_MGMNT tuple when the host clears the Save/Restore state field to zero (0) and sets the Begin/Done State Operation field to one (1). If the PC Card function has not completed itÕs part of the operation within its specified save/restore time and indicated successful completion by clearing this field. Upon completing the save or restore state operation and the function is ready for operation. this field commands the function to begin a save or restore state operation. RFU(0) RFU(0) RFU(0) RFU(0) Reserved. Before socket power is removed. The host shall allow the PC Card function up to the period of time indicated by the PWR_TIME field in the CISTPL_PWR_MGMNT tuple to complete the save state operation before power is removed from the socket. Field Stored State Exists Description When set. The 62 ©1999 PCMCIA/JEIDA . this field instructs the function to save state if set to one (1) or restore state if cleared to zero (0). indicates the PC Card function has preserved a state within the card that can be restored. State Restored This field is set to one (1) by the PC Card function when a restore state operation is successfully completed. 4. In the second method (when the CISTPL_PWR_MGMNT tuple PWR_METHOD field is 00H or 01H) the PC Card function outputs state information to a buffer area on the card during a save state operation and restores state information from the buffer area during a restore state operation. Whenever the PC Card function is configured by the host or a saved configuration state is restored.16-BIT PC CARD ELECTRICAL INTERFACE Field I/O Limit Type R/W Description Bit-mapped register indicating the number of I/O address lines decoded by the function on the PC Card. cleared to zero Reserved. After socket power is restored. This field is cleared to zero (0) by the PC Card function when the saved state is restored or the function is configured. cleared to zero Reserved. the other relies on the host to store the functionÕs state information.

the PC Card is responsible for restoring the state of the functionÕs internals including the state of the functionÕs Configuration Registers.15. 32 & 36 MA39 MA38 MA30 7 6 5 4 3 2 1 0 Address Extension Register 0. reload the PC Card functionÕs state buffer and command the function to restore its state. and command the PC Card function to restore its state.1 Configuration Option Register. 2 & 3 Low MA29 MA28 MA27 MA26 MA25 MA24 Address Extension Register 0. For either method. The last two host steps. The PC Card function shall save state when commanded to do so by the host regardless of having previously saved state. the hostÕs responsibilities are to restore the state of the socket. The address extension for the page is defined in terms of extended address signals. When four Address Extension Registers are present on the PC Card. 2 & 3 High MA37 MA36 MA35 MA34 MA33 MA32 During a memory cycle the cardÕs A24 and A25 address input signals select which one of the four Address Extension Registers provides the extended address signals to memory.15. The highest numbered (offset) register of a Function Configuration Register pair is the upper byte of the Address Extension Register. The register selection is defined as follows: © 1999 PCMCIA/JEIDA 63 . the A[23::0] card address signals select a byte or word location within a 16 MByte page of memory while one of the four registers provides an address extension to select the 16 MByte page. starting with MA24 as the least significant bit. The Address Extension Register locations are organized in pairs to allow for 4 16-bit Address Extension Registers. (Additionally. two or four Address Extension Registers may appear on a PC Card and these registers may be either 8-bit or 16-bit.ELECTRICAL SPECIFICATION host is responsible for storing the contents of the buffer after the PC Card function indicates the save state operation is complete and before the card is powered down. The Address Extension Registers provide an address extension which allows the host system to address locations within an extended PC Card memory space containing as many as 242 PC Card Common Memory locations with 8-bit registers. 28. 26. either one. The 26 address signals at the PC Card connector can directly address only 64 MBytes of memory. 30 & 34 MA31 24.) Eight Function Configuration Register locations in attribute memory have been assigned to the Address Extension Registers. the host reloads the saved buffer contents into the buffer area.9 Address Extension Registers This optional set of Function Configuration Registers provides a means for a system to access more than 64 MBytes of Common Memory space on a PC Card. When a restore state operation is successfully completed the PC Card function shall set the State Restored field to one (1). 4. reload the functionÕs state buffer (only when a buffer method is used). as described in Section 4. In a restore sequence. The extended address signals appear in the Address Extension Registers as follows: Register Offset 22. the Configuration Option Register may be used to provide 6 address extension bits as an alternative to the Address Extension Registers. verify that the PC Card in the socket has not been removed from the socket since state was saved. However. are repeated for each function on a Multiple Function PC Card. 1. After re-powering the PC Card and before starting the functionÕs restore state operation. 1.

Unused register bytes are reserved for unused extended address signals and return either all '0' bits or all '1' bits when read. The register selection is defined as follows: A25 0 1 Selected Register Address Extension Register 0 Address Extension Register 1 When only one Address Extension Register is present on the PC Card. The extended address signals appear in the Address Extension Registers as follows: Register Offset 22 & 26 MA32 24 & 28 MA40 MA39 MA31 7 6 5 4 3 2 1 0 Address Extension Register 0 & 1 Low MA30 MA29 MA28 MA27 MA26 MA25 Address Extension Register 0 & 1 High MA38 MA37 MA36 MA35 MA34 MA33 During a memory cycle the cardÕs A25 address input signal selects which one of the two Address Extension Registers provides the extended address signals to memory. 64 ©1999 PCMCIA/JEIDA . starting with MA26 as the least significant bit. The extended address bits appear in the Address Extension Register 0 as follows: Register Offset 22 MA33 24 MA41 MA40 MA32 7 6 5 4 3 2 1 0 Address Extension Register 0 Low MA31 MA30 MA29 MA28 MA27 MA26 Address Extension Register 0 High MA39 MA38 MA37 MA36 MA35 MA34 The exact number of Function Configuration Registers supported by a PC Card is specified by the TPCC_RMSK byte of the CISTPL_CONFIG tuple. each time reading the register locations to determine where registers actually exist to store the pattern. software can also determine used and unused register locations by writing the registers first with a pattern of all 1Õs and then with a pattern of all 0Õs. a PC CardÕs Card Information Structure (CIS) indicates which Address Extension Registers are present. The address extension for the page is defined in terms of extended address signals.16-BIT PC CARD ELECTRICAL INTERFACE A25 0 0 1 1 A24 0 1 0 1 Selected Register Address Extension Register 0 Address Extension Register 1 Address Extension Register 2 Address Extension Register 3 When two Address Extension Registers are present on the PC Card. Thus. The address extension for the page is defined in terms of extended address bits. However. The Address Extension Register High bytes need be present on a PC Card only for Common Memory spaces requiring more than the eight address extension bits provided by a single 8-bit register. the A[25::0] card address signals select a byte or word location within a 64 MByte page of memory while the register provides an address extension to select the 64 MByte page. the A[24::0] card address signals select a byte or word location within a 32 MByte page of memory while one of the two registers provides an address extension to select the 32 MByte page. starting with MA25 as the least significant bit.

the associated Address Extension Register Low byte is always present (as indicated by TPCC_RMSK). enables an indirect access mechanism for 16-bit PC Cards. Address Extension Register 2 is set to 2. However. Address Extension Register 1 is set to 1. 9 Address Data D7 D6 D5 D4 Control_lo Byte Gran Auto Inc Space D3 D2 D1 D0 © 1999 PCMCIA/JEIDA 65 . Address Extension Register 0 is set to 0.. After the registers have been initialized. and Address Extension Register 3 is set to 3. located in common memory space. To form the contiguous 64 MByte area. 7 8 .e. the host processor can write a register with the address extension of any page in the cardÕs memory array.) This mechanism requires only four (4) address lines to provide access to spaces equivalent to the standard 16-bit PC Card Attribute and Common Memory spaces. the Card Services Specification as of the PC Card Standard Release 6.. The actual size of any indirect access spaces is determined by the card vendor as it is for standard Common Memory and Attribute Memory spaces. each register is set to the registerÕs number. Upon card power-up the PC Card initializes its Address Extension Registers to form a contiguous 64 MByte area in Common Memory. (See CISTPL_INDIRECT in the Metaformat Specification. 4.1 supports a maximum Common Memory size of 4 GBytes.16 Indirect Access to PC Card Memory This optional register set. The contiguous 64 MByte area provides a single 64 MByte area of memory which non-extended PC host software (without address extension knowledge) can address.. All registers may be read or written. i.ELECTRICAL SPECIFICATION When an Address Extension Register is provided by a PC Card. Even though the Address Extension Registers can provide an address extension which addresses beyond 4 GBytes of Common Memory. Unused register bits are reserved for unused extended address signals and return either all 0Õs or all 1Õs when read. Table 4Ð36 Indirect Access Registers Offset 2 Reserved 3 Control_hi Reserved 4 . not all 8 bits of an Address Extension Register are required to be implemented for address extension.

1 = adjust Address according to the Byte Gran setting on each Data access. Writing a value to this register will present a write operation to card memory at the indirect address indicated by the Space setting in the Control register and the current value of Address. Reserved These register bits are reserved and must be set to zero. Reading this sixteen (16) bit register will fetch the sixteen (16) bit value at the indirect address indicated by the Space setting in the Control register using the current value of Address. 0 = add two (2) to Address following each Data access. 66 ©1999 PCMCIA/JEIDA . only the even byte data is valid. If the Space setting indicates indirect Attribute Space. Byte Gran This field is ignored when the Auto Inc field is zero (0). 0 = Indirect Attribute Space 1 = Indirect Common Space 0 = do not adjust Address when a read or write access is made to Data. 1 = add one (1) to Address following each Data access.16-BIT PC CARD ELECTRICAL INTERFACE Field Control_hi Control_lo Space Auto Inc Description This sixteen (16) bit register controls read and write accesses through the Data register at the address present in the Address register. Address Data This register indicates the current twenty-six (26) bit address that will be used on the next Data access.

interface control. two VCC. and 32-bit bus slaves. two Card Detect (CCD[2::1]#). While every attempt has been made to explain functions and operations within relevant sections of the specification.5 Requirements For CardBus PC Cards and Sockets and should also consider the following from the Guidelines Volume prior to any implementation: • • • • • Enabler Capabilities and Behavior Card-Application Interaction CardBus PC Card/PCI Common Silicon Requirements CardBus PC Card Operational Scenarios Additionally. any CardBus PC Card and/or any 16-bit PC Card within the capabilities/limitations of the host system (i. arbitration. and other functions. or both). • CardBus PC Card sockets must be able to support operations with. Refer to the Required Signals section of this specification for the lists of required and optional signals/pins for CardBus PC Cards and CardBus PC Card sockets. and four ground (GND).1 CardBus PC Card Signal Description The CardBus PC Card interface requires a minimum of 46 signals for a target-only device and a minimum of 49 signals for a master to handle data and addressing. Also. In addition. and two VPP[2::1] pins are defined.ELECTRICAL SPECIFICATION 5 . the following concepts apply and should be understood prior to assimilation of the CardBus PC Card specification details: • CardBus PC Cards may include. or gracefully reject. The specification text uses many terms which may be new to prior PC Card Standard users. depending on the functions supported by CardBus PC Card agents. All signals are organized in functional groups: • • System signals Address and Data signals © 1999 PCMCIA/JEIDA 67 . As briefly discussed in the Overview section of this specification. also referred to as transaction initiators.e. users should consider the following section: 8. CAR D BU S PC CAR D EL E C T R IC AL I N T E R F AC E The CardBus PC Card Interface provides a high performance 32-bit/bus master capability for fullsize PC Cards. CardBus PC Card Connector Test Methodology (Appendix B) 5. an I/O slave.. CardBus PC Card introduces many new features and functions. a system that is incapable of providing 5. in any combination: 32-bit bus masters.0 volts cannot support 5 V 16-bit PC Cards) The user of this specification should read and understand section 5. See the Overview and Glossary to aid in understanding these terms. there are several optional signals. two Voltage Sense (CVS[2::1]) signals. also referred to as transaction targets (may be a memory slave.

1 Pin Assignments In 16-bit PC Card interface mode. s/h/z i/o. h/z i/o. o/d out. h/z i/o. s/h/z in out. WAIT#. VS[2::1]#. s/h/z i/o. h/z i/o. h/z i/o.1. s/h/z i/o. WP. They must not be wire-ORÕd or wire-ANDÕd with any host system signals. s/h/z i/o. s/h/z out. s/h/z in in in in in i/o DC DC out DC out 5. the 16-bit PC Card signals. h/z i/o. they must not be directly connected to any other signal source within the host system. s/h/z i/o. s/h/z i/o. s/h/z i/o. CE[2::1]#. o/d in i/o. s/h/z i/o. s/h/z out. s/h/z i/o. CD[2::1]#. h/z out out i/o DC DC in DC in Socket out i/o. h/z in i/o. All sockets shall support both 16-bit PC Card and CardBus PC Card interfaces and cannot connect any signals together. For these signals that are outputs from the card. 68 ©1999 PCMCIA/JEIDA . s/h/z i/o. VPP[2::1]. and BVD[2::1] must not be connected between PC Cards. s/h/z out i/o.CARDBUS PC CARD ELECTRICAL INTERFACE • • • • • • Interface Control signals Arbitration signals Error Reporting signals Interrupt Additional signals Power and Ground Table 5Ð1 CardBus PC Card List of Signals Signal Name CCLK CCLKRUN# CRST# CAD[31::00] CCBE[3::0]# CPAR CFRAME# CIRDY# CTRDY# CSTOP# CBLOCK# CDEVSEL# CREQ# CGNT# CPERR# CSERR# CINT# CSTSCHG CAUDIO CCD[2::1]# CVS[2::1] GND VCC VPP1[2::1] Number of Pins 1 1 1 32 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 4 2 2 Description (CardBus PC Card) Clock (CardBus PC Card) Clock Request/Status (CardBus PC Card) Card Reset (CardBus PC Card) Multiplexed Address/Data lines (CardBus PC Card) Command and Byte Enables (CardBus PC Card) Parity (CardBus PC Card) Cycle Frame (CardBus PC Card) Initiator Ready (CardBus PC Card) Target Ready (CardBus PC Card) Stop transaction (CardBus PC Card) Card Lock (CardBus PC Card) Device Select (CardBus PC Card) Request (CardBus PC Card) Grant (CardBus PC Card) Parity Error (CardBus PC Card) System Error (CardBus PC Card) Card Interrupt request (CardBus PC Card) Card Status Changed (CardBus PC Card) Card Audio signal (CardBus PC Card) Card Detect (CardBus PC Card) Voltage Sense Ground Power Programming (peripheral supply) Voltages Card in i/o. h/z i/o. h/z i/o. o/d out.

no signal shall be directly connected between cards other than ground. In systems which switch VCC individually to cards. It must not be wire-ORÕd or wire-ANDÕd with any host system signals.ELECTRICAL SPECIFICATION The READY signal must not be connected between cards when the 16-bit PC Card interface socket supports both I/O and Memory interfaces. © 1999 PCMCIA/JEIDA 69 .

CardBus PC Card sockets support both the 16-bit PC Card and CardBus PC Card interfaces therefore. Reserved for future use by the CardBus PC Card interface. the signals must be connected as defined for the 16-bit PC Card interface when the CardBus PC Card adapter has detected a valid 16-bit PC Card insertion event. 2. 70 ©1999 PCMCIA/JEIDA . "O" indicates signal is output from PC Card.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð2 PC Card Pin 1 to Pin 34 Assignments 16-bit PC Card Interface Memory-Only Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# READY VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND I/O DC I/O I/O I/O I/O I/O I I I I I I I I I O DC in DC in I I I I I I I I I I I I/O I/O I/O O DC 1 1 Notes I/O and Memory Signal GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND I/O DC I/O I/O I/O I/O I/O I I I I I I I I I O DC in DC in I I I I I I I I I I I I/O I/O I/O O DC Signal GND CAD0 CAD1 CAD3 CAD5 CAD7 CCBE0# CAD9 CAD11 CAD12 CAD14 CCBE1# CPAR CPERR# CGNT# CINT# VCC VPP1 CCLK CIRDY# CCBE2# CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 RFU CCLKRUN# GND I/O DC I/O DC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O DC in DC in I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 2 Notes CardBus PC Card Interface "I" indicates signal is input to PC Card. Use of pin changes between the 16-bit PC Card Memory-Only and the I/O and Memory interface. 1.

VS2# was RFU in PCMCIA 2.0 / JEIDA 4. 4.2 and earlier versions of the Standard.1 and all later versions of the Standard.1 / JEIDA 4.ELECTRICAL SPECIFICATION Table 5Ð3 PC Card Pin 35 to Pin 68 Assignments 16-bit PC Card Interface Pin Signal 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND CD1# D11 D12 D13 D14 D15 CE2# VS1# RFU RFU A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# RFU REG# BVD2 BVD1 D8 D9 D10 CD2# GND 3. I O O I/O I/O I/O O DC I O I I I I I DC in DC in I I I I 5 3 3 1 1 1 1 Memory-Only I/O DC O I/O I/O I/O I/O I/O I O 4 1 1 Notes I/O and Memory Signal GND CD1# D11 D12 D13 D14 D15 CE2# VS1# IORD# IOWR# A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND I O O I O O I/O I/O I/O O DC I I I I I/O DC O I/O I/O I/O I/O I/O I O I I I I I I I DC in Signal GND CCD1# CAD2 CAD4 CAD6 RFU CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 RFU CBLOCK# CSTOP# CDEVSEL# VCC VPP2 CTRDY# CFRAME# CAD17 CAD19 CVS2 CRST# CSERR# CREQ# CCBE3# CAUDIO CSTSCHG CAD28 CAD30 CAD31 CCD2# GND I/O I/O I/O DC in DC in I/O I/O I/O I/O I/O I O O I/O O O I/O I/O I/O O DC I/O I/O I/O I/O I/O I/O 2 I/O DC O I/O I/O I/O 2 Notes CardBus PC Card Interface RESET and WAIT# are RFU in PCMCIA 1. VS1# was named RFSH in PCMCIA 2. 5.0 / JEIDA 4.2 and earlier versions of the Standard.0 version of the Standard.1 / JEIDA 4. © 1999 PCMCIA/JEIDA 71 . These signals are required in PCMCIA 2.

Data is transferred during those clocks where both CIRDY# and CTRDY# are asserted. it remains valid until one clock after the completion of the current data phase. CPAR i/o. and CSTSCHG are not affected by CRST#. this is a byte address.) CardBus PC Card Clock Run is a signal which is used by cards to request starting (or speeding up) the CardBus PC Card clock. Also. CSERR#. h/z CardBus PC Card Address and Data are multiplexed on the same CardBus PC Card pins. A bus transaction consists of an address phase followed by one or more data phases. To prevent CAD[31::00]. CAD[31::00] contain a physical address (32 bits). For data phases CPAR is stable and valid one clock after either CIRDY# is asserted on a write transaction or CTRDY# is asserted on a read transaction. and signals to a consistent state. Write data is stable and valid when CIRDY# is asserted and read data is stable and valid when CTRDY# is asserted. CCLKRUN# is an open drain output and also an input.1. CCLKRUN#. are sampled on the rising edge of CCLK. Negation of CRST# is synchronous to CCLK CCLKRUN# i/o. and CVS[2::1]. Anytime CRST# is asserted. CCD[2::1]#. o/d for card CRST# input to card 5.1.3. Once CPAR is valid. CardBus PC Card Parity is even5 parity across CAD[31::00] and CCBE[3::0]#. What effect CRST# has on an agent beyond the CardBus PC Card sequencer is beyond the scope of this specification. CSTSCHG. except for the reset states of required CardBus PC Card configuration registers. CardBus PC Card operates up to 33ÊMHz. CCBE[3::0]# i/o. and CCLKRUN# (open drain) are floated. CGNT# must be negated. h/z 4Bit 5 order follows the convention where: bit 0 is LSB and bit 31 is MSB.2.1 Clock Specifications and see also 5. In general. this means they must be in a High-Z state. and for driving it high to the negated state. All other CardBus PC Card signals. CCLKRUN# also indicates the clock status.1 System Pins CCLK input to card CardBus PC Card Clock provides timing for all transactions on the CardBus PC Card interface and is an input to every CardBus PC Card device. CardBus PC Card Reset is used to bring CardBus PC Card specific registers.2. CINT#. A CardBus PC Card requests the host system to start. The address phase is the clock cycle in which CFRAME# is asserted. they may not be driven high. The number of "1"s on CAD[31::00]. the central resource may drive these lines during reset but only to a low voltage level. During the address phase. The states of CCD[2::1]#.2 Signal/Pin Description 5. During the address phase of a transaction. 72 ©1999 PCMCIA/JEIDA . CINT#. for configuration and memory it is a DWORD address. (CPAR has the same timing as CAD[31::00] but delayed by one clock. The CSTSCHG signal may actually pulse while CRST# is asserted. CAUDIO. and all timing parameters are defined with respect to this edge. For PC Cards. CCBE[3::0]# are used as Byte Enables. CVS[2::1] must be driven low. CCBE[3::0]#. For the host system.2. the clock can be stopped in the low state. (See 5. speed up or maintain the interface clock by assertion of CCLKRUN#.2.2 Address and Data Pins CAD[31::00] i/o. CPAR is stable and valid one clock after the address phase.2. For I/O. CCBE[0]# applies to byte 0 (LSB) and CCBE[3]# applies to byte 3 (MSB). sequencers. The host system is responsible for maintaining CCLKRUN# asserted. CCBE[3::0]# define the bus command (refer to the Bus Commands section of this specification for bus command definitions). During the data phase. h/z CardBus PC Card Command and Byte Enables are multiplexed on the same CardBus PC Card pins. except CRST# (upon assertion). During data phases.CARDBUS PC CARD ELECTRICAL INTERFACE 5. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. and CPAR equal an even number. CCLK. all CardBus PC Card output signals must be driven to their benign state. CREQ# must be in a High-Z state (it cannot be driven low or high during reset).1.) The master drives CPAR for address and write data phases.10 Clock Control. CardBus PC Card supports both read and write bursts. CAD[07::00] contain the least significant byte (LSB) and CAD[31::24] contain the most significant byte (MSB)4. the target drives CPAR for read data phases. CCBE[3::0]#. it is a Sustained High-Z state I/O signal. CRST# may be asynchronous to CCLK when asserted. and CPAR signals from floating during reset. Parity generation is required by all CardBus PC Card agents.

While CFRAME# is asserted. Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together. CardBus PC Card Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. CDEVSEL# indicates whether any device on the bus has been selected. s/h/z 5. © 1999 PCMCIA/JEIDA 73 .1. CIRDY# is used in conjunction with CTRDY#. Host bridges that have system memory behind them must also implement CBLOCK#.1. non-exclusive transactions may proceed to an address that is not currently locked. It is possible for different agents to use CardBus PC Card while a single master retains ownership of CBLOCK#. During a write. h/z for card out. CIRDY# indicates that valid data is present on CAD[31::00]. h/z for socket CardBus PC Card Request indicates to the arbiter that this agent desires use of the bus. During a read. it must also implement CBLOCK# and guarantee complete access exclusion in that memory. when actively driven. s/h/z CTRDY# i/o. s/h/z CDEVSEL# i/o. the transaction is in the final data phase. A grant to start a transaction on CardBus PC Card does not guarantee control of CBLOCK#.4 Arbitration Pins (Bus Masters Only) CREQ# CGNT# out. CardBus PC Card Stop indicates the current target is requesting the master to stop the current transaction. CardBus PC Card Device Select. data transfers continue. Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together. indicates the driving device has decoded its address as the target of the current access. CFRAME# is asserted to indicate that a bus transaction is beginning. When CFRAME# is negated.2. If a CardBus PC Card implements shared memory. CardBus PC Card Lock is an optional signal which indicates an atomic operation that may require multiple transactions to complete. CIRDY# i/o.2. CardBus PC Card Grant indicates to the agent that access to the bus has been granted. CTRDY# is used in conjunction with CIRDY#. A data phase is completed on any clock both CTRDY# and CIRDY# are sampled asserted. it indicates the master is prepared to accept data. During a read. it indicates the target is prepared to accept data.3 Interface Control Pins CFRAME# i/o. When CBLOCK# is asserted. s/h/z i/o. s/h/z CardBus PC Card Cycle Frame is driven by the current master to indicate the beginning and duration of a transaction. Control of CBLOCK# is obtained under its own protocol in conjunction with CGNT#. Every master has its own CREQ#.ELECTRICAL SPECIFICATION 5. CardBus PC Card Target Ready indicates the agent's (selected target's) ability to complete the current data phase of the transaction. Every master has its own CGNT#. During a write. As an input. CTRDY# indicates that valid data is present on CAD[31::00]. s/h/z CSTOP# CBLOCK# i/o. A data phase is completed on any clock both CIRDY# and CTRDY# are sampled asserted.

This pull-up may take two to three clock periods to fully restore CSERR#.3 Register Descriptions) CAUDIO out for card Card Audio is an optional digital audio output signal from a PC Card to the system's speaker.CARDBUS PC CARD ELECTRICAL INTERFACE 5. and/or Pulse Width Modulation (PWM) encoded signal. (See 5. The assertion of CSERR# is synchronous to the clock and meets the setup and hold times of all bused signals. The agent that reports CSERR#s to the operating system does so anytime CSERR# is sampled asserted.) CCD[2::1]#.6 Interrupt Request Pin CINT# out.2. h/z for card Card Status Changed is an optional signal used to alert the system to changes in the READY. o/d for card 5. VCC. The minimum duration of CPERR# is one clock for each data phase that a data parity error is detected. The assertion and negation of CINT# is asynchronous to CCLK.2. CardBus PC Card System Error is for reporting address parity errors. CPERR# must be driven high for one clock before being tri-stated as with all sustained tri-state signals.1. The CPERR# pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. 74 ©1999 PCMCIA/JEIDA . WP. There are no special conditions when a data parity error may be lost or when reporting of an error may be delayed. Each function on a multi-function card has its own configuration space. VPP[2::1] GND 6 When several independent functions are integrated into a single PC Card. However.2. or BVD[2::1] conditions of the card. The system vendor is free to combine the various CINT# signals from CardBus PC Card connectors in any way to connect them to the interrupt controller.1. o/d for card Card Interrupt Request is an optional signal which is defined as level sensitive. or any other system error where the result could be catastrophic.5 Error Reporting Pins The error reporting pins are required by all devices.2. CardBus PC Card supports two types of audio signals: a single amplitude. including functions on the same multi-function card. All CardBus PC Card device drivers must be able to share an interrupt (chaining) with any other logical device. CSTSCHG is asynchronous to CCLK. it is referred to as a multi-function card. If sequential data phases each have a data parity error. CSERR# is pure open drain and is actively driven for a single CardBus PC Card clock by the agent reporting the error. Common Pin Description. This means the device driver may not make any assumptions about interrupt sharing.7 Additional Signals CSTSCHG out. If an agent does not want a non-maskable interrupt (NMI) to be generated. the CPERR# signal will be asserted for more than a single clock. It is also used for the system and/or CardBus PC Card interface Wake up. CSTSCHG is asserted while any field in the Function Event Mask Register other than INTR is set (1) and the field of the same name in the Function Event Register is set (1).11. Single function and multi-function6 cards are supported. CSERR# out. s/h/z CardBus PC Card Parity Error is only for the reporting of data parity errors during all CardBus PC Card transactions except a Special Cycle. binary waveform. and asserted low (negative true). the restoring of CSERR# to the negated state is accomplished by a weak pull-up (same value as used for s/h/z) which is provided by the system designer and not by the signaling agent or central resource.3 Register Descriptions) 5. using an open drain output driver. CAUDIO has no relationship to CCLK (See 2. (See 5.11. CVS[2::1]#.1. CPERR# i/o. CINT# is asserted while the INTR field of the Function Event Mask Register is set (1) and either or both the INTR field of the Function Event Register is set (1) or the INTR field of the Function Present State Register is set (1). An agent cannot report a CPERR# until it has claimed the access by asserting CDEVSEL# and completed a data phase. a different reporting mechanism is required. data parity errors on the Special Cycle command.2.

3 Central Resource Functions Throughout this specification the term central resource is used to describe CardBus PC Card support functions supplied by the host system.1 Bus Commands Bus Commands indicate to the target the type of transaction the master is requesting. CardBus PC Card targets must not alias allocated commands with other commands. If an allocated encoding is used on the interface.3. 5. and CardBus PC Card Clock control. These functions may include. Table 5Ð4 CardBus PC Card Commands CCBE[3::0]# 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command type Allocated Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Allocated Memory Read Line Memory Write and Invalidate Allocated indicates that the command encoding is not defined for CardBus PC Card.1 Command Definition CardBus PC Card Bus Command encodings and types are as listed below. Bus Commands are encoded on the CCBE[3::0]# lines during the address phase.2.3 Pull-ups. Targets must not respond to allocated encodings. 5. the access typically will be terminated with master-abort.1. The purpose of allocated command encodings is to maintain compatibility between CardBus PC Card and other environments. followed by a brief description of each. Byte Enables are asserted when 0.). Note that the command encodings are as viewed on the bus where a "1" indicates a high voltage and "0" is a low voltage. but are not limited to. and must not be defined as other environments use the encoding.2 CardBus PC Card Operation The CardBus PC Card specification requires strong ordering of all transactions and operands across the interface. typically in the host CardBus PC Card adapter or in a CardBus PC Card compliant bridge. © 1999 PCMCIA/JEIDA 75 .3.2. the following: • • • • Central Arbitration. Required signal pull-ups or "keepers" (See 5.ELECTRICAL SPECIFICATION 5. 5.1. Default ownership of the interface.

The memory controller should continue pipelining memory requests as long as CFRAME# is asserted. During the address phase of a configuration cycle.2. updating an I/O Status register or memory flag) are passed through this access path. CAD[31::00] provide a byte address. Reserved command encodings are reserved for future use. If a reserved encoding is used on the interface. This command is intended to be used with bulk sequential data transfers where the memory system (and the requesting master) might gain some performance advantage by sequentially reading ahead an additional cache line when a software transparent buffer is available for temporary storage. The I/O Write command is used to write data to an agent mapped in I/O address space.g. An agent is selected when the CFRAME# signal is asserted and CAD[1::0] are 00. The Configuration Read command is used to read the configuration space of each agent.g. CAD[7::2] address one of the 64 DWORD registers (where byte enables address the byte(s) within each DWORD) in the configuration space of each device and CAD[31::11] are logical don't cares. CardBus PC Card targets must not alias reserved commands with other commands. The Memory Read Multiple command is semantically identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. CAD[10::08] indicate which device of a multi-function agent is being addressed. the access typically will be terminated with masterabort. When the target returns "ready. Furthermore.7. All 32 bits must be decoded. It is designed to be used as an alternative to physical signals when sideband communication is necessary. This implies that the master is free to create a synchronization event immediately after using this command.2 Special Cycle. This command is intended to be used with bulk sequential data transfers where the memory system (and the requesting master) might gain some performance advantage by reading 76 ©1999 PCMCIA/JEIDA . The Memory Read command is used to read data from an agent mapped in the memory address space. The Byte Enables indicate the size of the transfer and must be consistent with the byte address. Such buffers must be invalidated before any synchronization events (e. (See 5. or by insuring any software transparent posting buffer will be flushed before synchronization events (e. The Memory Write command is used to write data to an agent mapped in the memory address space. CAD[10::08] indicate which device of a multi-function agent is being addressed. updating an I/O Status register or memory flag) are passed through this access path. The Byte Enables indicate the size of the transfer and must be consistent with the byte address. The Configuration Write command is used to transfer data to the configuration space of each agent. the CAD[7::2] lines address the 64 DWORD (where byte enables address the byte(s) within each DWORD) configuration space of each device and CAD[31::11] are logical don't cares. During the address phase of a configuration cycle.CARDBUS PC CARD ELECTRICAL INTERFACE The Special Cycle command provides a simple message broadcast mechanism on CardBus PC Card. The Memory Read Line command is semantically identical to the Memory Read command except that it additionally indicates that the master intends to complete more than two 32-bit CardBus PC Card data phases. All 32 bits must be decoded. This can be done either by implementing this command in a fully synchronous manner. An agent is selected when its CFRAME# signal is asserted and CAD[1::0] are 00. the target must ensure the coherency (which includes ordering) of any data retained in temporary buffers after this CardBus PC Card transaction is completed. The target is free to do an anticipatory read for this command only if it can guarantee that such a read will have no side effects." it has assumed responsibility for the coherency (which includes ordering) of the subject data... Targets must not respond to reserved encodings.) The I/O Read command is used to read data from an agent mapped in I/O address space.

This command requires implementation of a configuration register in the master indicating the cache line size..2.2 Command Usage Rules All CardBus PC Card agents are required to respond as a target to configuration (read and write) commands. (See 5.e. and Memory Read Multiple. Command execution order on the CardBus PC Card is guaranteed for I/O (read and write) commands. it must accept the request (if the address is decoded for a memory access) and treat it as a Memory Read command. CardBus PC Card targets that contain relocatable functions or registers are required to allow them to be mapped to memory space through the configuration registers. The master may allow the transaction to cross a cache line boundary only if it also intends to transfer the entire next line. For masters using Memory Read commands. Memory reads and writes to a mapped device constitute "memory mapped I/O.) 5. The Memory Write and Invalidate command is semantically identical to the Memory Write command except that it additionally guarantees a minimum transfer of one complete cache line. the master intends to write all bytes within the addressed cache line in a single CardBus PC Card transaction.ELECTRICAL SPECIFICATION up to a cache line boundary in response to the request rather than a single memory cycle.2. however the preferred use is shown below.2. any length access will work for all commands. Preferred use is shown for both cases (with and without using the Cache Line Size register). When such mapping is done.1 Master Initiated Termination.3. A target containing memory which might be cacheable by the host system is also required to implement the Cache Line Size register. The Memory Read or Memory Write commands can be used if for some reason the master is not capable of using the performance optimizing commands. This command allows a memory performance optimization by invalidating a dirty line in a write-back cache without requiring the actual write-back cycle. As with the Memory Read command. All other commands are optional. a target might not implement the Memory Read Line command. however. including Memory Write and Invalidate. but if it implements basic memory commands. but must accept the request (if the address is decoded for a memory access) and treat it as a Memory Write command. For block data transfer to/from system memory. command execution order will be guaranteed by the system designer whether the device is used in I/O or memory space. the bridge is responsible for the correctness of any latent data.2. (See also 5.9 Cache Support and 5. it must translate the requested command to a memory command it has implemented. For example.1 Configuration Space.4. This means that. a noncacheable target might not implement the Memory Write and Invalidate command. The preferred use when using the Cache Line Size register is: Memory Read command Memory Read Line command Memory Read Multiple command use when bursting one half or less of a cache line use when bursting more than one half of a cache line to three cache lines use when bursting more than three cache lines © 1999 PCMCIA/JEIDA 77 . it must support all the memory commands. if the target intends to complete the first data phase. This is to provide for the option of using the device in configurations where I/O space is not available. Memory Write and Invalidate and Read Memory Line are the recommended commands for masters capable of supporting them. pre-fetched buffers must be invalidated before any synchronization events are passed through this access path. While Write and Invalidate is the only command that requires implementation of the Cache Line Size register. it is strongly suggested the Memory Read commands use it as well. Memory Read Line. thus shortening access time.1." A master may implement the optional commands as needed.3. i. A target may also implement the optional commands as needed.) The target containing cacheable memory must accept a full cache line before disconnecting the transaction if it completes the first data phase. Similarly. In all cases.

) All signals are sampled on the rising edge of the clock7. the target and master must understand the implied addressing. they will normally only have a single data phase. if in the future some new device is capable of generating meaningful I/O bursts (e. 9 The notion of qualifying CAD signals is fully defined in 5. CREQ#. To ensure that I/O devices will operate correctly.2. CAUDIO. CSTSCHG#. CFRAME#. in which transitions are not allowed. CTRDY#. 7 78 ©1999 PCMCIA/JEIDA . This aperture occurs only on qualified rising clock edges for CAD[31::00] and CPAR8 signals. Since I/O accesses from the processor cannot be combined.g. When I/O bursts are done. Combining is allowed anytime the next DWORD address is more significant than the previous one. The host bridge may always combine sequential DWORDs (memory write) generated by the processor into bursts as long as the implied address ordering (associated with each DWORD) is the same. DWORD 2 and complete the burst with DWORD 3. A device indicates no side effects (allow prefetching of read data and merging of write data in any order) by setting the prefetch bit in the Base Address register (refer to the Base Address Register section of this specification). However. the target terminates with target-abort. CSERR# (only on assertion). A bridge may distinguish where merging is allowed and where it is not by an address range which could be provided by configuration software during initialization. The bridge may convert single Processor (memory) read requests into a read burst (reading ahead of the processor) when the read will not cause a side effect in the addressed target. even if in the prefetchable range. For example. Write transactions following either of these two events may be merged with subsequent writes. CGNT#. but not to previously merged data. All I/O accesses must appear on CardBus PC Card exactly as the processor generated them. Each signal has a setup and hold aperture with respect to the rising clock edge. CardBus PC Card devices that do not deal with multiple I/O data phases must disconnect the access after the first data phase. it will not be precluded.2 CardBus PC Card Protocol Fundamentals The basic bus transfer mechanism on CardBus PC Card is a burst. CRST# (only on negation). bridges may never merge or combine sequential I/O accesses into a single CardBus PC Card access or burst. CSTOP#. CCLKRUN#. (If a target of an I/O access is selected by its address but the byte enables indicate a transfer larger than the device supports. Merging of data into that buffer must stop (and the buffer flushed) when a subsequent write occurs that is not prefetchable or a read occurs to any range. CCBE[3::0]#.CARDBUS PC CARD ELECTRICAL INTERFACE The preferred use when not using the Cache Line Size register is: Memory Read command Memory Read Line command Memory Read Multiple command use when bursting two or less data transfers use when bursting 3 to 12 data transfers use when doing long bursts (13 or more data transfers) 5. are qualified on the clock edge that CFRAME# is first asserted. signal values or transitions have no significance.2. DWORD 2. Outside this aperture. The host bridge (that resides between the host processor and CardBus PC Card) may merge (or assemble) memory write accesses into a single transaction when no side effects exist. accessing a FIFO port). There is no implied addressing on I/O bursts.7. and CVS[2::1] which are discussed inthe Signal Definition Section. are qualified on The exceptions are CINT#. DWORD 1 (no byte enables). CardBus PC Card supports bursts in both memory and I/O address spaces. as byte enables.3 Address/Data Stepping. A burst is composed of an address phase and one or more data phases. and CPERR#. CCD[2::1]#. 8 CPAR is treated like a CAD line delayed by one clock. Currently. as bus commands. CIRDY#. no known processor or bus master generates bursts in I/O space.9 and on every rising clock edge for CBLOCK#. CDEVSEL#. The CardBus PC Card burst sequence could be DWORD 0. and DWORD 3. CCBE[3::0]#.. the bridge may create a burst when the processor write sequence is DWORD 0.

CTRDY# on a read transaction).2. At such time as the master intends to complete only one more data transfer (which could be immediately after the address phase). Once a target has asserted CTRDY# or CSTOP# it cannot change CDEVSEL#. is driven by the target. The source of the data is required to assert its CXRDY# signal unconditionally when data is valid (CIRDY# on a write transaction. 5. The memory and I/O address spaces are customary. CCD[2::1]#. Address decoding on CardBus PC Card is distributed. (See also 5.2 Addressing CardBus PC Card defines three physical address spaces.2.) CFRAME# CIRDY# CTRDY# is driven by the master to indicate the beginning and end of a transaction. it is very useful for an agent that must respond to a highly fragmented address space. or for device select signals.2.. The configuration address space has been defined to support CardBus PC Card hardware configuration. Each agent is responsible for its own address decode.7. (See Figure 5-1 CardBus PC Card Basic Read Operation. The next clock edge begins the first of one or more data phases. done on every device. Wait cycles may be inserted in a data phase by either the master or the target with CIRDY# and CTRDY# signals respectively. CCLKRUN#.) CardBus PC Card targets that contain relocatable functions or registers are required to allow them to be mapped to memory space through the Base Address registers located in the CardBus PC Card configuration space. and CVS[2::1] are not qualified or synchronous. After the target indicates the final data transfer (CTRDY# is asserted). The first clock edge on which CFRAME# is asserted is the address phase. and the address and bus command code are transferred on that clock edge. This obviates the need for central decode logic. © 1999 PCMCIA/JEIDA 79 . CardBus PC Card supports two styles of address decoding. since it accepts all accesses not positively decoded by some other agent. CSTSCHG. The receiving agent may assert its CXRDY# as it chooses. Once a master has asserted CIRDY# it cannot change CIRDY# or CFRAME# until the current data phase completes regardless of the state of CTRDY#. i. CFRAME# is negated and CIRDY# is asserted indicating the master is ready. allowing it to force wait cycles.1 Generating Configuration Cycles. CTRDY#. positive and subtractive. CAUDIO. However. Neither the master nor the target can change its mind once it has committed to the data transfer. CINT#. is driven by the master. Targets that perform either positive or negative decode must not respond (assert CDEVSEL#) to reserved or allocated bus commands. This decode mechanism is slower since it must give all other bus agents a "first right of refusal" on the access.4. This is to provide for the option of using the device in system configurations where I/O space is not available. The interface is IDLE when both CFRAME# and CIRDY# are negated.2. 5. Subtractive decoding can be implemented by only one device on the bus. during which data is transferred between master and target on each clock edge for which both CIRDY# and CTRDY# are asserted.2. Positive decoding is faster since each device is looking for accesses in the address range(s) that it has been assigned. or CSTOP# until the current data phase completes.1 Basic Transfer Control The fundamentals of all CardBus PC Card data transfers are controlled with three signals.e.ELECTRICAL SPECIFICATION each rising clock edge following the completion of an address phase or data phase. the interface returns to the IDLE state with both CFRAME# and CIRDY# negated. allowing it to force wait cycles.

CARDBUS PC CARD ELECTRICAL INTERFACE The information contained in the two low order address bits (CAD[1::0]) varies by address space. In the I/O address space, all 32 CAD lines are used to provide a full byte address. This allows an agent requiring byte level address resolution to complete address decode and claim the cycle10 without waiting an extra cycle for the byte enables (thus delaying all subtractive decode cycles by an extra clock). CAD[1::0] are used for the generation of CDEVSEL# only and indicate the least significant valid byte involved in the transfer. For example, if CCBE0# were asserted then CAD[1::0] would be 00; if only CCBE3# were asserted, then CAD[1::0] would be 11. Once a target has claimed an I/O access (using CAD[1::0]), it then determines if it can complete the entire access as indicated in the byte enables. If all the selected bytes are not in the selected target's address range, the entire access cannot be completed. In this case, the target does not transfer any data, but terminates with a target-abort. The table below summarizes the encoding of CAD[1::0]. Table 5Ð5 Address Bus Encoding
CAD1 0 0 1 1 CAD0 0 1 0 1 CCBE3# X X X 0 CCBE2# X X 0 1 CCBE1# X 0 1 1 CCBE0# 0 1 1 1

The above table is for decode purposes only and only applies to a device that does not control all bytes within a single I/O DWORD. Such devices must terminate the cycle with target abort for any byte enable/CAD[1::0] combination not in the above table. However, devices that "own" all bytes in the I/O DWORD do not have to check for illegal byte enable/CAD[1::0] combinations. Instead, they may ignore CAD1 and CAD0 (i.e., claim the cycle based on the DWORD address and perform the operation described by the byte enables). Note that any combination of byte enables is valid, including none. (A device may restrict which combination of byte enables its device driver may use.) All targets are required to check CAD[1::0] during a memory command transaction, and either provide the requested burst order, or execute a target disconnect with or after the first data phase. Implementation of linear burst ordering is required by all devices that can support bursting. Implementing other burst order modes is not required. In the memory address space, accesses are decoded to a DWORD address using CAD[31::02]. In linear incrementing mode, the address is assumed to increment by one DWORD after each data phase until the transaction is terminated. During Memory commands, CAD[1::0] have the following meaning:
CAD1 0 0 1 CAD0 0 1 X Burst Order Linear address incrementing Reserved (disconnect after first data phase) Reserved (disconnect after first data phase)

In the configuration address spaces, accesses are decoded to a DWORD address using CAD[7::2]. An agent determines that it is the target of the access (asserts CDEVSEL#) when a configuration command is decoded and CAD[1::0] are 00. Otherwise, the agent ignores the current transaction. A bridge determines that a configuration access is for a device behind it by decoding a configuration

10

Standard PC address assignments in the I/O space are such that separate physical devices may share the same DWORD address. This means that in certain cases a full byte address is required for the device to claim the access (assert CDEVSEL#).

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©1999 PCMCIA/JEIDA

ELECTRICAL SPECIFICATION command, its bridge number, and that CAD[1::0] are 01. For more details about configuration accesses refer to the (See also 5.2.7.4.1 Generating Configuration Cycles.)

5.2.2.3 Byte Alignment
Byte lane swapping is not done on CardBus PC Card since all CardBus PC Card compliant devices must connect to all 32 address/data bits for address decode purposes. This means that bytes will always appear in their natural byte lane, based upon byte address. Furthermore, CardBus PC Card does not support automatic bus sizing. In general, software is aware of the characteristics of the target device and only issues appropriate length accesses. The byte enables alone are used to determine which bytes carry meaningful data. The byte enables are free to change between data phases but must be valid on the edge of the clock that starts each data phase and must stay valid for the entire data phase. (See Figure 5-1 CardBus PC Card Basic Read Operation) and note that data phases begin on clocks 3, 5, and 7. Changing byte enables during a read burst transaction is generally not useful, but is permitted.) The master is free to change the byte enables on each new data phase (although the read diagram does not show this). If the master changes byte enables on a read transaction, it does so with the same timing as would be used in a write transaction. If byte enables are important for the target on a read transaction, the target must wait for the byte enables to be valid on each data phase before completing the transfer; otherwise, it must return all bytes. Targets are only required to return the bytes indicated by the byte enables. However, if a target supports prefetching of data (see the Socket Service Specification) it must return all bytes regardless of which byte enables are asserted. Prefetching should not be enabled if there are side effects, e.g. data loss or a status change because of the access. A target should not return bytes not indicated by the byte enables if reading those bytes has any side effects. CardBus PC Card allows any contiguous or non-contiguous combination of byte enables. If no byte enables are asserted, the target of the access must complete the transaction by asserting CTRDY# and providing parity if a read request. The target of an access where no byte enables are asserted must complete the current data phase without any permanent change. On a read transaction, this means that data or status are not changed. If completing the access has no affect on the data or status, then the target may complete the access by either providing data or not. The target (on a read) must provide parity across CAD[31::0] and CCBE[3::0]# regardless of the state of the byte enables. On a write transaction, the data is not stored but CPAR is valid. However, some targets may not be able to properly interpret non-contiguous patterns (e.g. bridges that interface to 8- and 16-bit slaves). If this occurs, a target (bus bridge) may optionally report an illegal pattern as an asynchronous error (CSERR#) or, if capable, break the transaction into two 16bit transactions that are legal for the intended agent. On an I/O access, the target is required to signal target-abort if unable to complete the entire access defined by the byte enables.

5.2.2.4 Bus Driving and Turnaround
A turnaround cycle is required on all signals that may be driven by more than one agent. The turnaround cycle is required to avoid contention when one agent stops driving a signal and another agent begins. This is indicated on the timing diagrams as two arrows pointing at each others' tail. This turnaround cycle occurs at different times for different signals. For instance, CIRDY#, CTRDY#, CDEVSEL#, and CSTOP# use the address phase as their turnaround cycle. CFRAME#, CCBE[3::0]#, and CAD[31::00] use the IDLE cycle between transactions as their turnaround cycle. The turnaround cycle for CBLOCK# occurs one clock after the current owner releases it. CPERR# has a turnaround cycle on the fourth clock after the last data phase, which is three clocks after the

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CARDBUS PC CARD ELECTRICAL INTERFACE turnaround cycle for the CAD lines. An IDLE cycle is when both CFRAME# and CIRDY# are negated (e.g., clock 9 in Figure 5-1). All CAD lines must be driven to stable values during every address and data phase. Even byte lanes not involved in the current data transfer must physically drive stable (albeit meaningless) data onto the bus. The motivation is for parity calculations and to keep input buffers on byte lanes not involved in the transfer from switching at the threshold level and more generally to facilitate fast, metastability free latching. In power sensitive applications, it is recommended that, in the interest of minimizing bus switching power consumption, byte lanes not being used in the current bus phase should be driven with the same data as contained in the previous bus phase. In applications that are not power sensitive, the agent driving the CAD lines may drive whatever it desires on unused byte lanes. Parity must be calculated on all bytes regardless of the byte enables.

5.2.3 Bus Transactions
Timing diagrams show the relationship of significant signals involved in 32-bit transactions. When a signal is drawn as a solid line, it is actively being driven by the current master or target. When a signal is drawn as a dashed line, no agent is actively driving it. However, it may still be assumed to contain a stable value if the dashed line is at the high rail. High-Z signals are indicated to have indeterminate values when the dashed line is between the two rails (e.g., CAD or CCBE# lines). When a solid line becomes a dotted line, it indicates the signal was actively driven and now is High-Z. When a solid line makes a low to high transition and then becomes a dotted line, it indicates the signal was actively driven high to precharge the bus, and then switched to the High-Z state. The cycles before and after each transaction will be discussed in the arbitration section.

5.2.3.1 Read Transaction
Figure 5-1 illustrates a read transaction and starts with an address phase which occurs when CFRAME# is asserted for the first time and occurs on clock 2. During the address phase CAD[31::00] contain a valid address and CCBE[3::0]# contain a valid bus command.

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ELECTRICAL SPECIFICATION
CCLK
1 2 3 4 5 6 7 8 9

CFRAME#

CAD

ADDRESS

DATA-1

DATA-2

DATA-3

CCBE#
CIRDY#

BUS CMD

BE#'s

DATA TRANSFER

DATA TRANSFER

CTRDY#

CDEVSEL#
ADDRESS PHASE DATA PHASE DATA PHASE BUS TRANSACTION DATA PHASE

Figure 5-1 CardBus PC Card Basic Read Operation The first clock of the first data phase is clock 3. During the data phase CCBE# indicate which byte lanes are involved in the current data phase. A data phase may consist of a data transfer and wait cycles. The CCBE# output buffers must remain enabled (for both read and writes) from the first clock of the data phase through the end of the transaction. This ensures CCBE# are not left floating for long intervals. The first data phase on a read transaction requires a turnaround-cycle (enforced by the target via CTRDY#). In this case the address is valid on clock 2 and then the master stops driving CAD. The earliest the target can provide valid data is clock 4. The target must drive the CAD lines following the turnaround cycle when CDEVSEL# is asserted. Once enabled, the output buffers must stay enabled through the end of the transaction. (This ensures CAD are not left floating for long intervals.) A data phase completes when data is transferred, which occurs when both CIRDY# and CTRDY# are asserted on the same clock edge. (CTRDY# cannot be driven until CDEVSEL# is asserted.) When either is negated a wait cycle is inserted and no data is transferred. As noted in the diagram, data is successfully transferred on clocks 4, 6, and 8, and wait cycles are inserted on clocks 3, 5, and 7. The first data phase completes in the minimum time for a read transaction. The second data phase is extended on clock 5 because CTRDY# is negated. The last data phase is extended because CIRDY# was negated on clock 7. The master knows at clock 7 that the next data phase is the last. However, because the master is not ready to complete the last transfer (CIRDY# is negated on clock 7), CFRAME# stays asserted. Only when CIRDY# is asserted can CFRAME# be negated, which occurs on clock 8.

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DATA TRANSFER

WAIT

WAIT

WAIT

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CARDBUS PC CARD ELECTRICAL INTERFACE

5.2.3.2 Write Transaction
Figure 5-2 illustrates a write transaction. The transaction starts when CFRAME# is asserted for the first time which occurs on clock 2. A write transaction is similar to a read transaction except no turnaround cycle is required following the address phase because the master provides both address and data. Data phases work the same for both read and write transactions.
CCLK
1 2 3 4 5 6 7 8 9

CFRAME#

CAD

ADDRESS

DATA-1

DATA-2

DATA-3

CCBE#
CIRDY#

BUS CMD

BE#'s-1

BE#'s-2

BE#'s-3

DATA TRANSFER

DATA TRANSFER

WAIT

WAIT

CDEVSEL#
ADDRESS PHASE DATA PHASE DATA PHASE BUS TRANSACTION DATA PHASE

Figure 5-2 CardBus PC Card Basic Write Operation In Figure 5-2, the first and second data phases complete with zero wait cycles. However, the third data phase has three wait cycles inserted by the target. Notice both agents insert a wait cycle on clock 5. CIRDY# must be asserted when CFRAME# is negated indicating the last data phase. The data transfer was delayed by the master on clock 5 because CIRDY# was negated. Although this allowed the master to delay data, it did not allow the byte enables to be delayed. The last data phase is signaled by the master on clock 6, but does not complete until clock 8.

5.2.3.3 Transaction Termination
Termination of a CardBus PC Card transaction may be initiated by either the master or the target. While neither can actually stop the transaction unilaterally, the master remains in ultimate control, bringing all transactions to an orderly and systematic conclusion regardless of what caused the termination. All transactions are concluded when CFRAME# and CIRDY# are both negated, indicating an IDLE cycle (e.g., clock 9 in Figure 5-2).

5.2.3.3.1 Master Initiated Termination
The mechanism used in master initiated termination is for CFRAME# to be negated when CIRDY# is asserted. This signals the target that the final data phase is in progress. The final data transfer 84 ©1999 PCMCIA/JEIDA

WAIT

CTRDY#

DATA TRANSFER

ELECTRICAL SPECIFICATION occurs when both CIRDY# and CTRDY# are asserted. The transaction reaches completion when both CFRAME# and CIRDY# are negated (IDLE bus condition). The master may initiate termination using this mechanism for one of two reasons:
Completion Timeout refers to termination when the master has concluded its intended transaction. This is the most common reason for termination. refers to termination when the master's CGNT# line is negated and its internal Latency Timer has expired. The intended transaction is not necessarily concluded. The timer may have expired because of target induced access latency, or because the intended operation was very long. (See 5.2.5.3.1 Managing Latency on CardBus PC Card.) A Memory Write and Invalidate transaction is not governed by the Latency Timer. A master that initiates a transaction with the Memory Write and Invalidate command ignores the Latency Timer until a cache line boundary. When the transaction reaches a cache line boundary and the Latency Timer has expired (and CGNT# is negated), the master must terminate the transaction. If a Memory Write and Invalidate transaction is terminated by the target, the master completes the transaction (the rest of the cache line) as soon as possible (adhering to the CSTOP# protocol) using the Memory Write command (since the conditions to issue Memory Write and Invalidate are no longer true).

A modified version of this termination mechanism allows the master to terminate the transaction when no target responds. This abnormal termination is referred to as master-abort. Although it may cause a fatal error for the application originally requesting the transaction, the transaction completes gracefully, thus preserving normal CardBus PC Card operation for other agents. Two examples of normal completion are shown in Figure 5-3.The final data transfer is indicated when CFRAME# is negated and when both CIRDY# and CTRDY# are asserted which occurs at clock 3. The bus reaches an IDLE condition when CIRDY# is negated which occurs on clock 4. Because the transaction has completed, CTRDY# is negated on clock 4 also. Note that CTRDY# is not required to be asserted on clock 3, but could have delayed the final data transfer (and transaction termination) until it is ready by delaying the final assertion of CTRDY#. If the target does that, the master is required to keep CIRDY# asserted until the final data transfer occurs.

CCLK
1 2 3 4 1 2 3 4

CGNT#
CFRAME#
T/O T/O

CIRDY#

CTRDY#

Figure 5-3 CardBus PC Card Master Initiated Termination Both sides of Figure 5-3 could have been caused by a timeout termination. On the left side, CFRAME# is negated on clock 3 because the timer expires, CGNT# is negated, and the master is ready (CIRDY# asserted) for the final transfer. Because CGNT# was negated when the timer expired continued use of the bus is not allowed except when using the Memory Write and Invalidate command, which must be stopped at the cache line boundary. Termination then proceeds © 1999 PCMCIA/JEIDA 85

CARDBUS PC CARD ELECTRICAL INTERFACE as normal. If CTRDY# is negated on clock 2, that data phase continues until CTRDY# is asserted. CFRAME# and CIRDY# must remain asserted until the data phase completes. The right-hand example shows a timer expiring on clock 1. Because the master is not ready to transfer data (CIRDY# is negated on clock 2), CFRAME# is required to stay asserted. CFRAME# is negated on clock 3 because the master is ready (CIRDY# is asserted) to complete the transaction on clock 3. The master must be driving valid data (write) or be capable of receiving data (read) whenever CIRDY# is asserted. This delay in termination should not be extended more than two or three cycles. Also note that the Latency Timer has no meaning unless CGNT# is negated. Master-abort termination, as shown in Figure 5-4, is an abnormal case (except for configuration or Special Cycle commands) of master initiated termination. A master determines that there will be no response to a transaction if CDEVSEL# remains negated on clock 6. (For a complete description of CDEVSEL# operation, refer to the 5.2.7.1 Device Selection). The master must assume that the target of the access is incapable of dealing with the requested transaction or that the address was bad. Once the master has detected the missing CDEVSEL# (clock 6 in this example), CFRAME# is negated on clock 7, and CIRDY# on clock 8. The earliest a master can terminate a transaction with master-abort is five clocks after CFRAME# was first sampled asserted, which occurs when the master attempts a single data transfer. However, the master may take longer to negate CFRAME# and terminate the access. The master must support the CFRAME# − CIRDY# relationship on all transactions which includes master-abort. CFRAME# cannot be negated before CIRDY# is asserted and CIRDY# must remain asserted for at least one clock after CFRAME# is negated, even when the transaction is terminated with master-abort. Alternatively, CIRDY# could be negated on clock 7, if CFRAME# was negated as in the case of a transaction with a single data phase. The master will normally not retry this access. (Refer to 5.2.8.2.2 Error Response and Reporting on CSERR#). Note that if CDEVSEL# had been asserted on clocks 3, 4, 5, or 6 of this example, it would indicate the request had been acknowledged by an agent, and master-abort termination would not be permissible. The host bus bridge, in a PC compatible system, and any CardBus PC Card-to-CardBus PC Card bridge must return all 1's on a read transaction and discard data on a write transaction when terminated with master-abort. The bridge is required to set the master-abort detected field in its status register. Other master devices may report this condition as an error by signaling CSERR# when the master cannot report the error through its device driver. Prefetching of read data by a bridge must be totally transparent to the system. This means that when a prefetched transaction is terminated with master-abort, the bridge must simply stop the transaction and continue normal operation without reporting. This occurs when a transaction is not claimed by a target.

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ELECTRICAL SPECIFICATION CCLK
1 2 3 4 5 6 7 8

CFRAME#

CIRDY#

CTRDY#
NO RESPONSE

CDEVSEL#

FAST

MED

SLOW

SUB

ACKNOWLEDGE

Figure 5-4 CardBus PC Card Master-abort Termination In summary, the following general rules govern CFRAME# and CIRDY# in all CardBus PC Card transactions. 1. 2. 3. 4. CFRAME# and its corresponding CIRDY# define the busy/IDLE state of the bus: when either is asserted, the bus is busy; when both are negated, the bus is IDLE. Once CFRAME# has been negated, it cannot be reasserted during the same transaction. CFRAME# cannot be negated unless CIRDY# is asserted. (CIRDY# must always be asserted on the first clock edge that CFRAME# is negated.) Once a master has asserted CIRDY#, it cannot change CIRDY# or CFRAME# until the current data phase completes.

5.2.3.3.2 Target Initiated Termination
The mechanism used in target initiated termination is the CSTOP# signal. The target asserts CSTOP# to request that the master terminate the transaction. Once asserted, CSTOP# remains asserted until CFRAME# is negated. The relationship between CIRDY# and CTRDY# is independent of the relationship between CSTOP# and CFRAME#. That is, data may or may not be transferred during the target's request for termination; this depends solely on the state of CIRDY# and CTRDY#. However, when CSTOP# is asserted and CTRDY# is negated, it indicates the target will not transfer any more data, and the master therefore does not wait for a final data transfer as it would in a completion termination. The target may initiate termination using this mechanism for one of two reasons:
Retry refers to termination requested because the target is currently in a state which makes it unable to process the transaction. This may include the possibility of deadlock, some non-CardBus PC Card resource busy condition, or an exclusive access locked condition. Retry means the target terminates the transaction and no data was transferred. refers to termination requested because the target is unable to respond within the latency guidelines of CardBus PC Card (which is four CardBus PC Card clocks). Note that this is not usually done on the first data phase (refer to 5.2.5.3.1 Managing Latency on CardBus PC Card). Disconnect means the target terminated the transaction with or after the data that was transferred. Cacheable targets must not disconnect a Memory Write and Invalidate command except at cache line boundaries, whether caching is currently enabled or not. Therefore, a snooping agent may always assume a Memory Write and Invalidate command will complete without being disconnected when the access is to a cacheable memory range.

Disconnect

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CARDBUS PC CARD ELECTRICAL INTERFACE A modified version of this mechanism allows the target to terminate a transaction in which a fatal error has occurred, or to which the target will never be able to respond. This abnormal termination is referred to as target-abort. Although it may cause a fatal error for the application originally requesting the transaction, the transaction completes gracefully, thus preserving normal CardBus PC Card operation for other agents. Most targets will be required to implement at least retry capability, but any other versions of target initiated termination are optional for targets. Masters must be capable of properly dealing with them all. Retry is also optional to very simple targets that 1) do not support exclusive (locked) accesses, 2) cannot detect possible deadlock or livelock conditions, and 3) cannot get into a state where they may need to reject an access. Three examples of disconnect are shown in Figure 5-5. Each example shows the same relationship between CSTOP# and CFRAME#, namely that: • • Disconnect is signaled when CSTOP# is asserted and is held asserted until CFRAME# is negated. CFRAME# is negated as soon as possible after CSTOP# is asserted. Example C shows this taking an extra cycle because CIRDY# could not be asserted immediately after CSTOP# was asserted. CSTOP# is negated the cycle immediately following CFRAME# being negated.

In addition, these three disconnect examples show that CDEVSEL# is always asserted when CSTOP# is asserted; otherwise, a target-abort is indicated. These three examples show three different possibilities for data transfer in association with a disconnect. Notice that the target can determine whether or not data is transferred after CSTOP# is asserted. Data transfer takes place on every cycle where both CIRDY# and CTRDY# are asserted, independent of the state of CSTOP#. If the target wants to do one more data transfer and then stop, it asserts CTRDY# and CSTOP# at the same time. In Figure 5-5, examples A and B show two different disconnects where data is transferred after CSTOP# is asserted. In both cases, the target declares its intent to do another data transfer by having CTRDY# asserted at the time CSTOP# is asserted. In example A, the data is transferred after CFRAME# is negated (on clock 3) because the master was not ready (CIRDY# negated on clock 2). In example B, the data is transferred before CFRAME# is negated (on clock 2). If CTRDY# was asserted when CSTOP# was asserted, CTRDY# must be negated when the current data phase completes. The target cannot negate CSTOP# and continue the transaction. A master restarts any transaction terminated with retry or disconnect at a later time starting with the address of the next untransferred data. The target, upon detecting that data was transferred, removes CTRDY# since it intends to transfer no more data. Notice that this means no data is transferred in the final data phase. If the target had kept CTRDY# asserted during clock 3, and delayed the assertion of CSTOP# until clock 3, then data would have been transferred on both clock 2 and clock 3. However, the target cannot complete more than one data transfer after CSTOP# is asserted, as is demonstrated by example A. Once CSTOP# is asserted, it must stay asserted until CFRAME# is negated. If the target requires a wait cycle in the last data phase, it must delay the assertion of CSTOP# until it is ready to complete the transaction. Example C shows a case in which data is not transferred after CSTOP# is asserted because CTRDY# is negated. Note that in this example, the negation of CFRAME# is delayed until CIRDY# could be asserted. This is also an example of retry, which is actually a special case of disconnect where no data transfer occurs at all. A common example of retry is when the target is currently locked for 88 ©1999 PCMCIA/JEIDA

ELECTRICAL SPECIFICATION exclusive access by another master. Another example is when the target needs to acquire access to some other non-CardBus PC Card resource before allowing the transaction to proceed. (Care needs to be taken in this case to ensure that there are no conditions where the retry itself could generate a deadlock condition.) The master must negate its CREQ# signal when the current transaction is terminated by the target. The master must negate CREQ# for a minimum of two CardBus PC Card clocks, one being when the bus goes to the IDLE state (at the end of the transaction where CSTOP# was asserted) and either the clock before or the clock after the IDLE state. If the master intends to complete the transaction, it must reassert its CREQ# immediately following the two clocks it was negated or a potential starvation condition may occur. If the master does not intend to complete the transaction (because it was prefetching or a higher priority internal request needs to be serviced), the agent only asserts CREQ# whenever it needs to use the interface again. The lower right example in Figure 5-5 shows target-abort, which is when CSTOP# is asserted and CDEVSEL# is negated. This indicates the target requires the transaction to be terminated and doesn't want the transaction tried again. Additionally, if any data has already been transferred in the current transaction, it may have been corrupted. (Refer to 5.2.8.2.2 Error Response and Reporting on CSERR#). CDEVSEL# must be asserted for one or more clock cycles and CTRDY# must be negated before target-abort can be signaled.

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CARDBUS PC CARD ELECTRICAL INTERFACE
CCLK
1 2 3 4 1 2 3 4

CFRAME#

CIRDY#

CTRDY#

CSTOP#

CDEVSEL#

Disconnect - A
CCLK
1 2 3 4 5 1

Disconnect - B

2

3

4

CFRAME#

CIRDY#

CTRDY#

CSTOP#

CDEVSEL#

Disconnect - C / Retry
Figure 5-5 Target Initiated Termination

Target-Abort

In summary, the following general rules govern CFRAME#, CIRDY#, CTRDY#, and CSTOP# in all CardBus PC Card transactions. 1. Whenever CSTOP# is asserted, CFRAME# must be negated as soon as possible pursuant to the rules for the negation of CFRAME# (i.e., CIRDY# must be asserted). The negation of CFRAME# should occur as soon after CSTOP# is asserted as possible, preferably within two or three cycles. The target must not assume any timing relationship between CSTOP# assertion and CFRAME# negation, but must keep CSTOP# asserted until CFRAME# is negated. When the master samples CSTOP# asserted, it must negate CFRAME# on the first cycle thereafter in which CIRDY# is asserted. This assertion of CIRDY# (and therefore CFRAME# negation) may occur as a consequence of the normal CIRDY# behavior of the master (had the current transaction not been target terminated), and be delayed zero or more cycles depending on ©1999 PCMCIA/JEIDA

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ELECTRICAL SPECIFICATION when the master is prepared to complete a data transfer. Alternatively, the master may assert CIRDY# immediately (even without being prepared to complete a data transfer) if CTRDY# is negated, thus indicating there will be no further data transfer. 2. 3. Once asserted, CSTOP# must remain asserted until CFRAME# is negated, whereupon, CSTOP# must be negated. During the final data phase of a transaction (CFRAME# negated and CIRDY# asserted), any clock edge on which either CSTOP# or CTRDY# is asserted becomes the last cycle of the transaction, and CIRDY# is negated on the following clock edge. (This creates an IDLE cycle and defines the end of the transaction.) The master must retry an access that was target terminated (except target-abort) with the address of the next untransferred data if it intends to complete the access. If the device was prefetching, it may elect not to retry the access. Once a target has asserted CTRDY# or CSTOP#, it cannot change CDEVSEL#, CTRDY#, or CSTOP# until the current data phase completes.

4.

5.

5.2.4 Arbitration
In order to minimize access latency, the CardBus PC Card arbitration approach is access based rather than time slot based. That is, a bus master must arbitrate for each access it performs on the bus. CardBus PC Card uses a central arbitration scheme, where each master agent has unique request (CREQ#) and grant (CGNT#) signals. A simple request-grant handshake is used to gain access to the bus. Arbitration is "hidden", which means it occurs during the previous access so that no CardBus PC Card bus cycles are consumed due to arbitration, except when the bus is IDLE. A specific arbitration algorithm must be implemented by the central arbiter, e.g., rotating priority, fair, etc. Since the arbitration algorithm is fundamentally not part of the bus specification, system designers may elect to modify it, but must provide for the latency requirements of their selected I/O controllers and for add-in cards. Refer to 5.2.5.3.2 Low Latency Design Guidelines for information on latency guidelines. The bus allows back-to-back transactions by the same agent and allows flexibility for the arbiter to prioritize and weight requests. An arbiter can implement any scheme as long as only a single CGNT# is asserted on any clock.

5.2.5 Arbitration Signaling Protocol
An agent requests the bus by asserting its CREQ#. Agents must use CREQ# only to signal a true need to use the bus. An agent must never use CREQ# to "park" itself on the bus. When the arbiter determines an agent may use the bus, it asserts the agent's CGNT#. The arbiter may negate an agent's CGNT# on any clock. An agent must ensure its CGNT# is asserted on the clock edge it wants to start a transaction. If CGNT# is negated, the transaction must not proceed. Once asserted, CGNT# may be negated according to the following rules. 1. 2. If CGNT# is negated and CFRAME# is asserted, the bus transaction is valid and will continue. One CGNT# can be negated coincident with another CGNT# being asserted if the bus is not in the IDLE state. Otherwise, a one clock delay is required between the negation of a CGNT# and the assertion of the next CGNT#, or else there may be contention on the CAD lines and CPAR. (This refers to internal arbitration conditions in a CardBus PC Card adapter while requests are present from the system bus and a card or from multiple cards.)

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CARDBUS PC CARD ELECTRICAL INTERFACE 3. While CFRAME# is negated, CGNT# may be negated at any time in order to service a higher priority11 master, or in response to the associated CREQ# being negated.

Figure 5-6 illustrates basic arbitration. Two agents (e.g., two cards supported by the same CardBus PC Card adapter) are used to illustrate how an arbiter may alternate bus accesses.
CCLK
1 2 3 4 5 6 7

CREQ#-a CREQ#-b CGNT#-a CGNT#-b CFRAME# CAD
ADDRESS DATA ADDRESS DATA

access - A

access - B

Figure 5-6 CardBus PC Card Basic Arbitration CREQ#-a is asserted prior to or at clock 1 to request use of the interface. Agent A is granted access to the bus because CGNT#-a is asserted at clock 2. Agent A may start a transaction at clock 2 because CFRAME# and CIRDY# are negated and CGNT#-a is asserted. Agent A's transaction starts when CFRAME# is asserted on clock 3. Since agent A desires to perform another transaction, it leaves CREQ#-a asserted. When CFRAME# is asserted on clock 3, the arbiter determines agent B should go next and asserts CGNT#-b and negates CGNT#-a on clock 4. When agent A completes its transaction on clock 4, it relinquishes the bus. CardBus PC Card agents can determine the end of the current transaction when both CFRAME# and CIRDY# are negated. Agent B becomes the owner on clock 5 (because CFRAME# and CIRDY# are negated) and completes its transaction on clock 7. Notice that CREQ#-b is negated and CFRAME# is asserted on clock 6 indicating agent B requires only a single transaction. The arbiter grants the next transaction to agent A because its CREQ# is still asserted. The current owner of the bus keeps CREQ# asserted when it requires additional transactions. If no other requests are asserted or the current master has highest priority, the arbiter continues to grant the bus to the current master. CGNT# gives an agent access to the bus for a single transaction. If an agent desires another access, it should continue to assert CREQ#. An agent may negate CREQ# anytime, but the arbiter may interpret this to mean the agent no longer requires use of the bus and may negate its CGNT#. An agent should negate CREQ# in the same clock CFRAME# is asserted if it only wants to do a single
11

Higher priority here does not imply a fixed priority abitration, but refers to the agent that would win arbitration at a given instant in time.

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ELECTRICAL SPECIFICATION transaction. When a transaction is terminated by a target (CSTOP# asserted), the master must negate its CREQ# for a minimum of two CardBus PC Card clocks, one being when the bus goes to the IDLE state (at the end of the transaction where CSTOP# was asserted) and either the clock before or the clock after the IDLE state. If the master intends to complete the transaction, it must reassert its CREQ# following the negation of CREQ# or a potential starvation condition may occur. If the master does not intend to continue (because it was prefetching or a higher priority internal request needs to be serviced), the agent asserts CREQ# whenever it needs to use the interface again. This allows another agent to use the interface while the previous target prepares for the next access. The arbiter can assume the current master is broken if it has not started an access after its CGNT# has been asserted (its CREQ# is also asserted), and the bus is IDLE for eight CardBus PC Card clocks. However, the arbiter may remove CGNT# at any time to service a higher priority agent.

5.2.5.1 Fast Back-to-Back Transactions
There are two types of fast back-to-back transactions that can be initiated by the same master, those that access the same agent and those that do not. Fast back-to-back transactions are allowed on CardBus PC Card when contention on CTRDY#, CDEVSEL#, or CSTOP# is avoided. The first type of fast back-to-back support places the burden of avoiding contention on the master, while the second places the burden on all potential targets. The master may remove the IDLE cycle between transactions when it can guarantee that no contention occurs. This can be accomplished when the master's second transaction is to the same target as the first and the first transaction is a write. This type of fast back-to-back transaction requires the master to understand the address boundaries of the potential target, otherwise contention may occur. This type of fast back-to-back is optional for a master but must be decoded by a target. The second type of fast back-to-back support places the burden of no contention on all potential targets. The Fast Back-to-Back Capable field in the Status register may be hardwired to a logical one (high) if and only if the device, while acting as a bus target, meets the following two requirements: 1. The target must not miss the beginning of a bus transaction, nor lose the address, when that transaction is started without a bus IDLE state preceding the transaction. In other words, the target is capable of following a bus state transition from a final data transfer (CFRAME# high, CIRDY# low) directly to an address phase (CFRAME# low, CIRDY# high) on consecutive clock cycles. Note that the target may or may not be selected on either or both of these transactions, but must track bus states nonetheless. The target must avoid signal conflicts on CDEVSEL#, CTRDY#, and CSTOP#. If the target does not implement the fastest possible CDEVSEL# assertion time, this guarantee is already provided. For those targets that do perform zero wait state decodes, the target must delay assertion of these three signals for a single clock, except in either one of the following two conditions:
a. b. The current bus transaction was immediately preceded by a bus IDLE state. That is, this is not a back-to-back transaction, or, The current target had driven CDEVSEL# on the previous bus transaction. That is, this is a backto-back transaction involving the same target as the previous transaction.

2.

For masters that want to perform fast back-to-back transactions that are supported by the target mechanism, the Fast Back-to-Back Enable field in the Command register is required. (This optional field is only meaningful in devices that act as bus masters.) It is a read/write field when implemented. When set to a one (high), the bus master may start a CardBus PC Card transaction using fast back-to-back timing without regard to which target is being addressed, provided the previous transaction was a write transaction issued by the current bus master. If this field is set to a © 1999 PCMCIA/JEIDA 93

CARDBUS PC CARD ELECTRICAL INTERFACE zero (low) or not implemented, the master may perform fast back-to-back only if it can guarantee that the new transaction goes to the same target as the previous one (master based mechanism). This field would presumably be set by the system configuration routine, after ensuring that all targets on the same bus had the Fast Back-to-Back Capable field set. Note that the master based fast back-to-back mechanism does not allow these fast cycles to occur with separate targets, while the target based mechanism does. If the target is unable to provide both of the guarantees specified above, it must not implement this field and it will automatically be returned as a zero when the Status register is read. However, it is recommended that all targets implement the target based fast back-to-back capability. Under all other conditions, the master must insert a minimum of one IDLE bus state. (There is always at least one IDLE bus state between transactions by different masters.) Note multi-ported targets should only lock themselves when they are truly locked during fast back-to-back transactions (refer to 5.2.6 Exclusive Access for more information). During a fast back-to-back transaction, the master starts the next transaction immediately without an IDLE bus state. The last data phase completes when CFRAME# is negated, and CIRDY# and CTRDY# are asserted. The current master starts another transaction on the same clock the last data is transferred for the previous transaction. It's important to note that agents not involved in a fast back-to-back transaction sequence cannot (and generally need not) distinguish intermediate transaction boundaries using only CFRAME# and CIRDY# (there is no bus IDLE cycle). During fast back-to-backs only, the master and target involved need to distinguish these boundaries. When the last transaction is over, all agents will see an IDLE cycle. However, those that do support the target based mechanism must be able to distinguish the completion of all CardBus PC Card transactions and be able to detect all address phases. In Figure 5-7, the master completes a write on clock 3 and the address phase of the next transaction occurs on clock 4. The target must begin sampling CFRAME# on the clock following the completion of the current data transaction. Targets must be able to decode back-to-back operations while a master may optionally support this function. A target is free to retry the request after it has claimed ownership by asserting CDEVSEL#.
CCLK
1 2 3 4 5 6 7

CREQ# CGNT# CFRAME# CAD CIRDY# CTRDY#
ADDRESS DATA ADDRESS DATA

Figure 5-7 Arbitration for Back-to-Back Access

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5.2.5.2 CardBus PC Card Idle Condition
The CardBus PC Card central resource, typically embedded in the host CardBus PC Card adapter, is the default owner of the interface. When no agent is using or requesting the bus, the central resource ensures that the CardBus PC Card signals are in stable states and prevented from floating. When the bus becomes IDLE and no CGNT# is asserted, the central resource must enable its CAD[31::00], CCBE[3::0]#, and (one clock later) CPAR output buffers within eight CardBus PC Card clocks, while two or three clocks is recommended. (Refer to parity discussion for description of timing relationship of CPAR to CAD.) The central resource is not required to turn on all buffers in a single clock. However, if the host system supports the Clock Control Protocol (refer to 5.2.10 Clock Control), the central resource must enable its CAD[31::00], CCBE[3::0]#, and CPAR output buffers before stopping the CardBus PC Card clock. Refer to 5.3 CardBus PC Card Electrical Specification for a description of how to maintain valid levels on other CardBus PC Card signals. The CardBus PC Card arbiter must not assert CGNT# to an agent located on a PC Card unless CREQ# is asserted by the agent. Note that the default owner of the interface, the central resource or the CardBus PC Card adapter, may start a transaction at any time while it owns the bus (provided that the clock is not stopped). Given the above, minimum arbitration latency achievable on CardBus PC Card from bus IDLE is as follows: • • Driven by the adapter: zero clocks for adapter, two clocks for others Not driven: one clock

5.2.5.3 Latency
CardBus PC Card is a low latency, high throughput interface. This section describes the CardBus PC Card mechanisms that help control worst case latency. Although latencies in a stand alone CardBus PC Card environment can be predicted with relatively high precision, the inclusion of a standard expansion bus (ISA, EISA, MC, or NuBus™), and other system effects, make latency prediction much more difficult.

5.2.5.3.1 Managing Latency on CardBus PC Card
Figure 5-8 depicts the different time components that a device sees as part of access latency. The first portion, arbitration latency, is the time that the master waits after having asserted CREQ# until it receives CGNT#. This time is a function of the arbitration algorithm, the priority of the requesting device, and system utilization. For the highest priority device, this time, typically, will be two CardBus PC Card clocks. The next component, bus acquisition latency, is how long the device has to wait for the bus to become free. The last component, target latency, is the amount of time that the target takes to assert CTRDY# for the first data transfer.
Master asserts CREQ# Master receives CGNT# Master asserts CFRAME# Target asserts TRDY#

Arbitration Latency

Bus Acquisition Latency

Target Latency

Figure 5-8 Components of Access Latency

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CARDBUS PC CARD ELECTRICAL INTERFACE A CardBus PC Card master can burst indefinitely so long as the target can source/sink the data, and no other agent requests the bus. However, CardBus PC Card specifies two mechanisms that cap a master's tenure in the presence of other requests, so that predictable bus acquisition latency can be achieved. These are defined as follows: Master Latency Timer (LT): Each master's LT is cleared and suspended whenever it is not asserting CFRAME#. When a master asserts CFRAME#, it enables its LT to count. If the master negates CFRAME# prior to count expiration, LT is meaningless. Otherwise, once the count expires (count = "T" clocks), the master must initiate transaction termination (refer to 5.2.3.3.1 Master Initiated Termination) as soon as its CGNT# is removed. In essence, "T" represents a minimum guaranteed time slice (measured in CardBus PC Card clocks) allotted to the master, after which it must surrender tenure as soon as its CGNT# is removed. (Actual termination does not occur until the target is ready.) Target Initiated Termination (Specifically Disconnect): A target must manipulate CTRDY# and CSTOP# so as to end the transaction upon consummation of data phase "N" (where N=1, 2, 3, ...), if incremental latency to data phase "N+1" is greater than eight clocks. For example, assume a CardBus PC Card master read from a target takes a minimum of eight clocks. Applying the rule for N = 1, the latency to data phase 2 is eight clocks, thus the target must terminate upon completion of data phase 1 (i.e., a target this slow must break attempted bursts on data phase boundaries). Note that neither mechanism restricts latency to the first data phase. (See also 5.2.5.3.2 Low Latency Design Guidelines). For example, assume that in a particular system, there is no target so slow that it delays CTRDY# by more than T+8 clocks for the first data phase to complete. Given this assumption and the mechanisms above, it can be shown that the longest transaction the master will execute is T+8 clocks (assuming its CGNT# is removed before its LT expires). In effect, T represents a trade-off between throughput (relatively high values) and latency (low values). For example, T = 40 accommodates a burst of 32 data phases (128 bytes in a 32-bit/clock transaction) if both master and target are capable of 0 wait cycle bursts (assuming an eight clock latency to first data). Reducing T to 20 would likely break the burst every 12 to 14 transfers, but would constrain the maximum transaction to 28 clocks.

5.2.5.3.2 Low Latency Design Guidelines
CardBus PC Card accommodates both throughput and latency sensitive devices. On occasion, unusually long accesses are tolerable as long as typical latency is short. CardBus PC Card features such as unlimited length bursts (for high bandwidth block I/O) favor such high throughput devices. On the other hand, a 10 Mbits/second LAN device consumes a small fraction of CardBus PC Card bandwidth. To keep such a device economical (minimize data buffer requirements), CardBus PC Card features like access-based arbitration and master Latency Timers help to bound worst case latency. For example, a buffered FDDI device, otherwise capable of a 128-DWORD burst in a single access, can be forced by its Latency Timer to break the transfer into several small pieces, allowing shallow-buffer, latency sensitive devices access to the bus more often. High throughput and low latency are often at odds with one another. Accordingly, it is important that CardBus PC Card components and systems be intelligently designed to minimize risk of latency-related interoperability problems, and to facilitate reasonable price/performance trade-offs. To facilitate such designs, and, in general, to encourage good design practices, the guidelines listed below are recommended for target interface design. In the following, "single layer" refers to a CardBus PC Card target that provides immediate access to the selected resource, i.e., a single port memory. "Multi-layer" refers to a target that must acquire an independently arbitrated resource to provide access to the selected resource, i.e., CardBus PC Card-to-bus bridges (e.g., CardBus PC Card-to-CardBus PC Card, CardBus PC Card-to-Host Memory, etc.) or dual port memory. 96 ©1999 PCMCIA/JEIDA

ELECTRICAL SPECIFICATION 1. Single layer targets should constrain first data phase latency to sixteen clocks. If a temporary internal state (e.g., DRAM refresh, full queue of previously posted writes) would otherwise stretch the access beyond eight clocks, retry immediately. Multi-layer targets should retry an access that collides with a busy resource. For example, an access to a system bus slave while the system bus is owned by another master should be immediately retried. (The cycle would likely have to be retried anyhow to avoid deadlock, so why wait?) Likewise, an access to a DRAM frame buffer currently consumed by screen refresh should be retried. Multi-layer targets (especially bus-to-bus bridges) should exercise great care in write buffer strategy. Write buffers make it difficult to bound latency, since strong ordering requirements typically mandate that all writes queued to a bus be completed before an access going the other way is allowed.

2.

3.

To facilitate making sound system level tradeoffs, component vendors should clearly document device latency behavior. (A common tradeoff is to disallow specific ill-behaved standard bus adapters in a real-time application.) Master devices should spell out both latency expectations and the consequences of latency violation. Target devices should specify worst case response, as well as all events that can cause a retry or disconnect. If a target's latency is paced by external factors (e.g., how long an ISA adapter stretches a cycle) this should be clearly stated.

5.2.6 Exclusive Access
CardBus PC Card provides a non-blocking exclusive access mechanism which allows non-exclusive accesses to proceed in the face of exclusive accesses. This is referred to as a resource lock, and allows an agent to hold a hardware lock across several accesses without interfering with non-exclusive, real-time data transfer, such as video. The mechanism is based on locking only the CardBus PC Card resource to which the original locked access was targeted. This mechanism is fully compatible with existing software exclusion techniques used on devices implementing a bus lock. The CardBus PC Card exclusive access model supports read-modify-write operations. CBLOCK# is required on any device providing system memory. Specifically, if the device implements shared memory, then it must also implement CBLOCK#, and guarantee complete access exclusion in that memory, i.e., if there is a master local to that memory, it must also honor the lock. Host CardBus PC Card bridges that have system memory behind them must also implement CBLOCK#. The CBLOCK# signal indicates an exclusive access is underway. The assertion of CGNT# does not guarantee control of CBLOCK#. Control of CBLOCK# is obtained under its own protocol in conjunction with CGNT#. When using a resource lock, agents performing non-exclusive accesses are free to proceed even while another master retains ownership of CBLOCK#. However when compatibility dictates, the arbiter can optionally convert a resource lock into a bus lock by granting the agent that owns CBLOCK# exclusive access of the bus until CBLOCK# is released. Refer to 5.2.6.6 Complete Bus Lock for more details. In a resource lock, exclusivity of an access is guaranteed by the target of the access, not by excluding all other agents from accessing the bus. The granularity of the lock is defined to be the length of the initial exclusive read transaction. The master cannot rely on any addresses outside the initial read range to be locked. A target is required to lock as minimum the address range read by the master in the initial exclusive read transaction and up to a maximum of the entire resource. A target that supports CBLOCK# on CardBus PC Card must adhere to the following rules: 1. The target of an access locks itself when CBLOCK# is negated during the address phase.

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CARDBUS PC CARD ELECTRICAL INTERFACE 2. 3. Once lock is established, the target remains locked until it samples both CFRAME# and CBLOCK# negated together or it signals target-abort. The target guarantees exclusivity to the owner of CBLOCK# (once lock is established) of at least the number of bytes read in the initial exclusive access.12 This includes accesses that do not originate on CardBus PC Card for multiport devices.

All CardBus PC Card targets that support exclusive accesses must sample CBLOCK# with address. If the target of the access performs medium or slow decode, it must latch CBLOCK# during the address phase to determine if the access is a lock operation when decode completes. The target of a transaction marks itself locked if CBLOCK# is negated during the address phase. If a target waits to sample CBLOCK# until it asserts CDEVSEL#, it cannot distinguish if the current access is a locked transaction or one that occurs concurrently with a locked access. An agent may store "state" to determine if the access is locked but this requires latching CBLOCK# on consecutive clocks and comparing to determine if the access is locked. The simpler way is for the target to mark itself locked on any access it claims where CBLOCK# is negated during the address phase. A locked target remains in the locked state until both CFRAME# and CBLOCK# are negated. To allow other accesses to a multiport device, the target may sample CBLOCK# the clock following the address phase to determine if the device is really locked. When CBLOCK# is negated during the address phase and is asserted the clock following the address phase, the multiport device is locked and must ensure exclusivity to the CardBus PC Card master. When CBLOCK# is negated during the address phase and the clock following the address phase, the target is not locked, and is free to respond to other requests. A currently locked target may only accept requests when CBLOCK# is negated during the address phase. A currently locked target will respond by asserting CSTOP# with CTRDY# negated (retry) to all transactions when CBLOCK# is asserted during the address phase. To summarize, a target of an access locks itself on any access it claims when CBLOCK# is negated during the address phase. It unlocks itself anytime CFRAME# and CBLOCK# are both negated. It may seem confusing for the target to lock itself on a transaction that is not locked. However, from an implementation point of view, it is a simple mechanism that uses combinatorial logic and always works. The device will unlock itself at the end of the transaction when it detects CFRAME# and CBLOCK# both negated. A target can also remember state (which is useful for a multiport device) to determine if it is truly locked or not. The target is truly locked when CBLOCK# is negated during the address phase and asserted on the following clock. The arbiter must be in some type of "fairness" algorithm when CBLOCK# is asserted; otherwise, a livelock may occur. Existing software that does not support the CardBus PC Card lock usage rules has a potential of not working correctly. CardBus PC Card resident memory that supports CBLOCK# and desires to be backward compatible to existing software is recommended to implement complete resource lock. Refer to 5.2.6.5 Supporting CBLOCK# and Write-back Cache Coherency for details of how to avoid deadlocks. A master that uses CBLOCK# on CardBus PC Card must adhere to the following rules: 1. 2. 3. 4. 5. A master can access only a single resource during a lock operation. A lock cannot straddle a device boundary. First transaction of lock operation must be a read transaction. Only the address range accessed in the initial read can be assumed to be locked. CBLOCK# must be asserted the clock following the address phase and kept asserted to maintain control.

12

The maximum is the complete resource.

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ELECTRICAL SPECIFICATION 6. 7. 8. CBLOCK# must be released if retry is signaled before a data phase has completed and the lock has not been established.13 CBLOCK# must be released whenever an access is terminated by target-abort or master-abort. CBLOCK# must be negated for a minimum of one IDLE cycle between consecutive lock operations.

Since different processors and system architectures support different, and often incompatible, exclusion protocols, both software and hardware designers should use only generally accepted, compatible constructs. Given the nature of a resource lock, the bus protocol will ensure that correctly written software exclusion algorithms will function over CardBus PC Card. Other system constraints, such as processor protocols and other system busses, however, make it only possible to guarantee that read-and-set operations (a read-modify-write where the data bits are all 1's) are universally accepted by the systems. This is sufficient to implement semaphores, and thus to implement all other forms of exclusion in software. Furthermore, it is an unreasonable burden, not to mention a potentially significant performance degradation, to ensure that arbitrary transaction combinations under lock operate correctly. Based on this, the following rules are defined for transactions initiated by a bus master residing on a CardBus PC Card: 1. 2. 3. 4. 5. First transaction of an exclusive access must be a Memory Read transaction14. An exclusive sequence may contain only one Memory Write transaction. If an exclusive sequence includes a Memory Write, then the Memory Write must be the last transaction. All Memory Read and Memory Write transactions must be DWORD aligned. If an exclusive sequence contains multiple Memory Read transactions, and ends with a Memory Write transaction, then the write is not guaranteed to be atomic with respect to any of the Memory Reads.

These rules should not be construed as defining the only behavior for exclusive accesses allowed in a system. However, a card designer cannot assume that the system supports other transaction sequences for exclusive operations.

5.2.6.1 Starting an Exclusive Access
When an agent needs to do an exclusive operation, it checks the internally tracked state of CBLOCK# before asserting CREQ#. The master marks CBLOCK# busy anytime CBLOCK# is asserted and not busy when both CFRAME# and CBLOCK# are negated. If CBLOCK# is busy, the agent should delay the assertion of CREQ# until CBLOCK# is available. While waiting for grant, the master continues to monitor CBLOCK#. If CBLOCK# is ever busy, the master negates CREQ#, because another agent has gained control of CBLOCK#. When the master is granted access to the bus and CBLOCK# is not busy, ownership of CBLOCK# has occurred. The master is free to perform an exclusive operation when the current transaction completes and is the only agent on the bus that can drive CBLOCK#. Any other agent must not drive CBLOCK#, even when it is the current master.
Once lock has been established, the master retains ownership of CBLOCK# when terminated with retry or disconnect. 14Note that any one command, Memory Read, Memory Read Line, or Memory Read Multiple, represents a single transaction. However, prefetching is not recommended for the command which establishes an exclusive access to a target unless a complete resource lock is implemented.
13

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When the exclusive access is complete.CARDBUS PC CARD ELECTRICAL INTERFACE Figure 5-9 illustrates starting an exclusive access. to keep the target in the locked state which allows the current master to retain ownership of CBLOCK# beyond the end of the current transaction.4 Completing an Exclusive Access for more information on completing an exclusive access). it negates CBLOCK# after the last data phase which occurs on clock 5 (refer to 5. the target is indicating it is currently busy and unable to complete the requested data phase. Target termination by retry or disconnect is a normal termination even when a lock operation is established. this access may or may not complete the exclusive operation.6. When a master is terminated by the target with disconnect or retry after the lock has been established. CCLK 1 2 3 4 5 CFRAME# CBLOCK# CAD CIRDY# CTRDY# ADDRESS DATA Figure 5-9 CardBus PC Card Starting an Exclusive Access A locked operation is not established on the bus until completion of the first data phase of the first transaction (CIRDY# and CTRDY# asserted). it starts another exclusive access to the target it previously locked. CBLOCK# is negated during the address phase to request a lock operation which must be initiated with a read command.6. and the master keeps CBLOCK# asserted until either the lock operation completes or an error (master. The target will accept the access when it is not busy and continue to honor the lock by excluding all other accesses. When the master is granted access to the bus.or target-abort) causes an early termination. CBLOCK# must be asserted the clock following the address phase. When the master completes the lock operation. CBLOCK# is asserted on clock 3 to keep the target in the locked state and allow the current master to retain ownership of CBLOCK# beyond the end of the current transaction. it continues to assert CBLOCK#. 5.2.2 Continuing an Exclusive Access Figure 5-10 shows a master continuing an exclusive access. 100 ©1999 PCMCIA/JEIDA . The locked device accepts and responds to the request. Non-exclusive accesses to unlocked targets on CardBus PC Card are allowed to occur while CBLOCK# is asserted. not only must the master terminate the transaction but it must also release CBLOCK#. However. the exclusive operation is established. CBLOCK# is negated during the address phase to re-establish the lock.2. CBLOCK# is negated and other masters may vie for ownership. If the target retries the first transaction without a data phase completing. The master continues to control CBLOCK#. When the master is continuing the lock operation. Once the first data phase completes. which is on clock 3.

ELECTRICAL SPECIFICATION CCLK 1 2 3 4 5 CFRAME# CBLOCK# CAD CIRDY# CTRDY# ADDRESS DATA Release Continue Figure 5-10 CardBus PC Card Continuing an Exclusive Access 5. Also. CCLK 1 2 3 4 5 CFRAME# CBLOCK# CAD CIRDY# CTRDY# CSTOP# CDEVSEL# ADDRESS (driven low by master holding lock) DATA Figure 5-11 CardBus PC Card Accessing a Locked Agent © 1999 PCMCIA/JEIDA 101 . an unlocked target does not go into a locked state.3 Accessing a Locked Agent Figure 5-11 shows a master trying a non-exclusive access to a locked agent.6. and if the target is locked. it signals retry and no data is transferred. An unlocked target ignores CBLOCK# when deciding if it should respond.2. since CBLOCK# and CFRAME# are asserted during the address phase. When CBLOCK# is asserted during the address phase.

it must ensure a minimum of one clock between operations where both CFRAME# and CBLOCK# are negated. then the complete bus lock has been established and the arbiter will not grant the bus to any other agent. Cache line n+1 has been modified in the cache.7 Other Bus Operations 5. If a master wants to execute two independent exclusive operations on the bus. particularly the video subsystem. (An agent must unlock itself when CFRAME# and CBLOCK# are both negated on one clock edge. then the master must negate both its CREQ# and CBLOCK#. If the arbiter granted the bus to another agent when the complete bus lock was being established.4 Completing an Exclusive Access During the final transfer of an exclusive operation. A deadlock may occur if software allows locks to cross a cache line boundary when write-back caching is supported and a complete resource lock is used.) This ensures any target locked by the first operation is released prior to starting the second operation. the cache writeback of the modified line fails because the target only accepts accesses from the owner of CBLOCK#.1 Device Selection CDEVSEL# is driven by the target of the current transaction as shown in Figure 5-12.2. The snoop (of n+1) results in a hit to modified line in the host system's write-back cache. CBLOCK# is negated so the target will accept the request. potential of a deadlock exists for complete bus lock.6 Complete Bus Lock The CardBus PC Card resource lock can be converted into a complete bus lock by having the arbiter not grant the bus to any other agent while CBLOCK# is asserted. All non-exclusive accesses will not proceed while a locked operation is in progress.6. CDEVSEL# may be driven one.6. and then re-asserted until the exclusive access terminates successfully.7.2. 5. two. the arbiter must remove the other grant to ensure that complete bus lock semantics are observed. When the first access of the locked sequence is retried. (For example. it is recommended (but not required) that CBLOCK# be negated with the negation of CIRDY# following the completion of the last data phase of the locked operation. or three clocks following the address phase and its timing is indicated in 102 ©1999 PCMCIA/JEIDA . 5. The locked operation continues by reading location corresponding to cache line n+1.2. When the first access completes normally. However.CARDBUS PC CARD ELECTRICAL INTERFACE 5. A master establishes a resource (memory) lock by reading location corresponding to cache line n. The master may negate CBLOCK# at anytime when the exclusive operation has completed. the fast back-to-back case depicted in Figure 5-7 (clock 3) would be illegal.) 5. An example of this potential deadlock is where the lock spans memory locations corresponding to the host system cache lines n and n+1.2.6. As with the complete resource lock and write-back cacheable memory. A locked agent unlocks itself whenever CBLOCK# and CFRAME# are negated.5 Supporting CBLOCK# and Write-back Cache Coherency The resource lock as described earlier has a potential of deadlock when the host system is using a write-back cache. A complete bus lock may have a significant impact on the performance of the system. However.2. This results in a deadlock because the read cannot occur until the modified line is written back and the writeback cannot occur until CBLOCK# ownership is released. Releasing CBLOCK# at any other time may result in a subsequent transaction being terminated with retry unnecessarily. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a lock is in progress.

In all cases except one. or any other target response signal. CSTOP#. CDEVSEL# must be asserted with or prior to the edge at which the target enables its CTRDY#. except to signal target-abort. CCLK 1 2 3 4 5 6 7 8 CFRAME# CIRDY# CTRDY# NO RESPONSE CDEVSEL# FAST MED SLOW SUB ACKNOWLEDGE Figure 5-12 CDEVSEL# Assertion If no agent asserts CDEVSEL# within three clocks of CFRAME#. If the first access maps into the targets address range. CDEVSEL# negation must be coincident with the negation of CTRDY#. 103 © 1999 PCMCIA/JEIDA . the master never sees CDEVSEL# asserted and terminates the transaction per the master-abort mechanism (refer to 5. additionally using byte enables to detect this problem and signal targetabort.ELECTRICAL SPECIFICATION the configuration space Status register.2. a target must assert CDEVSEL# (claim the transaction) before it is allowed to issue any other target response.3.3. (This could cause contention. With normal master termination. and the byte enables indicate one or more bytes of the access are outside the target's address range. once a target asserts CDEVSEL# it must not negate CDEVSEL# until CFRAME# is negated (CIRDY# is asserted) and the last data phase has completed. Once CDEVSEL# has been asserted. the target is required to signal disconnect. In other words.1 Master Initiated Termination). it asserts CDEVSEL# to claim the access. a subtractive decode device (e. it must signal target-abort. To deal with this type of I/O access problem.g. the agent doing subtractive decode may claim and assert CDEVSEL#. It's expected that most (perhaps all) target devices will be able to complete a decode and assert CDEVSEL# within one or two clocks of CFRAME# being asserted (fast and medium in the figure). The exception is the target-abort. or data (read). it cannot be negated until the last data phase has completed.) A target must qualify the CAD lines with CFRAME# before CDEVSEL# can be asserted on commands other than configuration. expansion bus bridge) may do one of the following: • do positive decode (by including a byte map) on addresses for which different devices share common DWORDs. If the system does not have a subtractive decode agent. But if the master attempts to continue the burst access across the resource boundary.. It is illegal to drive CDEVSEL# prior to a complete decode and then let the decode combinationally resolve on the bus. A target must qualify CCBE# and CAD[1::0] with CFRAME# before CDEVSEL# can be asserted on a Configuration command. When a target claims an I/O access. A target must do a full decode before driving/asserting CDEVSEL#.

In some cases it may not be possible to buffer or process all messages that could be received. 104 ©1999 PCMCIA/JEIDA . i. message dependent data. This allows delivery to be guaranteed. and subtractive decoding bridges must not pass this bus operation on to their secondary bus. but is broadcast to all agents. In addition to communicating processor status. As with sideband signaling in general. CAD[31::00] are driven to a stable level and parity is generated. A Special Cycle command may contain optional. The message is encoded on the least significant sixteen lines namely CAD[15::00]. which is not interpreted by the CardBus PC Card interface itself.e. Using a message dependent data field can break the logical wire paradigm mentioned above. (This occurs only when first addressed target resides on the expansion bus and the other is on CardBus PC Card.2. In this case there is no guarantee of delivery. implying that delivery is guaranteed. Normally this buffering is limited to a single flip flop. During the data phase CAD[31::00] contain the message type and an optional data field. CardBus PC Card agents will never assert CDEVSEL# in response to a Special Cycle command. as necessary. since targets only accept messages they recognize and understand.CARDBUS PC CARD ELECTRICAL INTERFACE • pass the full access to the expansion bus. where the portion of the access that cannot be serviced will be ignored. This allows the designer to define necessary sideband communication without requiring additional pins. it may also be used for logical sideband signaling between CardBus PC Card agents. There is no explicit address. The address phase starts like all other commands with the assertion of CFRAME# and completes like all other commands when CFRAME# and CIRDY# are negated. to the hardware application connected to the CardBus PC Card interface. implementation of Special Cycle command support is optional. when such signaling does not require the precise timing or synchronization of physical signals. A good paradigm for the Special Cycle command is that of a "logical wire" which only signals single clock pulses. This command is basically a broadcast to all agents. The optional data field is encoded on the most significant sixteen lines namely CAD[31::16] and is not required on all messages. Special Cycle commands will not propagate across bridges. In most cases. A Special Cycle command is like any other bus command where there is an address phase and a data phase. and create delivery guarantee problems. explicitly addressed messages should be handled in one of the three physical address spaces on CardBus PC Card. The master of a Special Cycle command can insert wait states like any other command while the target cannot (since there is no explicit target). but is passed. and not with the Special Cycle command. This means that there is no target handshaking of any kind on these transactions. the burden is placed on them to fully process the message in the minimum delivery time (six bus clocks) or to provide any necessary buffering for messages they accept. The Special Cycle command contains no explicit destination address.) 5. The information contained in and the timing of subsequent data phases is message dependent. it can be used to set and reset flip flops in real time.. The address phase contains no valid information other than the command field. However. However. The uniqueness of this command compared to the others is that no agent responds with the assertion of CDEVSEL#. and interested agents accept the command and process the request. The message and associated data are only valid on the first clock CIRDY# is asserted. Each receiving agent must determine whether the message is applicable to it.7.2 Special Cycle The Special Cycle command provides a simple message broadcast mechanism on CardBus PC Card.

There are 64 KBytes of messages. When the sequencer reports that the access terminated with a masterabort. The hardware application provides all the information like for any other command and starts the bus sequencer. the master runs the risk of losing its turn on the bus. © 1999 PCMCIA/JEIDA 105 . CCBE[3::0]# = 0001 (Special Cycle) and CAD[31::00] are driven to random values and must be ignored. thereby reducing the ground current load generated by each buffer. the master is required to immediately High-Z its signals because the arbiter has granted the bus to another agent. by delaying assertion of CFRAME#. CPAR is implicitly qualified on each clock after which CAD was qualified. (The new master would be at a higher priority level.e.ELECTRICAL SPECIFICATION During the address phase.) If CGNT# were negated on the clock edges marked B or C.2. and by CIRDY# or CTRDY# in data phases (depending on which direction data is being transferred). One additional clock is required for the turnaround cycle before the next access. Therefore. the hardware application knows the access completed.3 Address/Data Stepping The ability of an agent to spread assertion of qualified signals over several clocks is referred to as stepping. i. The quickest a Special Cycle command can complete is five clocks. thereby reducing the number of signals that must be switched simultaneously.7. But it may take multiple clocks to drive a valid address before asserting CFRAME#. The master is both permitted and required to drive CAD and CCBE# once ownership has been granted and the bus is IDLE. care must be taken to avoid mutual coupling between critical control signals that must be sampled on each clock edge and the stepped signals that may be transitioning on a clock edge. When using the continuous stepping approach.. CFRAME# will have already been asserted. CAD's are qualified by CFRAME# in address phases. Figure 5-13 illustrates a master delaying the assertion of CFRAME# until it has successfully driven all CAD lines. a total of six CardBus PC Card clocks is required from the beginning of a Special Cycle to the beginning of another access. The message encodings are defined and described in Appendix A. and the transaction continues. on the clock edges marked A. Either approach allows an agent to trade off performance for cost (fewer power/ground pins). CGNT# must be asserted on the clock edge before CFRAME# is asserted. Stepping is only permitted on CAD[31::00] and CPAR because they are always qualified by control signals. If CGNT# were negated. An alternative approach allows an agent with strong output buffers to drive a subset of them on each of several clock edges until they are all driven (discrete stepping). This notion allows an agent with weak output buffers to drive a set of signals to a valid state over several clocks (continuous stepping). During the data phase. 5. As with any master. However. these signals are only considered valid on clock edges for which they are qualified. CCBE[3::0]# are asserted and CAD[31::00] are as follows: CAD[15::00] CAD[31::16] Encoded message Message dependent (optional) data field The CardBus PC Card bus sequencer starts this command like all others and terminates it with a master-abort. the Received Master Abort field in the configuration space Status register must not be set. In this case.

4 Configuration Cycle The CardBus PC Card definition provides for totally software driven initialization and configuration via a separate configuration address space. A CardBus PC Card device is a target of a configuration command (read or write) only if CAD[1::0] are 00 during the address phase of the command. or as a burst operation. Internal addressing of the 64-DWORD register space is done by CAD[7::2] and the byte enables. word. As previously discussed.2.CARDBUS PC CARD ELECTRICAL INTERFACE CCLK 1 2 3 4 5 6 7 8 9 CGNT# A A B C CFRAME# CIRDY# CAD ADDRESS DATA-0 CCBE# BUS CMD BE#'s-0 Figure 5-13 Address Stepping 5.3. Register descriptions are provided in the CardBus PC Card Programming Model section of this specification. However. DWORD. like other commands. the request is terminated via master-abort (refer to 5. This section describes the bus commands for accessing the CardBus PC Card configuration space. 106 ©1999 PCMCIA/JEIDA . CardBus PC Card devices are required to provide 256 bytes of configuration space for this purpose.1 Master Initiated Termination).3. accesses in the configuration address space require device selection decoding to be done by the host CardBus PC Card adapter. each device decodes its own addresses for normal accesses. allows accesses of a byte. If no agent responds.7. The Configuration command. The rest of the transaction is the same as other commands. The configuration read and write cycle signals and timing are the same as for other read and write commands. including all termination semantics.2.

the bridge converts the access into a Type 0 configuration access. Type 1 accesses are ignored by all targets except CardBus PC Card-to-CardBus PC Card bridges. the access is ignored. If the Bus Number is not for a bus behind the bridge. The Register Number and Function Number fields have the same meaning for both configuration types. while Device Number and Bus Number are used only in Type 1 accesses. Reserved fields must be ignored by targets. The bridge changes CAD[1::0] to 00 and passes CAD[10::02] through unchanged. Table 5Ð6 Common Access Field Definitions Register Number Function Number Device Number Bus Number is an encoded value used to index a DWORD in configuration space of the intended target. The Device Number is decoded to select one of 32 devices on the local bus.ELECTRICAL SPECIFICATION To support hierarchical buses.. The Function Number is provided on CAD[10::08]. two types of configuration access are used. A Type 0 configuration cycle (when CAD[1::0] = "00") is used to select a device on the bus where the cycle is being run.g. a Type 1 configuration access must be used. Type 0 configuration accesses are not propagated beyond the local CardBus PC Card and must be claimed by a local device or terminated with master-abort. They have the following formats which show the interpretation of CAD lines during the address phase of a configuration access: 31 11 10 8 7 2 1 0 Reserved Type 0 Function Number Register Number 0 0 31 24 23 16 15 11 10 8 7 2 1 0 Reserved Bus Number Device Number Type 1 Function Number Register Number 0 1 Figure 5-14 Type 0 and Type 1 Configuration Accesses Type 1 and Type 0 configuration accesses are differentiated by the values on the CAD[1::0] pins. Host-to-CardBus PC Card) that need to generate a Type 0 configuration cycle use the Device Number to select a CardBus PC Card device. The bridge claims the access if the access is to a bus behind the bridge. A Type 1 configuration cycle (when CAD[1::0] = "01") is used to pass a configuration request on to another bus. © 1999 PCMCIA/JEIDA 107 . is an encoded value used to select one of eight possible functions on a device. is an encoded value used to select 1 of 32 devices on a given bus. If the target of a configuration access resides on another bus (not the local CardBus PC Card). is an encoded value used to select 1 of 256 buses in a system. and the bridge initiates a configuration access to that device. These devices decode the Bus Number field to determine if the destination of the configuration access is residing behind the bridge. If the Bus Number matches the secondary bus number. the access is simply passed through unchanged. CAD[1::0] must be 00 for a Type 0 configuration access. The Register Number is provided on CAD[7::2]. If the Bus Number is not to the secondary bus of the bridge. Bridges (e.

Implementing other functions is optional and may be assigned in any order (i. The first DWORD location (CF8H) references a read/write register that is named CONFIG_ADDRESS. The general mechanism for accessing configuration space is to write a value into CONFIG_ADDRESS that specifies a particular CardBus PC Card in the system. If a single function device is detected. Ô0Õ = disabled) Figure 5-15 Layout of CONFIG_ADDRESS Register The CONFIG_ADDRESS register is 32 bits with the format shown in Figure 5-15 Figure. This mechanism is typically located in the host bridge or the host CardBus PC Card adapter.. Host bridges and host CardBus PC Card adapters to be used in PC-AT compatible systems must implement this mechanism for generating CardBus PC Card configuration cycles. If a multi-function device is detected. then all remaining Function Numbers will be checked.1 Generating Configuration Cycles Systems must provide a mechanism that allows CardBus PC Card configuration cycles to be generated by software. The two classes are differentiated by an encoding in the configuration space header. read-only. The second DWORD address (CFCH) references a register named CONFIG_DATA. Bits 7 through 2 choose a DWORD in the device's configuration space. and configuration register in that device being accessed. The first class (single function device) uses only CAD[1::0] (00) to determine whether or not to respond.2. 5.e. They are also required to always implement function 0 in the device.1.1 Configuration Mechanism Two DWORD I/O locations are used in this mechanism.. the mechanism for generating configuration cycles is defined and specified below.7. Function Number will be zero). Bits 23 through 16 choose a specific CardBus PC Card bus in the system. and only respond to the configuration cycle if they have implemented the configuration space registers for the selected function. Bits 30 to 24 are reserved. Configuration code will probe the bus in Device Number order (i. A read or write to CONFIG_DATA will then cause the bridge to translate that CONFIG_ADDRESS value to the requested configuration cycle on that CardBus PC Card. For PC-AT compatible systems. as well as the encoded value on CAD[10::08] to determine whether or not to respond. device on that bus.e. 5. Bit 31 is an enable flag for determining when accesses to CONFIG_DATA should be translated to configuration cycles on CardBus PC Card. 31 30 24 23 16 15 11 10 8 7 2 1 0 Reserved Bus Number Device Function Number Number Register Number 0 0 Enable bit (Ô1Õ = enabled. a two-function device must respond to function 0. but can choose any of the other possible function numbers (1-7) for the second function).CARDBUS PC CARD ELECTRICAL INTERFACE Devices that respond to Type 0 configuration cycles are separated into two classes. no more functions for that Device Number will be checked.4. For other system architectures there is presently no specification. Multi-function devices are required to do a full decode on CAD[10::08]. 108 ©1999 PCMCIA/JEIDA .4.7. Bits 10 through 8 choose a specific function in a device (if the device supports multiple functions). Bits 15 through 11 choose a specific device on the bus.2. Bits 1 and 0 are read-only and must return 0's when read. The second class of device (multi-function device) understands the Function Number field and uses CAD[1::0] (00). and must return 0's when read.

I/O devices using BYTE or WORD registers are not affected because the cycles will be passed on unchanged. the bridge must return the data in CONFIG_ADDRESS. Bits 10 . it checks the enable bit and the BUS NUMBER in the CONFIG_ADDRESS register. the bridge directly copies the contents of the CONFIG_ADDRESS register onto the CardBus PC Card CAD lines during the address phase of a configuration cycle making sure that CAD[1::0] is 01. dropping the data on writes and returning all ones on reads. Type 1. Type 0. When a bridge sees an I/O access that falls inside the DWORD beginning at CONFIG_DATA address. the bridge must latch the data into its CONFIG_ADDRESS register. In both cases. Figure 5-16 shows the translation from the CONFIG_ADDRESS register to CAD lines on CardBus PC Cards. Accesses to the CONFIG_DATA register are typically handshaken by the bridge doing the configuration translation. The second. the only I/O space consumed by this register is a DWORD at the given address. 31 30 24 23 16 15 11 10 8 7 2 1 0 CONFIG_ADDRESS REGISTER Reserved Bus Number Device Number Function Number Register Number 0 0 Selects a CardBus PC Card CardBus PC Card CAD LINES 31 Undefined 11 10 0 0 1 0 Figure 5-16 Bridge Translation for Type 0 Configuration Cycles For Type 1 translations. is a translation where the device being addressed is on the CardBus PC Card bus connected to the bridge. the bridge does a decode of the Device Number field to access the appropriate device15 and performs a configuration cycle on CardBus PC Card. For systems with peer bridges on the processor bus. byte enables for the data transfers must be directly copied from the processor bus. the bridge must complete the processor access normally.8 of CONFIG_ADDRESS are copied to CAD[10::8] on CardBus PC Card as an encoded value which may be used by components which contain multiple functions. then a configuration cycle translation must be done. The first. Therefore. occurs when the device is on another bus somewhere behind this bridge. For Type 0 translations (see Figure 5-16). © 1999 PCMCIA/JEIDA 109 . 15 If the Device Number field contains an invalid device number. CAD[7::2] are also copied from the CONFIG_ADDRESS register. where CAD[1::0] is 00. Other bridges would snoop the data written to this register. There are two types of translation that take place. If configuration cycle translation is enabled and the BUS NUMBER matches the bridge's bus number or any bus number behind the bridge. one peer bridge would typically be designated to always handshake accesses to the CONFIG_ADDRESS register.ELECTRICAL SPECIFICATION Anytime a host bridge sees a full DWORD I/O write to CONFIG_ADDRESS. On full DWORD I/O reads to CONFIG_ADDRESS. Any other types of accesses to this address (non-DWORD) must be treated like a normal I/O access and no special action should be taken.

2. 110 ©1999 PCMCIA/JEIDA . One register (Bus Number) specifies the bus number of the CardBus PC Card directly behind the bridge. Reads to CONFIG_DATA.7.CARDBUS PC CARD ELECTRICAL INTERFACE Host bridges and CardBus PC Card-to-CardBus PC Card bridges typically require two configuration space registers whose contents are used to determine when the bridge does configuration cycle translation. and drives the data from the I/O write onto CAD[31::00] during the first data cycle. after CONFIG_ADDRESS has been set up this way. The detection and reporting of errors is also required. the generation of parity is required on all transactions by all agents. by definition. 5. The bridge can treat it as a normal configuration cycle operation (i.16 POST code is responsible for initializing these registers to appropriate values. and error reporting. the Device Number is all 1's. and recover from errors.8. If the Bus Number field of CONFIG_ADDRESS does not match the bridge's bus number. 5.e. the Function Number is all 1's. then the bridge is primed to do a Special Cycle the next time the CONFIG_DATA register is written. Byte lanes not actually transferring data are 16 Host bridges that do not allow peer bridges do not need either of these registers since the bus behind the bridge is. 5. During address and data phases. Host bridges are not required to provide a mechanism for allowing software to generate Special Cycles.2. the four byte enables are also included in the parity calculation. and the other register (Subordinate Bus Number) specifies the number of the last hierarchical bus behind the bridge. When the CONFIG_ADDRESS register gets written with a value such that the Bus Number matches the bridge's bus number.8 Error Functions CardBus PC Card provides for parity and other system errors to be detected and reported. To ensure that correct data is transferred. have undefined results.1 Parity Parity on CardBus PC Card provides a mechanism to determine transaction by transaction if the master is successful in addressing the desired target and if the data transfer occurred correctly.4. parity covers the CAD[31::00] and CCBE[3::0]# lines regardless of whether or not all lines carry meaningful information. bus 0 and all other CardBus PC Card buses are subordinate to bus 0.2. then the bridge passes the write through CONFIG_DATA on to CardBus PC Card as a Type 1 configuration cycle just like anytime the bus numbers don't match. To ensure that the correct bus operation is performed. signal. The discussion of errors is divided into the following two sections covering parity generation and detection.1. and the Register Number has a value of zero. When the CONFIG_DATA register is written. To allow this range of flexibility. generate a Type 0 configuration cycle on CardBus PC Card). CardBus PC Card error coverage may range from devices that have no interest in errors (particularly parity errors) to agents that detect. the bridge generates a Special Cycle encoding (rather than configuration write) on the CCBE[3::0]# pins during the address cycle. The agent that is responsible for driving CAD[31::00] on any given bus phase is also responsible for driving even parity on CPAR. the four command lines are included in the parity calculation. Each section explains what is optional and what is required for each function. This allows agents that recover from parity errors to avoid affecting the operation of agents that do not.2 Generating Special Cycles with the Configuration Mechanism This section defines how host bridges that implement the Configuration Mechanism for accessing configuration space should allow software to generate Special Cycles. This will terminate with a master-abort and the processor will have all 1's returned.

This error reporting chain from target to bus master to device driver to device manager to operating system is intended to allow error recovery options to be implemented at any level. Note that other than the one clock lag. some (or all) address lines are not defined but are required to be driven to stable values and are included in the parity calculation. CardBus PC Card provides for the detection and signaling of both parity and other system errors.8. they are reported directly to the system level. The number of "1"s on CAD[31::00]. and CPAR equals an even number. it must be done by all CardBus PC Card compliant devices. During Configuration or Special Cycle commands. Parity generation is not optional. CCBE[3::0]#. Agents that support parity checking must always set the Detected Parity Error field in the configuration space Status register when a parity error is detected.ELECTRICAL SPECIFICATION still required to be driven with stable (albeit meaningless) data and are included in the parity calculation. CPAR is driven by the agent that drives CAD[31::00] and lags the corresponding address or data by one clock. CPAR behaves exactly like CAD[31::00] including wait states and turnaround cycles. The master drives CPAR for the address phases on clock 3 and 7. Parity is generated according to the following rules: • • • Parity is calculated in the same way on all CardBus PC Card transactions regardless of the type or form. Any agent may check and signal an address parity error on CSERR#. Only the master may report a read data parity error and only the selected target may signal a write data parity error.2 Error Reporting. Any additional action beyond setting this field is conditional upon the Parity Error Response field in the configuration space Command register and is discussed in the error reporting section. The target drives CPAR for the data phase on the read transaction (clock 5) while the master drives CPAR for the data phase on the write transaction (clock 8). Checking of parity on CardBus PC Card is required except in one class of devices listed in 5. On any given bus phase.2.2. Figure 5-17 illustrates a read and write transaction with parity. 5. It is intended that parity errors be reported up through the access and device driver chain whenever possible. CCLK 1 2 3 4 5 6 7 8 9 CFRAME# DATA CAD ADDRESS DATA ADDRESS CPAR CPERR# Figure 5-17 Parity Operation Parity must be checked to determine if the master successfully addressed the desired target and if data transferred correctly.8.2 Error Reporting As mentioned. Since it is generally not possible to associate system errors with a specific access chain. © 1999 PCMCIA/JEIDA 111 .

however. Both CPERR# and CSERR# are required pins since parity error signaling on CardBus PC Card is required. Since CPERR# is a sustained tri-state signal.2. as shown in Figure 5-17. all parity error signaling and response is controlled by the Parity Error Response field. at each hardware or software level. it must be actively driven to the correct value on each qualified clock 17 On a write transaction. The following sections cover the responsibility placed on each bus agent regarding signaling on the CPERR# and CSERR# pins. data parity errors in all bus operations except Special Cycle commands. It must be assumed. On a read transaction. and may optionally be used on any other non-parity or system errors.CARDBUS PC CARD ELECTRICAL INTERFACE Two signals are used in the CardBus PC Card error reporting scheme. may be simultaneously driven by multiple agents. Except for setting the Parity Error Detected field. it must remain asserted until two clocks following the actual transfer. the Detected Parity Error field must be set. A master knows a data parity error occurred anytime CPERR# is asserted but only knows the transfer was error free two clocks following the transfer. In all cases. All references to parity errors in this section are by implication limited strictly to data parity (except Special Cycle commands). Since open drain signaling cannot guarantee stable levels on every clock edge. therefore. Bus protocol assures that CPERR# will never be simultaneously driven by multiple bus agents and that proper signal turn around times are observed to avoid any driver contention. Consequently. as well as Special Cycle command data parity errors are reported on the CSERR# signal. It is a sustained tri-state signal and is bussed to all CardBus PC Card agents. CPERR# will be qualified on multiple consecutive clocks accordingly. It is an open drain signal that is wire-ORÕed with all other CardBus PC Card agents and.1 Parity Error Response and Reporting on CPERR# This section describes proper response to. This gives the originator of the access. including address parity. this can occur when CIRDY# is asserted and the target is inserting wait states. CardBus PC Card uses the CPERR# pin to signal a data parity error between connected devices on CardBus PC Card (except on Special Cycle commands). therefore. The agent receiving data is free to assert CPERR# when a parity error is detected (which may occur before data is transferred). If the field is cleared. 112 ©1999 PCMCIA/JEIDA . Note that all agents are required to generate parity. Only the master of a corrupted data transfer is allowed to report parity errors to software. that signaling on CSERR# will generate an NMI and is. the agent ignores all parity errors and completes the transaction as though parity was correct. and may be asserted in any or all of them. Targets always signal data parity errors back to the master on CPERR#. and are described in the next section. In the case of multiple data transfers without intervening wait states. and data parity on Special Cycle commands. 5. CPERR# is used exclusively for reporting data parity errors on all transactions except Special Cycle commands. An agent must always assert CPERR# two CardBus PC Card clocks after a data transfer in which an error occurred. All address parity errors. fatal.8. using mechanisms other than CPERR#.2. the prerogative of recovery. once CSERR# is asserted its logical value must be assumed to be indeterminate until the signal is sampled in the negated state on at least two successive clock edges. the agent is required to assert CPERR# when a parity error is detected. If the field is set. this occurs when CTRDY# is asserted and the master is inserting wait states. and reporting of.17 Once CPERR# is asserted. Use of CSERR# to signal non-parity errors is optional. additional error response is device dependent. CSERR# is used for other error signaling. This field is required except in the previously listed (excluded) devices. care should be taken in using CSERR#.

or not claim the cycle and let it terminate with master-abort.. Any agent can check and signal address parity errors on CSERR#.g. 5.2. Otherwise. an agent may assert CSERR# under the following conditions: • • Address parity error.g. However. it is recommended that both the master and target complete the transaction. it is required to inform the system.ELECTRICAL SPECIFICATION edge. regardless of the error type. The only agent interested in CSERR# (as an input) is the central resource that converts a low pulse into a signal to the processor. errors should be signaled as quickly as possible. but reporting on CSERR# is conditioned on the Parity Error Response field in the Command register. To return it to nominal state at the end of each bus operation. CSERR# may only be asserted when the SERR Enable field in the Command register is set to a logical one (high). A selected agent that detects an address parity error should do one of the following: claim the transaction and terminate with target-abort. or flag). but could include generating an NMI. address parity). or data parity error on Special Cycles detected.2. the agent that asserts CSERR# must be willing for the central resource to generate an NMI.) CPERR# may never be driven (enabled) for the current cycle until at least three clocks after the address phase. status register. © 1999 PCMCIA/JEIDA 113 . When a master detects a data parity error and asserts CPERR# (on a read transaction) or samples CPERR# asserted (on a write transaction) it must set the Data Parity Detected field (Status register.. if the error type is parity (e. starting two clocks after the CAD bus turnaround cycle (e. and all errors other than parity errors.. the error should be reported by a different mechanism (e. It is recommended that the master inform its device driver of the error by generating an interrupt (or modifying a status register or flag to mention a few options). How the central resource signals the processor is system dependent. it must be actively driven high for one clock period. Targets never set the Data Parity Reported field. When the Parity Error Response field is enabled. preferably within two clocks of detection. or setting a status field or flag. bit 8). When CPERR# is asserted. the Parity Error Detected field must be set in all cases. If none of these options is available to the device. data parity errors on Special Cycle commands (since these are broadcast writes).) The CPERR# turnaround cycle occurs one clock later (clock 8 in Figure 5-17.2 Error Response and Reporting on CSERR# CSERR# is used to signal all address parity errors. 18 However. 18 Except for CCLK. regardless of intended master and target. pass responsibility of the error to the operating system by asserting CSERR#. it may. The target is not allowed to terminate with retry or disconnect because an address parity error was detected.8. and the SERR Enable field enabled. regardless of the error type. When an agent asserts CSERR# it is required to set the Signaled System Error field in the configuration space Status register.g. CPERR# is only an output signal for targets while masters use CPERR# as both an input and output. CSERR# has no timing relationship to any CardBus PC Card transaction. an interrupt. When the master of the access becomes aware that a parity error has occurred on its transaction. as a last recourse. high priority interrupt. The detection of a parity error that is not reported by some other mechanism (current bus master only). A target of a transaction that detects a parity error can either continue the operation or cause it to be stopped via target termination. In addition. Note that the system designer may elect to report all parity errors to the operating system by converting all CPERR# error signals into CSERR# error signals in the central resource. clock 7 in Figure 5-17. and can either continue the transaction or terminate it.

It is cacheable by the corresponding agent without any limitations pertaining to presence of CardBus PC Card in the system. both of which must be cacheable by the processor. An agent (a device or a function of the device) can cache its own private memory. ©1999 PCMCIA/JEIDA 2.2. An agent's private memory is not a shared memory. They are as following: 1. The host system's cache coherency must be maintained as if agents on the bus master cards would be accessing the host system memory. The agent is responsible for maintaining its cache and memory data consistency. are outside the scope of this specification. it is not visible to other agents in the system. Also. The first two rules for caching memory in the CardBus PC Card environment (and in the system) are generic. flat physical address space is maintained in the system. 5. Note that master-abort is not an abnormal condition for bridges during Configuration and Special Cycle commands. To make XIP viable. However. and. 114 . any memory mapped into the common address space. part or all of the system memory may reside on CardBus PC Card. is responsible for memory mapping and memory allocation. an agent may assert CSERR# under the following conditions: • • The master (which does not have a driver) was involved in a transaction that was abnormally terminated.e. then this data is not cacheable by that agent. otherwise the execution performance would suffer considerably. The cacheability rules are optimized for systems using removable PC Cards. the system master. This memory must not be shared with other agents (devices) in the system. and providing a mechanism for maintaining the memory and processor cache's data consistency involves some system and CardBus PC Card interface design trade offs. common. the XIP memory on PC Cards must be cacheable. supporting cacheability of the memory residing on PC Cards. a given address has a unique destination and an access of that address produces the same results regardless of the access origin. in a uniform way. Non-modifiable code or data (ROM) can be cacheable. supporting XIP (eXecute In Place) of software stored on PC Cards is an important part of the CardBus PC Card standard. in general. CardBus PC Cards may contain cacheable memory. i. Target-abort is generally an abnormal target termination and may be reported (only by the master) as an error by signaling CSERR# when the master cannot report the error through its device driver. This may include read only program modules as well as RAM. Also note that special memory mapping cases. The assertion of CSERR# should be done with deliberation and care since the result may be an NMI.CARDBUS PC CARD ELECTRICAL INTERFACE When the SERR Enable field is enabled. like the DOS Compatibility Hole.9 Cache Support In a mobile or a small desktop system. • • The host system. including the memory on PC Cards. providing that corresponding code or data in the cache(s) is write protected. Note that this provision does not preclude some private memory spaces in the host system or on PC Cards. This allows for the host system and bus masters on PC Cards to access the system memory and memory on PC Cards. If an agent cannot guarantee write protection of the cached ROM data in its own cache. A catastrophic error that left the agent questioning its ability to operate correctly. The CardBus PC Card memory caching option assumes: • A consistent. CSERR# should not be used for these conditions or for normally recoverable cases.

Cacheability of the card's memory by the host system or by the local agent must be configured by the host system during initialization of the card. disallowed in the card's Configuration Space).10 Clock Control 5.10. or disable caching of that memory. It must be written by the host system during the function configuration. the host CardBus PC Card adapter must forward addresses in the cacheable range to the system bus for snooping. 20CGNT# is not being considered here because it may never be asserted to a card unless the card's CREQ# is asserted. and no bus request (CREQ#20) or lock (CBLOCK#) is asserted by a CardBus PC Card agent. The term local (onboard) memory designates physical memory location. If the agent on the CardBus PC Card caches its local memory.. Also.g. Private memory is not a shared memory. In general.. 19 © 1999 PCMCIA/JEIDA 115 . it does not have to disconnect CardBus PC Card transactions on the cache line boundaries. All accesses to memory Cacheable by the host system must be visible to the host system for maintaining its cache coherency. the agent must disconnect all types of memory transactions (all Memory commands) crossing the cache line boundaries. implement a single. must implement a writable Cache Line Size register (refer to the CardBus PC Card Programming Model Section of this specification).g. all CardBus PC Card addresses should be visible on the system bus.e. If the Cache Line Size register is written to 0. could be logically shared by two or more agents in the system. the agent is released from maintaining the memory caching discipline.1 Clock Frequency The host system is allowed to vary the CardBus PC Card clock frequency.2. with hardware maintained data consistency. 4. 5. that memory must not be cacheable by the host system (e. If zero value is written to the Cache Line Size register. e. it is responsible for its cache and the memory data consistency when any other agent accesses that local memory.ELECTRICAL SPECIFICATION For a read/write shared memory on PC Cards. on a PC Card with another CardBus PC Card agent. as set in the card's Configuration Space). may hard-wire the contents of the Cache Line Size register to zero. An agent containing memory that is not cacheable by the host system. 2. The clock (CCLK) can be stopped by the host system only while the CardBus PC Card interface is idle. The local memory. Contents of this register cannot be hard-wired to any value. it is the responsibility of the host system software to maintain the host system's cache coherency with respect to the memory on the card. Any function in a CardBus PC Card device that contains memory that might be cacheable by the host system. The host system can change the clock frequency only when the CardBus PC Card interface is idle. if the CardBus PC Card and the system bus do not operate concurrently. i. the following cacheability discipline and requirements must be met: 1. The host system may cache memory on a CardBus PC Card if the card configuration allows it (e. or stop the clock without software notification to CardBus PC Card devices. card's address range(s) which represent memory mapped I/O are not cacheable.. The CardBus PC Card central resource (e. and the clock line must remain low until the clock is Private and local memory are not synonyms here. If a non-zero value is written into the Cache Line Size register.g. An agent on a CardBus PC Card may cache only the card's on-board (local19) memory. however. 3.g. Otherwise. the host CardBus PC Card adapter) is the default bus owner.2. while other regions of the card's memory might be cacheable. The clock can be stopped only in a low state. If an agent on the CardBus PC Card caches its local memory. constant clock frequency.

2. 5. A low current pull-up (a keeper) must be provided by the host system to prevent the line from floating. CCLK must not be stopped before the card can request it to continue by asserting CCLKRUN# (refer to 5. The minimum clock cycle time and the minimum clock high and low parameters must not be violated. For example. The device cannot rely on any particular frequency of the clock across the interface.10. The host system should not negate CCLKRUN# if it is not going to stop or slow down the clock. thus preventing the host system from stopping the clock.2. A host system which does not implement this clock control protocol must always assert the CCLKRUN# signal. and the clock edges must be monotonic. It does not necessarily mean the maximum CCLK frequency. after clock 8 (in the timing diagrams.2. 116 ©1999 PCMCIA/JEIDA . 5. Before stopping the clock or slowing the clock down to a non-operational frequency.1 Clock Stop or Slow down The host system (the CardBus PC Card adapter or the clock resource) drives CCLKRUN# low while CCLK is running at a normal operating frequency (refer to Figure 5-18). or about to be started (or brought up to a normal operating frequency) • The CCLKRUN# signal is functional only while power on the CardBus PC Card interface is on.3 Maintaining the Interface Clock). The provisions for variable clock frequency and for stopping the interface clock require the CardBus PC Card device's interface logic to maintain its state.2.CARDBUS PC CARD ELECTRICAL INTERFACE restarted. (See 5. Figure 5-18 and Figure 5-20).3 CardBus PC Card Electrical Specification for the clock specifications).3 are met.2. The host system drives the CCLKRUN# line as following: Negates CCLKRUN# to indicate that the clock is about to be stopped or slowed to a nonoperational frequency. Asserts CCLKRUN# when the interface clock is either: running at a normal operating frequency. the host system synchronously drives CCLKRUN# high for one clock period. When the power is off.2 Clock Control Protocol The CardBus PC Card clock control protocol is implemented using an optional CCLKRUN# signal. CardBus PC Card devices are required to maintain their states while the interface clock is stopped or the clock frequency is changed. To keep the clock running while an internal process on the card is in progress. In addition. 21Normal operating frequency is any frequency at which transactions can be executed across the interface. A PC Card which does not implement the CCLKRUN# signal must leave this pin unconnected. the host system may stop or slow down the clock if the requirements specified in 5.10.2. Devices are not allowed to pulse CCLKRUN# continuously to indicate non-static implementation of their logic. It is up to the host's discretion to establish the operating frequency of the interface at a given time.10.2. the CCLKRUN# line has no meaning. CCLK continues to run unchanged for a minimum of four clock periods after CCLKRUN# is negated. A PC Card asserts CCLKRUN# to request the host system: • • • To restore the interface clock to a normal operating frequency21 if it is stopped or running below this frequency. and then switches its driver to the High-Z state.10. Implementations may disable the pull-up when the host system samples CCLKRUN# low.

Figure 5-19 .10.ELECTRICAL SPECIFICATION CCLK 1 2 3 4 5 6 7 8 9 CFRAME# CIRDY# CCLKRUN# DRIVEN BY HOST PULL-UP ENABLED Figure 5-18 CardBus PC Card Clock Stop or Slow Down 5. the clock can be stopped again by the host system. not more than a few cycles of its internal clock) since this latency would negatively impact the interface performance.2 Clock Restart or Speed up To request restoration of the interface clock. e. Otherwise.) The host system may disable the pull-up on the CCLKRUN# line at this time. The host system drives CCLKRUN# low at any time after it detects that the line is asserted by the CardBus PC Card device. The device may not assert (start driving) CCLKRUN# if it is already driven low by the host system. a device asserts the CCLKRUN# signal asynchronously.. The device holds CCLKRUN# asserted until it detects two rising edges of CCLK (refer to Figure 519 . before the clock was stopped. or brings it to an operating frequency if the clock was slowed down. It is expected that a device which has asserted CCLKRUN# for gaining bus mastership would assert CREQ# no later than four clocks after the clock is restarted. The intent of this protocol is to provide a low latency clock control which is transparent to the host system software.2. After detecting the assertion of CCLKRUN#.2.) After the second clock edge. and which would have no apparent impact on the system performance. but not later than on clock 3 (in the timing diagram. © 1999 PCMCIA/JEIDA 117 . the host system starts the clock if the clock was stopped. the device must disable its open drain driver. The device must not assert CCLKRUN# unless the line has been negated for two successive clocks.g. The host system should provide low latency clock restoration to the interface upon assertion of CCLKRUN# (typically. The host system must not drive CCLKRUN# high earlier than on clock 5.

The host system must not drive CCLKRUN# high earlier than on the fourth clock edge after the CCLKRUN# line was first sampled asserted. All delays in the path to the systemÕs function controlling the clock and to the clock source. (The host system may drive the line low at any time after it detects that CCLKRUN# is asserted by the CardBus PC Card device. This is accomplished by having the device assert CCLKRUN# after it has been negated for two successive CardBus PC Card clocks (refer to Figure 5-20. In Figure 5-20 . 2. The host system must drive CCLKRUN# low on the CardBus PC Card interface no later than on clock 8.2.) The device must assert CCLKRUN# within a certain time window to avoid interruption of the clock stream. The host system must provide a non-interrupted clock when the device asserts CCLKRUN# in the time specified above. The device must not assert CCLKRUN# unless it has sampled the line high on a CCLK rising edge. The device keeps CCLKRUN# asserted for two clocks (clocks 6 and 7.3 Maintaining the Interface Clock Certain devices may require the interface clock to be active for completing some internal processes after a CardBus PC Card transaction is already completed.CARDBUS PC CARD ELECTRICAL INTERFACE CCLK 1 2 3 4 5 6 CCLKRUN# CREQ# PULL-UP ENABLED DRIVEN BY CARD DRIVEN BY HOST Figure 5-19 CardBus PC Card Clock Start or Speed up 5. 118 ©1999 PCMCIA/JEIDA . The clock resource must not stop the clock before a synchronized version of the CCLKRUN# signal received from the device can be generated. or clocks 7 and 8).10. and must drive CCLKRUN# low no later than one Tval after clock 6.2.) 3. The system designer should take into account: 1. the device samples CCLKRUN# high on clock 4. The device may not drive CCLKRUN# if it is already driven low by the host system. and must not drive CCLKRUN# on the same clock edge on which the line is first sampled high. but not earlier than after the turn around cycle which occurs after clock 4. The time required to synchronize CCLKRUN#. and must disable its open drain driver after the second clock.

14 Status Changed (STSCHG#) [I/O and Memory Interface]. Write Protect (WP).2 System and Interface Wake up The CardBus PC Card specification defines an optional system and interface Wakeup protocol using the CSTSCHG line. The CSTSCHG signal on CardBus PC Card is asserted high. When the interface is powered up. These registers are located in memory space at the location given by the CISTPL_CONFIG_CB tuple in the function's Card Information Structure (CIS). The order of the four 32-bit registers is: offset + 0: Function Event.1 Card Status Changed Card Status Changed (CSTSCHG) is an optional signal which is used by PC Cards to notify the host system about such events as changes in the Ready (READY). TPCC_ADDR (CISTPL_CONFIG_CB) must have the Address Space Indicator field set to zero (0) (see also the Metaformat Specification).11.11 Status Changed Notification 5.2.ELECTRICAL SPECIFICATION CCLK 1 2 3 4 5 6 7 8 9 CFRAME# CIRDY# CCLKRUN# DRIVEN BY HOST PULL-UP ENABLED DRIVEN BY HOST DRIVEN BY CARD Figure 5-20 Maintaining CardBus PC Card Clock 5. offset +12: Function Force Event.2.2.4. Each function on a CardBus PC Card provides a set of four 32-bit registers: Function Event. unlike its 16-bit PC Card (STSCHG#) equivalent. refer to 5. offset + 4: Function Event Mask. When the CINT# signal is implemented these registers support Functional Interrupt Notification.11.) CSTSCHG on CardBus PC Card is a level sensitive interrupt which is separate and distinct from the functional interrupt CINT#. 5. When neither CSTSCHG or CINT# signals are implemented these registers provide a consistent interface to CardBus PC Card system software. © 1999 PCMCIA/JEIDA 119 . For description of the registers. (See 4. and Function Force Event. and it is asynchronous to the CardBus PC Card clock.2. offset + 8: Function Present State. Function Event Mask.3 Register Descriptions.11. Function Present State. These registers are sometimes optional in CardBus PC Cards that do not implement the CSTSCHG signal. When the CSTSCHG signal is implemented these registers support Status Changed Notification. or Battery Voltage Detect (BVD[2::1]) conditions of the card. the CSTSCHG line is used to signal the Card Status Changed events. In that case. This protocol allows a CardBus PC Card to request that the system powers up and configures the interface when the interface is powered off.

the card must signal the Card Status Changed interrupt (assert CSTSCHG as a level) if an event field (WP.)(see the CardBus PC Card Electrical Specification and the Requirements for Cards and Sockets sections for CRST# parameters and power cycling requirements). The CSTSCHG signal driven by the card must be current-limited to prevent damage to the card or the host system. In its negated state. must implement the Function Event. After the CardBus PC Card interface is powered up and configured.4. the CSTSCHG line assumes its original Card Status Changed signaling functionality.3. BVD[2::1]) is set in the Function Event register and the corresponding mask field is set in the Function Event Mask register. In order to prevent the system from spurious wake up due to the CSTSCHG signal during a power down process. A CardBus PC Card which uses the CSTSCHG line for a system and/or the interface wake up. When an external event occurs.2 CSTSCHG Requirements. Function Present State and Function Force Event registers. Optionally. After the interface is powered up and configured. the Status Changed is signaled on the CSTSCHG line as a level.7. the power required to drive the CSTSCHG signal must come from either an external source or from some power source on the card itself (e. All fields corresponding to the wake up events in the Function Event. Function Present State and Function Force Event registers. Battery powered cards assert the CSTSCHG signal for a minimum duration of 1 ms to minimize energy drain from on card batteries (especially when the host system is completely powered off or does not support the Wakeup protocol).g. Note that when the CardBus PC Card interface is powered up. must retain their settings throughout power cycling of the CardBus PC Card interface. The host system can mask the CSTSCHG signal on a particular card or on several cards using the Function Event Mask register(s). Function Event Mask.. READY.2 Reset and 5. Also. Signaling Wakeup on the CSTSCHG line is allowed only if the Wakeup (WKUP) field is set and the mask field corresponding to the wake up event is set in the Function Event Mask register by the host system. which implements this Wakeup protocol. Upon detecting of the CSTSCHG signal assertion. a local battery). the system must assert the CardBus PC Card reset (CRST#) before and throughout powering off the CardBus PC Card interface (See also 5. must be able to latch a single CSTSCHG pulse of the minimum duration. not a pulse. the host system which supports this Wakeup protocol is expected to: • • Return the system to an operational state Power up and configure the CardBus PC Card interface The host system must assert the CardBus PC Card reset (CRST#) while powering up the interface. these fields are not effected by the CardBus PC Card reset (CRST#). The required signal parameters are specified in the CardBus PC Card Electrical Specification section. the card drives a single positive pulse on the CSTSCHG line. Function Event Mask. The host system cannot rely on continuous assertion or series of CSTSCHG pulses to be driven by the card when the interface is powered off.CARDBUS PC CARD ELECTRICAL INTERFACE When the CardBus PC Card interface is powered off. 120 ©1999 PCMCIA/JEIDA . The host system.3. CSTSCHG signal is held low. the card may drive CSTSCHG as a high level or series of pulses until the interface is powered up (or until CRST# is negated by the host system).5.

11.2. 5. writes to the associated status register field(s) are ignored. Function Event Mask. Writing "1's" into a field clears the field. writing "0's" has no effect. Such cards cannot implement the system or interface Wakeup protocol. If a Card Status Changed event can occur either when the CardBus PC Card interface is powered up or powered down. The requirements of retaining the field settings throughout power cycling or reset. The host system must not accept spurious signaling on the CSTSCHG line during power cycling of the interface as a valid Status Changed interrupt or the system Wakeup event.11. then the Wakeup functionality must be implemented on the card.1 Function Event Register A CardBus PC Card uses each card function's Function Event register to generate Status Changed interrupts or the host system Wakeup which are signaled on the CSTSCHG line. however.3 Register Descriptions The Function Event. The host system is also responsible for setting or clearing the fields in the Function Event Mask register. do not apply to the cards which do not have any auxiliary power source.ELECTRICAL SPECIFICATION The host system is responsible for reading and clearing the event field(s) in the Function Event register.2. Refer to the table in 5. A field in this register is set when the corresponding field in the Function Present State register changes its value.2. Card Services is responsible for clearing the appropriate fields after determining why the status changed interrupt occurred. The fields in this register. when set. and the card has an auxiliary power source. Card Services must read this register and the Function Present State register to determine the cause of the interrupt. 5.11.3.5 Default Field Values for the values of status register fields returned when a register is read and the associated capabilities are not implemented. When a capability is not implemented. Function Present State. These fields reflect the events which can cause the system (or the CardBus PC Card interface) wake up to be signaled on the CSTSCHG line. indicate that a change in the function status has occurred. The Function Event register can be read or written.3. these fields also reflect the events which are signaled to the host system as Status Changed interrupt on the CSTSCHG line when the interface power is on. © 1999 PCMCIA/JEIDA 121 . and Function Force Event registers have some corresponding fields with the same names. With the exception of the Interrupt request field.

Writing a 1 to this field by the host system clears the field. Interrupt bit field is set (1) when the INTR field in the Function Force Event Register is set. Otherwise. General Wakeup bit field is set (1) whenever the GWAKE field in the Function Present State register changes its state from 0 to 1. If the function can generate system/interface Wakeup when BVD2 changes state.CARDBUS PC CARD ELECTRICAL INTERFACE 31 16 15 14 5 4 3 2 1 0 Reserved Reserved Interrupt (INTR) General Wakeup (GWAKE) Battery Voltage Detect 1 (BVD1) Battery Voltage Detect 2 (BVD2) Ready/Busy (READY) Write Protect (WP) Figure 5-21: CardBus PC Card Function Event Register Bit 0 Field Name WP Description Write Protect bit field is set (1) whenever the WP field in the Function Present State register changes state. then it must also be implemented in this Function Event register and it must not be affected by CRST# or power cycling of the interface. If GWAKE field is implemented in the Function Present State register. this field must be treated as reserved. then this field must not be affected by CRST# or power cycling of the interface. Battery Voltage Detect 1 bit field is set (1) whenever the BVD1 field in the Function Present State register changes state. Battery Voltage Detect 2 bit field is set (1) whenever the BVD2 field in the Function Present State register changes state. WP. or BVD1 fields. Otherwise. the state after reset is 0. then this field must not be affected by CRST# or power cycling of the interface. Writing a 0 has no effect. Writing a 0 has no effect. If the function can generate Wakeup when this field is set. Writing a 0 to this field has no effect. Writing a 1 to this field by the host system clears the field. the state after reset is 0. the state after reset is 0. Writing a 0 has no effect. Otherwise. then this field must not be affected by CRST# or power cycling of the interface. Writing a 1 to this field by the host system clears the field. Writing a 0 has no effect. Otherwise. Writing a 1 to this field by the host system clears the field. the state after reset is 0. Ready bit field is set (1) whenever the READY field in the Function Present State register changes from the busy state to the ready state. then this field must not be affected by CRST# or power cycling of the interface. If the function can generate system/interface Wakeup when BVD1 changes state. READY. Writing a 1 to this field by the host system clears the field. the state after reset is 0. Otherwise. then this field must not be affected by CRST# or power cycling of the interface. This field is used to generate a system or interface Wakeup upon event(s) which are not represented by INTR. These fields are reserved for future use. The host system clears the INTR field by writing a 1 to this field. Writing a 0 has no effect. BVD2. 1 READY 2 BVD2 3 BVD1 4 GWAKE 5-14 15 Reserved INTR 16-31 Reserved 122 ©1999 PCMCIA/JEIDA . These fields are reserved for future use. If the function can generate system/interface Wakeup when WP changes state. If the function can generate system/interface Wakeup when READY changes from busy to the ready state. Otherwise.

Encodings 01 and 10 are not valid for this field. the masking is independent for each function on the card. Otherwise. then this field must not be affected by CRST# or power cycling of the interface. 1 READY 2-3 BVD[2::1] © 1999 PCMCIA/JEIDA 123 . Ready mask. BVD[2::1] Ready/Busy (READY) Write Protect (WP) Figure 5-22: Function Event Mask Register Bit 0 WP Field Name Description Write Protect mask. If the function can generate Wakeup when the BVD1 or BVD2 field in the Function Event register is set. setting of the BVD1 or BVD2 field in the Function Event register will not cause the Status Changed interrupt or the system Wakeup.ELECTRICAL SPECIFICATION 5. enables the BVD1 or BVD2 field in the Function Event register to generate the Status Changed interrupt (and the system Wakeup if the WKUP field in this Function Event Mask register is also set).2 Function Event Mask Register This register gives software the ability to control what events in the function cause the Status Changed interrupts or the host system Wakeup. the state after reset is 0. setting of the READY field in the Function Event register will not cause the Status Changed interrupt or the system Wakeup. enables the READY field in the Function Event register to generate the Status Changed interrupt (and the system Wakeup if the WKUP field in this Function Event Mask register is also set).11. then this field must not be affected by CRST# or power cycling of the interface. Otherwise. This register can be read or written. Setting this field to 1.3. setting of the WP field in the Function Event register will not cause the Status Changed interrupt or the system Wakeup. the Function Event Mask register provides capability to separately mask the system Wakeup signaling. Setting this field to 1. Battery Voltage Detect [2::1] mask. then this field must not be affected by CRST# or power cycling of the interface. If the function can generate Wakeup when the WP field in the Function Event register is set. When cleared (00). When cleared (0). Otherwise. 31 16 15 14 13 7 6 5 4 3 2 1 0 Reserved Reserved Interrupt (INTR) Wakeup (WKUP) PWM Audio Enable (PWM) Binary Audio Enable (BAM) General Wakeup (GWAKE) Battery Voltage Detect. Since each function on a CardBus PC Card contains its own set of registers. the state after reset is 00. Also.2. it enables the corresponding field in the Function Event register to cause a Status Changed interrupt or the system Wakeup. If the function can generate Wakeup when the READY field in the Function Event register is set. When a field is set in this register. the state after reset is 0. Setting this field (11). enables the WP field in the Function Event register to generate the Status Changed interrupt (and the system Wakeup if the WKUP field in this Function Event Mask register is also set). When cleared (0).

Setting this field to 1.. i. If GWAKE field is implemented in the Function Event and Function Present State registers. enables the GWAKE field in the Function Event register to generate the system Wakeup if the WKUP field in this Function Event Mask register is also set. PWM Audio encoded signal is enabled on the CAUDIO pin. When cleared (0). The state after reset is 0. Otherwise. When set (1). Wakeup mask. enables the INTR field in both the Function Present State register and the Function Event register to generate the functional interrupt (and the system Wakeup if the corresponding WKUP field in this Function Event Mask register is also set). nor the system Wakeup while the interface is powered off. These fields are reserved for future use. If the function can generate Wakeup when the INTR field in either the Function Present State register or the Function Event register is set. the Wakeup function is disabled. 5 BAM 6 PWM 7-13 14 Reserved WKUP 15 INTR 16-31 Reserved 5. Setting this field to 1. Interrupt mask. When cleared (0). the state of the CAUDIO pin is undetermined. If the PWM Audio Enable field is also set.3. Binary Audio signal is enabled on the CAUDIO pin. If the function can generate system/interface Wakeup. the state after reset is 0. Otherwise. then this field must not be affected by CRST# or power cycling of the interface. enables the fields in the Function Event register to generate the system/interface Wakeup on the CSTSCHG line (if the corresponding event mask field is also set in this Function Event Mask Register). this field must be treated as reserved. PWM Audio Mode is disabled. Otherwise.11.CARDBUS PC CARD ELECTRICAL INTERFACE Bit 4 Field Name GWAKE Description General Wakeup mask. Binary Audio Enable field. BVD[2::1] Ready/Busy (READY) Write Protect (WP) Figure 5-23: Function Present State Register 124 ©1999 PCMCIA/JEIDA . When cleared (0). The state after reset is 0. setting of the INTR field in either the Function Present State register or the Function Event register will neither cause assertion of the functional interrupt on the CINT# line while the CardBus PC Card interface is powered up. These fields are reserved for future use. 31 16 15 14 5 4 3 2 1 0 Reserved Reserved Interrupt (INTR) General Wakeup (GWAKE) Battery Voltage Detect. If the BAM field is also set. PWM Audio Enable field.2.e. then it must also be implemented in this Function Event Mask register and it must not be affected by CRST# or power cycling of the interface. Setting this field to 1. Binary Audio Mode is disabled. When set (1). When cleared (0). setting a field in the Function Event register will not cause the function to signal the system Wakeup even if the corresponding event mask field is set in this Function Event Mask Register. setting of the GWAKE field in the Function Event register will not cause the system/interface Wakeup.3 Function Present State Register This read-only register reflects the current state of the function. this field must be treated as reserved. then this field must be implemented and must not be affected by CRST# or power cycling of the interface. When cleared (0). the state of the CAUDIO pin is undetermined.

. e. It is cleared (0) by the function when the event has been serviced. If the card is never writeable. This field is not affected by CRST#. If the function can generate Wakeup when BVD[2::1] changes state. it is an address at which the Function Event register can be written. accept a data transfer command. the function is ready to perform a new operation. other events on the card may alter the contents of the Function Event register before it is read..g. the card is write protected (not writeable). This field is not affected by CRST#. When it is set (1). READY.) READY bit field reflects the current state of the function.. the function is busy. Rather. The status is encoded as following: BVD2 1 0 X BVD1 1 1 0 Battery operational Battery needs to be replaced Battery is not providing operational voltage 1 READY 2-3 BVD[2::1] This field is not affected by CRST#. If the function can generate Wakeup when READY changes state. connected to VCC). until the condition which caused the Wakeup request has been serviced.g. then this field must not be affected by power cycling of the interface.g. until the condition which caused the interrupt request has been serviced. primarily for debug purposes. the card is not write protected. When this field is 0. When this field is 0. This field is not affected by CRST#. Battery Voltage Detect [2::1] field reflects the current state of the card's battery. this field must be 0 (e. e. This field remains set (1). These fields are reserved for future use. It is cleared (0) by the function when the event has been serviced. These fields are reserved for future use. or BVD[2::1] fields. processing a previous command or performing initialization. WP.11.g. © 1999 PCMCIA/JEIDA 125 . then this field must not be affected by power cycling of the interface.4 Force Event Capability This provides the ability to simulate events by forcing values in the Function Event register. If the function can generate Wakeup when the interrupt occurs. then this field must not be affected by power cycling of the interface.ELECTRICAL SPECIFICATION Bit 0 Field Name WP Description Write Protect bit field reflects the current state of the Write Protect switch. The effect of a write to this address will be reflected in the Function Event register. connected to GND). 5-14 15 Reserved INTR 16-31 Reserved 5. If the function can generate Wakeup when WP changes state. Note that this is not a physically implemented register. This field remains set (1). However if the function is active. This is done by generating writes to the Function Force Event register.3 Write Protect Function and see also the Metaformat Specification. The value of INTR field is available even if the interrupts have not been configured. the field must be 1 (e.2.6. When it is set (1). If a memory card has no Write Protect switch but the card is always writeable.( See 4..3. 4 GWAKE General Wakeup field reflects the current state of the Wakeup event(s) which are not represented by INTR. then this field must not be affected by power cycling of the interface. Interrupt field represents the internal state of a function specific interrupt request. This field is not affected by CRST# or power cycling of the interface.

Battery Voltage Detect 2. These fields are reserved for future use. Writing a 1 to this bit field simulates a change in the state of the Write Protect switch. the BVD1 field in the Function Present State register is not affected and continues to reflect the current state of the battery. the INTR field in the Function Present State register is not affected and continues to reflect the current state of the functional interrupt. Writing a 0 to this field has no effect. Writing a 0 to this field has no effect. Interrupt. 0. the GWAKE field in the Function Present State register is not affected and continues to reflect the current state of the Wakeup request. However. Writing a 0 to this field has no effect. Ready. and sets the WP field in the Function Event register. Battery Voltage Detect 1. Writing a 1 to this bit field sets the READY field in the Function Event register. However. Writing a 0 to this field has no effect. Writing a 1 to this bit field sets the BVD1 field in the Function Event register. Writing a 0 to this field has no effect. However. Writing a 1 to this bit field sets the INTR field in the Function Event register. Writing a 0 to this field has no effect. 1 READY 2 BVD2 3 BVD1 4 GWAKE 5-14 15 Reserved INTR 16-31 Reserved 126 ©1999 PCMCIA/JEIDA . the READY field in the Function Present State register is not affected and continues to reflect the actual state of the function. However. However. Writing a 1 to this bit field sets the BVD2 field in the Function Event register. the BVD2 field in the Function Present State register is not affected and continues to reflect the current state of the battery.CARDBUS PC CARD ELECTRICAL INTERFACE 31 16 15 14 5 4 3 2 1 0 Reserved Reserved Interrupt (INTR) General Wakeup (GWAKE) Battery Voltage Detect 1 (BVD1) Battery Voltage Detect 2 (BVD2) Ready/Busy (READY) Write Protect (WP) Figure 5-24: Function Force Event Register Bit 0 Field Name WP Description Write Protect. General Wakeup. However. the WP field in the Function Present State register is not affected and continues to reflect the current state of the switch (if it exists). Writing a 1 to this bit field sets the GWAKE field in the Function Event register. These fields are reserved for future use.

The inverse relationship is true for the card's encoder if the audio signal being encoded is from an analog source.05 KHz carrier. depending on capabilities of the host system and the PC Card. Function Event Mask.6448 MHz (or a 22.31 Field Name WP READY BVD2 BVD1 GWAKE BAM PWM Reserved WKUP INTR Reserved Function Event Register clear (0) clear (0) clear (0) clear (0) clear (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) clear (0) Reserved (0) Function Event Mask Register clear (0) clear (0) clear (0) clear (0) clear (0) clear (0) clear (0) Reserved (0) clear (0) clear (0) Reserved (0) Function Present State Register clear (0) set (1) set (1) set (1) clear (0) Reserved (0) Reserved (0) Reserved (0) Reserved (0) clear (0) Reserved (0) 5.ELECTRICAL SPECIFICATION 5. and/or Pulse Width Modulation (PWM) encoded signal. 255 gives DC VCC..0 Vcc (or GND). Bit 0 1 2 3 4 5 6 7 . This relation holds at the system-side decoding point. i. In the Pulse Width Modulation (PWM) mode. or Function Present State registers are read and the capability associated with the field is not implemented in the CardBus PC Card.11. the CAUDIO signal shall be held inactive low.13 14 15 16 . The signal to the speaker should be generated by taking an exclusiveOR of the CAUDIO signals (SPKR# signals from 16-bit PC Cards) from all those cards providing Binary Audio.e. Similarly.2. Binary waveform. i.e. In the first method. it provides a single-amplitude. and when both the card and the system's socket have been configured to enable the signal.05 KHz rollover frequency) are used.. audio waveform intended to drive the host system's loudspeaker).5 Default Field Values The following table indicates the value of each field that shall be returned when the Function Event. if the card's source for the PWM waveform is a digital representation. or if the card does not support the Binary Audio mode.12 Card Audio CardBus PC Card supports two types of audio signals: a single amplitude. and a constant low signal represents 0. A PC Card would normally generate the PWM encoded signal using one of two methods.3. and 127 gives a 50% duty cycle waveform. on-off (binary). 0 gives DC GND. a 50% duty cycle represents 0. The CAUDIO signal may be available only when both the PC Card and the host system support the same type of audio functions. Comparing the two magnitudes creates the PWM signal. © 1999 PCMCIA/JEIDA 127 .e.. CAUDIO provides a PWM encoded signal on a 22. The portion of each 45.5 VCC. CAUDIO provides an interface to the system's speaker using one of the two protocols.3515 µs period during which the signal is held high corresponds to a voltage between GND and VCC. then the input values from 0 to 255 are encoded into a corresponding duty cycle. a set of stored 8-bit values and an 8-bit counter running at 5. When no audio signal is present.2. this signal is identical to the SPKR# signal definition given for 16-bit PC Cards (i. In the Binary Audio mode.

A "5 V component" can be designed to work in a 3. CISTPL_CFTABLE_ENTRY_CB.3 CardBus PC Card Electrical Specification 5.1 Overview This section defines all the electrical characteristics and constraints of CardBus PC Card components. The analog input and a "ramp wave" are used as inputs to a comparator. disable. On the system side. or by summing outputs of multiple integrators.3 V signaling environment. PC Cards which support the Binary Audio mode are required to support the Binary Audio Enable field in the Card Function Event Mask Register and the TPCE_CBMI field in the Configuration Table Entry Tuple.13 Special Design Considerations This section describes other topics related to CardBus PC Card. 5 V or lower for 16-bit PC Cards). and cards.3 V signaling environment and vice versa.2.13. However. Protocol differences between CardBus PC Cards and 16-bit PC Cards make it impossible for both cards to function on the same bus at the same time.3 V or lower for CardBus PC Cards. thereby preventing the processor from handling an interrupt that could be indicating an error condition. This should not be confused with 5 V and 3. Several signals can be summed through multiple isolation capacitors at the input node of the integrator. the bridge does not retry an access.2. the PWM signal is fed into an integrator to re-create the analog waveform. This is not a requirement but is recommended to guarantee that an access will not continue to be terminated with retry. 5.CARDBUS PC CARD ELECTRICAL INTERFACE The second method for generating a PWM signal is using an analog input. 5.3 V. this method can also be used to convert the signal to a store-able digital format. The integrator should work over the frequency range of 50 Hz to 10 KHz. and eventually lower voltage PC Cards. including pin assignment on the PC card connector. should implement a counter such that when the count expires. 5. in general. and the output is the PWM signal. and configure the audio functions on a card by card basis.3. systems. This means that the CardBus PC Card adapter must use the signaling convention of the PC Card in the socket (3. PC Cards which support the PWM Audio mode are required to support the PWM Audio Enable field in the Card Function Event Mask Register and the TPCE_CBMI field in the Configuration Table Entry Tuple. which are not part of the basic operation of the interface. component technologies can be mixed in either signaling environment. supporting 16-bit PC Cards as well as CardBus PC Cards in the same socket implies that the CardBus PC Card adapter must contain universal buffers capable of supporting 5 V. 128 ©1999 PCMCIA/JEIDA . The CardBus PC Card electrical definition provides for a 3.3 V component technologies. CISTPL_CFTABLE_ENTRY_CB. The signaling environments cannot be mixed. The counter is reset whenever the master transfers data.1 Multiple Retry Termination A host CardBus PC Card bridge. This allows the system to selectively enable. Supporting 16-bit PC Cards also means that CardBus PC Card's interconnect between the adapter and the component on the PC Card must not have traces for signals in common between two sockets. If the ramp wave is generated by ramping a digital-to-analog converter (DAC). 3. The counter is incremented (decremented) when an access is terminated with retry.

Specifically. CCLK needs to deliver crisp. The bus driver is actually in the middle of its switching range during this propagation time.3. it is specified in terms of its AC switching characteristics. Static Drive Specification The need to control di/dt noise forces the use of buffers with edge rates slow enough that the interconnect on the motherboard and PC Card do not exhibit transmission line characteristics. but in a CMOS environment these are minimal. Pull-up and pull-down sides of the buffer have separate V/I curves. which are provided with the parametric specifications. The intent of the electrical specification is that components connect directly together. Limits on acceptable V/I curves provide for a maximum output impedance that can achieve an acceptable first step voltage in typical configurations. The shaded areas on the V/I curves shown in Figure 5-25 define the allowable range for output characteristics. it must ensure that CCLK edge rate requirement are satisfied.1 Dynamic vs. The rise and fall times specified provide a range that can deliver signal edge rates that meet timing requirements while keeping the di/dt noise within reasonable bounds. creating a di/dt noise problem that is aggravated by CardBus PC Card's need to switch a high speed. The 3. 5. However. 5.. Therefore CCLK uses a fast edge rate driver sized to switch the bus half way to the required high or low voltage. If the motherboard implementation uses stubs. This connector provides a limited number of ground pins. The DC drive point specifies steady state conditions that must be maintained. positive currents flow into the component while negative currents flow out of the component. so the typical approach of specifying buffers based on its DC current sourcing capability is not useful. and for a minimum output impedance that keeps the reflected wave within reasonable bounds. the initial voltage excursion is doubled to achieve the required voltage level. These V/I curves are targeted at achieving acceptable switching behavior in point-to-point configurations with one load on the motherboard and one on the PC Card. both high going [V oh(AC)]. and is an optimized CMOS approach. both on the PC Card and on the motherboard.1. without any external buffers or other "glue. The sign on all current parameters (direction of current flow) is referenced to a ground inside the component. © 1999 PCMCIA/JEIDA 129 . the voltage to current relationship (V/I curve) of the driver through its active switching range is the primary means of specification. it means that the 68-pin connector must be used. As this electrical wave propagates down the bus and reflects off the unterminated end back to the point of origin.ELECTRICAL SPECIFICATION Finally. 32-bit interface over it. monotonic edges to the PC Card. i.3. which defines an acceptable first step voltage. During each edge. Usage of the same buffer type prescribed for the address/data and control signals would result in uncontrollable clock skew. and low going [Vol(AC)]. This necessitates managing di/dt noise across the interface so that a clean ground reference can be maintained on the card.e. together with required currents to achieve that voltage in typical configurations.3 V environment is based on VCC relative switching voltages. The effective buffer strength is primarily specified by an AC drive point. The CCLK output buffer is specified in terms of its V/I curves. where DC current is minimal. and do not indicate real output drive strength. whether on the planar or a PC Card. CCLK spends this relatively large proportion of time in transient switching." The CardBus PC Card interconnect is estimated as a capacitive load and the address/data and control signal output buffers are specified with respect to driving this load. Instead.2 Component Specifications This section specifies the electrical and timing parameters for CardBus PC Card components.

5. 2. The max value assumes 5 pF for the card trace.1 3.9 VCC 0.3 V signaling. and 1 pF for the connector and vias.7 VCC 0. Input leakage currents include High-Z output leakage for all bi-directional buffers with High-Z outputs. The min value assumes 1 pF for the motherboard trace.3.2 Reset.2 AC Specifications Inputs are required to be clamped to both ground and VCC (3.) 130 ©1999 PCMCIA/JEIDA . 6. and CVS2 do not have to meet leakage requirements.5 0. CCD[2::1]#. CCD2#. (See also 5. CVS1. CCLK values account for longer trace length and additional input capacitance on the input buffer.1 VCC 17 22 22 0. CIS reads to all of these spaces must meet this requirement. 10 pF for the buffer. When dual power rails are used.3. and/or memory space. 3 pF for the buffer.5 0. This specification must be guaranteed by design. 5.2. 3 pF for the buffer. and CVS2 do not have to meet the minimum capacitance requirement. The min value assumes 1 pF for the card trace. These diode paths can become significantly forward biased (conducting) if one of the power rails does not meet specifications momentarily. CVS1. parasitic diode paths could exist from one supply to another. Input High Voltage Input Low Voltage Input Device Turn-off Voltage (high) Input Device Turn-off Voltage (low) Input Leakage Current Output High Voltage Output Low Voltage Card Input Pin Capacitance System Load Capacitance Card CCLK Pin Capacitance 0 < Vin < VCC Iout = -150 µA Iout = 700 µA 5 5 10 0. This only applies to configuration accesses immediately following power-up and reset.3 V Signaling Environment 5. writes to memory space do not. Diode clamps to a power rail. and 2 pF for the connector and vias. However.325 VCC V V V V µA V V pF pF pF 5 6 7 4 3 Condition Min 3. The max value assumes 10 pF for the motherboard trace.3 V) rails.2 VCC +10 VCC + 0.2. This is determined solely by the maximum current capacity of the VCC pins on the connector. 4. It is the Vin value at which current through the input totem pole is essentially shut off.1.3 V Signaling Symbol VCC Icc Icc(CIS) Parameter Supply Voltage Supply current Supply current CIS reads Config reads Config writes Vih Vil Vitoh Vitol Iil Voh Vol Ccard Chost Cclk 1. and 1 pF for the connector and vias.2. CCD1#. expansion ROM.3. Table 5Ð7 DC Specification for 3.0 Max 3.CARDBUS PC CARD ELECTRICAL INTERFACE 5.6 1 70 Units V A mA 1 2 Notes 3. must be able to withstand short circuit current until drivers can be placed in a High-Z state.3.1 DC Specifications Table 5Ð7 summarizes the DC specifications for 3. 7.475 VCC -0. and is only important to devices built for a battery-operated environment.1. and 2 pF for the connector and vias. as well as output pull-up devices. Since CIS can be located in config space.3. Higher current may be drawn after permission has been given by the host system. 10 pF for the buffer.

3.3. This buffer may be realized by using the output buffer specified in the PCI Local Bus Specification. The short circuit output current of the CardBus PC Card's CSTSCHG output buffer must never exceed 1 mA.015 25+(Vin-VCC-1)/0.2.0 1.6 Vcc 0.6 Vcc . Revision 2. 2. The input must be designed to sustain this for an infinite amount of time.3.015 Min Max 1. 5. The following rules provide a framework to ensure that CSTSCHG buffers are implemented properly: 1. A detailed set of AC and DC characteristics are provided in that specification.2 Impedance.2 Vcc -3< Vin < -1 VCC+4> Vin > VCC+1 0. The values ensure the fastest edge rate will not switch rail-to-rail faster than 3.6 ns. © 1999 PCMCIA/JEIDA 131 .4.1.3 V signaling on CCLK. the potential exists for this pin to be shorted to GND through parasitic diodes.0 with a 47 Ω ±10% series termination resistor assuming the motherboard trace impedance is between 60 Ω and 90 Ω. the CSTSCHG pin can be used by the CardBus PC Card to remotely power up the system. Because the system could be powered off.0.ELECTRICAL SPECIFICATION Table 5Ð8 AC Specifications for 3.0 Units V / ns V / ns mA mA Notes 1 1 This does not apply to CCLK.3 V Signaling Symbol trcb tfcb Icl Ich 1. Parameter Output Rise Time Output Fall Time Low Clamp Current High Clamp Current Condition 0. Minimum and maximum rates are measured with the minimum capacitive load a driver will see (7 pF).2 Vcc . The CardBus PC Card trace impedance is specified in 5.0. 5.3 CSTSCHG Buffer Specification As noted in 5. The design of the CardBus PC Card's output buffer and the system's input buffer must ensure no electrical damage results.2. The ESD diodes in the socket's CSTSCHG input buffer must be able to withstand a sustained forward bias current of 1 mA when VCC = 0 V and Vin = 3.25 0.2.25 -25+(Vin+1)/0.1.2 CardBus PC Card Operation.4 CCLK AC Specifications Table 5Ð9 summarizes the AC specifications for 3.6 V.

46 VCC 0.2/VCC)*Vout*(VCC-Vout) for 0V < Vout < 0.1 VCC Vout = 0.1 Vcc 60 Ω load line Current (mA) test point -0. 2. Equations defining these maximums (A.2. In order to facilitate component testing.7 VCC 11.6 Vcc 0.3 V Signaling (CCLK) Symbol Ioh(AC) Parameter Switching Current High (Test Point) Iol(AC) Switching Current Low (Test Point) trclk tfclk 1.2 VCC . Unloaded Output Rise Time Unloaded Output Fall Time Condition 0< Vout<0. because the CCLK interconnect contains many reactive elements.1( VCC-Vout) Min Eqt'n A -11.9 VCC Vout = 0.3 Vcc AC drive point 0.0.7 VCC Equation B: Iol = (36. 2 2 1 1. 132 ©1999 PCMCIA/JEIDA .7 VCC Eqt'n B 9 VCC 4 4 Max Units mA mA mA mA mA mA V / ns V / ns Notes 1 1.. transmission line environment.9 Vcc Voltage DC drive point 0.6 VCC 0.4 VCC) for VCC > Vout > 0.2 Vout -5 VCC -7.6 VCC> Vout>0. B) are provided with the respective diagrams in Figure 5-25. and in general must be treated as a non-terminated. The equation defined maximum should be met by design. Maximum current requirements must be met as drivers pull beyond the first step voltage (AC drive point).8/VCC)*(Vout-VCC)*(Vout+0.3 VCC< Vout<0.0.3 VCC 0.1.5 6. 2 2 Refer to V/I curves in Figure 5-25. a maximum current test point is defined for each side of the output driver.5 -5 Vcc -13.3 V Signaling 5.7 VCC VCC> Vout>0.7 Vcc Current (mA) 11. The basic premise of the environment requires that a signal reflect at the end of the line and return to the driver before the signal is considered switched. Pull Up Vcc 60 Ω load line Pull Down Vcc test point Voltage AC drive point 0.8 Vcc 1.6 VCC 0.9 Vcc Equation A: Ioh = (35.2 VCC 1 1 6.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð9 AC Specification for 3.5 Maximum AC Ratings and Device Protection (CCLK) A maximum AC test specification is included here as a testing recommendation.3.5 Vcc DC drive point 0.6 VCC .46 VCC Figure 5-25 V/I Curves for 3.

For example. The technology used to implement CardBus PC Card can vary from vendor to vendor. Methods which slow the edge rate but create large shunt currents through the output stage will simply replace the switching current with VCC current without correcting the di/dt noise problem.6 V 7. Note that this also means that the technique used to slow the edge rates must actually reduce the CardBus PC Card's di/dt requirements.3. so it can not be assumed that the technology is naturally immune to these effects.5 V Undershoot Test Waveform Voltage Source Impedance R = 28 Ω Figure 5-26 Test Waveform for 3. against which the long term reliability of a device can be evaluated. i. This test covers the AC operating conditions only. The test is conducted with the equivalent of a zero impedance voltage source driving a series resistor directly into CCLK. p-to-p (minimum) . This test specification provides a synthetic worst case AC environment. These inputs to the CardBus PC Card should be capable of continuous exposure to the following test. The waveform provided by the voltage source (or open circuit voltage including the resistor) and the resistor value is provided in Figure 5-26. p-to-p (minimum) R DUT Test Setup 4 nS (max) 0V V 30.1 V.0 nS (33 MHz) + 3.1 V.ELECTRICAL SPECIFICATION As a consequence of this environment.1.3 V Signaling (CCLK) 5. © 1999 PCMCIA/JEIDA 133 . device topology. DC conditions are specified elsewhere.6 Noise Considerations As noted earlier. as long as many signals switching slowly is equivalent to a few signals switching quickly.. adding source resistance to the P-channel and N-channel devices of a series of strong buffers will deliver performance which meets the description above when many signals are switching but will exhibit fast edge rates when just a few switch.1 V 7. etc. Overshoot Test Waveform Voltage Source Impedance R = 29Ω 11 nS (min) + 7.2.3. This is acceptable as long as the overall current being driven across the connector remains constant. The technique(s) used to reduce this noise may exceed the signal edge rates specified in Table 5Ð8 under some conditions.e. board impedance. under certain conditions of drivers. the primary consideration in designing a buffer for CardBus PC Card is managing the di/dt noise caused by the limited number of AC return paths (VCC and GND) on the 68-pin connector. the open circuit voltage at the pins of CardBus PC Card devices will exceed the ground to VCC voltage range expected by a considerable amount.

(See Table 5Ð7 DC Specification for 3.1 Clock Specifications The clock waveform must be delivered to each CardBus PC Card component in the system.3.) 5. not at the connector slot.2. In general.4 Vcc. If the clock is stopped.) The grounded shroud connector is required for CardBus PC Card implementations. In the case of CardBus PC Cards. compliance with the clock specifications is measured at the card component. 8.2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform (See Figure 5-27.2. di/dt noise shall not exceed Vil. it must be in a low state. A variance on this specification is allowed for the CardBus PC Card adapter which may operate the CardBus PC Card interface at any single fixed frequency up to 33 MHz. CardBus PC Card Connector Test Methodology.CARDBUS PC CARD ELECTRICAL INTERFACE In all cases.) 134 ©1999 PCMCIA/JEIDA . The clock frequency may be changed at any time during the operation of the system so long as the clock edges remain clean (monotonic) and the minimum cycle and high and low times are not violated.325 Vcc 0.3 V Signaling.2 Timing Specification 5. Rise and fall times are specified in terms of the edge rate measured in V / ns.475 Vcc 0. all CardBus PC Card components must work with any clock frequency up to 33 MHz. 3.4 Vcc 0. (See the Physical Specification and see also Appendix-B.2 Vcc 0. and may enforce a policy of no frequency changes. Table 5Ð10 summarizes the clock specifications. p-to-p (minimum) tlow Figure 5-27 CardBus PC Card Clock Waveform Table 5Ð10 CardBus PC Card Clock Specifications Symbol tcyc thigh tlow 1. Parameter CCLK Cycle Time CCLK High Time CCLK Low Time CCLK Slew Rate Min 30 12 12 1 4 Max ∞ Units ns ns ns V / ns 2 Notes 1 2.3.6 Vcc 0.3 Volt Clock tcyc thigh 0. Figure 5-27 shows the clock waveform and required measurement points.

"CCLK Stable" means that VCC is within tolerances (See Table 5Ð7 DC Specification for 3.2 Timing Parameters Table 5Ð11 provides the timing parameters for the 3. Maximum tval is measured from CCLK crossing Vtest to the signal's last transition out of the threshold region (Vil for falling edges. must reduce the CCLK frequency appropriately.2. 5. Vih for rising edges). 2. maximum times are specified with 30 pF equivalent load. 2 1 1 3 3 4 4 4.3.3.2 Reset. 5 6 tval includes the time to propagate data from internal registers to the output buffer and drive the output to a valid level. Systems which exceed this capacitance.).3 Measurement and Test Conditions Vth Vtest Vtl tval(min) CCLK OUTPUT DELAY tval(max) Vih Vil High-Z OUTPUT Vtest ton toff Vtest Figure 5-28 Output Timing Measurement Conditions © 1999 PCMCIA/JEIDA 135 .3 V Signaling. Table 5Ð11 3.2. Minimum tval is measured from CCLK crossing Vtest to the signal crossing Vih on falling edges and Vil on rising edges. CRST# is asserted asynchronously and negated synchronously with respect to CCLK.3 V Timing Parameters Symbol tval ton toff tsu th trst trst-clk trst-off tpulse 1.3. Actual test capacitance may vary. This parameter only applies when signaling remote wakeup over the CSTSCHG pin. 3.2. 4.3 V signaling environment. All other status change information must be signaled by asserting CSTSCHG until the resultant interrupt is serviced.3. 5.2.) See 5. but results should be correlated to these specifications.ELECTRICAL SPECIFICATION 5. due to long traces between the socket and adapter.) and CCLK is meeting specifications (See Table 5Ð10 CardBus PC Card Clock Specifications. tsu and th are measured at Vth for rising edges and Vtl for falling edges. 6.2 Signal/Pin Description for the CardBus PC Card and adapter signals which must be in a High-Z state. Minimum times are specified with 0 pF equivalent load. Parameter CCLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Set up Time to CCLK Input Hold Time from CCLK Reset Active Time After Power Stable Reset Active Time After CCLK Stable Reset Active to Output float delay CSTSCHG remote wakeup pulse width 1 7 0 1 100 40 Min 2 2 28 Max 18 Units ns ns ns ns ns ms clocks ns ms Notes 1. (See also 5.1.

325 VCC 0. Input V/I curves. Two curves should be given for each output type used: one for driving high. This plot should also show best-typical-worst curves over the range of -3 to 7 V. and PC Card vendors should make the following information available in their data sheets: • • • Pin capacitance for all pins Pin inductance for all pins Output V/I curves. as well as provide complete information.3.3 V signaling. Vmax specifies the maximum peak-to-peak waveform allowed for testing input timing. the other for driving low. Both should show best-typical-worst curves. To help facilitate this effort. This will ensure that system implementations are manufacturable and that components are used correctly.3 V Signaling 0.2. component.2 VCC 0. A V/I curve of the input structure when the output is in a High-Z state is also important. many system vendors will do board-level electrical simulation of CardBus PC Card components.4 VCC 0. etc. • • • 136 ©1999 PCMCIA/JEIDA . Timing parameters must be met with no more overdrive than this. so the voltage range should span -3 to 7 V for 3.CARDBUS PC CARD ELECTRICAL INTERFACE Vth CCLK tsu Vtest Vtl th Vth INPUT Vtl inputs valid Vih Vil Vmax Figure 5-29 Input Timing Measurement Conditions Table 5Ð12 Measurement and Test Condition Parameters Symbol Vth Vtl Vih Vil Vtest Vmax 1. connector. "beyond-the-rail" response is critical. Note that AC switching characteristics may be necessary depending on how the buffer is designed. Unloaded rise/fall times for each output type Complete absolute maximum data.6 VCC 0. Also.125 VCC of overdrive. including operating and non-operating temperature.3 V environment is done with 0. 5.3 Vendor Provided Specifications In the time frame of CardBus PC Card.475 VCC 0. DC maximums. 3.4 VCC Units V V V V V V 1 Notes 1 1 The input test for the 3.

Therefore. To correctly evaluate clock skew. Table 5Ð13 Clock Skew Parameters Symbol Vtest tskew 3.4. This specification applies not only at a single threshold point.e. not to the connector. After CRST# is asserted.3.Vih range. i. © 1999 PCMCIA/JEIDA 137 . The CardBus PC Card specification does not preclude the implementation of a fully synchronous CRST#.) The Tfail parameter provides for system reaction to any of the power rails failing to meet specifications momentarily. CardBus PC Card components are not considered reset until both trst and trst-clk parameters have been met. but at all points on the clock edge that fall in the switching range defined in Table 5Ð12 and Figure 5-30.3. The value of tfail is 500 ns (maximum) from any power rail going out of specification.3 V Signaling 0. In all cases.4 VCC 2 (max) Units V ns Vih CCLK (@Device #1) Vil tskew Vtest tskew tskew Vih Vil CCLK (@Device #2) Vtest Figure 5-30 Clock Skew Diagram 5. The maximum skew is measured between any two components22. the system designer must take into account clock distribution on the CardBus PC Card. if desired. power down.2 Reset The assertion of the CardBus PC Card reset signal (CRST#) is asynchronous with respect to CCLK while the negation is synchronous.3 V Timing Parameters. which is specified in Section 5. This occurs between two components that have clock input trip points at opposite ends of the Vil . (See Table 5Ð11 3.3. exceeding specified tolerances by more than 500 mV.1 Clock Skew The maximum allowable clock skew between the CardBus PC Card and the CardBus PC Card adapter is 2 ns.3. (See Figure 5-31. CRST# is asserted upon power failure in order to float the output buffers. this can add to the clock skew measurement as described here.3.ELECTRICAL SPECIFICATION 5. Both edges of the CRST# signal must be monotonic through the input switching range.3. If this occurs.) 22There may be an additional source of clock skew with which the system designer need be concerned. parasitic diode paths could short circuit active output buffers elsewhere in the system. The system must assert CRST# during power up.3 System (Motherboard) Specifications 5. or in the event of a power failure. total clock skew must be limited to the specified number. In certain circumstances.

CARDBUS PC CARD ELECTRICAL INTERFACE POWER Vnominal . ensure that floating inputs. the existence of 16-bit PC Cards and protocol in this interface complicates this because some of the pull-ups needed on the host system for CardBus PC Card conflict with pull-downs required on 16-bit PC Cards. CREQ#. not just the control signals. CGNT#. However. Whatever scheme is chosen. CIRDY#. the system designer must 1. This requirement applies to all adapter inputs. CINT#. or use an alternative means such as gated input structures. use "switchable" pull-ups which can be disconnected when 16-bit PC Cards are present.3. CSTOP#. This is often accomplished through the use of pull-up resistors on the motherboard. the system designer must eliminate the need for these pull-ups. CBLOCK#. CPERR#. 138 ©1999 PCMCIA/JEIDA . do not create a crossover current in the adapter's input structure. This guarantees that cycles are not falsely detected and that input structures will not oscillate due to input voltages remaining in the threshold region for long periods of time. CCLKRUN#. caused by an empty socket. CSTSCHG and. 2.3 Pull-ups CardBus PC Card control signals must always contain stable values when no agent is actively driving the bus.X% tfail )( CCLK 100 ms (typ) PWR_GOOD )( trst-clk CRST# )( trst trst-off CARDBUS PC CARD SIGNALS High-Z Figure 5-31 Reset Timing 5.3. CSERR#. CDEVSEL#. when used. Note that pull-up resistors are always required for CSERR# and CINT# because they are open-drain outputs. CTRDY#. and CAUDIO. ensure stable values on all signals at all times when a transaction is not in progress. Therefore. This includes CFRAME#.

The pull-ups on CIRDY#. In this case. the adapter must begin driving these signals when the bus is sampled idle and set them to a High-Z state.3. and CSTOP# may be eliminated if the adapter ensures the signal is always driven when the bus is idle. CTRDY#. as appropriate. The range of resistance values allowed for the 3. 5.3. alleviating current draw when an 16-bit PC Card is present. during the address phase. Rmin. 3. whereas the number of loads only has a secondary effect. 2.3 V signaling) Signaling Rail 3. the adapter must begin driving one clock after the CardBus PC Card releases it and set it to a High-Z state during the same cycle CGNT# is asserted.3. two clocks after CFRAME# is sampled asserted.3 V signaling environment are provided in Table 5Ð14. Rmax. In this case. 6.8 KΩ Rmax 45 KΩ 5. Table 5Ð14 Minimum and Maximum Pull-up Resistor Values (3.1 Pull-up Values for Control Signals The minimum pull-up resistance value allowed.3. the maximum value allowed. the adapter must begin driving on the fourth clock after the last data phase and set it to a High-Z state.ELECTRICAL SPECIFICATION The pull-up resistors on certain CardBus PC Card signals can be removed when the following conditions are met: 1. In this case. 5. if the adapter guarantees the signal will not be in a High-Z state when a CardBus PC Card is present. but the actual value is a function of how much power drain is desired when a PC Card is present. The pull-up on CRST# may be eliminated. is primarily driven by Iol. as appropriate. The pull-up on CPERR# may be eliminated if the adapter ensures the signal is always driven when the bus is idle. The equations for calculating this are: © 1999 PCMCIA/JEIDA 139 .3. The pull-up on CBLOCK# may be eliminated if the adapter ensures the signal is always driven when the bus is idle. the DC low output current. 4. In this case.3 V Rmin 4. the adapter would always drive this signal low when a CardBus PC Card is present. CDEVSEL#.2 Pull-up Values for Card Detect and Voltage Sense Pins The CCD1# and CCD2# pins require pull-up resistors either on the motherboard or integrated in the socket adapter. The minimum resistance implemented is recommended to be consistent with Table 4Ð19 Electrical Interface.3. On the other hand. is primarily driven by the number of loads present. The maximum resistance implemented must be sufficient to hold the CCD1# and CCD2# inputs at a valid Voh level when no PC Card is present and the CCD[2::1]# pin is drawing its maximum rated leakage current. The pull-up on CCLKRUN# may be eliminated if clock stopping is not implemented and the adapter never places this signal in a High-Z state. The pull-down on CSTSCHG may be eliminated as long as the adapter implements the pull-up required for 16-bit PC Cards and ensures that remote wakeup isn't falsely signaled when the socket is empty.

and Large enough so that the socket adapter's CVS1 and CVS2 buffers are not damaged by excessive currents when the inserted PC card has one of the CVS[2::1] pins shorted to ground. Refer to Table 4Ð19 Electrical Interface for specific resistance values.3 V signaling environment When driving high. The ON resistance of the CVS[2::1] pin driving low in a CardBus PC Card adapter can be calculated using the following relationship: Rvsl(min) = 0 Rvsl(max) = (Vil(max))(Rcd(min))/(VCC(max) .3. The location and type (pull-up. 140 ©1999 PCMCIA/JEIDA . Small enough to deliver a valid Voh level to the CVS[2::1] and CCD[2::1]# inputs. The adapter must implement CVS1 and CVS2 so that a valid Vol can be delivered to the CCD1# and CCD2# inputs of the socket adapter.6 V for the 3. The ON resistance of the CVS[2::1] pins is a function of the Rcd resistance.Vil(max)) where Vil(max) is for the adapter's CCD[2::1]# and CVS[2::1] inputs Rcd(min) is the minimum value used for Rcd VCC(max) is 3.3 Pull-up Resistor Requirements The signal differences between the 16-bit PC Card and CardBus PC Card interfaces can lead to different requirements regarding the location of pull-up and pull-down resistors on both the host system and on cards. and the input threshold used for those pins. pull-down) of resistor for each connector pin is summarized in the following table. the CVS[2::1] output's on resistance must be: 1.3.3. Note that the time required to achieve a valid Voh is related to on resistance by the RC time constant of the CVSX and CCDX# interconnect. The ON resistance of the CVSX pin driving high can be calculated using the following relationship: Rvsh(max) = Vih(min)/(Iil(max) for CCDX# + Iil(max) for CVS[2::1]) Rvsh(min) = function of the CVS[2::1] output buffer specification 5. the leakage characteristics of the CCD[2::1]# and CVS[2::1] pins. 2.CARDBUS PC CARD ELECTRICAL INTERFACE Rcd(max) = Vih(min)/Iil(max) where Vih(min) and Iil(max) are for the adapter's CCD[2::1]# pins Rcd(min) = recommended to be greater than 10 KΩ.

support for 16-bit PC Card interface cards still necessitates the presence of the resistor.3.3 Pull-ups are met. I/O and Memory GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# IREQ# VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND CardBus PC Card Interface GND CAD0 CAD1 CAD3 CAD5 CAD7 CCBE0# CAD9 CAD11 CAD12 CAD14 CCBE1# CPAR CPERR# CGNT# CINT# VCC VPP1 CCLK CIRDY# CCBE2# CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 RFU CCLKRUN# GND Note 2 Note 2 pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-up pull-up Note 2 pull-down pull-down pull-down pull-down pull-down pull-up pull-down pull-up pull-down pull-down pull-down pull-down pull-down pull-up pull-up Host Resistors 16-bit PC Card Only CardBus & 16-bit PC Card PC Card Resistors 16-bit PC Card CardBus PC Card The pull-up can be integrated into the adapter's CVS[2::1] output buffers.3. However. © 1999 PCMCIA/JEIDA 141 .ELECTRICAL SPECIFICATION Table 5Ð15 Pull-up/Pull-down Resistor Requirements Pin Name 16-bit PC Card Interface Memory-Only GND D3 D4 D5 D6 D7 CE1# A10 OE# A11 A9 A8 A13 A14 WE# READY VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND 1. 2. The CardBus PC Card interface does not require the host system pull-up if the conditions outlined in 5.

The pull-up can be integrated into the adapter's CVS[2::1] output buffers. 2.3. I/O and Memory GND CD1# D11 D12 D13 D14 D15 CE2# VS1# IORD# IOWR# A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND CardBus PC Card Interface GND CCD1# CAD2 CAD4 CAD6 RFU CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 RFU CBLOCK# CSTOP# CDEVSEL# VCC VPP2 CTRDY# CFRAME# CAD17 CAD19 CVS2 CRST# CSERR# CREQ# CCBE3# CAUDIO CSTSCHG CAD28 CAD30 CAD31 CCD2# GND pull-up pull-up Note 3 pull-up pull-up Note 2 pull-down pull-down pull-down pull-up pull-up pull-up Note 1 Note 2 pull-up pull-up pull-up pull-up Note 2 pull-down pull-down pull-down pull-down pull-up Note 2 Note 2 Note 2 pull-up Note 1 pull-up pull-up pull-down pull-down pull-down pull-down pull-down pull-up pull-up pull-down pull-down pull-down pull-down pull-down pull-up Host Resistors 16-bit PC Card Only CardBus & 16-bit PC Card PC Card Resistors 16-bit PC Card CardBus PC Card 3. However.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð16 Pull-up/Pull-down Resistor Requirements Pin Name 16-bit PC Card Interface Memory-Only GND CD1# D11 D12 D13 D14 D15 CE2# VS1# RFU RFU A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2# RESET WAIT# RFU REG# BVD2 BVD1 D8 D9 D10 CD2# GND 1.3 Pull-ups are met. PC Cards must pull-up BVD2 (pin 62) to avoid sensing a battery low condition. support for 16-bit PC Card interface cards still necessitates the presence of the resistor. The CardBus PC Card interface does not require the host system pull-up if the conditions outlined in the 5.3. 142 ©1999 PCMCIA/JEIDA .

CCLK must be compensated for the routing delay on the CardBus PC Card.3. During reset. the system designer must make sure © 1999 PCMCIA/JEIDA 143 . Signals that must cross from one domain to the other should be routed on the opposite side of the board so they are referenced to the ground plane. 5.4 Power Sequencing The system must assert CRST# both at power up.6. the two planes should be capacitively tied together (motherboard plane decoupled directly to CardBus PC Card plane) with 0. the length and signal velocity must allow a valid logic level to be presented at the far end of the trace within the specified amount of time. Valid output delay (t val) and input setup time (tsu) are specified by the component specifications while total clock skew (tskew) is a system parameter.6. The split in the plane disrupts the AC return path for the signal..3.4.3. This means that signal timing can be measured anywhere on the net with equivalent results.3.3.2 Physical Requirements. However. Due to edge rate constraints. whereas the actual pin capacitance may be used for the CardBus PC Card adapter. While this is a standard technique. and signals must be routed over the plane split.3. Because of the edge rate restrictions in this specification. (See also 5. the maximum pin capacitance must be assumed for PC Cards. which is not split.6 Physical Requirements Traces between the CardBus socket connector pad and the CardBus PC Card adapter may be stubbed as long as loading and etch characteristics are not compromised and the stub is short enough that it does not behave as a transmission line. A recommended solution is to arrange the signal level layouts so that no high speed signal (e.3.1.2 Motherboard Impedance There is no bare board impedance specification for motherboards. If this is not possible. creating an impedance discontinuity. 5. 5.01 µF high-speed capacitors for each four signals crossing the split.2 Signal/Pin Description.g. and whenever the VCC rail does not meet specifications. careful attention must be paid to maximum trace length and loading of CardBus PC Cards. This allows system designers to directly validate interface timings at the connector for all signals except CCLK. making propagation time across the interface negligible.25 inches (6. All stubs shall have a length of 2 inches (50. (See 5. CardBus PC Cards will not operate in a transmission line environment.3. CardBus PC Card will not be operating in a transmission line environment. routing high speed signals directly over this plane split can cause signal integrity problems. and that the capacitor be placed not more that 0.) Also.) 5.3. However. some motherboards may employ a split power plane especially in light of the cold insertion requirements.8 mm) or less.ELECTRICAL SPECIFICATION 5.1 Routing and Layout of Four Layer Boards All CardBus PC Card interface signals are required to be referenced to the host system supplied rails.35 mm) from the point the signals cross the split. The total clock period can be divided into three segments.3. all CardBus PC Card signals are driven to their benign state.5 System Timing Budget When computing a total CardBus PC Card load model. Therefore.3. CCLK) is referenced to both planes. Signal traces should remain entirely over one plane or the other.

3. 5. is exempt from this rule since it must be referenced to an external power supply.4.5 + 2. 5.3.1 inches (63.5 inches ± 0.3. but no other power supply may be used to power the interface.1 Decoupling Under typical conditions.2.3.54 mm) and must be routed to only one load. used to initiate remote wakeup.3.4.4.2 External Power Supplies All signals which pass through the CardBus PC Card connector shall switch between the ground and VCC levels which are provided to the interface by the host system.25 inches (6. 5.4 CardBus PC Card Specifications 5.1 mm). additional local decoupling will still be needed for components on the PC Card. The trace length for the CCLK signal is 2.2 Impedance The unloaded characteristic impedance (Z0) of the signal traces on the CardBus PC Card shall be controlled to be in the 60 .1 Power Requirements 5. and the CardBus PC Card adapter does not exceed the capacitance specified in Table 5Ð7.4.3.4. 5. any stubbed components.4.1 Trace Length Limits Trace lengths from the CardBus PC Card connector pad to the CardBus PC Card device are as follows: • • The maximum trace lengths for all interface signals are limited to 1. The host system VCC may be used to power PC Card functions other than the interface.2. CSTSCHG. Any signal translation to/from signals referenced to other power supplies must be performed by the PC Card/system maker in such a way that it is invisible to the interface.5 inches (38.3.CARDBUS PC CARD ELECTRICAL INTERFACE the capacitance presented by the motherboard trace. However. Those supplies shall be used to provide the current sink/source capacity for all such signals and reference for semiconductor substrates and clamping diodes which may be forward biased by CardBus PC Card interface signals. the VCC plane to ground plane capacitance will provide adequate decoupling for the VCC connector pins.2 Physical Requirements 5.3 V signaling convention to avoid interoperability problems. 144 ©1999 PCMCIA/JEIDA .1.1. The maximum trace length from a connector pad to the VCC/GND plane via shall be 0. The trace velocity must be between 150 and 190 ps/inch (381 and 483 ps/cm).90Ω range. This CardBus PC Card output must always use the 3.35 mm) assuming a 20 mil trace width.

g.3. Violation of CardBus PC Card trace length or loading limits will compromise system signal integrity. unless they are placed behind a CardBus PC Card-to-CardBus PC Card bridge. separate address and data path components. 5. configuration space (required to be present) memory space I/O space expansion ROM • Each function has the following defined and standardized logical spaces. (See the Card Services Specification. Use a CardBus PC Card component that has more than 10 pF capacitance per pin (12 pF for CCLK).. All logical spaces are accessible by software clients.3 Signal Loading CardBus PC Card signals must be limited to one load on the expansion card. Attach any logic (other than a single CardBus PC Card device) that snoops CardBus PC Card pins. Use CardBus PC Card component sets that place more than one load on each CardBus PC Card pin. The CardBus PC Card system programming environment extends the existing 16-bit PC Card software model as required to support the new features of CardBus PC Card. It is specifically a violation of this specification for CardBus PC Cards to: • • • • • Attach an expansion ROM directly (or via bus transceivers) to any CardBus PC Card pins.4.3 Register Descriptions) A CardBus PC Card is required to have at least one function. 2. Each function is composed of one or more of the following physical spaces: 1. The presence and location of other functions and physical spaces © 1999 PCMCIA/JEIDA 145 .4. configuration header space Ñ corresponds physically to the first 64 bytes of the configuration space. status registers Ñ located physically in memory space.2. 5. If implemented.4 CardBus PC Card Programming Model 5. functions 0-7 must each have a separate configuration space. (See also 5. Additionally.11.2 Card Organization A CardBus PC Card's organization may be viewed in the following hierarchy: • • The card is divided into one or more functions. the CardBus PC Card programming model continues to support 16-bit PC Cards.1 Overview CardBus PC Cards operate in a dynamic environment similar to 16-bit PC Cards. There may be up to 8 functions associated with a card. 4. 3.ELECTRICAL SPECIFICATION 5. Attach two or more devices on a CardBus PC Card. This section describes the organization of a CardBus PC Card which drives many of the decisions concerning programming model design.) 1.2. 2. e. Each function is required to implement a configuration space.4.

This requires that a Memory Base Address Register be provided for each I/O Base Address Register or set of I/O Base Address Registers. It does not. Note that 16-bit PC Card mappings only apply to 16-bit PC Cards and Base Address Register mappings only apply to CardBus PC Cards. 16-bit PC Card mappings are supported on the same adapter with Base Address Register mappings. In this case the actual address space is still uniform. all CardBus PC Card I/O spaces must be mappable into host memory space. as presented to both cards and system. even when a portion of the card space described by the Base Address Register is unpopulated. refers to a unique location in this address space. CardBus PC Card has a 32-bit uniform address space. For CardBus PC Card systems. meaning that a given address. refer to some offset within an individual card space. Card spaces do not share their host system addresses with other card spaces. Instead. A card space is not mappable in finer granularity than that described by its associated Base Address Register. to support processor independence. An actual host system address space may be less than that which would be created by a full 32-bit address space. This eases the addressing required for bus mastering by allowing the bus master to present addresses which do not require further translation. for example.CARDBUS PC CARD ELECTRICAL INTERFACE on the card is determined via a combination of the presence of configuration space registers and the descriptions included in the function's CIS. A card space is mapped into the host system address space by assigning a host system address to the Base Address Register for the card space. Thus the Base Address Register uniquely identifies the card space's location in the global system address space. 146 ©1999 PCMCIA/JEIDA . any CardBus PC Card address bits which exceed the host system address space must be 0. A Base Address Register maps the beginning of a given card address space into Host System address space. The following figures provide mapping examples of the various spaces on a CardBus PC Card using the Base Address Register mapping paradigm. but cards must be mapped into the reduced address space. In addition. each CardBus PC Card space is individually mappable via its corresponding Base Address Register. There is no simple direct analogy between CardBus PC Card memory spaces and 16-bit PC Card Common and Attribute Memory address spaces.

with the I/O Base Address Register (or Registers) immediately preceding the memory Base Address Register. to avoid inadvertent double mapping. or a contiguous set of I/O Base Address Registers may be followed by a single memory Base Address Register which maps all of the I/O spaces described by the set. These Base Address Registers must be provided in order.ELECTRICAL SPECIFICATION Host System Host System Memory Address Space Memory Base Address Register I/O Base Address Register Memory Base Address Register Card Memory Space 2 I/O Space Memory Base Address Register Expansion ROM Base Address Memory Space 1 Device Dependent Region Expansion ROM Figure 5-32 Card with Memory and I/O Space in Host System with no Separate I/O Space Figure 5-32 shows a card with I/O space in a host system having no separate host I/O space. rather than the I/O Base Address Register which is not supported by the host system.e. i. there may be a memory Base Address Register following each I/O Base Address Register to map the I/O space. © 1999 PCMCIA/JEIDA 147 . requiring that the card space be memory-mapped. This is accomplished by using the memory Base Address Register corresponding to that space.

CARDBUS PC CARD ELECTRICAL INTERFACE Host System Host System Memory Address Space Memory Base Address Register Card Memory Space 2 Memory Base Address Register Expansion ROM Base Address Memory Space 1 Device Dependent Region Expansion ROM Figure 5-33 Memory-only Card in Host System 148 ©1999 PCMCIA/JEIDA .

ELECTRICAL SPECIFICATION A PC Card is not required to have any I/O spaces. Note that the card I/O space could be memory-mapped as in Figure 5-32. © 1999 PCMCIA/JEIDA 149 . which is another optional component of a CardBus PC Card. In this example. Host System Host System I/O Address Space Host System Memory Address Space Card I/O Space 1 I/O Base Address Register Memory Base Address Register I/O Base Address Register Memory Base Address Register I/O Space 2 Device Dependent Region Figure 5-34 I/O Space-only Card in a Host System with a Separate I/O Space Figure 5-34 depicts a card that has I/O spaces and no memory spaces in a system with a separate host I/O space. an expansion ROM is included. as in Figure 5-33. and thus might contain only memory spaces.

2 CardBus PC Card Operation. Tuples may reside in any card space except I/O space and the first 64 bytes of configuration space. For complete information on tuple definitions and tuple chain traversal.4.) These registers are located in that function's memory space at the location given by the CISTPL_CONFIG_CB tuple in that function's CIS. see the Metaformat Specification. The programming model for CardBus PC Card takes into consideration all of the above spaces.1 Configuration Space The CardBus PC Card configuration space is a 256 byte memory region which is accessed during a configuration access cycle.) 5. both in describing what types of configuration information may reside where and in defining how card and system software may gain access to a given space. (See 5. and using both host system memory space and a separate host I/O space. (See the Metaformat Specification. Each function on a CardBus PC Card has a set of four status registers associated with it.CARDBUS PC CARD ELECTRICAL INTERFACE Host System Host System I/O Address Space Host System Memory Address Space Memory Base Address Register I/O Base Address Register Memory Base Address Register Memory Base Address Register Card Memory Space 2 I/O Space Expansion ROM Base Address Memory Space 1 Device Dependent Region Expansion ROM Figure 5-35 Card and Host with All Spaces Described Figure 5-35 shows a card having all of the allowable card spaces.2. Configuration space is divided into two parts: 150 ©1999 PCMCIA/JEIDA .

The purpose of the "Allocated" registers is to maintain compatibility between CardBus PC Card and other environments. a device-dependent region which is always physically present.ELECTRICAL SPECIFICATION • • a mandatory 64 byte predefined header. CardBus PC Card system software must not make use of any of the information which may be stored in these "Allocated" fields. "Allocated" indicates that the register is not defined for CardBus PC Card and must not be redefined as other environments may use the register. "Reserved" indicates that the register is reserved for future use. but which might not be implemented by the card and used by its software. The CardBus PC Card configuration space is as described in Figure 5-36. Cards have a separate configuration space for each implemented function. Following the figure each element is defined. © 1999 PCMCIA/JEIDA 151 .

CARDBUS PC CARD ELECTRICAL INTERFACE All unimplemented registers must return all 0's when read. However.13 Register Summary.4. Registers which are marked "Allocated" may contain readable values.) 152 ©1999 PCMCIA/JEIDA .2. 31 16 15 0 Allocated Status BIST Allocated Command 00h 04h Allocated Header Type Latency Timer Base Address Register Base Address Register Base Address Register 08h Allocated Cache Line Size 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h Pre-Defined Header 64 bytes Base Address Register Base Address Register Base Address Register CIS Pointer Reserved Expansion ROM Base Address Reserved Reserved Allocated Allocated Interrupt Pin Beginning of Device Dependent Space Cap_Ptr Allocated 34h 38h 3Ch 40h 44h Device Dependent Space 192 bytes Tuple Space Tuple Space End of Device Dependent Space FFh Figure 5-36 CardBus PC Card Configuration Space CardBus PC Card header fields and registers are defined in the following sections.1. these values will be ignored by all CardBus PC Card software and no programmatic interface is provided with which to access them. (See also 5.

At this time (after the card is reset) the client and/or the system software may reconfigure the card as necessary. functions for which no I/O accesses are possible should not implement a writable field at location 0. the Fast Back-to-Back Enable field will contain an appropriate value based on the capabilities of the system. after the card reset is complete. After a card is mapped into the host system.1. all fields in the Command register are reset (given a value of 0). Additionally. Figure 5-37 shows the layout of the register and Table 5Ð17 explains the meanings of the different fields in the Command register. 15 10 9 8 7 6 5 4 3 2 1 0 Reserved Fast Back-to-Back Enable SERR# Enable Wait Cycle Control Parity Error Response VGA Palette Snoop Memory Write and Invalidate Enable Special Cycles Bus Master Memory Space I/O Space Figure 5-37 COMMAND Register Layout © 1999 PCMCIA/JEIDA 153 . After the CRST# signal is asserted. Configuration accesses are required to be supported by all functions on all cards as a minimum level of functionality. When this register has a value of 0.ELECTRICAL SPECIFICATION 5. Individual fields in the Command register may or may not be implemented depending on a function's use.1 Command This register specifies a function's ability to generate and respond to the different access cycles possible for CardBus PC Card. system software will enable the appropriate accesses (memory and/or I/O) by setting the memory and/or I/O bits in the Command register.4. the function accepts only configuration accesses. For instance.2.

VGA compatibles must implement this field.2. Functions must generate parity even if their parity checking mechanism is disabled. If set. If reset. the SERR# output buffer is enabled. the function responds to memory space accesses. Reserved. the function must ignore any parity error that it detects and continue normal operation. If a card always does stepping. or never does it. For instance.4. write the value 0100000000000000B to the register. then the card is accepting only configuration accesses. the function may behave as a bus master. Specifies how the function responds to parity errors. when a parity error is detected. This field and the Parity Error Response field at location 6 must both be set in order for address parity errors to be reported. If the I/O Space field is reset and this field is reset. This will be set by system software if the adapter and the card are fast back-to-back capable. (See Figure 5-38: STATUS Register Layout and Table 5Ð18 STATUS Register Field Definition.) Functions implement fields based on the presence of functionality. Specifies whether a function can act as a master on the bus. This controls whether or not the SERR# output buffer is enabled. If set. masters may generate the command. to clear the field at location 14 and not affect any other fields. Specifies whether this master may generate the Memory Write and Invalidate command. This register can be read without side-effects. If set. 154 ©1999 PCMCIA/JEIDA . the function should treat palette accesses like all other accesses. the card does stepping. the function does not respond to I/O space accesses. This controls whether or not a card does address/data stepping. This controls whether or not a master can do fast back-to-back transactions to different devices. fast back-to-back transactions are only allowed to the same agent. If reset.1. the function responds to I/O space accesses. If reset. special palette snooping behavior is enabled (i. the master is allowed to generate fast back-to-back transactions to different agents.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð17 COMMAND Register Field Definitions Bit 0 Field Name I/O Space Description Specifies whether a function responds to I/O space accesses. This field must be implemented by masters that can generate the Memory Write and Invalidate command. except for the DEVSEL# Timing and Fast Back-to-Back Capable bit fields which are read-only. This field has the same value for all of the functions on a card. should not implement the Signaled Target Abort field at location 11. Specifies whether a function responds to memory space accesses. Writes are slightly different in that fields can be reset. the function may not generate bus accesses. If reset. 1 Memory Space 2 3 Bus Master Special Cycles 4 Memory Write and Invalidate Enable 5 VGA Palette Snoop 6 Parity Error Response 7 Wait Cycle Control 8 SERR# Enable 9 Fast Back-to-Back Enable 10-15 5. If reset. All functions must implement this field. A field is reset whenever the register is written and the data in the corresponding location is a 1. If the Memory Space field is reset and this field is reset. If set. the SERR# output buffer is disabled. After a card reset all implemented fields in this register are reset. and should not implement fields they will not use. If set. All functions must implement this bit field. Specifies how palette registers are handled by VGA compatibles. If set. the field must be read/write and must be initialized to 1 after the card is reset. If set. If reset. If reset. For cards that can do either. Memory Write must be used. If set.2 Status This register holds run-time status information for bus related events. a function which acts as a target but will never signal target-abort. If reset.e. however. the function may monitor Special Cycle operations. then the card is accepting only configuration accesses. the function must take whatever action is defined for it in that event. If reset. the function must not respond). then this field may be read-only. the function does not respond to memory space accesses. If set. If reset. but not set. For instance. If set. the function ignores all Special Cycle operations. Specifies whether a function responds to Special Cycle operations. the card does not do stepping.

All masters must implement this field.ELECTRICAL SPECIFICATION 15 14 13 12 11 10 9 8 7 6 5 4 0 Reserved Extended Capabilites Support Fast Back-to-Back Capable Data Parity Dectecte CDEVSEL# Timing 00 . If set. is terminated with master-abort. 01b for medium. (3) the Parity Error Response bit field (Command Register) is set. indicates this device supports the PCI Extended Capabilities feature and the Capabilities Pointer at offset 34h should be used to locate the offset to the first data structure. This field must be set whenever the function asserts CSERR#. even if parity error handling is disabled.medium 10 . This field is only implemented by bus masters. Functions that will never signal target-abort do not need to implement this field. This field must be set by a target whenever it terminates a transaction with targetabort. This field encodes the timing of CDEVSEL#. then three conditions must have been met: (1) the bus agent asserted CPERR# itself or observed CPERR# asserted.fast 01 . 5-6 7 8 Data Parity Detected 9-10 CDEVSEL# Timing 11 12 13 14 15 Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error © 1999 PCMCIA/JEIDA 155 .slow Signaled Target Abort Received Target Abort Received Master Abort Received System Error Detected Parity Error Figure 5-38: STATUS Register Layout Table 5Ð18 STATUS Register Field Definition Bit 0-3 4 Extended Capabilites Support Field Name Description Reserved If set. This field must be set by a master whenever its transaction. Reserved Fast Back-to-Back Capable This read-only field indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. If set. This field is readonly and must indicate the slowest time in which a card asserts CDEVSEL# for any bus command except Configuration Read and Configuration Write. the function can accept these transactions. This field must be set by the function whenever it detects a parity error. If reset. See the PCI Bus Power Management Specification for CardBus Cards section for further definition of extended capability. the function cannot accept these transactions. This field must be set by a master whenever its transaction is terminated with targetabort. except for Special Cycles. The three allowable timings are encoded as 00b for fast. (2) the agent setting the bit field acted as the bus master for the operation in which the error occurred. All masters must implement this field. and 10b for slow (11b is reserved).

1. This register is set by Card Services to inform the card what size is supported by the system. software must guarantee coherency if it is cached. A typical implementation would be to build the five high-order bits (leaving the bottom three as read-only). If set.1. all cacheable functions on a card will have the same value for Cache Line Size.4 Latency Timer This register specifies. in units of bus clocks. but the hardwired value must be limited to 16 or less.CARDBUS PC CARD ELECTRICAL INTERFACE 5. 7 6 5 4 3 0 Completion Code Reserved Start BIST BIST Capable Figure 5-39 BIST Register 156 ©1999 PCMCIA/JEIDA .4. Functions that do not support BIST must always return a value of 0 (i.4. If reset. 00H. Bits 6 through 0 specify the layout of bytes 10H through 3FH. Table 5Ð19 defines the BIST register fields. One encoding.e. 5. the value of the Latency Timer for this bus master.1. This register may be implemented as read-only for cards that burst two or fewer data phases. Bit 7 indicates that the card has multiple functions.2.4. resulting in a timer granularity of eight clocks. Bit 7 in this register is used to identify a multi-function card. Figure 5-39 shows the layout for the BIST register. A function whose BIST is invoked should not prevent normal operation of the bus. treat it as a reserved register). is 0.6 Built-in Self Test (BIST) This optional register is used for control and status of BIST. This header layout allows compatible information to be stored for both CardBus PC Card configuration spaces and those used by other environments.3 Cache Line size This register specifies the system cache line size in units of 32-bit words. A size of 0 generally indicates that the memory spaces of this function is not cacheable.1. Every card must contain function 0.e.2. The remaining encodings (1-127) are reserved for future use. then the card has a single function.2. Functions participating in the caching protocol use this register to know how to disconnect burst accesses at cache line boundaries. This register must be implemented by masters that can generate the Memory Write and Invalidate command. 5. i. which is defined by the system.4. is defined and specifies the layout of the pre-defined header space shown in Figure 5-36. The default value of the non-read-only fields of this register when the card is reset is 0.2. Each function on the card has a configuration space including the pre-defined header. 5.5 Header Type This register identifies the layout of bytes 10H through 3FH in configuration space and also whether or not the card contains multiple functions. Since this register indicates the level of system support.. This register must be implemented as writable by any master that can burst more than two data phases. The default value of this register when the card is reset.

the only way to access memory or I/O space on a CardBus PC Card from a host system is via the Base Address Registers. 31 4 3 2 1 0 Base Address 0 Prefetchable Type Memory Space Indicator Figure 5-40 Base Address Register Mapping for Memory Space The Prefetchable field is set by the card if the following are all true: • • • There are no side effects on reads. is in a disabled state.4. A Base Address Register that contains a zero value. No access shall be accepted by a card for a Base Address Register with bits (31:4) set to zero. invoke BIST. The Type field indicates valid placements in memory space for the mapping. The layout for a Base Address Register referring to a memory mapping is given in Figure 5-40. but will not be participating in CardBus PC Card's caching protocol. Reserved. A value of 0 means the function has passed its test. function is not BIST capable.2. A linear frame buffer in a graphics device is an example of a range which should be marked prefetchable. If reset. If set.7 Base Address Register These registers provide the beginning Host System address for mapping CardBus PC Card memory and I/O spaces into the Host System. Function-specific failure codes can be encoded in the non-zero value. Non-zero values mean the test failed. i. BIST is complete. The field must be reset otherwise. Since it is not required that all CardBus PC Card host systems implement a separate I/O space.. memory-mapped I/O. © 1999 PCMCIA/JEIDA 157 . 5.1.ELECTRICAL SPECIFICATION Table 5Ð19 BIST Register Fields Bit 7 6 5-4 3-0 Completion Code Field Name BIST Capable Start BIST Description If reset.e. should mark the range as prefetchable. Any function that has memory which behaves like normal memory. There are a maximum of six Base Address Registers per configuration space. CardBus PC Card does not require that any Base Address Registers be implemented in a CardBus PC Card function. Such mappings use Base Address Register windows. in bits (31:4). Host bridges can merge processor writes into this range without causing errors. Test fails if BIST is not complete after 2 seconds. All base address registers must be have bits (31:4) set to zero by assertion of CRST#. function supports BIST. However. Only reset is supported. The function returns all bytes on reads regardless of the byte enables. The values are defined as below in Table 5Ð20. If set. A Base Address Register may refer to either a memory or an I/O mapping. any I/O space on a CardBus PC Card must be able to be mapped into the host system memory address space.

2.2.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð20 Meaning of the Type Fields for a Memory Base Address Register Bits 2/1 00 01 10 11 Meaning Base Address Register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.1. 5. The number of upper bits that a function's configuration space actually implements in this Base Address Register depends on how much of the address space to which the memory associated with that Base Address Register will respond. the number of upper bits implemented indicates directly the size of the mapping required and leads to a power-of-2 sizing and alignment for the mapping. the number of upper bits implemented indicates directly the size of the mapping required and leads to a power-of-2 sizing and alignment for the mapping. The function may in fact decode all 32 bits of a presented address.8 CIS Pointer This read-only register points to where the CIS begins. In other words. The memory Base Address Register associated with the I/O space(s) immediately follows the I/O space(s)'s I/O Base Address Register(s) in configuration space. Expansion ROM space Ñ may be in any of the images. memory space Ñ may be in any of the memory spaces. with the first starting at offset 10H. 31 2 1 0 Base Address 0 1 Reserved I/O Space Indicator Figure 5-41 Base Address Register Mapping for I/O Space Bits 0-1 of an I/O Base Address Register are read only.4. in one of the following spaces: • • • 158 configuration space Ñ must begin in device-dependent space at or after location 40H. There are six DWORD locations allocated for Base Address Registers.2. for those cards implementing an I/O space there will be. ©1999 PCMCIA/JEIDA . The layout for a Base Address Register referring to an I/O mapping is given in Figure 5-41. Therefore.) The number of upper bits that a function's configuration space actually implements in this Base Address Register depends on how much of the I/O space to which this function will respond. Allocated.2 Addressing. This results in 16 byte alignment for CardBus PC Card base memory addresses. All CardBus PC Cards implementing I/O spaces must to be able to be memory-mapped as well as mapped via I/O Base Address Registers. at least 1 memory Base Address Register to also map the space. as well as any I/O Base Address Registers mapping that space(s). (See also 5. which allows a one (1) byte granularity to be supported without waiting the extra cycle for a byte enable. Base Address Register is 32 bits wide but must be mapped below 1M (Real Mode mapping) in memory space. This results in 4 byte alignment for CardBus PC Card I/O addresses. Reserved Bits 0-3 of a memory Base Address Register are read only. In other words.

For example. The value consists of the remaining bytes. The value is the offset of the start of the CIS from the base of that image. This is the offset into the memory address space governed by Base Address Register x. at which the CIS begins.2 Required CIS. The image is the image number used as the location reference for the start of the CIS. The address in device-dependent configuration space at which the CIS starts. (See Table 5Ð22 Address Space Offset Values.) Table 5Ð22 Address Space Offset Values Address Space Indicator 0 x. Adding this value to the value in the Base Address Register gives the location of the start of the CIS. 7 expansion ROM Note that the above definition ensures that no properly implemented CIS Pointer register will ever have the value 0. 1 ≤ x ≤ 6 Space Type configuration space memory space Address Space Offset Values 40H ≤ value ≤ F8H. pointed to by the CIS Pointer in its configuration space. It is required that each function in a multi-function CardBus PC Card have this register implemented and that the pointer indicates the location of a valid CIS. if the value is 2.3. Adding this offset plus the starting offset of the image to the value in the Expansion ROM Base Register gives the location of the start of the CIS. into the address space indicated by the Address Space Indicator field. The CIS begins in the Expansion ROM space. (See 5. This is the offset into the expansion ROM address space governed by the Expansion ROM Base Register. The image number is in the uppermost nibble of the Address Space Offset.ELECTRICAL SPECIFICATION Each configuration space of a multi-function card must have its own CIS. then the CIS begins in the memory address space governed by Base Address Register 2. Table 5Ð21 Address Space Indicator Values Value 0 1-6 7 Meaning CIS begins in device-dependent configuration space.) © 1999 PCMCIA/JEIDA 159 . 0 ≤ value ≤ 0FFF FFF8H. 31 28 27 3 2 1 0 Address Space Offset ROM Image Address Space Indicator Figure 5-42 CIS POINTER Layout The Address Space Indicator field indicates in which of this function's address spaces the CIS begins.5. The encoding for this pointer is given below in Figure 5-42. The CIS begins in the memory address space governed by one of the six Base Address Registers. 0 ≤ value ≤ FFFF FFF8H. 0 ≤ image ≤ FH. The value of the Address Space Offset gives the offset. The encoding for this field is given below in Table 5Ð21.

This register is read-only.4. that a function's configuration space actually implements depends on what address alignment the function supports.11 Interrupt Pin The Interrupt Pin register tells whether or not the function uses the interrupt pin.2. Note that when multiple functions exist on a CardBus 160 ©1999 PCMCIA/JEIDA . Functions which don't use the interrupt pin must reset this register. out of the upper 21 bits. Functions that support an expansion ROM must implement this register.4. If the PCI Extended Capabilities feature is not implemented. The number of bits. When set. even if the Expansion ROM is a read-only device.2. A CardBus PC Card device responds to such write accesses as if it was a successful transaction (CDEVSEL# and CTRDY# asserted. See the PCI Bus Power Management Specification for CardBus Cards section for further definition of extended capability. this field indicates that address decoding is enabled using the parameters in the other part of the register.1. in bits (31:11). a CardBus PC Card device must also respond to a write access to the Expansion ROM.2. The write data should be ignored and should not affect the operation of the CardBus PC Card device. When reset. Functions which do use the interrupt pin must set this register. Since the Expansion ROM Base Address Register controls all accesses to the Expansion ROM. this value is 0. 5.4. It represents an offset from the beginning of the PCI Configuration Space into the Configuration Space where the first data structure will be found.1. The register functions exactly like a 32-bit Base Address Register except that the encoding and usage of the lower bits is different. This allows a function to be used with or without an expansion ROM depending on system configuration. No access shall be accepted by a card for the Expansion ROM Base Address Register with bits (31:4) set to zero.4. the function's expansion ROM address space is disabled.10 Cap_Ptr The 8-bit Capabilities Pointer at location 34h is used to point to the beginning of the first PCI defined Extended Capabilities data structure. The Memory Space field in the Command register has precedence over the Expansion ROM Enable field. Figure 5-43 shows how this register is organized.(See also 5.2. The Expansion ROM Base Address Registers must be have bits (31:11) set to zero by assertion of CRST#. 31 11 10 1 0 Expansion ROM Base Address Reserved Address Decode Enable Figure 5-43 Expansion ROM Base Address Register Layout The field at location 0 in the register is used to control whether or not the function accepts accesses to its expansion ROM.9 Expansion ROM Base Address Register The 4-byte register at offset 30H in configuration space is defined to handle the base address and size information for an expansion ROM.CARDBUS PC CARD ELECTRICAL INTERFACE 5. A function will only respond to accesses to its expansion ROM if both the Memory Space field and the Expansion ROM Base Address Enable field are set.4 Expansion ROM. with CSTOP# negated).) An Expansion ROM Base Address Register that contains a zero value. 5.1. is in a disabled state.

(See the Card Services Specification.1. The knowledge provided by this register or field may be available to the client via the Card Services interface.this register or field does not give information about or control the card to system interface. Tuple space must begin with a CISTPL_LINKTARGET tuple.this register or field either gives information about or controls the card to system interface. 5.1. The columns in Table 5Ð23 have the following meanings: Register Field Mandatory Function Unique the name of the register in CardBus PC Card configuration space. each function could give this register or field a different value. © 1999 PCMCIA/JEIDA 161 . if applicable. NO .12 Tuple Space The device-dependent configuration space of a CardBus PC Card may contain a tuple chain. This tuple chain may start anywhere on or after 40H in configuration space and must be contiguous until a CISTPL_END is reached. YES . NO .4. based on the function.the function's client software is allowed to read from or write to this register or field. YES . Additionally.the register or field is required. YES . However. for some of the registers.the register or field is optional. the separately accessible field in the register.within a multi-function card.4. (See the Metaformat Specification.CardBus PC Card system software is expected to read from or write to this register or field.ELECTRICAL SPECIFICATION PC Card and more than one uses the interrupt pin and these functions are concurrently enabled.13 Register Summary All of the registers defined above may be accessed by CardBus PC Card system software. In fact.2. NO .it is required that this register or field be given the same value by all functions on the card.2. the CardBus PC Card system software will provide the client with an access API.) NO . it would be possible to alias all of the occurrences of this register or field in all of the functions to the same physical register. the functions share the interrupt pin. YES .) 5. the client does not directly read from this register or field.) Table 5Ð23 below gives a summary of the usage characteristics of the configuration space registers. This tuple chain may contain a LongLink tuple to another tuple chain in another space associated with that function.CardBus PC Card system software is not expected to read from or write to this register or field. Interface Control System Software (Read/Write) Client Software (Read/Write) YES . (See the Card Services Specification. NO .the function's client software does not access this register or field.

as defined for 16-bit PC Cards. Each CardBus PC Card memory device is mapped into host system address space via one of the six Base Address Registers in configuration space.2 Memory Space While there is no Attribute Memory. This includes the 16-bit PC Card window mapping 162 ©1999 PCMCIA/JEIDA . the CardBus PC Card programming model must support 16-bit PC Card memory mapping mechanisms as well as the Base Address Register mappings used for CardBus PC Cards.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð23 Configuration Space Register Usage Summary Register Field Command I/O Space Memory Space Bus Master Special Cycles Memory Write and Invalidate Enable VGA Palette Snoop Parity Error Response Wait Cycle Control SERR# Enable Fast Back-to-Back Enable Status Extended Capability Support Fast Back-to-Back Enable Data Parity Detected DEVSEL# Timing Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error Cache Line Size Latency Timer Header Type BIST Base Address Register Expansion ROM Base Register Interrupt Pin CIS Pointer YES YES YES YES YES YES NO YES YES YES YES YES NO YES NO YES NO NO NO NO YES YES YES YES NO NO NO YES YES YES NO YES NO YES YES YES YES YES NO NO NO YES YES YES YES YES NO YES YES YES YES YES YES YES YES YES YES NO NO YES YES YES NO YES YES YES YES YES YES YES YES YES YES YES YES NO YES YES YES YES NO YES YES NO YES YES YES YES YES YES YES NO NO YES YES NO NO YES NO NO NO NO NO NO NO NO NO NO NO YES YES YES NO YES NO NO NO NO NO NO NO NO NO NO NO NO YES NO NO NO NO YES YES YES YES YES YES YES NO YES NO YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES NO NO YES NO YES YES NO NO NO NO NO NO YES NO YES YES NO NO NO NO Mandatory Function Unique Interface Control System Software Read Write Client Software Read Write 5.4. on CardBus PC Cards. Because CardBus PC Card sockets support 16-bit PC Cards.2. CardBus PC Cards' memory space(es) could be viewed as 16-bit PC Card-like Common Memory.

cards are assigned I/O addresses. in order not to conflict with the placement of the image header. Whether the memory space is mapped into host system address space via a 16-bit PC Card-like mapping from a 16-bit PC Card or a Base Address Register mapping from a CardBus PC Card.4 Expansion ROM An expansion ROM may be mapped into the host system address space via the Expansion ROM Base Address Register in the configuration space.this is a two-byte pointer in little endian format which points to the CardBus PC Card Data Structure. Table 5Ð24 Expansion ROM Image Header Offset 0H 1H 2H-17H 18H-19H Length 1 1 16 2 Value 55H AAH variable variable Description ROM Signature. If an expansion ROM is present. At the beginning of each expansion ROM image is an expansion ROM header. with legal values. All of the registers in the expansion ROM Image Header and in the CardBus PC Card Data Structure. Pointer to CardBus PC Card Data Structure .ELECTRICAL SPECIFICATION where a window of a given size is requested between a card offset address and a host system base address. ROM Signature .4.) Tuple chains may appear anywhere in memory space.2.) 5. each of which may apply to different system and processor architectures. unlike those in configuration space. may be mapped directly into the host system address space and accessed by the client. (See the Card Services Specification. The reference point for this pointer is the beginning of the ROM image. below. unless otherwise stated. as described in Table 5Ð24. The ROM consists of one or more images. as indicated by the Expansion ROM Base Address Register. then there may be tuple chains in any of the images. This pointer must have a value of at least 20H. © 1999 PCMCIA/JEIDA 163 . Any tuple chains in memory space. Each image must start on a 512byte boundary and must contain the CardBus PC Card expansion ROM header. The last image in a ROM has a special encoding in the header to identify it as the last image. (See the Card Services Specification.2.3 I/O Space When used in CardBus PC Card systems which implement a separate host system I/O space.4. are required to be present. byte 2 Reserved (processor architecture unique data) Pointer to CardBus PC Card Data Structure (defined in Table 5Ð25). byte 1 ROM Signature. it is important that the card software manage the mapping. 5.this is a two-byte field containing 55H in the first byte and AAH in the second byte. although the Card Services tuple parsing routines are still the preferred access mechanism partly because those tuple chains in CardBus PC Card configuration space cannot be directly mapped into the host system address space. This signature must be the first two bytes of the ROM address space for each image of the ROM. The starting point of each image within the expansion ROM depends on the size of previous images.

these four bytes provide a unique signature for the CardBus PC Card Data Structure. CardBus PC Card Data Structure Revision . This revision level is 0. The VPD must be within the first 64 KBytes of the ROM image.this is a 1-byte field which identifies the type of code contained in this section of the ROM. "Reserved" in the diagram below indicates that the register is reserved for future use.CARDBUS PC CARD ELECTRICAL INTERFACE The CardBus PC Card Data Structure must be located within the first 64 KBytes of the ROM image and must be DWORD aligned. Revision Level . CardBus PC Card Data Structure Length . Code Type .the Pointer to Vital Product Data (VPD) is a 16-bit field which is the offset from the start of the ROM image and points to the VPD.this is a 16-bit field which defines the length of the data structure from the start of the data structure (the first byte of the Signature field). etc. The CardBus PC Card Data Structure contains the information summarized in Table 5Ð25. the string "PCIR" Allocated Pointer to Vital Product Data CardBus PC Card Data Structure Length CardBus PC Card Data Structure Revision Allocated Image Length Revision Level of Code/Data Code Type Indicator Reserved Signature . "Allocated" indicates that the register is not defined for CardBus PC Card and must not be redefined as other environments may use the register. "C" at offset 1. A value of 0 indicates that no VPD is in the ROM image. Image Length . Pointer to Vital Product Data .this is a two-byte field which represents the length of the image. Table 5Ð26 describes the available Code Types. CardBus PC Card system software will not make use of any of the information which may be stored in these fields. This field is in little-endian format and is in units of bytes. This field is in little-endian format and gives the value in units of 512 bytes. Table 5Ð25 CardBus PC Card Data Structure Fields Offset 0H 4H 8H AH CH DH 10H 12H 14H 15H 16H Length 4 4 2 2 1 3 2 2 1 1 2 Description Signature. The code may be executable binary for a specific processor and system architecture or interpretive code. 164 ©1999 PCMCIA/JEIDA . Details of each field are given after the figure.this is a two-byte field which contains the revision level of the code in the ROM image. The purpose of the "Allocated" registers is to maintain compatibility between CardBus PC Card and other environments.this is an 8-bit field which identifies the data structure revision level. The string "PCIR" is the signature with "P" being at offset 0. This field is in little-endian format. The content of the VPD structure is not currently defined.

another image follows. Documentation for Open Firmware is available in the IEEE P1275-1994 Standard for Boot (Initialization. and applications with efficient and non-conflicting use of system resources. and related software.2. The primary components of the software interface are Socket Services and Card Services. This allows the CardBus PC Card-compatible software to operate without conflicts and gain control of host system resources.5. After Card Services is initialized. This isolates higher-level software from most hardware implementation dependencies allowing different socket implementations to be supported by a common client. 5.1 Overview This chapter describes the minimum hardware and software interfaces that PC Card and system designers can rely on for basic compatibility across PC Cards.5. Configuration) Firmware Core Requirements and Practices.2 Software Requirements CardBus PC Card allows PC Cards and sockets to be accessed by multiple PC Card-aware device drivers. Both components can be developed as a single module as long as all functions described are available. It is the lowest level software layer. The services provide hardware-independent control functions that are used to manipulate implementation-dependent hardware. Card Services allocates resources and coordinates PC Card-related activities for higher-level clients. configuration utilities. PC-AT compatible Open Firmware Standard23 Reserved Indicator . If set. 5. Bits 0-6 are reserved. (See also the Socket Services Specification. Socket Services provides the lowest-level function set for socket hardware adapter control. Once Card Services is loaded. 5. If reset. © 1999 PCMCIA/JEIDA 165 . Card Services has exclusive use of Socket Services.5 Requirements For CardBus PC Cards and Sockets 5. Socket Services is the only interface defined and supported by the PC Card Standard.1 Socket Services Socket Services functionality must be provided. providing only socket-control functions and low-level PC Card functions accessible through control of CardBus PC Card sockets. this is the last image. systems. These interfaces ensure that the CardBus PC Card can meet the PCMCIA/JEIDA goal of PC Card interoperability. any software using Socket Services will receive an error status when accessing Socket Services functions directly.5.ELECTRICAL SPECIFICATION Table 5Ð26 Code Type Descriptions Type 0 1 2-FFH Description Intel Architecture.) 23 Open Firmware is a processor architecture and system architecture independent standard for dealing with device specific option ROM code.bit 7 in this field tells whether or not this is the last image in the ROM.

The Card ServicesÕ specification explicitly defines a guaranteed minimum set of card control functions on which higher-level software and associated PC Cards can rely. etc. I/O address space. In this case. One adapter could be part of the motherboard and another adapter could be plugged into a system expansion slot. The hardware notification of PC Card insertion and status change events from all adapters goes to a single Card Services handler.2. Note that automated processes to determine system resource availability are usually not 100% accurate..CARDBUS PC CARD ELECTRICAL INTERFACE 5. mapping windows. what system I/O and memory address space is unused. Card Services is the central coordinator for clients to acquire system and socket resources (e.2.2 Card Services Card Services is the only required software interface for managing CardBus PC Cards in CardBus PC Card-compliant systems.24 24This method does not have to be supported if an automated process can guarantee 100% accuracy in dynamically determining system resource availability and it is used to initialize Card Services whenever resources change.5. As a result.2. and applications share system resources in providing for PC Card access..5. system mappable address space. 166 ©1999 PCMCIA/JEIDA . and what interrupts are unused. 5. memory address space. even if there is more than one Socket Services handler. there can be only one Card Services implementation present in a system. CardBus PC Card-compliant systems must provide the following: an automated method of initializing Card Services with the available resources (those not preassigned) or a Card Services that is preinitialized with the available resources and a method of later modifying the Card Services set of available resources based on the changing configuration of non-PC Card components in the host system. one implementation to control each adapter type. However. It provides the capability of client registration for card event call backs and meets the minimal requirements for manipulating CardBus PC Card-compliant host system interfaces. interrupts) present in a given system. there must be the ability for later adjustment of the Card Services resource table. In this case. there will typically be several implementations of Socket Services. utilities.) 5. Therefore. it returns a failure indication. CardBus PC Card compliance cannot guarantee that any given client of Card Services will always be granted a requested resource. (See also the Card Services Specification.4 System Resource Determination Each implementation of Card Services must have some implementation-dependent way to determine the system hardware resources (e. Card Services must know what system I/O and memory address space is usable by the adapter hardware. the client can try to operate with different or fewer resources or may simply report that it is unable to provide its function. what interrupts can be steered by the adapter hardware.).3 System Resource Availability Multiple CardBus PC Card-aware device drivers. Most of the Card Services functions are used by clients only for installation and configuration. If Card Services is unable to provide resources to a client due to resource availability limitations.g. Also the system configuration could change rendering a pre-initialized table obsolete. Therefore. It is important to recognize that more than one type of adapter can be present in any given system.g.5.

network adapters have a NET.1 Configuration Space All CardBus PC Cards are required to implement configuration space for each function (see the CardBus PC Card Programming Model section of this specification).) © 1999 PCMCIA/JEIDA 167 .5. Some cards offer functionality that use configuration files to describe where they are located in system memory address space. 5. it may be used by software that is or is not aware that the functionality is located on a PC Card. they may recognize a card specifically from information in the Card Information Structure (CIS) that is unique to that card. All other spaces.3 Card Requirements In order for a socket to reliably recognize a PC Card and configure it.2 Required CIS CardBus PC Cards must implement a minimum set of tuples per function. Enablers recognize PC Cards in one of two ways.CFG or PROTOCOL. As an example. If the software is PC Card-aware. It is recommended that CardBus PC Card software implementations provide for the support of enablers.3.ELECTRICAL SPECIFICATION 5. memory. and expansion ROM. all CardBus PC Cards must meet certain minimum functionality requirements. it may piggy-back on the efforts of the enabler and use the card's functionality until the card is removed and the enabler releases the system resources used by the card. Common silicon (CardBus PC Card interface components designed for use on both PC cards and PCI) must implement configuration space as outlined in the "CardBus PC Card/PCI Common Silicon Requirements" guideline. For example. If the software is not PC Card-aware. For most cards this means assuming the PC Card is placed at the same locations typically used by standard ISA peripherals that perform the same functions.) 5. the enabler must place the PC Card's resources as indicated in the configuration file. I/O address range and memory range used to address the adapter. some enablers use combinations of the manufacturer string and product string from the VERS_1 tuple and the Manufactuer ID and Function ID tuples.5. Second. First. enablers may recognize a PC Card solely from its Function ID tuple. (See the Metaformat Specification. (See also Guidelines.5. I/O.INI file describing the IRQ level. In this case.5 Enabler Support The purpose of an enabler is to allow a single piece of software to configure and unconfigure a PC Card to prevent the redundancy of every PC Card requiring separate and unique configuration software. Once a card is configured. 5.5. it must locate the card's resources where the enabler mapped them into the host system's address space.2. For most Data/FAX modems.3. are optional. This section outlines this minimum functionality for CardBus PC Cards. a Function ID that indicates the PC Card has a serial interface causes the card to be configured as the next available COM port. This document specifies how to construct configuration space such that it is usable both by CardBus PC Card and PCI in addition to documenting electrical and protocol considerations.

4 Pull-up/Pull-down Resistors When a PC Card is removed from the socket. READY.) for CardBus PC Cards using the system's speaker for CardBus PC Cards requiring this additional supply The remote wakeup capability is optional even for CardBus PC Cards which implement the CSTSCHG pin. there will be periods when the connector contacts bounce causing signals on the interface to glitch. the interface signals will float. CGNT# (for bus masters) and CFRAME# (on all cards) must be pulled-up to VCC on the CardBus PC Card using the resistor values specified in 5.3. WP.5.3 Required Signals All CardBus PC Cards must implement the following signals: Address and Data: CAD[31::0] CCBE[3::0]# CPAR CFRAME# CTRDY# CIRDY# CSTOP# CDEVSEL# CPERR# CSERR# CCLK CRST# CCD[2::1]# CVS[2::1] GND (four pins) VCC (two pins) Interface Control: Error Reporting: System: Card and Voltage Detect: Power and Ground: CardBus PC Cards with bus master capability must also implement: Arbitration: CREQ# CGNT# CCLKRUN# The following signals are optional: CINT# CSTSCHG CBLOCK# CAUDIO VPP1. 5. The CGNT# resistor ensures the CardBus PC Card never initiates a cycle.3. During these times. e. possibly leading to false initiation or detection of cycles by the CardBus PC Card..3. BVD[2::1]. The CFRAME# resistor ensures that it never falsely detects a cycle. All connector pins associated with signals which aren't implemented must be noconnects on the PC Card.2.5. 5.CARDBUS PC CARD ELECTRICAL INTERFACE 5.5 Supporting CBLOCK# and Writeback Cache Coherency. VPP2 for CardBus PC Cards requiring interrupt services for CardBus PC Cards which generate status changed events or remote wakeup for CardBus PC Cards containing shared memory (See 5.3.3. CardBus PC Cards do not have to implement all of the fields in the associated 168 ©1999 PCMCIA/JEIDA .1 Pull-up Values for Control Signals.g. or remote wakeup.5 CSTSCHG Support CSTSCHG can be generated from a number of different sources.5. Therefore.6.3.

This power saving state can be achieved in a variety of ways. For this reason. There are additional requirements on CSTSCHG support when implementing PCI Bus Power Management for CardBus.5.3. CardBus PC Cards must not consume more than Icc(CIS) (see 5.5.4.3.1 DC Specifications) when reading the CIS and for configuration space reads and writes after power-up or reset. Any CardBus PC Card which requires more than Icc(CIS) during normal operation must report this. 5. For example.5. just those which apply to the particular function.6 Power Consumption The maximum power allowed for any CardBus PC Card is a function of the maximum current that can be supplied by the VCC pins. Clock rates on the CardBus PC Card can be reduced. (See the Metaformat Specification. 5. 5. in the CIS. © 1999 PCMCIA/JEIDA 169 .5.6 Card Insertion and Removal and the following sections for how the adapter must deal with configuring the interface to utilize the correct protocol.4 Socket Requirements This section outlines the minimum functionality that must exist in a CardBus PC Card socket. Refer to the PCI Bus Power Management for CardBus Cards section for CardBus card specifics and the PC Card Host System Specification for additional details.3.3 V-only systems are not required to support 5 V 16-bit PC Cards.2.5. The CardBus PC Card interface does not impose any additional constraints on adapters than is already implied by the 16-bit PC Card specification. CardBus PC Card adapters implemented in 3.ELECTRICAL SPECIFICATION registers. along with the maximum current it requires. For example. Refer to the Configuration Space section of this specification for details on where I/O and memory-mapped I/O base address registers must be placed.) 5. All other functions can be suspended. This means that CardBus PC Cards which utilize I/O space must also implement a memory base address register(s) to facilitate memory-mapped I/O. It is anticipated that some systems either cannot or will not provide the full power budget. if necessary. This functionality may be integrated in the socket adapter silicon but is not required to be.1 16-bit PC Card Support All CardBus PC Card adapters must provide support for 16-bit PC Cards.7 I/O Space Support Any addresses on a CardBus PC Card that can be mapped into I/O space must also be mappable into memory space. Refer to 5.4. which could limit functional capability. Power planes to non-critical parts could be shut off with a FET. LAN functions typically won't implement the write-protect switch but memory cards would.1. This is done using a power description structure. which reduces performance but does not limit functionality. For example: • • • Circuitry on the PC Card can be disabled on power-up or reset until re-enabled via an access to configuration space. It is the system's responsibility to configure the appropriate base address register.

prefetchable non-cacheable The CardBus PC Card adapter must provide a means to decode accesses from the system intended for its PC Card interfaces and those from CardBus PC Cards intended for the system. The low four bits of the prefetchable memory base and limit registers are required to be read only and must return a value of 0 to indicate only 32-bit addressing is supported. configuration space does not have to be mapped into the system address space.CARDBUS PC CARD ELECTRICAL INTERFACE 5.5. In the bridged implementation mentioned above. The resources they point to must be mappable anywhere in the available system memory space. which is generally not cacheable (i. and non-cacheable).2.. In many cases. Note that some system buses. If that cacheable space is supported. to allow support of noncacheable memory and/or memory mapped I/O. particularly in hierarchical topologies. As a result. system bus constraints will dictate that the adapter function as a system bus-to-CardBus PC Card bridge. The returned value of 01 is allocated and must not be used by CardBus PC Card adapters. Similarly. prefetchable. it is recommended that 170 ©1999 PCMCIA/JEIDA .2 Address Spaces The CardBus PC Card interface supports three basic address spaces: memory. These registers are also required on a per socket basis. must ensure that Card Services can correctly map CardBus PC Card adapters and cards into the system address space. Therefore. and configuration. 5. The availability and capability of this hardware mechanism is a function of the system architecture. the socket adapter only needs to be concerned with mapping memory and I/O spaces. specify bridges which require the assignment (i. including systems with hierarchical bus topologies. it assumes that address bits CAD[11::0] of the limit address are FFFH. the base address value) to be above 1 MB. which is not being cached but doesn't exhibit side effects when read.5.1 Memory Space A CardBus PC Card's memory space is classified as either: cacheable which uses hardware mechanisms to guarantee coherency. the adapter must provide additional base and limit register pairs for that space. Configuration space is accessed using an address independent mechanism which treats each function's configuration space as being unique. I/O. For the purposes of address decoding the adapter assumes that address bits CAD[11::0] of the base address are zero. Therefore. If this memory exhibits side effects when read. These implementations must also accommodate the dynamic insertion/removal characteristics fundamental to PC Cards. The solution to these issues is system dependent and outside the scope of this document. the adapter must provide a base address register and limit address register for each supported space (cacheable. on a per window basis. It has the same characteristics as memory mapped I/O space. Implementations. This forces a prefetchable address range to be aligned to a 4 KByte boundary and to have a size granularity of 4 KBytes. software must guarantee coherency if it is). In these cases. but may not be shared across multiple sockets simultaneously. A mechanism must also be provided to disable prefetching. All CardBus PC Card adapters must provide support for prefetchable memory.4.4. This may impact the performance of card-to-card transfers since addresses must be presented to the snooping agents before letting the transaction proceed. The top 20 bits of the prefetchable base and limit registers correspond to address bits CAD[31::12] of a memory address. The adapter must provide at least 32 KBytes of contiguous memory to each socket and also must be able to map larger memory blocks into available system memory space.e. it may not be prefetchable or cacheable under any circumstances. Note: Each Base and Limit register pair may be reassignable from socket to socket.e. this means the adapter must provide each socket with a minimum of two prefetchable base and limit register pairs for each socket supported.

2. Since the CardBus PC Card interface requires each address to have a unique destination. © 1999 PCMCIA/JEIDA 171 . The top 20 bits of the base and limit registers correspond to address bits CAD[31::12] of a memory address. of the 32-bit I/O address space.ELECTRICAL SPECIFICATION CardBus PC Card follow the convention of placing memory in upper memory whenever the CardBus PC Card adapter does not reside on the primary system bus. In this case. is driven by the potential emergence of memory-mapped I/O only cards. corresponding to CAD[31::16]. 5.5. of the I/O base address register are zero. Therefore. Supporting both modes may also position the adapter to be sold into multiple system architectures.2 CardBus PC Card with I/O Space CardBus PC Card adapters which support I/O space must also provide each socket with a minimum of: • • two I/O base address registers two I/O limit address registers Each register must have 4 byte granularity and power-of-two alignment. If these bits have the value 0.2. 5. The address spaces of a CardBus PC Card with multiple address spaces may be interleaved with another CardBus PC Card's spaces only if all the affected cards reside on the same adapter and the adapter provides a mechanism to allow this. particularly in hierarchical topologies. if I/O space is supported.5.1 CardBus PC Card with Memory Mapped I/O The adapter must provide at least 4 KBytes of contiguous memory for each socket and must be able to map larger memory blocks into available system memory space. The low four bits of the memory-mapped I/O base and limit registers are required to be read only and return zero when read. When the I/O base and limit registers indicate support for 32-bit I/O address decoding. it is recommended that CardBus PC Card follow the convention of placing memory-mapped I/O in upper memory whenever the CardBus PC Card adapter does not reside on the primary system bus.. For the purposes of address decoding the adapter assumes that address bits CAD[11::0] of the base address are zero. The adapter must provide at least 1 byte of I/O space for each socket.2.e. 5. the I/O address range may be anywhere in the 4 GB CardBus PC Card I/O address range. Similarly. the base address value) to be above 1 MB.4.2.5. it assumes that address bits CAD[11::0] of the limit address are FFFH.4. This forces a memory mapped I/O address range to be aligned to a 4 KByte boundary and to have a size granularity of 4 KBytes. Note that some system buses. specify bridges which require the assignment (i. this mechanism must allow the mapping to be done such that the spaces do not overlap. CAD[31::16].4. The selection will depend largely on the system architecture the adapter is intended to be used in. The requirement to also support memory-mapped I/O.2 I/O Support All CardBus PC Card adapters must support either memory-mapped I/O or both memory-mapped I/O and I/O space.2. the I/O address range supported by the adapter will be restricted to the first 64 KBytes of I/O address space. then the adapter supports 32-bit I/O address decoding and the upper 16 bits of the base and limit registers hold the upper 16 bits. then the adapter supports only 16 bit addressing and assumes that the upper 16 address bits. If the lower two bits of the I/O base and I/O limit registers are 01. The lower two bits are read only and encode whether the adapter supports 16 or 32 bit I/O addressing.

4. Therefore. It does not affect the adapter's prefetching. when this mode is enabled. 5. 5. posting.3.4.3. the adapter will only forward transactions downstream (from the system bus to CardBus PC Card) when they are in the top 768 bytes of each naturally aligned 1 KByte address block. i. This is a historical artifact of ISA's 10-bit I/O addressing capability and the convention of using the two most significant bits to indicate motherboard devices. Further. This interrupt routing must be distinct from functional interrupts.5. shared by all CardBus PC Card sockets. 5.2 Status Change Events CardBus PC Card adapters must provide a second system interrupt for signaling Status Changed events such as card insertion. or error handling behavior.CARDBUS PC CARD ELECTRICAL INTERFACE Note that some system buses. This created a situation where the lower 256 bytes of every 1 KByte block were aliases of ISA addresses. Note that there is a distinction between the ability to route an interrupt and the availability of that interrupt. never functional ones. specify bridges which decode I/O addresses on 4 KByte boundaries.2. This results in I/O address decoding on the CardBus PC Card interface that is similar to EISA slot decoding. This means that Card Services must be aware of where each CardBus PC Card function physically resides in the system so valid I/O assignments can be made.2.4. other system buses which support a 16-bit I/O addressing mode decode the upper six bits for additional register selection. The adapter must generate the Status Changed interrupt for at least each of the conditions listed below: • • • • PC Card insertion event PC Card removal event CardBus PC Card asserted CSTSCHG PC Card power-up completed 172 ©1999 PCMCIA/JEIDA . I/O transactions on CardBus PC Card in the top 768 bytes of any 1 KByte block will be forwarded upstream (from CardBus PC Card to the system bus).5. Any interrupt request lines which are available to the CardBus PC Card interface must be reported to Card Services during its initialization.. ordering. Conversely. The system software responsible for configuring this mode must enable it in systems with an ISA bus.3 ISA Support Implications CardBus PC Card adapters in systems which support the ISA expansion bus must also support an ISA mode which defaults to the disabled state whenever the adapter is reset.5.5.4. and CSTSCHG assertion. that cannot be routed to. an implementation could provide only a single functional interrupt.e. and still be compliant although it would pay an interrupt latency penalty.3 Interrupt Handling and Routing 5. hardware does not have to provide a separate functional interrupt for each socket. Since CardBus PC Cards must support sharable interrupts. Note that this mode only affects the I/O address decoding. particularly in hierarchical topologies. The system shall not report any interrupt. Therefore. as being available.1 Functional Interrupts (CINT#) A CardBus PC Card socket must have at least one system interrupt for routing PC Card functional interrupts (CINT#). removal. Card Services must only receive Status Changed interrupts.

4. available to Card Services: • • • if a removal event caused a failed transaction or left data in the adapter's buffers if an inserted PC Card cannot be supported by the hardware what type of PC Card was inserted (16-bit PC Card vs.1 Socket EVENT Register The adapter uses the socket Event register to generate status changed interrupts. Present State. See the PC Card Host System Specification for additional information for adapter (PCI to CardBus Bridge) requirements. PC Card insertion/removal.ELECTRICAL SPECIFICATION Further. Force.4. and Control registers for each socket it supports.5.5. These registers and the fields that they contain are described in the following sections. 5. the socket must capture this event.4 Register Descriptions CardBus PC Card adapters must contain a number of registers to manage status changed events.4. associated with status change events. 5. Card Services is responsible for clearing the appropriate fields after determining why the status changed interrupt occurred. If the system supports remote wakeup. and status information about the PC Card in the socket. remote wakeup events. Note that space from the host system's address space must be allocated for these registers. The adapter must provide Event. 31 4 3 2 1 0 Reserved Interface power cycle completed (PowerCycle) CCD2# changed state (CCD2#) CCD1# changed state (CCD1#) CSTSCHG pin was asserted (CSTSCHG) Figure 5-44 Socket EVENT Register © 1999 PCMCIA/JEIDA 173 . CardBus PC Card) Note that a CardBus PC Card may assert CSTSCHG as a pulse to request remote wakeup when the CardBus PC Card interface is powered down. Card Services must read this register and the socket Present State register to determine the cause of the interrupt. The fields in this register indicate that a change in socket status has occurred. There are significant additional requirements for the adapter (PCI to CardBus Bridge) when supporting PCI Bus Power Management for CardBus. the adapter must make the following status information. Mask.

1 2 3 CCD1# CCD2# PowerCycle This field is set (1) whenever the CCD1# field in the Present State register changes state. It is cleared by writing it to 1. This field is set (1) by the adapter when it detects that the interface has finished powering up or powering down. The state after the adapter has been reset is 0. Also. see PC Card Host System Specification for additional CSTSCHG requirements when supporting PCI Bus Power Management for CardBus.2 Socket MASK Register This register gives software the ability to control what events cause the status changed interrupt to be generated. These fields are reserved for future use. see the PC Card Host System Specification for additional CSTSCHG requirements when supporting PCI Bus Power Management for CardBus. It is cleared by writing it to 1.4. 31 4 3 2 1 0 Reserved Interface Power Cycle Completed (PowerCycle) Card insertion/removal (CardDetect) CSTSCHG pin was asserted (CSTSCHG) Figure 5-45 Socket MASK Register 174 ©1999 PCMCIA/JEIDA . The state after the adapter has been reset is 0. Also. The state after the adapter has been reset is 0. This field is cleared by writing it to 1.CARDBUS PC CARD ELECTRICAL INTERFACE Table 5Ð27 Socket EVENT Register Fields Bit 0 Field Name CSTSCHG Description This field is set (1) whenever the CSTSCHG field in the Present State register changes state. This field is set (1) whenever the CCD2# field in the Present State register changes state. The state after the adapter has been reset is 0. It inhibits the corresponding fields in the socket Event register from causing a status changed interrupt.5. 4-31 Reserved 5.4. It is cleared by writing it to 1. Note that the Present State register must be read to see if it was successful.

The meaning of the bits is: 00 Masks the CCD1# and CCD2# fields in the Event register.4. These fields are reserved for future use. This register may be written using the Force event capability described in 5. Also.4. the status changed event signaling the power up process has completed will not be generated although the PowerCycle field in the Event register will be set. the assertion of CSTSCHG by the card will not cause a status changed interrupt to occur although the CSTSCHG field in the Event register will be set.4 FORCE Event Capability. see the PC Card Host System Specification for additional CSTSCHG requirements when supporting PCI Bus Power Management for CardBus.ELECTRICAL SPECIFICATION Table 5Ð28 Socket MASK Register Fields Bit 0 Field Name CSTSCHG Description When cleared (0). Some of the fields are reflections of interface signals while others are flags set to indicate conditions associated with a status changed event. This is the default state after the adapter is reset. © 1999 PCMCIA/JEIDA 175 . Insertion and removal events will cause a status changed interrupt.3 Socket PRESENT STATE Register This read-only register reflects the current state of the socket. The state after the adapter has been reset is 0. It is set by writing it to 1.5. Insertion and removal events will not cause a status changed interrupt. 4-31 Reserved 5. 01 Undefined 10 Undefined 11 Unmasks the CCD1# and CCD2# fields in the Event register. 1-2 CardDetect This field masks the CCD1# and CCD2# fields in the Event register so that insertion and removal events will not cause a status changed interrupt to occur. Note that the CCD1# and CCD2# fields in the Event register will still be set.5.4. It is set by writing it to 1. It must be cleared whenever the socketed PC card is removed or when the adapter is reset.4. 3 PowerCycle When cleared (0).

3 V (3Vsocket) Socket can supply 5.3 V (3Vcard) Card can accept Vcc=5.CARDBUS PC CARD ELECTRICAL INTERFACE 31 30 29 28 27 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Socket can supply Y.0 V (5Vcard) Illegal Vcc value requested (BadVccReq) Card removal caused data loss (DataLost) Unrecognized card inserted (NotACard) Reserved CardBus PC Card inserted (CBcard) 16-bit PC Card inserted (16card) Power applied successfully (PowerCycle) State of CCD2# pin (CCD2#) State of CCD1# pin (CCD1#) State of CSTSCHG pin (CSTSCHG) Figure 5-46 Socket PRESENT STATE Register 176 ©1999 PCMCIA/JEIDA .Y V (YVsocket) Socket can supply X.X V (XVsocket) Socket can supply 3.X V (XVcard) Card can accept Vcc=3.Y V (YVcard) Card can accept Vcc=X.0 V (5Vsocket) Card can accept Vcc=Y.

indicates that a PC card removal event may have caused data to be lost either because a transaction was not completed properly or data was left in the adapter's buffers.0 V. indicates that the card inserted will function at VCC= X. 2 CCD2# 3 PowerCycle 4 16card 5 CBcard 6 7 Reserved NotACard 8 DataLost 9 10 BadVccReq 5VCard 11 3VCard 12 XVCard 13 YVCard 14-27 28 29 Reserved 5Vsocket 3Vsocket © 1999 PCMCIA/JEIDA 177 . i. indicates that software attempted to apply a VCC voltage to a socket that was outside the range detected using the CVS[2::1] and CCD[2::1]# pins. indicates that the card inserted will function at VCC=3. When set (1). the value stored here is for when the CVS[2::1] pins are held low. indicates that the card inserted was a CardBus PC Card. indicates that the interface is powered up. indicates that the socket cannot supply VCC=3.3 V. This is determined by interrogating the voltage sense and card detect pins. This is determined by interrogating the voltage sense and card detect pins. When cleared (0). the power up process was successful. When a CardBus PC Card is present.0 V. This is determined by interrogating the voltage sense and card detect pins.g. 1 indicates CCD2# is High (card is not present). and this bit is cleared.X V. indicates that the card inserted will function at VCC= Y. When set (1). When cleared (0). indicates that the socket can supply VCC=3. indicates that the card will not function at VCC= X.Y V. 0 indicates it is negated.Y V.X V. indicates that the type of card inserted could not be determined. When set (1). indicates that the card will not function at VCC=3. When cleared (0). and this bit is cleared. 0 indicates CCD1# is low (card is present). the power up process was not successful. When set (1). and this bit is cleared. When cleared (0). indicates that the socket can supply VCC=5. Since the CCD1# pin could be shorted to either CVS1 or CVS2.e.Y V. 16-bit PC Card or CardBus PC Card) is inserted. indicates that the socket cannot supply VCC=5. the adapter must not allow the socket to be powered up at VCC= X.X V. i. When set (1).g.e. indicates that the interface is powered down. When set (1). When a CardBus PC Card is present.3 V. When set (1). CardBus PC Card or unrecognized card) is inserted. the value stored here is for when the CVS[2::1] pins are held low. the adapter must configure the socket interface for CardBus PC Card. When set (1). This field is updated by the adapter to communicate the status of each power up/power down request. When a CardBus PC Card is present. When set. indicates that the card will not function at VCC= Y. 1 indicates CSTSCHG is asserted.3 V.3 V. 16-bit PC Card or unrecognized) is inserted. This value does not have to be updated until a non-16-bit PC Card (e. This field reflects the current state of the CCD1# pin on the interface. When cleared (0).0 V. When set (1). the adapter must not allow the socket to be powered up at VCC=5. indicates that the card inserted will function at VCC=5. When set. 0 indicates CCD2# is low (card is present).0 V. indicates that the card will not function at VCC=5. These fields are reserved for future use. 1 indicates CCD1# is High (card is not present). the adapter must not allow the socket to be powered up at VCC=3. When set (1). It must be cleared by Card Services when the removal event status changed interrupt is serviced. This field reflects the current state of the CCD2# pin on the interface. the adapter must configure the socket interface for 16-bit PC Card.g. When cleared (0). When set (1). When a CardBus PC Card is present. This value does not have to be updated until a recognizable card (e. indicates that the card inserted was an 16-bit PC Card. When cleared (0).3 V. Setting this field disables the adapter's voltage checking hardware so extreme care must be taken when writing the Control register or the hardware could be damaged.0 V. the adapter must not allow the socket to be powered up at VCC= Y. Since the CCD2# pin could be shorted to either CVS1 or CVS2. This is determined by interrogating the voltage sense and card detect pins. When set (1).ELECTRICAL SPECIFICATION Table 5Ð29 Socket PRESENT STATE Register Fields Bit 0 1 Field Name CSTSCHG CCD1# Description This field reflects the current state of the CSTSCHG pin on the interface. This value does not have to be updated until a non-CardBus PC Card (e. This field is reserved for future use.

Note that this is not a physically implemented register.4.5. When set (1). However.X V. indicates that the socket can supply VCC= X.3 V (3Vcard) Card can accept Vcc=5. indicates that the socket cannot supply VCC= Y. Rather.Y V.X V (XVcard) Card can accept Vcc=3.Y V (YVcard) Card can accept Vcc=X.4.X V. 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Force interrogation of CVS/CCD pins (CVStest) Card can accept Vcc=Y.4 FORCE Event Capability CardBus PC Card provides the ability to simulate events by forcing values in the socket's Event and Present State registers. it is an address at which the socket's Present State register can be written. When cleared (0).0 V (5Vcard) Illegal Vcc value requested (BadVccReq) Card removal caused data to be lost (DataLost) Unrecognized card inserted (NotACard) Reserved CardBus PC Card inserted (CBcard) 16-bit PC Card inserted (16card) Power applied successfully (PowerCycle) State of CCD2# pin (CCD2#) State of CCD1# pin (CCD1#) State of CSTSCHG pin (CSTSCHG) Figure 5-47 Socket FORCE Register 178 ©1999 PCMCIA/JEIDA . 5. primarily for debug purposes. When cleared (0). indicates that the socket cannot supply VCC= X.Y V. The effects of a write to this address will be reflected in the socket's Present State and Event registers.CARDBUS PC CARD ELECTRICAL INTERFACE 30 31 XVsocket YVsocket When set (1). indicates that the socket can supply VCC= Y. This is done by generating writes to the socket Force register. other events may alter those registers before they can be read.

This results in the Event register's CSTSCHG field being set. Note that the PowerCycle field in the Present State register is not affected and continues to reflect the present state of the interface power.e. Writing a 0 has no meaning. Writes to this field cause the 16-bit PC Card field in the Present State register to be written. 1 CCD1# 2 CCD2# 3 PowerCycle 4 16card 5 CBcard 6 7 Reserved NotACard 8 9 10 DataLost BadVccReq 5VCard 11 3VCard 12 XVCard 13 YVCard 14 CVStest 15-31 Reserved © 1999 PCMCIA/JEIDA 179 .ELECTRICAL SPECIFICATION Table 5Ð30 Socket FORCE Register Fields Bit 0 Field Name CSTSCHG Description Writing a 1 to this field simulates the assertion of the CSTSCHG pin. writes to this bit field are ignored. Writing a 0 has no meaning. writes to this bit field are ignored. Writing a 0 has no meaning. These fields are reserved for future use. Note that the CCD1# field in the Present State register is not affected and continues to reflect the present state of the CCD1# pin. If a card is present in the socket (i. Writes to this field cause the 3VCard field in the Present State register to be written. Writes to this field cause the CBcard field in the Present State register to be written. CCD1# and CCD2# are asserted). CCD1# and CCD2# are asserted). If a card is present in the socket (i. Setting this field disables the socket's ability to power up VCC until the CVStest field is set. Writes to this field cause the 5VCard field in the Present State register to be written. Note that the CCD2# field in the Present State register is not affected and continues to reflect the present state of the CCD2# pin. Setting this field disables the socket's ability to power up VCC until the CVStest field is set. Note that the CSTSCHG field in the Present State register is not affected and continues to reflect the present state of the CSTSCHG pin. Setting this field disables the socket's ability to power up VCC until the CVStest field is set. Writes to this field cause the BadVccReq field in the Present State register to be written. Writing a 0 has no meaning. Writing a 1 to this field causes the CCD2# field in the Event register to be set. If a card is present in the socket (i. Writing a 1 to this field causes the CCD1# field in the Event register to be set. causes the adapter to interrogate the CVS[2::1] and CCD[2::1]# pins and update the nVCard fields in the Present State register. When written to a 1. Writing a 1 to this field simulates the successful completion of a power cycle event by causing the PowerCycle field in the Event register to be set. Writes to this field cause the NotAcard field in the Present State register to be written. Writes to this field cause the DataLost field in the Present State register to be written. Writes to this field cause the YVCard field in the Present State register to be written.e.e. CCD1# and CCD2# are asserted). Setting this field disables the socket's ability to power up VCC until the CVStest field is set in the Force register. This action also reenables the socket to power up VCC if the nVCard fields had been previously forced. This field is reserved for future use. writes to this bit field are ignored. Writes to this field cause the XVCard field in the Present State register to be written.

5.4.Y V 110 Reserved 111 Reserved 7-31 Reserved These fields are reserved for future use. Other voltages can be applied to VPP1 and VPP2 only after the allowed values have been determined from the PC Card's Card Information Structure.X V 101 Requested VPP[2::1] voltage = Y. if the PC Card was previously configured and the socket can guarantee that no card change has taken place.0 V 011 Requested VCC voltage = 3. 180 ©1999 PCMCIA/JEIDA .3 V 100 Requested VPP[2::1] voltage = X.0 V 011 Requested VPP[2::1] voltage = 3.) However. VPP[2::1] may be powered up at the desired voltage instead of VCC.4. VPP1.0 V 010 Requested VPP[2::1] voltage = 5. This field is used to request VCC voltages: 000 Requested VCC voltage = power off 001 Reserved 010 Requested VCC voltage = 5. and VPP2 must be initially powered up at the voltage indicated by the CVS[2::1] pins.5 CONTROL Register This register provides control of what voltages should be applied to VPP[2::1] and VCC.3 V 100 Requested VCC voltage = X.5.CARDBUS PC CARD ELECTRICAL INTERFACE 5. (See the Metaformat Specification.X V 101 Requested VCC voltage = Y. 31 7 6 4 3 2 0 Reserved Vcc Requested (VccControl) Reserved Vpp Requested (VppControl) Figure 5-48 Socket CONTROL Register Table 5Ð31 Socket CONTROL Register Fields Bit 0-2 Name VppControl Description This field is used to request VPP[2::1] voltages: 000 Requested VPP[2::1] voltage = power off 001 Requested VPP[2::1] voltage = 12.4.Y V 110 Reserved 111 Reserved 3 4-6 Reserved VccControl This field is reserved for future use.5.5 VPP[2::1] Power Requirements VCC.

CCD[2::1]#. 5. it must High-Z or power off all signals25 at this time in preparation for power up activities. 16card. 2. When a PC Card insertion is detected. This must be done from card insertion until the "Power Up Complete" condition is reached.6.e. the adapter must set the BadVccReq field in the socket's Present State register and must not apply power to the VCC pins.5. When servicing the status changed interrupt. The adapter must ensure that the interface is setup for the correct card type before the status changed interrupt is serviced. (See 3. No signals may be actively driven High to an unpowered PC Card except CVS1 and CVS2. If a CardBus PC Card was inserted. the adapter applies that voltage to the socket's VCC and VPP[2::1]26 pins. is forbidden.ELECTRICAL SPECIFICATION 5. 2.5.1 Card Insertion The CardBus PC Card interface requires Cold socket insertion. and Card Voltage Sense. 3.4. Card Detect. CardBus PC Card) and determine the correct voltage for VCC. and CVS2 must not be set to a High-Z state or the CCD# pins will indicate a card removal event for CardBus PC Cards. Debounce the CCD[2::1]# pins when a low on the card detect lines occurs. i. Note that this 3. Set up its logic to match the protocol required by the PC Card inserted (16-bit PC Card or CardBus PC Card).4. If the requested voltage is supported by the PC card and can be supplied to the socket. The power up process will not proceed beyond this point until Card Services gives permission. Interrogate the CVS[2::1] and CCD[2::1]# pins to determine the type of PC Card inserted (CardBus PC Card or 16-bit PC Card) and its VCC requirements.4. If the requested voltage is outside the range decoded from the card's CVS[2::1] pins or is not available in the system. NotACard. Card Services determines the cause of the status changed interrupt (insertion event in this scenario) by reading the socket's Event register. and nVCard fields of the socket's Present State register. Card Services must also read the socket's Present State register to ensure power was successfully applied. then the adapter should proceed with powering-up the interface as described in 4.6 Card Insertion and Removal 5. 1. the adapter must: 1. Socket Services writes the appropriate register(s) in the adapter to specify the requested VCC and VPP[2::1] value. signals are allowed to be active in this cold state. CVS[2::1]. Automatic power up upon insertion. The adapter must keep glitches on the CSTSCHG input from causing the CSTSCHG field to be set in the socket's Event register during the power-up process by disabling this field.4. This allows the adapter to properly configure its interface to the correct protocol (16-bit PC Card vs. WARN I N G : If a 16-bit PC Card was inserted. 26The requirements for applying power to Vpp are specified in 5. Card Services reads the socket's Present State register to obtain PC Card type and VCC requirement information. CRST# must be driven low. but must not cause any damage to PC Cards and systems.1 Socket Vcc for CIS Read.5. Card Services notifies Socket Services of the voltage requirements. If the adapter chose to drive outputs low to the empty socket..16. Notify Card Services that an insertion event occurred by generating a Status Changed interrupt. 25CVS1 © 1999 PCMCIA/JEIDA 181 .5 Vpp[2::1] Power Requirements. without software involvement. 4. The results will be reflected in the CBcard. Card Type Detection Mechanism). After identifying the socket.

This action must be automatic. Also. 5. and driving CFRAME# high one clock later to allow for a turn-around cycle. 4. This immediate assertion is necessary since contact bounce issues make it impossible to reliably execute cycles across the interface. If a transaction on the CardBus PC Card interface was aborted by the CRST# assertion or data was stranded in the adapter's buffers.3 CardBus PC Card Electrical Specification have been met. CCBE[3::0]#. no power up will actually occur. and set the other outputs to a High-Z state. driving CGNT# high. the adapter must also set the DataLost field in its Present State register. Card Services instructs the socket to negate CRST#. 2. the adapter must: 1. Only by physically locking the card in.) 5. After recognizing that the power up process is complete. CPAR. CVS1. The adapter must not drive any signal High to an unpowered socket. Card Services proceeds with the CardBus PC Card configuration process as defined in 5.. software alone controls the negation of CRST# but hardware will automatically assert CRST# in most circumstances. Disable the socket's remote wakeup capability by clearing the CSTSCHG field in the socket's Mask register. 182 ©1999 PCMCIA/JEIDA . Immediately idle the bus by asserting CRST# even if the final data phase has not been completed. in addition to CRST#. even if only momentarily. Note that software must ensure that the timings outlined in 5. 6. 4. Note that if an illegal voltage was requested. The adapter sets the PowerCycle field in the socket's Event register to cause a status changed interrupt to inform Card Services that the power up process is complete.4. it must not wait for the involvement of software.g. and CVS2 low. or providing an imminent removal indication. If a CardBus PC Card is present. glitches on CSTSCHG from CardBus PC Cards not supporting remote wakeup).4 CardBus PC Card Programming Model.2 Card Removal CardBus PC Card adapters must consider a PC Card removed when either of the CCD[2::1]# signals is negated. 3. Card Services clears the socket's EVENT Register to eliminate spurious interrupt events arising from powering up the interface (e.6. Remove power.5. from the connector. 7. Note that the imminent removal warning must occur at least 256 CCLK periods before card removal begins.4.CARDBUS PC CARD ELECTRICAL INTERFACE requires the adapter to be aware of the voltages available so that illegal requests can be detected. When this condition is detected and a 16-bit PC Card is present. the adapter must take action as defined in 4. can cycles be reliably completed and the need to immediately assert CRST# be avoided. VCC and VPP[2::1]. 5.1. The adapter must also disable the CSTSCHG field in the socket's Event register to keep glitches on CSTSCHG from causing false status changed events. (See also the Card Services Specification. Update the CCD1# and CCD2# fields in the socket's Present State register to set corresponding fields in the socket's Event register and generate a status changed interrupt notifying Card Services of the removal event. Drive CAD.7 Socket Vcc for CIS Read. CRST# must remain asserted throughout the power up process. This action could be taken in parallel with steps 1-3. CRST# must remain asserted throughout the power down process. Note that CGNT# must be set to a High-Z state or driven low before power is removed.

care should be taken when dynamically changing the voltage applied to VCC or VPP[2::1] so that power supply shorts do not occur. The only exception is in systems which provide another mechanism to deal with accesses during this status changed interrupt latency window.2 CSTSCHG Requirements The adapter must default to ignoring the CSTSCHG signal during the power up and power down procedures. the adapter would have to continue accepting transactions to the previous card but not forwarding them on.7.3 In-Rush Current During the PC Card power up process. It is the responsibility of the system designer to ensure that this does not pull VCC out of its specified tolerance range by either current limiting the supply to the socket or other appropriate means. any externally powered CardBus PC Card must appear at the CardBus PC Card interface like a CardBus PC Card without an external power source. between the removal event and when the status changed interrupt is serviced.5.4.5. 5. drawing a large amount of current. (See 5.5.5.2 Signal/Pin Description. The adapter must not drive any signal High to an unpowered socket.7 Power Cycling the Interface It is recommended for the host system to discharge the CardBus PC Card connector's VCC and VPP[2::1] to ground as soon as the power is switched off. a significant amount of capacitance will be instantaneously added to the power supply's load.1 Signal Requirements When powering up or powering down the CardBus PC Card interface.4. The safest implementation is to ensure that all power supply changes transition through 0V.ELECTRICAL SPECIFICATION The dynamic removal of a card creates a window of time. When CRST# is asserted.3.2 Reset. 5. if the adapter supports remote wakeup and the CardBus PC Card in the socket has implemented it. However. either on its own or at the direction of a client. must explicitly enable this capability. (See 5.7. One exception to this rule is for CSTSCHG which can be driven across the interface by CardBus PC Cards complying with the remote system wakeup protocol. This is referred to as "in-rush" current. Therefore. the adapter may drive the interface signals low.) The CardBus PC Card adapter's inputs must not react to voltages on its inputs for the duration of the power up or power down process (except for the CCD[2::1]# and CVS[2::1] pins). This means that the adapter must accept writes to the removed card and return "false" data on reads (all one's for x86 architecture systems) from it. When a socket is in the Cold state. This is necessary because CardBus PC Cards which don't implement remote wakeup may glitch this pin while VCC transitions. where clients may attempt to access non-existent resources.4.7.1. Further. © 1999 PCMCIA/JEIDA 183 . the adapter must hold CRST# asserted throughout the process.3.) After the interface has been powered down. If a new card is inserted. 5. the interface signals must be driven to their benign state. the attempted accesses must be completed before pending interrupts can be serviced. The adapter reverts to this default mode whenever it is reset or the CardBus PC Card is removed. this could cause a remote wakeup pulse to be missed during power down events. 5. Card Services. In many systems.4.

4. Note that this has implications on the system design since the adapter doesn't necessarily have full control of the clock resource. 2.) However. This capability has been defined to allow communication in the event sufficient pins do not exist on the interface.8 Required Pins The implementation of CAUDIO is recommended but not required.9 Clock Stopping Support CardBus PC Card adapters that are going to participate in the clock control protocol (CCLKRUN#) must be able to communicate with the clock source. 3. or generate special cycles on the CardBus PC Card interface. The adapter must be able to restart CCLK when a transaction originates on the system bus.1. (See 5.4. a simplified implementation is allowed for CCLKRUN#.5.11 Actions When Adapter Is Reset When the system resets the CardBus PC Card adapter.10 Special Cycle Support CardBus PC Card adapters do not have to respond to. 5. If the adapter is implemented in a system which will not stop the clock. and needs to cross the affected CardBus PC Card interface. Quit accepting transactions on its system bus and CardBus PC Card interfaces. 184 ©1999 PCMCIA/JEIDA .2 Signal/Pin Description. Flush write buffers to its CardBus PC Card interfaces. 5.4. or another CardBus PC Card. Flush read buffers when the master resides on one of its CardBus PC Card interfaces. The mechanisms required are system bus dependent but the following behavior must be present in all adapters: 1.4. 5. All other signals are required. The adapter must ensure that the latency involved in restarting the clock doesn't become visible to software.5.5. 2. Any read data intended for masters elsewhere in the system should be deleted. The adapter must forward "don't stop the clock" requests from the CardBus PC Card to the clock source in a manner that ensures the clock stream isn't interrupted when the CardBus PC Card meets the CCLKRUN# specification.CARDBUS PC CARD ELECTRICAL INTERFACE 5.5. the adapter must: 1. the adapter may simply assert CCLKRUN# when CRST# is not asserted and set CCLKRUN# set to a High-Z state when CRST# is asserted. The adapter must not allow the clock to stop before the time specified in the CCLKRUN# protocol.4.

Detailed Goals for PCI Power Management Interface: • • • • • • • • • Enable multiple PCI function power levels Establish a standard for PCI function wakeup events Establish a standard for reporting power management capabilities Establish a standard mechanism for controlling a PCI function's power state Establish a standard mechanism for controlling a PCI bus's power state Minimal impact to the PCI Local Bus Specification Backwards compatible with PCI Bus Revision 2. its low pin count and high integration factor has enabled very low cost solutions.ELECTRICAL SPECIFICATION 6 . While this strategy has successfully brought the PC platform into the mobile environment it is beset with problems because of the fact that there is no standard way to truly determine when the system is busy and when it is actually idle. The reason that this has not happened up to now is a lack of standards to provide the operating system with the required information that would allow it to control the hardware in a platform independent way.1 Introduction Since its introduction in 1993. and 2.1 Goals of this Specification The goal of this specification is to establish a standard set of PCI peripheral power management hardware interfaces and behavioral policies.1. This specification addresses this need. Its bandwidth and efficient support for multiple masters has allowed it to sustain high performance applications while at the same time. and buses.0 compliant designs Preserve the designerÕs ability to deliver differentiated products Provide a single architecture for all markets from mobile through server © 1999 PCMCIA/JEIDA 185 . It is used in a wide variety of computer systems sold today ranging from laptops to large servers. PCI has become a very popular bus. While the PCI Local Bus Specification is quite complete with a solid definition of protocols. no provision was made in the original specification for supporting power management functionality. PCI BU S POW E R M AN AGE ME N T I N T E R F AC E F OR CAR D BU S CAR D S 6. This specification addresses this requirement by defining four distinct power states for the PCI bus and four distinct power states for PCI functions as well as an interface for controlling these power states.1. The operating system does have this information so it makes sense to give it the responsibility for power management. electrical characteristics and mechanical form factors. Power Management in the current PC platform is performed by a combination of BIOS and System Management Mode (SMM) code utilizing hardware unique to each platform. 6. Once established this infrastructure enables an operating system to intelligently manage the power of PCI functions.

developers of operating systems and device drivers need to understand the power management interfaces presented by compliant devices to be able to manage them. 186 ©1999 PCMCIA/JEIDA .3 Overview/Scope In order to implement a power managed system under the direction of the operating system. Software developers are also a targeted audience for this specification. The following diagram outlines. Standardized power state definitions Standardized register interface in PCI configuration space Standardized wake events 6. this set of required architectural building blocks. and software ingredients needs to be defined and integrated. 6.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Key Attributes of this Specification: • • • • Enhances the PCI BusÕs Plug and Play capabilities by comprehending power management. a large array of tightly coupled hardware.1.1. at a high level.2 Target Audience This chapter is intended to address the needs of developers of CardBus cards. Specifically. This chapter describes the hardware requirements of such devices to allow the power management of those devices in an operating system directed power management environment.

PM policy specifications Storage Audio Graphics Platform Architecture Integration Specification Device-Class Power Management Specifications Host PCI Bus IEEE1394 USB PCI I/O Bus Power Management Specifications Config Regs PCI to CardBus Bridge SCOPE of Specification Config Regs Config Regs CardBus Function CardBus Function Figure 6-1: Operating System Directed Power Management System Architecture The scope of this specification is sharply focused on establishing a standard set of interfaces that are required to power manage PCI-to-CardBus Bridges. Device drivers specifications . Any PCI based component can use the mechanisms described in this specification. © 1999 PCMCIA/JEIDA 187 . The PCI Bus Power Management Interface Specification describes requirements for implementing power management for PCI functions which are capable of being used on an add-in card. As such Docking bridges are not covered by this specification. for example fall into the motherboard devices category because the physical docking bridge component always resides logically on the motherboard. and as such. buses. and is never deployed as an add-in card. Docking bridges. devices. fall outside the scope of this specification. Devices which can only be implemented on the motherboard are power managed in motherboardspecific ways (such as ACPI).ELECTRICAL SPECIFICATION OSPM specifications . CardBus cards and functions.

user mode services. For a CardBus card. A class of CardBus cards built before the PCI Bus Power Management Interface Specification for CardBus was added to the PC Card Standard and are PC Card Standard February 1995 compliant.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS 6. the first bridge component encountered with a PCI bus downstream of it is defined as the Originating Device for that PCI bus segment. and/or kernel mode services. the terms ÒOperating SystemÓ and Òsystem softwareÓ refer to the combination of power management services. From the perspective of the operating system (Host CPU). The Bus Segment Reset signal for a CardBus card is the CRST# signal. the originating device is the PCI-to-CardBus bridge controlling its bus (see figure below) Legacy PCI Devices Operating System Originating Device CPU Host Bus I/F Host Bridge PCI Bus I/F Originating Device for bus(0) PCI Bus(0) Primary Bus I/F PCI to CardBus Bridge Secondary Bus I/F Originating Device for CardBus bus CardBus bus Figure 6-2: Example "Originating Devices" 188 ©1999 PCMCIA/JEIDA .1. device drivers.4 Glossary of Terms Bus Segment Reset Bus Segment Reset is defined as the hardware reset signal that is taken as actual physical input to a given component within a system. Throughout this specification. Legacy CardBus cards are assumed to be in the D0 power management state whenever power is applied to them.

For a CardBus card. but rather refers also to the operational states of the function including state machine context. a device could use a PME to request a change to a lower power state. The secondary bus of a CardBus card refers to the bus that is topologically farthest from the CPU that is running the operating system.1. manage system thermal limits and maximize system battery life. The user will be able to select (through some user interface) various performance/power characteristics of the system to have the software optimize for performance or battery life. report PME status. the display is off. A power management event is requested via the assertion of the PME# signal. user mode threads are not being executed. and the system ÒappearsÓ to be off (from an end userÕs perspective. April 5. assertion of CSTSCHG (and STSCHG# for a PC Card) are translated to the host systemÕs PME# through the PCI-to-CardBus bridge . the internal status and mask registers and the Vcc control signals would be a special case of Function Context which must be preserved.5 Related Documents PCI Local Bus Specification. Each CardBus function within a device generally has a separate software driver. Latency for returning to the Working state varies on the wakeup environment selected prior to entry of this state (for example.0. Power management involves tradeoffs among system speed. for a PCI-to-CardBus Bridge.). The power management policies of the system ultimately dictate what action is taken as a result of a power management event. PCI Special Interest Group PCI to PCI Bridge Architecture Specification. This single CardBus card may contain up to 8 CardBus Functions.ELECTRICAL SPECIFICATION PCI-to-CardBus Bridge CardBus card (or device) CardBus Function PCI Function Context PCI-to-CardBus bridges couple the PCI bus and the CardBus bus together. The system responds to external events in real time. Function context refers to small amounts of information held internal to the function. It is not safe to disassemble the machine in this state. The primary bus of a CardBus card refers to the bus that is topologically closest to the CPU that is running the operating system. No user mode or system mode code is run. 1994. In this state. Revision 1. A power management event is the process by which a CardBus function can request a change of its power consumption state. For example. A computer state where the computer consumes a small amount of power. A computer state where the computer consumes a minimal amount of power. and a secondary bus interface. The systemÕs context will not be preserved by the hardware. The variable data held by the CardBus function. usually volatile. power state. A computer state where the system dispatches user mode (application) threads and they execute. The system must be restarted to return to the Working state. execution stack (in some cases).0. This state requires a large latency in order to return to the Working state. 1994. battery life. However. devices (peripherals) are dynamically having their power state changed. A physical card consisting of one load on the CardBus bus. etc. noise. PCI Special Interest Group PCI Mobile Design Guide. An event which can be enabled to wake the system from a Sleeping or Soft Off state to a Working state to allow some task to be performed. June 1. It is measured as the total elapsed time between when the system software request for restoration occurs to when the function is fully configured and activated. They are characterized by a primary bus interface. Mechanisms in software and hardware to minimize system power consumption. Typically a device uses a PME to request a change from a power savings state to the fully operational (and fully powered) state. should the system answer phone calls. and AC power consumption. A set of functionality inside a CardBus card represented by one 256 byte configuration space. October 27. Restore time is defined as the time required to fully restore a CardBus function to its fully operational state from a power saving mode of operation. Power Management Event Context is defined as the functional state information and logic required to generated Power Management Events (PMEs). Revision 1. 1995. etc.1. It is not safe to disassemble the machine.). PCI Special Interest Group © 1999 PCMCIA/JEIDA 189 . and enable PMEs. etc. Revision 2. Work can be resumed without rebooting the OS because large elements of system context are saved by the hardware and the rest by system software. It is not safe to disassemble the machine in this state. Function Context is not limited only to the contents of the functionÕs PCI registers. PME Context Power Management Power Management Event (PME) Primary or Ordinate Bus Restore Time Secondary or Subordinate Bus Sleeping State Soft Off State Wakeup Event Working State 6.

1996. Microsoft Corporation PCI Hot-Plug Specification. 190 ©1999 PCMCIA/JEIDA . specified and discussed. 6. by convention. These are D0-D3 with D0 being the maximum powered state.6 Conventions Used in this Chapter Several conventions are used in this chapter to help make it more readable. Intended power savings increase with the power management state number. Microsoft Corporation OnNow Power Management and the Win32 Driver Model. Power management states for PCI buses. Draft Proposals. April 1998 (Release 6. Microsoft Corporation OnNow Design Initiative and ACPI.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS PCI Bus Power Management Specification.2 CardBus Power Management Overview 6. 6. DCH).2.0. Microsoft Corporation Device Class Power Management Reference Specifications. and D3 being the minimum powered state.g. Revision 1. Binary numbers are represented with a following ÒBÓ (e. The higher the number the more aggressive the intended power savings. 10B). Power Management states are denoted by a state number. and end in the power management state number (0-3). 1996. distinct levels of power savings.2. Microsoft Corporation Device Power Management. Signal names are all capitalized and bold as in PME#. Microsoft Corporation and Toshiba Toward the ÒOnNowÓ Machine: The Evolution of the PC Platform. 1996. All numbers are represented in decimal unless followed by a small letter. PCI Special Interest Group PC Card Standard. Mar 18. D1 and D2 power management states enable intermediate power savings states between the D0 (on) and D3 (off) power management states.g. Microsoft Web Page with links to many of the documents above. Throughout this chapter power management states for both CardBus buses and CardBus functions will be defined. • • • • • • • Power states are shown in bold italic text as in D0. Microsoft Technology Brief. and ends with the power management state number (0-3). April 1996. Names of bits or fields within registers are in italic text as in PowerState.0.1. PCI Special Interest Group 6. Register names are shown in bold text as in PMCSR. 1997. Similarly for CardBus functions the power management state is prefixed with a ÒDÓ.1 CardBus Function Power States Up to four power states are defined for each CardBus function in the system. These are listed below. Microsoft Technology Brief.1. PCMCIA/JEIDA Advanced Configuration and Power Interface Specification Revision 1. April 1996. are prefixed with a ÒBÓ.1 CardBus Power Management States Power management states are defined as varying. Intel Corporation. Hexadecimal numbers are represented with a following ÒHÓ (e.1).

6.4. However CardBus functions belonging to different device classes may behave differently when operating in the same power management state. For example. These states are referred to as B0. 6. This specification defines a mechanism that enables explicit control of a CardBus busÕ power and CardBus clock as a function the power management state of its originating device. and CardBus cards. B1. the list of capabilities that an audio subsystem would support in a given power management state would most likely be different than the list of capabilities supported by a graphics controller operating in the same power management state. While Device-Class Power Management Specifications fall outside the scope of this specification.3 Device-Class Specifications The PCI Bus Power Management Interface Specification standardizes the power management hardware interface for the CardBus Bus. the meaning. © 1999 PCMCIA/JEIDA 191 .7.2.PMCSR PCI-to-PCI Bridge Support Extensions (Offset=6) Ð Not Used in CardBus Cards .1 Control of Secondary Bus Power Source and Clock). or intended functional behavior when transitioned to a given power management state is dependent upon the type (or class) of the function. the speed of the clock.2 Bus Power States The power management state of a bus can be characterized by certain attributes of the bus at a given time such as whether or not power is supplied. This is the notion of Device-Class specific power management policy.Reserved.2.2. For a fully integrated power management system. and 6. these class-specific power management policies must also be standardized.1. and what types of bus activities are allowed. Each major device type must have a ÒDevice-Class Power Management SpecificationÓ that all manufacturers can use as a guide to facilitate the seamless integration of their power managed products into a system.ELECTRICAL SPECIFICATION While the concept of these power states is universal for all functions in the system. B2 and B3.5 PMCSR_BSE . The mechanism can be disabled (see 6.3. they are mentioned here to inform the reader of their important relationship to the interfaces defined in this chapter. Each class of device must have its own class specific set of power management policies to define their intended behavior while in each of the power management states.1.

should be specified. If any of these characteristics are in conflict with the requirements of the bus specifications. using the Data register of Function 0. This includes setting the function to wake the system from a sleeping state if certain events occur.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Device-Class Specifications will generally cover the following areas: Device-class power characteristics Each class of CardBus function should have a standard definition for each function power management state. An example might be to require support either for all four power states or for some lesser number. As an example one might consider a hardware administered logic control policy where the common logic can not be internally powered down unless all of the functions hosted by the device have been placed in the D3hot state first. see 6. with implementation details and examples where appropriate. For example. Each class of CardBus function should have a standard definition of its Wakeup policy. This includes specifying the various class-specific events that can wake up the system.1. the network adapter can receive. For example. Control of the common logic is handled by the multi-function device in a software transparent fashion. For further detail on the reporting of CardBus function power consumption. The capabilities are defined as: Get Capabilities operation This operation informs the operating system of the power management capabilities and features of a given function. may be based upon the power states of the functions behind it.3. Minimum Device-Class power capabilities Device-class functional characteristics Device-class Wakeup characteristics 6. It is performed as a part of the Operating SystemÕs device enumeration27 and uses the information it receives to help determine the power management policies to implement in the system. Each class of CardBus function should have a standard definition of the available subset of functioning capabilities and features in each power state. 192 ©1999 PCMCIA/JEIDA . and the functionÕs Wakeup capabilities. For multi-function CardBus cards there is a common portion of bus interface logic that physically binds each of the supported functions to the CardBus bus.2. and so on. and so on. and the power states from which the Wakeup can be signaled. This operation puts the function into a specific power management state and enables power management features based on the global system power management policy and the functionÕs specific capabilities. For further power savings in a runtime environment. This common logicÕs power consumption is explicitly reported if supported.2. if implemented. and state-change latencies. the function may not be able to implement that state on that particular bus. the enabling and disabling of some portion of this common CardBus bus interface logic is the responsibility of the multi-function component hardware. including a recommended resume latency specification. Information required from the function include which power states are implemented. all basic power management operations must be supported by the bus architecture to ensure that CardBus functions on the bus can be power managed. Requirements might also be specified for accuracy and frequency of power status updates. This implicit power control. if so. Each class of CardBus function should have a standard set of power capabilities appropriate to the class.4 Bus Support for CardBus Function Power Management Four base capabilities enable a robust power management solution. This should include target power consumption levels. Set Power State operation Get Power Status operation Wakeup operation While individual CardBus functions must support only the first three capabilities with wakeup being optional. there might be class-specific requirements for Wakeup capabilities. Finally. 27 The CardBus function provides power management capabilities reporting through a standard register definition as specified in this document. This is a mechanism for having a CardBus function wake the system from a sleeping state on specified events. Implementation details for achieving these levels (such as whether an entire functional block is powered-off or the clock is stopped) might be important to a particular device class and. command response latencies. the sound card is fully functional except that the power amps are off. but cannot transmit. all modems should be able to wake the PC from D1. This operation returns information about the current power state of the CardBus function.6 Data (Offset = 7).

6. Of these four capabilities all are required of each function with the exception of wakeup event generation. Setting Power State and System Wakeup.3 Restoring PCI Functions From a Low Power State).1 Capabilities List Data Structure The New Capabilities bit in the PCI Status Register (offset=06h) indicates whether or not the subject function implements a linked list of extended capabilities. Power Status Reporting. Device ID Status (with bit 4 set to 1) Class Code BIST Header Type Latency Timer Vendor ID Command Revision ID Cache Line Size 00h 04h 08h 0Ch 10h 14h Base Address Registers 18h 1Ch 20h 24h CardBus CIS Pointer Subsystem ID Expansion ROM Base Address Reserved Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Cap_Ptr(type 0) Subsystem Vendor ID 28h 2Ch 30h 34h 38h 3Ch Figure 6-3: Standard PCI Configuration Space Header Type 0 Software must have a standard method of determining if a specific function is designed in accordance with this specification. Software can then traverse the list looking for the proper ID for CardBus card PCI Power Management (Cap_ID=01H). the Cap_Ptr register is implemented to give the offset in configuration space for the first item in the list. These Legacy CardBus functions may also require a device specific initialization sequence after any transition from D3cold to D0 (see 6. the function does not support the CardBus PCI Power Management interface described in this chapter and the Operating System will assume that the function only supports the D0 and D3cold power management states. Specifically.ELECTRICAL SPECIFICATION 6. If there is no Capabilities List (New Capabilities bit in the Status register = 0) or if the list does not contain an item with the proper ID. The Status and Capabilities Pointer (Cap_Ptr) fields have been highlighted to indicate where the PCI Power Management features appear in the standard Configuration Space Header.8.3 CardBus Power Management Interface The four basic power management operations that have been defined are: Capabilities Reporting. This is accomplished by using a bit in the CardBus cardÕs PCI Status register to indicate the presence of the Capabilities List and a single byte in the standard CardBus card PCI Configuration Space Header which acts as a pointer to a linked list of additional capabilities.3. © 1999 PCMCIA/JEIDA 193 . This section describes the format of the registers in CardBus configuration space which are used by these operations. if bit 4 is set.

the New Capabilities bit in the PCI Status register (bit 4) should read as Ò0Ó and the Cap_Ptr register should be ignored. If a function does not implement any capabilities with IDs defined by the PCI SIG.3. Values of 00h-3Fh are not valid values for the Cap_Ptr because they point into the standard CardBus cardÕs PCI header. When set this bit indicates the presence of New Capabilities.Cap_Ptr Bits 07:00 Default Value XXH Read/Write Read Only Description The Cap_Ptr provides an offset into the functionÕs CardBus cardÕs PCI Configuration Space for the location of the first item in the Capabilities Linked List. Standard PCI Config Header Type 0 Offset 34h Cap_Ptr 8 bits Next Item ID Capability X Next Item 01h PM Regs Next Item 0 ID Capability Y Figure 6-4: Capabilities Linked List 194 ©1999 PCMCIA/JEIDA . A value of 0 means that this function does not implement New Capabilities. Reserved 03:00 0H Read Only The location of the Capabilities Pointer (Cap_Ptr) depends on the CardBus cardÕs PCI header type.This bit indicates whether this function implements a list of extended capabilities such as PCI Power Management.1 New Capabilities . Table 6-2: Capabilities Pointer .1 Capabilities List Cap_Ptr Location for Header Type specific Cap_Ptr offsets.1. See 6.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Table 6-1: PCI Status Register Bits 15:05 04 Default Value -1B Read/Write -Read Only Description Definition given in PCI Local Bus Specification Revision 2. The Cap_Ptr offset is DWORD aligned so the two least significant bits are always Ò0Ós. A CardBus function may choose any DWORD aligned offset as indicated in Table 6-3: PCI Configuration Space Header Type / Cap_Ptr mappings.

The following table shows where to find the Cap_Ptr register for each of these Header Types.1. size and bit definitions) is specific to each capability. The figure below illustrates the organization of the CardBus Power Management Register Block. The first 16 bits (Capabilities ID [offset = 0] and Next Item Pointer [offset = 1]) are used for the linked list infrastructure. The PCI Power Management capability has an ID of 01H. The CardBus PCI Power Management Register Block is defined in this specification. The first byte of each entry is required to be the ID of that capability.3. and the remaining 8 bit Data register [offset = 8] is optional for any class of function. Table 6-3: PCI Configuration Space Header Type / Cap_Ptr mappings Header Type 0 1 2 Associated PCI Function Type All other PCI-to-PCI Bridge PCI-to-CardBus Bridge Cap_Ptr (PCI Config Space Offset) 34H 34H 14H Minimum Value 040H 040H 080H Maximum Value 0F8H 0F8H 0F8H Regardless of the implemented Header Type the definition of the Cap_Ptr register and the New Capabilities bit in the CardBus PCI Status register is common. that is. The Cap_Ptr gives the location of the first item in the list which is the PCI Power Management Registers in this example (although the capabilities can be in any order). 6.3.1 Capabilities List Cap_Ptr Location There are currently three defined PCI Configuration Space Header types. Power Management Capabilities (PMC) Data PMCSR_BSE Bridge Support Extensions Next Item Ptr Capability ID Offset = 0 Offset = 4 Power Management Control / Status Register (PMCSR) Figure 6-5: Power Management Register Block © 1999 PCMCIA/JEIDA 195 .ELECTRICAL SPECIFICATION The figure above shows how the capabilities list is implemented. As with all PCI configuration registers. the access must be completed normally on the bus and the data is discarded. the Next_Item_Ptr must be set to 0 to indicate that the end of the linked list has been reached. The next 8 bit register (Bridge support PMCSR extensions [offset = 6]) is required only for bridge functions. Each capability can then have registers following the Next_Item_Ptr. If there are no more entries in the list. these registers may be accessed as bytes. 6. The definition of these registers (including layout.2 Power Management Register Block Definition This section describes the CardBus cardÕs PCI Power Management Interface registers. 16 bit words or 32 bit DWORDs. all write operations to reserved registers must be treated as no-ops. Read accesses to reserved or unimplemented registers must be completed normally and a data value of 0 returned. Unless otherwise specified. The next byte is a pointer giving an absolute offset in the functionÕs CardBus PCI Configuration space to the next item in the list and must be DWORD aligned. The next 32 bits (PMC [offset = 2] and PMCSR registers [offset = 4]) are required for compliance with this specification.

The information in this register is generally static and known at design time. The value given is an offset into the functionÕs CardBus cardÕs PCI Configuration space. when read by system software as 01H indicates that the data structure currently being pointed to is the PCI Power Management data structure. then this register must be set to 00H.3 PMC .3.2. If there are no additional items in the Capabilities List.Power Management Capabilities (Offset = 2) The Power Management Capabilities register is a 16 bit read-only register which provides information on the capabilities of the function related to power management.Cap_ID (Offset = 0) The Capability Identifier.3. Table 6-4: Capability Identifier . 6.Cap_ID Bits 07:00 Default Value 01H Read/Write Read Only Description ID . 6.Next_Item_Ptr Bits 07:00 Default Value 00H Read/Write Read Only Description Next Item Pointer .Next_Item_Ptr (Offset = 1) The Next Item Pointer Register describes the location of the next item in the functionÕs capability list. Table 6-5: Next Item Pointer . this register is set to 00H.2.1 Capability Identifier .2.This field.This field provides an offset into the functionÕs PCI Configuration Space pointing to the location of next item in the functionÕs capability list.3.2 Next Item Pointer . 196 ©1999 PCMCIA/JEIDA .PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS The offset for each register is listed as an offset from the beginning of the linked list item which is determined either from the Cap_Ptr (If Power Management is the first item in the list) or the Next_Item_Ptr of the previous item in the list. Each function of a PCI device may have only one item in its capability list with Cap_ID set to 01H. or if power management is the last item in the list. If the function does not implement any other capabilities defined by the PCI SIG for inclusion in the capabilities list. when Ò01HÓ identifies the linked list item as being the PCI Power Management Registers. 6.

CSTSCHG can not be asserted unless PME_En is set. are defined to be ÒstickyÓ bits for functions that can generate power management events from D3cold. D2 and D3xxx. Functions that do not support PME# generation in any state must return Ò0Ó for this field. or by using non-volatile storage cells for them. will cause these bits to change state from a Ò1" to a "0". bit(11) XXXX1B Ð PME# can be asserted from D0 bit(12) XXX1XB Ð PME# can be asserted from D1 bit(13) XX1XXB Ð PME# can be asserted from D2 bit(14) X1XXXB Ð PME# can be asserted from D3hot bit(15) 1XXXXB Ð PME# can be asserted from D3cold 10 Device Specific Device Specific 000B Device Specific Device Specific Read Only D2_Support .4 PMCSR . Auxiliary Power Source (VAUX) -This bit is only meaningful if bit 15 (D3cold supporting PME#) is a Ò1Ó. 03 0B Read Only PME Clock . A value of 0B for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. Preservation of these bits is typically achieved by either powering them with an auxiliary power source.3.If this bit is a Ò1Ó.For definition regarding the Device Specific Initialization bit.If this bit is a Ò1Ó. setting PME_En in state D0 really performs no additional function other than causing the CSTSCHG signal to be latched into the PME_Status field of the PMCSR. The Power Management Event support bits. 08:06 05 04 Read Only Read Only Read Only Reserved DSI .A value of 001B indicates that this function complies with the Revision 1. in states D1. These bits follow the ÒstickyÓ rules associated with any PCI device. the CardBus cardÕs PME# signal.When this bit is a Ò1Ó it indicates that the function relies on the presence of the PCI clock for PME# operation.This five bit field indicates the power states in which the function may assert PME#. Only a software write to each bit or complete removal of all Vcc voltages. bit(15)=0. © 1999 PCMCIA/JEIDA 197 . this function supports the D1 Power Management State. to be latched into the PMCSRÕs PME_Status bit.0 of the PCI Power Management Interface Specification. this causes CSTSCHG. and PME_En. The only way to clear out these bits is to have system software write to them with the appropriate values. A Ò0Ó in this bit indicates that the function supplies its own auxiliary power source. this function supports the D2 Power Management State. 02:00 001B Read Only Version . Functions that do not support D2 must always return a value of Ò0Ó for this bit.Power Management Control/Status (Offset = 4) This 16 bit register is used to manage the PCI functionÕs power management state as well as to enable/monitor power management events. For a CardBus card. PME_Status. see the PCI Bus Power Management Specification. Functions that do not support D1 must always return a value of Ò0Ó for this bit. When this bit is a Ò0Ó it indicates that no PCI clock is required for the function to generate PME#.2. When this bit is also a Ò1Ó it indicates that support for PME# in D3cold requires auxiliary power supplied by the system by way of a the slot Vcc pins and will consume less than 200 mA. 09 Read Only D1_Support . including VAUX. 6. then this field must always return Ò0Ó. in that their states are not affected by power on reset or transitions from D3cold to the D0 Uninitialized state.ELECTRICAL SPECIFICATION Table 6-6: Power Management Capabilities Ð PMC for CardBus Cards Bits 15:11 Default Value Device Specific Read/Write Read Only Description PME_Support . However. Again. If the function does not support PME# while in D3cold.

its PME Function Context is not affected by either a CardBus slot reset. the PME Function Context is defined as the logic responsible for identifying power management events. the PME Function Context must be preserved for the system software to process. including the Power Management Event support bits. Because a CardBus bus CRST# assertion does not necessarily clear all functionsÕ PME Function Context. Therefore. PME Function Context also contains any device class specific status that must survive the transition to the D0 Uninitialized state as well. and each functionÕs PME_Status bit must be written with a "1" by system software as part of the process of initializing the system. the logic responsible for generating the PME# (CSTSCHG) signal and the bits within this register that provide the standard system interface for this functionality. (hardware component reset). for all functions during initial operating system load. If PME# (CSTSCHG) generation is not supported from D3cold then all PME Function Context is initialized with the assertion of a bus segment reset. If a function supports PME# (CSTSCHG) generation from D3cold. CRST#.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS As mentioned previously. or the internal "soft" reinitialization that occurs when restoring a device from D3hot. (functions that support PME# (CSTSCHG) from D3cold). the system software is required to explicitly initialize all PME Function Context. 198 ©1999 PCMCIA/JEIDA . This is because the functionÕs Power Management Event functionality itself may have been responsible for the wake event which caused the transition back to D0. In terms of the PMCSR this means that during the initial operating system load each functionÕs PME_En bit must be written with a "0".

indeterminate at time of initial OS boot if function supports PME# (CSTSCHG) from D3cold. the write operation must complete normally on the bus. This field is required for CardBus cards. See 6.2. If the function supports PME# (CSTSCHG) from D3cold then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. See 6. The definition of the field values is given below. indeterminate at time of initial OS boot if function supports PME# (CSTSCHG) from D3cold. 12:09 0000B Read Write Data_Select . 14:13 Device Specific Read Only Read/ Write Read/ WriteClear Description PME_Status .3. Read/ Write PME_En . 07:02 01:00 000000B 00B Read Only Read/ Write Reserved PowerState . 0B.3. Writing a "0" has no effect.6 Data (Offset = 7)for more details.This two bit field is used both to determine the current power state of a function and to set the function into a new power state.Reserved PMCSR_BSE supports PCI bridge specific functionality and is required for all PCI-to-PCI and PCI-toCardBus bridges. if the function does not support PME# (CSTSCHG) from D3cold.D1 10B . This bit defaults to "0" if the function does not support PME# (CSTSCHG) generation from D3cold.D2 11B . optional state to this field. if the function does not support PME# (CSTSCHG) from D3cold. If the function supports PME# (CSTSCHG) from D3cold then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded.ELECTRICAL SPECIFICATION Table 6-7: Power Management Control/Status .3.PMCSR Bits 15 Value at Reset Sticky Bit.5 PMCSR_BSE . The value and meaning of this field will vary depending on which data value has been selected by the Data_Select field.D3hot If software attempts to write an unsupported. however the data is discarded and no state change occurs. Writing a "1" to this bit will clear it and cause the function to stop asserting a PME# (CSTSCHG) (if enabled).This two bit read-only field indicates the scaling factor to be used when interpreting the value of the Data register. 08 Sticky Bit.2. When "0" PME# (CSTSCHG) assertion is disabled.2.D0 01B . 00B .6 Data (Offset = 7)for more details. 6. This field is required for CardBus cards.This four bit field is used to select which data is to be reported through the Data register and Data_Scale field. 0B."1" enables the function to assert PME# (CSTSCHG). © 1999 PCMCIA/JEIDA 199 . Data_Scale .PMCSR PCI-to-PCI Bridge Support Extensions (Offset=6) Ð Not Used in CardBus Cards .This bit is set when the function would normally assert the PME# (CSTSCHG) signal independent of the state of the PME_En bit. This bit defaults to "0" if the function does not support PME# generation from D3cold.

Table 6-9: Data Register Bits 07:00 Default Value 00H Read/Write Read Only Description Data .Reserved Reserved 6.Reserved B2_B3# (B2/B3 support for D3hot) . The Data register is used by writing the proper value to the Data_Select field in the PMCSR and then reading the Data_Scale field and the Data register. Typically the data returned through the Data register is a static copy (look up table.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Table 6-8: PMCSR Bridge Support Extensions .This register is used to report the state dependent data requested by the Data_Select field. This data is required for CardBus cards. 200 ©1999 PCMCIA/JEIDA . The binary value read from Data is then multiplied by the scaling factor indicated by Data_Scale to arrive at the value for the desired measurement. The table below shows which measurements are defined and how to interpret the values of each register.3.6 Data (Offset = 7) The Data Register is an 8 bit read-only register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. but only power usage is defined by this version of the specification. The Data_Select and Data_Scale fields must also be implemented.PMCSR_BSE Bits 07 06 05:00 Value at Reset 0 0 000000B Read/Write Read Only Read Only Read Only Description BPCC_En (Bus Power/Clock Control Enable) .2. The value of this register is scaled by the value reported by the Data_Scale field. Any type of data could be reported through this register. for example) of the functionÕs worst case "DC characteristics" data sheet.

1 W resolution. This excludes any power delivered to external devices but must include any power derived from a battery or external power source and dissipated inside the computer chassis. Power should be reported as accurately as possible. and other functions (greater than function 0) within a multi-function device) 0 = Unknown 1-3 = TBD 0 = Unknown 1-3 = TBD TBD TBD 0 = Unknown 1 = 0. It should not include any power derived from a battery or an external source. © 1999 PCMCIA/JEIDA 201 . The "Power Dissipated" values provide the amount of heat which will be released into the interior of the computer chassis. the values reported through this register may need to be loadable through a serial EPROM or strapping option at reset much like the Subsystem Vendor ID and Subsystem ID registers Multi-function devices implementing power reporting should report the power consumed by each function in each corresponding functionÕs Configuration Space.01x 3 = 0. This information is useful for fine grained thermal management. the data returned for each state supported must indicate the maximum power used by the function when in that particular state. 0 to 2.3 VDC The power measurements defined above have a dynamic range of 0 to 25. The "Power Consumed" values defined above must include all power consumed from the PCI power planes through the PCI connector pins.01 W resolution or 0 to 255 mW with 1 mW resolution.1x 2 = 0. If the PCI card provides power to external devices that power must be included as well.55 W with 0. For example. The sum of the values reported should then be accurate for the condition of all functions in the device being put in that state. This information is useful for management of the power supply or battery.ELECTRICAL SPECIFICATION Table 6-10: Power Consumption/Dissipation Reporting Value in Data_Select 0 1 2 3 4 5 6 7 8 Data Reported D0 Power Consumed D1 Power Consumed D2 Power Consumed D3 Power Consumed D0 Power Dissipated D1 Power Dissipated D2 Power Dissipated D3 Power Dissipated Common logic power consumption (Multi-function PCI devices.001x Watts Data_Scale Interpretation Units/Accuracy 9-15 8-15 When using the Data register as a window into the data sheet for the PCI function. If a function allows a wide range of implementation options. Function 0 only) Reserved (function 0 of a multifunction device) Reserved (single function PCI devices. the common logic power consumption is reported in function 0Õs Configuration Space through the Data register once the Data_Select field of the function 0Õs PMCSR has been programmed to "1000B". In a multi-function device.5 W with 0. data returned must comply with measurements derived from the following test environment: • • Bus Frequency: VCC: 33 MHz 3.

6. For a CardBus bus. The B2 state carries forward the characteristics of the B1 state. If an access is attempted to a function residing downstream of a bus that is not 28 Enforced by the operating system which has previously programmed the functions residing on. but also has its clock stopped. CardBus compliant Stopped Bus Activity Any CardBus Transaction. The table below shows a mapping of the four defined power states to key characteristics of the PCI bus. The PC Card Standard defines a bus power (VCC) and clock control mechanism.4. Bus may be off if VCC removed Stopped PME Event Each CardBus bus in a system has an originating device which can support one or more power states. Table 6-11: CardBus Bus Power Management States CardBus Bus States B0 (Fully On) B1 B2 Vcc On On On Clock Free running.1 CardBus B0 State . Function Interrupt.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Each function of each device on the card is responsible for reporting the power consumed by that function. A bus in B0 is capable of running any legal CardBus transaction. that particular bus segment to power management states that would preclude normal CardBus transactions or functional interrupts from occurring. the CardBus bus can be characterized at any point in time by one of four power management states. and further downstream of.4 CardBus Bus Power States This section describes the different power states of the CardBus bus itself. 6. 202 ©1999 PCMCIA/JEIDA . or PME Event PME Event PME Event B3 Indeterminate except CRST# asserted and CCLK stopped low. B0 corresponds to the bus being fully useable (full power. The B1 bus power management state is defined as a fully powered yet "enforced" idle28 CardBus bus with its clock free running. Since B0 is the only CardBus Bus power management state where data transactions can take place.Fully On All buses support B0 by default. From a power management perspective. In most cases this will be some kind of a bridge such as a PCI-to-CardBus Bridge. system software must ensure that a CardBus bus is in B0 before attempting to access any CardBus resources on that bus. and B2 represent intermediate power management states. B1. CardBus compliant Free running. and clock frequency) and B3 meaning that the power to the bus has been switched off or is indeterminate. the clock control mechanism is CCLKRUN# and the Vcc control mechanism is the Vcc control registers.

the transaction must be treated as if a "Master Abort" had occurred and error reporting handled in the same manner. Note that the bridge controller may not cause slot Vcc settings to change when returning to D0 from any power state except on a card removal event. For new CardBus functions compliant with the CardBus PCI Bus Power Management Interface Specification this means that all functions must have been previously programmed to a power management state that. The CardBus card is not allowed to initiate any transaction in these states except PME. Vcc may be removed from all devices and the CardBus card may be operating on VAUX which may be supplied through the CardBus slot Vcc pins and limited to 200 mA. the CardBus card must be in device state D1. with the possible exception of a power management event. the PCI-to-CardBus bridge device can use this information to intelligently apply more aggressive power savings in the bridgeÕs design. has precluded any bus activity on their parts. It is the system softwareÕs responsibility to ensure that.3 CardBus B2 State When a CardBus bus is in B2.4. However no bus transactions are allowed to take place on the bus except type 0 configuration cycles. Vcc is still applied to all devices on the bus. There is a minimum time requirement of 50 ms which must be provided by system software between when the bus is switched from B2 to B0 and when a device on the bus is accessed to allow time for the clock to start up and the bus to settle.4. 6. after the bridge controller receives its bus segment reset (RST#). the bridge controller must assert CRST# for its subordinate bus segments for slots having Vcc applied. prior to attempting to program the CardBus bus to a power management state other than B0. all CardBus card functions residing on that CardBus bus have previously been programmed to a state that would preclude any further bus activity initiated by them. 6. When full Vcc is reapplied to the CardBus bus. provides the bridge function with information indicating that no functions residing on the bus will attempt to initiate any bus transactions. The busÕs originating device must always exit from B0 gracefully by first allowing the bus to settle into the idle state.Off In B3. Clock run may be asserted. 6. In the B1 state. for each of them.ELECTRICAL SPECIFICATION in B0. and the bus brought to an active. CRST# must be asserted for that bus segment.7 Control/Status of CardBus Bus Power Management States). the CardBus bus is idle with the clock running.4 CardBus B3 State . Vcc is still applied to all devices on the bus but the clock is stopped using the CCLKRUN# protocol if implemented. All CardBus Bus signals are required to be held at valid logic states at all times.4. if comprehended by the bridge design (see 6.4. consistent with the Electrical Specification. idle state in accordance with the Electrical Specification. In the case of when the PCI-to-CardBus bridge in the D3cold state.2 CardBus B1 State When a CardBus bus is in B1. For legacy CardBus functions system software must rely on other means such as disabling the Bus Master Enable bit of the legacy functionÕs CardBus Command register to ensure that the function does not attempt to initiate any bus transactions. and held in the low state. This information could then be used to intelligently apply more aggressive power savings in the bridge design. Before the CardBus bus can be in the B1 state. The B2 state. D2 or D3. © 1999 PCMCIA/JEIDA 203 . Nor do any of the CardBus functions require a CardBus clock. therefore.

A programmable interface for placing a bus in B3. Mobile PCI Clock Run protocol also meets this requirement. Unless otherwise specified. Removing all power always takes the bus to B3.5 CardBus Bus Power State Transitions The CardBus Bus Power States can be changed as shown in the figure below. These programmed function power state transitions implicitly have impact on the next power state for a particular bus. or restoring it from B3 is optional. 6. A bridge may optionally support B3 when its power state is programmed to D3hot.4. which writes to the appropriate location in the busÕs originating device. 204 ©1999 PCMCIA/JEIDA . must either directly drive and control the clock to their secondary bus and/or provide sideband information to an external clock source for that bus segment. All buses support B3 by default if power is removed from the system. B0 (On) B2 (Clock Stopped) B1 (Idle Bus) B3 (Off) Figure 6-6: PCI Bus PM State Transitions A system reset always returns the CardBus bus to B0. All other bus state changes are made by software. all CardBus bus clocking is required to be Electrical Specification compliant.6 CardBus Clocking Considerations PCI-to-CardBus bridge functions. 6.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS B3 is exhibited by all PC Card Standard compliant systems when their power is removed.4.

The D3hot state may cause its secondary busÕs power management state to transition to either B2 or B3. as defined in this specification. dictates that a CardBus function must be at the same or greater power management state as that of the bus it physically resides on. a PCI-to-CardBus bridge whose secondary bus is in B1 could correctly assume that no CardBus functions on its secondary bus will attempt to initiate any bus traffic until the bridgeÕs state is changed to D0 which would result in the secondary busÕs transition to B029. an originating bridge functionÕs PMCSR PowerState field the operating system can explicitly set. So by writing to. Table 6-12: PCI Bus Power and Clock Control Originating DeviceÕs Bridge PM State D0 D1 D2 D3hot Secondary Bus PM States B0 B1 B2 B3 Resultant Actions by Bridge (either direct or indirect) None or CCLKRUN# none or CCLKRUN# Clock stopped on secondary bus or CCLKRUN# Clock stopped and Vcc may be removed from the slot. 6. adhere to the general policy that a busÕs power state follows.7. permission is granted as applicable.7 Control/Status of CardBus Bus Power Management States CardBus bus power management states. and that of its secondary bus.ELECTRICAL SPECIFICATION 6. When the PCI-to-CardBus bridge desires to stop the clock to the CardBus card. The third column defines actions that must occur as a direct consequence of the originating deviceÕs PowerState field having been programmed to the current power management state. it uses the clock run 29 Bus activity wouldnÕt actually resume until the downstream functions were also programmed to states that permitted bus transactions to occur. as defined in 6.4. New PCI-to-CardBus bridge designs could take advantage of this information regarding its surroundings to potentially achieve further power savings in their designs. Behavioral policy for power managed CardBus functions on a given bus. When the CardBus card requires that the clock be started again. or tracks. Clock control for the PCI-to-CardBus bridgeÕs CardBus bus is accomplished using the Mobile PCI clock run protocol. and power source of a CardBus bus.5. © 1999 PCMCIA/JEIDA 205 . that of its originating deviceÕs power management state. The following table defines the relationship between an originating PCI-to-CardBus bridge functionÕs power management state.1 Control of Secondary Bus Power Source and Clock This section defines the standard mechanism that system software uses to control the clock. (See definition of B2_B3# in Table 6-8) D3cold B3 VAUX support only CCLK stopped low CRST# low Note that the power management state of a CardBus bus segment follows that of its originating bridgeÕs power management state with one exception. it requests permission from the card. If the card supports stopping the clock. or determine its CardBus busÕs power management state.6 CardBus Card Function Power Management Policies. or reading from. This mechanism ties control of secondary bus power and clock to the originating deviceÕs power management state. For example.4.

Functions in the D3cold state can only be transitioned to an uninitialized D0 state by reapplying Vcc and asserting Card Reset (CRST#) to the functionÕs CardBus device. CardBus functions operating in either D0. the CardBus card can still request that the clock be started only if PME_EN is true. for example. Once initialized by the system software the function will be in the D0 active state. It is expected that the PCI-to-CardBus bridge use the clock run protocol to stop the clock in when the PCI-to-CardBus bridge is placed in device state D2/B2. This describes the D0/B0 scenario. 6. Functions in D3hot can be transitioned to an uninitialized D0 state via software by writing to the functionÕs PMCSR register or by having itÕs Bus Segment Reset (CardBus CRST#) asserted. each with its own CardBus configuration space. Transitioning from D0 unitialized to D0 active occurs when the functionÕs appropriate memory.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS protocol to request that the CardBus clock be started from the PCI-to-CardBus bridge. I/O or bus master enable bits are enabled. Legacy CardBus functions built prior to the CardBus Bus Power Management Interface specification are assumed to be in D0 whenever power is applied to them. the CardBus card must be capable of the clock run request being denied because the PCI-to-CardBus bridge may not have a PCI clock to pass on to the CardBus bus. All CardBus functions must support D0 and a reset will force all CardBus functions to the uninitialized D0 state. interrupts and functions are fully functional. Each CardBus device can host multiple functions. A CardBus function must initially be put into D0 before being used. and low power feature availability tradeoffs for a given device class. be supported as a slightly more power consuming state than D2. D2. or transition from D3hot. 6. D1.5 CardBus Function Power Management States CardBus defines a device as a physical load on the CardBus bus. The clock run protocol cannot be exercised in device state D3. Each CardBus function can be in one of four power management states. restore time. 206 ©1999 PCMCIA/JEIDA . or by physically removing power from its CardBus device. In device state D2.1 CardBus Function D0 State All CardBus functions must support the D0 state. however one that yields more available features and quicker restore time than could be realized from D2. All CardBus card functions that adhere to this specification are required to support D0 and D3hot. or D3hot are required to be compliant with the Electrical Specification.2 CardBus Function D1 State Implementation of the D1 power management state is optional. The D3 power management state constitutes a special category of power management state in that a function could be transitioned into D3 either by software. In CardBus card device states D1 and D2. each function must implement its own power management interface. the device will be in an uninitialized state. Since each CardBus function is an independent entity to the software. Upon entering D0 from power on reset.5. All of PCI and CardBus Configuration Space. In that sense the two D3 variants have been designated as D3hot and D3cold where the subscript refers to the presence or absence of Vcc respectively. 6. CardBus cards which utilize the D3cold must consume less than 200ma of Vcc current when placed in the D3 state with PME_En true. D1 and D2 are optional power management states for CardBus cards. The D1 state could. These intermediate states are intended to afford the system designer more flexibility in balancing power savings.5.

All of CardBus PCI Configuration Space is functional. Functional context is preserved but not accessible. PME_En and PME_Status are functional only if the card supports PME in the D3 state. This allows time for the function to reset itself and bring itself to a power-on condition. Initiated actions such as bus mastering and functional interrupt request generation can only commence after the function has been restored to the D0 active state. memory and I/O spaces are disabled). 6. In this state function context need not be maintained. All of PCI Configuration Space can be read and is valid. Some functions may be processing background tasks such as monitoring the network which actually requires most of the function to be active. When a CardBus Function is not currently being used and probably will not be used for some time. 6.5. When programmed to D0 the function performs the equivalent of a warm (soft) reset internally. Allowable behavior for a given function in D1 is dictated by the Device-Class-Power Management Specifications for that class of function.1 Software Accessible D3 (D3hot) Functions in D3hot must respond to configuration space accesses as long as power and clock are supplied so that they can be returned to D0 by software. 6. When the function is brought back to D0 (the only legal state transition from D3) software will need to perform a full reinitialization of the function including its CardBus PCI configuration space.5. All of PCI and CardBus Configuration Space is functional.5. Configuration Space must be accessible by system software while the function is in D2.e. undefined system behavior may result. In this state the only CardBus bus operation the CardBus card function is allowed to initiate is a power management event (PME). The function is only required to respond to PCI configuration accesses (i. This state requires the function to provide significant power savings while still retaining the ability to fully recover to its previous condition. the end result from a software perspective is that the function will be in the D0 Uninitialized state. it may be put into D2.4.3 CardBus Function D2 State Implementation of the D2 power management state is optional. functional and CSTSCHG interrupts are not available. System software must restore the function to D0 active before memory or I/O space can be accessed. However if power management events (PME) are supported from D3 then PME context must be retained at a minimum. PME# is functional.4 CardBus Function D3 State All CardBus functions must support D3. The PowerState. There is a minimum recovery time requirement of 200 µs between when a function is programmed from D2 to D0 and when the function can be next accessed as a target (including CardBus Configuration Accesses).ELECTRICAL SPECIFICATION D1 is used as a light sleep state. There is a minimum recovery time requirement of 10 ms (enforced by system software) between when a function is programmed from D3 to D0 and when the function is accessed (including CardBus Configuration Accesses). If an access is attempted in violation of the specified minimum recovery time. PME_En and PME_Status bits must be functional. and returns to the D0 Uninitialized state without PCI RST# being asserted and without asserting © 1999 PCMCIA/JEIDA 207 . It is important to note that regardless of whether the function is transitioned to D0 from D3hot or D3cold.

it must provide a minimum of 200 mA of IAUX for each slot so indicated. The unlabeled arcs represent a software initiated state transition (Set Power State Operation). It is appropriate for the CardBus card to enter the D3cold state from the D3hot state when PME_En is true and the host CardBus bus enters state B3. The power required to do this must be provided by some auxiliary power source assuming that no power is made available to the PCI device from the normal Vcc power plane. Other bus activity may be taking place during this time on the same CardBus bus segment so the device that has returned to D0 Uninitialized state must ensure that all of its CardBus signal drivers remain disabled for the duration of the D3hot to D0 Uninitialized state transition30. PME context takes precedence over initialization default context when returning from a PME_En enabled D3cold state.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS CRST#. The CardBus card can then qualify the D3cold transition by PME_En true.2 Power Off (D3cold) If Vcc. 6. thus the CardBus card can utilize the transition of the bus to transition from D3cold to D0 uninitialized.5. 6.4. If the host platform supports D3cold power management events. CardBus cards have no method to determine when the cardÕs state is D3cold and not D3hot. When power is restored.5 CardBus Function Power State Transitions All CardBus function power management state changes are explicitly controlled by software except for hardware reset which brings all functions to the D0 Uninitialized state. the poweron defaults will be restored to the function by hardware just as at initial power up. when the CardBus bus transitions from B3 to B0. The figure and table below shows all supported state transitions. CardBus CRST# must be asserted and functions will return to D0 (D0 Uninitialized state) with a full PC Card Standard Electrical Specification compliant power-on reset sequence. All CardBus device functions support this state by default. 208 ©1999 PCMCIA/JEIDA . CRST# low (asserted). is removed from a CardBus card device. The function must then be fully initialized and reconfigured by software after making the transition to the D0 uninitialized state. Whenever the transition from D3 to D0 is initiated through assertion of CardBus CRST#. all of its CardBus functions transition immediately to D3cold. the bus continues to assert CRST# for 100 clocks. including VAUX. By specification. 4CardBus bus signal drivers must behave the same as if the component had received a CRST#.5. The only function context that must be retained in D3hot and through the soft reset transition to the D0 Uninitialized state is the PME context. Functions that support power management events from D3cold must preserve their PME context through the D3cold to D0 transition. There is a required delay of 10 ms when changing the state from D3 to D0 before the CardBus card can be accessed.

ELECTRICAL SPECIFICATION Power on Reset D0 Uninitialized CRST# D0 Active D2 soft reset D3 cold D1 D3 hot Vcc removed Vaux applied Figure 6-7: PCI Function Power Management State Transitions © 1999 PCMCIA/JEIDA 209 .

D2. The figure below illustrates the areas being discussed in this section.5. 210 ©1999 PCMCIA/JEIDA . D2. D3 D0 uninitialized via bus segment reset Off D0. D3 D0 uninitialized via bus segment reset Off D0.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Table 6-13: State Diagram Summary Present state D0 (unitialized) Valid next states Software: á á á á D0 (active) á á á D1 á á á D2 á á á D3hot á á á á D3cold á á á D0 (active) D3 D0 uninitialized via bus segment reset Off D1.6 CardBus Card Function Power Management Policies This section defines the behavior for CardBus card functions. D3 D0 uninitialized via bus segment reset Off D0 uninitialized D0 uninitialized via bus segment reset D3cold if VAUX supplied Off None D0 uninitialized via bus segment reset Off Hardware: Software: Hardware: Software: Hardware: Software: Hardware: Software: Hardware: Software: Hardware: 6.

whichever is greater. Configuration register and functional state information that are required to be valid for the given power management state. If the bus is fully accessible (B0) then this delay is solely the result of the state transition delay. following the last write to the functionÕs PowerState field. B2 or B3) then the delay is characterized by either the functionÕs state transition recovery time. and the features that must remain available for a given class of device are typically dictated by the corresponding Device-class power management specification. If the bus is not in a fully accessible state (B1. or the time it takes to restore the bus to a fully accessible state. Valid CardBus bus transactions that can be conducted with the function as the target of the transaction. and/or operations that can be initiated by the function. Valid CardBus bus transactions. or recovery time. Power consumption The minimum required delay before attempting to access the CardBus function to change its power state. Current power management state of the CardBus functionÕs hosting CardBus bus segment. Legend: CardBus Function PM State CardBus Bus PM State Context Current CardBus function power management state.ELECTRICAL SPECIFICATION PCI to CardBus Bridge SCOPE Config Regs CardBus Card Config Regs CardBus Card Function Function Figure 6-8: Non-Bridge CardBus Function Power Management Diagram The following tables define the behavior for a CardBus card function while operating in each combination of bus and functional power management states. The registers that must remain valid. (Measurement beginning from either a write to the functionÕs PMCSR. The total time from when a CardBus function transitions from its current power management state to the fully configured D0 active state. or a bus segment reset). Power Access Delay Restore Time Actions to Function Actions from Function © 1999 PCMCIA/JEIDA 211 .

PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Table 6-14: D0 CardBus Card Power Management Policies CardBus Bus PM State B0 B0 CardBus Function PM State Legacy CardBus Function (D0) D0 (Uninitialized) Context Power Access Delay None None Restore Time None None Actions to CardBus card Any CardBus Transaction CardBus Config Cycles Actions from Function Full PME Context* Full <70mA Vcc: off -> on. 245mA if transitioning from D3cold with PME_En true Full N/A** Any CardBus Transaction or Interrupt None B0 B1-B3 D0 (Active) D0 (Active) Full N/A** None N/A** None N/A** Any CardBus Transaction N/A** Any CardBus Transaction or Interrupt. or < D0 uninitialized N/A** 200 µs (Note 1) PME only* B1 D2 Greater of either the bus restoration time or 200 µs (Note 2) Greater of either the bus restoration time or 200 µs (Note 2) N/A** None PME only* B2 D2 Device Class Specific and PME Context* Device Class Specific none PME only* B3 D2 N/A** N/A** N/A** N/A** 212 ©1999 PCMCIA/JEIDA . PME* N/A** Table 6-15: D1 CardBus Card Power Management Policies CardBus Bus PM State B0 CardBus Function PM State D1 Context Power Access Delay Restore Time Device Class Specific Device Class Specific N/A** Actions to CardBus card CardBus Config Cycles None Actions from Function Device Class Specific and PME Context* Device Class Specific and PME Context* N/A** < D0 uninitialized < D0 uninitialized N/A** None PME only* B1 D1 Bus restoration time N/A** PME only* B2-B3 D1 N/A** N/A** Table 6-16: D2 CardBus Card Power Management Policies CardBus Bus PM State B0 CardBus Function PM State D2 Context Power Access Delay Restore Time Device Class Specific Device Class Specific Actions to CardBus card CardBus Config Cycles Actions from Function Device Class Specific and PME Context* Device Class Specific and PME Context* < next lower supported PM state. or < D0 uninitialized < next lower supported PM state. or < D0 uninitialized < next lower supported PM state.

5. Additional Notes: 1. or < D0 uninitialized < next lower supported PM state. or < D0 uninitialized < next lower supported PM state. (see 6. In this case the bus restoration time is dictated by state transition recovery times incurred in programming the busÕs originating device to D0 which then transitions its bus to B0.1 State Transition Recovery Time Requirements) When in D1. it must always be ready to accept a CardBus configuration access when in D1. Bus restoration time is typically the deciding factor in access delay for this case. or boot latency full context restore. © 1999 PCMCIA/JEIDA 213 . A CardBus function cannot tell the state of its CardBus bus. 2. It specifies the case where the system software has programmed the functionÕs PowerState field and then immediately decides to change its power state again.ELECTRICAL SPECIFICATION Table 6-17: D3hot CardBus Card Power Management Policies CardBus Bus State B0 CardBus Function PM State D3hot Context Power Access Delay Restore Time Device Class Specific Device Class Specific Actions to CardBus card CardBus Config Cycles Actions from Function PME and functional context* PME and functional context* < next lower supported PM state.6. Typically the state transition recovery time will have expired prior to a power state change request by software. This condition is not typical. or < D0 uninitialized 10 ms (Note 1) PME only* B1 D3hot Greater of either the bus restoration time or 10 ms (Note 2) Greater of either the bus restoration time or 10 ms (Note 2) N/A none PME only* B2 D3hot PME and functional context* Device Class Specific none PME only* B3 D3hot PME and functional context* N/A none PME only* Table 6-18: D3cold CardBus Card Power Management Policies CardBus Bus State B3 CardBus Function PM State D3cold Context Power Access Delay Restore Time full context restore. or < D0 uninitialized < next lower supported PM state. D2 or D3hot. State transition recovery time begins from the time of the last write to the functionÕs PowerState field. or slot specific power supplies which is outside the scope of this specification. *** Implies device specific. or boot latency Actions to CardBus card none Actions from Function PME context only* VAUX N/A PME only* B3 Legacy CardBus Function (D3) none No Power N/A none none Notes: * If PME is supported in this state ** This combination of function and bus power management states is not allowed. The more typical case where the bus must first be restored to B0 before being able access the function residing on the bus to request a change of its power state. therefore. D2 or D3hot a CardBus function must not respond to CardBus transactions targeting its I/O or memory spaces or assert a functional interrupt request.

The following sections describe how these mechanisms work for CardBus cards. This section details the power management policies for CardBus card functions. The shaded regions in the figure below illustrate what will be discussed in this section. While defining Device-Class specific behavioral policies for most functions is well outside of this specificationÕs scope. The CardBus card function can be characterized as a CardBus bus load.6. The mechanisms for controlling the state of these function vary somewhat depending on which type of originating device is present. between the time that a function is programmed to change state and the time that the function is next accessed (including CardBus configuration space).1 State Transition Recovery Time Requirements The following table shows the minimum recovery times (delays) that must be guaranteed.6 CardBus Cards and Power Management With power management under the direction of the operating system each class of devices (PCI and CardBus functions) must have a clearly defined criteria for feature availability as well as what functional context must be preserved when operating in each of the power management states.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS 6. by hardware in some cases and by system software in others. D1 or D2 D1 D2 D3hot Next State D1 D2 D3hot D0 D0 D0 Minimum System Software Guaranteed Delays 0 200 µs 10 ms 0 200 µs 10 ms 6. 214 ©1999 PCMCIA/JEIDA . The definitions here apply to the PCI-to-CardBus cards. defining the required behavior for the CardBus interface function is within the scope of this specification.5. Table 6-19: CardBus Function State Transition Delays Initial State D0 D0 or D1 D0. Some example Device-Class specifications have been proposed as part of the Intel/Microsoft/Toshiba ACPI Specification for various functions ranging from audio to network adapters.

Legend: Bridge PM State Secondary CardBus Bus State Secondary CardBus Attributes Downstream Function Attributes Current CardBus function power management state of bridge function. The characteristics of the secondary bus for the current bus power management state. Current power management state of the originating deviceÕs CardBus bus segment. Also detailed are the resultant attributes of the secondary bus. Necessary attributes of a CardBus function residing on the secondary bus given the secondary busÕs power management state.ELECTRICAL SPECIFICATION PCI PCI Bus Segment PCI to CardBus Bridge SCOPE Config Regs Function Config Regs Function Config Regs CardBus Segment Function Figure 6-9: CardBus Card Power Management Diagram The following table defines the relationship between a bridge functionÕs power management state. The rightmost column of the table details a set of conditions that all "downstream" CardBus card functions must be capable of withstanding when residing on a bus in a given state without their application breaking in a way that cannot be gracefully recovered from. It is the responsibility of the system software to ensure that only valid. workable combinations of bus and downstream PCI-to-CardBus bridge and CardBus bus function power management states are used for a given CardBus bus and the CardBus card functions residing on that bus. and that of its secondary bus. © 1999 PCMCIA/JEIDA 215 .

power on defaults PME_En true PME context Power consumed by the CardBus card is < 70 mA if coming from no Vcc or VAUX. functional context is not available. CardBus card PCI configuration space is readable. If clock run is not functional in the PCI-to-CardBus bridge. Card responds appropriately to all CardBus bus cycles Power consumed by the CardBus card is as specified by the vendor for the D0 / B0 state D1 Software: á á á D0 D2 D3 Vcc: On Bus: B1 CardBus clock is running unless Clock Run is asserted. clock is off CardBus bus is idle CardBus card functional and CardBusStatusChange interrupts are not available CardBus card PME# is available if PME_En is true CardBus card responsibilities: All context. only CardBus card Power Management Control and Status Register PowerState bits are required to be writeable CardBus card only responds to CardBus type 0 cycles Power consumed by the CardBus card is as specified by the vendor for the D1 / B1 state but must be lower than the < 200mA D2 Software: á á D0 D3 Vcc: On Bus: B2 CardBus clock is not running unless Clock Run is required by CardBus card. If clock run is not functional in the PCI-to-CardBus bridge. clock is on CardBus bus is fully functional CardBus card functional and CardBusStatusChange interrupts are functional All context. CardBus card PCI configuration space is readable. PCI and functional.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Table 6-20: CardBus Card Power Management Policies Present state D0 (unitialized) Valid next states Software: á á D0 (active) D3 CardBus Card Requirements in Present State Vcc: On Bus (including CCLK): Per PC Card Standard for appropriate card technology Context (CardBus bus in B0) PME_En false No context. functional context is not available CardBus card only responds to CardBus type 0 cycles Power consumed by the PCI-to-CardBus bridge is as specified by the vendor for the D2 / B2 state but must be lower than the D1 / B1 state Hardware: á D0 uninitialized via CardBus bus segment reset á Off Hardware: á D0 uninitialized via PCI bus segment reset á Off Hardware: á D0 uninitialized via PCI bus segment reset á Off Hardware: á D0 uninitialized via PCI bus segment reset á Off 216 ©1999 PCMCIA/JEIDA . clock is on CardBus bus is idle CardBus card functional and CardBusStatusChange interrupts are not available CardBus card PME# is available if PME_En is true CardBus Card responsibilities: All context. If clock run is not functional in the PCI-to-CardBus bridge. PCI and functional. PCI and functional. is preserved. is available. is preserved. < 245mA if PME_En true and returning from D3cold state D0 (active) Software: á á á D1 D2 D3 Vcc: On Bus (including CCLK): B0 CardBus clock is running unless Clock Run is asserted.

6. however it does define a signal with similar intended usage. PME_En must make the CardBus card power management event functionality act as if the CardBus card were a standard PCI device.6. When the operating system sets PME_En true. Setting PME_En false must clear (0) GWAKE and WKUP as well. PME_En and PME_Status bits are required to be functional CardBus card only responds to CardBus type 0 cycles Power consumed by the PCI-to-CardBus bridge is as specified by the vendor for the D3 / B3 state but must be lower than the D2 / B2 state D3cold Software: á None Hardware: á D0 uninitialized via PCI bus segment reset á Off Vcc: Off.2 PME_En/PME_Status and CardBus Cards A CardBus cardÕs PME_En has special requirements unlike a standard PCI device because there is no CardBus device driver defined in an ACPI operating system. CardBus card PCI configuration space is readable. In order to support power management events using an ACPI operating systemÕs PCI device driver. The CardBus function must continue to target the GWAKE bit in the Function Event Register as the function general wakeup event. When enabled (PME_En true). this action must set (1) the GWAKE (bit 4) and WKUP (bit 14) bit fields in the CardBus Function Event Mask Register. PME_Status functionality maps to CardBusÕs CSTSCHG and PME_En functionality maps to CardBusÕs GWAKE / WKUP. 6. CardBus card CardBus PME context consists of the CardBus Function Event Register and the CardBus Function Event Mask Register. VAUX on if required Bus: Off CardBus clock is off CardBus bus is indeterminate except CRST# and CCLK which must be low Interrupts are not available Card PME# is available if PME_En is true CardBus card responsibilities: Only PME context is preserved if PME_En is true Does not respond to any PCI cycles Power consumed by the CardBus card is required to be < 200 mA 6.ELECTRICAL SPECIFICATION D3hot Software: á D0 uninitialized Hardware: á D0 uninitialized via PCI bus segment reset á á D3cold if VAUX supplied Off Vcc: On Bus: B3 CardBus clock is off CardBus bus is indeterminate except CRST# and CCLK which must be low Interrupts are not available CardBus card PME# is available if PME_En is true CardBus card responsibilities: Only PME context is preserved if PME_En is true. The Card Status Change signal will be used as a source for power management events for a CardBus card and /Status Change will be used for a PC Card. Clearing the GWAKE / WKUP mask © 1999 PCMCIA/JEIDA 217 . the PME_En bit must support generating a CSTSCHG for a CardBus card. a CSTSCHG event is latched into PME_Status and the CardBus cardÕs GWAKE bit in the Function Event Register. The PCI-to-CardBus Bridge will use this event as one condition for assertion of PME#. only CardBus card Power Management Control and Status Register PowerState. functional PME context is not available.1 CardBus Card Context CardBus does not define a PME# signal.

D2 and D3. There may be additional PME function context which must be preserved. however. The level and signal translation will be performed in the PCI-to-CardBus bridge. 6. Setting the Function Event Mask RegisterÕs READY (Ready/Busy). Writing a "1" to the PME_Status bit will clear the GWAKE bit in the Function Event Register and clearing the GWAKE bit in the Function Event Register clears the PME_Status bit in the PMCSR register. then the assertion of CSTSCHG is latched into the CardBus cardÕs PCI Power Management PME_Status bit. Once asserted. active low signal that is to be driven low by a PCI function to request a change in its current power management state and/or to indicate that a power management event has occurred. Since CardBus does not have a pin to dedicate to the PME# function. CardBusÕs CSTSCHG will implement the functionality. BVD2. but that is implementation specific and is not addressed in this specification. these bits are not required to track PME_En and BVD1. . READY and WP are not required to follow PME_Status. It is expected that ACPI software configures power management in a CardBus card using PME_En / PME_Status. setting PME_En false will prevent the CSTSCHG pin from being asserted and clear the GWAKE and WKUP bits in the Function Event Mask Register. It is imperative that each hardware configuration set be controlled by the appropriate software controller.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS bits does not clear the PME_En bit in the PMCSR. Table 6-21: PME_En / PME_Status Summary in a CardBus Card ACPI Operating System CardBus PCI Configuration Space PME_En Default 0 Written 1 1 1 Written 0 DonÕt care Function Event Mask Register Function Event Register GWAKE Default 0 0 0 1 1 0 CardBus pin CardBus PCI Configuration Space PME_Status Default 0 0 0 Latches CSTSCHG change 1 Written 1 GWAKE Default 0 WKUP Default 0 CSTSCHG Default 0 0 0 1 0 0 Follows PME_En 1 1 Follows PME_En DonÕt care DonÕt care 1 1 Non-ACPI Operating System No effect Per Electrical Specification No effect The setting of the CardBus cardÕs PME_En enables the CSTSCHG signal to be active in states other than D0.7 Power Management Events The Power Management Event (PME#) signal is defined as an open drain. CardBus devices must be enabled by software before asserting this signal. If PME_En is false. CSTSCHG can be asserted with or without PME_En true in device state D0. BVD1:2 (Battery Voltage detects) and WP (Write Protect) may also generate a CSTSCHG event. Furthermore. the device must continue to drive the signal low until software explicitly clears the PME_Status or 218 ©1999 PCMCIA/JEIDA . If CSTSCHG is asserted. Only if PME_En is true can the CardBus card assert CSTSCHG in device states D1. If PME_En is true. it is expected that a CardBus card configured through PME_En / PME_Status generate a PME# through the CardBusÕ bridge and a non-ACPI configured CardBus card generate a CSTSCHG through the CardBusÕ bridge. Non-ACPI software should work with the CardBus Function Event registers. changes in the CardBus card Function Event registers have no effect on PME_En / PME_Status.

Likewise. Such devices must maintain the value of the PME_Status bit through reset (CRST#). This requirement is true even though the operating system software may clear the Event Register bits which caused the PME.7.1 Auxiliary Power for D3cold Power Management Events Power managed systems that support PME generation while in the D3cold state may require an auxiliary power source. The CardBus card must not consume more than 200 mA Icc when: 1. 2. On-Board Battery AC "Brick" adapter. See Figure 6-10: Vcc to VAUX Transitioning for more information. externally provided power source Auxiliary power supplied by the system In the case of the CardBus card. the function will assert CSTSCHG. 4. When a CardBus card function generates or detects an event which requires the system to change its power state (e.ELECTRICAL SPECIFICATION PME_En bit in the PMSCR register of the function. VAUX must remain stable for 50 ms after Vcc is up and stable. 6. It must continue to assert CSTSCHG until software either clears the PME_En bit or clears the PME_Status bit in the PMCSR even if the source of the power management event is no longer valid (e. 3. D3cold. © 1999 PCMCIA/JEIDA 219 . There are several ways to provide auxiliary power for any necessary "keep alive" circuitry including but not limited to: 1. PME_STATUS and PME_En are only cleared when written with a "1". the auxiliary supply provided for the controller will be limited to 200 mA provided via the Vcc pins as there are no pins available on the CardBus card connector that can be designated VAUX. the phone rings). PCI bus power management aware software will enable its use by setting the PME_En bit in the PMCSR. Additionally. 2. Some devices which are powered by a battery or some external power source may use this signal even when powered off. the phone stops ringing). the transition from Vcc to VAUX must include the stable application of VAUX for a minimum of 50 ms prior to transitioning Vcc off.g. when transitioning from off to on.g. 3. The CardBus card is programmed to the D3 state and The CardBus clock is stopped and The CardBus bus is idle and The PME_Support bit 15. bit is set The transition from Vcc to VAUX can occur only after the above three conditions are implemented.

8 Software Support for PCI Power Management The PCI Power Management specification for CardBus defines the requirements for PCI and CardBus functions to be managed by an Operating System. and reading the Power Management Capabilities Register (PMC). and remain in whatever state it was in before the request. it is necessary to address some of the basic assumptions that have been made regarding which aspects of power management are enforced by system software versus by hardware such that the functions might react appropriately. Restoring PCI and CardBus Functions from a Low Power State.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Vcc CardBus going inactive VAUX 50ms Vcc transitions to VAUX Figure 6-10: Vcc to VAUX Transitioning 6. for any reason. Placing PCI and CardBus Functions in a Low Power State. This is NOT a hardware error condition. The specification does not attempt to define any sort of Power Management Policy. However. If. Within each of these areas. It is the Operating SystemÕs responsibility to ensure that it does not attempt to place a function into a power management state which the function does not support. the function should handle this gracefully31. It must be noted that in the context of this chapter references to the Operating System software include any device drivers and other Operating System specific power management services.8.1 Identifying CardBus Function Capabilities The Operating System software is responsible for identifying all CardBus function power capabilities by traversing the New Capabilities structure in CardBus cardÕs PCI Configuration space. not the intended invalid state which was written. the Operating System software attempts to put a function into a power management state that the function does not support. 220 ©1999 PCMCIA/JEIDA . That is left up to the individual Operating System. it has been assumed that the Operating System software will handle certain power management functions in addition to itÕs basic power management policy. The PowerState bits of the PMCSR will reflect the current state of the function. and Wake Events. 31 Finish the PCI transaction with normal completion and ignore the write data. These assumptions fall into four basic categories: Identifying PCI and CardBus Function Capabilities. 6.

This is accomplished by either programming the hosting busÕs originating device to D0. then the Operating System should not put the device into D3.3 D3 State Restoring a function from D3 requires the Operating System to reinitialize the function. System software must ensure that sufficient time elapses between when the PMCSR is updated and when the first access targeting that PCI function may occur.3. Full context must be restored to the function before it is capable of resuming normal operation. beginning with.B3) the Operating System must first ensure that all CardBus functions on that bus have been placed in an appropriate low power state. or in the case of a Bridge device. 6.8. In other words. If the Operating System and the PCI function both support Wake Events. Furthermore.2. If the Operating System is not capable of fully reinitializing a device. 6. it is the Operating SystemÕs responsibility to ensure that the function has no pending (host initiated) transactions. it is the Operating SystemÕs responsibility to notify any and all device drivers that are conducting peer-to-peer transfers to the target function that the target function will no longer be accessible.3 Restoring PCI Functions From a Low Power State 6.2 Placing CardBus Functions in a Low Power State When attempting to place a CardBus function in a low power state D1 . restoring power to the device and initiating a PCI Bus Segment Reset.8.2 D3 State Prior to placing a CardBus function into D3.3. re-enabling the I/O and Memory spaces. The Operating System must make sure that it has the appropriate driver loaded for that function in order to restore the functions to operation.2 D1 and D2 States Restoring a function from D1 or D2 simply requires the Operating System to update the PowerState field of the PMCSR. 6. Restoration includes reinitializing the function.D3.1 Dx States and the DSI Bit For support of the DSI (Device Specific Initialization) bit.ELECTRICAL SPECIFICATION 6. but is not necessarily limited to restoring the Base Address Registers.3.8.8. for the case of D3cold. that there are no CardBus functions behind the bridge that require the bridge to be in the fully operational D0 state. re-enabling Bus © 1999 PCMCIA/JEIDA 221 . the Operating System should enable the functionÕs Power Management Event ( PME# CardBus cardÕs CSTSCHG) line via the PME_En bit in the functionÕs Power Management Control Register (PMCSR). When placing a function into D3.8. consult the PCI Bus Power Management Specification. 6. 6.1 Buses When attempting to place a CardBus Bus segment into a lower power management state (B1.8. or by other ACPI-type control methods. For example reintialization includes. the Operating System must determine if it has the capability to restore the function from this state. the Operating System Software is required to disable I/O and memory space as well as Bus Mastering via the CardBus PCI Command Register.8.2. it is the Operating SystemÕs responsibility to ensure that no peer-to-peer activity occurs with the sleeping CardBus function as the target.

6. but whether this interrupt is handled by a device driver or an Operating System service routine.8. it is the system hardwareÕs responsibility to restore the Host processor subsystem to a state which will permit the Operating System to function (through ACPI or some other architecture). baud rate. or functions had generated PME#. the Operating System should follow this procedure for any subsequent PCI bridges. When the client is called upon to interact with the modem (such as a ring-resume event). Should PME# become deasserted before the Operating System identifies the device which generated it.8. Transitioning from D0 unitialized to D0 active is defined when the appropriate memory and IO windows and busmastering enable bits are set by the operating system. the Operating System will have transitioned the modem function to the D0 initialized state. Furthermore.PCI BUS POWER MANAGEMENT INTERFACE FOR CARDBUS CARDS Master capabilities. This information is often client specific. modulation characteristics. 6.2 The D0 "Initialized" State From a Wake Event Before the Operating System returns a function to D0 which will require a re-initialization of the function. 222 ©1999 PCMCIA/JEIDA . The System is responsible for notifying the Operating System that a PCI Power Management Event has occurred. Once the Operating System has been notified that a PCI PME has occurred. or before the PME# is serviced. it must ensure that the Operating System not only has the information necessary to reinitialize the function.8. then the system hardware does not need to take any special action.4 Wake Events 6.1 Wake Event Support PCI Power Management supports Wake events generated by functions on the PCI bus in which the CardBus cardÕs CSTSCHG becomes a PME# event. However restoration of the modem function to D0 alone may not be sufficient for the function and client to perform the indicated task. It is manifest upon Device-Class specifications to include sufficient context save requirements for successful restoration of a function.4. It is expected that PME# will generate some form of System Configuration Interrupt (SCI). the Operating System must be able to handle multiple PME#s generated by different functions simultaneously. it is the Operating SystemÕs responsibility to restore power to the primary PCI and CardBus bus and to restore it to the B0 state. assume a modemÕs client has set up a modem function in a specific state additional to default initialization (error correction. is left up to the individual Operating System architecture. the Operating System must recover gracefully. If the sub-system is already in a D0 state. As an example. then to restore power to any unpowered slots/devices. Upon identifying the source or sources of the PME#. and unmasking any IRQs or PCI Interrupts as well as restoring the INT Line register. but also any information necessary to restore the function as well. Furthermore. The restoration must be transparent to the extent that the host application is unaware that a power state transition and the associated restoration occurred. The client/function then goes unused for an extended amount of time which may cause the power manager to place the modem in a D2 or perhaps even a D3 state. the Operating System is required to execute whatever initialization code is necessary. it is up to the Operating System Power Management Policy to identify the correct course of action with regard to waking the functions and/or the rest of the system.). if the function has the DSI bit set. If the generating device is a bridge device. either via the device driverÕs initialization code or executing POST.4. and finally query the PCI and CardBus functions that have been configured with PME# enabled to determine which function. Assuming the Operating System supports Wake Events. etc.

6.8.8. whether or not the device supports waking the machine and from what power states it is capable of wakeup.6 Set Power State The Set Power State operation is used by the operating system to put a device into one of the four power states. Therefore functions should update status information bits ONLY after carrying out the intended task. This operation will read the PMC and PMCSR to obtain this information. Software assumes that reported status information reflects the current state of the function.8.9 Other Considerations In addition to supporting the minimum set of required mechanisms defined in this specification. The operating system will track the state of all devices in the system. taking advantage of the optional headroom provided by this specification.ELECTRICAL SPECIFICATION 6. The PCI Mobile Design Guide makes several suggestions on designing for low power which are applicable to all devices. 6. This includes which power states the device supports. Get Capabilities tells the Operating System information about what power management features the device supports. Even simple things such as minimizing current drain through pull-up resistors can add up to real power savings. 6.7 Get Power Status The Get Power Status operation is used by the operating system to determine the present state of the power configuration (power states & features). Additional power saving techniques while in D0 are also encouraged as long as they are transparent to the operating system. Designers are encouraged to design for low power consumption in all operating modes. © 1999 PCMCIA/JEIDA 223 .5 Get Capabilities The Get Capabilities operation is performed by the operating system as it is enumerating devices in the system. designers of PCI devices and systems are encouraged to add additional power management functionality.

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but it is expected to grow. 7. The current list of defined encodings is small.A 7 . HALT is a broadcast message from the processor indicating it has executed a halt instruction. © 1999 PCMCIA/JEIDA 225 .2 Use of Specific Encodings Use or generation of architecture-specific encodings is not limited to the requester of the encoding. SP E C IAL CYC L E M E S S AGE S Special cycle message encodings are defined in this appendix.1 Message Encodings CAD[15::0] 0000H 0001H 0002H 0003H Ñ FFFFH Message Type SHUTDOWN HALT x86 Architecture Specific Reserved SHUTDOWN is a broadcast message indicating the processor is entering into a shutdown mode. Reserved encodings should not be used. Specific meanings are defined by Intel Corporation and are found in product specific documentation. These encodings allow system specific communication links between cooperating CardBus PC Card devices for purposes which cannot be handled with the standard data transfer cycle types. 7. Specific encodings may be used by any vendor in any system. The x86 Architecture Specific encoding is a generic encoding for use by x86 processors and chipsets. CAD[31::16] determine the specific meaning of the special cycle message.ELECTRICAL SPECIFICATION AP P E N D IX .

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These include: 1. Connectors used for CardBus PC Card implementations shall provide sufficient signal ground return paths to support 33 MHz operation. The focus of this procedure is on the connector alone. This procedure or methodology. 3. 8. The frequency of operation.1 General Recommendations 1. This does not diminish the importance of the other factors listed above. The design impedance of the boards should be matched to the CardBus PC Card drivers chosen. CAR D BU S PC CAR D CON N E C T OR TE S T M E T H OD OL OGY This appendix outlines a methodology which may be used to quantify the effect CardBus PC Card and host connectors have on system noise levels. it just allows for a concise test procedure to be documented for the connector. in conjunction with in-system testing.2. is intended to provide connector manufacturers with a standard for evaluation of their product performance. The test hardware should provide sufficient flexibility to meet the recommendations defined in this appendix. several other factors may influence signal integrity across the interface.1 Background There are many factors which contribute to overall signal quality and integrity across the CardBus PC Card interface. The number of outputs switching simultaneously. The test system should be on a stable platform and be capable of repeatable noise measurements. 227 © 1999 PCMCIA/JEIDA . In order to understand the effect of any one variable in a system the effect of other variables must be minimized. The CardBus PC Card connector system is comprised of a mated pair of CardBus PC Card connectors as specified by the Physical Specification. The test hardware for this system includes the connectors. including maximum ground bounce noise for the interface. of which the CardBus PC Card connector is one of the most significant. 2. 8. mounting boards. 2.ELECTRICAL SPECIFICATION AP P E N D IX . In addition to the connector. interface circuitry and test/measurement equipment necessary to perform the evaluation. 4.B 8 . 75 ohms is typical. 8. The quality of local and bulk decoupling on the host system and CardBus PC Card.2 Test Hardware Recommendations This section defines the test hardware recommended for evaluation of the CardBus PC Card connector system. The output edge rate transmitted across the interface. The CardBus PC Card Electrical Specifications defines the criteria for 33 MHz operation.

3. The output edge rate seen at the connector should be the maximum allowed by the CardBus PC Card specification.2 Host-side Requirements 1. 10X.5 pF.2. The board layouts and features of each are provided as examples of a functional test setup. 7. The test board should be capable of driving or receiving at least 45 signals simultaneously. The output edge rate seen at the connector should be the maximum allowed by the CardBus PC Card specification.CARDBUS PC CARD CONNECTOR TEST METHODOLOGY 8. 4. Individual adaptations and variations are acceptable as long as the results produced are comparable to those achievable with the described setup. 7. 8. It is recommended that series damping resistors be used to tune edge rates across the interface. The power source should develop a clean VCC at voltages from 3. 1 Megohm impedance Less than 1" in length HP54100 (or equivalent) Digitizing at 1 Gsample/S 8.3 Card-side Recommendations 1. 5. 228 ©1999 PCMCIA/JEIDA . 8.2. The card boards should be capable of being stacked to accommodate 2 card vertical socket arrangements. Test board construction and design should be consistent with current PC Card methodology. 3. The test board should be capable of both driving and receiving signals. 6. Either on or off board signal generation capable of 33 MHz speeds should be provided to drive the CardBus PC Card interface I/O devices. It is recommended that series damping resistors be used to tune edge rates across the interface. 2. Either on or off board signal generation capable of 33 MHz speeds should be provided to drive the CardBus PC Card interface I/O devices. 5.4 Measurement Equipment Recommendations The following test equipment considerations are recommended to support the test and measurement activities: Probe: Probe GND: Oscilloscope: Active FET probe 1. 6.2. 8. 4.0 to 3.3 Test Board Considerations This section provides block diagram layouts for both test boards and identifies the major attributes of each. 2.6 volts and have a current rating of at least one ampere. The test board should be capable of switching at least 45 outputs simultaneously into each CardBus PC Card socket. Test board construction and design should be consistent with current mobile computer methodology. It should be possible to measure ground bounce and VCC droop at all test points. It should be possible to measure ground bounce and VCC droop at all test points.

No vias between device pins and connector pins to maintain trace impedances which are designed for 75 ohms.1 Host-side Implementation The following features are descriptive of the test board used for the host side of the test setup (reference Figure B-1: Host-side Test Board Layout): • • • • • • • • • • • • Surface mount series resistance on all signal lines. or equivalent. the power source. Utilizes HP8180. Three (3) pin headers allow for static high or low noise measurements at each test point. Eight (8) 16245. or equivalent. Crosstalk measurement points may be terminated or unterminated. and for every device. I/O DRIVERS I/O DRIVER DATA INPUT POWER SUPPLY CardBus PC Card GROUND BOUNCE MEASUREMENT I/O DRIVER DATA MONITOR I/O DRIVER TRANSMIT/RECEIVE CARD 0 AND 1 GROUND BOUNCE MEASUREMENT I/O DRIVER GROUND BOUNCE CONTROL GROUND BOUNCE MEASUREMENT Connector I/O DRIVERS SERIES RESISTOR TERMINATION – AS REQUIRED Figure 8Ð1 Host-side Test Board Layout © 1999 PCMCIA/JEIDA 229 . Test points designed to accommodate 1 GHz FET probe. I/O drivers (24 mA output drive) Word wide control over OE# signals. or equivalent. Maximum capacitive decoupling provided at the connector. Corner mounting holes provide for sturdy platform mounting. allows for varied number of outputs switching. Matched trace lengths for simultaneous switching experimentation.3. Utilizes 16245. word generator to drive I/O devices. devices allow for greater than 45 outputs switching into each socket at the same time.ELECTRICAL SPECIFICATION 8.

Matched trace lengths for simultaneous switching experimentation. I/O DRIVERS I/O DRIVER DATA INPUT GROUND BOUNCE MEASUREMENT I/O DRIVER DATA MONITOR CardBus PC Card GROUND BOUNCE MEASUREMENT I/O DRIVER TRANSMIT/RECEIVE CARD 0 AND 1 GROUND BOUNCE MEASUREMENT Connector SERIES RESISTOR TERMINATION – AS REQUIRED I/O DRIVER GROUND BOUNCE CONTROL I/O DRIVERS Figure 8Ð2 Card-side Test Board Layout 230 ©1999 PCMCIA/JEIDA .): • • • • • • • • • • • • Surface mount series resistance on all signal lines. Utilizes HP8180 or equivalent word generator to drive I/O devices. I/O drivers (8 mA output drive) Byte-wide control over OE# signals. Maximum capacitive decoupling provided at the connector and for every device. Utilizes TI VHC245. which are designed for 75 ohms Corner mounting holes provide for sturdy platform mount and board stacking capability. Three (3) pin headers allow for static high or low noise measurements at each test point. devices allow for greater than 45 outputs switching. or equivalent. or equivalent.CARDBUS PC CARD CONNECTOR TEST METHODOLOGY 8. Test points designed to accommodate 1 GHz FET probe.2 Card-side Implementation The following features are descriptive of the test board used for the card side of the test setup (See Figure 8Ð2 Card-side Test Board Layout. Eight (8) TI VHC245. No vias between device pins and connector pins to maintain trace impedances. allows for varied number of outputs switching. Crosstalk measurement points may be terminated or unterminated.3.

as follows: Driver Host Host Card 0 Card 1 Receiver Card 0 Card 1 Host Host 8. © 1999 PCMCIA/JEIDA 231 . all driver devices should be enabled. A true worst case may be found by applying the two worst singular conditions for Cards 0 and 1 simultaneously across the vertical CardBus PC Card connector and measuring as before. Then the data timing is adjusted so all outputs are actively switching simultaneously at frequency. In a two card vertically mounted host system. The most important aspect of this is in the design of the test system itself. The test system should provide multiple ground bounce test points positioned as far away as possible from connector power and ground pins.1 Finding the Worst Case Ground Bounce The technique for finding a "worst case" is simply to try all available alternatives and use the measurement point that provides the highest ground bounce measurement. Ground bounce data may then be taken at each test point.ELECTRICAL SPECIFICATION 8. Now that the worst case measurement point has been located. four singular Card-Host driver-receiver pairings are possible.6 V Frequency = 1 MHz Card conditions: VCC = 3. This "local" reference gives an accurate picture of what the receiving devices will "see" and respond to in a system. Host Conditions: VCC = 3. This technique may then be applied to each of the four singular combinations above.6 V Frequency = 1 MHz To find worst case ground bounce.4. the frequency may be ramped to 33 MHz and the ground bounce monitored to ensure proper operation to the maximum CardBus PC Card system frequency. In this configuration.4 Measurement Methodology The ground bounce measurements should always be taken in reference to the "local" ground. the test system is supporting at least 45 outputs switching across the CardBus PC Card interface.

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Ó 9. For example. 9. PC Cards not using a custom interface shall not be adversely affected by the presence or state of a custom interface capability anywhere in the host. For example.1. list the headings and describe the contents of each paragraph required.1.ELECTRICAL SPECIFICATION AP P E N D IX . PC CAR D CU S T OM I N T E R F AC E S 9. where x is two (2) and above. As an example: ÒThis interface supports random access to 16 Bytes of memory address per memory space using signals A[3::0].x. 9. I/O (Bi-directional). Identify each custom interface signal under one of four classifications: I (Input).5 Custom Interfaces. Ò9.1. (See also 4. Describe signals not available to cards using the custom interface while the custom interface is enabled.Ó 9. The title of paragraph 9. 9.5 Signal Description Describe each signal as used while the custom interface is active. O (Output). a custom interface that redefines the SPKR# signal does not allow a PC Card to use the optional 16-bit PC Card Binary Audio signal.1 and its subordinates. © 1999 PCMCIA/JEIDA 233 .2 ZV Port (0141H).1 Purpose/Overview Describe the custom interface giving the primary purpose and an operational overview of the interface. 9.1. and R (Reserved).1.1 Custom Interface Requirements The features and capabilities of specific custom interfaces are described in this appendix.2 Compatibility The addition of support for a custom interface does not relax any requirement in both the host and the card associated with 16-bit PC Cards or CardBus PC Cards.3.) This section.4 Features Describe the features of the custom interface. Input signals are driven by the host and output signals are driven by the card. is the name for the custom interface followed by the custom interface identification number in parenthesis.3 Pin Assignments Describe all pin assignments.C 9 .

234 ©1999 PCMCIA/JEIDA .6 Functions Describe the functions for any and all address spaces available while the custom interface is active.1. 9.9 Specific Signals and Functions Provide further discussion. 9.7 Timing Describe the access timing for any and all address spaces available while the custom interface is active.1.1.1. of specific signals and functions available while the custom interface is active. Include logic levels and address decoding mechanisms in describing the electrical interface.8 Electrical Interface Identify the characteristics of the electrical interface while the custom interface is active.PC CARD CUSTOM INTERFACES 9. as needed. 9.

2.2 Compatibility The addition of support for the ZV Port interface does not relax any requirement associated with 16bit PC Cards or CardBus PC Cards in either the host or the card. When either the 16-Bit PC Card memory only interface or the ZV Port interface is active the card shall support direct access to 16 © 1999 PCMCIA/JEIDA 235 . or a teleconferencing card could also be plugged into the PC Card slot.2. The ZV Port complies with CCIR601 timing to allow NTSC decoders to deliver real-time digital video straight into the VGA frame buffer from a PC Card. TV LCD CRT SPEAKERS PCI Local Bus 256Kx16 DRAM Analog Encoder Amp VGA Audio Codec PC Card Slot PC Card ZV Port (Video) 19 PCM Audio Input 4 Audio PCM Converter 4 PC Card Host Adapter Audio PC Card Interface 19 Video & Control Video Decoder Video NTSC/PAL RF Signal Motherboard Figure 9-1 Example ZV Port Implementation 9. 9. The diagram demonstrates how TV in a window could be achieved in a portable computer with a low cost PC Card. PC Cards implementing the ZV Port interface shall present the 16-Bit PC Card memory only interface following the application of VCC or the RESET signal.1 Overview The following diagram shows the system level concept of the ZV Port.2 ZV Port Custom Interface (0141H) The ZV Port is a single-source uni-directional video bus between a PC Card socket and a VGA controller. PC Cards not using the ZV Port interface shall be unaffected by the presence or state of the ZV Port interface capability anywhere in the host. An MPEG.ELECTRICAL SPECIFICATION 9. The ZV Port also uses an industry standard mechanism for transferring digital audio PCM data to a low cost DAC for conversion to an analog signal.

The Input Port Acknowledge (INPACK#) signal is not available when the ZV Port interface is active. The I/O Is 16 Bit Port (IOIS16#) signal is not available when the ZV Port interface is active.1.) Direct access to any address beyond the first 16 Bytes of attribute or common memory is undefined. (See 4.3 Pin Replacement Register. 16-bit PC Card DMA operation shall not be supported in a socket when the ZV Port interface is active because the entire set of pins over which the DREQ# signal can be routed.)The Battery Voltage Detect 2 (BVD2) signal may be available in the cardÕs Pin Replacement register while the ZV Port interface is active.16 Indirect Access to PC Card Memory. digital audio PCM is provided. The Audio Digital Waveform (SPKR#) signal is not available when the ZV Port interface is active.9 Specific Signals and Functions. are in use. (See 9. (See 4.PC CARD CUSTOM INTERFACES Bytes (signals A[3::0]) of attribute and common memory space and provide access to two 64 Mbyte indirect memory spaces using registers in common memory. SPKR#.) 236 ©1999 PCMCIA/JEIDA .15. INPACK# or IOIS16#. PC Cards supporting I/O operations while using the ZV Port interface shall indicate eight or 16 bit I/O access via the TPCE_IO field in the CISTPL_CFTABLE_ENTRY tuple.

PC Card signals not mentioned in the table below.2. remain unchanged from the 16-bit PC Card I/O and Memory interface. then V[7::0]. UV[7::0] starts with U[7::0] at the first pixel of the line. "O" indicates signal is output from PC Card. After HREF has started. I/O and Memory Interface Signal Name A10 A11 A9 A8 A13 A14 A16 A15 A12 A7 A6 A[5::4] A[3::0] IOIS16# A17 A18 A19 A20 A21 A22 A23 A24 A25 INPACK# SPKR# I/O and Memory I/O 1 I I I I I I I I I I I I I O I I I I I I I I I O O ZV Port Interface Signal Name HREF VSYNC Y0 Y2 Y4 Y6 UV2 UV4 UV6 SCLK MCLK RESERVED ADDRESS[3::0] PCLK Y1 Y3 Y5 Y7 UV0 UV1 UV3 UV5 UV7 LRCLK SDATA ZV Port I/O 1 O O O O O O O O O O O RFU I O O O O O O O O O O O O Comments Horizontal Sync to ZV Port Vertical Sync to ZV Port Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Audio SCLK PCM Signal Audio MCLK PCM Signal Put in three state by Host Adapter No connection in PC Card Used for accessing PC Card Pixel Clock to ZV Port Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Video Data to ZV Port YUV:4:2:2 format Audio LRCLK PCM signal Audio PCM Data signal "I" indicates signal is input to PC Card. then U[7::0].3 Pin Assignments The following table shows the function of various PC Card signals when the ZV Port custom interface mode is set in the PC Card Host Adapter. É © 1999 PCMCIA/JEIDA 237 .ELECTRICAL SPECIFICATION 9. Table 9-1 ZV Port Interface Pin Assignments PC Card Pin Number 8 10 11 12 13 14 19 20 21 22 23 24::25 26::29 33 46 47 48 49 50 53 54 55 56 60 62 1. the transfer of UV data always starts with the U component.

1 35 2 GND GND 36 HREF VSYNC Y0 Y2 Y4 Y6 Y7 UV0 VCC VPP UV2 UV4 UV6 (SCLK) A7 (MCLK) A6 UV5 UV7 UV1 UV3 VCC VPP Y3 Y1 Y5 Reserved A3 A2 A1 A0 SPKR# (SDATA) INPACK# (LRCLK) 33 PCLK 34 67 GND 68 GND Figure 9-2 ZV Port Signals on PC Card Socket 238 ©1999 PCMCIA/JEIDA .PC CARD CUSTOM INTERFACES The following diagram shows the PC Card socket and the location of the signals that carry video/audio signals when the PC Card and the Host Adapter are in ZV Port mode. This diagram shows the rationale behind selecting these signals to maintain signal integrity and minimize noise.

9. The unused address pins are used to define the 19 pin ZV Port data bus.5.2. and 4 wire digital audio interface. Because ZV Port restricts PC Card memory access to four address lines. The address lines A[25::4]. 9. The maximum rate is 16 MHz.5.2 VSYNC This signal supplies the vertical synchronization pulse to the ZV Port that displays the video data. 9. BVD2/SPKR# and INPACK# signals are then replaced by ZV Port signals which carry video/audio data from the PC Card to the ZV Port. For an MCLK frequency of 256Fs the LRCLK to SCLK ration must be 32. 9.5.16 Indirect Memory Access and see also the Metaformat Specification. A[3::0].1 PCLK This signal is used to clock valid data and HREF signal into the ZV Port. control signals.5.2. When the ZV Port custom interface is selected in the PC Card Host Adapter.) 9. (See 4.2. rising edge of PCLK is used to clock the 16-bit pixel data into the ZV Port. The ZV Port interface has the following unique signals detailed in the sections below.2.5.2.2. The primary difference is that the address signals A[25::4] are put in three state by the PC Card Host Adapter thereby restricting the Common Memory space address range to sixteen bytes and the Attribute Memory space address range to eight valid bytes.2.5. cards implementing the ZV Port interface will also implement indirect memory access.2. most of the host adapter control signals and data bus follow the same data path to the card as it would for any other 16-bit PC Card in I/O and Memory mode.5.4 Y[7::0] These signals are 8 bits of luminance data that are input to the ZV Port from the PC Card.5 Signal Description This section describes the signal definitions of ZV Port.3 HREF This signal supplies the horizontal synchronization pulse to the ZV Port that displays the video data. address lines A[25::4] to the PC Card are either put in three state by the Host Adapter or become inputs to the Host Adapter. For an MCLK frequency of 384Fs the LRCLK to SCLK ration must be 48. Supported sample frequencies are shown in section 9.6 LRCLK This signal determines which audio channel (left/right) is currently being input on the audio Serial Data input line. 9.2.5 UV[7::0] These signals are the 8 bits of chrominance data that are input to the ZV Port from the PC Card.ELECTRICAL SPECIFICATION 9. During display time. 9.4 Features In the ZV Port interface mode.9 MCLK. © 1999 PCMCIA/JEIDA 239 . LRCLK is low to indicate the left channel and high to indicate the right channel.

1920 11.4112 1. LRCLK SCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Left Channel Right Channel Figure 9-3: 1A I2S Format .5.2.2896 12.5.PC CARD CUSTOM INTERFACES 9. LRCLK (Hz) Sample Frequency 22050 32000 44100 48000 SCLK (MHz) 32xfs 0.2880 240 ©1999 PCMCIA/JEIDA . The ZV Port audio DAC should support a MCLK frequency of 256 times and 384 times the input word rate.6448 8. SDATA and SCLK. Digital audio data is transferred using the I2S format.2. I2S Format The I2S formats are shown below. This results in the frequencies shown below. MCLK is asynchronous to LRCLK. 9.0240 1.MCLK = 384fs 9.5. The MCLK must be either 256x or 384x the desired Input Word Rate (IWR).9 MCLK This signal is the Master clock for the digital audio. The following table illustrates several standard audio word rates and the required MCLK and LRCLK frequencies.8 SCLK This signal is the serial digital audio PCM clock.7 SDATA This signal is the digital PCM signal that carries the audio information.7056 1. The digital audio data is left channel-MSB justified to the high-tolow going edge of the LRCLK plus one SCLK delay. IWR is the frequency at which words for each channel are input to the DAC and is equal to the LRCLK frequency.2.5360 MCLK (MHz) 256x 5.MCLK = 256fs LRCLK SCLK SDATA Left Channel Right Channel 23 22 21 20 19 18 17 16 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 9-4: 1B I2S Format .

4320 9. DMA Signals shall not replace I/O Interface Signals on a socket when the ZV Port custom interface mode is set in the PC Card Host Adapter for that socket.9344 18.6 Memory Function.) Direct access to any address beyond the first 16 Bytes of attribute or common memory is undefined. 9.4672 12.2880 16.2.2.3040 MCLK (MHz) 384x 8.1168 2.2.) The PC Card shall support direct access to 16 Bytes (signals A[3::0]) of attribute and common memory space and provide access to two 64 Mbyte indirect memory spaces using registers in common memory. (See 4. The associated video interface timing table shows the AC parameters associated with the ZV Port signals when the ZV Port custom interface is in use.16 Indirect Access to PC Card Memory.1 Video Interface Timing The following timing diagram depicts the relationship amongst the ZV Port signals.6 Functions There are no changes to the functions of the Common Memory and Attribute Memory areas when the ZV Port custom interface mode is set in the PC Card Host Adapter.5360 2.0584 1. Even Field Odd Field VSYNC t8 t8 HREF t6 t5 t7 PCLK t1 t2 t3 t4 t6 t7 2 3 END Y[7:0] / UV[7:0] 0 1 Figure 9-5 Video Interface Timing © 1999 PCMCIA/JEIDA 241 .ELECTRICAL SPECIFICATION LRCLK (Hz) Sample Frequency 22050 32000 44100 48000 SCLK (MHz) 48xfs 1.7. (See 4.7 Timing 9.

8 Electrical Interface PC Card logic levels are unchanged when the ZV Port custom interface mode is set in the PC Card Host Adapter.9.5 ns 30 ns 10 ns 100 ns 8 ns Maximum 8 ns Note: All video signals have a minimum rise and fall time of 4 ns and a maximum rise and fall time of 8 ns.2.2 Audio Interface Timing LRCLK tslrd tslrs t sclkl tsclkh SCLK tsdlrs tsdh SDATA Figure 9-6 Audio Interface Timing Table 9-3 AC Parameters for Audio Signals SYMBOL tslrd tslrs tsclkl tsclkh tsdlrs tsdh PARAMETER LRCLK delay LRCLK setup bit clock low bit clock high data setup data hold MIN 2ns 32ns 22ns 22ns 32ns 2ns 9.) 242 ©1999 PCMCIA/JEIDA .PC CARD CUSTOM INTERFACES Table 9-2 AC Parameters for Video Signals Symbol t1 t2 t3 t4 t5 t6 t7 t8 Parameter PCLK fall time PCLK low time PCLK rise time PCLK high time PCLK cycle time Y[7::0] / UV[7::0] / HREF setup time Y[7::0] / UV[7::0] / HREF hold time VSYNC setup / hold time to HREF Minimum 4 ns 20 ns 4 ns 20 ns 62.1 Signal Interface and Table 4-18 PC Card Logic Levels. (See 4. Non-interlaced data asserts VSYNC at the Odd Field timing.7. 9.2.

3 volt signaling environment used in CardBus and ZV has twenty-three (23) signals at 16. any stub shall have a maximum length of 2 inches (50. the test conditions are different.2. In addition to testing with the forty-five (45) CardBus signals that operate at 3.) Note that a stubbed implementation allows vias between device pins and connector pins. The ZV Port interface in a CardBus PC Card capable host may be implemented using stubbed signal traces when the stubs are short avoiding transmission line effects. CardBus PC Card Connector Test Methodology. 9.8 mm).) The testing methods outlined in the appendix are the same.0 to 3.25 volts) and interactions with the forty-five (45) ZV signals. © 1999 PCMCIA/JEIDA 243 .6 volts and a frequency of 33 MHz.2.10 PC Card Connector Test Methodology This section notes changes in test methodology that should be observed when quantifying the effect of a ZV Port interface on system noise levels in a CardBus capable host. Worst case ground bounce evaluation is expanded to include the ZV Port interface active at maximum VCC (5.6 MHz and twenty-two (22) signals at 5. (See Appendix B: 8.9 Specific Signals and Functions The specific signals and functions of the ZV Port interface are discussed in the previous sections.ELECTRICAL SPECIFICATION Table 9-4 ZV Port Electrical Interface Item ZV Port Signals Signal PCLK VSYNC HREF Y[7::0] UV[7::0] LRCLK SDATA SCLK MCLK Card The card shall be able to drive a load of 50 pF at a DC current of 4 mA in the low state and 700 µA in the high state.5 MHz. The ZV Port interface also operates at 5 volts in addition to the 3. (See Figure 9-7 Host-side Test Board Layout. 9. the forty-five (45) ZV signals are added to the Host-side and Card-side test requirements. Host The host shall present a load of no more than 50 pF at a DC current of 4 mA in the low state and 700 µA in the high state.

PC CARD CUSTOM INTERFACES I/O DRIVERS I/O DRIVER DATA INPUT I/O DRIVERS INPUT BUFFER GROUND BOUNCE MEASUREMENT I/O DRIVER DATA MONITOR I/O DRIVER TRANSMIT/RECEIVE CARD 0 AND 1 GROUND BOUNCE MEASUREMENT I/O DRIVER GROUND BOUNCE CONTROL GROUND BOUNCE MEASUREMENT STACKED CARDBUS CONNECTOR SERIES RESISTOR TERMINATION – AS REQUIRED I/O DRIVERS MIXED VOLTAGE POWER SUPPLY Figure 9-7 Host-side Test Board Layout 244 ©1999 PCMCIA/JEIDA .

European TV Standardization body) compliant Conditional Access System built into a PC Card or a PC Card adapter module. © 1999 PCMCIA/JEIDA 245 . The module complements an IRD host system (Integrated Receiver Decoder) for receiving digital encoded and scrambled TV applications.3 DVB CI Port Custom Interface (0241h) The DVB CI port is a bi-directional video and audio bus and a command control interface based on the PC Card socket providing a DVB (Digital Video Broadcasting.ELECTRICAL SPECIFICATION 9. The Port complies with the specifications of EN 50221 (CENELEC) laid out for timing of the interface to allow DVB compliant decoders to daisy chain scrambled data and to deliver unscrambled real-time MPEG-2 transport data streams straight into the de-multiplexing and MPEG decoding process of the IRD.

246 ©1999 PCMCIA/JEIDA . The second interface. as shown in Figure 9-9. After error correction this multiplex is fed via a descrambler. the command interface. Note that a host can support more than one instance of this interface. are defined. In this case the MPEG-2 Transport Stream interface is daisy-chained through all DVB CI sockets. a cable system. from terrestrial transmitters or from telecommunications network.1 Overview The IRD receiver for Digital Video Broadcasting services receives a digital data multiplex. to a demultiplexer where the desired services . to recover scrambled services. The following block diagrams shows the system level concept of the DVB CI Port integrated into an IRD host environment and demonstrate how a DVB Conditional Access is operated in principal for receiving data streams.3. carries commands and data between the host and the module. Digital video data are received from a satellite transponder. The link and physical layers are defined in the Common Interface specification of EN 50221 and the higher layers are defined by MPEG.PC CARD CUSTOM INTERFACES 9. structured according to the MPEG-2 specifications. The first interface is the MPEG-2 Transport Stream. to be included on the same physical interface. Six layers are defined in the Common Interface specification for this interface.video. audio and data . RGB Out RF In Tuner Demodulator MPEG Decoder Audio Out Remote Microprocessor Verifier Demultiplexer Host Control Scrambled Transport Stream Descrambled Transport Stream Common Interface Descrambler Microprocessor Verifier Module Smart Card (Optional) Figure 9-8: Example DVB CI Port Implementation Two logical interfaces.are extracted and fed to the appropriate host decoder referred to as 'host' because of the variety of possible platforms which may perform these operations. and each command interface is a separate logical connection to the host. In the model of this process the descrambler and its associated control functionality reside on a PC Card module which communicates with the host by means of the DVB Common Interface which is defined on the PC Card physical layer as the DVB CI Port.

3. but address lines A[13::0] are available to address Attribute Memory.ELECTRICAL SPECIFICATION Host CA module 1 CA module 2 CA module n Figure 9-9: Transport Stream Interface Chaining between Modules 9.2 Compatibility The addition of support for the DVB CI Port interface does not relax any requirement associated with 16-bit PC Cards or CardBus PC Cards in either the host or the card. Access to any address beyond the first 8 kBytes of attribute or common memory is possible by indirect addressing. When either the 16-bit PC Card memory only interface or the DVB CI Port interface is active the card shall support direct access to 8 kBytes (signals A[13::0]) of attribute memory. the CE2# signal shall be ignored and interpreted by the module as always being in the ÓhighÓ state. PC Cards not using the DVB CI Port interface shall be unaffected by the presence or state of the DVB CI Port interface capability anywhere in the host. © 1999 PCMCIA/JEIDA 247 . The Audio Digital Waveform (SPKR#) and the Status Changed (STSCHG#) signals are not available when the DVB CI Port custom interface mode is active. IOIS16# is never asserted and the module ignores CE2#. However in case the host is not capable of operating with PC Cards in a non-custom interface mode the card shall be gracefully rejected by the host. PC Cards implementing the DVB CI Port interface shall present the 16-bit PC Card memory only interface following the application of VCC or the RESET signal. BVD1 and BVD2 shall remain ÓhighÓ. When operating in this configuration D[7::0] are retained as a byte-oriented I/O port. The IOIS16# signal is never asserted. and the capability to read the Attribute Memory is retained. if required. In DVB Common Interface Specification only two address lines are required for four Bytes of register space.

PC CARD CUSTOM INTERFACES 9.3 Pin Assignments The following table shows the function of various PC Card signals when the DVB CI Port custom interface mode is set in the PC Card Host Adapter.3. 248 ©1999 PCMCIA/JEIDA . "O" indicates signal is output from PC Card. Table 9-5: DVB CI Port Interface Pin Assignments PC Card Pin Number 56 55 54 53 50 49 48 47 46 19 20 14 41 40 39 38 37 66 65 64 63 62 1. I/O and Memory Interface Signal Name A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 D15 D14 D13 D12 D11 D10 D9 D8 BVD1 BVD2 I/O and Memory I/O1 I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O O O DVB CI Port Interface Signal Name MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 MDI0 MISTRT MIVAL MCLKI MCLKO MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0 MOSTRT MOVAL DVB CI Port Comments I/O1 I I I I I I I I I I I O O O O O O O O O O O MPEG Data In 7 MPEG Data In 6 MPEG Data In 5 MPEG Data In 4 MPEG Data In 3 MPEG Data In 2 MPEG Data In 1 MPEG Data In 0 MPEG Data In Start MPEG Data In Valid MPEG Data Clock Input MPEG Data Clock Output MPEG Data Out 7 MPEG Data Out 6 MPEG Data Out 5 MPEG Data Out 4 MPEG Data Out 3 MPEG Data Out 2 MPEG Data Out 1 MPEG Data Out 0 MPEG Data Out Start MPEG Data Out Valid "I" indicates signal is input to PC Card. remain unchanged from the 16-bit PC Card I/O and Memory interface. PC Card signals not mentioned in the table below.

ELECTRICAL SPECIFICATION The following diagram shows the PC Card socket and the location of the signals that carry digital video-audio I/O-signals when the PC Card and the Host Adapter are set to the DVB CI Port custom interface mode.3.4 Features In the DVB CI Port custom interface mode. © 1999 PCMCIA/JEIDA 249 . most of the host adapter control signals and data bus follow the same signal path to the card as they would for any other 16-bit PC Card in I/O and Memory mode. The primary difference is that the address signals A[25::14] and the data signals D[15::8] are used by the PC Card Host Adapter thereby restricting the Common Memory space (optional) address range to 16 kBytes and the Attribute Memory space address range to 8k valid Bytes (8 bit even access only). 1 35 2 GND GND 36 MDO3 MDO4 MDO5 MDO7 MDO6 MISTRT MCLKO MDI0 MDI1 MDI2 VCC VCC MDI3 VPP VPP MIVAL MDI4 MCLKI MDI5 MDI6 MDI7 SPKR# (MOVAL) MOSTRT MDO0 MDO1 MDO2 67 33 PCLK 34 GND 68 GND Figure 9-10: DVB CI Port Signals on PC Card Socket 9.

address lines A[25::14] to the PC Card are put in high impedance state by the Host Adapter.3.6 MOVAL This signal is active to indicate valid Bytes on MDO[7::0].4 MDO[7::0] This is the MPEG Transport data output from the module.3. 9. The Port interface has the following unique signals detailed in the sections below.5.5.2 MISTRT This signal is active to indicate the first Byte of a MPEG Transport packet on MDI[7:0].5 Signal Description This section describes the signal definitions of DVB CI Port.1 MDI[7::0] This is the MPEG data input to the module.5 MOSTRT This signal is active to indicate the first Byte of a MPEG Transport packet on MDO[7::0].5. the data lines D[15::8]. It uses the pin assigned to A15. assigned to A14. The timing relationship between MCLKI and the input signal is shown in Figure 9-11 and the timing limits are given in Table 9-6.5. 9.3. It uses pin 14. as the way the input is generated within the host means that there may be periods of non-valid data between or even within MPEG Transport packets. It clocks the MPEG Transport data into the module. It uses the pin assigned to A16. It uses the pin assigned to BVD2.5.PC CARD CUSTOM INTERFACES 9.3.3 MIVAL This signal is active to indicate valid Bytes on MDI[7:0]. The address lines A[25::14].3. BVD1/STSCHG# and BVD2/SPKR# signals are then replaced by DVB CI Port signals which carry video-audio data to and from the PC Card to the DVB CI Port.7 MCLKI This signal is a continuously running clock input to the module during the period when the interface is in this particular configuration.3. As the interface is clocked continuously.3. It utilizes the pins assigned to A[25::18]. 9. 9.5. It uses the pin assigned to A17. 9. there is a need to indicate when valid data is present. It uses the pins assigned to D[15::8].3. When the DVB CI Port custom interface mode is selected in the PC Card Host Adapter. 9.5.8 MCLKO This signal is a continuously running clock output from the module during the period when the interface is in this particular configuration. 9. The timing relationships between MCLKO and the output signal is 250 ©1999 PCMCIA/JEIDA . It clocks the MPEG Transport data out of the module. It uses the pin assigned to BVD1.5.3. 9.

) The PC Card shall support direct access to 8 kBytes (signals A[13::0]) of attribute memory space and shall support access to any address beyond the first 8 kBytes of attribute or common memory by indirect addressing. © 1999 PCMCIA/JEIDA 251 . Common Memory space support in the host is optional. and the capability to read the Attribute Memory is retained. DVB CI Modules shall use an independent I/O address window of 4 Bytes in space starting at address Ó00HÓ.).6 Functions There are no changes to the functions of the Attribute Memory areas when the DVB CI Port custom interface mode is set in the PC Card Host Adapter. Since the DVB CI Port custom interface is 8 bit only interface the Attribute Memory Bytes are at consecutive even addresses (0. There are changes to the functions of the I/O accesses. 9. When operating in this configuration D[7::0] are retained as a byte-oriented I/O port.4.3.6 Memory Function.3. etc. (See 4. 9.ELECTRICAL SPECIFICATION shown in Figure 9-11 and the timing limits are given in Table 9-6.2. DMA Signals shall not replace I/O Interface Signals on a socket when the DVB CI Port custom interface mode is set in the PC Card Host Adapter for that socket.7 Timing Transport Stream Interface Timing The following timing diagram depicts the relationship for Transport Stream Interface signals Table 9-6 shows the AC parameters associated with the DVB CI Port signals when the DVB CI Port custom interface is in use. MCLKO may be a delayed copy of MCLKI but it could also be an entirely different clock signal with no relationship with MCLKI.

MVAL MOVAL Figure 9-11: Transport Data Stream Interface Timing Table 9-6: Timing Relationship Limits SYMBOL tclkp tclkh tclkl tsu th tosu toh PARAMETER Clock period Clock High time Clock Low time Input Data Setup Input Data Hold Output Data Setup Output Data Hold MIN 111 ns 40 ns 40 ns 15 ns 10 ns 20 ns 15 ns 252 ©1999 PCMCIA/JEIDA . MISTRT MVAL MIVAL tclkp tclkh MCLKO tclkl tosu toh MDO MOSTRT. MISTRT. MDI. MDO.PC CARD CUSTOM INTERFACES tclkp tclkh MCLKI th tclkl tsu MDI [7::0]. [7::0]. MOSTRT.

9. (See 4.3. Further specifications addressing the operation and functions of a Conditional Access System and the Command Interface hosted on the PC Card Module are laid down in the Standard of EN 50221.8 Electrical Interface PC Card logic levels are according to the specifications when the DVB CI Port custom interface mode is set in the PC Card Host Adapter.9 Specific Signals and Functions The specific signals of the DVB CI Port interface are addressed in the previous sections.3.ELECTRICAL SPECIFICATION 9.) 9. © 1999 PCMCIA/JEIDA 253 .1 Signal Interface and Table 4-18 PC Card Logic Levels.

P C C A R D S TA N D A R D Volume 3 Physical Specification .

recording or otherwise. Suite 209 San Jose. Printed in the United States of America.Ó Document No. WITH RESPECT TO THE STANDARD. registered in Japan. PCMCIA HAS BEEN NOTIFIED BY CERTAIN THIRD PARTIES THAT THE IMPLEMENTATION OF THE STANDARD WILL REQUIRE A LICENSE FROM THOSE THIRD PARTIES TO AVOID INFRINGEMENT OF THEIR RIGHTS. electronic. MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. INCLUDING AS TO NONINFRINGEMENT. February 1999 . THIS STANDARD IS PROVIDED TO YOU ÒAS IS. in any form or by any means. CA 95134 USA +1-408-433-2273 +1-408-433-9558 (Fax) JEIDA (Japan Electronic Industry Development Association) Kikai Shinko Kaikan. without prior written permission of PCMCIA and JEIDA. PCMCIA (Personal Computer Memory Card International Association) 2635 North First Street. BUT NOT ALL. EXPRESS OR IMPLIED. 3-5-8.PCMCIA JEIDA ©1999. CONTINGENT UPON YOUR ENTERING INTO AND DELIVERING TO PCMCIA THE RECIPROCAL GRANT OF IMMUNITY AGREEMENT CONTAINED ELSEWHERE IN THIS STANDARD. Shibakoen Minato-ku. mechanical. The PC Card logo and design are trademarks of JEIDA. JAPAN +81-3-3433-1923 +81-3-3433-6350 (Fax) The PC Card logo and PC Card are trademarks of PCMCIA. No part of this publication may be reproduced. CA 95134 USA NEITHER PCMCIA NOR JEIDA MAKES ANY WARRANTY. IMPORTANT: In order to receive the Grant of Immunity. stored in a retrieval system. the owner of this Standard must sign and return the enclosed Registration Card to: PCMCIA 2635 North First Street. or transmitted. registered in the United States. 0299-03-2000 First Printing. PCMCIA HAS OBTAINED FROM SOME. Suite 209 San Jose. PCMCIA/JEIDA All rights reserved. photocopying. OF THOSE PARTIES A GRANT OF IMMUNITY THAT PCMCIA WILL EXTEND TO YOU. Tokyo 105.

...........................................................................1 Office Environment..................6 Single Pin Holding Force ...................................................................2..............1..................................................................1.......................................................................1 6 7............................11 6..................2 Electrical Performance..................1 6 7.............2 Harsh Environment .....................................................................1 2 7.................................................1...................................................1......................1 3 7...........5 Insulation Material.........................1 6 © 1999 PCMCIA/JEIDA iii ................................3 Total Insertion Force ...........................1......2.........1 2 6..........2...................................................PHYSICAL SPECIFICATION CONTENTS 1....................................................1 4 7..................1 Mechanical Performance.........................1..................7 4...............................1.......................1 Card Connector.............................................................1 4 7.1 Contact Resistance (low level) .......2 Battery Location ....................................1 Write Protect Switch (WPS) ....................................................................................................................................1..... Related Documents _____________________________________3 3...................1 4 7............................................................................................................. Introduction____________________________________________1 2...............2 Withstanding Voltage .............................................................................1.......... Connector Reliability __________________________________13 7................................................. Grounding/EMI Clips __________________________________11 6...................................5 4.........................1.....4 Total Pulling Force......................................................................1 5 7................4 Current Capacity.....13 7..........................................7 Single Socket Holding Force....10 Pin Connector Inverse Insertion ......................... Connector______________________________________________7 4..........................2.....................................................................................................................5 3.......................................2 Host Connector....................................1 3 7.....................................................................................................................................2 Harsh Environment ........3 Material Compatibility...........................................................................................2......... PC Card Guidance ______________________________________9 6.......................................................................................8 Vibration and High Frequency.............................................................................................6 Ground Return Inductance..............................................................................................................................3 Insulation Resistance................1.......1..............7 5.......................1...............................................................................................................................9 Shock ..................................................................5 3....1 3 7.....................2.................................1 5 7..............................................................1 Office Environment........................................3 Labeling (Marking) ......................................................................1 2 6................................................................................................................................................................................................................................................................1 5 7...........................................1 5 7................................ Card Dimensions _______________________________________5 3.......15 7...................................................1 Card/Ground Clip Contact Resistance Measurement Procedure ......................1 5 7.....................................................................................................................................................................................1 4 7....5 Single Pin Pulling Force....................................................................1 3 7..........................................................................................................................................................................................................................

......................................................................2 Harsh Environment..........2 5 9..........................................4 Cold Resistance .........................................3.........18 Small PC Card Torque Test...2 7 9......3...........3 Environmental Performance ..15 Small PC Card Bend Test.......................13 Shock.............3 Environmental Resistance...................................18 8................................1 Operating Environment ..........................8 X-ray Exposure......3.......................................7 Electrostatic Discharge ..................................3 Durability (High Temperature).......................1 Card Warpage...........................4.......2 2 9.................................................................................3...................2 3 9................................................................................1 7 7......2 4 9................................................ PC Card Environmental________________________________ 21 9..........................................10 Electromagnetic Field Interference..................4..............3..............................................................3....2 2 9.....................................................................................................................................................................................................................................................19................................................3..........................................................................1 6 7...................................................................................................5 Approved Test Procedures .............................................2 7 iv © 1999 PCMCIA/JEIDA ...3..............2...................................................................19 PC Card Warpage ........................................................................3..............6 Moisture Resistance...........3......2 5 9.............................4........................................................................................................................19 8........................................................................3.....................6 Hydrogen Sulfide .......................................................................................................................................2 1 9..............16 7.........................................................................................................................................................................2 Method of Measuring Warpage..........................................1 7 7....................................................................................3.......................................................................................................................3.................3.......................2 Storage Environment .................................................................................3..................................................4......3..............................................4......................................................................................1 High Storage Temperature.....................................................................................................2 Storage Environment ..................4 Environmental Resistance.........................2 6 9...............................................................................................1 Reference Standards ................CONTENTS 7......................................................16 Drop Test...................................................3............................11 Card Inverse Insertion..............................................................................................................................2 2 9..........................1 7 7..................................................................................................................................................................2 2 9.........................................................3..............................................2 3 9......2 Environmental Performance ....................................................2 6 9.........................................................4..............................................................2......................................................................................1 7 7.............................21 9...........................................................................22 9.......................................12 Vibration and High Frequency ...........2 4 9.............1 Moisture Resistance.2 6 9..............................................................................................................................2 Thermal Shock..............................................................................................................................................................19 9..........................................................................................2 5 9.............................2 Low Storage Temperature .................................................................................................................................................4 Low Operating Temperature..................3 High Operating Temperature....................3........................................................................................................................................................1 6 7..........................................................................3......2 5 9..14 Full-size PC Card Bend Test ..........................................................................2 6 9......................1 Office Environment...............................................5 Humidity (Normal Condition).................5 Thermal Shock..................................................................................................................................1 7 7...........2 3 9...........................................................................................................3..................................9 Ultraviolet Light Exposure....................................2 7 9...........................................................1 7 7....................17 Full-size PC Card Torque Test ........................2 4 9............................................................................................................2 4 9....19.............1 Operating Environment ..........................................3...................21 9............. Connector Durability __________________________________ 19 8.17 7..............................................................3................................................

.......................3 Recommended Value of Warpage Dimensions .....29 10...........................................................2 8 9...3.......................... Temperature Rise..........2........... PC Card Thermal Rating ______________________________31 10.............................................1 Thermal Rating vs....................................................2 Procedure .....................................................................................................1..........3 1 10.................................................................................1 Determination Using a Temperature Rise Method........20 SRAM Data Retention ......................................19...............3 5 11..........31 10...............................1 Measuring the PC Card Temperature......................................................................................3 1 10......PHYSICAL SPECIFICATION 9........................................................1....................................2 8 9...... Figures ______________________________________________37 © 1999 PCMCIA/JEIDA v .............................................................1...............................3.........4 Approved Test Procedures ...

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....................................................................41 Figure 11-5: Small PC Card Type I Package Dimensions.....................40 Figure 11-4: Type III PC Card Package Dimensions ........................58 Figure 11-26: Electrostatic Discharge Test-1 Fixture ...............58 Figure 11-27: Electromechanical Discharge Test-2 Fixture ................................................................................53 Figure 11-19: Recommended Right Angle Connector PCB Footprint............42 Figure 11-6: Small PC Card Type II Package Dimensions ..............................35 Figure 11-1: Grounding/EMI Clips Contact Resistance Measurement.........................................................................................................................................................5 Each Side........................................................... Pin Contacts............................37 Figure 11-2: TYPE I PC Card Package Dimensions.....................50 Figure 11-16: Small PC Card Pin Connector ...................................................................................................................................................................56 Figure 11-24: Small PC Card Guide Guidance.............................49 Figure 11-15: Full-size PC Card Pin Connector.....................................55 Figure 11-23: Full-size PC Card Guide Guidance ................52 Figure 11-18: Small PC Card Host Connector............................................................................46 Figure 11-10: Type III PC Card (3D).......................................................................................38 Figure 11-3: TYPE II PC Card Package Dimensions....................................................................48 Figure 11-12: Small PC Card Connector Socket ........................ Temperature Rise................................................................................33 Figure 10-5: Thermal Rating vs............................5 Each Side .........................................................................................................................................................................................57 Figure 11-25: Connector Shock & Vibration Test Fixture..............................................55 Figure 11-22: Recommended One Row Surface Mount Connector PCB Footprint ..................................................................32 Figure 10-2: Free Area Around Card Being Rated .....................................51 Figure 11-17: Full-size PC Card Host Connector..45 Figure 11-9: Type II PC Card (3D)............................................................58 © 1999 PCMCIA/JEIDA vii .... Pin Contacts....................33 Figure 10-4: Location of Thermocouples for Small PC Card .....................................PHYSICAL SPECIFICATION FIGURES Figure 10-1: PC Card Thermal Environment Measurement Method...................................................................................43 Figure 11-7: Small PC Card Type III Package Dimensions..................48 Figure 11-13: Full-size PC Card Pin/Socket Contact Length with Wipe..............................46 Figure 11-11: Full-size PC Card Connector Socket ........32 Figure 10-3: Location of Thermocouples ..............................44 Figure 11-8: Type I PC Card (3D) .................................49 Figure 11-14: Small PC Card Pin/Socket Contact Length with Wipe..................................................................................................................54 Figure 11-21: Recommended Two Row Surface Mount Connector PCB Footprint ..........................54 Figure 11-20: Recommended Straight Connector PCB Footprint ..................

.................72 viii © 1999 PCMCIA/JEIDA ...........66 Figure 11-41: CardBus PC Card Recommended PCB Footprint.....................................................68 Figure 11-43: CardBus PC Card Recommended Right Angle PCB Footprint.........65 Figure 11-39: Card Inverse Insertion Push Block ............................................................64 Figure 11-38: Card Inverse Insertion Test Fixture...................67 Figure 11-42: CardBus PC Card Recommended Host Connector Grounding Interface Dimensions ..........60 Figure 11-31: Full-size PC Card Torque Test Fixture .......................................................................................................................................................................68 Figure 11-44: CardBus PC Card Recommended Right Angle PCB Footprint (Stacked) ...................................................................................................60 Figure 11-30: Small PC Card Bend Test Fixture ..........................................69 Figure 11-45: CardBus PC Card Reference Shrouded Connector.71 Figure 11-47: Contact Resistance Measurement..................................................................................65 Figure 11-40: CardBus PC Card Recommended Connector Grounding Interface Dimensions........................59 Figure 11-29: Full-size PC Card Bend Test Fixture.................................................................63 Figure 11-36: Warpage Measurement BÐMeasurements ..............................................................................70 Figure 11-46: CardBus PC Card Reference Shrouded Connector (Stacked Connector).................................62 Figure 11-35: Warpage Measurement BÐThickness Measurements ..................................................63 Figure 11-37: Warpage Measurement BÐMeasurement Positions ........................................................61 Figure 11-32: Small PC Card Torque Test Fixture..........62 Figure 11-34: Warpage Measurement AÐSubstrate Area...............................................................................................................FIGURES Figure 11-28: PC Card Shock and Vibration Test Fixture...................................................61 Figure 11-33: Warpage Measurement AÐInterconnect Area........................................................

......................................PHYSICAL SPECIFICATION TABLES Table 4-1: Host Connector Pin Configuration ..7 © 1999 PCMCIA/JEIDA ix .........................................

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including Small PC Card. and CardBus PC Card applications. I N T R OD U C T ION This section of the specification defines the PC CardÕs physical outline dimensions.PHYSICAL SPECIFICATION 1. and PC Card Environmental Sections are the minimum parameters which must be met. Connector Durability. Note that these tests apply to all PC Cards. Small PC Card. The tests specified in the Connector Reliability Section. connector system and qualification test parameters for 5 volt. Each manufacturer is responsible for qualification of their own products to this specification. The CardBus PC Card interface requires the use of a grounded shroud CardBus PC Card connector or PCMCIA/JEIDA approved equivalent for all CardBus PC Card applications. unless a different test is specified for a specific card. © 1999 PCMCIA/JEIDA 1 . low voltage.

INTRODUCTION 2 © 1999 PCMCIA/JEIDA .

S. 1990. November. Military Standard. PC Card ATA Specification Volume 9. Department of Defense ANSI/UL 94-1979. Standard for Tests for Flammability of Plastic Materials for Parts in Devices and Appliances.S. U. Overview and Glossary Volume 2. R E L AT E D D O C U M E N T S The following documents which comprise the PC Card Standard: PC Card Standard Release 7. Electronic Industries Association © 1999 PCMCIA/JEIDA 3 . Military Standard. Department of Defense MIL-STD-1344A. XIP Specification Volume 10. PCMCIA/JEIDA Volume 1. Physical Specification Volume 4. Test Methods for Electronic and Electrical Component Parts. Media Storage Formats Specification Volume 8. 1979 EIA-364-B. Electrical Specification Volume 3. Guidelines Volume 11. Socket Services Specification Volume 7. Card Services Specification Volume 6. U. PC Card Host Systems Specification MIL-STD-202F.PHYSICAL SPECIFICATION 2 . Metaformat Specification Volume 5. Test Methods for Electrical Connectors. August.0 (February 1999). Electrical/Socket Test Procedures Including Environmental Classifications.

RELATED DOCUMENTS 4 © 1999 PCMCIA/JEIDA .

Type II. Figure 11-5. Type II. and Type III full-size PC Cards are shown in Figure 11-2: TYPE I PC Card Package Dimensions. Figure 11-6. The battery holder. 3. If a WPS is used. Figure 11-6: Small PC Card Type II Package Dimensions. Type II. Figure 11-5. shall not cause the PC Card to exceed the thickness specified in Figure 11-2. U N L E S S O T H E R WIS E S P E C IF IE D . 3.3 Labeling (Marking) The thickness of labeling. as shown in Figure 11-2. must withstand all environmental test specified the PC Card Environmental Section. and three types of Small PC Cards: also Type I. Connector location and pin numbers for Type I. if used. Type II. Figure 11-3. Figure 11-3. and Type III. and Figure 11-4: Type III PC Card Package Dimensions. CAR D DIME N S ION S There are six types of PC Cards in this specification. © 1999 PCMCIA/JEIDA 5 . it is recommended that it pass all requirements. shall be located at the locations shown in Figure 11-2. Three types of full-size PC Cards: Type I. Figure 11-3. shall be designed so that the positive (+) side of the battery faces Surface A. Figure 11-6. Figure 11-3. D IME N S IO N S S H O WN D O N O T IN C L U D E WA R P A G E A L L O WA N C E S .2 Battery Location The battery. Figure 11-5 and Figure 11-6. The PC Card logo may be displayed by member company manufacturers as authorized.PHYSICAL SPECIFICATION 3 .1 Write Protect Switch (WPS) The WPS. and Figure 11-7: Small PC Card Type III Package Dimensions. and Figure 11-6 or on the bottom cover. A L L D IME N S IO N S A R E IN MIL L IME T E R S (MM). Figure 11-4. and Type III Small PC Cards are shown in Figure 11-5: Small PC Card Type I Package Dimensions. if installed. and shall be indicated by an arrow and the words ÒWrite ProtectÓ or ÒProtectÓ or ÒWPÓ. 3. shall be located at the locations shown in Figure 11-2. if installed. Connector location and pin numbers for Type I. or on both the end and bottom cover. The label. PC Card polarization technique and dimensions are also shown in Figure 11-2. if used. or Figure 11-7. and Figure 11-7 for Small PC Cards. and Figure 11-4 for full-size PC Cards. Figure 11-3: TYPE II PC Card Package Dimensions. as applicable. The write-protected position of the WPS shall be the far-right position. Figure 11-3. if installed. and in Figure 11-5. The arrow and indication may be on the end of the PC Card. Figure 11-5 and Figure 11-6. PC Cards must be opaque (non see-through). It is also recommended the WPS perform as specified for a minimum of 100 (Write Protect/Write Enable) cycles. in PC Card Environmental. and Type III.

CARD DIMENSIONS 6 © 1999 PCMCIA/JEIDA .

34. The socket contacts shall be within the PC Card connector. keying. and number in Table 4-1: Host Connector Pin Configuration. electrically conductive. 2-piece pin-and-socket.00 Pin Number 36. 35. The Small PC Card host pin connector shall be a 68-pin connector with opening. Table 4-1: Host Connector Pin Configuration Pin Type Detect General Power/Ground Pin Length (L) ±.1 Card Connector The socket contacts are located on the full-size PC Card as shown in Figure 11-2: TYPE I PC Card Package Dimensions. and the host-pin lengths are shown in Figure 11-13: Full-size PC Card Pin/Socket Contact Length with Wipe and Figure 11-17 and pin type. ground plate (Figure 11-40: CardBus PC Card Recommended Connector Grounding Interface Dimensions) with eight (8) raised dimples 0.0.50 4. Pin Contacts. Figure 11-9: Type II PC Card (3D). Figure 11-6: Small PC Card Type II Package Dimensions. polarization. The CardBus PC Card connector (or PCMCIA/JEIDA approved equivalent) shall contain a top side planar. The PC Card connector socket shall be configured as shown in Figure 11-11: Full-size PC Card Connector Socket or Figure 11-12: Small PC Card Connector Socket. This ground plate is connected to the PC Card electrical system ground (Figure 11-41: CardBus PC Card Recommended PCB Footprint). The PC Card connector socket layout shall match the host pin-connector layout as shown in Figure 11-15: Full-size PC Card Pin Connector or Figure 11-16: Small PC Card Pin Connector.5 mm in height.10 mm 3. The host connector-pin configuration is shown in Figure 11-18: Small PC Card Host Connector. length. keying. and pin location as shown in Figure 11-16: Small PC Card Pin Connector. polarization. Figure 11-4: Type III PC Card Package Dimensions. length. and shall meet Electrostatic Discharge requirements as specified in the Electrostatic Discharge Section. Figure 11-8: Type I PC Card (3D). CON N E C T OR The specified PC Card interconnect system shall be a 68-position. 4. 51. and Figure 11-10: Type III PC Card (3D). 17.PHYSICAL SPECIFICATION 4. and pin type. and pin location as shown in Figure 11-15: Full-size PC Card Pin Connector. Figure 11-3: TYPE II PC Card Package Dimensions. 4. and number in Table 4-1: Host Connector Pin Configuration. 68 © 1999 PCMCIA/JEIDA 7 . and the host-pin lengths are shown in Figure 11-14: Small PC Card Pin/Socket Contact Length with Wipe and Figure 11-18.25 5. and Figure 11-7: Small PC Card Type III Package Dimensions. Pin Contacts. must be isolated from chassis ground. 67 All Other Pins 1.2 Host Connector The full-size PC Card host pin connector shall be a 68-pin connector with opening. The host connector-pin configuration is shown in Figure 11-17: Full-size PC Card Host Connector. The socket contacts for Small PC Card are located on the Small PC Card as shown in Figure 11-5: Small PC Card Type I Package Dimensions.

The recommended host connector PCB footprints for: the right angle connector (Figure 11-19: Recommended Right Angle Connector PCB Footprint). If a connector ejector mechanism is used. it is recommended the ejector mechanism pass all requirements for reliability and durability. 8 © 1999 PCMCIA/JEIDA . as applicable.6 mm when mating with the CardBus PC Card Connector (Figure 11-45: CardBus PC Card Reference Shrouded Connector and Figure 11-46: CardBus PC Card Reference Shrouded Connector (Stacked Connector)). The interconnect system shall pass all requirements of the Connector Reliability Section and the Connector Durability Section. and one row surface mount connector (Figure 11-22: Recommended One Row Surface Mount Connector PCB Footprint) are shown without mounting or hardware hole locations. two row surface mount connector (Figure 11-21: Recommended Two Row Surface Mount Connector PCB Footprint).254 mm minimum air gap when mating with 16-bit PC Cards.CONNECTOR The outermost plating of socket and pin contact area shall be gold or other plated materials compatible with gold and shall meet the requirements specified in the Connector Reliability and Connector Durability Sections. The host connector ground shroud is connected to host system electrical ground signals and must be isolated from chassis ground. The host pin connector for CardBus PC Card applications (or PCMCIA/JEIDA approved equivalent) shall contain a top side planar electrically conductive. ground shroud (Figure 11-42: CardBus PC Card Recommended Host Connector Grounding Interface Dimensions) with eight (8) fingers having an effective minimum contact wipe length of 3. the straight connector (Figure 11-20: Recommended Straight Connector PCB Footprint). These eight (8) fingers shall be recessed within the host pin connector protective dielectric shroud providing a 0. in Section 7 Connector Reliability and Section 8 Connector Durability. The recommended CardBus PC Card host connector PCB footprints for the right angle connector (Figure 11-43: CardBus PC Card Recommended Right Angle PCB Footprint and Figure 11-44: CardBus PC Card Recommended Right Angle PCB Footprint (Stacked)) is shown with mounting hole locations.

0 mm before engagement. © 1999 PCMCIA/JEIDA 9 . the guide shall be designed with G2 as large as possible and W2 as small as possible. and the Small PC Card shall be guided for a minimum distance of 27. the full-size PC Card shall be guided for a minimum distance of 40.PHYSICAL SPECIFICATION 5 . NOTE Figure 11-24 is a reference for the design of the guide. To ensure alignment of the Small PC Card to the connectors.0 mm before the socket connector bottoms on the host (pin) connector (see Figure 11-23: Full-size PC Card Guide Guidance or Figure 11-24: Small PC Card Guide Guidance). PC CAR D G U ID AN C E The PC Card shall be guided by the host connector for a minimum distance of 10.0 mm before engagement. To ensure alignment of the PC Card to connectors.

PC CARD GUIDANCE 10 © 1999 PCMCIA/JEIDA .

instead of out the card into the surrounding area. and Figure 11-7: Small PC Card Type III Package Dimensions. Material(s) selected for the mating surfaces of the grounding clips must be compatible to prevent corrosion resulting from galvanic action.1. to a level that is no longer suitable for the application.1 Office Environment Record the contact resistance of the ground clip interface then subject the card to life cycle testing (10. Figure 11-5: Small PC Card Type I Package Dimensions. test procedure 23 with the following test conditions: a) open circuit voltage equals 20 mV. S E E P CM CI A GRA NT OF I M M U NI T Y A ND S U B L I CE NS E F OR E M I GROU ND CL I P S U B -L I CE NS E A GRE E M E NT . RJ11 cable) through an I/O connector will not act like an antenna. 6.1 Card/Ground Clip Contact Resistance Measurement Procedure The contact resistance between a PC Card ground clip and the host socket chassis attachment point shall not degrade after life cycle testing (in both the harsh and office environments) by more than 20 mW from its initial resistance measurement. The process of attaching the clip to the frame. The interface must not wear. With the clips. The location of the grounding/EMI clip on different types of PC Cards is detailed in Figure 11-2: TYPE I PC Card Package Dimensions. the cardÕs emissions are directed back through the card and into the system to either the Battery or AC input. cover or card PWB is left to the card designer. The ground clip to host contact resistance shall be measured © 1999 PCMCIA/JEIDA 11 .000 insertion/extraction cycles). The recommendation is for the material. Figure 11-9: Type II PC Card (3D). Figure 11-8: Type I PC Card (3D). Figure 11-4: Type III PC Card Package Dimensions. Figure 11-3: TYPE II PC Card Package Dimensions. OR CONT A CT P CM CI A OF F I CE F OR A DDI T I ONA L I NF ORM A T I ON. The clips create a path of least resistance to ground so that the external connection (e. Refer to Figure 11-1: Grounding/EMI Clips Contact Resistance Measurement for lead connection. 6. Figure 11-10: Type III PC Card (3D). Grounding/EMI clips can be included on memory cards as well if needed.g. The resistance of the PC Card ground clip to host interface shall be measured in accordance with EIA 364-B. The base alloy material(s) and mating surfaces for the grounding clip(s) in host systems and on the mating surface(s) on the card must be compatible with gold. after life cycle testing. dimensions and location of the grounding/EMI clip. Figure 11-6: Small PC Card Type II Package Dimensions.PHYSICAL SPECIFICATION 6. G R OU N D IN G/ EM I CL IP S PC Card manufacturers may use frame mounted grounding/EMI Clips to reduce the Electromagnetic Emissions of PC Cards. b) test current equals 100 mA maximum.

GROUNDING/EMI CLIPS using the same procedure outlined above. 6. present a contact interface that is no longer suitable for the application. after the life cycle testing.2 Harsh Environment Record the contact resistance of the ground clip interface then subject the card to the harsh environment test specification.1. The material specification for the ground clip in the host and the mating surface on the card must be compatible with gold. A suitable mating interface is one that has a contact potential difference of 0. The contact interface is acceptable if the resistance has increased by no more than 20 mW from the initial value.1. 6. The ground clip to host contact resistance shall be measured using the contact resistance measurement procedure.3 Material Compatibility The material selected for the mating surfaces of the ground clip must be compatible to prevent corrosion due to galvanic action. The contact interface is acceptable if the resistance has increased by no more than 20 mW from the initial value.3 Vdc or less. 12 © 1999 PCMCIA/JEIDA . The interface must not wear to a point where the metal contacts.

Unless otherwise specified.1. all test and measurements shall be made at: Temperature Air pressure Relative humidity 15°C to 35°C 86 to 106 kPa 25% to 85% If conditions must be closely controlled in order to obtain reproducible results.5 Approved Test Procedures for approved test procedures.3 Total Insertion Force STANDARD 39.67 N minimum and 39. the parameters shall be: Temperature Air pressure Relative humidity 23°C ± 1°C 86 to 106 kPa 50% ± 2% See Section 7. 7.000 minimum TESTING See Harsh Environment Section.1 7. 7.1 Mechanical Performance The interconnect system mechanical performance is specified in the following sections.PHYSICAL SPECIFICATION 7 .1. CON N E C T OR RE L IAB IL IT Y The interconnect system as specified in the Connector Section shall meet or exceed all reliability test requirements of this subsection.1.2 N maximum TESTING Insert at speed of 25 mm/minute 7.1. EIA 364-B Class 1.4 Total Pulling Force STANDARD 6.2 Harsh Environment STANDARD Guaranteed number of insertions/ejections = 5.2 N maximum TESTING Extract at speed of 25 mm/minute © 1999 PCMCIA/JEIDA 13 . EIA 364-B Class 1.000 minimum TESTING See Office Environment Section.1 Office Environment STANDARD Guaranteed number of insertions/ejections =10.3 7.

1.8 N minimum force is applied to the pin TESTING Push pin on the axis at speed of 25 mm/minute with 9.6 Single Pin Holding Force STANDARD Pin shall not push out of the insulator when 9.Tool making steel Hardness . See Figure 11-25: Connector Shock & Vibration Test Fixture 14 © 1999 PCMCIA/JEIDA .2 TESTING Pull the gauge pin shown to left at speed of 25 mm/minute Gauge pinÕs surface must be wiped clean of dirt and lubrication oil 0.098 N minimum initial value 0.7 Single Socket Holding Force STANDARD Socket shall not be dislodged or damaged when 4. Insulator 9.CONNECTOR RELIABILITY 7.9 N minimum force is applied to the socket TESTING Push socket on the axis with 4.350 ±0. Must not cause current interruption greater than 100 ns TESTING 147 m/s_ (15G) peak amplitude.420 ±0. 10 Hz to 2000 Hz.005 mm DIAMETER (FULL-SIZE PC CARD) 0.8 N Min Force PIN 7.8 Vibration and High Frequency STANDARD a.1.1. 12 cycles per axis.HRC = 50 to 55 7. 3 axis.9 N minimum force at a speed of 25 mm/minute while holding insulator rigid INSULATOR 4. 20 minute sweep.005 mm DIAMETER (SMALL PC CARD) Gauge: Material .9 N Min Force SOCKET 7. No mechanical damage shall occur on the parts b.5 Single Pin Pulling Force STANDARD 0.8 N minimum force while holding insulator rigid.1.

See Figure 1147: Contact Resistance Measurement Ri £ 40 mW b.2 Electrical Performance The interconnect system electrical performance is specified as follows. No mechanical damage shall occur on the parts b. Current leakage 1 mA maximum 7. Resistance value after test: Rf = Ri ± 20 mW 7. Initially 40 mW maximum b.3 Insulation Resistance STANDARD a. Semi-sine wave Velocity change 3.8 N or more Travel after contact to key of pin connector: 5 mm or less Since this requirement is for a single pin connector. After test 20 mW maximum change TESTING Open voltage 20 mV Test current 1 mA a.2 Withstanding Voltage STANDARD a.44 m/s (11. TESTING Maximum insertion force: 58.2. inverse insertion test method in Section 9.3 ft/s) See Figure 11-25: Connector Shock & Vibration Test Fixture 7. 7. 7. After test 100 MW minimum TESTING Measure within 1 minute after applying 500V DC © 1999 PCMCIA/JEIDA 15 . Measure and record resistance after test (Rf) of the connector system.1. Initially 1000 MW minimum b.3.2.2.10 Pin Connector Inverse Insertion STANDARD Measurements shall be made by putting aside a gauge card to a guide portion of two different pin connectors and right side measurement at another. Measure and record the initial resistance (Ri) of the separate connector contact interface. No shorting or other damages when 500 Vrms AC is applied for 1 minute b.11 Card Inverse Insertion is applied to test the performance at actual use.9 Shock STANDARD a.PHYSICAL SPECIFICATION 7. Must not cause current interruption greater than 100 ns TESTING Acceleration 490 m/s_ (50G) Standard holding time 11 ms.1 Contact Resistance (low level) STANDARD a.1.

3 Environmental Performance 7.2.3.0 nH maximum Inductance @ 1 MHz applies to both single and stacked configurations 7.3.5 Insulation Material STANDARD Flame retardant material will not burn nor support combustion 7.5 A per contact TESTING Based upon 30°C rise above ambient temperature 7. TESTING Low level inductance STANDARD 18.1 Operating Environment STANDARD Operating Temperature: -20°C to +60°C Relative humidity: 95% maximum (non-condensing) 7.6 Ground Return Inductance Note: This requirement applies to CardBus PC Card applications.CONNECTOR RELIABILITY 7.2.2 Storage Environment STANDARD Storage Temperature: -40°C to +70°C Relative humidity: 95% maximum (non-condensing) 16 © 1999 PCMCIA/JEIDA .2.4 Current Capacity STANDARD 0.

Part b TESTING 3 PPM hydrogen sulfide 40°C. Part b TESTING 85°C. approx.1 Moisture Resistance STANDARD Per Contact Resistance (low level) Section.4 Environmental Resistance 7. Part b TESTING -55°C to +85°C 5 minute transition time (max) 5 cycles (1 cycle = 1 hour) with connectors engaged 7. 80% RH 96 hours.4.4 Cold Resistance STANDARD Per Contact Resistance (low level) Section. Part b TESTING Temperature Cycling (excluding vibration).4.2 Thermal Shock STANDARD No physical damage shall occur during testing Per Contact Resistance (low level) Section. 250 hours with connectors engaged Exclude load and insulation resistance measurements 7. Part b TESTING Steady State40°C. 90 to 95% RH 96 hours with connectors engaged 7. 10 cycles (1 cycle = 24 hours) with connectors engaged 7.4.4. Part b TESTING -55°C. 96 hours with connectors engaged 7.3 Durability (High Temperature) STANDARD Per Contact Resistance (low level) Section. with connectors engaged © 1999 PCMCIA/JEIDA 17 .5 Humidity (Normal Condition) STANDARD Per Contact Resistance (low level) Section.6 Hydrogen Sulfide STANDARD Per Contact Resistance (low level) Section. Part b Per Insulation Resistance Section.4.4.PHYSICAL SPECIFICATION 7. Part b Per Insulation Resistance Section. Part b Per Insulation Resistance Section.

1 202.1.3 7.2. Method 106 202. Method 3002.5 7. Method 108 364-69 364-31 364-32 364-17 364-59 364-31 6-11d 5-9b 6-11j 6-11c JEIDA 382 JISC 00201 Mil Std 202.4 7.5 7.4.1 7.4.2.2 7. Method 301 202. Method 204 202. Test Vibration and High Frequency Shock Contact Resistance (low level) Withstanding Voltage Insulation Resistance Insulation Material Ground Return Inductance Moisture Resistance Thermal Shock Durability (High Temperature) Cold Resistance Humidity (Normal Condition) Hydrogen Sulfide JIS = Japanese Industrial Standard JEIDA = Japanese Electronic Industry Development Association 202. Method 103 202.3 7.CONNECTOR RELIABILITY 7.4.4.2 7.6 1.2.4. Method 213 1344.2. Method 107 202.4.5 Approved Test Procedures Section 7.9 7.2.6 7.1.1 7.8 7. 2. Method 302 EIA TP 364-28 364-27 364-23 364-20 364-21 IEC 512 4-6d 4-6c 2-2a 2-4a 2-3a UL 94V-0 Other 18 © 1999 PCMCIA/JEIDA .

2 Harsh Environment The harsh environment is defined in EIA-364-B Class 1.3Ñno air conditioning.PHYSICAL SPECIFICATION 8 . Part a Mate and unmate the connector for a total of 10. Part b Note: Connector durability utilizing Moisture Resistance in lieu of Humidity is acceptable.1 .1 Office Environment The office environment is defined in EIA-364-B Class 1. Test conditions for the mate/unmate cycles are: Cycle Rate Temperature Relative Humidity Air Pressure 400-600 cycles per hour 15°C to 35°C 25% to 85% 86 to 106 kPa 8. CON N E C T OR DU R AB IL IT Y The interconnect system as specified in Connector Section shall meet or exceed all durability requirements of this subsection.year round air conditioning (non-filtered) with humidity control.000 cycles Humidity per Humidity (Normal Condition) Section Mate and unmate the connector 3.000 © 1999 PCMCIA/JEIDA 19 . Part a Mate and unmate the connector 1. Test Sequence: Contact resistance per Contact Resistance (low level) Section.000 cycles Contact resistance per Contact Resistance (low level) Section. Part b 8.000 cycles Humidity per Humidity (Normal Condition) Section Hydrogen sulfide per Hydrogen Sulfide Section Contact resistance per Contact Resistance (low level) Section. no humidity control with normal heating and ventilation: Contact resistance per Contact Resistance (low level) Section.000 cycles Humidity per Humidity (Normal Condition) Section Mate and unmate the connector 1.000 TOTAL CYCLES = 2.000 TOTAL CYCLES = 1. TOTAL CYCLES = 5.

CONNECTOR DURABILITY 20 © 1999 PCMCIA/JEIDA .

Scratches. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here. 9.1 Operating Environment Ambient temperature 0°C to 55°C Relative humidity 95% maximum (non condensing) SRAM data retention per Section 9. Form: The form and dimensions. 2.3. Note: Evaluation standards are limited and evaluations are to be within the reliability of the connectors. if the connectors are used in the test.PHYSICAL SPECIFICATION 9 . for which tests specific to Small PC Card have been developed: · · Bend Test Torque Test The battery. Electrical performance: Electrical performance must conform to these requirements after testing. 9.1 Reference Standards 1. P C CAR D E N V IR ON M E N TAL The PC Card as specified in this Standard shall meet or exceed all environmental tests of the Environmental Resistance Section.20 SRAM Data Retention © 1999 PCMCIA/JEIDA 21 . must conform to the physical use requirements after testing. if part of the PC Card. including warpage.2. all test and measurements shall be made at: Temperature Air Pressure Relative Humidity 15°C to 35°C 86 to 106 kPa 25% to 85% If conditions must be closely controlled in order to obtain reproducible results. shall be installed for all tests. Unless otherwise specified. The storage and operating environment test parameters are specified in Environmental Resistance Section. 9.2 Environmental Performance The PC Card storage and operating environment are specified in this subsection. the parameters shall be: Temperature Air Pressure Relative Humidity 23°C ± 1°C 86 to 106 kPa 50% ± 2% See Section 9.4 Approved Test Procedures for approved test procedures. The Small PC Card shall meet or exceed all of the same environmental tests in the Environmental Resistance Section with the exception of the following tests.

including warpage.20 SRAM Data Retention The form and dimensions.2 Low Storage Temperature STANDARD PC Card to function as specified after test and all non. including warpage.3. 9.20 SRAM Data Retention 9. must conform to the physical use requirements of these specifications after testing Scratches.volatile memory to retain the data stored prior to test Data retention of SRAM and other battery powered solid state memory per section 9.2.3.20 SRAM Data Retention The form and dimensions. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Test Condition 65°C and 90-95% RH for 96 hours minimum.3 High Operating Temperature STANDARD PC Card to function as specified after test and all non-volatile memory to retain the data stored prior to test The form and dimensions. must conform to the physical use requirements of these specifications after testing Scratches.1 High Storage Temperature STANDARD PC Card to function as specified after test and all non-volatile memory to retain the data stored prior to test Data retention of SRAM and other battery powered solid state memory per section 9. including warpage. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Test Condition -20°C for 96 hours minimum.3 Environmental Resistance The PC Card shall be tested per the Environmental Resistance specifications listed below.3. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Test Condition 55°C for 96 hours minimum Vcc = manufacturer specified 22 © 1999 PCMCIA/JEIDA .PC CARD ENVIRONMENTAL 9.3.3.2 Storage Environment Storage temperature -20°C to 65°C Relative humidity 95% maximum (non condensing) SRAM data retention per Section 9. Vcc = 0 9.3. The manufacturer shall ensure adequate testing in order to ensure the PC Card conforms to this specification. Vcc = 0 9. must conform to the physical use requirements of these specifications after testing Scratches.

3.20 SRAM Data Retention TESTING TEST 1 2 3 4 TEMP (°C) -20 25 65 25 TIME 30 <05 30 <05 The form and dimensions. The form and dimensions. including warpage. including warpage. must conform to the physical use requirements of these specifications after testing Scratches. Minimum temperature 0 °C Steps 7a and 7b deleted from Method 106E MIL-STD 202. must conform to the physical use requirements of these specifications after testing Scratches.6 Moisture Resistance STANDARD PC Card to function as specified after test and all non-volatile memory to retain the data stored prior to test The form and dimensions. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Maximum Temperature 55 °C. color and other appearance shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here Repeat for 100 cycles Vcc = 0 Card Connector disengaged Time in minutes.4 Low Operating Temperature STANDARD PC Card to function as specified after test and all non-volatile memory to retain the data stored prior to test. including warpage. 9. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Test Condition 0°C for 96 hours minimum Vcc = manufacturer specified 9. must conform to the physical use requirements of these specifications after testing Scratches.3. © 1999 PCMCIA/JEIDA 23 .volatile memory to retain the data stored prior to test Data retention of SRAM and other battery powered solid state memory per section 9.PHYSICAL SPECIFICATION 9. Repeat test for 10 cycles (excluding vibration) Vcc = manufacturer specified.3. Card connector disengaged.5 Thermal Shock STANDARD PC Card to function as specified after test and all non.3.

3.10 Electromagnetic Field Interference STANDARD PC Card to function as specified after test and all non.volatile memory to retain the data stored prior to test TESTING Wavelength 254 nm Intensity 15000 mW/cm2 Exposure time 20 minutes 9. the magnetic field is 100 Oersted Exposure time 10 seconds 24 © 1999 PCMCIA/JEIDA .8 X-ray Exposure STANDARD PC Card to function as specified after test and all non-volatile memory to retain the data stored prior to test TESTING 140 kV @ 5 mA Intensity 0.7 Electrostatic Discharge STANDARD PC Card to function as specified after test 1 and 2 and all nonvolatile memory to retain the data stored prior to test TEST 1 and TEST 2 should not be done as a series test TESTING TEST 1: Discharge two (2) times on Surface A Repeat test on Surface B Total discharge cycles = 4 (See Figure 11-26: Electrostatic Discharge Test-1 Fixture) TEST 2: Discharge total twelve (12) times each side as indicated in Figure 11-27: Electromechanical Discharge Test-2 Fixture Turn PC Card over and repeat test Total discharge cycles = 24 9.volatile memory to retain the data stored prior to test TESTING Place PC Card in uniform magnetic field of 1.3.1Gy minimum or 10 Roentgen minimum for 1 hour minimum 9.000 Oersted Exposure time 10 seconds For rotating media cards.PC CARD ENVIRONMENTAL 9.3.3.9 Ultraviolet Light Exposure STANDARD PC Card to function as specified after test and all non.

Apply 19.11 Card Inverse Insertion STANDARD No electrical contact between the card and connector during the test except for Vcc and GND pins Note: Host connector has pin (male) contacts. Apply 19.3. velocity change: 3.13 Shock STANDARD PC Card to function as specified after test and to retain the data stored prior to test TESTING Acceleration 490 m/s2 (50G) Duration 11ms Semi-sine wave.6 N to the unclamped end using the force bar as shown in Figure 11-29: Fullsize PC Card Bend Test Fixture. TESTING Provide a grooved metal block as shown in Figure 1138: Card Inverse Insertion Test Fixture and fix it to a load tester Align the center of host connector and pushing block as shown in Figure 11-39: Card Inverse Insertion Push Block Manually insert a sample card into the pin connector until the front end of card key slightly touches it Press the pushing block in the X direction at a speed of 25 mm/minute until the pushing load reaches 58.3.6 N to the unclamped end using the force bar as shown in Figure 11-29: Fullsize PC Card Bend Test Fixture.3 ft/s) (Figure 11-28: PC Card Shock and Vibration Test Fixture) 9. Time ³ 1 minute Test 2: Clamp the non-connector end of the PC Card with surface A facing upward.000 Hz.3.44 m/s (11. 20 minute sweep.14 Full-size PC Card Bend Test STANDARD PC Card to function as specified after test and to retain the data stored prior to test The dimensions must conform to the use requirements of these specifications after testing Scratches. Time ³ 1 minute Test 3 and 4: Repeat test 1 and 2 with surface B facing upward Total test must include all four procedures © 1999 PCMCIA/JEIDA 25 . 12 cycles per axis. 36 cycles for 3 axes (12 hr) Vcc = 0 With battery installed (Figure 11-28: PC Card Shock and Vibration Test Fixture) 9.3. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Test 1: Clamp the connector end of the PC Card with surface A facing upward.12 Vibration and High Frequency STANDARD PC Card to function as specified after test and all to retain the data stored prior to test TESTING 147 m/s2 (15G) peak amplitude 10 to 2.PHYSICAL SPECIFICATION 9.8 N Hold the status for 1 minute Repeat the above test 5 times Temperature: room temperature (15°CÐ35°C) 9.

3.3.15 Small PC Card Bend Test STANDARD PC Card to function as specified after test and to retain the data stored prior to test The dimensions must conform to the use requirements of these specifications after testing Scratches.236 N-m maximum and/or angle = 10° maximum.3. Time >= 1 minute Test 2: Clamp the non-connector end of the Small PC Card with surface A facing upward. Apply 19.PC CARD ENVIRONMENTAL 9.18 Small PC Card Torque Test STANDARD PC Card to function as specified after test and to retain the data stored prior to test The dimensions must conform to the use requirements of these specifications after testing Scratches.16 Drop Test STANDARD PC Card to function as specified after test and to retain the data stored prior to test The PC Card must conform to the use requirements of these specifications after testing Scratches. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Drop PC Card two(2) times in three(3) mutually exclusive axes from a height of 75 cm onto a noncushioning. 9. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Test 1: Clamp the connector end of the Small PC Card with surface A facing upward.17 Full-size PC Card Torque Test STANDARD PC Card to function as specified after test and to retain the data stored prior to test The dimensions must conform to the use requirements of these specifications after testing Scratches. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING ISO 7816-1 Apply clockwise torque to the unsupported end of the Small PC Card (torque = 1.236 N-m maximum or angle = 10° maximum. whichever occurs first) Time = 5 minutes Repeat test applying counter-clockwise torque Repeat test five (5) times in each direction See Figure 11-32: Small PC Card Torque Test Fixture. whichever occurs first) Time = 5 minutes Repeat test applying counter-clockwise torque Repeat test five (5) times in each direction See Figure 11-31: Full-size PC Card Torque Test Fixture 9. Total test must include all four procedures. vinyl-tile surface For rotating media cards: Drop PC Card (in a protective pouch) two(2) times in three (3) mutually exclusive axes from a height of 75 cm onto a non-cushioning vinyl-tile surface Drop PC Card (in a protective pouch) two(2) times in three (3) mutually exclusive axes from a height of 75 cm onto a 0. color and other appearance items shall depend on the specifications of the manufacturer for each card and are not a basis for evaluation here TESTING Apply clockwise torque to the unsupported end of the PC Card (torque = 1.635 cm nap industrial carpeted surface 9. Time >= 1 minute Test 3 and Test 4: Repeat test 1 and 2 with surface B facing upward. 26 © 1999 PCMCIA/JEIDA . Apply 19.6N to the unclamped end using the force bar as shown in Figure 11-30.3.6N to the unclamped end using the force bar as shown in Figure 11-30: Small PC Card Bend Test Fixture.

and slide the card or the measuring instrument to measure the height.3. b) Measuring substrate area warpage Place a parallel plate against the entire substrate area. Figure 11-35: Warpage Measurement BÐThickness Measurements. (2) Warpage Measurement Method B Measure the interconnect areaÕs thickness T(i) and substrate areaÕs thickness T(s) within the ranges shown.3. It is recommended that warpage dimensions be controlled as follows at the time of manufacturer shipment. 9. © 1999 PCMCIA/JEIDA 27 . (1) Warpage Measurement Method A a) Measuring warpage at interconnect area Place a parallel plate against the interconnect area. Figure 11-36: Warpage Measurement BÐMeasurements.3. See Figure 11-34: Warpage Measurement AÐSubstrate Area. micrometer or other measuring instrument which can measure the height from the horizontal plane. a) Measuring warpage at interconnect area Read the maximum value T(MAX) measuring after sliding. This is the control value. avoid using a large load that would damage the card. See Figure 11-36: Warpage Measurement BÐMeasurements.PHYSICAL SPECIFICATION 9. Figure 11-34: Warpage Measurement AÐSubstrate Area. This applies only to Type I and Type II PC Cards. Warpage dimension = T(MAX)-T(i). and Figure 11-37: Warpage Measurement BÐMeasurement Positions 9. Measure the thickness of the card (T) including warpage.1 Card Warpage Card warpage dimensions are an important element in assuring that the connector engages. See Figure 11-33: Warpage Measurement AÐInterconnect Area. Next.19 PC Card Warpage STANDARD PC Card to function as specified after test and retain the data stored prior to the test The dimensions must conform to the use requirements of these specification after testing TESTING Measure the PC Card (Type I or II) interconnect and substrate thicknesses Then place the PC Card (Type I or II) on a flat plate and measure the maximum warpage Figure 11-33: Warpage Measurement AÐInterconnect Area.2 Method of Measuring Warpage Measurement methods A and B are prescribed for measuring warpage.19. use a dial gauge. See Figure 11-35: Warpage Measurement BÐThickness Measurements. When measuring warpage.19. The interconnect area warpage measurement is the maximum open space dimension (W) measured by a projector.

See Figure 11-36: Warpage Measurement BÐMeasurements.15 mm maximum 0. Warpage dimension equals T(MAX)-T(s).20 SRAM Data Retention STANDARD SRAM PC Card to retain all data after each test (1 and 2) TESTING Test 1: Test condition 55°C for 24 hours minimum Vcc = 0 Test 2: Test condition 0°C for 24 hours minimum Vcc = 0 28 © 1999 PCMCIA/JEIDA . Recommended positions for warpage measurement are indicated in Figure 11-37: Warpage Measurement BÐMeasurement Positions.PC CARD ENVIRONMENTAL b) Measuring substrate area warpage Read the maximum value T(MAX) measured after sliding.3.80 mm maximum 5. and measure at least 3 locations.3 Recommended Value of Warpage Dimensions (1) Interconnect area: Width (short side) Length (long side) 0.19. 9.3.50 mm maximum 0.35 mm maximum To be defined b) For warpage measurement method B Type I: Type II: Type III: 0. in the center and at both sides.35 mm maximum (2) Substrate area (card thickness including warpage): a) For warpage measurement method A: Type I: Type II: Type III: 3.50 mm maximum To be defined 9. slide in the longside direction. When measuring.

Method 106 202.3.7 9.3.3.3.3. Method 204 202.3.3.10 9.PHYSICAL SPECIFICATION 9.13 9.9 9. Method 213 364-28 364-27 4-6d 4-6c ISO 7816-1 202.3.17 1.4 Approved Test Procedures Section 9.1 9.12 9.3. Method 103 EIA TP 364-31 364-59 364-17 364-59 364-32 364-31 ISO 7816-1 ISO 7816-1 ISO 7816-1 ISO 7816-1 IEC 512 6-11c 6-11j 5-9b 6-11j 6-11d JIS C 00201 JIS C 00201 Other © 1999 PCMCIA/JEIDA 29 .3.3.3 9. Method 108 Mil Std 202. Test High Storage Temperature Low Storage Temperature High Operating Temperature Low Operating Temperature Thermal Shock Moisture Resistance Electrostatic Discharge X-ray Exposure Ultraviolet Light Exposure Electromagnetic Field Interference Vibration and High Frequency Shock Full-size PC Card Torque Test JIS = Japanese Industrial Standard 202.4 9. Method 107 202.5 9.3.2 9.6 9.8 9.3.

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1 Measuring the PC Card Temperature It is important when measuring the PC Card temperature to ensure that only heat generated within the PC Card physical space is determined.1 Determination Using a Temperature Rise Method Like the host system. This temperature rise is then converted to the PC CardÕs thermal rating. will yield acceptable results. P C C A R D T H E R M A L R AT I N G 10. In a balanced system. The card shall be in a free air environment on both sides. the PC Card must also have a thermal rating. The PC Card shall be free of external influences for a quartersphere of 304. The following is a low cost optional method to determine the thermal rating derived from the temperature gradient produced by the operating card.4 . Place five thermocouples or similar temperature measuring devices on each side of the PC Card as indicated by the template in Figure 10-3: Location of Thermocouples . Any heat generated by external input must be accounted for. the heat energy above 65¡C generated by the PC Card is removed by the host system thus maintaining the PC Card at a temperature at or below 65¡C. This method shall be made in a draft free environment under the following conditions: Temperature Air Pressure Relative Humidity 24¡C ± 1¡C 86 to 106 kPa 50% ± 10% Note that alternative methods.5 Each Side or Figure 10-4: Location of Thermocouples for Small PC Card .2 Procedure The PC Card shall be removed from the host test system using a card type specific extender (PC Card 16 or CardBus PC Card type extender) and any external heat loads produced by the PC Card in order to isolate external influence of the measurement as in Figure 10-1: PC Card Thermal Environment Measurement Method. if performed correctly.1.8 millimeters and 25. 10.1. © 1999 PCMCIA/JEIDA 31 . such as an electrical summation of all power dissipated within the PC Card.38. Any heat generated external to the PC Card envelope must not influence the PC Card temperature measurement.5 Each Side.1 millimeters above a dielectric (non-conductive) table surface as indicated in Figure 10-2: Free Area Around Card Being Rated.PHYSICAL SPECIFICATION 1 0 . 10.

38.4 .8 mm End of Card Connector Card Centerline 304.5 Each Side Figure 10-1: PC Card Thermal Environment Measurement Method 304. See Figure 10-3: Location of Thermocouples .1 mm Top/Bottom view of card Figure 10-2: Free Area Around Card Being Rated 32 © 1999 PCMCIA/JEIDA .8 mm Edge view of card End view of card Dielectric Table Surface 25.PC CARD THERMAL RATING Thermocouples 1 To Thermal Measuring Device PC Card Thermal Environment External Dongle (or other external load) 1.

When the temperature of the PC CardÕs surface is stable within ± 1¡C over thirty minutes.7 38.18 21. © 1999 PCMCIA/JEIDA 33 .64 PC Card Card Host Connector Edge Note: All Notes: All dimensions dimensions in millimeters Tolerance = ± 2.16 Card Host Connector Edge Note: All dimensions in millimeters Tolerance = ±1.5 43.54 mm in millimeters Tolerance = +/.4 12.PHYSICAL SPECIFICATION 63.5 Each Side 38. a program must be run in order to realistically exercise the card at its extremes.4 SmallPC Card Figure 10-4: Location of Thermocouples for Small PC Card .7 10.5 Each Side From a host system.59 12.2. the card has reached its thermal rating.1 40.54mm Figure 10-3: Location of Thermocouples .27 mm 32.1 25.64 21.

The copper tape's optical properties do not match. This is the value that is recorded in the PC CardÕs CIS thermal entry (see TPCE_MI: Miscellaneous Features Field in the Metaformat Specification).05DT1. Type T) Hot Spot TC Welder (welded thermocouples) Fluke Hydra Data Acquisition Unit (2620A Module) 3M Copper Electrical Tape.PC CARD THERMAL RATING Determine the average temperature rise from the total number of thermocouples or similar temperature measuring devices. 25.1E-7DT4. we achieved very good agreement between the IR image and the thermocouple readouts. 34 © 1999 PCMCIA/JEIDA . The copper tape provides a good stiff bond of the wire to the card and it provides a good thermal interface of the card to the wire. Temperature Rise. 12. Obtain the PC CardÕs Thermal Rating by using the averaged temperature rise and Figure 10-5: Thermal Rating vs. Below is the list of items used to determine this Thermal Rating curve and equation: · · · · T30-2-506 Thermocouple Wire (30 Gauge. When married to the drafting tape as an overlay.26 + 1. H813441E181R. The Thermal Rating is characterized by the equation Thermal Rating (X.Y) = 0. because it is a conductor and not a dielectric.7 mm 3M 230 Drafting Tape Used to match the IR emissivities of the card surface to the thermocouple wire mounting area.4 mm. This implies minimal test-induced error.

05 D T + 1. D T (TFINAL .PHYSICAL SPECIFICATION 10.1.Y) = 0. Temperature Rise © 1999 PCMCIA/JEIDA 36 48 4 0 35 .2.1E D T 8 7 6 Thermal Rating 5 4 3 2 1 20 24 28 0 8 40 44 12 16 32 o Temperature Rise.T AMB). C Figure 10-5: Thermal Rating vs. Temperature Rise 1.26 -7 4 Thermal Rating (X.1 Thermal Rating vs.

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FIGU R E S V POWER SUPPLY A GROUND CLIP HOST SOCKET CHASSIS ATTACHMENT POINT Figure 11-1: Grounding/EMI Clips Contact Resistance Measurement © 1999 PCMCIA/JEIDA 37 .PHYSICAL SPECIFICATION 11.

60 P MIN 3 10.0 T 6 1.60 H ± 0.20 85.05 2.05 mm OVER DIMPLES (REFER TO Figure 11-40: CardBus PC Card Recommended Connector Grounding Interface Dimensions) INTERCONNECT AREA TOLERANCE = ± 0.10 0.10 mm 2 3 4 5 6 Figure 11-2: TYPE I PC Card Package Dimensions 38 © 1999 PCMCIA/JEIDA PROTECT 5 2x H L 2x G SUBSTRATE AREA 3 P INTERCONNECT AREA CONNECTOR W 2x R 4 2x T 6 X #1 X 5 volt key #68 Surface B #35 #68 Surface B #35 4 S MIN 3.60 .10 G ± 0.60 1 RECOMMENDED BATTERY LOCATION.60 Z ± 0.65 W ± 0.05 1.60 79.00 X ± 0.05 mm SUBSTRATE AREA TOLERANCE = ± 0. THE BATTERY HOLDER SHOULD BE DESIGNED SO THAT THE POSITIVE SIDE OF THE BATTERY IS UP (TOWARD SURFACE A) THE PC CARD SHALL BE OPAQUE (NON SEE THRU) POLARIZATION KEY LENGTH DIMENSION R CORNER RADIUS GROUND CLIP LOCATION FOR CARDBUS PC CARDS DIMENSION T IS INCREASED BY 0.05 1.00 Y ± 0.60 65.FIGURES WPS 1 BATTERY Surface A C 2x S X #34 Surface A Y X #34 Surface A X #1 Z low voltage key Y C MIN 10.10 54.0 L ± 0.0 R ± 0.50 ± 0.

0 R ± 0.0 T1 ± 0.05 mm OVER DIMPLES (REFER TO Figure 11-40: CardBus PC Card Recommended Connector Grounding Interface Dimensions) 2 3 4 5 6 Figure 11-3: TYPE II PC Card Package Dimensions © 1999 PCMCIA/JEIDA PROTECT SUBSTRATE AREA 3 P INTERCONNECT AREA CONNECTOR W 2x R 4 2x T1 6 2x T2 Surface A X #1 X 5 volt key #68 Surface B #35 Surface A #68 Surface B #35 S MIN 3.10 G ± 0.05 1.60 4 1 RECOMMENDED BATTERY LOCATION.60 H ± 0.00 X ± 0.60 39 .60 P MIN 3 10.05 1.60 Z ± 0.PHYSICAL SPECIFICATION WPS 1 BATTERY Surface A 5 2x H L 2x G C 2x S X #34 Y X #34 X #1 Z low voltage key Y C MIN 10.05 1.60 79.20 85.50 W ± 0.65 6 T2 MAX 2.60 65.0 L ± 0.50 ± 0. THE BATTERY HOLDER SHOULD BE DESIGNED SO THAT THE POSITIVE SIDE OF THE BATTERY IS UP (TOWARD SURFACE A) THE PC CARD SHALL BE OPAQUE (NON SEE THRU) POLARIZATION KEY LENGTH DIMENSION R CORNER RADIUS GROUND CLIP LOCATION FOR CARDBUS PC CARDS DIMENSION T1 IS INCREASED BY 0.10 0.05 2.10 54.00 Y ± 0.

60 1 2 THE PC CARD SHALL BE OPAQUE (NON SEE THRU) POLARIZATION KEY LENGTH DIMENSION R CORNER RADIUS GROUND CLIP LOCATION FOR CARDBUS PC CARDS DIMENSION T1 IS INCREASED BY 0.65 Y ± 0.0 P MIN 2 10.60 79.00 R ± 0.20 85.60 T4 REF 10.50 Z ± 0.05 1.50 ± 0.05 1.00 L ± 0.10 T3 MAX 8.FIGURES Surface A 4 2x H L 2x G SUBSTRATE AREA 2 INTERCONNECT AREA P 2x C CONNECTOR 2x S X W1 W2 Surface A X 2x R 3 2x T1 5 T2 #34 #1 T3 T4 Y #68 Surface B #35 X 5 volt key X W2 Surface A X #34 #1 T3 T4 low voltage key Y #68 Surface B #35 Z C MIN 10.10 54.10 3 0.50 G ± 0.0 W1 ± 0.60 W2 MAX 51.60 H ± 0.05 2.60 65.05 1.00 T1 ± 0.05 mm OVER DIMPLES (REFER TO Figure 11-40: CardBus PC Card Recommended Connector Grounding Interface Dimensions) 3 4 5 Figure 11-4: Type III PC Card Package Dimensions 40 © 1999 PCMCIA/JEIDA .60 5 T2 MAX 2.0 X ± 0.50 S MIN 1.

80 41 .00 Y ± 0.60 S MIN 3.2 45.00 P MIN 10.05 mm TOLERANCE OF OTHER AREA = ± 0. THE BATTERY HOLDER SHOULD BE DESIGNED SO THAT THE POSITIVE SIDE OF THE BATTERY IS UP (TOWARD SURFACE A) THE PC CARD SHALL BE OPAQUE (NON SEE THRU) POLARIZATION KEY LENGTH GROUND CLIP LOCATION INTERCONNECT AREA TOLERANCE = ± 0.05 mm SUBSTRATE AREA TOLERANCE = ± 0.10 mm 2 3 4 5 6 Figure 11-5: Small PC Card Type I Package Dimensions © 1999 PCMCIA/JEIDA BATTERY Surface A 4 1 H ± 0.0 T 5 1.40 P 2x G SUBSTRATE AREA G ± 0.PHYSICAL SPECIFICATION WPS PROTECT L 3 C INTERCONNECT AREA 2x S CONNECTOR W 2x R 2x T 5 Surface A #34 Y #1 Y 5 volt key #68 X Surface B #35 X Surface A #34 Z #1 Y low voltage key #68 X Surface B #35 X C MIN 10.05 1.55 Z ± 0.00 2x H 1 RECOMMENDED BATTERY LOCATION.65 W 6 X ± 0.0 L ± 0.0 R ± 0.10/-0.05 1.00 42.60 39.10 mm TOLERANCE OF ENGAGEMENT AREA C = +0.60 25.05 2.10 0.

20 45.65 T2 MAX 2.60 S MIN 3.55 P Z ± 0.00 P MIN 10.00 H ± 0.60 39.40 2x G SUBSTRATE AREA 2x H 1 RECOMMENDED BATTERY LOCATION.0 L ± 0.80 © 1999 PCMCIA/JEIDA .05 1.0 R ± 0.50 W 5 X ± 0.10 0.FIGURES WPS PROTECT L 3 C INTERCONNECT AREA 2x S CONNECTOR W 2x R 2x T1 Surface A #34 Y #1 Y 5 volt key 2x T2 X #68 Surface B #35 X Surface A #34 Z #1 Y low voltage key #68 X Surface B #35 X C MIN 10.05 1.00 Y ± 0.10/-0.05 1.60 25.05 mm TOLERANCE OF OTHER AREA = ± 0.10 mm 2 3 4 5 Figure 11-6: Small PC Card Type II Package Dimensions 42 BATTERY Surface A 4 1 G ± 0. THE BATTERY HOLDER SHOULD BE DESIGNED SO THAT THE POSITIVE SIDE OF THE BATTERY IS UP(TOWARD SURFACE A) THE PC CARD SHALL BE OPAQUE(NON SEE THRU) POLARIZATION KEY LENGTH GROUND CLIP LOCATION TOLERANCE OF ENGAGEMENT AREA C = +0.0 T1 ± 0.05 2.00 42.

50 T3 MAX 8.0 G ± 0.05 1.10 0.65 H ± 0.60 25.50 1 2 3 4 THE PC CARD SHALL BE OPAQUE(NON SEE THRU) POLARIZATION KEY LENGTH GROUND CLIP LOCATION TOLERANCE OF ENGAGEMENT AREA C = +0.05 1.00 X ± 0.60 Z ± 0.00 P 2x G SUBSTRATE AREA T4 REF 10.00 T2 MAX 2.0 Y ± 0.20 45.05 1.80 L ± 0.10 mm Figure 11-7: Small PC Card Type III Package Dimensions © 1999 PCMCIA/JEIDA 2x H 43 .PHYSICAL SPECIFICATION T4 T3 Surface A 3 L 2 C INTERCONNECT AREA 2x S CONNECTOR W Surface A 2x R T1 T2 #34 Y #1 5 volt key Y X #68 Surface B Surface A #35 X #34 Z #1 Y low voltage key #68 X Surface B #35 X C MIN 10.00 T1 ± 0.40 S MIN 3.0 W 4 42.00 P MIN 10.05 mm TOLERANCE OF OTHER AREA = ± 0.60 39.10/-0.55 R ± 0.05 2.

FIGURES C N O N C E R TO C P D R A C BA TT ER Y PR B A TT E R Y BA TT OT EC T G R O U N D W P S Figure 11-8: Type I PC Card (3D) C LI P C O N N E C TO R C P D R A C ER Y PR B A TT E R Y OT EC T G R O U N D W P S Figure 11-9: Type II PC Card (3D) C P LI 44 © 1999 PCMCIA/JEIDA .

PHYSICAL SPECIFICATION E N N O C R TO C Figure 11-10: Type III PC Card (3D) C P D R A G R O U N D C LI P C © 1999 PCMCIA/JEIDA 45 .

FIGURES Figure 11-11: Full-size PC Card Connector Socket Figure 11-12: Small PC Card Connector Socket      .      .85 MIN PIN INSERTION 46 © 1999 PCMCIA/JEIDA . 0.94 MIN PIN INSERTION 0.

1 POWER GENERAL DETECT 5.15/-0.10 L3 (+0.1 POWER GENERAL DETECT 5.50 ~ 2.50 ~ 2.50 0.50 Figure 11-14: Small PC Card Pin/Socket Contact Length with Wipe © 1999 PCMCIA/JEIDA 47 .75 3.50 ~ 2.50 ~ 2.50 L1 MAX 0.50 L2 REF 4.50 0.50 0.50 ~ 2.50 ~ 2.10 0.PHYSICAL SPECIFICATION L 1 L3 L1 L2 L4 2 SOCKET CONTACT PIN 1 2 PIN/SOCKET CONTACT AREA L4 IS THE POINT OF FIRST ENGAGEMENT FOR MATING WITH THE SOCKET CONTACTS/HOUSING MOUNTED WITHIN THE CARD L ± 0.50 0.25 3.50 3.50 0.60 3.50 0.40 0.40 0.50 L2 REF 4.10) 0.50 0.50 0.50 L4 0.00 4.50 L1 MAX 0.50 0.50 Figure 11-13: Full-size PC Card Pin/Socket Contact Length with Wipe L 1 L3 L1 L2 L4 2 SOCKET CONTACT PIN 1 2 PIN/SOCKET CONTACT AREA L4 IS THE POINT OF FIRST ENGAGEMENT FOR MATING WITH THE SOCKET CONTACTS/HOUSING MOUNTED WITHIN THE CARD L ± 0.00 L3 ± 0.40 L4 0.25 3.50 0.85 3.00 4.

05 0.10 1.20 Y ± 0.27 T ± 0.30 Figure 11-15: Full-size PC Card Pin Connector 48 © 1999 PCMCIA/JEIDA .05 1.05 2.40 Z ± 0.68 PINS T W #1 #34 #68 Y 5 volt key #35 X T L2 T W #1 FRONT VIEW Y #34 #68 low voltage key #35 Z T L2 FRONT VIEW L1 ± 0.50 X ± 0.20 P ± 0.90 W ± 0.08 54.FIGURES 33 EQ SP = L1 P P PIN LAYOUT 2 ROW .15 41.05 1.91 L2 ± 0.08 3.

10 1.75 Y ± 0.50 X ± 0.60 Figure 11-16: Small PC Card Pin Connector © 1999 PCMCIA/JEIDA 49 .90 W ± 0.10 1.68 PINS T W #1 T #34 #68 X 5 volt key X #35 L2 FRONT VIEW T W #1 #34 #68 T Y low voltage key #35 X L2 FRONT VIEW L1 ± 0.PHYSICAL SPECIFICATION 33 EQ SP = L1 P1 P2 P3 P4 PIN LAYOUT 2 ROW .00 P3 ± 0.27 P2 ± 0.00 P1 ± 0.15 33.05 2.10 0.08 43.10 1.05 1.05 0.00 L2 ± 0.50 T ± 0.07 3.00 P4 ± 0.

110˚ MIN (CONTACT AREA) 0.5 MAX 0.46 MAX PIN-CONNECTOR PIN CROSS-SECTION FORM AND DIMENSIONS PIN-CONNECTOR PIN-TIP FORM AND DIMENSIONS Figure 11-17: Full-size PC Card Host Connector. Pin Contacts 50 © 1999 PCMCIA/JEIDA .10 10˚ .02 (PIN DIAMETER) 0.5 MIN 2.FIGURES PIN LENGTH L PIN LENGTH L 0.5 MIN PLATING AREA MATED CONTACT ENGAGEMENT AREA: THE SOCKET-CONNECTOR PIN CONTACT POSITION MUST BE WITHIN THE SHADED AREA WHEN THE PIN AND SOCKET CONNECTORS ARE FULLY MATED.50 ± 0. THE EFFECTIVE CONTACT AREA (SHADED AREA) IS SHOWN ABOVE.44 ± 0. MINIMUM PLATING AREA: FOR THE PIN CONNECTOR.15˚ RADIUS INCLUDED 0.

THE EFFECTIVE CONTACT AREA (SHADED AREA) IS SHOWN ABOVE.15 -0.37 ± 0.5 MAX 0.25 MAX 0.40 +0. (1) 110˚ MIN (CONTACT AREA) 0.5 MIN 2.10 0.PHYSICAL SPECIFICATION PIN LENGTH L PIN LENGTH L 0.15˚ RADIUS INCLUDED (2) 0.02 (PIN DIAMETER) 0.15 -0.5 MIN PLATING AREA MATED CONTACT ENGAGEMENT AREA: THE SOCKET-CONNECTOR PIN CONTACT POSITION MUST BE WITHIN THE SHADED AREA WHEN THE PIN AND SOCKET CONNECTORS ARE FULLY MATED. MINIMUM PLATING AREA: FOR THE PIN CONNECTOR.40 +0.39 MAX PIN-CONNECTOR PIN CROSS-SECTION FORM AND DIMENSIONS PIN-CONNECTOR PIN-TIP FORM AND DIMENSIONS ((1) or (2)) Figure 11-18: Small PC Card Host Connector.10 10˚ . Pin Contacts © 1999 PCMCIA/JEIDA 51 .

08 41.72 Figure 11-19: Recommended Right Angle Connector PCB Footprint #33 #1 #2 W2 #35 #36 #67 L2 L1 #68 3x W1 #34 L1 ± 0.08 41.91 L2 ± 0.91 L2 ± 0.72 Figure 11-20: Recommended Straight Connector PCB Footprint 52 © 1999 PCMCIA/JEIDA .05 1.91 W2 REF 5.27 W1 ± 0.05 1.FIGURES INSERT CARD #36 #68 #67 W2 #34 #33 #2 L2 L1 #1 3x W1 #35 L1 ± 0.05 1.05 1.91 W2 REF 5.27 W1 ± 0.

PHYSICAL SPECIFICATION INSERT CARD #68 #35 #34 L2 TYP 2x L1 L3 #1 L1 ± 0.10 41.635 L2 ± 0.050 0.545 Figure 11-22: Recommended One Row Surface Mount Connector PCB Footprint © 1999 PCMCIA/JEIDA 53 .27 L3 REF 0.080 42.64 Figure 11-21: Recommended Two Row Surface Mount Connector PCB Footprint INSERT CARD #34 #68 #35 #1 L1 TYP L2 (L1 X 67) L1 ± 0.91 L2 ± 0.05 1.

0 G3 ± 0.10 W1 ± 0.4 55.6 1 THE PC CARD SHOULD BE GUIDED FOR A MINIMUM DISTANCE OF 40.0 mm BEFORE ENGAGEMENT 3 THE CONNECTOR POLARIZATION KEYS ARE DEFINED IN Figure 11-15: Full-size PC Card Pin Connector Figure 11-23: Full-size PC Card Guide Guidance 54 © 1999 PCMCIA/JEIDA .FIGURES     .08 54.0 mm 2 THE CONNECTOR SHALL GUIDE THE PC CARD FOR A MINIMUM DISTANCE OF 5.20 W2 ± 1..0 G2 MIN 40.     1 W2 G2 POLARIZATION KEYS 1 2 G3 3 G1 P 2 W1 G1 MIN 10.70 P MAX 5.30 9.

0 mm 2 THE CONNECTOR SHALL GUIDE THE SMALL PC CARD FOR A MINIMUM DISTANCE OF 5.6 1 THE SMALL PC CARD SHOULD BE GUIDED FOR A MINIMUM DISTANCE OF 27.    1 W2 POLARIZATION KEYS G2 PHYSICAL SPECIFICATION 1 2 G3 3 G1 P 2 W1 G1 MIN 10..0 G3 ± 0.0 mm BEFORE ENGAGEMENT THE CONNECTOR POLARIZATION KEYS ARE DEFINED IN Figure 11-16: Small PC Card Pin Connector 3 Figure 11-24: Small PC Card Guide Guidance © 1999 PCMCIA/JEIDA 55 .70 P MAX 5.10 W1 ± 0.00 W2 ± 0..08 43.0 G2 MIN 27.6 43.3 9.

Figure 11-27: Electromechanical Discharge Test-2 Fixture 56 © 1999 PCMCIA/JEIDA .   FIGURES 0.295 N MIN PC Card or Dummy Card PC Card Stop PCB Mounting Rack Figure 11-25: Connector Shock & Vibration Test Fixture 1. The PC Card cover facing the conducting plate. should make mechanical contact with the conducting plate during test. left side.5 kV 100 pF GND 1 25 mm2 max Contact Area PC Card Insulator 1 Connect to the four (4) ground contacts (Pin No’ s 1.5 kW C C 15 kV GND 100 pF C C P C C A R D CO NN EC TO R N CO DU CT P ING LA TE TE U INS LA T P ING LA Notes: 1.5 kW 1. 35 and 68) Figure 11-26: Electrostatic Discharge Test-1 Fixture 1. non-connector end and right side three times each. PC Card to make contact with the conducting plate. Discharge to top cover.50 Pin Connector with Card Guide 0. 2. 34. Total discharge cycles = 12 on each side.

The PC Card shock and vibration test fixture shall entrap the PC Card such that all shock and vibration shall be transmitted into the sample card Figure 11-28: PC Card Shock and Vibration Test Fixture © 1999 PCMCIA/JEIDA 57 .PHYSICAL SPECIFICATION 55 Clamping Device mm CO NN EC PC TO R CA RD 86 mm 1.

  .70 MAX CLAMP 19..0° 2 THE FORCE BAR SHALL APPLY A UNIFORM FORCE ACROSS THE END OF THE PC CARD Figure 11-29: Full-size PC Card Bend Test Fixture 19..60 MIN 1 12.20 MIN 1 12.70 MAX FULL-SIZE PC CARD 1 THE CONTACT RADIUS FORCE BAR IS 5.FIGURES   .0° ± 1.0° ± 1. 19.6 N Static Load 12.0° THE FORCE BAR SHALL APPLY A UNIFORM FORCE ACROSS THE END OF THE SMALL PC CARD Figure 11-30: Small PC Card Bend Test Fixture 58 © 1999 PCMCIA/JEIDA .70 MAX SMALL PC CARD 1 2 THE CONTACT RADIUS FORCE BAR IS 5.6 N Static Load 12.70 MAX CLAMP 60.

.236 Nm OR 10°. THE TORQUE AND ANGLE MAX ARE: TORQUE 1.70 MAX CLAMP 19. WHICHEVER OCCURS FIRST Figure 11-32: Small PC Card Torque Test Fixture © 1999 PCMCIA/JEIDA 59 . THE TORQUE AND ANGLE MAX ARE: TORQUE 1.236 Nm OR 10°.60 MIN 10˚ 10˚ SMALL PC CARD 1 1 1 APPLY TORQUE TO UNCLAMPED END OF SMALL PC CARD. 12.70 MAX 12.20 MIN 10˚ 10˚ FULL-SIZE PC CARD 1 1 PHYSICAL SPECIFICATION 1 APPLY TORQUE TO UNCLAMPED END OF PC CARD..70 MAX CLAMP 60.70 MAX 12.  . WHICHEVER OCCURS FIRST Figure 11-31: Full-size PC Card Torque Test Fixture 12.   ..

.. PARALLEL PLATES T NOTE: CARD ENLARGED FOR ILLUSTRATIVE PURPOSES Figure 11-34: Warpage Measurement AÐSubstrate Area 60 © 1999 PCMCIA/JEIDA . .. . . . ... LONG SIDE 3... .... .0) PARALLEL PLATES NOTE: CARD ENLARGED FOR ILLUSTRATIVE PURPOSES 0. ... . ..0.0 SH O RT SI DE 10 ... INTERCONNECT AREA (SHORT SIDE 10.... ...15 MAX CONNECTOR SIDE Figure 11-33: Warpage Measurement AÐInterconnect Area .. ........0 0.. . . ...FIGURES . . .... .. . .. .35 MAX W LONG SIDE 3.

0 T(s) T (MAX) SLIDE CARD © 1999 PCMCIA/JEIDA ..... .0 Figure 11-35: Warpage Measurement BÐThickness Measurements ...0 10..0 T(i) 10.. 10. 10.. HORIZONTAL PLATE Figure 11-36: Warpage Measurement BÐMeasurements 61 . ..PHYSICAL SPECIFICATION CONNECTOR SIDE ....... .

.. ..0 3.0 MIN Figure 11-37: Warpage Measurement BÐMeasurement Positions . . 3.FIGURES MEASUREMENT POSITION CONNECTOR SIDE 10.0 MIN 62 10.. .. .. . .. ... .0 10. . ..0 10..0 MIN © 1999 PCMCIA/JEIDA . . .. . .. ..

.PHYSICAL SPECIFICATION Y X Z  . Host Connector Figure 11-38: Card Inverse Insertion Test Fixture Figure 11-39: Card Inverse Insertion Push Block © 1999 PCMCIA/JEIDA 63 ..

08 ± 0.10 SURFACE A Figure 11-40: CardBus PC Card Recommended Connector Grounding Interface Dimensions 64 © 1999 PCMCIA/JEIDA .10 5.10 5.60 S 2.30 R 0.35 ± 0.00 ± 0.15 A S +0.10 6 PLC -A0.50 ± 0.15 6.83 ± 0.10 36.FIGURES 54.38 ± 0.20 -0.

91 REF 1.64 8 PLC E 2.64 0.PHYSICAL SPECIFICATION X ¢ X 0.27 TYP TOP SURFACE 41.27 REF BOTTOM SURFACE Figure 11-41: CardBus PC Card Recommended PCB Footprint © 1999 PCMCIA/JEIDA 65 .01 TYP 1.41 ± 0.05 TYP 0.

91 REF POSN #67 POSN # 68 2.36 REF 2 PLC 51.26 Figure 11-43: CardBus PC Card Recommended Right Angle PCB Footprint 66 © 1999 PCMCIA/JEIDA .62 REF 1.91 TYP POSN #36 1. FOR GROUNDING TO PCB POSN #33 POSN #34 POSN #1 POSN #2 POSN #35 7. ASSEMBLY KEYED FOR LOW VOLT CARDS (3.27 TYP INSERT CARD 41.FIGURES POSN #34 POSN #1 POSN #35 POSN #68 1.3V) Figure 11-42: CardBus PC Card Recommended Host Connector Grounding Interface Dimensions POSITIONS FOR GROUND SHROUD FEATURE 16 PLC.

36 REF 2 PLC 1.95 REF Figure 11-44: CardBus PC Card Recommended Right Angle PCB Footprint (Stacked) © 1999 PCMCIA/JEIDA 67 .14 REF 2.91 TYP POSN #68 POSN #67 POSN #33 POSN #34 POSN #36 17.PHYSICAL SPECIFICATION POSN #2 POSN #1 POSN #36 POSN #35 POSN #1 POSN #2 POSN #35 POSITIONS FOR GROUND SHROUD FEATURE 32 PLC.62 REF 8.91 REF 44.26 4.27 TYP INSERT CARD POSN #67 POSN #68 41.70 REF 51.13 REF GROUND PAD TO BE LOCATED WITHIN AREA SHOWN 2 PLC 60. FOR GROUNDING TO PCB POSN #33 POSN #34 1.

5 mm DIMPLES (8) GROUND SHROUD FOR HOST CONNECTOR FOR REFERENCE ONLY Figure 11-45: CardBus PC Card Reference Shrouded Connector 68 © 1999 PCMCIA/JEIDA .6 mm WIPE FINGERS (8) GROUND PLATE FOR CARD CONNECTOR 0.38 mm 3.FIGURES 5.

5 mm DIMPLES (8) 2x GROUND SHROUD FOR HOST CONNECTOR FOR REFERENCE ONLY Figure 11-46: CardBus PC Card Reference Shrouded Connector (Stacked Connector) © 1999 PCMCIA/JEIDA 69 .PHYSICAL SPECIFICATION 5.6 mm WIPE FINGERS (8) 2x GROUND PLATE FOR CARD CONNECTOR 0.38 mm 3.

FIGURES A PC CARD POWER SUPPLY SOCKET TERMINATION RESISTANCE MEASUREMENT POINTS Figure 11-47: Contact Resistance Measurement 70 © 1999 PCMCIA/JEIDA .

P C C A R D S TA N D A R D Volume 4 Metaformat Specification .

Suite 209 San Jose. Suite 209 San Jose. PCMCIA HAS OBTAINED FROM SOME. registered in the United States. EXPRESS OR IMPLIED. photocopying. PCMCIA (Personal Computer Memory Card International Association) 2635 North First Street. PCMCIA/JEIDA All rights reserved. MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. in any form or by any means. 0299-04-2000 First Printing. recording or otherwise. INCLUDING AS TO NONINFRINGEMENT. IMPORTANT: In order to receive the Grant of Immunity.PCMCIA JEIDA ©1999. PCMCIA HAS BEEN NOTIFIED BY CERTAIN THIRD PARTIES THAT THE IMPLEMENTATION OF THE STANDARD WILL REQUIRE A LICENSE FROM THOSE THIRD PARTIES TO AVOID INFRINGEMENT OF THEIR RIGHTS. CA 95134 USA +1-408-433-2273 +1-408-433-9558 (Fax) JEIDA (Japan Electronic Industry Development Association) Kikai Shinko Kaikan. Tokyo 105. Shibakoen Minato-ku. WITH RESPECT TO THE STANDARD. BUT NOT ALL. or transmitted. without prior written permission of PCMCIA and JEIDA. 3-5-8. CONTINGENT UPON YOUR ENTERING INTO AND DELIVERING TO PCMCIA THE RECIPROCAL GRANT OF IMMUNITY AGREEMENT CONTAINED ELSEWHERE IN THIS STANDARD. Printed in the United States of America.Ó Document No. registered in Japan. OF THOSE PARTIES A GRANT OF IMMUNITY THAT PCMCIA WILL EXTEND TO YOU. February 1999 . No part of this publication may be reproduced. mechanical. JAPAN +81-3-3433-1923 +81-3-3433-6350 (Fax) The PC Card logo and PC Card are trademarks of PCMCIA. CA 95134 USA NEITHER PCMCIA NOR JEIDA MAKES ANY WARRANTY. the owner of this Standard must sign and return the enclosed Registration Card to: PCMCIA 2635 North First Street. electronic. The PC Card logo and design are trademarks of JEIDA. stored in a retrieval system. THIS STANDARD IS PROVIDED TO YOU ÒAS IS.

.........................................8 2.................................................................2 Scope..............................1 0 2..........................................................................10............7 2...........................................................................3...................................................................................................................................3....................4 2.........4 2.....................................................................................1 Metaformat Layer Hierarchy ...........................................3.......................................3 Longlink Pointing to Invalid Tuple Chain.........................................................................................10 Tuple Processing Recommendations.........3...........................................................................................1.......................5..............................1..................4 2......................................................................4................................3 2...........................................................................................................................................................3 Byte Order on Wide Cards ..........................................................................................................2 1 3............................1 2.......................................................................................3.................................................4 2....................................3 Metaformat Architecture......................................2 System Rejection of Unsupported Cards...........................4 Metaformat Summary.7 CardBus PC Card Metaformat.........9 2......2 0 3...............3..................................2 3 3........................................................................5 Special Considerations .........................1 9 3......................................................................................17 3.................................................................................................3 CISTPL_INDIRECT: Indirect Access PC Card Memory ......................2 CISTPL_END: The End Of Chain Tuple................................................................................................................6 CISTPL_LONGLINK_CB: The CardBus PC Card LongLink Tuple......................8 2.................3............................................4 CISTPL_LINKTARGET: The LinkTarget Tuple.............................METAFORMAT SPECIFICATION CONTENTS 1.....1...................................2 Metaformat Requirements..............................4 16-bit PC Card Metaformat in Attribute Memory Space .......................................2 2 3.1 Purpose.......5 CISTPL_LONGLINK_A.....................1 8 3.......1 Control Tuples.............................................2 Processing Longlink Tuple ........7 CISTPL_LONGLINK_MFC: The Multiple Function 16-bit PC Card Link Tuple...........................5 2.........................3...............................................8 16-bit PC Card Tuple Chain Processing ...........7 2...................... 8 2...............................10.........................................................................................................................1 Vendor-Specific Information .................1 1.....................3.............................................3........................2 5 © 1999 PCMCIA/JEIDA iii ......................5 16-bit PC Card Metaformat in Common Memory Space................................3....1 5 2..........................9 CardBus PC Card Tuple Chain Processing ..1 1....10.....4................... Basic Compatibility (Layer 1) ___________________________ 17 3..............................1 Metaformat Overview .1.....1 0 2.... Introduction ___________________________________________ 1 1....1...............................6 2......9 2...................................................................................................................................3................................................................................... Overview ______________________________________________ 3 2.1.............. CISTPL_LONGLINK_C: The 16-bit PC Card LongLink Tuples........3....................................1 Tuple Code Known....................................10 2................3 Related Documents ................9 2.........1 5 3.....................................2 Tuple Code Summary ..1.............1 CISTPL_CHECKSUM: The Checksum Tuple ..........................................................15 2............5 2....................................................3 2......................................................................................................................................1 Basic Tuple Format and Tuple Chain Structure....................................................................2 Byte Order Within Tuples .........................3.......11 16-bit PC Card CIS with Indirect Access PC Card Memory .......................................................................................5........................................6 16-bit PC Card Metaformat for Multiple Function Cards....................................................................

..............3......................2 7 3....................1 Device Info Fields (For Tuples CISTPL_DEVICE.....10 CISTPL_VERS_1: The Level 1 Version / Product Information Tuple ..1...........................................................................................6.3 Address Space Indicator Field (CardBus PC Card only) ....................................4 8 3......5 3 3..........5......7 4 3...... CISTPL_DEVICEGEO_A: Device Geometry Tuples......3 4 3.....................1........................3 Function Extension Tuple for Data Modem........1......6 9 3..........1 LAN_TECH Function Extension Tuple ...............2..................2...................................................... CISTPL_DEVICE_A)....................2 9 3.......................2...................................................2..............................4 Function Extension Tuple for ISDN..............5.......1 Other Conditions Info Field.........6...6 3 3........5 LAN_CONN Function Extension Tuple .........................1...................................................................5 Function Extension Tuple for Voice Function ...2 Device Info fields (for tuple CISTPL_EXTDEVICE).......1.2......3 1 3..5......28 3.................6 7 3.....................5......................2..........1 CISTPL_ALTSTR: The Alternate Language String Tuple......1 Device ID fields .2....................2...............................................4 0 3...............3 0 3.......................................................5 CISTPL_EXTDEVICE: The Extended Common Memory Device Information Tuple...............3 9 3.........2 Device Memory Size > 64 MBytes ...................3 4 3................2................3 2 3.........................................1...3......2.........................6......1............2 8 3..........2.4 Function Extension Tuple for Document Facsimile ...5 Function Extension Tuple for Serial I/O Bus Adapter...........4 9 3...............................................4 3 3....5 6 3...........2................2..............................3 8 3................................................2............................2.............................................1.....................2...........................6........................................4 5 3......2..................................1 Serial Port Interface Function Extension...............3.....................................2....2..............................................6.....................................................................2............9 CISTPL_MANFID: Manufacturer Identification Tuple.......................2................................2.................2..9 CISTPL_NULL: The Null Tuple ..........................2.................1 Device Memory Size £ 64 MBytes .................2..2 Function Extension Tuple for Modem and ISDN Interface..........................4 CISTPL_DEVICEGEO................6 8 3.........4 LAN_NID Function Extension Tuple ...........................3 Tuple Examples for Memory Device Size > 64 MBytes...................2....................6............7 CISTPL_FUNCID: Function Identification Tuple ..1...............................................................2...4 5 3...............................3 1 3.............................3 8 3................................................4 6 3.......2....................................6 6 3.........4..................2............................2..........1 Device ID Fields ...........................................................2 Basic Compatibility Tuples.....3...........6...................2.............................................................2.................................1.....................2........................3 CISTPL_DEVICE_OC....6 CISTPL_FUNCE: Function Extension Tuple....2 The Device Size Byte(s) (For Tuple CISTPL_EXTDEVICE).........2..............................5..............................4 0 3................1.....2...6..............3..................................................8 CISTPL_JEDEC_C...6..............1...1.............2 6 3........................2...........3 6 3........................2........................................... CISTPL_DEVICE_A: The 5 volt Device Information Tuples.........................................................................6.......3 Function Extension Tuple for LAN ......2.................................................................2............................................2...4 0 3..................1.........................................................................6...................3 LAN_MEDIA Function Extension Tuple.....2..6 Function Extension Tuple for ISDN Terminal Adapter ......................3 1 3.........................6 8 3...............2................................5 8 3..1..............................................2 CISTPL_DEVICE...................................................................1 Function Extension Tuples for Serial Ports..2....2..............1...........................................2................6..........6...................2..................................2 WPS Field...2.....2.2 The Device Size Byte (For Tuples CISTPL_DEVICE....2..................................2..............5.......2.........................................2...........................................CONTENTS 3......................................................6 8 3....................7 2 3.....................1 Device Type Code Field.............1 ISDN_TECH Function Extension Tuple ............6.......6 7 3.........3 0 3.................6.....6 7 3................................................6.....5.......................................3..........8 CISTPL_NO_LINK: The No-Link Tuple ......7 7 iv © 1999 PCMCIA/JEIDA .....2............................7 6 3......1....................................................................2 Function Extension Tuple for Disk........................2 LAN_SPEED Function Extension Tuple............................................... CISTPL_DEVICE_OA: The Other Conditions Device information Tuples.1 Memory Paging Info Field ....4 1 3.............4 Device Speed Field (16-bit PC Card only).....1..................................................3 3 3................... CISTPL_DEVICE_A)...........................6 9 3...... CISTPL_JEDEC_A: The JEDEC Identifier Tuples..........2.........2........................................6........................................

.....................................................5..................3....................4 TPCE_CBIO: I/O Base Address Registers Used.................106 3........................6 TPCE_IO: I/O Space Addresses Required For This Configuration...........................103 3.....................3.....................................................4..........8 9 3...........................3 CISTPL_VERS_2: The Level-2 Version and Information Tuple...........................3 CISTPL_CFTABLE_ENTRY_CB: CardBus PC Card Configuration Table Entry Tuple.3.....111 4..........................................2 TPCE_CBFS: Feature Selection Byte ...4 CISTPL_CONFIG: 16-bit PC Card Configuration Tuple............................................5......................3....3.......9 8 3................................................100 3.....................................9 2 3....6 TPCE_CBMS: Memory Base Address Registers Used.....................5.......7 TPCE_IR: Interrupt Request Description Structure........3........................................................................2..3..5 TPCC_SBTPL: Configuration tuple Sub-tuples....3................9 8 3............3 Configuration Tuples ................3........................................................7 9 3.......3.......3 TPCC_RADR: Configuration Registers Base Address in Attribute Space ............................................................................................5..........7 TPCE_CBMI: CardBus PC Card Miscellaneous Features Field..................8 2 3.............................1 CISTPL_BATTERY: The Battery-Replacement Date Tuple .......................4.....9 5 3.................................2 TPCC_LAST: Card Configuration Table Last Entry Index..............................8 TPCE_ST: Additional information in subtuple format .............2 TPCC_LAST: Card Configuration Table Last Entry Index.......3............................................................2 TPCE_IF: Interface Description Field.............4 TPCE_PD: Power Description Structure ...9 4 3..................3............3..............................................................................112 © 1999 PCMCIA/JEIDA v ..............................3 TPCE_FS: Feature Selection Byte ..1 TPCE_INDX: The Configuration Table Index Byte...............................................................................1 TPCE_INDX: The Configuration Table Index Byte....METAFORMAT SPECIFICATION 3....................2..6 CISTPL_PWR_MGMNT: Function State Save/Restore Definition............................................................................8 6 3.................................3................................2........10....3..........................9 3 3......110 4..........10 TPCE_ST: Additional information in subtuple format............................................................2............101 3............78 3.9 6 3...109 4......9 4 3.3............1 Card Information Tuples ..................................2 CISTPL_CFTABLE_ENTRY: 16-bit PC Card Configuration Table Entry Tuple ......................1..105 3....102 3.................................................................................9 9 3...................................................106 3...................5 TPCE_TD: Configuration Timing Information.3.1 TPCC_SZ: Size of Fields Byte...........3.............4...............................3.........1 CCSTPL_CIF: Custom Interface Subtuples................................................3.........3 Additional I/O Feature Definitions within Entry..............................................8 1 3......3....3....................3....2 CISTPL_DATE: The Card Initialization Date Tuple .......................................................................1 STCE_EV: Environment Descriptor Subtuple.......5 CISTPL_CONFIG_CB: CardBus PC Card Configuration Tuple..............................3..........................3.....................................................................................3..............103 3..................3.......1..................3....102 3.....4.......................3.......9 5 3....................................9 8 3.............2....9 6 3........3 TPCC_ADDR: CardBus PC Card Status Register Pointer.......3.3...............................2.................................8 0 3........9 1 3......102 3.1 TPCC_SZ: Size of Fields Byte.............................1 CISTPL_BAR: CardBus PC Card Base Address Register Tuple....3........105 3.............................................2......2........................2................................105 3....3.........................10................4......................10................2.....3.............8 4 3....4.................................8 0 3..................................3.........................................106 4................9 TPCE_MI: Miscellaneous Features Field.................................................................8 TPCE_MS: Memory Space Description Structure .............................................3.................1 I/O Space Encoding Guidelines.........................8 7 3...2.........................2 STCE_PD: Physical Device Name Subtuple.....................3.......................3..............3....5.103 3..................3..................3........................5 TPCE_IR: Interrupt Request Description Structure.................................................................3.............3.............4 TPCC_RMSK: Configuration Register Presence Mask Field for Interface Tuple.......6......................................................................3 TPCE_PD: Power Description Structure ........................................................................2........................................................1...2.................4 TPCC_SBTPL: Additional Information Stored in Tuple Format...........................9 7 3........................................................................9 8 3.........................3......2.......... Data Recording Formats (Layer 2) ______________________ 109 4......3....3...................................

..........................118 4.......3 Arithmetic Checksums As Error-Detection Codes...5 Byte Mapping for Disk-Like Media ..116 4......................2 CISTPL_FORMAT................................................................................114 4............................1 CISTPL_SPCL: Special Purpose Tuple ......129 7.............131 7..............................................................................................1 The Format Tuple for Disk-like Regions...2.....................2..............................................2.. CISTPL_FORMAT_A: The Format Tuples.....................CONTENTS 4.......................122 4....2.........129 6.....................................1 System-Specific Standard Tuples.....120 4.............................115 4..2.............. System-Specific Standards (Layer 4)____________________ 129 6............................................................................................................................120 4................123 5.............................2..............................................2....131 vi © 1999 PCMCIA/JEIDA ...........................................................................1 CISTPL_BYTEORDER: The Byte-Order Tuple.........................................................................1..................................1 CISTPL_ORG: The Organization Tuple.............1........ Data Organization (Layer 3) ___________________________ 125 5.................2 Media Storage Formats .......123 4............1 Buffer Pages.............................117 4.............................4 Mixed Data Formats ................................................... 120 4...........................2....................................2.....2..........................4 CRC Error-Detection Codes.................................................................................................................................................................125 5............121 4................2 Data Recording Format Tuples..............................2 The Format Tuple for Memory-like Regions.........................................2...3 Standard Data Recording Formats.................................................. Compatibility Issues _________________________________ 131 7.......126 6......................................................................................................2................................3 CISTPL_GEOMETRY: The Geometry Tuple.......................................................................2......................................2.....................................................4 CISTPL_SWIL: Software Interleave Tuple......................................................................................1 Data Organization Tuples ......

........................................................23 Table 3-7 CISTPL_LONGLINK_MFC: The Multiple Function 16-bit PC Card Link Tuple...............................................................19 Table 3-3: CISTPL_INDIRECT: Indirect Access PC Card Memory......................................................................................................20 Table 3-4 CISTPL_LINKTARGET: Link Target Tuple .........................................................54 Table 3-20 CISTPL_FUNCE: Voice Function Extension Tuple .....................................34 Table 3-13 CISTPL_DEVICEGEO and CISTPL_DEVICEGEO_A: Device Geometry Tuples ..59 Table 3-22 CISTPL_FUNCE: Disk Function Extension Tuple...............................................METAFORMAT SPECIFICATION TABLES Table 2-1 Basic Tuple Format......25 Table 3-8 CISTPL_NO_LINK: The No-Link Tuple...........22 Table 3-6 CISTPL_LONGLINK_CB: The CardBus PC Card LongLink Tuple...........................64 Table 3-23 CISTPL_FUNCE: Combined PC Card ATA Function Extension Tuple......21 Table 3-5 CISTPL_LONGLINK_A and CISTPL_LONGLINK_C: 16-bit PC Card LongLink Tuples .............................................38 Table 3-15 CISTPL_FUNCE: Function Extension Tuple ...............................................................................45 Table 3-16 CISTPL_FUNCE: Serial Port Interface Function Extension Tuple............................ CISTPL_DEVICE_A: The 5 volt Device information Tuples..............14 Table 3-1 CISTPL_CHECKSUM: Checksum Tuple.............26 Table 3-9 CISTPL_NULL: The Null Tuple....................................................................6 Table 2-4: Minimal CIS for Indirect Memory Access PC Cards ....50 Table 3-19 CISTPL_FUNCE: TPCID_FF: Document Facsimile Function Extension Tuple ..............................................................18 Table 3-2 CISTPL_END: End of Chain Tuple....... CISTPL_DEVICE_OA: The Other Conditions Device information Tuples....................................................................................................................................................................................36 Table 3-14 CISTPL_EXTDEVICE: The Extended Common Memory Device information Tuples ............56 Table 3-21: CISTPL_FUNCE: ISDN Function Extension Tuple ...........6 Table 2-3 Function-specific CIS for Multiple Function PC Cards ......................................................................................................................................................................................................................................................28 Table 3-11 CISTPL_DEVICE........4 Table 2-2 Global CIS for Multiple Function PC Cards................48 Table 3-18 CISTPL_FUNCE: Data Modem Function Extension Tuple ........12 Table 2-6 Tuple Summary Table (Numerically by Tuple Code) ............................................................64 © 1999 PCMCIA/JEIDA vii .............................47 Table 3-17 CISTPL_FUNCE: Modem and ISDN Interface Function Extension Tuple..................9 Table 2-5 Tuple Summary Table ..................................................................................................27 Table 3-10 CISTPL_ALTSTR: The Alternate Language String Tuple.....29 Table 3-12 CISTPL_DEVICE_OC...........................................................................................................................................................................................

......TABLES Table 3-24 CISTPL_FUNCE: Dual-Drive Card PC Card ATA Function Extension Tuple............................................................................................119 Table 4Ð8 CISTPL_GEOMETRY: Geometry Tuple .....................................................................70 Table 3-34 CISTPL_FUNCID: Function Identification Tuple .............69 Table 3-33: CISTPL_FUNCE: USB Serial I/O Bus Adapter Function Extension Tuple ...............101 Table 3-42 CISTPL_CONFIG_CB: CardBus PC Card Configuration Tuple .80 Table 3-40 CISTPL_CFTABLE_ENTRY_CB: CardBus PC Card Configuration Table Entry Tuple............................................66 Table 3-26 CISTPL_FUNCE: LAN_TECH Function Extension Tuple................105 Table 3-43 CISTPL_PWR_MGMNT: Function State Save/Restore Definition ......................72 Table 3-35 CISTPL_JEDEC_C and CISTPL_JEDEC _A: JEDEC Identifier Tuples.................................67 Table 3-29 CISTPL_FUNCE: LAN_NID Function Extension Tuple..................................................................69 Table 3-32: CISTPL_FUNCE: 1394 Serial I/O Bus Adapter Function Extension Tuple ....................................74 Table 3-36 CISTPL_MANFID: Manufacturer Identification Tuple ..................................................................................79 Table 3-39 CISTPL_CFTABLE_ENTRY: Configuration Table Entry Tuple .................................................................110 Table 4Ð2 CISTPL_DATE: Card Initialization Date Tuple.......................................111 Table 4Ð3 CISTPL_VERS_2: Level-2 Information Tuple...............................................................................107 Table 4Ð1 CISTPL_BATTERY: Battery Replacement Date Tuple.......117 Table 4Ð7 Format Tuple for Memory-like Regions......................................................121 Table 4Ð9 CISTPL_SWIL: Software Interleave Tuple.............................................112 Table 4Ð4 CISTPL_BYTEORDER: Byte Order Tuple............................129 viii © 1999 PCMCIA/JEIDA .........................................................96 Table 3-41 CISTPL_CONFIG : 16-bit PC Card Configuration Tuple .........................................................126 Table 6Ð1 CISTPL_SPCL: Special Purpose Tuple ........116 Table 4Ð6 Format Tuple for Disk-like Regions...............68 Table 3-30 CISTPL_FUNCE: LAN_CONN Function Extension Tuple ..................................68 Table 3-31: CISTPL_FUNCE: ISDN Function Extension Tuple .....122 Table 5Ð1 CISTPL_ORG: Data Organization Tuple.......115 Table 4Ð5 CISTPL_FORMAT and CISTPL_FORMAT_A: Format Tuples.....................................67 Table 3-28 CISTPL_FUNCE: LAN_MEDIA Function Extension Tuple........77 Table 3-38 CISTPL_BAR: CardBus PC Card Base Address Register Tuple .....................................................................................................66 Table 3-25 CISTPL_FUNCE: LAN Function Extension Tuple...................................................67 Table 3-27 CISTPL_FUNCE: LAN_SPEED Function Extension Tuple ...............................................................................................................................................................................................................76 Table 3-37 CISTPL_VERS_1: Level 1 Version / Product Information Tuple .........................

Physical Specification Volume 4. Guidelines Volume 11: PC Card Host System Specification IEEE 1394-1995 Specification. on PC Cards and for interpreting the metaformat for the purposes of configuring and utilizing PC Cards. PC Card ATA Specification Volume 9. Card Services Specification Volume 6. Socket Services Specification Volume 7.2 Scope It is recommended that all aspects of a PC Card which can be described in CIS be so described. I N T R OD U C T ION 1. XIP Specification Volume 10. Metaformat Specification Volume 5. IEEE © 1999 PCMCIA/JEIDA 1 .1 Purpose This specification provides information necessary for implementing the Card Information Structure (CIS). or Metaformat.METAFORMAT SPECIFICATION 1. Electrical Specification Volume 3. 1. 1.0 (February 1999). Full disclosure of a PC CardÕs characteristics in the CIS is a basic component of compatibility and interchangeability. Overview and Glossary Volume 2. PCMCIA /JEIDA Volume 1. Media Storage Formats Specification Volume 8.3 Related Documents PC Card Standard Release 7.

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the card is asserting READY and the card has been reset by the host after power-up in accordance with the PC Card Standard. 2. and individual device characteristics. (See the Physical Specification and the Electrical Specification. 4. the electrical and physical interface characteristics of PC Cards. The Data Organization Layer Ñ currently includes a single tuple. CISTPL_ORG. The Basic Compatibility Layer Ñ specifies a minimal level of card-data organization. the Metaformat is a hierarchy of layers. The format and interpretation of any tuple in the vendor-unique range is not documented within the Standard. 2. which increases as the level of abstraction gets higher. The CIS of a 16-bit PC Card shall be readable whenever the card is powered. 3. the file system) in use in a partition described by Data Recording Format Layer tuple(s). The MBR shall contain a partition table describing how the media is partitioned. Below the Metaformat is the physical layer.) The Metaformat layers are: 1. (See the Electrical Specification.METAFORMAT SPECIFICATION 2. and the range of vendor-unique tuple codes. Each layer has a number. CISTPL_SPCL.) All linear memory PC Cards shall describe how they are partitioned. The Data Recording Format Layer Ñ includes tuples which describe partitioning information and provide card initialization information. manufacturer. which specifies the partition organization (for example. even if the entire PC Card is used as a single partition. (See the Media Storage Formats Specification. somewhat incompatible data-recording formats and data organizations. and programming information. As is done with networking standards. The special purpose tuple provides a mechanism for documenting the format and interpretation of special tuple usage within the PC Card Standard. (See the Media Storage Formats Specification. such as size. O V E R V IE W 2.1 Metaformat Overview Metaformat goals include the ability to handle numerous. This includes after the PC Card is configured and when the PwrDwn bit is set in the Card Configuration and Status Register. speed.) · · · © 1999 PCMCIA/JEIDA 3 . The System-Specific Layer Ñ includes the special purpose tuple.2 Metaformat Requirements The PC Card Standard has the following Card Information Structure (CIS) requirements: · · All PC Cards shall have a CIS that describes the functionality and characteristics of the card. Tuples at this level provide fundamental information about the PC Card including supported configurations.) All ATA PC Cards shall be formatted with a Master Boot Record (MBR) in the first physical sector of the media. (See the Electrical Specification.) The CIS of a CardBus PC Card shall be readable whenever the card is powered and the power up process has been completed.

3. There are two ways of marking the end of a tuple chain for 16-bit PC Cards: a tuple code of FFH.3 Byte Order on Wide Cards If a card has a data path wider than 8-bits.3. System software must use the link field to validate tuples. software must not scan beyond the implied length of the tuple. the same process shall be repeated on subsequent words 4 © 1999 PCMCIA/JEIDA . In this case.2 Byte Order Within Tuples Within tuples. (See also 2.3. but it is recommended to use the End of Chain tuple. only the even bytes are present.OVERVIEW 2. No CardBus PC Card tuple can be longer than 256 bytes: 1 byte TPL_CODE + 1 byte TPL_LINK + FEH byte tuple body. (n) The tuple body. all character data shall be stored in the natural order. or a tuple link of FFH. the leastsignificant byte of a data item shall be stored in the first byte of a given field. Within tuples. However. This is the number of bytes in the tuple body. A tuple code of FFH is a special mark indicating that there are no more tuples in the chain. one must assign a byte order to the data path. Fixed-length character fields shall be padded with null characters. When the first word is filled. the first character of the field shall be stored in the first byte of the field.9 CardBus PC Card Tuple Chain Processing. Ascending bytes of each word shall be used to sequentially record bytes from the CIS.1 Control Tuples. then the tuple body is empty. then this tuple is the last tuple in its chain.) All tuples have the format shown below.) The use of an FFH link value is allowed in 16-bit PC Cards for backward compatibility.8 16-bit PC Card Tuple Chain Processing and 2.1 Basic Tuple Format and Tuple Chain Structure The Card Information Structure is one or more chains (or linked lists) of data blocks or tuples. This standard requires that the low-order byte of word 0 be used to record byte 0 of the CIS. even if a termination byte has not been seen. This applies to all CardBus PC Card CISÕs and to those fields within a 16-bit PC Card CIS that are recorded in Common Memory space. Some tuples provide a termination or stop byte that marks the end of the tuple.3 Metaformat Architecture 2. 2. No 16-bit PC Card tuple can be longer than 257 bytes: 1 byte TPL_CODE + 1 byte TPL_LINK + FFH byte tuple body (and this 257 byte tuple ends the chain).3. Attribute Memory Space is byte-wide only. all multi-byte numeric data shall be recorded in little-endian order. At present. That is. if necessary. TPL_LINK Offset to next tuple in chain. If the link field of a 16-bit PC Card contains FFH. 2. There is only one way of marking the end of the tuple chain for CardBus PC Cards: A tuple code of FFH. Longlink and linktarget tuples are used to connect chains (See 3. Byte 1 of each tuple contains a link to the next tuple in the chain.3. That is. If the link field is zero. the tuple can effectively be shorter than the value implied by its link field. (n bytes) Byte 0 of each tuple contains a tuple code. Table 2-1 Basic Tuple Format Byte 0 1 2áá(n + 2) 7 TPL_CODE 6 5 4 3 2 1 0 Tuple code: CISTPL_xxx.

some data-format layers impose further requirements. Both the card's even and the odd bytes are used to record data. other machines may need to reorder the bytes when reading or writing the CIS. The Common Memory CIS may be stored immediately following the Attribute Memory CIS. the contents of location 0 in Attribute Memory space will be different and distinct from the contents of location 0 in Common Memory space. These cards provide an Attribute Memory-style CIS starting at byte zero of the card. The basic compatibility layer does not impose any particular byte order on non-header portions of the card.3. the offset to the next tuple in Attribute Memory is two times the link field. some 16-bit PC Cards will not have Attribute Memory distinct from Common Memory. In this case. However. the data will be recorded in even bytes only. For simplicity. some 16bit PC Cards will have a distinct physical Attribute Memory. even if Attribute Memory is not distinct from Common Memory. many 16-bit PC Cards.3. If. Here. If only the even bytes are read. On x86 architecture machines. However.METAFORMAT SPECIFICATION until the entire CIS is recorded. When a tuple is recorded in Common Memory space of a 16-bit PC Card. memory cycles always access Common Memory. 2. Link fields of tuples stored in Attribute Memory space are handled as follows.4 16-bit PC Card Metaformat in Attribute Memory Space 16-bit PC Cards have two address spaces: Attribute Memory space and Common Memory space. this specification describes the tuples of the Metaformat as if the bytes of each tuple were recorded consecutively. this does mean that if Attribute Memory is directly addressed. This standard allows attribute information to be stored both in Attribute Memory and CommonMemory space. In addition. for space reasons. The contents of odd-byte addresses of Attribute Memory space are not defined. the link fields shall be set appropriately for byte addressing. 2. However. when a tuple is recorded in Attribute Memory space. and the tuples are packed into consecutive bytes in system memory. On these cards. The electrical specification for 16-bit PC Cards requires that information be placed only in even-byte addresses of Attribute Memory space. the bytes will indeed be recorded consecutively. regardless of the state of the REG# line. It is important to distinguish between Attribute Memory space and Attribute Memory. Regardless of the presence or absence of Attribute Memory. will not implement a separate Attribute Memory space. © 1999 PCMCIA/JEIDA 5 . accessed by asserting the REG# pin. memory-read operations from a given location in Attribute Memory space will return the same data as read operations from the same location in Common Memory space. All 16-bit PC Cards will have Attribute Memory space. a long link to Common Memory shall be embedded in the CIS. the CIS for 16-bit PC Cards always begins at location 0 of Attribute Memory space. such as ROM cards. the manufacturer wants to switch to a Common Memory-style CIS (packed into ascending bytes). However. and recorded in even bytes only. Data accessed from Attribute Memory space must be stored in the even bytes only. this byte order is equivalent to the native order.5 16-bit PC Card Metaformat in Common Memory Space For cost reasons. Tuples stored in Common Memory space are recorded in sequential bytes. This means that the link-field values are conceptually the same whether a tuple resides in Common or in Attribute memory.

The starting location of each function-specific CIS is given in a single CISTPL_LONGLINK_MFC tuple in the global CIS. Table 2-2 Global CIS for Multiple Function PC Cards Tuple CISTPL_DEVICE CISTPL_EXTDEVICE CISTPL_DEVICE_OC CISTPL_LONGLINK_MFC CISTPL_VERS_1 CISTPL_MANFID CISTPL_END Code 01H 09H 1CH 06H 15H 20H FFH Presence Mandatory (if PC Card has 5 volt key) Mandatory (if PC Card has > 64 MBytes of common memory) Recommended Mandatory Mandatory Mandatory Mandatory There is a function-specific Card Information Structure for each function on a Multiple Function PC Card. it must be stored only in the even bytes. Note: A CISTPL_FUNCID with a TPLFID_FUNCTION field reset to zero (0) shall not be placed in the CIS of a Multiple Function PC Card. Table 2-3 Function-specific CIS for Multiple Function PC Cards Tuple CISTPL_LINKTARGET CISTPL_CONFIG CISTPL_CFTABLE_ENTRY CISTPL_FUNCID CISTPL_FUNCE CISTPL_END Code 13H 1AH 1BH 21H 22H FFH Presence Mandatory Mandatory Mandatory Recommended Recommended Mandatory 6 © 1999 PCMCIA/JEIDA . Each function-specific CIS begins with a CISTPL_LINKTARGET tuple.OVERVIEW Note: The use of odd bytes to represent tuple data is controlled by the logicaladdress space in which the tuple resides. The 16-bit PC Card shall also contain a separate function-specific CIS for each set of Configuration Registers on the card. it must be stored in both even and odd bytes following a longlink target.6 16-bit PC Card Metaformat for Multiple Function Cards Multiple function 16-bit PC Cards shall contain multiple Card Information Structures (CIS). The global CIS on a multiple function 16-bit PC Card shall contain the following tuples. not by the type of memory actually used to record the tuple. If it is intended to be accessed in Common Memory space. The following tuples are contained in each function-specific CIS. 2. The first or global CIS on a 16-bit PC Card shall identify the card as containing multiple functions by the presence of a CISTPL_LONGLINK_MFC tuple. If the tuple is intended to be accessed in Attribute Memory space.3. This tuple is reserved for vendor-specific multiple function PC Cards that do not follow the multiple function PC Card definitions in this specification.

Tuple chains may be located in any of the card space with the exception of I/O space. Attribute Memory can be read-only memory.3. Note that most implementations will be limited to reading cards of a specific format. Tuple chains may appear in any of the images in an expansion ROM. Expansion ROM. Tuple chains in configuration space may only be placed in the device dependent region. many combinations of values available in the tuples will be non- © 1999 PCMCIA/JEIDA 7 . Cards with > 64 MBytes of Common Memory must contain the tuple CISTPL_EXTDEVICE (tuple code 09H).1. see 3. Memory Space. For flexibility. To facilitate automatic identification of ÒblankÓ cards. or at most.3.8 16-bit PC Card Tuple Chain Processing The information block must be located such that it can be easily found by low-level software. All tuple chains must start with a CISTPL_LINKTARGET tuple aligned on a four word boundary. Thus. the location of the next tuple chain is indicated by a CISTPL_LONGLINK_CB.7 CardBus PC Card Metaformat There is one CIS per card function. Low voltage keyed cards shall omit the CISTPL_DEVICE (tuple code 01H) or shall include a CISTPL_DEVICE with NULL Device Info fields. The CISTPL_DEVICE (tuple code 01H) must be the first non-control tuple found when traversing the chain(s). The formats of the CIS Pointer and the Address-SpaceOffset field of the CISTPL_LONGLINK_CB allow specifying a twenty-eight bit offset from the base of any of the first sixteen images in the expansion ROM. but subsequent tuples within a chain need not be so aligned. These issues are beyond the scope of the Standard. the CIS of a 16-bit PC Card can be extended into Common Memory. It is recommended that 16-bit PC Cards using a low voltage key begin the primary CIS chain with a CISTPL_LINKTARGET (tuple code 13H). a CISTPL_NULL (tuple code 00H). of a few different formats. The chain need not be located in the image on which the offset is based. It is expected that the CIS will be written once when the card is manufactured (or formatted) and then infrequently updated. it is suggested that problems of process interruption and disaster recovery be addressed.2 CISTPL_END: The End Of Chain Tuple for processing).METAFORMAT SPECIFICATION 2. independent of their eventual placement on a CardBus PC Card. or an CISTPL_END (tuple code FFH. If the functionÕs CIS does not complete in the current chain. allowing chains to be placed in images beyond the first sixteen. The beginning of the function's CIS is pointed to by the CIS Pointer in the function's configuration space header. which may consist of multiple tuple chains in different spaces. On any PC Card that expects or requires the CIS to be erased (for example a Flash or EEPROM technology card that erases the CIS area when it is reorganized). Multi-function CardBus PC Cards have an independent configuration space and CIS for each function. Requiring a CIS for each function allows each function to be generically described and helps in delivering such things as function specific executables in the expansion ROM associated with the function. Tuple chains can be located in the following card spaces: · · · Configuration Space. The first tuple in the primary CIS chain of a 16-bit PC Card with a 5 volt key must be either a CISTPL_DEVICE (tuple code 01H). Tuple chains may be located anywhere within memory space. 2. This also allows functions to be individually manufactured. This Standard requires that the primary CIS of a 16-bit PC Card be recorded in Attribute Memory starting at address zero (00H). but no single chain shall span multiple images.

3. memory space. and if the tuple does not contain active registers (which is the case for all standard tuples). All tuple chains. 4. However. The following are some specific recommendations. There is a separate CIS for each card function. If the link field is FF H (which also means end-of-chain and is only allowed for a 16-bit PC Card) then a maximum of 257 bytes Ñ the code byte. Bytes should be copied from the code byte up to the last byte before the next tuple. It is recommended that implementers restrict themselves to the suggested low-level formats defined in the Media Storage Formats Specification. The routine that reads a given tuple should be coded to start by examining the tuple code. (See also the Electrical Specification and 3. Traversing a CardBus PC Card's CIS(s) is the same as traversing that of a 16-bit PC Card. begin with a CISTPL_LINKTARGET tuple. if the code is vendor specific or represents an extension under a future standard).3.3. it is safe to read the code byte and the link byte.g. or the expansion ROM. Card Services will decode any long link tuples for the client.6 CISTPL_LONGLINK_CB: The CardBus PC Card LongLink Tuple. the beginning of the CIS is pointed to by the CIS Pointer. then the routine should copy bytes into a buffer in main storage. other bytes within the tuple may represent active registers.9 CardBus PC Card Tuple Chain Processing The recommended method of traversing a CardBus PC Card CIS is to use the Card Services GetFirstTuple/GetNextTuple interface. the Address Space Offset field gives the absolute address in device-dependent configuration space. 2. then the tuple should be ignored. the link byte and as many as 255 bytes of tuple data Ñ should be copied from the card to the main store. It may contain one CISTPL_LONGLINK_CB (tuple code 05H) to another tuple chain in the current space or another space. 2.OVERVIEW portable.10 Tuple Processing Recommendations This standard requires that system software be carefully coded in order to prevent incompatibilities from one system to another.1. The CISTPL_LONGLINK_CB tuple allows the placement of tuple chains in configuration space. The beginning of each function's CIS is indicated by the CIS Pointer in that function's configuration space header. When a client does this.) Each tuple chain on a CardBus PC Card must begin with a CISTPL_LINKTARGET (tuple code 13H). 2.10. The encoding of the CISTPL_LONGLINK_CB address matches that of the CIS Pointer. 2. If the code is not recognized. with the following exceptions: 1. If the tuple code is not recognized by the routine (e.3.1 Tuple Code Known If the tuple code is known. including the first one. For a given function. For the configuration space. 8 © 1999 PCMCIA/JEIDA . The Address Space Indicator field indicates in which space the CIS begins and the Address Space Offset field gives the offset into that space for the memory spaces and the expansion ROM space. The client requests tuples from each function's CIS by specifying the logical function number (0 through 7).

The software should not validate the target address. from a card which was initialized for some unanticipated use. An example of a minimal. Tuple processing in the indirect spaces follows the previously stated rules for processing tuples on all 16-bit PC Cards. 2. 2. _CB). or from corrupted data. nor should it immediately begin processing of tuples from the target address. Common Memory register-based indirect access mechanism. After processing tuple chains in the Attribute and Common memory spaces. but legally sufficient. In all cases. Longlink and no-link tuples should be processed after reaching the end of the tuple chain. Once tuple processing begins in the indirect spaces there is no return link to the direct access spaces. i. that fact should be recorded for later use. This situation may result from an uninitialized card. There is an implied link to indirect Common address zero if there is no tuple chain at indirect Attribute address zero. if a longlink is to be processed. Since only the corrupted data case merits a diagnostic message. This means that all longlink tuples placed in the indirect spaces refer to the indirect spaces.10. _C.3 Longlink Pointing to Invalid Tuple Chain A longlink that points to an invalid tuple chain should not usually cause any diagnostic messages to be displayed to the user.11 16-bit PC Card CIS with Indirect Access PC Card Memory 16-bit PC Cards with very limited Attribute and Common Memory spaces can utilize an optional. when a no-link tuple (CISTPL_NO_LINK) is found. software should validate the target address (by checking for a CISTPL_LINKTARGET tuple) and begin processing the target chain if it appears to be valid. At that time.3. software should merely record the target address and address space. a CISTPL_LONGLINK_A refers to indirect Attribute memory. The CISTPL_INDIRECT tuple is used to indicate the presence of indirect access registers. Similarly.METAFORMAT SPECIFICATION 2.10. Table 2-4: Minimal CIS for Indirect Memory Access PC Cards Address Space / Offset Attribute / 00H Attribute / 08H Attribute / 0CH Tuple CISTPL_DEVICE CISTPL_INDIRECT CISTPL_END Values 01H 02H 00H FFH 03H 00H FFH Common / 00H CISTPL_END FFH © 1999 PCMCIA/JEIDA 9 .2 Processing Longlink Tuple When processing a longlink tuple (CISTPL_LONGLINK_A.3. tuple processing follows the implied link indicated by the CISTPL_INDIRECT tuple to the indirect Attribute and indirect Common spaces.) Using this indirect access method these cards provide full disclosure of their capabilities and attributes by extending their CIS into the indirect space(s). (See the Electrical Specification.3. For example. or that it is initialized in some non-conforming way. Card Information Structure is shown in the table below. the implied link goes first to the indirect Attribute space where a CISTPL_LINKTARGET should be located at indirect Attribute address zero.e. a minimal legal CIS must be placed in the standard Attribute and Common Memory spaces. it is better to assume either that the card is uninitialized.

2.0 / JEIDA 4. or base address register description 1 Ñ first published PCMCIA 1.4 Metaformat Summary 2. Memory . 2. The Data Organization Layer Ñ Specifies how data on a card which is used for data storage is logically organized.X Volts VCC.1 / JEIDA 4. or Main-Chain in 16-bit MFC. Multiple Function PC Card . the numeric code assigned to the tuple.16-bit PC Cards providing either disk-like or memory-like data storage.2 Tuple Code Summary The following table provides a summary of all curent tuples and an indicator of the types of cards or the classes of functions where they are used. notes for 16-bit PC Cards which operate at 5 Volts VCC. Configurable .4. notes for CardBus PC Cards. requires NULL Device Info fields 10 © 1999 PCMCIA/JEIDA .2 4 Ñ first published PC Card Standard. 3.reference indicates when this tuple definition was first published. February 1995 5 Ñ recommended for use as appropriate 6 Ñ required in cards capable of operating at voltages other than 5 V VCC 7 Ñ recommended for use when applicable values (IDs and extensions) exist 8 Ñ not recommended. Column Entries: R Ñ Recommended M Ñ Mandatory NA Ñ Never. The System-Specific Layer Ñ Includes tuples that by their nature are specific to a particular operating environment or vendor implementation. Not Applicable S Ñ Single Instance Only per Function-Chain.1 Metaformat Layer Hierarchy 1.3 Volts or X. 4. Low Voltage . The columns are: Tuple Code Name Description First Pub CardBus 16-bit PC Card all MEM CFG MFC 5 Volt Key Low Volt Key notes applying to 16-bit PC Cards in general Ñ NA here applies also to all other 16-bit PC Card columns. First Published . the name which uniquely identifies the tuple. The Basic Compatibility Layer Ñ Fundamental information about the card's physical devices and configurations.notes for 16-bit PC Cards which operate at 3. a brief statement of the tuple's intended use.4. or per region/partition definition.0 2 Ñ first published PCMCIA 2.OVERVIEW 2.16-bit PC Cards having configuration and status registers.0 / JEIDA 4.notes for Multiple Function 16-bit PC Cards.1 3 Ñ first published PCMCIA 2. The Data Recording Format Layer Ñ Specifies how data on a card which is used for data storage is organized at the lowest level.

November 1995 10 Ñ first published PC Card Standard March 1997 11 Ñ first published PC Card Standard February 1999 12 Ñ mandatory for cards with >64 Mbytes of Common Memory © 1999 PCMCIA/JEIDA 11 .METAFORMAT SPECIFICATION 9 Ñ first published PC Card Standard.

4.S NA 7 7. M.4. 1 12 © 1999 PCMCIA/JEIDA . JEDEC programming information for Common Memory.3 5 5. Attribute Memory device information. 4 5. Device geometry information for Attribute Memory devices.S 5.S S 5.3.S NA NA R. 1 1 9 1 1 1 4 4 1 1 NA NA M.S 5.S S S 5 5 12 7 7 S S M.4. Device geometry information for Common Memory devices. 4 M. No-link to Common Memory. S M. Null tuple . 4 R. 4 Basic Compatibility Tuples 16H 01H 17H 1DH 1CH 1EH 1FH 09H 22H 21H 19H 18H 20H CISTPL_ALTSTR CISTPL_DEVICE CISTPL_DEVICE_A CISTPL_DEVICE_OA CISTPL_DEVICE_OC CISTPL_DEVICEGEO CISTPL_DEVICEGEO_A CISTPL_EXTDEVICE CISTPL_FUNCE CISTPL_FUNCID CISTPL_JEDEC_A CISTPL_JEDEC_C CISTPL_MANFID Alternate-language-string. Other operating conditions device information for Common Memory. Indirect Access PC Card Memory Link-target-control.4.4.3 R. Longlink to Attribute Memory. JEDEC programming information for Attribute Memory. 4 S M.ignore.OVERVIEW Table 2-5 Tuple Summary Table 16-bit PC Card Tuple Tuple Name Code Description 1st Pub Card Bus PC Card all M E M C F G M F C 5 Low Volt Volt Key Key Layer 1: Basic Compatibility Tuples Control Tuples 10H FFH 03H 13H 11H 12H 02H 06H 14H 00H CISTPL_CHECKSUM CISTPL_END CISTPL_INDIRECT CISTPL_LINKTARGET CISTPL_LONGLINK_A CISTPL_LONGLINK_C CISTPL_LONGLINK_CB CISTPL_LONGLINK_MFC CISTPL_NO_LINK CISTPL_NULL Checksum control. 1 1 1 2 2 3 3 11 3 3 1 1 3 NA NA NA M. Longlink to Common Memory. Function class identification. 3 S S S S NA S S M. S 15H CISTPL_VERS_1 Level 1 version/product-information. Longlink to function specific chain(s) on a Multiple Function PC Card. 6 M. Longlink to next chain on a CardBus PC Card. The end-of-chain tuple. Manufacturer Identification string. Common Memory device information.6 8 8 5 M. Extended Common Memory device information Function Extensions.S M. Other operating conditions device information for Attribute Memory.S R.S NA 5.4.

METAFORMAT SPECIFICATION Table 2-5 Tuple Summary Table .3. Level-2 version tuple. Reserved for future Layer 4 tuples.S NA 5.S NA NA S NA S R. M.S Layer 4: System-Specific Standard Tuples 90H CISTPL_SPCL Special Purpose Vendor unique tuples 4 1 80Háá8FH Available Tuple Codes 0AHáá0FH 24Háá3FH 48Háá7FH 91HááFEH Reserved for future Layer 1 tuples.S S R. Software interleaving. Reserved for future Layer 3 tuples.3 Layer 3: Data Organization Tuples 46H CISTPL_ORG Partition organization. M.4.4 NA R.4 Layer 2: Data Recording Format Tuples Card Information Tuples 45 H 44H 40H CISTPL_BATTERY CISTPL_DATE CISTPL_VERS_2 Battery replacement date.4. © 1999 PCMCIA/JEIDA 13 .4 M.Continued Tuple Code Tuple Name Description 1st Pub Card Bus PC Card all M E M 16-bit PC Card C F G M F C 5 Low Volt Volt Key Key Layer 1: Basic Compatibility Tuples Configuration Tuples 07H 1BH 05H 1AH 04H 08H CISTPL_BAR CISTPL_CFTABLE_ENTRY CISTPL_CFTABLE_ENTRY_CB CISTPL_CONFIG CISTPL_CONFIG_CB CISTPL_PWR_MGMNT Base Address Register definition tuple for a CardBus PC Card. 1 1 1 S S S S S S Data Recording Format Tuples 43H 41H 47H 42H 23H CISTPL_BYTEORDER CISTPL_FORMAT CISTPL_FORMAT_A CISTPL_GEOMETRY CISTPL_SWIL Byte ordering for disk-like partitions.4 M.S 5. Card initialization date. Data recording format for Common Memory Data recording format for Attribute Memory Partition geometry. 1 5.S 5. Configuration tuple for a CardBus PC Card function.4 NA M. Reserved for future Layer 2 tuples. Function state save/restore definition. Configuration tuple for a 16-bit PC Card. A Configuration-Table-Entry for a CardBus PC Card function.S S S 5. 1 1 4 1 3 S 5. 4 2 4 4 4 10 M.S 5.3. A Configuration-Table-Entry.S NA M.

Longlink to Attribute Memory. Device geometry information for Common Memory devices. No-link to Common Memory. Other operating conditions device information for Common Memory. Data recording format for Common Memory Layer 2: Card Information Layer 2: Data Recording Format Layer 1: Control Layer 1: Control Layer 1: Control Layer 1: Control Layer 1: Control Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Configuration Layer 1: Configuration Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 1: Basic Compatibility Layer 2: Data Recording Format Metaformat Layer Layer 1: Control Layer 1: Basic Compatibility Layer 1: Control Layer 1: Control Layer 1: Configuration Layer 1: Configuration Layer 1: Control Layer 1: Configuration Layer 1: Configuration Layer 1: Basic Compatibility 14 © 1999 PCMCIA/JEIDA .OVERVIEW Table 2-6 Tuple Summary Table (Numerically by Tuple Code) Code 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AHáá0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24Háá3FH 40H 41H CISTPL_VERS_2 CISTPL_FORMAT CISTPL_CHECKSUM CISTPL_LONGLINK_A CISTPL_LONGLINK_C CISTPL_LINKTARGET CISTPL_NO_LINK CISTPL_VERS_1 CISTPL_ALTSTR CISTPL_DEVICE_A CISTPL_JEDEC_C CISTPL_JEDEC_A CISTPL_CONFIG CISTPL_CFTABLE_ENTRY CISTPL_DEVICE_OC CISTPL_DEVICE_OA CISTPL_DEVICEGEO CISTPL_DEVICEGEO_A CISTPL_MANFID CISTPL_FUNCID CISTPL_FUNCE CISTPL_SWIL Name CISTPL_NULL CISTPL_DEVICE CISTPL_LONGLINK_CB CISTPL_INDIRECT CISTPL_CONFIG_CB CISTPL_CFTABLE_ENTRY_CB CISTPL_LONGLINK_MFC CISTPL_BAR CISTPL_PWR_MGMNT CISTPL_EXTDEVICE Description Null tuple . Indirect Access PC Card Memory. Link-target-control. Extended Common Memory device information Reserved for future Layer 1 tuples. Function Extensions. Attribute Memory device information. Longlink to next chain on a CardBus PC Card.ignore. Function state save/restore definition. JEDEC programming information for Common Memory. Base Address Register definition tuple for a CardBus PC Card. Configuration tuple for a 16-bit PC Card. Manufacturer Identification string. Level-2 version tuple. Checksum control. Function class identification. Reserved for future Layer 2 tuples. Configuration tuple for a CardBus PC Card function. Software interleaving. Device geometry information for Attribute Memory devices. Longlink to Common Memory. Longlink to next chain on a Multiple Function card. Level 1 version/product-information. Common Memory device information. A Configuration-Table-Entry. Other operating conditions device information for Attribute Memory. A Configuration-Table-Entry for a CardBus PC Card function. JEDEC programming information for Attribute Memory. Alternate-language-string.

In the absence of other information. Byte ordering for disk-like partitions. Card initialization date.5. a system will not be able to interpret all possible vendor-specific fields or code values. Vendor-specific codes are encoding values reserved to represent non-standard values in standard fields. In general. standard software must interpret vendorspecific codes as meaning Òthe information in this field is not specified. © 1999 PCMCIA/JEIDA 15 . the system must refuse to perform any operation that requires the information encoded in that field. Battery replacement date.Ó The card-manufacturer field in the CIS gives (knowledgeable) system software enough information to interpret vendor-specific fields and code values in the card Physical-Description tuples. Similarly. Layer 1: Control Metaformat Layer Layer 2: Data Recording Format Layer 2: Data Recording Format Layer 2: Card Information Layer 2: Card Information Layer 3: Data Organization Layer 2: Data Recording Format Layer 4: System-Specific Standard Layer 4: System-Specific Standard 2. These fields have no meaning to the standard software. If a standard field contains an unrecognized vendor-specific code. Data recording format for Attribute Memory Vendor unique tuples Special Purpose Reserved for future Layer 4 tuples.2 System Rejection of Unsupported Cards This standard requires the following behavior when a system encounters an unrecognized vendorspecific field: · If the unrecognized field itself is vendor-specific. The end-of-chain tuple.METAFORMAT SPECIFICATION Tuple Summary Table (Numerically by Tuple Code) .5 Special Considerations 2.1 Vendor-Specific Information Vendor-specific information allows card and software vendors to implement proprietary functions while remaining within the general framework of this Standard. the OEM and INFO fields in the CISTPL_VERS_2 tuple give (knowledgeable) system software enough information to interpret vendor-specific fields and code values in the card LogicalFormat tuples. Partition organization. 2. Vendor-specific information is of two kinds: · · Vendor-specific fields are areas reserved in the data structures for free use by vendors. the system shall ignore that field.5.continued Code 42H 43H 44H 45 H 46H 47H 80Háá8FH 90H 90HááFEH FFH CISTPL_END CISTPL_SPCL Name CISTPL_GEOMETRY CISTPL_BYTEORDER CISTPL_DATE CISTPL_BATTERY CISTPL_ORG CISTPL_FORMAT_A Description Partition geometry.

.

The CIS on 16-bit PC Cards must start at address zero of the card's Attribute Memory space.) 3. (See also the Electrical Specification.METAFORMAT SPECIFICATION 3 . © 1999 PCMCIA/JEIDA 17 . B A S I C C O M P AT I B I L I T Y ( L AY E R 1 ) This layer is the cornerstone of the Standard.1 Control Tuples Multiple instances of a tuple are allowed unless otherwise specified. All PC Cards shall have at least a rudimentary Card Information Structure. Each function of a CardBus PC Card has a CIS Pointer field in configuration space which points to a CISTPL_LINKTARGET tuple which begins the CIS for that function.

Then. the checksum is calculated in the obvious way. Negative values indicate locations prior to the checksum tuple. ignoring the odd bytes. Relative addressing is used to make the CIS. position independent. the CIS can contain one or more checksum tuples. If the tuple appears in the Attribute Memory space of a 16-bit PC Card. the algebraic sum is formed of the even bytes in the address range [i. To form the target address. positive values indicate locations after the checksum tuple. 2-byte integer. Again. The number is expressed as an unsigned. The contents of TPLCKS_ADDR (as a signed integer) are added to the base address of the tuple. The length of the block of CIS memory to be checked. The result must match the value stored in byte 6 of the checksum tuple. The exact interpretation depends on the address space containing the tuple. TPLCKS_ADDR TPLCKS_LEN TPLCKS_CS Offset to region to be checksummed. Starting at the target address. yielding the target address. The checksum algorithm is a straight modulo-256 sum. If the tuple appears in the Common Memory space of a 16-bit PC Card or in any of the spaces of a CardBus PC Card. 2 * offset is added to the base byte target address of the tuple. 2-byte integer. The checksum tuple can only validate memory in its own address space. TPLCKS_LEN contains the number of bytes to be checksummed. Length of region to be checksummed. The checksum of the region.e. of the region to be checksummed. Then. Table 3-1 CISTPL_CHECKSUM: Checksum Tuple Byte 0 1 2áá3 4áá5 6 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_CHECKSUM (10H) TPL_LINK Link to next tuple (at least 5). The low-order 8-bits of this sum is then compared to the value stored in TPLCKS_CS. the algebraic sum is calculated of all the bytes included in the range. as a whole.BASIC COMPATIBILITY (LAYER 1) 3. The address is a signed. the low-order 8-bits of this sum are compared to the value stored in TPLCKS_CS. relative to the start address of this tuple. and The expected checksum. the checksum operation is a bit more complicated. the data structures are recorded in such a way as to minimize the differences between Attribute space representation and Common Memory representation. This tuple has three fields: · · · The relative address of the block of CIS memory to be checked. stored with LSB first. target + 2 * length-1].1 CISTPL_CHECKSUM: The Checksum Tuple For additional reliability. TPLCKS_ADDR contains the offset. 18 © 1999 PCMCIA/JEIDA . target. If identical. the region of tuple memory covered by the checksum passes the checksum test. The checksum is calculated by summing the bytes of the selected region using modulo 256. given with LSB first..1.

If processing a tuple chain (other than the primary CIS tuple chain of a 16-bit PC Card). and neither a longlink nor a no-link tuple were seen in this chain. then continue tuple processing as if a longlink to address 0 of Common Memory space were encountered. then no tuples remain to be processed. Table 3-2 CISTPL_END: End of Chain Tuple Byte 0 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_END (FFH): end of this tuple chain. Upon encountering this tuple.1. It has a non-standard form and consists solely of the code byte. no tuples remain to be processed. and no longlink tuple was seen in this chain. · · · If a longlink tuple was encountered previously in this chain. system software shall take one of the following actions. All CardBus PC Card tuple chains are required to be terminated with a CISTPL_END tuple. and a CISTPL_NO_LINK tuple was encountered previously in this chain. For validation of the implied longlink to Common Memory.2 CISTPL_END: The End Of Chain Tuple The end of chain tuple marks the end of a tuple chain. If processing the primary CIS tuple chain of a 16-bit PC Card (the chain starting at address 0 in Attribute Memory space). No other method of terminating a tuple chain is permissible for CardBus PC Cards.METAFORMAT SPECIFICATION 3. · © 1999 PCMCIA/JEIDA 19 . the tuple chain in Common Memory must begin with a valid CISTPL_LINKTARGET tuple. continue tuple processing at the location specified in the longlink tuple. as with an explicit CISTPL_LONGLINK_C tuple. If processing the primary CIS tuple chain of a 16-bit PC Card (the chain starting at address 0 in Attribute Memory space).

) When processing software encounters this tuple in either Attribute or Common Memory it shall assume the presence of an additional chain beginning at address zero (0) of either the indirect Attribute or the indirect Common Memory space. This tuple chain shall appear at most once in a Card Information Structure and always in a tuple chain present in direct accessed Attribute or Common Memory space.3 CISTPL_INDIRECT: Indirect Access PC Card Memory 16-bit PC Cards providing indirect access to memory spaces through registers placed in Common Memory shall indicate the presence of these registers with this tuple. All tuple chains in indirect spaces begin with CISTPL_LINKTARGET tuples. (See the Electrical Specification.BASIC COMPATIBILITY (LAYER 1) 3.1. Tuple processing in the indirect spaces follows processing of all tuples in the direct spaces. Note: The body of this tuple is always empty. Table 3-3: CISTPL_INDIRECT: Indirect Access PC Card Memory Byte 0 1 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_INDIRECT (03H) TPL_LINK Link to next tuple (may be zero). 20 © 1999 PCMCIA/JEIDA .

TPLTG_TAG ÒCÓ (43H) ÒIÓ (49H) ÒSÓ (53H) © 1999 PCMCIA/JEIDA 21 . This tuple must be at the beginning of every tuple chain present on a CardBus PC Card and the beginning of any secondary chain(s) on a 16-bit PC Card. Table 3-4 CISTPL_LINKTARGET: Link Target Tuple Byte 0 1 2 3 4 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_LINKTARGET (13H) TPL_LINK Link to next tuple (at least 3).4 CISTPL_LINKTARGET: The LinkTarget Tuple The linktarget tuple is used for robustness. It is recommended that the link field of the link target point to the next byte after the CISTPL_LINKTARGET tuple. It is recommended that 16-bit PC Cards using a low voltage key begin their primary CIS chain with this tuple. Processing software is required to check that the linktarget tuple is correct before deciding to process the tuple chain at the new target address. Every longlink tuple must point to a valid linktarget tuple.1.METAFORMAT SPECIFICATION 3. The linktarget tuple has one fieldÑ the string ÒCISÓ.

_C.5 CISTPL_LONGLINK_A. The TPLL_ADDR field of a CISTPL_LONGLINK_A tuple is interpreted in the same manner as its TPL_LINK field. WA R N IN G The 16-bit PC Card longlink tuples (_A. The target tuple chain may be in Attribute Memory or Common Memory space. Software shall verify that the longlink tuple points to a linktarget tuple before processing the target chain. Note: A given tuple chain shall contain at most one longlink tuple (_A. 22 © 1999 PCMCIA/JEIDA . For example. To compute the address of the linktarget in the cardÕs Attribute Memory space. CISTPL_LONGLINK_C indicates Common Memory space. CISTPL_LONGLINK_C: The 16-bit PC Card LongLink Tuples A given tuple chain for a 16-bit PC Card shall contain at most one longlink tuple (_A. The tuple code byte selects the new address space. Table 3-5 CISTPL_LONGLINK_A and CISTPL_LONGLINK_C: 16-bit PC Card LongLink Tuples Byte 0 1 2áá5 7 TPL_CODE 6 5 4 3 2 1 0 LongLink tuple code (CISTPL_LONGLINK_A. and must never be used by. _C and _MFC) are not applicable to.1. as indicated by the tuple code.BASIC COMPATIBILITY (LAYER 1) 3. multiply the value in the TPLL_ADDR field by two. 11H. 12H) TPL_LINK Link to next tuple (at least 4). low-order byte first. stored as an unsigned long. only even bytes in the address range are counted. _CB or _MFC). CISTPL_LONGLINK_A indicates that the target is in Attribute Memory space. A given tuple chain shall contain at most one longlink tuple. it is important that software simply reject target tuple chains that do not begin with a linktarget tuple. TPLL_ADDR Target address. from one tuple chain to another. The longlink tuples are used to jump beyond the limits of the 1-byte link field. _C or _MFC). CardBus PC Cards. The longlink tuple need not appear as the last tuple in a given chain because all remaining tuples in the current chain will be processed before the link is honored. Because a longlink tuple may point to uninitialized RAM. or CISTPL_LONGLINK_C.

_CB or _MFC). An address at which a tuple chain begins will have an 8 byte alignment. The encoding is the same as for the CIS Pointer. if the value is 2. 0 through 2. This tuple may also occur in tuple chains in any of these spaces. are given by the Address Space Offset field.1. (See the Electrical Specification. 7 The offset into the address space indicated by the Address Space Indicator field is given by the 32 bit value where the three low order bits.must begin in device dependent configuration space at or after location 40H. The tuple chain is in the memory address space governed by one of the six Base Address Registers. must be 0 offset within Config Space Address Space Indicator replace with 0s replace with 0s replace with 0s offset within Base Address Register memory space image number offset from image base The Address Space Indicator field indicates in which of this function's address spaces the tuple chain is located. For example. or the expansion ROM. memory space.METAFORMAT SPECIFICATION 3. The encoding for this field is given below: Address Space Indicator field Value 0 1-6 Meaning Tuple chain is in device dependent configuration space. The tuple chain is in the Expansion ROM space.may be in any of the (up to) six (6) spaces. TPLL_ADDR points to a tuple chain in one of the following spaces: · · · configuration space . Table 3-6 CISTPL_LONGLINK_CB: The CardBus PC Card LongLink Tuple Byte 0 1 2áá5 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_LONGLINK_CB (02H) TPL_LINK Link to next tuple (at least 4) TPLL_ADDR Indicates the location of a tuple chain in a function's address space. as well.may be in any of the images. The encoding for this pointer is given below: TPLL_ADDR field DWORD 31 É 28 27 É 8 7 É 3 2 1 0 Address Space Offset Config Space Memory Space Exp ROM Reserved.6 CISTPL_LONGLINK_CB: The CardBus PC Card LongLink Tuple This gives the location of a tuple chain in a function's address space.) Note: A given tuple chain shall contain at most one longlink tuple (_A. Expansion ROM space . Note that this cannot be an I/O space. are zero and the high order bits. 3 through 31. whether device dependent configuration space. _C. Appropriate values for the various spaces are given below: © 1999 PCMCIA/JEIDA 23 . memory space . then the tuple chain is in the memory address space governed by Base Address Register 2.

The value consists of the remaining bytes. 0 £ value £ FFFFFFF8H. The value is the offset of the tuple chain from the base of that image. The image number is in the uppermost nibble of the Address Space Offset.BASIC COMPATIBILITY (LAYER 1) Address Space Offset field Address Space Indicator 0 x. 0 £ image £ FH. Adding this value to the value in the Base Address Register gives the location of the start of the tuple chain. This is the offset into the expansion ROM address space governed by the Expansion ROM Base Register. 7 expansion ROM 24 © 1999 PCMCIA/JEIDA . This is the offset into the memory address space governed by Base Address Register x. The image is the image number used as the location reference for the tuple chain. 1 £ x £ 6 Space Type configuration space memory space Address Space Offset 40H £ value £ F8H. The address in device dependent configuration space at which the tuple chain starts. Adding this offset value plus the starting offset of the image to the value in the Expansion ROM Base Register gives the location of the start of the tuple chain. 0 £ value £ 0FFFFFF8H.

_CB or _MFC). _C.7 CISTPL_LONGLINK_MFC: The Multiple Function 16-bit PC Card Link Tuple This longlink tuple indicates the number of sets of configuration registers on a Multiple Function 16bit PC Card. Table 3-7 CISTPL_LONGLINK_MFC: The Multiple Function 16-bit PC Card Link Tuple Byte 0 1 2 3 4áá7 8 9áá12 13áán 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_LONGLINK_MFC (06H) TPL_LINK Link to next tuple (at least 6. 1 plus 5 bytes per function) TPLMFC_NUM TPLMFC_TAS1 TPLMFC_ADDR1 TPLMFC_TAS2 TPLMFC_ADDR2 Number of sets of configuration registers for individual functions CIS Target address space for first function on the 16-bit PC Card (00 = Attribute. When a TPLMFC_TASn field is 00H. the associated TPLMFC_ADDRn field is interpreted in the same manner as its TPL_LINK field in a tuple placed in Attribute Memory space. stored as an unsigned long.METAFORMAT SPECIFICATION 3. To compute the address of the linktarget in the cardÕs Attribute Memory space. multiply the value in the TPLMFC_ADDRn field by two. © 1999 PCMCIA/JEIDA 25 . low order byte first Additional TPLMFC_TASn and TPLMFC_ADDRn entries for any additional functions on the 16bit PC Card. low order byte first CIS Target address space for second function on the 16-bit PC Card Target address. 01 = Common) Target address. only even bytes in the address range are counted.1. This tuple does not apply to and must never be used by a CardBus PC Card. Note: A given tuple chain shall contain at most one longlink tuple (_A. only the prior fields shall be present. This tuple also describes the location of the each function-specific CIS describing the function provided by a specific set of configuration registers. stored as an unsigned long. indicating a longlink to Attribute Memory space. If there are only two (2) sets of configuration registers.

BASIC COMPATIBILITY (LAYER 1) 3. Table 3-8 CISTPL_NO_LINK: The No-Link Tuple Byte 0 1 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_NO_LINK (14H) TPL_LINK Link to next tuple (may be zero). Note: The body of this tuple is always empty. 26 © 1999 PCMCIA/JEIDA . This assumption can be overridden either by placing an explicit longlink tuple (CISTPL_LONGLINK_A or CISTPL_LONGLINK_C) or a no-link tuple (CISTPL_NO_LINK) in the primary tuple chain. processing software shall assume the presence of a CISTPL_LONGLINK_C tuple to address 0 of Common Memory as part of the primary tuple chain. or a longlink tuple.8 CISTPL_NO_LINK: The No-Link Tuple To save Attribute Memory space on 16-bit PC Cards. A given chain may contain either a no-link tuple. No-link tuples and longlink tuples are mutually exclusive. but not both.1. A given tuple chain shall contain at most one no-link tuple. The primary tuple chain starts at address 0 of Attribute Memory space.

It has a non-standard form and consists solely of the code byte. © 1999 PCMCIA/JEIDA 27 . The next tuple begins at the next byte in sequence.METAFORMAT SPECIFICATION 3.9 CISTPL_NULL: The Null Tuple The null tuple is simply a place holder. Table 3-9 CISTPL_NULL: The Null Tuple Byte 0 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_NULL (00H): ignore this tuple. Note: Software shall ignore these tuples.1.

A special escape sequence denotes the PC Extended ASCII character set. 28 © 1999 PCMCIA/JEIDA .marks end of strings. and A series of strings.BASIC COMPATIBILITY (LAYER 1) 3. Terminated by a NULL (00H). 3. Alternate string tuples contain two kinds of information: · · A code representing the language (an ISO-standard escape sequence). this standard provides alternate string tuples. Tuple codes affected are 15H (CISTPL_VERS_1) and 40H (CISTPL_VERS_2). Indicates which character set is associated with these strings. Strings in the primary tuples are always recorded in ISO 646 IRV code using characters in the range 20Háá7EH. The leading ESCAPE is not recorded.1 CISTPL_ALTSTR: The Alternate Language String Tuple Several tuples contain character strings which are intended to be displayed to the user only under certain circumstances. FFH . Table 3-10 CISTPL_ALTSTR: The Alternate Language String Tuple Byte 0 1 2áá(m-1) 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_ALTSTR (16H) TPL_LINK Link to next tuple (at least p-1). translation for second string in most recent non-ALTSTR tuple. each associates with most recent (previous) ÒNON-ALT STRINGÓ tuple. Some international applications need the ability to store strings for a number of different languages. Rather than having various languages used in the tuples. These strings are to be substituted for the primary strings when operating in a different language environment. Multiple instances of this tuple are allowed. Etc.2.2 Basic Compatibility Tuples Multiple instances of a tuple are NOT allowed unless otherwise specified. Terminated by 00H. TPLALTSTR_ESC ISO-standard escape sequence to select the character set for these strings. Terminated by 00H. máá(n-1) náá(o-1) É p Alternate string 1 Alternate string 2 translation for first string in most recent non-ALTSTR tuple.

CISTPL_DEVICE_A. shall exist to describe the 3. CISTPL_DEVICE_A. The tuples contain: device speed. Table 3-11 CISTPL_DEVICE. as the first non-control tuple in Attribute Memory. CISTPL_DEVICE_OC and CISTPL_DEVICE_OA.3. One or more Other Conditions Tuples.3 volts VCC shall use the Device Info fields in CISTPL_DEVICE and CISTPL_DEVICE_A to describe the characteristics when operating at 5 volts VCC. © 1999 PCMCIA/JEIDA 29 . (See 2.METAFORMAT SPECIFICATION 3. device type. 16-bit PC Cards that operate at both 5 volts VCC and 3. CISTPL_DEVICE.8 16-bit PC Card Tuple Chain Processing). It is recommended that the device information tuple for Attribute Memory. PC Cards with a 5 volt key shall present a device information tuple for Common Memory space.2. See section 3. The code CISTPL_DEVICE_A indicates that this tuple describes Attribute Memory space.2. Whenever both CISTPL_DEVICE and CISTPL_DEVICE_OC tuples are present. CISTPL_DEVICE_A: The 5 volt Device information Tuples Byte 0 1 n 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_DEVICE (01H) or CISTPL_DEVICE_A (17H) TPL_LINK Link to next tuple (at least m-1) Device Info 1 (2 or more bytes) Device Info 2 (2 or more bytes) É m (etc. Null devices are counted in the matching process. This one-to-one correspondence shall also exist between Device Info entries in the CISTPL_DEVICE_A and CISTPL_DEVICE_OA tuple(s).1 Device Info Fields. there must be a one-to-one correspondence between their Device Info entries. or Common Memory.2 CISTPL_DEVICE. CISTPL_DEVICE_A: The 5 volt Device Information Tuples The 5 volt device information tuples contain information about the card's devices. space.3 volts VCC operating characteristics.) Device Info n (2 or more bytes) FFH (marks end of Device Info field) The tuple code CISTPL_DEVICE indicates that this tuple describes Common Memory space. CISTPL_DEVICE. and address space layout information for either Attribute Memory.2. for the Device Info field definition. be provided. device size.

Device ID fields Byte n 7 6 5 4 3 WPS 2 1 Address Space Indicator or Device Speed 0 Device Type Code n+1 Extended Device Speed EXT If Device Speed Code equals 7H. Reserved for future use.2. otherwise omitted.2.1 Size Code 3. Each field is further composed of two variable length byte sequences Ñ the Device ID and the Device Size. Each Device Info field defines the characteristics of a group of addresses in the appropriate memory space.1 Device Info Fields (For Tuples CISTPL_DEVICE.1 Device ID Fields The device ID indicates the device type and the access time for a block of memory. otherwise omitted.1.2. Additional Extended Device Type Code Speed Exponent (n+2)áá(o-1) Additional Extended Device Speed EXT o Extended Device Type EXT (o+1)áá Additional Extended Device Type EXT 30 © 1999 PCMCIA/JEIDA . Device Info fields Byte n n+m 7 Device ID Device Size 6 5 4 3 2 1 0 one or more bytes of Device ID fields one byte indicating the device size # of address units .2.BASIC COMPATIBILITY (LAYER 1) 3. CISTPL_DEVICE_A) The device information tuples are composed of a sequence of Device Info fields. Extended Device Type Code While EXT of previous byte is set. If Device Type Code equals EH. Speed Mantissa While EXT of previous byte is set.

If the devices at offset zero in the 16-bit PC Card's common memory space are intended for function specific use. (See the Electrical Specification. which are not intended to be used as general-purpose memory. the Device Type Code shall be DTYPE_FUNCSPEC.2. communication buffers. the Device Speed field should be set to 0H.1.) 3. Accesses to function-specific address ranges may be configuration dependent Extended type follows. The extended device type. the device is always writable unless the device code is DTYPE_ROM. An Address Space Indicator value of zero (0) is illegal since it would indicates that the device(s) is(are) in CardBus PC Card Configuration Space. Bit 7. is reserved for future use. in which case this address range is never writable. The Address Space Indicator field used here has the same format and interpretation as the field used in the CIS Pointer and the CISTPL_LONGLINK_CB tuple.1. When the WPS bit is reset (0).2 WPS Field The WPS bit indicates whether the Write Protect Switch is in control of the device(s) in this address range. Generally used to designate a hole in the address space. such as memory mapped I/O registers or communications buffers.1.1 Device Type Code Field The Device Type Code field in bits 4 through 7 of byte 0 of the Device ID sequence indicates the device type. If there are no devices in a 16-bit PC Card's common memory space. Reserved EH FH DTYPE_EXTEND Note: Device Type Codes are used to describe only devices which are fixed in their memory address. The end is marked by an extended device type byte with bit 7 reset. 3. if set.1.2.2. Relocatable devices are described by the configuration tuples. Masked ROM One Time Programmable ROM UV EPROM EEPROM Flash EPROM Static RAM Dynamic RAM Reserved Function-specific memory address range.1. indicates that the next byte is also an extended type byte.3 Address Space Indicator Field (CardBus PC Card only) The Address Space Indicator field indicates the memory or Expansion ROM Base Address Register associated with the devices described in the CISTPL_DEVICE_OC tuple. (See 3.6 CISTPL_LONGLINK_CB: The CardBus PC Card LongLink Tuple. the Device Type Code shall be DTYPE_NULL. If used for 16-bit PC Cards.METAFORMAT SPECIFICATION 3. The chain of extended type bytes can continue indefinitely. The following codes are defined: Device Type Code field Code 0 1 2 3 4 5 6 7 8ááCH DH DTYPE_FUNCSPEC Name DTYPE_NULL DTYPE_ROM DTYPE_OTPROM DTYPE_EPROM DTYPE_EEPROM DTYPE_FLASH DTYPE_SRAM DTYPE_DRAM Meaning No device.1.) © 1999 PCMCIA/JEIDA 31 .2. dual-ported memory. Includes memory-mapped I/O registers.2. the Write Protect Switch and WP signal indicate whether or not the device(s) is(are) writable.. if specified.1. not dynamically relocatable devices.2. etc. When the WPS bit is set (1).

1. It extends through (and includes) the first byte with bit 7 reset.BASIC COMPATIBILITY (LAYER 1) 3.2. However.4 Device Speed Field (16-bit PC Card only) If the device speed/type byte is 00H. The meaning of that byte is not presently defined.2. if set. The speed value indicates the external card access time to this address range (See the Electrical Specification.0 host platforms that pre-date the definition of the WAIT# signal. indicates that an additional extended speed byte follows. If the device size information is valid. and up to one or two additional bytes. there is no device at this address. The EXT bit. the string of extended speed bytes may be arbitrarily long. 16-bit PC Cards that support the use of the WAIT# signal shall include the CISTPL_DEVICE_OC tuple to define 5 volt device speed with the WAIT# signal honored. the address range shall be treated as a NULL device. Device Speed Codes Code 0 1 2 3 4 5áá6 7 DSPEED_EXT Name DSPEED_NULL DSPEED_250NS DSPEED_200NS DSPEED_150NS DSPEED_100NS Meaning Use when device type = NULL 250 nsec 200 nsec 150 nsec 100 nsec (Reserved) Use extended speed byte. 32 © 1999 PCMCIA/JEIDA . If the extended speed byte is zero. Note: The values given in the Device Speed fields of CISTPL_DEVICE and CISTPL_DEVICE_A tuples must define the worst case cycle time required by a 16-bit PC Card without the use of the WAIT# signal.0 / JEIDA 4. This is required by PCMCIA 1. Bits 0 through 2.1.) The device speed field contains one of the values in the table below. represent the speed of the devices associated with this part of the address space. then the byte should be ignored.

CISTPL_DEVICE_A) Within the device information tuple fields.5 6. The tuple CISTPL_EXTDEVICE shall indicate the exact divice size when device size exceeds 64 MBytes.0 7.0 1. © 1999 PCMCIA/JEIDA 33 . The indicated size describes the total memory address range of the specified device type.5 3. The device type and speed information encoded for this entry should be ignored. A code of zero indicates 1 unit.5 2.2.0 3.2 The Device Size Byte (For Tuples CISTPL_DEVICE. is the Device Size byte.0 4.0 Exponent part Code 0H 1H 2H 3H 4H 5H 6H 7H Meaning 1 ns 10 ns 100 ns 1 ms 10 ms 100 ms 1 ms 10 ms 3.3 1.5 5.METAFORMAT SPECIFICATION The extended device speed mantissa and exponent specify the speed of the device. If the device size byte is FFH. as follows: Extended Device Speed Codes Mantissa Code 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Meaning Reserved 1.5 4.2.0 5. following the device speed/type information. Device Size Codes Code 0 1 2 3 4 5 6 7 Units 512 bytes 2 KBytes 8 KBytes 32 KBytes 128 KBytes 512 KBytes 2 MBytes Reserved Max Size 16 KBytes 64 KBytes 256 KBytes 1 MByte 4 MBytes 16 MBytes 64 MBytes Reserved Bits 3 through 7 represent the number of address units.0 2. then this entry should be treated as an end marker for the device information tuple.0 8.2 1. and so on.1. a code of 1 indicates 2 units. For a device size > 64 MBytes the device size byte shall indicate a size of 64 MBytes.

must be 0. Other-Conditions-Info field 7 EXT EXT Additional Bytes 6 5 4 3 2 VccUsed 1 0 MWAIT Reserved. There are two condition fields defined Ñ the VccUsed and the MWAIT fields. there must be a one-to-one correspondence between entries in the CISTPL_DEVICE tuple and each CISTPL_DEVICE_OC tuple.1 Other Conditions Info Field The Other-Conditions-Info field is a sequence of one or more bytes each with up to seven condition fields and one extension bit.2.3 CISTPL_DEVICE_OC.3. The condition fields indicate the set of defined conditions which apply to the device information in the tuple. CardBus PC Cards shall use the CSTPL_DEVICE_OC tuple to describe memory space devices.2.2 CISTPL_DEVICE. Bit 7 of each byte is the extension bit which indicates that another byte of conditions follows the present byte. Link to next tuple (m-1. there must be a one-to-one correspondence between entries in the CISTPL_DEVICE_A tuple and each CISTPL_DEVICE_OA tuple. Table 3-12 CISTPL_DEVICE_OC.0 / JEIDA 4. CISTPL_DEVICE_A: The 5 volt Device Information Tuples.) 2 or more bytes FFH (marks end of Device Info fields). CISTPL_DEVICE_OA: The Other Conditions Device information Tuples Byte 0 1 2 n 7 TPL_CODE TPL_LINK Other Conditions Info Device Info 1 Device Info 2 É Device Info n m 6 5 4 3 2 1 0 CISTPL_DEVICE_OC (1CH) and CISTPL_DEVICE_OA (1DH). If a CISTPL_DEVICE_A tuple is present. (See 3. The tuples are identical in format to the device information Common and Attribute Memory tuples except that an Other-Conditions-Info field precedes the first Device Info field.BASIC COMPATIBILITY (LAYER 1) 3. Note that the card is not required to assert the 34 © 1999 PCMCIA/JEIDA . All CISTPL_DEVICE_OA tuples have corresponding entries. All undefined fields are reserved for future standardization and must be zero.2. When the MWAIT field is set (1). the timings given are intended for PCMCIA 2. CISTPL_DEVICE_OA: The Other Conditions Device information Tuples The Other Conditions device information tuples contain information about the card's devices under a set of operating conditions. Null devices are counted in the matching process. All CISTPL_DEVICE_OC tuples have corresponding entries. Each is present only if EXT bit is set in previous byte The MWAIT field is ignored by CardBus PC Cards. 1 or more bytes 2 or more bytes 2 or more bytes (etc. There shall be a one-to-one correspondence between entries of each related tuple that describes operating characteristics. 3.) There may be several CISTPL_DEVICE_OC and CISTPL_DEVICE_OA tuples in the CIS Ñ one to describe the card under each set of alternative operating conditions. 3 or more). If a CISTPL_DEVICE tuple is present.1 and later systems which will observe the WAIT# signal.

is indicated using the CISTPL_DEVICE and CISTPL_DEVICE_A tuples The VccUsed field indicates a VCC voltage at which the PC Card can be operated. A PC Card capable of operating at more than one VCC voltage shall have a separate instance of the Other Conditions tuple. Reserved for CardBus PC Card Y. When the MWAIT field is reset (0). 3. Note that the VccUsed field shall not indicate 5 V VCC operation because this condition. PCMCIA 1.2.1Device Info Fields © 1999 PCMCIA/JEIDA 35 . Reserved for X. for each such operating voltage. shall not use timing data provided in a tuple with the MWAIT field set (1).X volt VCC operation. Host systems which do not support the WAIT# signal.0 / JEIDA 4.0 and earlier. The fields are defined in section 3.1 Device Info Fields (For Tuples CISTPL_DEVICE. VccUsed field Value 00B 01B 10B 11B Meaning 5 volt VCC operation.2.2.3 volt VCC operation. The Device Info fields for the CISTPL_DEVICE_OC and CISTPL_DEVICE_OA tuples have the same definition and format as the CISTPL_DEVICE and CISTPL_DEVICE_A tuples. the timings given represent worst case cycle times and shall be used by host systems which do not support the WAIT# signal.Y volt VCC operation. 3.METAFORMAT SPECIFICATION WAIT# signal during operation. MWAIT reset (0) and 5 V VCC. CISTPL_DEVICE_OC or CISTPL_DEVICE_OA.2. CISTPL_DEVICE_A).

this deals with the fixed architecture of the memory device(s) or subsystem(s). this applies to the entire address range of that device type. The value n = 00H is not allowed. so that a 1:1 correspondence between Device Info and Device Geometry Info fields of the described regions exists. The value n = 00H is not allowed. Value = n.4 CISTPL_DEVICEGEO. While conceptually similar to a DOS disk geometry tuple (CISTPL_GEOMETRY). in CISTPL_DEVICE or CISTPL_DEVICE_OC tuples when the CISTPL_DEVICEGEO tuple is employed. where card architectures employ a multiple of 2(q-1) times interleaving of the entire memory arrays or subsystems with the above characteristics. Value = p. +1 DGTPL_EBS Value = n. (etc. 2 1 0 Value = n. The value n = 00H is not allowed. CISTPL_DEVICE_OA or CISTPL_DEVICE_A. Value = q. where memory array/subsystem's physical memory segments have a minimum read block size of 2(n-1) address increments of DGTPL_BUS-wide accesses.BASIC COMPATIBILITY (LAYER 1) 3. P = 1 where array partitioning at erase block boundaries is allowed. The value p = 00H is not allowed. Accordingly. Non-interleaved cards have values of q = 1. even for devices without any special geometry (e.g. where memory array/subsystem's physical memory segments have a minimum write block size of 2(n-1) address increments of DGTPL_BUS-wide accesses. Flash Memory. including NULL device space. Rather than being specific to a partition within a larger device type. CISTPL_DEVICEGEO_A: Device Geometry Tuples The device geometry info tuple CISTPL_DEVICEGEO is required for certain memory technologies (e. The value q = 00H is not allowed. Device Geometry Info for Device 2. +2 DGTPL_RBS +3 DGTPL_WBS +4 DGTPL_PART +5 DGTPL_HWIL If the Device Geometry Info field is used. The value n = 00H is not allowed. Value = n.g. Bit 7 of 36 © 1999 PCMCIA/JEIDA . the entire six byte entry must be filled out for each entry in the corresponding CISTPL_DEVICE.2. CISTPL_DEVICE_OC. where card interface width = 2 n = 2 for 16-bit PC Cards. each Device Geometry Info entry in the CISTPL_DEVICEGEO tuple must have a corresponding Device Info entry. Device Geometry Info for Device 1. where k = the number of devices described. RAM). n = 3 for CardBus PC Cards. This one-to-one relationship also applies to device geometry entries in the CISTPL_DEVICEGEO_A tuple and device info entries in CISTPL_DEVICE_A or CISTPL_DEVICE_OA tuples.) áá((6 * k)+1) Device Geometry Info for Device k. where memory array/subsystem's physical memory segments can have partitions subdividing the arrays in minimum granularity of 2 (p-1) number of erase blocks. ROM. The table length is 6 * k + 2 bytes. Table 3-13 CISTPL_DEVICEGEO and CISTPL_DEVICEGEO_A: Device Geometry Tuples Byte 0 1 2áá7 8áá13 7 TPL_CODE TPL_LINK 6 5 4 3 2 1 0 CISTPL_DEVICEGEO (1EH) and CISTPL_DEVICEGEO_A (1FH) Link to next tuple (at least 6 * k). it is not a format dependent property. Device Geometry Info field Byte +0 7 DGTPL_BUS 6 5 4 (n-1) 3 bytes. where memory array/subsystem's physical memory segments have a minimum erase block size of 2(n-1) address increments of DGTPL_BUS-wide accesses. EEPROM) or card integrated memory subsystems.

It has no special partitioning requirements (DGTPL_PART: p = 1). It requires partitioning in erase block groups of four (DGTPL_PART: p = 3). Internal components erase in blocks that are 64 KBytes.. respectively. and DGTPL_WBS (address increment or bus operation based values) are multiplicative of the DGTPL_BUS entry (denoting bus width) to define the noninterleaved physical memory erase. system resident memory arrays using the same file system).. = = = = 2 x 4096 2x 2x x Interleave x1 1 256 x1 x1 x1 = 8192 bytes = 2 bytes = 512 bytes = 8192 bytes ERASE Geometry A particular four layer interleaved (DGTPL_HWIL: q = 3) 16-bit PC Card based memory array (DGTPL_BUS: n = 2) employs a new type of word wide flash memory device with built in byte/word mode operation.768 2x 2x 1 1 x Interleave x4 x4 x4 x4 = 262. Examples: 1.2) is multiplicative of the resulting non-interleaved erase. DGTPL_PART is a special partitioning info field based on physically distinct segments of the memory array(s) such that data are not affected by read/write/erase operations in adjacent partitions. The product of these three geometry info layers yields the resulting card level minimum physical block geometry. The resulting physical geometry is: Bus x Block ERASE Geometry READ Geometry WRITE Geometry PARTITION Boundary 2. A particular non-interleaved (DGTPL_HWIL: q = 1) 16-bit PC Card based memory array (DGTPL_BUS: n = 2) employs a new EEPROM type of byte-wide memory device which erases in 4K bytes (DGTPL_EBS: n = 13) and writes in 256 byte pages (DGTPL_WBS: n = 9). and write geometry.144 bytes = 8 bytes = 8 bytes = 1.g. The resulting physical geometry is: Bus x Block ERASE Geometry READ Geometry WRITE Geometry PARTITION Boundary = = = = 2 x 32. It is multiplicative of the resulting erase geometry (only) and defines the minimum partition size allowed for that card. read. Subsystems using internal bus widths less than 8 bits wide must employ low-level drivers which accept 8 bit minimum data from the higher levels. is reserved for future use and must be reset (0). The purpose of this entry is to accommodate possible wider width cards of the future and/or to allow file systems to use this tuple structure in non-card environments (e. and write block sizes in bytes. the last (sixth) byte of each detailed Device Geometry Info field.e. The DGTPL_BUS tuple has a value of n = 2 for 16 bit bus width of 16-bit PC Cards regardless of word or byte wide operation (byte wide operation is logically low and high byte sequencing of a fundamental 16 bit wide card internal bus) and n = 3 for the 32 bit bus width of CardBus PC Cards. or 32 KBytes times their 16 bit bus (DGTPL_EBS: n = 16) and write in single words (DGTPL_WBS: n = 1). ÒbanksÓ of) memory arrays or subsystems (where DGTPL_HWIL . read. The DGTPL_EBS. DGTPL_RBS. When set (1) this bit indicates that an extended device geometry information structure follows. there are no special partitioning requirements). DGTPL_PART: p = 1 where array partitioning at erase block boundaries is allowed (i.e. Note: The device geometry info is normalized to byte equivalent geometry to simplify the context for the O/S or driver level software which utilizes it. The DGTPL_HWIL value for cards employing hardware interleaved (i.024 KBytes ERASE Geometry © 1999 PCMCIA/JEIDA 37 .METAFORMAT SPECIFICATION DGTPL_HWIL.

All undefined fields in the Memory Paging-Info byte sequence are reserved for future standardization and shall be zero. tuple CISTPL_EXTDEVICE should present the same Device ID field information in the same sequential order as what the tuple CISTPL_DEVICE and/or tuple CISTPL_DEVICE_OC provides. The tuple (illustrated in Table 3-14) is primarily intended to be used with PC Cards containing more than 64 MBytes of common memory. When this tuple is present and recognized by the system software. the Other Conditions Info part of the CISTPL_DEVICE_OC tuple shall still apply. Table 3-14 CISTPL_EXTDEVICE: The Extended Common Memory Device information Tuples Byte 0 1 2 n 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_EXTDEVICE (09H) TPL_LINK Link to next tuple (at least m-1) Memory Paging Info (1 or more bytes) Device Info 1 (2 or more bytes) Device Info 2 (2 or more bytes) É m (etc.2. Even though the CISTPL_EXTDEVICE tuple overrides the Device Info parts of a CISTPL_DEVICE_OC tuple. tuples CISTPL_DEVICE and CISTPL_DEVICE_OC should be encoded to describe the first (non-extended) 64 MByte region of common memory for a PC Card. however. Other bytes in the byte sequence are undefined. If a host system supported the CISTPL_EXTDEVICE tuple. be able to access the 1st 64 MBytes of the cardÕs memory. the data provided by the tuple shall override the Device Info field data presented by the CISTPL_DEVICE and CISTPL_DEVICE_OC tuples. To maintain backward compatibility as much as possible with host systems which do not recognize the CISTPL_EXTDEVICE tuple. device type. address extension register location and memory page size information for Common Memory space. Each byte consists of a set of fields with up to seven bits of paging information and one extension bit. The fields indicate defined paging conditions which apply to the device information in the tuple. device size. For each device type the CISTPL_DEVICE and/or CISTPL_DEVICE_OC tuple(s) would encode a maximum device size of 64 MBytes. the host system would process the information presented by the CISTPL_EXTDEVICE tuple and ignore the information contained in the CISTPL_DEVICE and CISTPL_DEVICE_OC tuples.1 Memory Paging Info Field The Memory Paging-Info field is a sequence of one or more bytes.2.BASIC COMPATIBILITY (LAYER 1) 3. 38 © 1999 PCMCIA/JEIDA . Then. address space layout.5 CISTPL_EXTDEVICE: The Extended Common Memory Device Information Tuple The extended common memory device information tuple contains information about the card's devices which reside in common memory. The CISTPL_EXTDEVICE tuple contains device speed. all host systems would recognize the CISTPL_DEVICE and/or CISTPL_DEVICE_OC tuple(s) and. Bit 7 of each byte is defined as the extension bit which indicates that another byte of paging information follows the present byte. For the first byte of the byte sequence there are 3 paging condition fields Ñ the Page Size. address extension size.) Device Info n (2 or more bytes) FFH (marks end of Device Info field) 3. Page Address Location and the Number of Address Extension Bits fields.5. using the tuple information.

while for a 16 MByte page size Address Extension Registers 0.1 field indicates the actual number of bits in the address extension provided by the register(s).METAFORMAT SPECIFICATION The 3 fields for the single defined byte are defined as follows: Memory-Paging-Info field 7 EXT EXT 6 5 4 3 2 Page Address Location 1 Page Size 0 Number of Address Extension Bits . The Memory Paging-Info fieldÕs Page Size and Page Address Location sub-fields indicate the page size and Function Configuration Registers as follows: Memory-Paging-Info Field Bits Page Address Location Bit 2* 0 1 Page Size Description Selected Page Size 64 MBytes 64 MBytes 32 MBytes 16 MBytes Reserved Function Configuration Register(s) providing Address Extension Address Extension Register 0 Configuration Option Register Address Extension Registers 0 and 1 Address Extension Registers 0. Each Device Info field defines the characteristics of a group of addresses in the appropriate memory space. 3.5.1 Additional Bytes Each is present only if EXT bit is set in previous byte The Page Size field indicates the page size for Common Memory. The Page Address Location bit applies only for 64 MByte page size and denotes which Function Configuration Register provides a set of address extension bits for accessing > 64 MBytes of Common Memory. © 1999 PCMCIA/JEIDA 39 . The Page Address Location bit indicates the choice of either the Configuration Option Register or Address Extension Register 0 as the source for the address extension bits. The number of actual address extension bits is represented as a binary value equal to the number of actual address extension bits minus 1.2 Device Info fields (for tuple CISTPL_EXTDEVICE) The device information tuples are composed of a sequence of Device Info fields. 2 and 3 contain the address extension bits to address a 16 MByte memory page. Each field is further composed of two variable length byte sequences Ñ the Device ID and the Device Size.2. 1. 2 and 3 ¾ Bit 1 0 0 0 1 1 * Bit 0 0 0 1 0 1 Bit 2 is defined only for the condition where bits 1 and 0 both equal `0Õ. For the Function Configuration Register(s) providing an address extension the Number of Address Extension Bits . 0 would imply that an address extension consisted a single address extension bit. thus. For all other conditions bit 2 is reserved and must = `0Õ. For a 32 MByte page size Address Extension Registers 0 and 1 provide the address extension bits for addressing a 32 MByte memory page. 1.

the device size information depends on whether or not the amount of common memory for the device being described is greater than 64 MBytes. 3.2.BASIC COMPATIBILITY (LAYER 1) For a device memory size £ 64 MBytes the following definition holds: Device Info fields Byte n n+m 7 Device ID Device Size 6 5 4 3 2 1 0 one or more bytes of Device ID fields one byte indicating the device size for a £ 64 MByte device memory space # of address units .3 of the Device Size byte) and the Size Code field (bits 2 . the # of Address Units .5.0 of the Device Size byte). 3. is not extender byte) and that no further device size bytes follow.2.5. However. following the device speed/type information. ExtBytes = 1 signifies that 2 Device Extended Size bytes and then the Device Final Size byte follow extender byte.1 Device ID Fields. For £ 64 MByte memory device size the # of Address Units . The indicated size describes the total memory address range of the device type specified with the device speed/type information.2.2.4. 40 © 1999 PCMCIA/JEIDA . 3 or 4 bytes contain the device size information.1 Size Code 3. n+m+1 P7 P6 P5 P4 P3 P2 P1 P0 Device Extended Size byte #1 n+m+2 P15 P14 P13 Bits 0 through 7 of P (`64 MByte pageÕ multiplier lower byte) P12 P11 P10 P9 P8 Device Extended Size byte #2 n + m + (s-1) Device Final Size Bits 8 through 15 of P (`64 MByte pageÕ multiplier upper byte) Last of three or four bytes (s). for a > 64 MByte device memory size.2. A code of zero indicates 1 unit. is the Device Size byte.2 The Device Size Byte(s) (For Tuple CISTPL_EXTDEVICE) As outlined in Section 3. The Device Size byte consists of 2 fields.2. For a £ 64 MByte device memory size a single Device Size Byte provides the information.1 Size Code For a device memory size > 64 MBytes the following definition holds: Device Info fields Byte n n+m 7 Device ID Device Size Extender 0 0 0 6 5 4 3 2 1 0 one or more (m) bytes of Device ID fields Indicates > 64 MBytes of device memory space 0 ExtBytes 1 1 1 ExtBytes = 0 signifies that 1 Device Extended Size byte and then the Device Final Size byte follow extender byte.1 Device Memory Size £ 64 MBytes Within the device information tuple fields.2. a code of 1 indicates 2 units.2.2.1 Device ID fields Same as Section 3.1 field (bits 7 .5. This byte codes an amount of device memory up to a maximum of 64 MBytes..2.e. All other bit combinations of bits 7 through 0 indicate that this byte is the single Device Size byte defining a £ 64 MByte device memory space (i.1 field represents the number of memory units specified by the Size Code field. and so on (for device size codes 0 through 6).1. # of address units .

The Device Size Extender byte contains the ExtBytes field which is not defined for the Device Size byte. Device Size Extender Byte Device Extended Size Byte 1 Device Extended Size Byte 2 (for device memory size > 16 Gigabytes) and Device Final Size Byte © 1999 PCMCIA/JEIDA 41 . If the Device Size byte is FFH. The size definition which follows allows for PC Cards with more than 4 Gigabytes of common memory. 2.2. For a code 7 the Device Size byte is redefined to be the Device Size Extender byte.2. is a sequence of bytes for defining a > 64 MByte device memory size. following the device speed/type information. The byte sequence describes the total memory address range of the device type specified with the device speed/type information.METAFORMAT SPECIFICATION When the device size code = 7 (and reserved bits 7 through 4 of the Device Size byte = 0). 3. The Size Code field ranges in value from 0 to 7 with codes 0 to 6 used to determine £ 64 MByte device memory size The Size Code field is defined as follows: Device Size Codes Code 0 1 2 3 4 5 6 7* ExtBytes = 0 Identifies byte as Device Size Extender byte for > 64 MByte device memory size and indicates that 1 Device Extended Size byte and the Device Final Size byte follow next in the tuple sequence (see following section) Identifies byte as Device Size Extender byte for > 64 MByte device memory size and indicates that 2 Device Extended Size bytes and the Device Final Size byte follow next in the tuple sequence (see following section) Reserved (= 0) Units 512 bytes 2 Kbytes 8 Kbytes 32 Kbytes 128 Kbytes 512 Kbytes 2 MBytes Max Size 16 Kbytes 64 Kbytes 256 Kbytes 1 MByte 4 MBytes 16 Mbytes 64 Mbytes ExtBytes = 1 Device Size [7::4] * Code 7 is defined for a memory device size > 64 MBytes. the larger memory provisions can be utilized with Memory Technology Driver (MTD) software which bypasses Card and Socket Services software to directly drive a PC Card. For > 64 MByte device memory spaces the device size information is contained in the following 4 bytes: 1. 3.2 Device Memory Size > 64 MBytes Card and Socket Services software support is specified for PC Card common memory spaces not exceeding 4 Gigabytes. The device type and speed information encoded for this entry should be ignored.2. Within the device information tuple fields. then this entry should be treated as an end marker for the device information tuple.5. 4. the first of a sequence of bytes defining > 64 MByte device size. then a > 64 MByte device memory size is indicated (see following section).

The device type and speed information encoded for this entry should be ignored. When the single-bit ExtBytes field (bit 3) of the Device Size Extender byte = 0. The Device Final Size byte which follows the Device Extended Size byte is formatted identical to the single Device Size Byte used for < 64 MByte device memory sizes. 64 MBytes. The Device Final Size byte should not contain a device size code of 7 (where the device size codes are defined in the table of the previous section).BASIC COMPATIBILITY (LAYER 1) Bits 0 . Device memory size is calculated using the single Device Extended Size byte and the Device Final Size byte as follows: (P )* 64 MBytes + Device Final Size where .2 of the Device Size Extender byte must all = 1 in order to indicate device size extension beyond 64 MBytes. then they represent the Size Code field for a device memory size < 64 MBytes (see the previous section). Regardless of the device size stipulated by the Device Extended Size byte(s) immediately preceding the Device Final Size byte. obtained with a device size code of 6. the Device Size Extender byte indicates that 2 Device Extended Size bytes and then a Device Final Size byte follow next in line after the Device Size Extender byte.4.2. When the single-bit ExtBytes field (bit 3) of the Device Size Extender byte = 1. Device memory size is calculated using the 2 Device Extended Size bytes and the Device Final Size byte as follows: (P )* 64 MBytes + Device Final Size where: P = the binary-encoded value provided by the Device Extended Size bytes and Device Final Size = the device size coded in the Device Final Size byte. 42 © 1999 PCMCIA/JEIDA . is the maximum value which can be indicated for Device Final Size. Thus. If bits 0 -2 do not all = 1. P = the binary-encoded value provided by the Device Extended Size byte and Device Final Size = the device size coded in the Device Final Size byte. If the Device Size Extender byte is FFH. Thus. if the Device Final Size byte is FFH. obtained with a device size code of 6. then this entry should be treated as an end marker for the device information tuple. The device type and speed information encoded for this entry should be ignored. 64 MBytes. a single Device Extended Size byte and then a Device Final Size byte follow next in line after the Device Size Extender byte. The Device Final Size byte which follows the 2 Device Extended Size bytes is formatted identical to the single Device Size Byte used for < 64 MByte device memory sizes. then this entry should be treated as an end marker for the device information tuple. The order and format of the 2 Device Extended Size bytes are illustrated in section 3. is the maximum value which can be indicated for Device Final Size. The Device Final Size byte should not contain a device size code of 7 (where the device size codes are defined in the table of the previous section).

/byte[12]: /*device final size byte ¾ units/code Ð 64 MBytes*/ (1Fh<<3) | 6.2. /byte[2] /*other conditions -.3 volt Vcc operation */ 1<<1. /byte[20]: /*TPCC_RMSK*/ 01h. /byte[4]: /*device size ¾ units/code Ð 64 MBytes*/ (1Fh<<3) | 6. /byte[6]: (CISTPL_EXTDEVICE.METAFORMAT SPECIFICATION 3. /byte[14]: (CISTPL_CONFIG. /byte[13]: /*end of tuple*/ FFh ). /byte[21]: /* end of tuple*/ FFh ).TPCC_RFSZ/TPCC_RMSZ/TPCC_RASZ*/ 1. /*1AH*/ /byte[15]: /*link*/ 6. /byte[10]: /*device size extender ¾ 1 device extended size byte*/ 7. then a software header block might be laid out as follows: /byte[0]: (CISTPL_DEVICE_OC. /byte[11]: /*device extended size byte*/ 1. /*09H*/ /byte[7]: /*link*/ 6. /byte[17]: /*TPCC_LAST*/ 0. © 1999 PCMCIA/JEIDA 43 . /byte[3]: /*type/speed*/ DTYPE_FLASH | DSPEED_200NS. /byte[19]: /*TPCC_RADR byte 1*/ 40h. /byte[9]: /*type/speed*/ DTYPE_FLASH | DSPEED_200NS.3. /byte[5]: /*end of tuple*/ FFh ). /byte[8]: /*number of address extension bits/page address location/page size*/ 1<<2 . /byte[18]: /*TPCC_RADR byte 0*/ 00h. /byte[16]: /*field sizes -. /*1CH*/ /byte[1]: /*link*/ 4.3 Tuple Examples for Memory Device Size > 64 MBytes If 16-bit PC Card Common Memory consists of 128 MBytes of Flash memory arranged in 64 MByte pages and the page address is provided by the COR.5.

/byte[30]: /*TPCC_RADR byte 1*/ 40h. /byte[18]: /*device extended size byte*/ 01h. /byte[9]: (CISTPL_EXTDEVICE.BASIC COMPATIBILITY (LAYER 1) If a 16-bit PC Card contains a 576 Mbyte Common Memory area consisting of 128 MBytes of ROM memory. /byte[19]: /*device final size byte ¾ units/code Ð 64 MBytes */ ((1Fh<<3) | 6) /byte[20]: /*type/speed*/ DTYPE_FLASH | DSPEED_200NS.TPCC_RFSZ/TPCC_RMSZ/TPCC_RASZ*/ 2<<2 | 1. followed by 320 MBytes of Flash memory. /byte[13]: /*device size extender ¾ 1 device extended size byte */ 7. /byte[11]: /*number of address extension bits/page address location/page size*/ ((6<<3) | 2) /byte[12]: /*type/speed*/ DTYPE_ROM | DSPEED_100NS. /byte[31]: /*TPCC_RMSK byte 0*/ 00h. /byte[5]: /*device size ¾ units/code Ð 64 MBytes*/ ((1Fh<<3) | 6) /byte[6]: /*type/speed*/ DTYPE_FLASH | DSPEED_200NS. /byte[27]: /*field sizes -. /byte[32]: /*TPCC_RMSK byte 1*/ 54h. /byte[7]: /*device size ¾ units/code Ð 64 MBytes*/ ((1Fh<<3) | 6) /byte[8]: /*end of tuple*/ FFh ). /byte[15]: /*device final size byte ¾ units/code Ð 64 MBytes */ ((1Fh<<3) | 6) /byte[16]: /*type/speed ¾ no device present */ DTYPE_NULL | DSPEED_NULL. /byte[3]: /*device size ¾ units/code Ð 64 MBytes*/ ((1Fh<<3) | 6) /byte[4]: /*type/speed ¾ no device present*/ DTYPE_NULL | DSPEED_NULL. /byte[22]: /*device extended size byte*/ 04h. /byte[23]: /*device final size byte ¾ units/code Ð 64 MBytes */ ((1Fh<<3) | 6) /byte[24]: /*end of tuple*/ FFh ). 44 © 1999 PCMCIA/JEIDA . /byte[28]: /*TPCC_LAST*/ 0. /byte[25]: (CISTPL_CONFIG. /byte[21]: /*device size extender ¾ 1 device extended size byte*/ 7. then a software header block might be laid out as follows using 16 MByte pages: /byte[0]: (CISTPL_DEVICE. /byte[34]: /* end of tuple*/ FFh ). /*1AH*/ /byte[26]: /*link*/ 8. /byte[17]: /*device size extender ¾ 1 device extended size byte*/ 7. /byte[14]: /*device extended size byte*/ 01h. /byte[2]: /*type/speed */ DTYPE_ROM| DSPEED_100NS. /byte[33]: /*TPCC_RMSK byte 2*/ 01h. /*09H*/ /byte[10]: /*link*/ Eh. /*01H*/ /byte[1]: /*link*/ 7. /byte[29]: /*TPCC_RADR byte 0*/ 00h. followed by a 128 MByte empty (null) area.

3. Table 3-15 CISTPL_FUNCE: Function Extension Tuple Byte 0 1 2 3áán 7 TPL_CODE 6 5 4 3 2 1 0 CISTPL_FUNCE (22H) TPL_LINK Link to next tuple (see following sections) TPLFE_TYPE TPLFE_DATA Type of extended data (see following sections) Function information (see following sections) The TPLFE_TYPE field identifies the type of extended information provided about a function by this tuple. Consequently. The subsections are numbered corresponding to the function code being extended.6 CISTPL_FUNCE: Function Extension Tuple The function extension tuple contains information about a specific PC Card function. Please note that separate codes are provided to describe the modem and serial port interfaces for individual modem services. © 1999 PCMCIA/JEIDA 45 . that is being extended. Since all function extension tuples contain the same code (22H).2.1 Function Extension Tuples for Serial Ports The tuples defined in this document contain information which describe the operational features of a modem. Only those features commonly available and of particular interest to application software are included. Each of the function classes identified in the PC Card Functions table may be extended. both the position and the value of the TPLFE_TYPE field must be used to identify the functionality described by a particular extension tuple. distinguishes each successive CISTPL_FUNCE serial port/modem extension tuple. Each function has a defined set of extension tuples.METAFORMAT SPECIFICATION 3. The following subsections describe specific extension tuples. Separate codes are also provided to describe the modem and serial port interfaces common to all modem services. The codes defined for the TPLFE_TYPE field are presented below. This information varies depending on the function being extended. They are described in subsections following this one. Actual card identification extensions are to be determined by working groups concerned with specific PC Card function classes. The information provided is determined by the function identification tuple. If a particular function may be extended with multiple types of extended data. the serial port/modem extension tuples defined in this document must always appear immediately after the CISTPL_FUNCID tuple defined for serial port devices. Function extension tuples are optional.6. they relate to the function identification tuple preceding them in the Card Information Structure. The TPLFE_DATA field is the specific information being provided by the extended function. CISTPL_FUNCID. The TPLFE_TYPE field presented below. The content of this field varies depending on the function being extended and the TPLFE_TYPE field. a further division is provided for each type of extension data within the subsection. Modems are identified using a function ID of a Serial Port and defined further using function extension tuples to describe specific capabilities.2. If present. Function extension tuples are intended for informational use and not configuration control. The structure of a function extension tuples is determined by a code appearing in the TPLFE_TYPE field. Multiple Function 16-bit PC Card function identification tuples are not extendible.

3. Identifies the extension tuple as a description of a serial port interface for facsimile modem services. Identifies the extension tuple as a description of a serial port interface for voice modem services. Identifies the extension tuple as a description of data modem services. 16550) not. Identifies the extension tuple as a description of a serial port interface for ISDN Terminal Adapter services.2. however. Identifies the extension tuple as a description of ISDN Terminal Adapter services. The structure of the tuple and the codes currently defined for each field are presented below.e. facsimile. and/or ISDN terminal adapter). 16450. Identifies the extension tuple as a description of voice encoding services. Identifies the extension tuple as a description of the capabilities of ISDN Terminal Adapter services.1.. Identifies the extension tuple as a description of facsimile modem services. Identifies the extension tuple as a description of the capabilities of the voice modem interface. Reserved for future standardization. common to all modem and ISDN Terminal Adapter services. a specific product identification. Identifies the extension tuple as a description of the capabilities of the data modem interface. Identifies the extension tuple as a description of a serial port interface for data modem services.6. Please refer to the Serial Port Extension Tuple Type Codes Table for a list of all TPLFE_TYPE field codes. PC Card Subfunction Descriptor: Identifies a sub-category of services provided by the modem Code 1áá15 Description Identifies the extension tuple as a description of the EIA/TIA Service Class specified in the numeric value of the code. Identifies the extension tuple as a description of the capabilities of the modem interface. A specific code in the TPLFE_TYPE field is defined to describe the serial port interface to all modem services. 46 © 1999 PCMCIA/JEIDA . Additional codes are also defined to describe the serial port interface for each available modem service (data. The UART capabilities field is provided to describe the asynchronous data formats supported in UART implementations which vary from the standard. voice.BASIC COMPATIBILITY (LAYER 1) TPLFE_TYPE: Serial Port Extension Tuple Type Codes 7 6 5 4 3 2 1 0 PC Card Subfunction Descriptor PC Card Subfunction Id PC Card Subfunction Id: Identifies a category of services provided by the modem and ISDN Terminal Adapter Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14áá15 Description Identifies the extension tuple as a description of a serial port interface. Identifies the extension tuple as a description of the capabilities of the facsimile modem interface.1 Serial Port Interface Function Extension This tuple indicates the type and capabilities of the serial port interface used in communicating with the modem. The UART is identified with a generic reference to the de-facto standard it conforms to (i. When describing a de-facto standard UART the contents of this field may be set to zero.

The use of two (2) stop bits encoded in each serial data unit.5 stop bits Field space parity mark parity odd parity even parity 5 bit char 6 bit char 7 bit char 8 bit char 1 stop bit: 1. set to zero. Indicates that an 85230 ESCC is present. Reserved for future standardization.5 stop bit 2 stop bit Description The protocol where the parity bit is always reset. RFU. 08H.METAFORMAT SPECIFICATION Table 3-16 CISTPL_FUNCE: Serial Port Interface Function Extension Tuple Byte 0 1 2 3 4áá5 7 TPL_CODE TPL_LINK TPLFE_TYPE TPLFE_UA TPLFE_UC 6 5 CISTPL_FUNCE (22H) Link to next tuple (04H minimum) Type of extended data (00H. or 0DH) Identification of the type of UART in use. The encoding of data where each serial data unit contains 8 data bits. 09H. 5 4 3 2 interface 1 0 interface: The type of the UART is described using the codes defined below Code 0 1 2 3 4 5 6áá31 Description Indicates that an 8250 UART is present. Indicates that an 8530 SCC is present. Indicates that an 8251 USART is present. © 1999 PCMCIA/JEIDA 47 . The protocol where the parity bit is always set. The use of one (1) stop bit encoded in each serial data unit. The encoding of data where each serial data unit contains 7 data bits. TPLFE_UC: UART Capabilities Field 7 6 5 4 3 even parity 1 stop bit 8 bit char 2 odd parity 7 bit char 1 mark parity 6 bit char 0 space parity 5 bit char RFU. 4 3 2 1 0 TPLFE_UA: UART Identification Field 7 6 RFU. Identification of the UART capabilities. The encoding of data where each serial data unit contains 5 data bits. set to zero. 0AH. The protocol where the parity bit is generated to create an even number of set bits. Indicates that a 16450 UART is present. set to zero 2 stop bits 1. The encoding of data where each serial data unit contains 6 data bits. The protocol where the parity bit is generated to create an odd number of set bits. When the field is set (1) the specified capability is supported. when the field is reset (0) the specified capability is not supported.5) stop bits encoded in each serial data unit. Indicates that a 16550 UART is present. The use of one and one-half (1.

2 Function Extension Tuple for Modem and ISDN Interface This structure describes the characteristics of the modem interface when considered separately from the UART. Size in bytes of the DTE to DCE buffer. 07H.2. set to zero. when the field is reset (0) the specified flow control method is not supported. This includes an indication of the types of flow control supported. then multiplied by 4 ((n+1)* 4). Table 3-17 CISTPL_FUNCE: Modem and ISDN Interface Function Extension Tuple Byte 0 1 2 3 4 5áá7 8áá10 7 TPL_CODE TPL_LINK TPLFE_TYPE TPLFE_FC TPLFE_CB TPLFE_EB TPLFE_TB 6 5 CISTPL_FUNCE (22H) Link to next tuple (09H minimum) Type of extended data (01H.1. A specific code in the TPLFE_TYPE field is defined to describe the modem interface to all modem services. facsimile. TPLFE_CB: DCE Command Buffer 7 6 5 4 3 2 1 0 size of DCE command buffer size of DCE command buffer Code v/4 . 05H. voice. the size of the command buffer. 48 © 1999 PCMCIA/JEIDA . To compute the actual size of the command buffer. A command buffer of 256 bytes is represented by a field value of 3FH (63). the value of this field (represented in the formula as n) is increased by 1. 4 3 2 1 0 TPLFE_FC: Flow Control Methods 7 6 RFU. 06H. Please refer to the Serial Port Extension Tuple Type Codes table for a list of all TPLFE_TYPE field codes.1 Description Indicates the number of bytes within the command line buffer. and/or ISDN Terminal Adapter).BASIC COMPATIBILITY (LAYER 1) 3. DCE to DTE buffer. and the DTE to DCE buffer. 5 4 transparent 3 rx h/w flow ctrl 2 tx h/w flow ctrl 1 rx xon/xoff 0 tx xon/xoff Field tx xon/xoff rx xon/xoff tx h/w flow ctrl rx h/w flow ctrl transparent Description DTE to DCE transmit flow control using DC1/DC3 for XON/XOFF DCE to DTE receive flow control using DC1/DC3 for XON/XOFF DTE to DCE transmit flow control (CTS) DCE to DTE receive flow control (RTS) DCE to DCE flow control When the field is set (1) the specified flow control method is supported.6. Size in bytes of the DCE command buffer. Size in bytes of the DCE to DTE buffer. or 0CH) Supported flow control methods. Additional codes are also defined to describe the modem interface for each available modem service (data.

The actual number of bytes in the buffer appears in this field to allow a more precise definition f its size. Indicates that a DCE to DTE buffer is available and its size in bytes. the country code field TPLFE_CD was positioned as the last field in the Data Modem function extension tuple.6. The actual number of bytes in the buffer appears in this field to allow a more precise definition of its size. © 1999 PCMCIA/JEIDA 49 . This includes the level of error correction and data compression supported. the ÒMiscellaneous End User Feature SelectionÓ field. and the ITU-T(CCITT) defined country code of the target market The escape codes supported for the return to command mode are also described. A value of FFH is used to indicate the end of the country code list if it does not extend to the end of the tuple. TPLFE_TB: Modem DTE to DCE Buffer Fie