The information Intel Corporation warranties information

in this document

is subje<:t to change without

notice, including, but not limited to, the implied assumes no responsibility for any the to update nor to keep cerrent

makes no WMrilnty of any kind with regard to this material, and fitness for
.1

of merch.lntability contained

partiGulM purpose.

Intel Corporation

errors tNt m.ty ap~

in this document. in this document. in this document

Intel Corporation

makes no commitment

The software described

is furnished

under a license and may be used or copied only in accordance with

the terms of such license. Intel Corporation Intel. No part of this document of Intel ·Corporation. The following are trademarks of Intel Corporation ICE-3O ICE-48 ICE-SO ICE-8S INSITE INTEl INTEllEC and lTIolybe used only to describe Intel products: LIBRARY MCS MEGACHASSIS MICROMAP MUlTIBUS PROMPT UP! MANAGER m.ty be copied or reproduced in i1ny form or by any means without the prior _ittcn consent assumes no responsibility for the use or reliilbility of its software on equipment that is not supplied by

8080/8085

ASSEMBLY LANGUAGE PROGRAMMING MANUAL

Copyright © 1977,1978 Intel Corporation,

Intel Corporation 95051

3065 Bowers Avenue, Santa Clara, California

ASSEMBLY General assembly Chapter 3. As these examples of the Interrupt programmer's system. should read Chapters 1 and 2 and then skip to the examples in Chapter 3 or 4.PREFACE This manual Although programmer. refer to the appropriate information you will need to read The 'Programming Tips' in Chapter programmer. INSTRUCTION Descriptions for quick reference) Chapter 4. as follows: ASSEMBLY Description Overview Description LANGUAGE of the assembler of 8080 hardware and instruction differences CONCEPTS coding rules set of 8080/8085 LANGUAGE language SET of each instruction (these are listed alphabetically AND PROCESSORS Chapter Chapter 2. reference requirements. MACROS Macro directives Macro examples Chapter 6. INTERRUPTS Description Chapters 3 and 4 will fill most of the experienced information programmer quickly. especially Before writing 4 are intended for the beginning in Chapter a program. ASSEMBLER Data definition Conditional Relocation Chapter 5. iii . 6. this manual for reference. PROGRAMMING Programming Chapter 7. Chapter 4. Use the table of contents or the TECHNIQUES assembly DIRECTIVES examples index to locate The beginning raise questions. It will not teach you how to program some instructional material a computer. It also contains to help the beginning The manual is organized 1. describes programming is designed with Intel's primarily assembly language.

you have the option of specifying a number of controls. 9800292 When you activate the assembler.A.ER'S GUIDE. The operator's sequence for the assembler. The ISIS·II User's GUide describes the use of the text programs. 9800306 User program. Hardware References For additional Manual: 8080 MICROCOMPUTER SYSTEMS USER'S MANU. are commonly stored on diskette files.L. The manual also describes the debugging tools ISIS·II SYSTEM U~. 9800153 8085 MICROCOMPUTER SYSTEMS USER'S MANUAL. you should be familiar with the following Intel ISIS·II 8080/8085 IAACRO ASSEMBLER OPERATOR'S MANUAL. manual descrioes the activation and the error messages supplied by the assembler. 9800366 information about processors and their related components. The manual also describes the procedures for linking and editor for entering and maintaining locating reloc itable program modules. refer to the appropriate User's iv .RELATED PUBLICATIONS To use your Intellec development publications: system effectively.

TABLE OF CONTENTS Chapter 1. Set Modes Addressing Addressing Addressing Indirect Effects Naming Transfer Group Group I/O. Hardware/I nstruction Pair Accumulator Register Branching Instruction Conventions Arithmetic Group v . Summary Instructions (Word) Guide Instructions Set and Addressing Addressing Implied Register Immediate Direct Register Combined Ti mmg Addressing Instruction Data Logical Branch Stack. ASSEMBLY Introduction What Is An LANGUAGE AND PROCESSORS 1-1 1-1 Assembler? Does 1-1 1-1 1·2 1-2 Listing Assembler? Hardware 1-3 1·3 1-5 1-5 1·5 1-5 1-6 1-7 What the Assembler Object Code Program Do Overview You of Listing Need 8080/8085 the Symbol-Cross-Reference Memory ROM RAM Program Work Internal Condition Carry Sign Zero Parity Auxiliary Stack and Stack Saving Input/Output Instruction Stack Counter Registers Work Flags Flag Flag Flag Flag Carry Flag Pointer Registers 1-9 1·9 1-10 1·10 1-11 1-11 1-11 1-12 1-13 1-13 1-14 1-15 1-15 1-15 1-15 1-15 1-15 Addressing Modes Addressing Modes of Group 1-16 1-16 1-16 1-16 1-16 1-17 1-17 1-18 Machine Control Instructions 1-19 1-19 1-19 Instructions 1·21 1-22 1-23 Operations Program Status Ports .

Global Absolute Assernbl /-Time Permanent Redefinable Relocatable Evaluation Expression Or era tors Arithmetic Operators Shift Operators Logical Operators Compare Byte Pe omissible Precedence Operators Range of Isolation Operators Rclocatable Expressions .8085 Proc essor Differences for the 8085 Instructions CONCEPTS 1-24 1-24 1-25 2-1 2-1 Pr ogramming Cc nditional Chapter 2. gister-Type Two's Svrnbols Complement and Symbol Sv mbol ic Addressing Sy mbolic Characteristics User-Defined.tructions vi . ASSEMIIL Y LANGUAGE lntrodur tion Source Line Format Cl. and and Limited and Reserved.CII Labels Labels Data Counter Constant Assigned of Instruction as Operands Operands Representation Tables E> pressions In . Chaining of Symbol Definitions Chapter 3.tructions R.aracter Set Delimiters Label/Name Opcode Operand Cc mment Coding Operand He xadecimal Field Field Field Field 2-1 2-1 2-2 2-3 2-4 2-4 2-4 2-4 2-5 2-5 2-5 2-5 2-6 2-6 Values or Data 2-6 2-6 2-6 2-7 2-7 of Data 2-7 2-9 2-9 2-9 and Symbols Symbols Symbols Assembler-Generated Symbols 2-9 2-10 2-11 2-11 2-11 2-11 2-12 2-12 2-13 2-13 2-14 2-15 2-15 2-16 2-18 3-1 3-1 3-1 in alphabetical order Values Operators of Field Information Data Decimal Data O( tal Data Biiarv Lc cation A~. INSTRLCTION How Timing tc Use SET this Chapter are listed Information In .

Subroutines vii . ELSE. . .. .Chapter 4. MACROS Introduction Why What Macros to Use Macros Macros? 5·1 5·1 5-1 5-3 Is A Macro? Vs. ASSEMBLER Svmbol SET Data DB DIRECTIVES 4-1 4-2 4-2 Definition Directive Directive Directive EQU Definition DW Directive 4-3 4-3 4·3 44 4-5 Tips: Access Data Versus Description Read and Only Access Memory Memory Reservation OS Directive Pr ogtarnmlng Random Data Data Add Conditional Assembler END Location Description Access Symbols for Data Access 4·5 4-6 4-6 4-6 4·6 Assembly ENDIF Termination Directive Counter ORG Control Directive to Relocatability Development . 4·7 4-8 4-8 4·10 4-10 4·11 4-11 4-11 4·12 4·12 4·12 4-14 Location Introduction Memory Modular Directives Used ASEG CSEG DSEG ORG Program for Location Counter 4·14 4-14 Directive Directive Directive Directive 4·15 4·15 [Relocatable Mode) 4·16 linkage Directives Directive Directive 4-16 4-17 4-17 4-18 PUBLIC EXTRN NAME STKLN STACK and Programming Directive Directive MEMORY Tips: Reserved Words Modules Testing Routines Used for Testing Relocatable 4·18 4-19 4·19 4-19 4·20 4·20 5·1 Initialization Input/Output Remove Coding Chapter 5. (Relocatable Programs) Management Program Relocation Control and Control Relocation (Non-Relocatable Mode) Counter Directives If.

.6·7 6·11 6·12 6-14 7·1 and Chapter 7.cr o Null Sample Chapter Macros Macros TECHNIQUES Pseudo-Subroutine 6.. Interrupt Subroutines 7·1 7-4 Appendix Appendix Appendix Appendix A B C D INSTRUCTION ASSEMBLER ASCII SUMMARY DIRECTIVE SET CONVERSION TABLES· SUMMARY Al B·l (....Using Macros Definition Macro Definition Directives MACRO Directive ENDM LOCAL REPT I RP I RPC EXITM Special Nested Directive Directive Directive Directive Directive Directive B 5·3 5-4 5-4 5·5 5·5 Macro 5-6 5·8 5-8 5·9 5·10 5·12 5·12 5·12 5·14 5·15 5·16 5·\ 6 Macro Ooer ators M~cro Definitions Format Macro> Macro Nested Call~ Call Macro Calls Expansion M....PROGRAMMING Branch Software Multibyte Decimal Decimal Taoles .1 CHARACTER BINARY·DECIMALHEXADECIMAl D-I viii .. 6·\ 6·1 6·) Trdnsferring Dau Multiply Addition Addition Subtraction to and Subroutine Divide Subtraction ..INTERRUPTS Interrupt Writing Concept.

C INSTRUCTION 1-2 1-4 1-6 1-8 1-9 ix .LIST OF ILLUSTRATIONS Figure 1-1 1-2 1-3 1-4 1-5 ASSEMBLER OUTPUTS COMPARISON OF ASSEMBLY LANGUAGE WITH PL/M 8080/8085 INTERNAL REGISTERS INSTRUCTION FETCH EXECUTION OF MOV M.

.

Programming differences between the 8080 and the 8085 microprocessors are relatively minor. Therefore. repeatedly )MP for jump). you will appreciate the advantages of programming In a symbolic assembly language. The second part describes the features of the 8080 microprocessor from a programmer's point of view. WHAT IS AN ASSEMBLER? An assembler IS a software tool . The source program consists of programmer-written assembly language instructions. the assemblerfile. you can name the instruction What the Assembler Does To use the assembler. You can then pass the resulting source program in the ISIS-II System User's Guide. Since you if your express addresses and values referenced the operand field of instructions. 1-1 . previously. Assembler output consists of three possible files: the object file containing your program translated into object code.1. and the symbol table. assign these names. If your program contains a until a specific amount of time group TIMER. you can make them as meaningful as the mnemonics executed For example. ASSEMBLY LANGUAGE AND PROCESSORS INTRODUCTION Almost every line of source coding in an assembly language source program translates directly instruction for a particular processor. a listing of the symbol-cross- generated reference object code. The file to the assembler.a program . you first need a source program. These differences are described in a short section at the end of this chapter. These instructions are written using mnemonic opcodes and labels as described system includes a text editor that will help you maintain source programs as paper tape (The text editor is files. used as a timing loop (a set of instructions has passed). you can assign it the symbolic name DATE. Assembly language source programs must be in a machine-readable Intellec development files or diskette described form when passed to the assembler. If you have ever written a computer program directly in a machine-recognizable form such as binary or hexadecimal code. Assembly language operation You can also symbolically program rrust manipulate set of instructions codes (opcodes) are easily remembered 111 (MOY for move instructions. a date as data.) The assembler program performs the clerical task of translating symbolic code II1tOobject code which can be executed by the 8080 and 8085 microprocessors. the list file printout of your source code. and the symbol-crass-reference records. the assembly language programmer ' the assembly language and the processor for which he is programming. for the instructions. into a machine must be familiar with both The first part of this chapter describes the assembler.designed to simplify the task of writing computer programs.

Also. Assembler Outputs Object Code For most rrucrocornputer system with raidorn development application svstern applications. Such modules are both easier to of the advantages of the relocation code and to te u. format. In most cases you can load and execute your object program on the for testing and debugging. you probably will eventually load the object program into some form of system IS an 8080 microcomputer read only men orv. This frees In the application A special feature of this assembler IS that it allows you to request object code In a relocatable the programme system.Chapter 1. a large program can be broken Into a number of separately assembled modules. the assembler tells you that the value messages for common 1-2 .uage and Processors OBJECT FILE SOU<. However. The assembler programming errors in the program listing. Program Listing The program lisung provides a permanent also provides diagnostic specify a Lri-b: exceeds the pernissible value for an Instruction range. individual portions of the program can be relocated as needed when the application description r from worrvmg about the eventual mix of read only and random access memory design is final. do not forget that the Intellec development access memory.CE PROGRAM FILE ASSEMBLER PROGRAM I~ ~ PROGRAM LISTING CROSS REFERENCE LISTING Figure 1-1. Assembly Lani. record of both the source program and the object code. See Chapter 4 of this manual for a more thorough feature. For example. This allows you to test your program before your prototype sys:em IS fully developed. if you that can use only an 8-blt value.

wntmg programs. Manual systems may be SUitable for limited and those who want to explore possible applications If most of the factors listed previously apply to you. Also. have not yet been described. A high-level language is directed more to problem solving TIllS allows you to write programs much more quicklv than a hardware- oriented language such as assembly language. digits. The greater the number of programs to be written. The following example illustrates the coding differences between assembly language and PL/M. multiply this requirement. you should explore the advantages of PL/M. than to a particular microprocessor. Also. the need for • The level of support the program has been for exisung programs: 111 Sometimes programming errors are not discovered support programs In use can until use for quite a while. The symbol-crass-reference that references POints you to each instruction Do You Need the Assembler? The assembler IS but one of several tools available for developing microprocessor programs. Also. choosing the most suitable tool IS based on cost restraints versus the required level of performance. error In that your program manipulates a data field named DATE. You or your company must determine • cost restraints. hobbvtsts. the handling of this data.Chapter 1. As an example. Such manual programming prograrnrrung. Assume. program support frequently subject to stringent If none of the factors described above apply to your Situation. the required level of performance depends on a number of variables: the more The number of programs to be written: you need development support. agree to correct such errors for YOUI'customers. read only IS relatively slow and more prone to human error than computer-assisted the least expensive tools available for microprocessor applications. the assembly language instructions 1-3 . As the time allowed for prograrnmmg decreases. allows you to enter programs directly Into programmable You enter the program manually as a string of hexadecunal programming. It must be pointed out that there can be penalties for not you may be With custom features through program changes. you may be able to o The time allowed for programrmng: prograrnrnmg support mcrcases. Since Instructions are represen ted by a flowchart. assume that a program must move five characters from one location 111 memory to another. Assembly Language and Processors Symbol-Crass-Reference Listing listing is another of the diagnostic tools provided by the assembler. memory. Typically. Your need for programming The number of supported 15 mcreases if you time constraints. for example. you may be able to get along Without the assembler. manual systems are one of for microprocessors. PL/M IS Intel's high-level language for program development. has access to the power of a microprocessor. for The symbol-crass-reference example. and that testing reveals a program logic listing simplifies debugging this error because it the symbol DATE. Intel's PROMPT-80. When your application able to provide customers add features through prograrnrrung. However.

FLD2. Assembly Lan 5uage and Processors ASSEI~BL Y LANGUAGE CODING PLiMCODING ~"GISTER WITH NUMBER i~RACTERS TO BE MOVED I E"GISTER PAIR B WITH ESS OF SOURCE (FLD1) I LOAD I~EGISTER PAIR D WITH ADDRESS OF DESTINATION (FLD2) I LOAD . I INCRHIENT ADDRESS DESTINATION ~ I I DECRE. Comparison of Assembly Language with PL/M 1-4 .ENT CHARACTER COUNT NO IS CHARACTER COUNT =O? YES ( CONTINUE Figure 1-2.FLD1).Chapter 1.~CCUMULA TOR WITH 1 BYTE F ROM SOURCE FIELD I MOVE:HARACTER TION FIELD FROM ACCUM ULATOR TO DESTINA- I IINCWIENT SOURCE ADDRESS CALL MOVE(5.

With RAM a program Notice. There are two general types of memory: read only memory (ROM) and random access memory ROM As the name Implies. If your program modifies any of its own Instructions The mix of ROM and RAM Normally. your application is likely to require some random access memory. it cannot alter the contents and unchanging data With ROM you the processor can both read from and write to RAM. Instructions used for program storage in single-purpose microprocessor fixed into ROM and remain intact whether or not power is applied to the system. but is of interest to the programmer. Two special types of ROM PROM (Programmable Read Only Memory) and EPROM (Eraseable Programmable Read Only Memory) are frequently used during program development. By contrast. the programmer an application IS important to both the system designer and the programmer. These memories are useful during program development applications. programs can be loaded to serve different reason. RAM Even if your program resides entirely Any time your program attempts discouraged).Chapter 1. are permanently and data from ROM. Of the components Memory Since the program required (RAM). those instructions In in ROM. all microprocessor applications require some memory. gram uses the stack. however. memory is not part of the processor. Assembly Language and Processors OVERVIEW OF 8080/8085 HARDWARE comprises the following parts: To the programmer. For this applications. ROM is typically can be certain that the program is ready for execution in RAM allows a multi-purpose system since different must be loaded into memory each time power is applied to the processor. that storing programs needs. since they can be altered by a special PROM programmer. you need RAM. must reside in RAM. to drive a microprocessor resides'in memory. Also. if your pro(this procedure is to write any data to memory. when power is applied to the system. must know the physical addresses of the RAM in the system so that data variables 1-5 . the computer • • • • • • • Memory The program cou nter Work registers Condition flags The stack and stack pointer Input/output ports The instruction set listed above. that memory must be RAM. In high-volume commercial these special memories are usually replaced by less expensive ROM's. the processor can only read instructions of ROM.

8080 IACCUMULATORI B D FLAGS HIGH INSTRUC[EJ DECOD::R C E L STACK PROGRAM ADDRESS LOW POINTER COUNTER BUS LATCH 8085 I DATA BUS_ATCH I H 8-bit bidirectk mal data b JS D 16-bit address bus U r-------.Chapter 1. With the progr irn counter. the program counter always indicates the next byte to be fetched. the Information and the 8085. Each time It fetches an instruction byte from memory. Assembly Lang rage and Processors can be assignee program feature without repositioned within those addresses. 8080/8085 Internal Registers . The next instruction fetch occurs from the new address. applies equally to the 8080 Internal registers illustrated in Figure 1-3. However. To alter the flow of program execution as with a jump irstruction or a call to a subroutine. ROM INSTRUCTIONS CONSTANT DATA RAM INSTRUCTIONS VARIABLE DATA STACK INPUT PORTS OUTPUT PORTS Figure 1-6 1-3. The relocation is fully explained 4 of this manual. these program af:er the program has been tested and after the system's IS final. the processor overwrites the current contents of the program counter with t re address of the new Instruction. Therefore. This process continues as ie ng as program instructions are executed sequentially. the relocation feature of this assembler memory layout allows you to code a elements can be concern for the ultimate in Chapter placement of data and instructions. the processor increments the program counter by on". Program Counter we reach the first of the 8080's NOTE Except for the differences listed at the end of this chapter. in this chapter The program counter keeps track of the next instruction byte to be fetched from memory (which may be either ROM or RAM:.

C. can be accomplished by more than half a dozen different Instructions. The choice of which pair as III PUSH B {which pushes Notice contents lator}. and L can provide results III a wide variety and storing of functions 16-bit address such as storing pointers. A simple add to the accumulator. instructions but It has some special capabilities IN and OUT transfer the accumulator involving affect not shared with the the accumuflags as ex- data only between the condition Also. by the Hand The MOV M. the mput/output register. many operations In the next section. Because of set. by the letters A (for the accumulator). The accumulator other plained Example: The following of register figures illustrate the execution location specified to memory. When possible. D. pair. for example. lator and external also acts as a general-purpose For example. C to the memory L registers. Thus. ADD B is an 8·blt operation. C. H. E. I/O devices. B. the stack} is a 16-blt operation. provides reference an 8-bit accumulator these registers and six other general purpose work registers. H. S-bit data values.e moves a copy of the contents Notice that this location must be in registers. using data already present in a register eliminates a memory access and thus reduces the time required for the operation. The general the 8080's purpose extensive that the letters of Hand of the Band M both refer to the Hand L register addresses by the Hand to use depends the on the instruction. as shown in Figure 1-3. onto C registers pair. RAM since data is to be written 1-7 . The mstruction to be executed By contrast how the processor the reference. D. storing arithmetic operations. the to the contents of the accumu- ADD B may be interpreted as 'add the contents of the B register Some instructions reference Symbolic a pair of registers Reference B D H M PSW as shown in the following: Registers Referenced Band Hand Hand C L L (as a memory reference) flags (explained D and E A and condition later rn this section) The symbolic determines reference for a single register interprets the contents Hand IS often the same as for a register For example. and L. it is usually possible to achieve a common result with any of several different instructions. E. Assembly Language and Processors Work Registers The 8080 Programs mstruction lator. it is generally desirable to select a register-to-register mstrucnon such as ADD B. Use M when an instruction via the Hand as in ADD M {add the contents L registers to the contents of the accumu- registers intermediate instruction B. These Instructions tvpicallv require only one byte of program storage. Also.Chapter 1. of a move instruction. Use H when an instruction of the memory location acts upon the Hand specified L register memory INX H {increment L registers L by one}.

and then increments the program counter by one to Indicate address of the next Instruction in Figure 1·5. for normal refer to the User's Manual for your processor. byte. 1·8 .e instruction does not account concerning memory is conceptually interface. the Instruction is decoded into the series of actions NOTE The following description of the execution bus control.Chapter 1.--- Ll ROM • RAM Figure 1-4. correct. of the but For details MOV M. Instruction Fetch The processor memory initiates the instruction fetch by latching the contents the of the program shown counter on the address bus. Assembly Laru uage and Processors IACCUMULATORI FLAGS e E L t INST RU(~ DE COl. When the respc nds.ER I I HIGH STACK PROGRAM ADDRESS LOW 8080 8085 B D H I DATA BUS LATCH t II I I I II Il II I 1 I POINTER COUNTER BUS LATCH I .

Coding a J PE (jump if parity is even) or J PO (jump if parity is 1-9 . for example. Since it is unacceptable to destroy either of the operands. a different for the programmer instruction as will be explained to know which flags are set by a particular that your program is to test the parity of an input byte and then execute one Instruction set if parity is odd. of a previous operation. a zero result indicates includes that the opreands are equal.C Instruction To execute the contents terminates the MOY M. When the memory accepts the data. later in this section. It is important even.Chapter 1. sign. is reserved for the use of the DAA instruction. and parity) using one of the conditional based on the outcome carry. Certain arithmetic and logical instructions alter one or This allows you The 8080 provides five flip flops used as condition more of these flags to indicate the result of an operation. Assume. call. These registers are Condition Flags flags.C instruction. instruction. Execution of MOY M. the processor several work registers reserved for its own use. in destructive operations. a compare is actually a subtract operation. zero. L registers on the address bus. auxiliary flags (carry. to alter the flow of program execution Your program can test the setting of four of these iurnp. Assembly Language and Processors 8080 8085 IACCUMULATORI FLAGS I I INSTRUCTION DECODER B I I I C I E L I I HIGH LOW I STACK PROGRAM ADDRESS ! POINTER COUNTER BUS LATCH I I I I D H i ! I I DATA BUS LATCH ~ t ROM •• RAM Figure 1-5. The programmer used for internal data transfers and for preserving operands cannot access these registers. For example. sequence if parity is The fifth flag. or return Instructions. the processor Internal Work Registers Certain operations are destructive. of the Hand execution of this instruction the processor latches the contents and initiates the next instruction of the C register on the data bus and fetch.

next higher Complement 01 the carry flag IS commonly used to Indicate whether an addition flag 111 causes a 'carry' as explained into the der digit. This sets the parity flag without altering the data In the accumulator. A zero In bit 7 . under 'Two's by the logical of Data' In Chapter 2 of this manual. tions before desired flag. and XRI instructions which move the contents 3 of this manual. Sign Flag As explained rnder 'Two's Complement Representation of Data' In Chapter 2. ANI. of the ANA. In these cases. XRA. an addition that does not cause a carry resets the flag to zero. The carry flag is also affected set ON or OFF particular in Chapter 3. the parity flag after the IN instruction. RLC. tion that alter. Carry Flag As ItS name it rplies. treat the of the RAL. you can does not affec t the condition unrelated by your program reflects the outcome to work correctly. RAR. NOTE are detailed in the individual YJU use It. ani exclusive OR instructions. ORA. See the descnnions bits of the accumulator. The jump executed For the operation produces false results since the IN instruction of some previous you must include some instrucFor example.Chapter 1. of the accumulator The rotate in-tructions. when a flag IS 'reset' it IS reset OFF (has the value zero). ORI. add zero to tl e accumulator. and RRC it were a ninth bit of the accumulator See the descrrptions of tvo one-byte numbers can produce a carry out of the high-order bit: 7654 3210 1010 1110 0111 0100 0010 001 0 = 22 carry flag = 1 Bit Number: AE= +74= An addition t rat causes a carry out of the high order bit sets the carry flag to 1. but before the lump Instruction. The flags set l. but then have a number of intervening instructions instruc- In other cases you will want to set a flag With one instruction. AND.v each Instruction manual. Instructions 1-10 that affect the sign flag set the flag equal to bit 7. The carry flag IS also used as a 'borrow' :~epresentatlon These instructions subtractions. OR. to the IN instruction. Assembly Language and Processors odd) instruction operation Immediately following the IN (input) Instruction flags. carry bit as trough instructions Example: Addition rr Chapter one position to the left or right. bit 7 of a result in the accumulator can be interpr eted as a sign. you must be certain that the mterverung do not affect the instruction descriptions In Chapter 3 of this When a flag is 'set' It IS set ON (has the value one).

Assembly Language and Processors indicates a positive value. that adding one to this value produces values such as the A in the preceding example back into binary coded requires the auxiliary carry flag since the BCD format makes it decimal (BCD) format.) Notice. as two 4-bit as a in The auxiliary carry flag indicates a carry out of bit 3 of the accumulator. is other than zero. (If this value is interpreted a non-decimal it has the value 25. a one indicates a negative value. it is present to enable the DAA (Decimal Adjust Accumulator) The auxiliary carry flag and the DAA instruction binary number. A result that has a carry and a zero result also sets the zero bit as shown below: 10100111 +0101 1001 00000000 Carry Flag = 1 Zero Flag = 1 Parity Flag Parity IS determined by counting the number of one bits set in the result in the accumulator. Auxiliary Carry Flag You cannot test this flag directly to perform its function. Instructions that affect the parity flag set the flag to one for even parity and reset the flag to zero to indicate odd parity. your program. This value is duplicated conditional [urnp. call. result: 0001 1001 +00000001 0001 1010 = lA The DAA instruction possible for arithmetic converts hexadecimal operations allow you to treat the value in the accumulator binary coded decimal numbers. The DAA performs the following addition 0001 1010 +00000110 0001 0000 +0001 0000 (auxiliary carry) 0010 0000 = 20 1-11 . and return instructions in the sign flag so that can test for positive and negative values.Chapter 1. the value 0001 1001 is equivalent to 19. Thus. however. Zero Flag Certain Instructions These instructions set the zero flag to one to indicate that the result in the accumulator reset the flag to zero if the result in the accumulator contains all zeros. The DAA instruction to generate a carry from the low-order 4-bit digit Into the high-order 4-bit to correct the preceding example: digit.

The base address of the stack is commonly available addess in RAM. and all logical AND. You can recode this routine inline each time it is needed.Chapter 1. (Since the 8080 has no multiply 3x4 is equivalent to 3+3+3+3. subtract.rn as though the subroutine IS. (See the descriptions of these Instructions In compare. This means that your program must load the base address of the stack into the stack pointer. a return instruction pops that previously-stored address off the stack and puts it back into the program counter. YOiJr program must initialize the stack pointer. The 8080 logical AND s et the flag to reflect the logical OR of bit 3 of the values involved in the AND operation. you can code a subroutine: but this can lise a great deal of memory. The contents the program counter are replaced by the address of the desired subroutine. Program exec ution then continues The rnechani. (the contents of the program counter) When the call instruction is executed. decrement. the of pushed onto the stack. had been coded inline. needs this multiply routine several times. the concept of a subroutine. At the end of the subroutine. However. Stack and Stack Po inter To understan j the purpose and effectiveness of the stack. 1·12 . The 8085 logical AND instructions always set the auxiliary flag ON. this that Assume that /our program requires a multiplication can be performed your prograrr through repetitive addition.essor. and excl . the stack. Chapter 3.) There is some In the 8080 processor and in the handling of the auxiliary carry flag by the logical AND instructions the 8085 pro . that makes this possible of course. Assembly Lan zuage and Processors The auxiliary carry flag is affected OR.) instructions. The stack is simply an area of random access IS memory add: essed by the stack pointer The stack pointer a hardware register maintained by the processor. This is because the stack expands by decrementing assigned to the highest As items are the stack pointer. nline Coding Subroutine nline routine nline routine nline routine 1 I I I CALL CALL CALL 1 I I I IS subroutine The 8080 provides instructions address of th e next instruction that call and return from a subroutine. increment. it is useful to understand routine. Or.rsive OR instructions. Assume further For example. difference instructions by all add.

and POP. term because you can always put can call a subroutine.Chapter 1. that removes an Item from the stack. To be more precise. In terms of programming. a subroutine the contents executing of that register before returning to the main program. you can subany the stack any data it places on the stack. which adds data to the stack. for any Instruction means that you must assign data that requires RAM to the lowest RAM addresses available. However. your program should remove from that adds to the stack. The results are of course. The most critical factor is the maximum of RAM you intend for other data. The subroutine pushing the contents the POP instructions original location. the return mstrucuon unpredictable. if you caJl a subroutine and the subroutine pushes data onto the stack. The only limitation to the number of items that can be added to the stack is the amount to the stack is important to the programmer. of the registers onto the stack and then popping the data back into the registers before sequence saves and restores all the working registers. pushes the contents of the program counter (which contains the address of the next instruction) by placing its address in the program counter. not what you want. Otherwise. Notice that you must be sure to remove data your program adds to the stack. As you write your program. left-over items on the stack may cause the stack to grow into portions Stack Operations Stack operations operations transfer sixteen bits of data between memory and a pair of processor registers. you this must be certain that the stack will not expand into areas reserved for other data. For most applications. The two basic are PUSH. it IS equally returns to the main can do this by should save the contents control of a register before using it and then restore likely that the main program has data stored in the registers that it needs when control As general rule. This requires the A call Instruction onto the stack and then transfers control A return instruction to the desired subroutine pops sixteen bits off the stack and places them in the program counter. but probably Savtnq Program Status It is likely that a subroutine program. Therefore. requires the use of one or more of the working registers. Ultimately. of RAM available for back toward Its base address. which removes data from the stack. For example. the stack pointer something the stack. Nonetheless. pops data from the stack and places It in the program counter. you must count up all instructions tract any intervening instruction that add data to the stack. Otherwise. Notice that order of the PUSH instructions if the data is to be restored to its must be in the opposite a return. The following instruction 1-13 . it expands into memory locations stack. programmer to keep track of what is in the stack.' Stack is still a most descriptive else on top of the stack. Assembly Language and Processors added to the stack. the subroutine must remove that data before executing a return instruction. size of the stack. As Items are removed from the the most recent item on the and so on. The amount of RAM allocated is incremented with lower addresses. a subroutine stack is known as the 'top of the stack.

tion latches the number of the desired port onto the address bus. are almost totally application dependent. Because input and output the scope of t liS manual. Assembly Language and Processors SUBRTN: PUSH PUSH PUSH PUSH PSW B 0 H coding subroutine POP POP POP POP RETURN The letters B. EI. (PUSH PSW adds three bits of filler to expand the condition flags into a full Input/Output Ports ports provide communication with the outside world of peripheral devices. and Hand L register pairs. 01. information. The IN and The 256 mpur/output OUT mstructr. hera I device. Notice that the IN and OUT instructions Simply Initiate a data transfer It is the responsibility of the peripheral device to detect that It has been addressed. 15 The IN mstru. (The RIM and SIM instructions 1-14 . Notice also that it is possible to dedicate any number of ports to the same pen. The program status word IS a 16-blt word comprising byte. 0. The OUT inst: uction latches the number of the desired port onto the address bus and latches the data in the accumulator The specified onto the data bus.) Chapter 3 of this manual.Chapter 1. refer to the 8080 or 8085 Microcomputer see the descriptions Systems User's Manual. for example. OUT. You might use a number of ports as control signals. a discussion of design techniques IS beyond For related prograrnmmg Instructions In of the IN. For additional hardware mforrnauon. it is transferred into the accumulator.) of the accumulator flags. 0 and E. and H refer to the Band and the five condition H 0 B PSW C. the instruction IN 5 latches the bit configura- tion 0000 01 (1 0000 0101 onto the address bus. As 500n as a byte of data returned to the data bus latch. RST. Thus. rort number 15 duplicated on the address bus.ins initiate data transfers. the contents PSW refers to the program s atus word. and RIM and SIM apply only to the 8085. respectively. POP PSI/ stnps out these filler brts.

the DAA (decimal accumu- Register Addressinq. operand. must initialize the instruction (load register is commonly LXI SP.' code. LXI IS the instruction most commonly With the hexadecimal used for this purpose. value 30FF. exchanges However. as an Implied as in the CPI instruction moves the hexadecimal The MV! (move the accumulator. Instructions that use Immediate addressing have data assembled the contents fetches value FE43. The processor the next byte Into one of its internal and then performs that the names of the Immediate indicate that they use immediate is ADI. For example. deals only with the carry flag. As mentioned data IS a 16-bit previously. H or L as well as the operation For example. must specify 'compare the accumulator QUite a large set of instructions A through as a second operand. previously including use the accumulator Instruction Thus. When this instruction the compare operation. Assembly Language and Processors Instruction Set incorporates a powerful operation array of Instructions. Thus. Instruction program counter Jump Instructions include al6-bit address as part of the instruction. Addressing Modes can be categorized according to their method of addressing the hardware registers and/or memory. CMP E may be Interpreted the contents of the E register that use register with the contents addressing Most of the Instructions deal with 16-bit register with the contents deal with 8-bit values. the name of an add instruction is ADD: the name of an add Immediate instructions Instruction All but two of the Immediate shown registers.30FFH pair immediate) is even more unusual Into a register in that ItS Immediate pall'. instructions it must fetch one more byte. for the letter that this instruction has the hexadecimal Hexadecimal representation and determines registers Notice C. data. a few of these Instructions of the program counter pairs.Chapter 1. the instruction of the accumulator. 1-15 . you as one of the registers IS implied E. call for register addressing. adjust example. For Instructions Implied Addressinq. loads the stack pointer Direct Addresstnq. the processor fetches as a part of the instruction of the accumulator the first instruction with byte 43 IS the Internal Itself. With these instructions. of each instruction This section provides a general overview of the Instruc- The 8080 tion set. The detailed is described In Chapter 3 of this manual. Immediate) can move its immediate the Instruction data to any of the working or to memory. the PCHL Instruction the contents of the Hand Immediate the letter Addressinq.' When assembled. the Instruction CPI 'C' may be Interpreted IS executed. as 'compare c. The LXI Instruction value. The addressing mode of certarn Instructions is implied by the instruction's function. the of the J MP 1000H causes a jump to the hexadecimal address the current contents With the new value 1000. the STC (set carry flag) instruction lator) instruction deals with the accumulator. MVI D. 1000 by replacing For example.OFFH value FF to the D register. This Instruction program ample. vour For ex- used to load addresses the stack pointer. L registers. With these Instructions. For example.

8 microseconds. Modes. Some instructions subroutine. instructions about through on the clock frequency range from 48) nanoseconds microse:onds and therefore zan execute the timing of a four state Instruction clock frequency than the 8080. puhes the current of the program counter into the memory Timinq Ettect: of Addresstnq an Instruction register present execution counter and the amount registers.. each mstructic 1. 7976. Instruction register In the Band pair. may range from of 320 nanoseconds n.) The length of a state depends to 2 microseconds. requires of the program More important. can access memory once during descriptions each processor in Chapter Thus. three to access the entire and two more to push the contents onto ihe stack. Addressing required modes affect both the amount For example. Assernblv Lang rage and Processors Instructions that include a direct address require three bytes of storage: one for the Instruction code.Chapter 1. with the processor of time required instructions hardware factor for executing or of memory for ItS storage.) (The 8085 has a maximum Instruction Narnt. 1 he instruction C register Register indirect instructions reference memory via a register address stored pair. MOV MVI LDA STA LHLD SHLD ALL MNEMONICS 1-16 categories: instructions move data between registers or between memory and The data transfer Move Move Immediate Load Accumulator Directly from Memory Store Accumulator Directly in Memory Load Hand L Registers Directly from Memory Store Hand L Registers Directly in Memory © 7974. of memory require accesses is that the entire instruction can be fetched single memory five memory access. Each cycle comprises the number specified a variable number and may of for The processor states. A CALL instruction.920 (The individual Instruction 3 specify of cycles and states required for your system.iq Conventions assigned to the instructions functional are designed to indicate the function of the instruction. of the C register into the memory LDAX B loads the accumulator with the byte of data specified by the address Combined for example. accesses or with data already in determining for example. specifies instruction pointer Adc'ressinq combines the address Modes. and two for the 16-bit address. Register Indirect Addressing. A CALL instruction. use a combination Indirect the register indirect of addressing address modes.s tions fall into the following Data Transfer Group. 7975. 50% faster cycle.C moves the contents pair. registers. Thus. time. The number More memory accesses: required is the single greatest more execution Instruction. in the Hand the L MC>V M . that use implied with a very quickly since they deal directly however. addres ung execute in hardware timing. 7977 INTEL CORPORA TlON . The instruc- The rnnernoru. The direct address location in a CALL instruction The CALL by the stack specified IS the stack pointer. direct addressing of the desired contents and register addressing.

OR.Chapter 1. AND. The arithmetic instructions add. condition flags. or decrement data in registers or ADD ADI ADC ACI SUB SUI SBB SBI INR DCR INX DCX DAD Add to Accumulator Add Immediate Add Immediate Subtract Subtract Subtract Subtract Increment Decrement Increment Decrement Double from from Data to Accumulator Using Carry Flag Using Carry Flag Data to Accumulator Accumulator Data from from Accumulator (Carry) Flag Using Borrow Accumulator Using Borrow Accumulator Add to Accumulator Immediate Immediate Specified Specified Register Register Register Byte by One Byte by One Pair by One Pair by One Add Contents Pair to Hand of Register L Register Pair Add: Logical Group. and Exclusive OFF. Group. 7977 INTEL CORPORA nON '·17 . This group performs logical (Boolean) operations on data in registers and memory and on The logical. 7975. subtract. Assembly Language and Processors An 'X' In the name of a data transfer LXI LDAX STAX XCHG XTHL instruction implies that it deals with a register data in Register Pair Pair pair: Load Register Pair with Immediate from Address in Address Load Accumulator Store Accumulator Exchange Exchange Hand in Register L L with D and E Top of Stack with Hand Arithmetic memory. ANA ANI ORA ORI XRA XRI The compare instructions CMP CPI compare OR instructions enable you to set specific bits in the accumulator ON or Logical AND with Accumulator Logical AND with Accumulator Logical OR with Accumulator Logical OR with Accumulator Exclusive Exclusive OR Using Immediate Using Immediate Data of the accumulator: Data Logical OR with Accumulator Using Immediate Data the contents Compare Compare of an 8·blt value with the contents Using Immediate Data ALL MNEMONICS © 7974. 7976. increment.

7976. 7977 INTEL CORPORA TION 1-18 . either unconditionally or are as follows: Conditional specified br mching Instructions bran: h IS the status of one of four condition flags to determine whether the to be executed. conditionally. 7975.id carry flag instructions: CMA CMC STC Complement Complement Set Carry Accumulator Carry Flag Flag Branch Group. The branching Ihe unconditional JMP CALL RET instructions branching Jump Call Return examine alter normal instructions sequential program flow. The conditions that may be specified are as follows: NZ Z NC C PO PE P M Thus.Chapter 1. the conditional branching Not Zero (Z = 0) Zero (Z = 1) No Carry Carry Parity Plus (5 (C = 0) (C = 1) Parity Odd (P = 0) Even (P = 1) = 0) 1) are specified Returns RC RNC RZ RNZ RP RM RPE RPO by replacing (Carry) (No Carry) (Zero) (Not Zero) (Plus) (Minus) (Parity (Parity the contents Counter Used with Interrupts Even) Odd) of the program counter: as follows: Minus (5 Instructions Calls CC CNC CZ CNZ CP CM CPE CPO can effect a branch Jumps JC JNC JZ JNZ JP JM JPE JPO Two other instructions PCHL RST Move Hand Special L to Program Instruction Restart ALL MNEMONICS © 1974. Assembly Language and Processors The rotate instructions RLC RRC RAL RAR shift the contents Rotate Rotate Rotate Rotate of the accumulator Accumulator Accumulator Left Through Right Through Left Right Carry one bit position to the left or right: Carry Complement a.

Assembly Language and Processors Stack.D&E. 7975. 7976. I/O.E.C. Designates Designates Designates Designates Designates which calls for two operands. are also shown all act on the data in the accumulator.B. immediate Accumulator Instructions illustration shows the Instructions that can affect the accumulator.D. the Instruction Code REGMS does not allow operands. of its operands. MOV Instruction. or SP). Meaning The operand (a memory may specify reference one of the S-bit registers A.H&L.H. The type of operand for each Instruction IS Indicated When no code is given. operand. instructions. an S-bit port number a 16-blt a 16-blt register pair (B&C. The instructions listed above affect The following the accumulator accumulator. The STC (set carry) and CMC (complement ALL MNEMONICS © 7974. or L or M The via the Ifi-brt address in the Hand L registers). The instructions condition but do not affect here. operand. and Machine Control Instructions. flags.Chapter 1. can specify M for only one S-bit immediate a 16-bit address. and all except CMA (complement accumulator) carry) one or more of the condition listed below the accumulator move data Into or out of the instructions flags. PUSH POP XTHL SPHL The I/O instructions IN OUT The machine control EI DI HLT NOP Instructions are as follows: Initiate Initiate The following instructions the Stack L affect the stack and/or stack pointer: Push Two Bytes of Data onto Exchange Pop Two Bytes of Data off the Stack Top of Stack with Hand of Hand L to Stack Move contents Pointer Input Operation Output Operation are as follows: Enable Disable Interrupt Interrupt System System Halt No Operation HARDWARE/INSTRUCTION The following specific illustrations SUMMARY graphically summarize allowed the instruction set by showing the hardware through acted upon by the use of a code. 7977 INTEL CORPORA TlON 1-19 .

-1 I ACCUMULATORI FLAGS I STC CMC HIGH STACK LOW POINTER COUNTER I I C E L J I I I PROGRAM I HI LDAX} STAX EC.DE MEMORY MVI MOV [J S S STACK F. Assembly Lan guage and Processors ADD ADC SUB SBB ANA XRA ORA CMP RLC RAR RAL CMA INR} DCR REGMS ADI ACI SUI SBI ANI XRI ORI CPI RRC DAA REGM S DS MOV REGMS: RECMsi J~ B D I . 7976. 7975.REG ALL MNEMONICS © 7974. 7977 INTEL CORPORA TlON '·20 .EGMS.Chapter 1.

7977 INTEL CORPORA TlON 1-21 . 7975.H. IACCUMULATORI B FLAGS C E L ._- REG16 [SPH' PCHL -I HIGH LOW POINTER XCHG _I PROGRAM ! COUNTER 1 STACK ! XTHL LHLD SHLD 1 MEMORY STACK PUSH } POP B.Chapter 1.- D H 'NX) 1-DCX DAD . Assembly Language and Processors Register Pair (Word) Instructions The following instructions all deal with 16-bit words.. DAD affects only the carry flag.".D.PSW ALL MNEMONICS © 7974. 7976. Except for DAD (which adds thecontents of the B&C or D&E register pair to H&L). none of these instructions affect the condition flags.

Chapter 1. stack pointer. execution Instructions can alter the contents of the program counter. ~CUMjLATORI ~i FLAGS C E L I HIGH I I ~ LOW POINTER ~) I PCHL COUNTER RST ~I IMP jC IZ IP INC cc CNC} INZ (> A CZ CNZ 1M I 16 CP CM 1 J CALL RET RC RZ 16RP RNcl RNZ A RM J> 16 A JPE IPO CPE CPO RPE RPO MEMORY CONTROL INSTRUCTIONS RST Nap HLT EI 01 STACK SIM} RIM 8085 only ALL MNEMONIC5'~ 7974.iguage and Processors Branching Instructions The followin. and stack.7977 INTEL CORPORATION 1-22 .7975. Call and Return Instructions program counter. thereby altering the normal sequential affect the flew.1976. Iump instructions affect only the program counter. Assembly La.

Chapter 1. MEMORY A16 INPUT PORTS OUT P8 OUTPUT PORTS CONTROL INSTRUCTIONS RST NOP HLT EI DI SIMI RIM] MVI D8 MOV REGM8.E.or SP).PSW 1 8085 ONLY MEANING REGM8 The operand may specify one of the 8-bit registers A. can specify M for only one of its operands. 7977 INTEL CORPORA nON 1-23 . Assembly language and Processors Instruction Set Guide The following is a summary of the instruction set: ADDl ADC SUB SBB ANA XRA ORA CMP ADI ACI SUI SBI ANI XRI ORI CPI REGM8 D8 RLC RAR RAL RRC CMA DAA INR} DCR REGM8 FLAGS I "ACCUMULATORI MOV REGM8.H& L. 7975. Designates a 16-bit address.D&E.B. Designates a 16 -bit immediate operand. The MOV instruction. 7976.REGM8 CODE f---------- STACK ~ PUSH pOP ) B.REGM81 LXI REG16. ALL MNEMONICS © 7974.D16 1 iSTC CMC INX} IDCX REG16 HIGH LOW RST B C E L I D H I ~ XCHG JMP JC JZ JP JPE JNCi JNZ ~ A JM 16 JPO CALL CNCl CZ CNZ CP CM CPE CPO RET cc J J A RC RZ 16 RP RPE RNCi RNZ ~ A RM 16 RPO J ~ LHLD} STHD LDAX\ STAX) BC DE .H.C.H. or l or M (a memory reference via the 16-bit address in the Hand L registers).D. Designates an 8-bit port number. Designates 8-bit immediate operand.D. Designates a Ifi-bit register pair (B&C. which calls for two operands.

the processor always recognizes the higher priority Interrupt first. for handling serious problems such as power failures.Chapter 1. Program routines that service interrupts hz ve no special priority. either disable the interrupt 1-24 . These priori.5 RST5.5 interrupt can Interrupt the service routine for an RST7. Despite the new Interrupt 8085 hardware interrupt features of the 8085. however. The programmer prior to execution must place the desired interrupt mask and/or serial output serial data if one is present and the Interrupt mask Into the accumulator. . or mask out other potential interrupts (SIM instruction). ies apply only to the sequence in which interrupts are recognized. The SIM instruction The RIM Instruction Details of these instruc- mask and/or writes out a bit of serial data. Most programs written for the 8680 should operate on the 8085 with- than to the programmer..abled. and RESTART addresses fall between the existing 8080 RESTART addresses. Notice.5 INTR lowest highest When more han one interrupt is pending. out rnodificaion.5 RST6.. Assernblv Larguage and Processors 8085 PROCESSOR DIFFERENCES The differences compatible between the 8080 processor and the 8085 processor will be more obvious to the system designer Except for two additional instructions. the new features of the 8085 are summarized These instructions sets the interrupt reads a bit 0 differ from the 8080 instructions In the accumulator in that each has multiple functions. programming for interrupts is little changed. system speed of the 8085 may alter the time values of such routines. of the SIM instruction. that Input is non-maskable routine for it. cannot be di . Execution speeds approximately 50% faster than the 8080. If your application The interrup:s have the following priority: TRAP RSn. A partial listing of 8085 design features . and Driver and the Incorporation A non-maskable in the processor of the features of the 8224 Clock Generator and Bus Driver. internal RST instructions. tions are covered in Chapter 3.. For the prog ·ammer. with the 8080 instruction The only programs that may require changes are those with critical timing routines.. be certain to provide an interrupt only four bytes are available for certain RST instructions.5 system (01 interrupt. instruction). the 8085 iti~truction set is identical to and fully the higher set. If you want to protect a service routine from interruption. Thus. Also. an RST5. Therefore. TRAP Interrupt 8228 System Controller Three separately rnaskable interrupts that generate Input/output lines for serial data transfer Programming for tile 8085 In the two new Instructions SIM and RIM. e . the TRAP interrupt uses this input. e . Includes the following: A single 5 volt power supply.

byte and 1·25 . the 8085 skips over the third instruction Skipping the unnecessary byte allows for faster execution. Assembly Language and Processors Conditional Instructions Execution of conditional instructions on the 8085 differs from the 8080. The 8085 evaluates the condition while it fetches the second instruction immediately byte. If the specified condition fetches the next Instruction.Chapter 1. The 8080 fetches all three instruction bytes whether or not the condition is satisfied. is not satisfied.

.

the assembler treats all letters as though they were upper-case. < • • The digits 0 through 9. Each and directive must be entered on a single line terrnmated lines are possible. Controls are described m the operator's manual for your version of the assembler. directives (see Chapters 4 and 5) may have specific coding rules. are printed exactly as they were Input in the assembly listing. but the characters Internally. assembly language has certain coding rules.and lower-case letters are allowed. mstrucuons. as follows: . The following special characters: 2-1 . and controls. ASSEMBLY LANGUAGE CONCEPTS INTRODUCTION Just as the English language has its rules of grammar.Comment by any number of blanks. Even so. -. Specific instructions directives must conform to the general rules in this chapter. but you may have lines cons. The following characters • The letters of the alphabet. Character Set arc legal In assembly language source statements: A through Z. but must be separated by at least one delimiter. the coding of such Instructions SOURCE LINE FORMAT Assembly language mstrucuons Label:} { Name The fields may be separated Instruction conunuauon and assembler direcuves Opcode may consist of up to four fields. No entirely of comments. directives. (see Chapter 3) and and This chapter describes the general rules for coding source lines.sung by a carriage return and a line feed.2. This manual describes This assembler recognizes instructions three types of source lines: and directives. Both upper. The source line [S the assembly language equivalent of a sentence.

list defines Delimiters define the end of a . Delimiters . Notice that many delimiters are related to the macro feature explained In Chapter 5.ource a field. 2·2 . meaning to the assembler in that they function of a field.. any ASCII character Carnage Form Horizontal may appear return feed tab In in a string enclosed single quotes or in a comment.Chapter 2.ised for macros are shown here 50 that you will not accidentally use a delimiter improperly Refer to Char-ter 5 for a description of macros. Delimiters Certain characters have special statement. The following as delimiters. In addition. Assembly Lan luage Concepts Character + Meaning Plus sign Minus sign Asterisk Slash Comma Left parenthesis Right parenthesis Single quote * & Ampersand Colon Dollar sign Commercial Question Equal sign Less than sign Greater Percent than sign sign $ @ 'at' sign mark < % blank > Exclamation point Blank or space Semicolon Period CR FF HT . or a component the delimiters recognized by the assembler.

Assembly Language Concepts Characterts) blank Meaning Use field separator or symbol terminator one or more blanks comma separate operands in the operands field. > % pair of angle brackets delimit macro parameter contains commas or embedded also used to delimit a parameter percent sign delimit a macro parameter evaluated that is to be prior to substitution used to pass the as part of a macro might as a delimiter in macro definitions when exclamation point an escape character following character parameter otherwise when the character be Interpreted double semicolon delimiter for comments when the comment the macro is expanded is to be suppressed Label/Name Field An instruction label is a symbol name whose value is the location where the instrucSIX Labels are always optional.Chapter 2. list < . but the first character must be or the special characters '7' or '@' The label name must be terminated with a colon. including macro parameters pair of single quote characters ( .... A symbol used as a label can be defined only once in your program.) 2-3 . alphabetic A label may contain from one to alphanumeric characters. (See 'Symbols and Symbol Tables' later in this chapter.• J delimit a character string pair of parentheses delimit an expression CR HT carriage return horizontal semicolon colon tab statement terminator or symbol terminator field separator comment field delimiter delimiter for symbols used as labels delimit macro prototype parameters text or formal & ampersand for concatenation text which blanks. tion is assembled.

when two operands the destination (as in data of the operation's and the second operand Examples: MO".'B' . Operand Field field identifies the data to be operated the first operand the source on by the specified identifies data. with a blank rather Names follow the same coding rules as labels. each of which 2-4 . and MACRO directives. opcode. your program. specifies As a general rule.Chapter 2. Assernblv Language Concepts Alphanurneri.MOVE B TO ACCUMULATOR Comment Field comment field may contain the comment the readability any information from the previous of the comment. comments program.MOVE CONTENTS OF REG C TO ACCUMULATOR . Ot ners require and arithmetic one or two operands.nd ENDM directives.C A.. A name is required except for the SET. the question mark character. However. operations). spaces are you should no need to separate used to improve use them lib erallv since it is easier to debug and maintain a well documented CODING OPERAI~D FIELD INFORMATION There are four types of information operand field. you deem useful for annotating by a semicolon. the information (a through d in the following list) that may be requested is described below. field must be empty for that t ley must be terminated than a colon. is a delimiter. as items in the may be specified in nine ways. EQU. and the decimal digits 0 throi gh 9. MV A. Although field with one or more spaces. The label/name the LOCAL . Opcode Field field contains the mnemonic operation code for the 8080/8085 instruction or assembler directive This required to be perforned. transfer result. The The optiona there IS only coding requirement commonly for this field is that it be preceded Because the semicolon are always optional. Some instructions are required (or target) require no The operand operands. characters include the letters of the alphabet.

15D Comment . stand alone. Comment . or binary Any number not specifically as hexadecimal.LOAD OCTAL 72 INTO ACCUM Binary Data.WITH OF6H 2·5 . Each decimal statements D immediately octal. Assernblv language Concepts OPERAND Information (a) (b) (c) (d) Register Register Immediate Pair Data required FIELD INFORMATION Ways of specifying (1) (2) (3) (4) (5) (6) (7) (8) (9) Hexadecimal Decimal Data Octal Data Binary Location Data Counter ($) values or data Data 16-bit Address ASCII Constant Labels assigned Expressions Labels of instructions Hexadecimal Data. followed Each hexadecimal H.OBAH may be identified identified by the letter Comment . Thus. Each binary Label NOW: number must be followed by the letter B.LOAD E WITH 15 DECIMAL Octal Data.LOAD REG C WITH HEX BA after its last digit or may is assumed to be decimal. Comment .LOAD REGISTER D Opcode MVI Operand D. the following Label ABC: are equivalent: Opcode MVI MVI Operand E.72Q 0 or the letter Q.l1l1 011 OB .Chapter 2.15 E. Each octal number Label LABEL: must be followed Opcode MV! by the letter Operand A. Oocode MVI number number must begin with a numeric digit (0 through 9) and must be by the letter Label HERE: Operand C. Dectrnal Data.

abe! -jERE: or Data. to an Instruction Instructions or a data definition in the program has as its value the can refer to this of tile first byte of the instruction label name.9FH D. The location counter contains the wher ~ the current label (. successive One or more ASCII characters enclosed in single quotes define an ASCII constant. All of the operand types discussed counter previously can be combined by operators to form an expression. Operand D. nguage Concepts Location address Counter.j UMP TO ADDRESS .0: will be assembled.LOAD E REG WITH 8-BIT ASCII A TION OF MYI DATE: DB 'TODAY"S DATE' .THE FIRST . further discussion of expressions is deferred until later in this chapter.jUMP TO INSTRUCTION AT THERE fHERE.INSTRUCTION 6 BYTES BEYOND BYTE OF THIS ASCII Const tnt.YALUE can assign values to labels.REPRESENT * Labels Assig led Values. assume that VALUE The SET and EQU directives the value 9FH.9FH Expressions. Because the rules for coding expressions ($+6) IS an expression that combines are rather extensive.Chapter 2. Opcode jMP elsewhere Operand THERE Comments . Two single quotes iabel must be used to represent Opcode one single quote Within an ASCII constant. MVI D.\L . the location counter In fact. The $ character instruction Opcode jMP refers to the current or data statement Operand $+6 location counter. the example given for the location with the deiirnal number 6. Comment . has been assigned Opcode are equivalent: . The label assigned or data. 2·6 .\2: MYI MYI Labels of ln ttructton address address by I:S symbolic . the two statements Comment In the following example. Assembly L. Operand Comment .

TWO'S COMPLEMENT REPRESENTATION OF DATA combinations of zeros and ones. Also. are flagged as errors. that is strongly Register-Type Expressions Operands. and actual parameters in can be assigned names only by EQU or SET. cuits are required. arithmetic the computer 2-7 . of a of in of decimal are in the 'two's arithmetic: complement' Arithmetic format. to the minuend (the top number). above defines a byte with the value 81 H (the object program modifies is typically used where the object itself during execution. a technique Such The statement coding discouraged. then add one to the result to form the ten's complement. The ability to perform subtraction with a form of addition operations within is a great advantage are binary. 99-12=87. containing Only instructions register-type jMP A operands that allow registers as operands may have register-type like operands.Chapter 2. the decimal as an instruction as the hexadecimal 00011111. Thus. One operand type was intentionally may appear omitted from the list of operand field. Registers directives that may contain alternate register-type operands are EQU. or simply combination (Rotate the bit may Any 8-bit byte contains be interpreted Accumulator pattern one of the 256 possible of ways. To understand why. The only assembler macro calls. Carry). For example. instructions assume that the data bytes upon which they operate two examples 35 +88 123 are equal if we disregard illustrates subtraction the carry out of the high order position by adding the ten's complement To form the ten's complement the ten's complement in a computer which simplifies of 12. in a number Right Through the code 1 FH may be interpreted value 1 F. The operand field infor- Instructions enclosed in parentheses instruction. from 9 to form the nine's complement. each digit of the subtrahend Thus. an instruction is flagged as an illegal use of a register. let us first examine 35 -12 23 Notice that the results of the two examples example. SET. Opcode DB in the operands has the value of byte of the assembled Label INS: Operand (ADD C) code for an ADD C instruction). since fewer cirmatters even more. Any particular value 31. Assembly Language Concepts Instructions mation: the left-most as Operands. The second example (the bottom first subtract number) the second decimal performed the subtrahend number. 87+1=88.

. adding one tc the result. so :hat it can be used as a 'borrow' St> the carry flag IS set OFF. number. bec. 1 2 = 000011 -35 flag in multibyte By contrast. by dis 'egarding addition. It must also be stated r rogramrning consider responsibility. the processors the carry flag at the end of a subtract 35 from p. high order Your program The compare logic considers number only the raw bit values of the higher than a positive of the flags set by As an exarnpe. the carry flag would In the example shown. 00 the carry flag IS set ON if we subtract 00001100 = 0010 0011 = + 11 01 11 00 +1101 1101 1110 1001 1101 1101 IS required = 233 or --105 In this case. are reversed. Assembly Larguage Concepts The processoi the subtractic forms n shown the two's complement previously 35 -12 23 of a binary value simply by reversing the value of each bit and then is formed. seven low order bits provide At the begrnuing of data is a Thus. at the end of the subtraction. complement number. you must again form its two's complement: 0110 1 = + 0001 0001 Two's compl-iment the high order numbers 0111 = 23 15 may also be signed. if any form. operation IS required.Chapter 2. 0111 arithmetic. 2-8 . The bit indicates a one a negative number. Thus. Therefore. the compare instruction a negative two's complement always compares the negative bit IS always ON. When a byte the sign. number's instruction. If you want th he absence 0 0 of a carry indicates that a borrow from the next higher order is stored byte. the subtraction IS performed through a form of be set OFF no borrow if this operation by the 8080 or the 8085. Hov/ever. complement subtractions. Notice this result as a decimal 1110 1001 also that the result In a complemented value. the meanings must account for this condition. the carry out of the high order were performed This is because position. Any carry out of the high order is performed 0010 0000 0011 1100 as follows: bit is ignored when the complement = = 00100011 = + 1111 0011 +11110100 1 0001 0111 = 23 1111 01 00 Again. Interpreted a positive as a signed two's number. the compare Therefore. A zero In this bit indicates the magnitude of the number. As a result. processor Interpret sets the carry flag ON.use Items being compared. 1111 equals +127 it was stated that any 8-blt byte may conthat the proper Interpretation of this description of two's complement tain one of tie 256 possible combinations of zeros and ones.

Note that you do not have to assign values to symbolic addresses. the following analogy may help clarify the distinction If you have never done symbolic programming between a symbolic and an absolute address. The mnemonic names for machine instructions and the assembler directives are all reserved 2-9 . The content of the post office box can be accessed by a fixed. The locations in program memory can be compared rents box 500 for two months.) these addresses for you.' If Donald Smith later rents box 500. Reserved. Assembly Language Concepts SYMBOLS AND SYMBOL TABLES Symbolic Addressing before. In variable name. The assembler performs the same function. reserved or user-defined. by the assembler The assembler regards symbols as having the following attributes: permanent or redefinable. the command ]MP $+6 Symbols of the forces a jump to the instruction form '??nnn' are generated residing six memory locations higher than the ]MP instruction. (The location counter does for the assembler what the program counter or operand does for the microcomputer. The assembler references its location counter instruction during the assembly process to calculate is to be placed in memory. symbols. global or limited. absolute address (500) or by a symbolic. and absolute or relocatable. User-Defined. to a cluster of post office boxes. The postal clerk correlates the symbolic names and their absolute values his log book. It tells the assembler where the next Symbol Characteristics A symbol can contain one to six alphabetic or the special character location counter '7' (A·Z) or numeric (0-9) characters (with the first character alphabetic) in the or '@'.Chapter 2. to uniquely name symbols local to macros. Suppose Richard Roe He can then ask for his letters by saying 'Give me the mail in box 500: or 'Give me the mail for Roe. he too can ask for his mail by either box number 500 or by his name. keeping track of symbols and their values in a symbol table. and Assembler-Generated Symbols cannot appear as Reserved symbols are those that already have special meaning to the assembler and therefore user-defined symbols. A dollar sign can be used as a symbol to denote the value currently For example.

only within a macro definition because or within a call to that macro.imied Most symbol. SET. Assembly Lan. Symbols This means that they have meaning name RTN to a routine. have given rm rluple definitions Certain 'local' multiple program. 2-10 . are global. may be used many these symbols times in the cause are If you assign the symbolic throughout your program. to the same name. are created by the assembler to replace user-defined symbols whose scope is limited 4. that you assij n the symbolic point in your program. rouune.Chapter 2. definitions Macros require local symbols names. or MACRO Assembler-get era ted symbols to a macro d. about the same macro If tile symbolic names Within macros were global. finition.tuage Concepts The following instruction Symbol operand symbols are also reserved: Meaning Location counter reference pair Band C A B Accumulator Register Register Register Register Register Register Program Memory C register B or register D or register E H or register L register C D E H L SP PSW M STACK MEMORY pair D and E pair Hand L Stack pointer status word (Contents reference feature feature of A and status flags) in Hand L code using address Special relocatabilitv Special relocatabilitv NOTE The STACK and MEMORY in Chapter User-defined' defined directives vrnbols are symbols 4 and 5). These symbols are symbols are fully discussed you create when they appear (see Chapters in the label field of an instruction or In the name field of EQU. each use of the macro (except the first) would for those symbolic information See Chapter -. to reference Instruction and data addresses. for example. svmbils have meaning You may then code a jump or a call to RTN from any an error results since you name RTN to a second to the macro. Assume. for additional macros. Global and l.

LlST+6 the second. logical operations. Symbols with becomes important when Symbols with addresses that change during relocation as will be explained addresses that do not change during relocation the symbols are used within expressions. may be absolute For the sake of readers who do not require the should read all the feature. Assembly Language Concepts Permanent and Redetinab!e Symbols since their value cannot change during the assembly operation. and operators.Chapter 2. defined registers A through L. program module. External symbols are those used in the current Such symbols must appear in an EXTRN statement. Assume. LlST+l 2-11 . but defined In another or the assembler will flag them as undefined. part of your program. Absolute and relocatable symbols may both appear in a relocatable E. instruction operations: arithmetic it and byte Isolation operations. Hand module. relative to memory to some other set of memory symbols. and so on. These programs are later relocated are relocatable are absolute Relocatable programs are An important assembled locations. that your program defines a list of ten con- loads the address of the seventh item in the list Into H. relocation following. symbols. ASSEMBLY-TIME An expression Expressions. It is important Once the assembler has evaluated an expression. the following the Hand L registers: LXI which permit the following assembly-time compare operations. Notice that LIST addresses the first item. However. like symbols. PSW. The addresses for these symbols are resolved when the modules are bound together. absolute expressions are described first. shift operations. to keep in mind that these are all assembly-time becomes a permanent stants starting at the label LIST. and M are absolute since they refer to hardware But these references are valid in any module. Only symbols Most symbols are permanent defined with the SET and MACRO assembler directives are redefinable. program module. References to any of the assemblerlocations. Absolute and Relocatable attribute Symbols of symbols with this assembler is that of relocatability location zero. Each element of an expression is a term. External symbols. program linkage when several relocatable program modules are bound together program. Conversely. operations. for example. SP. These symbols are required to establish to form a single application module. users of relocation Operators The assembler Includes five groups of operators operations. or relocatable. This distinction later. but may be accessed by other PUBLIC symbols are defined in the current modules. and public symbols are special types of relocatable symbols. EXPRESSION EVALUATION IS a combination of numbers.

The shift operators do not bits shifted operator of the operation Example: Assume are zero-filled. Assembly Lan ruage Concepts Arithmetic The Open tors operators are as follows: Meaf1l1lg Unary Unary or binary or binary addition subtraction is discarded an error. causes MOD Modulo.Chapter 2.e MOD operator must be separated NUMBR from ItS operands by spaces: MOD 8 evaluates to the value Assuming tha . Notice the shift be separated ItS operands that NUMBR has the value 0101 0101. anthrnen- Operator + * Multiplication Division. The effects SHR SHL of the shift operators is as follows: NUMBR NUMBR 0001 0101 1010 1010 2-12 . division is the remainder (7 MOD Examples: The Iollowrng expressions generate the bit pattern for the ASCII character A. the previous expression Shift Operators shift opeators are as follows: Operator y SHR y SHL x x wraparound that any Meaninq Shift Shift operand operand out must The 'v ' to the right 'x ' bit posiuons. 5+30*2 (25/5)+30*2 5+( -30*-2) Notice that tl. NUMBR has the value 25. left 'x ' bit posiuons. Bit positions from vacated by the shift by spaces. caused by a 3=1) (7/2=3). Division Any remainder by zero Result operation. 'v' to the byte.

bit of values involved These directives are commonly are fully explained the IF is assembled only if the condition least significant bit position. act only upon the least Significant used In conditional IF directives. Assembly Language Concepts Notice position that a shift one bit posiuon to the right has the effect to the left has the effect of dividing a value by two. a shift one bit Logical Operators The logical operators are as follows: Operator NOT AND OR XOR The logical operators operators Example: The following IF directive tests the least significant IS TRUE. IF FLDI that all three fields must have a one bit in the AND FLD2 AND FLD3 Compare Operators The compare operators are as follows: Operator EQ NE LT LE GT GE NUL Meaning Equal Not equal Less than Less than or equal Greater Greater than than or equal used to test for null (missing) macro Special operator parameters 2·13 . these in Chapter 4. of multiplying a value by two. The assembly language code that follows Meaninq Logical one's complement Logical AND (=1 if both ANDed ORed bits are 1) bit is 1) Logical OR (=1 if either Logical EXCLUSIVE OR (=1 if bits are different) in the operation. bit of three This means Items.Chapter 2. Also.

When neither as 16·bit addresses. if the evaluation negative of the relation operations number is TRUE. are commonly used in conditional NUL is described IF directives. a two's complement than a two's complement positive number Relational are based strictly tude comparisons bit) is g 'eater (which always has a one in its high {which always has a zero in its high order bit}. Any program argument segment containing a symbol used as the only on of a HIGH operator should be located described a page boundary.e compare operators applies only to the macro feature. you need to deal only with a part of an of the HIGH and LOW operators._ operator The compare Chapter Notice Example: The following TRUE. 2-14 object code is relocated carry flag will be lost. Thus. If false. Thus. of bit values. the code is skipped is over. This is done using the PAGE option in Chapter byte and the from the low-order with the CSEG or DSEG directives 4. These directives operator must be separated from its operands by spaces. the LOW operator and Issues an error message. This IS the function treats all external expression and relocatable The assembler's these symbol. the value of the on magni- is all ores. Assernblv Lan guage Concepts The compare result order operators Yield a yes-no result. tests the values of FLDl coding following and FLD2 for equality. of an Immediate assumes NOTE HIGH or LON operator which byte of the address the assembler IS to be used of the expression. in Chapter 5. the value of the result is all zeros. Carries are not propagated when the assembler flag is O. Using PAGE ensures that this . In an 8-bit value. If the result of the comparison Otherwise. symbols instruction. that tl.Chapter 2. IS assembled. In certain cases. or Y<lU treats expressions need to generate relocation appears operator feature as l ti-bit addresses. are fully explained in Since the NU. IF directive 4. the assembly language the I F directive IF FLDl EO FLD2 Byte Isolation Ooerators The byte isol uion operators are as follows: Meaning Isolate high-order Isolate low-order 8 bits of 16·bit value 8 bits of lfi-bit value. Operator HIGH LOW The assemble' address. It must be preceded the evaluation When one of by either the in the operand to specify is present.

are nested. can be used to override normal rules of precedence. thus indicating that the address is still less than 256: IF HIGH ADRS EQ 0 Permissible Range of Values Internally. so these values are evaluated range of values is OH through OFFFFH. Certain Instructions of these instructions operations are performed for two-byte no overflow detection require that their operands through yields an out-of-range be an eight-bit value. 16-bit value. the assembler treats each term of an expression All arithmetic The assembler performs as a two-byte. enclosed In paren- theses is evaluated first. the Innermost =5+2=7 The part of an expression are evaluated first. the maximum using unsigned two's complevalues. operands are flagged as errors. The assembler generates an error message if an expression value. The only assembler directives that may contain register-type operands are EQU. Precedence of Operators left to right. Parentheses precede or follow them. ment arithmetic. When two operators have equal precedence. Expressions for these instructions must for one yield values in the range -256 +255. modulo 64K. If parentheses 15/3 + 18/9 15/(3 + 18/9) = 15/(3 + 2) = 15/5 = 3 2-15 . SET. Registers can be assigned alternate names only by EQU or SET. The following IF directive determines is zero.Chapter 2. Assembly Language Concepts Examples: Assume that ADRS is an address manipulated at assembly-time for building tables or lists of items that must all whether the high-order byte of ADRS be below address 255 in memory. Operators with higher precedence are evaluated before other operators the left-most is evaluated Expressions are evaluated that immediately first. Thus. and actual parameters in macro calls. NOTE Only instructions register-type that allow registers as operands may have Expressions containing register-type operands.

/. LT. NE The relational. GT. LOW Multiplication/Division: Addition/Subtraction: Relational Operators: Logical NOT Logical AND Logical OR. SHR +. A reference to the location counter (specified D .Chapter 2. Relocatable Express ions t ie relocatabilitv of an expression requires that you understand of allowable is absolute a symbol the relocatability operators or relocatabie. is an A symbol defined absolute symbol. XOR *. as equivalent using the SET or EQU directive Relocatable • • • • til can be defined that appears defined a number of ways: IS in a label field when the DSEG or CSEG directive to a relocatable expression in effect is a relocatable is as equivalent symbols using the SET or EQU directive Tile special assembler STACK and MEMORY are relocatable.EG directive is in effect. MOD.(unary and binary) EQ. LE. Assembly Lan tuage Concepts The following list describes • • • • • • o e the classes of operators expressions in order of precedence: Parenthesized NUL HIGH. svrnbols A symbol symbol. GE. . of each term used reduced. Determining in the express on.ABS RELOC+ABS _ ABS ABS [ HIGH ~ RELOC ~LOW ) RELOC + RELOC 2-16 r ~ \ HIGH} LOW f HIGH '1 LOW } ABS . A symbol reocatable. This is easier than it sounds But first it is recessarv Absolute • • svrniots since the number whether is substantially to know what determines two ways: can be defined that appears A symbol in a label field when the ASEG directive to an absolute expression is in effect is an absolute symbol. and HIGH/LOW operators must be separated from their operands by at least one blank. by the $ character) relocatable when the CSEG or The expressions ABS IS shown in the following and RELOC list are the only expressions IS that yield a relocatable result. SHL. logical. IS External symbols are considered relocatable. Assume that an absolute symbol a relocatable symbol: ABS + RELOC RELOC RELOC fHIGH'( \ LOW ) + ABS .

Operator X absolute Y absolute Y Y y A A A A A A A A A A A A A A A A A A A A A X absolute Y relocatable R I I I I I I I I I I I I I I I - X relocatable Y absolute R R I I I I I I I I I I I I I I I R R R I X relocatable Y reloca table I A I I I I I A A A A A A I I I X+ X X• XI X MOD X SHL X SHR X EQ X LT X LE X GT X GE X NE X AND X OR X XOR NOT HIGH LOW unary+ unary- y y Y Y Y Y Y Y Y Y y y Y X X X X X - 2-17 .RELOC2 EQ LT RELOCl LE GT GE NE Relocatable The following symbols may not appear In expressions combinations With any other of operators operators. Symbols with the same type of relocatabilitv.RELOC When two relocatable certain expressions symbols have both been defined result. An A in the an RELOC2 list shows all possible With absolute table indicates that the resulting address is absolute: an R indicates a relocatable address: an I Indicates illegal combination. both are relative to MEMORY.Chapter 2. Notice that only one term may appear With the last five operators in the list.100 is legal. or both are relative to STACK. The following expressions are val id and produce absolute results: RELOCl . but 100 . and relocatable terms. Assembly Language Concepts Remember is not. that numbers are absolute terms. have the same type of relocatability they may appear when both are In that yield an absolute relative to the CSEG location counter. Thus the expression RELOC . both are relative to the DSEG location counter.

Chapter 2. Assembly Language Concepts Chaining of Symbol Definitions The ISIS-II 81180/808S Macro Assembler is essentially a 2-pass assembler. Therefore.wo passes. y x EQU EQU y is legal. All symbol table entries must be resolvable in . but iii the series y Z x EQU EQU EQU y Z the first line s illegal as X cannot be resolved in two passes and remains undefined. 2-18 .

If you are reading this manual to learn about with Carry) to XTHL (exchange set in about particular of the processor and instruction of 8080 and 8085 Instructions. the processor can outrun for the memory to deliver the desired instruction Refer to the appropriate speed of the memory in your system. TIMING INFORMATION The instruction operating The 'state' descriptions in this manual do not explicitly state execution timings. your system. is complete The instruction descriptions are listed alphabetically Each description so that you are seldom required to look elsewhere for addition- the 8080 or the 8085. In applications manufacturer's 3·1 .. This reference format necessarily requires repetitive top of stack with Hand Chapter instructions. Notice that two sets of cycle/state is satisfied. the specified condition or data. When you begin to have questions look them up in this chapter. read the description 1 and the programming examples in Chapter 6.e. do not try to read this chapter from ACI (add immediate Instead. This is because the 8085 fetches the third instruction needed. L registers). wait can be significant. the processor must wait with critical timing requirements. This is because the basic speed of your processor depends on the clock frequency IS used in your system. With a fast the memory. A state may range from 480 nanoseconds When you know the that basic execution time by rnultiplving the basic unit of time measurement on the 8085) to 2 microseconds. INSTRUCTION SET HOW TO USE THIS CHAPTER This chapter is a dictionary for quick reference. al information.3. In for the processor. you can determine figure by the number of states required for the instruction. i. depending an instruction's (~20 nanoseconds length of a state on the clock frequency. literature In this case. for memory timing data. information. This basic timing factor can be affected by the operating clock cycle and a slow memory. this specifications are given for 8085 conditional byte only if it is actually call and jump instructions.

CY.ontents of the second instruction ADD IMMEDIATE byte and the carry bit to the contents WITH CARRY and of the accumulator stores the result in the accumulator. an ASCII constant. ADC then updates the setting of the carry flag to indicate the outcome 3-2 .AC the value 14H and that the carry bit is set to one. Data defined value. these symbols appears in the operand expression HIGH or LOlA operator When neither operator is present. Addressing. to specify which byte of the address is to be used in the evaluation the assembler assumes the LOW operator and issues an error message. The ADC insruction's use of the carry bit enables the program to add multi-byte numeric strings. Instruction Se: ACI ACI adds the . The instruction ACI 66 = 14H Carry = 42H 00010100 01000010 01010111 57H ADC ADD WITH CARRY The ADC ins! ruction adds one byte of data plus the setting of the carry flag to the contents The result istored of the operaton.P.S. The assemblers relocation feature treats all external and relocatable the label of a previously symbols as 16-bit addresses. Opcode ACI Operand data except. Flags: Example: Assume that the accumulator has the follov ing effect: Accumulator Immediate data contains 2 7 Immediate Z. for the carry bit. or an expression. The operand soecifies the actual data to be added to the accumulator may be in the form of a number. o 0 data o Cycles: States.Chapter 3. of course. The data may not exceed one byte. in the accumulator of the accumulator. of an immediate instruction. When one of It must be preceded by either the of the expression.

Carry 0 0 0 0 0 3-3 . and the carry bit is set to zero. Instruction Set Add Reqtster to Accumulator with Carry Operand reg E.CY. the accumulator as follows: 2 7 register indirect Z.Chapter 3. M is a symbolic reference Cycles: States: Addressing: Flags: Example: Assume that register C contains instruction ADC C performs 3DH.S.s.p. H or L.CY. adds the contents bit to the accumulator and stores the result in the accumulator. ISS SI Cycles: States: Addressings: Flags: Add Memory to Accumulator with Carry Operand M of the memory location addressed by the Hand L registers and the carry to the Hand L 4 register Z. This instruction adds the contents of the Opccde ADC The operand must specify one of the registers A through specified register and the carry bit to the accumulator and stores the result in the accumulator.AC contains 42H.AC Opcode ADC This instruction registers. The the addition 3DH 42H CARRY 00111101 01000010 o 01111111 = 7 FH The condition flags are set as follows: Carry Sign Zero Parity Aux.P.

P.P. States: Addressing: Flags: register Indirect Z. Instruction Set If the carry hit IS set to one.CY.Chapter 3. Carry ADD The ADD mtruction accumulator adds one byte of data to the contents of the accumulator.S. Iss 4 register sl Cycles: States: Addressing: Flags: Add From Memory Opcode ADD This mstrucuon adds the contents Operand M of the memory location addressed by the Hand L registers to the contents L registers. The result is stored in the but sets the flag to Notice that the ADD instruction excludes the carry flag from the addition ADD indicate the outcome of the operation. 11 0 0 0 0 2 7 M is a symbolic reference to the Hand Cycles. of Z. The instruction adds the contents of the The operand must specify one of the registers A through specified reg ster to the contents 11 of the accumulator 0 0 0 0 and stores the result in the accumulator.CY. the instruction 3DH 42H CARRY has the following results: 00111101 01000010 10000000 SOH 0 1 0 0 1 Carry Sign Zero Parity Aux.S. H or L.AC the accurnul itor and stores the result in the accumulator. Add Reqistet to Register Opcode ADD Operand reg E.AC 34 .

3-5 . The data may not exceed one byte.CY. Instruction Set Examples: Assume that the accumulator addition as follows: 2EH 6CH 9AH The accumulator contains 0010111 0 01101100 10011010 of the ADD D instruction. The assembler's the label of a previously the form of a number. Opcode ADI Operand data This data may be In ADD IMMEDIATE of the second instruction byte of the contents of the accumulator and stores the result The operand specifies the actual data to be added to the accumulator an ASCII constant. these symbols appears in the operand expression the HIGH or LOW operator When neither operator to specify which byte of the address is to be used In the evaluation is present.S. The contents of the D contains 6CH and register D contains 2EH. When one of instruction. relocation feature treats all external and relocatable of an immediate symbols as 16-bit addresses. flags are set as follows: o o The following instruction doubles the contents ADD A of the accumulator: ADI ADI adds the contents in the accumulator. or an expression. defined value. The Instruction ADD D performs the the value 9AH following execution The condition Carry Sign Zero Parity Aux.AC and Issues an error message. Carry register remain unchanged.P. it must be preceded by either of the expression.Chapter 3. the assembler assumes the LOW operator 000 data Cycles: States: Addressing: Flags: 2 7 immediate Z.

The result in tile accumulator.CY.AC 3-6 . a one bit In the result when the corresponding bits in either the test data or the mask data are OR produces a one bit only when the corresponding bits in the test data and the mask data are a one bit In the r. 001555 Cycles: States: Addressing: Flags: 1 4 register Z. OR produces ones. a one bit in either the test data or the mask data . Instruction Se Example: Assume that he accumulator contains the value 14H.Chapter 3. with Accumulator Opcode ANA The operand specified must specify one of the registers OR 1010 1010 0000 1111 1010 1111 EXCLUSIVE 1010 0000 1010 OR 1010 1111 0101 Operand reg A through E. Exclusive different: result.but not both .produces AND 1010 1010 0000 1111 0000 1010 AND Reqiste. ANDs the contents of the regi iter with the accumulator and stores the result 1 The carry flag is reset to zero. value 66 into the hexadecimal ANA ANA perforrrs IS placed Summary a logical AND operation using the contents LOGICAL AND WITH ACCUMULATOR of the specified byte and the accumulator. This Instruction in the accumulator.S. The Instruction 14H 42H 00010100 01000010 01010110 Notice that tile assembler converts the decimal ADI 66 has the following effect: Accumulator Immediate data = 56H value 42. H or L.P.e. of 'zoqtca] Operations s a one bit In the result only when the corresponding bits In the test data and the mask data are AN D product ones.

Chapter 3. Instruction

Set

AND Memory with Accumulator Opcode ANA This Instruction ANDs the contents Operand M of the specified memory location with the accumulator and stores the result

in the accumulator.

The carry flag is reset to zero.

o
Cycles: States: Addressing: Flags: Example: Since any bit ANDed with a zero produces

o

0
2 7 register Indirect Z,S,P,CY,AC

a zero and any bit ANDed

with a one remains

unchanged,

AND is

frequently used to zero particular groups of bits. The following example ensures that the high-order four bits of the accumulator are zero, and the low-order four bits are unchanged. Assume that the C register contains OFH: Accumulator C Register 11

o

o
o

0 0

OFCH OFH OCH

000 000 0

11

ANI
ANI performs a logical AND operation is placed using the contents

AND IMMEDIATE
of the second

WITH ACCUMULATOR
and the accumu-

byte of the Instruction

lator. The result

In the accumulator. Opcode ANI

AN I also resets the carry flag to zero. Operand data
In

The operand byte. The assembler's these symbols When neither

must specify

the data to be used

the AND operation. defined

This data may be in the form of a number, The data may not exceed one

an ASCII constant,

the label of some previously

value, or an expression.

relocation appears operator

feature to specify

treats all external expression

and relocatable

symbols instruction,

as 16-bit addresses. it must be preceded

When one of by either the

in the operand is present,

of an immediate assumes

HIGH or LOW operator

which byte of the address the assembler

is to be used in the evaluation

of the expression.

the LOW operator

and issues an error message.

3-7

Chapter 3. Instruction

Se :

o
data Cycles: States: Addressing: Flags: Summary of Loqtca! Operations

0

2 7 immediate Z,S,P,CY,AC

AND product s a one bit in the result only when the corresponding ones. OR produces ones. Exclusive different; result. AND 10lO 10lO 0000 1111 000010lO Example: The followin;. instruction IS used to reset OFF bit SIX of the byte ANI Since any bit ANDed instruction program uses individual with a one remains bits as status 1011111IB unchanged OR 10lO 10lO 0000 1111 10lO1111 a one bit in the result when the corresponding

bits

In

the test data and the mask data are

bits In either

the test data or the mask data are

OR produces a one bit only when the corresponding bits in the test data and the mask data are i.e. a one bit in either the test data or the mask data - but not both - produces a one bit in the

EXCLUSIVE 10lO 1010 0000 1111 10lO 0101

OR

In

the accumulator:

and a bit ANDed

with a zero is rest to zero, the ANI This technique IS useful when a

sl own above sets bit six OFF and leaves the others flags.

unchanged.

CALL
The CALL rrstructron program specified counter combines functions of. the PUSH and I MP Instructions. instruction) onto CALL pushes the contents

CALL
of the

(the address

of the next sequential

the stack and then [urnps to the address

in t re CALL instruction. or one of ItS variants return, implies the use of a subsequent RET (return) Instruction. When a

Each CALL Instruction call has no corresponding

excess addresses

are built up in the stack.

3-8

Chapter 3. Instruction

Set

Opcode CALL

Operand address (The label is most common.) The assembler

The address may be specified as a number, a label, or an expression.

inverts the high and low address bytes when it assembles the instruction. 1 1 0 0 1 1 0 1

low addr high addr Cycles: States: Addressing: Flags: Example: When a given coding sequence the sequence as a subroutine an application of two different calculations is required several times in a program, you can usually conserve memory by coding invoked by the CALL instruction or one of its variants. For example, assume that as a result of an operator input or because to drive the display can be included If the label DISPL Y is is used to invoke the 5 17 (18 on 8085) immediate/register none indirect

drives a six-digit LED display; the display is updated

that occur in the program. The coding required

in-line at each of the three points where it is needed, or it can be coded as a subroutine. assigned to the first instruction display subroutine: of the display driver, the following CALL instruction

CALL This CALL instruction control

DISPLY instruction onto the stack and then transfers or one of its of the effect of CALL and return

pushes the address of the next program The DISPL Y subroutine

to the DISPL Y subroutine.

must execute a return instruction

variants to resume normal program flow. The following instructions: CALL

is a graphic illustration

DISPL Y CALL ~

------DISPL Y

DISPL Y - - - - -

--- - -RET

CALL

Consideration

for Using Subroutines and the greater the number of repetitions, the greater the potential

The larger the code segment to be repeated memory savings of using a subroutine.

Thus, if the display driver in the previous example requires one hundred

3-9

Chapter 3. Instruction Se:

bytes, coding it In-line would require three hundred plus nine bvt ss for the three CALL instructions.

bytes. Coded as a subroutine,

it requires one hundred

bytes

Notice that subroutines require the use of the stack. This requires the application memory for
1 he

to include random access the system designer

stack. When an application

has no other need for random access memory,

might elect to) avoid the use of subroutines.

CC
The CC instruction address speciied continues combines functions of the [C and PUSH instructions. of the program counter

CALL IF CARRY
CC tests the setting of the carry flag. onto the stack and then jumps to the

If the flag is set to one, CC pushes the contents wi.h the next sequential Opcode CC Although the use of a label is most common, 1 1 0 instruction.

in bytes two and three of the CC instruction.

If the flag is reset to zero, program execution

Operand address the address may also be specified as a number or expression. 1 1 1 0 0

lowaddr high addr Cycles: States: Addressing: Flags: Example: For the sake of brevity. an example variants.
IS

3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) immediate/register none indirect

given for the CALL instruction

but not for each of its closely related

CM
The CM mstuction If the flag
IS

CALL IF MINUS
combines functions of the J M and PUSH instructions. of the accumulator CM tests the setting of the sign flag. are minus), CM pushes the contents If the instruction.

set to one (indicating counter

that the contents

of the progr.un

onto the stack and then iumps to the address specified by the CM instruction. simply continues Operand address with the next sequential

flag is set to zero, program execution Opcode CM

3-10

it becomes OAEH: 3-11 . Instruction Set Although the use of a label is most common. is given for the CALL instruction but not for each of ItS closely related 3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) immediate/register none indirect CMA CMA complements unchanged. Opcode CMA Operands are not permitted with the CMA instruction. 1 1 1 the address may also be specified as a number or an expression. an example variants. been executed. 1 1 1 0 0 lowaddr high addr Cycles: States: Addressing: Flags: Example: For the sake of brevity. when complemented 51H OAEH 01010001 10101110 by CMA. Operand each bit of the accumulator to produce COMPLEMENT ACCUMULATOR the one's complement. Example: Assume that the accumulator o 4 none of the accumulator after the CMA instructions has add one to the contents contains the value 51H. All condition flags remain 10 0 Cycles: States: Flags: To produce the two's complement.Chapter 3.

Call.Chapter 3. a No carry indicates that the accumulator IS carry indicates that the accumulator less than the byte. or Return instructions.ROTATE BIT 7 INTO ACCUMULATOR :RETURN Itefore returning rotates whether a subroutine is called. the subroutine CMP CMP cornpar es the specified byte with the contents carry and zero flags. Instruction SI t CMC COMPLEMENT CARRY If the carry flag equals zero. flags using one of the conditional Jump. the prothe flag byte using the following 1 4 CYonly bit 7 into the carry flag.SET BIT 7 OFF . recomplernents 3·12 . when the values have different The program tests the condition example. If the carry flag is one. For JZ (jump if Zero) tests for equality Description: are performed by subtracting the specified byte from the contents uses two's complement of the accumulator. of the accumulator COMPARE WITH ACCUMULATOR and Indicates the result by setting the remain unchanged. However. The values being compared The zero fla. All other flags remain unchanged. code: CMC RAR RET . is greater than the specified byte. the meaning of the carry flag is reversed signs or one of the values is complemented. CMC sets it to one. To test the bit. and executes a CC (Call if Carry) reinitializes to the calling program. uses the processor's addition. Opcode CMC Operands are not permitted with the CMC instruction. indicates equality. instruction. This subtraction Because subtraction the carry flag generated by the subtraction. CMC resets it to zero. which Functional Comparisons IS why the zero and carry flags indicate the result. internal registers the CMP instruction so that source data is preserved. Operand 10 0 Cycles: States: Flags: Example: Assume that a program uses bit 7 of a byte to control gram loads the byte into the accumulator.

Chapter 3. The operand must name one of the registers A through S Cycles: States: Addressing: Flags: Compare Memory with Accumulator Opcode CMP This instruction contents compares the contents Operand M of the memory 4 register s sl Z.AC the value OAH and register E contains {remember that subtraction the value OSH. M is a symbolic reference Cycles: States: Addressing: Flags: Example 1: Assume that the accumulator CMP E performs the following addition}: Accumulator +(-E Register) contains 2 7 register indirect Z.CY. Instruction Set Compare Register with Accumulator Opcode CMP Operand reg E.P.S.P.CY. The instruction is actually two's complement internal subtraction 00001010 11111011 00000101 +{-carry} operation. both the zero and carry bits are zero. After the carry is complemented thus indicating A greater than E. H or L. Example 2: Assume that the accumulator to account for the subtract contains the value -1 BH and register E contains OSH: 11100101 11111011 111 00000 +( -carry) Accumulator +{-E Register} 3-13 .AC location addressed by the Hand to the Hand L register pair.S. L registers with the of the accumulator.

Instruction S:t After the ClIP Instruction this indicate. Opcode CNC Although counter the stack and thenjumps simply continues by the CNC instruction. of the accumulator execution CALL IF NOT ZERO CNZ tests the setting specified of the zero the that the contents are other than zero). CNC The CNC in: truction to the addres combines functions of the )NC and PUSH instructions. program simply continues with the next sequential as a number or an expression.Chapter 3. The user program is responsible interpretation of the carry flag. both the carry flag and zero flag are zero. Operand address the address may also be specified of . Opcode CNZ Although th e use of a label is most common.ies have different signs. If the fag is off (indicating contents second instruction. 3-14 . counter functions onto of the) NZ and PUSH Instructions. variants. Normally than register E. th. CNZ pushes in the Instruction's the stack and then jumps to the address If the flag is set to one. 1 1 0 low addr high addr Cycles: States: Addressing: Flags: Example: For the sake of brevity.he program and hird bytes. the contents of the program IS CALL IF NO CARRY CNC tests the setting onto execution of the carry flag. program Operand address the address 1 0 1 may also be specified 0 0 as a number or an expression. recomplements the carry flag. the meaning for proper of the carry flag IS that the accumulator is greater reversed since the val .: use of a label is most common. If the flag set to one. CNC pushes specified with the nes t sequential instruction. If the fag is set to zero. However. an example IS 3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) immediate/register none Indirect given for the CALL instruction but not for each of its closely related CNZ The CNZ In: tructron combines flag.

program execution simply continues with the next sequential instruction. is given for the CALL instruction but not for each of its closely related 3 or 5 (2 or 5 on 8085) 1. If are positive).1 or 17 (9 or 18 on 8085) immediate/register none indirect CP The CP instruction combines features of the J P and PUSH instructions. 1 0 1 0 0 low address high addr Cycles: States: Addressing: Flags: Example: For the sake of brevity.Chapter 3. CP pushes the contents of If the flag the flag is set to zero (indicating the program counter onto the stack and then jumps to the address specified by the CP Instruction. is set to one. Instruction Set 1 1 0 0 0 1 0 0 lowaddr high addr Cycles: States: Addressing: Flags: Example: For the sake of brevitv. that the contents of the accumulator CALL IF POSITIVE CP tests the setting of the sign flag. an example variants. Opcode CP Although the use of a label is more common. an example variants. is given for the CALL instruction but not for each of its closely related 3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) immediate/register none indirect 3-15 . 1 1 1 Operand address the address may also be specified as a number or an expression.

a: a carry Indicates that the accumulator is less than the immediate data. The parity flag is set to one to are useful for testing the parity of input data.Chapter 3. the meaning of the carry llag is reversed when the values have different Opcode CPI Operand data signs or one of the values is complemented. 3-16 . an example variants. is given for the CALL instruction but not for each of its closely related CPI CPI compare. the contents of the second instruction byte with the contents COMPARE IMMEDIATE of the accumulator and sets the zero and carry flap to indicate the result. If the flog is set to one.. CALL IF PARITY EVEN has an even number of one bits. of the accumulator are greater than the No carry indicates that the contents da . Opcode CPE Although the use of a label is more common. The values being compared The zero flag Indicates equality. program execution the address may also be specified as a number or an expression. CPE tests the setting of the parity onto the stack and then iurnps simply continues flag. 1 1 1 Operand address of the program counter If the flag is set to zero. CPE pushes the contents to the addres: specified by the CPE instruction. However. Instruction Sei CPE Parity is even if the byte in the accumulator indicate this condition. However. 0 1 1 0 0 lowaddr high addr Cycles: States: Addressing: Flags: 3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) immediate/register none Indirect Example: For the sake rf brevity. the contents The ePE instr uction combines of the J PE and PUSH instructions. immediate remain unchanged. The flags can be set without altering the data by The CPE and CPO instructions of the accumulator. functions the IN instruc tion does not set any of the condition adding OOH t. flags. with the next sequential instruction.

an ASCII The data may not exceed one byte.P.AC CPO Parity is odd if the byte in the accumulator indicate this condition. Opcode CPO Although the use of a label is more common. Instruction Set The operand must specify the data to be compared.Chapter 3. The parity flag is set to zero to are useful for testing the parity of input data. However. CPO tests the setting of the parity simply continues flag. This data may be in the form of a number. does not set any of the condition adding OOH to the contents The CPO instruction combines functions of the J PO and PUSH instructions.S. the IN instruction CALL IF PARITY ODD has an odd number of one bits. to specify which byte of the address is to be used In the evaluation the assembler assumes the LOW operator and issues an error o data Cycles: States: Addressing: Flags: Example: The instruction CPI 'C' compares the contents of the accumulator to the letter C (43H). constant. When one of instruction. with the next sequential instruction. 0 0 1 0 0 lowaddr high addr Cycles: States: Addressing: Flags: 3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) immediate/register none 3-17 indirect . symbols as 16-bit addresses. program execution the address may also be specified as a number or an expression. 1 1 1 Operand address of the program counter onto the stack and then jumps If the flag is set to one. message.CY. relocation feature treats all external and relocatable of an immediate The assembler's these symbols appears in the operand expression the HIGH or LOW operator expression. When neither operator is present. If the flag is set to zero. or an expression. The flags can be set without altering the data by The CPO and CPE instructions of the accumulator. CPO pushes the contents to the address specified by the CPO instruction. it must be preceded by either of the the label of a previously defined value. flags. 2 7 register Indirect Z.

CZ pushes than zero). of the accumulator are other CZ tests the setting are zero). 1 I 0 may also be specified 0 0 as a number or an expression. vanants. Opcode DAA Operands are not permitted with the DAA mstruction. In multi-byte whose function typically is coded requires use of the auxiliary after the arith- the DAA instruction immediately metic instruc lion so that the auxiliary 3-18 carry flag is not altered unintentionally.Chapter 3. variants. an example IS given for the CALL instruction but not for each of its closely related 3 or 5 (2 or 5 on 8085) 11 or 17 (9 or 18 on 8085) Immediate/register none indirect DAA The DAA mstrucuon digits. operations. Operand address the address 0 1 1 specified in the CZ Instruction. Instruction Sf t Example: For the sake of brevity. lowaddr high addr Cycles: States: Addressing: Flags: Example: For the sake of brevity. program of the zero flag. the contents execution of If the flag simply If the flag IS set to one (indicating IS set to zero (indicating wi: h the next that the contents the stack and then lumps to the address that the contents sequential Opcode CZ of the accumulator Instruction. an example is given for the CALL Instruction but not for each of its closely related CZ The CZ instriction the program continues :ounter combines onto functions of the CALL IF ZERO IZ and PUSH Instructions. decimal arithmetic numbers. . Although the use of a label is most common. It is the only instruction Operand adjusts the eight-bit value in the accumulator DECIMAL ADJUST ACCUMULATOR to form two four-bit binary coded decimal DAA IS used when adding carry flag.

the Instruction CY AC 1011 0110 0001 o 1001 0000 1010 = A1H than nine. Instruction Set DAA operates as follows: 1.P. the instruction adds SIX Now that the most significant bits have a value greater CY 1 1010 0110 0000 AC 1 0001 0000 0001 contains to them: When the DAA has finished. the accumulator program. DAA adds six to the accumulator. If the least significant four bits of the accumulator carry flag is ON. IS carry flags are set ON. or if the carry ON. If the most significant four bits of the accumulator flag IS have a value greater than nine.AC the value 9BH as a result of adding 08 to 93: AC o 0 1001 0000 1001 0011 1000 1011 = 9BH adds six to contents of the accumulator: Since OBH IS greater than nine. or if the auxiliary have a value greater than nine. o Cycles: States: Addressing: Flags: Example: Assume that the accumulator contains CY 0 4 register Z. 2. Instruction Notice that the carry flag setting is 3-19 .S.Chapter 3. DAA adds six to the most significant four bits of the accumulator. The program IS the value 01 in a BCD format. both the carry and auxiliary is 101. the carry flag that alters the flag. Since the actual result of this addition responsible lost as soon as the program executes any subsequent probably significant to the for recovering and using this information.CY.

Chapter 3.OOH SP SAVSP .GET SP INTO H&L . Decrement I 'eqister Opcode routines for decrementing Operand reg DCR 3-20 . Instruction S et DAD DAD adds the 16-bit value in the specified register pair to the contents is stored in Hand L.STORE SP IN MEMORY L registers except when the operation causes a carry The instruct on DAD H doubles the number in the Hand out of the I. DCR affects all the condition arithmetic DECREMENT flags except the carry flag. or the SP (Stack Pointer) register pairs to the contents of H& L. H&L.register. DAD sets th ~ carry flag ON if there is a carry out of the Hand flags other han carry. DCR DCR subtrai ts one from the contents of the specified byte. Opcode DOUBLE REGISTER ADD of the Hand L register pair. H. Because DCR preserves the carry flag. it can be used within multi-byte character co rnts and similar purposes. D&E. No ice that the letter H must be used to specify that the H& L register pair is to be added to Itself. The result Operand DAD DAD may add only the contents of the B&C. DAD affects none of the condition 10 0 Cycles: States: R P 3 10 o 0 11 Addressing: Flags: Examples: The DAD intrucnon register CY provides a means for saving the current contents LXI DAD SHLD of the stack pointer.CLEAR H&L TO ZEROS . L registers.

M is a symbol ic reference to the Hand L registers.S.DECREMENT CONTROL COUNTER :REPEAT LOOP UNTIL COUNTER=O LOOP: This example also illustrates an efficient programming technique.AC The DCR instruction is frequently used to control multi-byte operations such as moving a number of characters from one area of memory to another: MVI LXI LXI MOV STAX DCX DCX DCR jNl B.M D D M B LOOP . Instruction Set The operand must specify one of the registers A through E.DECREMENT SOURCE ADDRESS .LOAD H&L WITH SOURCE ADDR .S. This technique avoids the need for a compare instruction and therefore conserves both memory and execution time. Notice that the control counter is decremented to zero rather than incremented until the desired count is reached. 3-21 . 10 0 Cycles: States: Addressing: Flags: Example: o o 3 10 register indirect l.LOAD D&E WITH DESTINATION ADDR .Chapter 3. 100lDDD Cycles: States: Addressing: Flags: Decrement Memory Opcode Operand M 0 5 (4 on 8085) register l.260H D.900H A.AC DCR This instruction subtracts one from the contents of the memory location addressed by the Hand L registers.SET CONTROL COUNTER .P.LOAD BYTE TO BE MOVED :STORE BYTE .5H H. H or L.P. The instruction subtracts one from the contents of the specified register.DECREMENT DESTINATION ADDRESS .

performs DCX a borrow from the H register te produce the value 97FFH. DI The interrur t system is disabled when the processor recognizes an interrupt of a DI insn uction. 3-22 . Because DC.: preserves all the flags. D&E. 10 0 Cycles: States: R P o 5 (6 on 8085) register none Addressing: Flags: Example: Assume that the Hand considers th« contents L registers contain the address 9800H when the instruction of the two registers to be a single 16·bit value and therefore DCX H is executed. H&L. it can be used for address modification relies on the passing of the flags. at the beginning of the code sequence. Notice that the letter L pair. Opcode Operand sequence that DCX DCX may decrement only the B&C. or the SP (Stack Pointer) register pairs. In applicaticns interrupted. Opcode DI code sequences become inaccurate when interrupted. DCX affects none of the condition in any instruction flags.ents the contents DECREMENT REGISTER PAIR of the specified register pair by one.Chapter 3. between the pointer H must be used to specify the Hand Exercise carl' when decrementing and the actual contents the stack pointer as this causes a loss of synchronization of the stack. Instruction Stt DCX DCX decrerr. Because you cannot For example. the DI instruction is commonly DISABLE INTERRUPTS or Immediately following execution used only when a code sequence must not be You can disable code sequence. at the end of the time-dependent system by including a DI instruction predict the occurrence include an EI instruction Operand Operands an not permitted with the DI instruction. time-dependent of an interrupt. the interrup that use interrupts.

Example: The EI instruction begins operating is frequently used as part of a start-up sequence. Instruction Set I' Cycles: States: Flags: 0 . including TRAP can interrupt EI The EI instruction enables the interrupt system following execution to allow interrupt the interrupt system is delayed one instruction before a subsequent interrupt is acknowledged. Operand Operands are not permitted with the EI instruction. In applications interrupt interrupt. to return to the main program system is usually disabled only when the processor accepts an You can disable the interrupt system by including of an Because you cannot predict the occurrence or when a code sequence must not be interrupted. This special interrupt is intended for serious problems that must be serviced regardless of the interrupt flag such as power failure or bus failure. address. This special interrupt is intended for serious problems that must be serviced regardless of the flag such as power failure or bus error.1 none NOTE The 8085 TRAP interrupt interrupt cannot be disabled. no interrupt the execution of the 01 or EI instruction.Chapter 3. 4 0 . o Cycles: States: Flags: 4 none NOTE The 8085 TRAP interrupt cannot be disabled. However. include an EI instruction Opcode EI at the end of the code sequence. no interrupt including TRAP can interrupt the execution of the 01 or EI instruction. at the beginning of the code sequence. However. the processor to 3-23 at some indeterminate of a RESET signal forces the program counter . a 01 instruction that use interrupts. Application When power is first applied. the interrupt subroutines ENABLE INTERRUPTS Enabling of the next program instruction.

m for the TR/. for the HL T instruction However. access request.P The processor Interrupt. except even when the interrupt can temporarily leave the halt state to service a direct has been serviced. NOTE fhis description Input/output IS restricted to the exact function of the IN instruction. However. This forces which recognized the program to zero. is EI.truction instruction. the processor is of a RESET signal. A common (RESET instruction sequence start-up at this point address. IN The IN inst uction reads eight bits of data from the specified INPUT FROM PORT port and loads it into the accumulator. counter the only way to restart system memory is disabled. structures are described in the 8080 or 8085 Microcomputer Systems User's Manual. typically IS an interrupt. 3-24 . the pro- cessor reent er s the halt state once the request A basic purpose peripheral processing device. Opcode IN The operand expression may be a number Operand exp or any expression that yields a value in the range OOH through OFFH. you should oe certain the EI (Enaile Interrupt) If an 8080 I-lLT instruction by applicati. The same is true of the 8085. See the description executed IS while interrupts are disabled. of before the HL T instruction executed. the processor that interrupts instruction. IS can be restarted are enabled only by an external event. Otherwise. HL T. Instruction 5 et zero. Therefore. contains the address of the next sequential HALT the flags and registers 0 1 0 1 01 7 (5 on 8085) none Cycles: States: Flags: Once in the halt state. halts the processor. The program remain counter unchanged. These instructions A subsequent enable manual the interrupt or automatic system interrupt also disables the interrupt system) and halt the processor. is to allow the processor resources to pause while waiting for an interrupt from a a halt wastes processor and should be used only when there is no useful t isk available.Chapter 3. then determ mes the effective HLT The HL T in .

P.AC 3-25 . Instruction Set o exp Cycles: States: Addressing: Flags: o 3 10 direct none INR INR adds one to the contents character Increment of the specified byte. INR affects all of the condition arithmetic flags except INCREMENT the carry flag.AC Addressing: Flags: Increment Memory Opcode INR This instruction increments by one the contents L registers. The Instruction adds one to the contents of 10 0 Cycles: States: D D D 1 o 0 I 5 (4 on 8085) register Z.P. Register Opcode INR Operand reg routines for incrementing The operand must specify one of the registers A through the specified register. E.S.Chapter 3. it can be used within multi-byte counts and similar purposes. Operand M of the memory location addressed by the Hand L registers. M is a symbolic reference to the Hand 10 0 Cycles: States: Addressing: Flags: o 3 10 o 0 I register indirect Z.S. Because INR preserves the carry flag. H or L.

e been pushed stack entry ti A subsequent POP instruction and the low-order but overlays 10 byte of the next older entry. tha . flag. tests the setting in the JC instruction. or the SP (Stack the Hand L register pair. program If the flag is reset to zero. byte of the most recent 0 11 Cycles: States: Addressmg: Flags: Example: Assume 0200H. "he INX instruction sets no flags to indicate JC The JC instruction address specified instruction.) INX SP increments the contents of SP INX D increments the value to a result of 5 (6 on 8085) register none the INR E Instruction can be detected the carry out of the low-order byte and produces If the stack pointer register contains the value OFFFFH. it can be used for address modification multi-byte INX INX may m zrement only the B&C. D&E. for example. that INX SP IS executed accesses entry the high-order a PUSH Instruction after a number byte of the most adds the two of Items ha. Opcode Operand all the condition of the specified register pair. the low-order olR PO Similarly. The instruction ignores by testing the Zero condition the instruction this condition. H& L. Instruction 5 et Example: If register C contains 99H. new bytes the stack. the instruction INR C increments the contents of the register to 9AH. 0100H. the D and E registers By contrast. Pointer) register pairs. INX affects INCREMENT none of the condition within REGISTER PAIR flags. Assume. to OOOOH. INX INX adds one to the contents INX preserves routines. If the flag is set to one. Notice that the letter H must be used to specify Exercise recent car e when incrementing onto the stack pointer. execution continues JUMP IF CARRY execution resumes at the with the next sequential 3-26 . the stack. Because arithmetic flags.Chapter 3. of the carry flag. (Tills condition contain the value 01 FFH.

1 1 0 1 1 0 1 0 lowaddr high addr Cycles: States: Addressing: Flags: Example: Examples of the variations of the jump instruction appear in the description of the J PO instruction. If the contents of the accumulator If the contents instruction. 1 1 1 1 1 0 1 0 The assembler inverts the high and low lowaddr high addr Cycles: States: Addressing: Flags: Example: Examples of the variations of the lump instruction appear in the description of the J PO instruction.Chapter 3. Instruction Set Opcode Operand address The assembler inverts the high and low JC The address may be specified as a number. are negative (sign flag = 1). 3-27 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) immediate none . of the accumulator are program execution positive (sign flag = resumes at the address specified In the J rv1 instruction. a label. 0). or an expression. or an expression. 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) immediate none JM The JUMP IF MINUS JM Instruction tests the setting of the sign flag. address bytes when it assembles the instruction. a label. address bytes when it assembles the instructions. execution Opcode continues with the next sequential Operand address JM The address may be specified as a number.

Chapter 3. 3 10 immediate none JNC The INC insruction tests the setting of the carry flag. If there is no carry (carry flag If there is a carry (carry flag Instruction. execution INC address The assembler inverts the high and low The address nay be specified as a number. address byte. program = 1). Oocode Operand JUMP IF NO CARRY execution continues resumes at the address specified in the I NC instruction. or an expression. Opeode Operand JUMP alters the execution sequence by loading the address in its second and third bytes into the IMP address The assembler inverts the high and low The address riav be specified as a number.uction program courter. with the nex t sequential = 0). 1 1 0 0 0 0 1 1 lowaddr high addr Cycles: States: Addressing: Flags: Example: Examples of the variations of the Jump instruction appear in the description of the I PO instruction. when it assembles the instruction. a label. Instruction Set JMP The IMP inst. 1 1 0 1 0 0 1 0 lowaddr high addr Cycles: States: Addressing: Flags: 3-28 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) immediate none . address bytes when it assembles the address. a label. or an expression.

= resumes at the address specified in the J P Instruction. address bytes when it assembles the instruction. The address may be specified as a number. a label. 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) immediate none JP The JP instruction program execution minus (sign flag tests the setting of the sign flag. If the contents 1).Chapter 3. address bytes when it assembles the instruction. program execution resumes at the address specified In the )NZ instruction. execution Opcode )NZ continues Operand address The assembler inverts the high and low with the next sequential instruction. The assembler inverts the high and low order 3-29 . 1 1 0 0 0 0 1 0 lowaddr high addr Cycles: States: Addressing: Flags: Example: Examples of the variations of the lump instruction appear In the description of the J PO instruction. If the contents of the accumulator are not zero (zero flag = 0). or an expression. Instruction Set Example: Examples of the variations of the jump instruction appear in the description of the J PO Instruction. a label. JUMP IF POSITIVE are positive (sign flag of the accumulator = 0). or an expression. JNZ JUMP IF NOT ZERO The J NZ Instruction tests the setting of the zero flag. execution continues with the next sequential Operand address of the accumulator If the contents instruction. are Opcode JP The address may be specified as a number. If the contents of the accumulator are zero (zero flag = 1).

The parity flag IS set to one to The J PE Instruction flag is set to one. program continues execution resumes at the addre: s specified sequential in .Chapter 3. in the J PE instruction. 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) immediate none IPE Parity indicate IS even if the byte In the accumulator this condition. may be specified when it assembles if parity as a number.truction. . Operand address a label. If the parity has an even number JUMP IF PARITY EVEN of one bits. execution with the next Opcode JPE The address address byte. IN instruction of . or an expression. The assembler inverts the high and low the instruction. The flags can be set by adding OOH to the 1 1 1 0 1 0 1 0 lowaddr high addr Cycles: States: Addressing: Flags: Example: Examples 3-30 01 the variations 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) Immediate none of the iurnp instruction appear In the description of the J PO instruction. odd) instructions are especially useful for testing the parity of input data. If the flag IS reset to zero. contents th.he accumulator. Instruction $1 t 1 1 1 1 0 0 1 0 lowaddr high addr Cycles: States: Address: ng: Flags: Example: Examples of the variations of the lump instruction appear in the description of the J PO instruction. The J PE anc J PO (jump However. tests the setting of the parity flag. does not set any of the condition flags.

program continues execution with the in the J PO instruction.C PLUS MINUS A.Chapter 3. If the flag is set to one. tests the setting specified of the parity flag. Instruction Set JPO Parity is odd if the byte in the accumulator indicate this condition. or an expression. The flags can be set by adding OOH to the 1 1 0 0 0 1 0 low addr high addr Cycles: States: Addressing: Flags: Example: This example upon whether shows three different but equivalent methods for lumping to one of two points IS 3 (2 or 3 on 8085) 10 (7 or 10 on 8085) immediate none in a program based or not the Sign bit of a number Label ONE: Code MOV ANI JZ JNZ MOV RLC JNC THREE: JMP MOV ADI JM PLUS: MINUS: is set. The J PO and J PE (jump if panty However. a label. execution instruction. TWO: MINUS . The assembler Inverts the high and low The address address may be specified bytes when it assembles the instruction.C 0 that the byte to be tested the C register. If the parity has an odd number JUMP of one bits. Opcode JPO Operand address as a number. contents the IN instruction of the accumulator.C 80H PLUS MINUS A. The parity IF PARITY ODD flag is set to zero to The J PO Instruction resumes at the address next sequential flag is reset to zero. 1 does not set any of the condition flags.SIGN BIT RESET .SIGN BIT SET 3-31 . even) instructions are especially useful for testing the parity of Input data. Assume Operand A.

If the flag is set to one. Otherwise. the Zero condition cortrol to be transferred by three. stituted for the unconditional jump with identical results. Instruction Set The AND immediate program instruction in block ONE zeroes all bits of the data byte except to the Instruction and the JNZ instruction at PLUS. could be subin this instance. may be specified address bY1es when it assembles as a number.) bit to be set equal to the Sign bit of the data byte. or an expression. will be executed. 1 1 0 0 1 0 1 0 low addr high addr Cycles: States: Addressing: Flags: Example: Examples if the variations of the jump instruction appear In the description of the J PO instruction. the JMP instruction a JC Instruction is executed.] The add irrmediate J M instruction matically instruction In block THREE control causes the condition to MINUS. If the sign bit was set. program control flows auto- causes program to be transferred irto the PLUS routine. of the zero flag. Operand address a label. execution continues execution JUMP IF ZERO resumes at the with the next sequential the high and low the instruction. If the causes a lump to PLUS. If the Sign bit was zero. bits to be set. which will merely to be transferred reupdate to mains unch inged. (The Zero bit IS unaffected The RLC instruction in block TWO causes Sign bit wa s reset. the program counter bit will be set.Chapter 3. and the JZ instruction the JZ instruction causing control will cause the instruct ion at M INUS. the JNC instruction the Carry by all jump instrucuons. the Sign bit. Otherwise unconditionallv transferring control to MINUS. the Otherwise. (Note that. 3 (2 or 3 on 8085) 10 (7 or lOon Immediate none 8085) LOA LDA load! the accumulator LDA instr iction. program If the flag is reset to zero. with a copy of the byte at the location LOAD ACCUMULATOR specified In bytes DIRECT two and three of the 3-32 . JZ The J Z instruction address specified Instruction Opcode JZ The addres . The assembler inverts tests the setting in the J Z instruction.

location 300H. high and low address bytes when it builds the instruction. LOAD: LDA LDA LDA 300H 3*(16*16) 200H+256 When executed. or an expression. a previously defined label. Instruction Set Opcode LDA Operand address The assembler inverts the The address may be stated as a number. This instruction specify only the B or D register pair. each replaces the accumulator contents with the byte 4 13 direct none LDAX L DAX loads the accumulator B or register pair D. Opcode Operand LOAD ACCUMULATOR with a copy of the byte stored at the memory location addressed INDIRECT by register pair LDAX The operand B specifies the Band C register pair. D specifies the D and E register pair. may o L- 01 fo '" register l1 '" register pair B pair D Cycles: States: Addressing: Flags: 2 7 register indirect none 3-33 . 0 0 1 1 1 0 1 0 lowaddr high addr Cycles: States: Addressing: Flags: Examples: The following instructions of data stored at memory are equivalent.Chapter 3.

SHLD stores Hand 0 1 0 1 0 L in memory. The Both LHLD and provided for loading new addresses into the Hand top of the stack into the Hand POP replace the contents of the Hand L registers. Instruction !·et Example: Assume that register D contains with the contents 93H and register E contains 8BH. The following instruction ioads the accumulator of memory location 938BH: LDAX D LHLD LOAD HAND L DIRECT LHLD loads the L register with a copy of the byte stored itt the memory location specified in bytes two and three of the LHLD instruction. or an expression. tile MOY instruction moves a copy of the byte stored at address 064E into the accumulator: LHLD MOY 3000H A. Certain instr uctions use the symbolic reference L registers.o load the current M to access the memory location currently L registers (POP instruction). specified by the Hand L registers. higher rnernorv location. Opcode LHLD Operand address LHLD then loads the H register with a copy of the byte stored at the next The address may be stated as a number. a label. In the following sequence.SET UP ADDRESS . 1 0 lowaddr high addr Cycles: States: Addressing: Flags: Example: Assume that locations 3000 and 3001 H contain the address 064EH stored in the format 4E06. You can also exchange the contents of Hand L with the D and E registers (XCHG instruction) or the top of the stack (XTHL instruction) if you need to save the current Hand L registers for subsequent 0 use.LOAD ACCUM FROM ADDRESS 5 16 direct none 3·34 . _HLD is one of the instructions user may al.Chapter 3.M .

STACK 3-35 .Chapter 3. Instruction Set LXI LXI is a three-byte instruction. LXI can load the Band E register pair. or an expression. its second and third bytes contain LOAD REGISTER PAIR IMMEDIATE the source data to be loaded into a register register pair. or the Stack Pointer.M . LXI loads a register pair by copying its second and third bytes into the specified destination Opcode Operand LXI The first operand must specify the register pair to be loaded. an ASCII constant. use for LXI is to establish a memory address for use in subsequent the LXI instruction loads the address of STRNG into the Hand instructions. two bytes. All other immediate instructions require 8-bit the label of some previously defined value. Notice that the assembler inverts the two bytes of data to create the format of an address stored in memory. loads A Into register Band 0 Z into register C. LXI MOV The following LXI instruction H. 0 0 1 that accepts a 16-bit value. pair.SET ADDRESS .STRNG A. Thus. The data must not exceed o I R P I 0 low-order data high-order data Cycles: States: Addressing: Flags: Examples: A common sequence. C register pair. LXI is the only immediate instruction values. the D and The second operand specifies the two bytes of data to be loaded. In the following then 3 10 immediate none L registers.'AZ' the data into the format required for an address stored in registers. The MOV instruction loads the data stored at that address into the accumulator. The LOCATE pro- is used to initialize the stack pointer gram provides an address for the special reserved label STACK. LXI SP. This data may be coded in the form of a number. the Hand L register pair. This has the effect of reinverting the instruction LXI B.LOAD STRNG INTO ACCUMULATOR in a relocatable module. LXI loads its third byte into the first register of the pair and its second byte into the second register of the pair.

The second operand must address one of the L 5 (4 on 8085) register none 1 0 Cycles: States: Addressing: Flags: o I 2 S 5 51 7 register Indirect none Move from vlernory Opcode MOV Operand r. and time than NOP.M is not allowed.Chapter 3. or L.reg2 MOVE field. The instruction's register to mirnorv. MOV H. as a NOP (no opera- effect.M 3-36 .A). ha: a slightly longer execution (as in MOV A. Source data operands specify whether the move is from register to register. Move Reqister to Register Opcode MOV The instruction E. Since M addresses a register pair rather than a byte of Cycles: States: Addressing: Flags: Move to Memory Opcode MOV This instruct ion copies the contents registers. the MOV functions copies the contents Operand regl. Operand M. Instruction Set MOV The MOV in: trucuon moves one byte of data by copying the source field into the destination remains unchanged. D. M s a symbolic reference registers. or from memory to a register. C. B. When the same register is specified for both operands tion) since II has no other noticeable therefore data. from a of reg2 into regl. Each operand must specify one of the registers A. H. This form of MOV requires one more machine state than NOP.r of the specified register Into the memory location addressed by the Hand to the Hand L register pair.

Move Immediate to Register Opcode MVI Operand reg.M E. or an expression. the labei of some previously defined value. Instruction Set This instruction reference copies the contents L registers. This data may be in the form of a number. MVI moves one byte of field. these symbols appears in the operand expression HIGH or LOW operator When neither operator to specify which byte of the address is to be used in the evaluation is present. the assembler assumes the LOW operator 0 and issues an error message. MOVE IMMEDIATE its second byte contains the source data to be moved. The first operand must name one of the registers A through The second operand specifies the actual data to be moved.LOAD ACCUM FROM MEMORY . an ASCII constant. When one of instruction. of the memory location addressed by the Hand L registers into the specified register.COPY ACCUM INTO E REG .data E. it must be preceded by either the of the expression. H or L as a destination for the move. M is a symbolic 10 0 0 Cycles: States: Addressing: Flags: Examples: Label LDACC: NULOP: Opcode MOV MOV MOV Operands A. o 10 0 data o 11 0 Cycles: States: Addressing: Flags: 2 7 immediate none 3-37 .NULL OPERATION 2 7 register indirect none MVI MVI is a two-byte instruction. The assembler's symbols as 16-bit addresses.A C. The second operand must be M. The first operand to the Hand must name the destination register.Chapter 3.C Comment . relocation feature treats all external and relocatable of an immediate The data must not exceed one byte. The instruction's operands specify whether the move data by copying its second byte into the destination is to a register or to memory.

ORA ORA perf result 01 INCLUSIVE OR WITH ACCUMULATOR ms an inclusive OR logical operation usmg the contents of the specified byte and the accumulator. The is placed in the accumulator. Instruction iet Move Immediate to Memory Opcode MVI This instruc:ion a symbolic copies the data stored to the Hand Operand M. immediate data In the MVI instruction.01000001B M:A' MA1H M.Chapter 3. none of the condition Operand NO OPERATION flags. 3-38 . All of the example s generate for the ASCII character M.data in its second pair.lOlQ M. M is eference L register o 0 data o o Cycles: States: Addressing: Flags: Examples: The followi.65 M.5+30*2 NOP NOP perfor ns no operation and affects Opcode NOP Operands ar e not permitted with the NOP instruction. NOP IS useful as filler in a timing loop.ig examples show a number the bit pattern MVI MVI MVI MVI MVI MVI of methods 3 10 Immediate/register none indirect for defining A. byte into the memory location addressed by Hand L.

e. This instruction ORs the contents of the must specify one of the registers A through specified register and the accumulator flags are reset to zero. The carry and auxiliary carry flags are reset to zero. result.CY. OR produces a one bit in the result when the corresponding ones.CY.P. Instruction Set Summary of Logical Operations AND produces a one bit in the result only when the corresponding one. the accumulator.produces AND OR EXCLUSIVE OR 1010 1010 0000 1111 00001010 OR Register with Accumulator Opcode ORA The operand 1010 1010 00001111 1010 1111 1010 1010 0000 1111 1010 0101 Operand reg E. bits in the test data and the mask data are a one bit in the bits in either the test data or the mask data are bits in the test data and the mask data are i. Exclusive OR produces a one bit only when the corresponding different.but not both .S. o Cycles: States: Addressing: Flags: o 2 7 register indirect Z. and stores the result in the accumulator.AC 3·39 .P. H or L.Chapter 3..AC OR Memory with Accumulator Opcode ORA The contents Operand M L registers are inclusive-Oked with the contents of of the memory location specified by the Hand The result is stored in the accumulator. a one bit in either the test data or the mask data . The carry and auxiliary carry o Cycles: States: Addressing: Flags: o S S S I 4 register Z.S.

Oocode ORI The operar d must specify the data to be used number. these symbols appears in the operand expression HIGH or LOW operator When neitler operator is present.P. OR produr es a one bit in the result when the corresponding bits in both the test data and the mask data bits in either the test data or the mask data are ones. a one bit in either the test data or the mask data .S. i. o o 000 00 000 0 ORI ORI performs an inclusive OR logical operation contents 01 the accumulator. The following example ensures that bit 3 of the done when individual bits Assume that register D contains the value OSH: 01000011 is set ON. The assembler's relocation feature treats all external and relocatable of an immediate Operand data In INCLUSIVE using the contents OR IMMEDIATE and the of the second byte of the instruction The result is placed in the accumulator. 3-40 . ORI also resets the carry and auxiliary the inclusive OR operation. Instruction Set Example: Since any tit inciusive-ORed accumulator with a one produces a one and any bit ORed with a zero remains unchanged. symbols as 16·bit addresses.e. When one of instruction. This data may be in the form of a The data may not the label of some previously defined value. carry flags to zero. This is frequently ORA is frequentl y used to set ON particular are used as status flags in a program. to specify which byte of the address is to be used in the evaluation the assembler assume the LOW operator and issues an error message. but the remaining bits are not disturbed.Chapter 3..AC AND prod ices a one bit in the result only when the corresponding are ones. exceed one byte.but not both produces a one bit in the result. ar ASCII constant. o data Cycles: States: Addressing: Flags: Summary of Logical Operations o 2 7 immediate Z. Accumulator Register D bits or groups of bits.SY. Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are different. it must be preceded by either the of the expression. or an expression.

01000001B 'A' 41H 101Q 65 5+30*2 examples show a number of methods for defining immediate the bit pattern for the ASCII character ORI ORI ORI ORI ORI ORI OUT The OUT instruction places the contents of the accumulator OUTPUT TO PORT on the eight-bit data bus and the number of the 255.Chapter 3. NOTE Because a discussion of input/output this manual. o 0 exp 0 Cycles: States: Addressing: Flags: 3 10 direct none 3·41 . Operand exp port. this description OUT instruction. Input/output Systems 8085 Microcomputer Opcode OUT The operand expression structures is beyond the scope of of the in the 8080 or is restricted structures to the exact function are described User's Manual. Instruction Set AND 1010 1010 00001111 00001010 Example: See the description generate of the ORA instruction OR 1010 1010 00001111 1010 1111 EXCLUSIVE OR 1010 1010 0000 1111 1010 0101 for an example of the use of the inclusive OR. It is the responsibility of external logic to decode the port number and to accept the output data. Since the number of ports ranges from 0 through number is duplicated on the address bus. the port selected port on the sixteen-bit address bus. All of the examples A. The following data in the ORI instruction. This may be in the form of a number or an must specify the number of the desired output in the range OOH through OFFH.

Instruction Se: PCHL PCHL loads t. For this example. assume that two bytes of data follow the subroutine following coding sequence performs a return to the next Instruction GO BACK: POP INR INR PCHL H L L .RETURN ADDRESS POP The POP insruction Program POP removes two bytes of data from the stack and copies them to a register pair or copies the and the condition flags. PCHL has the effect of a jump instruc- of the H register to the high-order eight bits of the program counter and the contents of the L reg Her to the low-order eight bits of the program counter. The call. Because the processor fetches the next instruction from the updated address.GET DATA ADDRESS . Operand of the Hand MOVE H&L TO PROGRAM COUNTER L registers Into the program counter program counter register. The return addre s pushed onto the stack by the CALL Instruction actually addresses the data rather than the next after the call: the CALL. The user pro-tram must ensure that the Hand the PCHL In: truction L registers contain the address of an executable instruction when is executed.itus Word into the accumulator POP Reqiste. o Cycles: States: Addressing: Flags: Example: One technique instruction ater for passing data to a subroutine o 0 5 (6 on 8085) register none IS to place the data Immediately after the subroutine call. Opcode PCHL Operands are not permitted PCHL moves the contents with the PCHL instruction.Chapter 3. St. Pair POP copies: he contents of the memory location addressed by the stack pointer Into the low-order register of the the stack pointer by one and copies the contents of the resulting address into register pair POP then increments 3-42 .ie contents tion.ADD 2 TO FORM .RETURN .

Chapter 3.AC Example: Assume that a subroutine is called because of an external interrupt.CY. POP then increments older Item on the stack. such subroutines should save and The following restore any registers it uses so that main program can continue sequence of PUSH and POP instructions normally when it regains control. 000 Cycles: States: Addressing: Flags: 3 10 register Indirect Z.P. POP PSW is explained separately. the stack pointer by one and restores the contents the stack pointer again so that it addresses the next older item on the stack. the registers: 343 . Instruction Set the high-order register of the pair. or the H&L register pairs. Cycles: States: Addressing: Flags: POP PSW POP PSW uses the contents POP PSW increments POP then increments of the memory 3 10 register indirect none location specified by the stack pointer to restore the condition of that address to the accumulator. Opcode Operand the stack pointer again so that it addresses the next POP The operand may specify the B&C. D&E.S. In general. save and restore the Program Status Word and all. flags.

PUSH The PUSH instruction the Progran copies two bytes of data to the stack. This data may be the contents below: Status Word. and the stack pornter is set at 9AAF.Chapter 3. PUSH then decrements the pointer again and copies the low-order register to the resul: ing address. D&E. the C register contains 4CH. The operand may specify the B&C. PUSH PSW is explained 11 1 1R P a 3 Cycles: States: Addressi ng: Flags: Example: Assume tha: register B contains 11 (13 on 8085) register indirect none 2AH. The instruction'USH B stores the B register at memory address 9AAEH and the C register at 9AADH. The source registers remain unchanged. Opcode Operand PUSH {U separately.et PUSH PUSH PUSH PUSH PSW B D H subroutine coding POP POP POP POP RET H D B PSW Notice that the sequence of the POP instructions is the opposite of the PUSH instruction sequence. as explained PUSH of a register pair or PUSH Reqis'er Pair PUSH decrements the stack pointer register by one and copies the contents of the high-order register of the register pair to the resulting address. The stack pointer is st:t to 9AADH: 344 . Instruction :. or H&L register pairs.

Sign up to vote on this title
UsefulNot useful