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A New Current Sensor Based on MagFET Highly

Immune to EMI
O. Aiello1 F. Fiori2

Abstract − This paper deals with the susceptibility to


electromagnetic interference of CMOS integrated current ISENSE IX
sensors for power transistor current monitoring. Conventional VDD
integrated solution are first considered, hence a new OV_PROT
integrated current sensor based on the Hall effect in MOS +
EMI_FILTER
transistors (MagFET) is proposed. The susceptibility to radio
frequency interference of a conventional (wired) current -
sensor and that of the MagFET-based solution is discussed.
POWER MOS
VSS
1 INTRODUCTION

Common electronic systems are usually made of


several modules that include printed circuit boards SENSE MOS
FET DRIVER
(PCBs), discrete components and integrated circuits
(ICs). Power and data interconnects in such systems
are usually routed through cables, which in turn Figure 1: Integrated current sensor based on the
behave like unintentional antennas collecting mirroring principle
electromagnetic interference (EMI) from the
surrounding environment. For this reason additional passive filters at printed
Although several studies have dealt with the circuit board (PCB) or at IC level are usually needed.
susceptibility of integrated circuits to EMI [1], such a Based on that and aiming at the design of integrated
topic is far from being completely addressed and current sensors intrinsically immune to EMI, this paper
deserves further insights. To this purpose, this paper describes a new current sensor based on the Hall effect
introduces the susceptibility to radio frequency which takes place in a split-drain nMOS transistor,
interference (RFI) of common analog, digital and (namely the MagFET) surrounded by the magnetic
power front-end circuits like those used in field of the current to be monitored [3].
Application-Specific-Integrated-Circuits (ASICs), then The paper is organized as follows: Section 2 describes
it focuses on Smart-Power System-on-Chip [2] and in a circuit implementing the current mirroring principle
particular on the susceptibility to RFI of conventional (the SenseFET circuit). Section 3 recalls how magnetic
integrated current sensors needed for power transistor field unbalances the drain current of a splitted drain
current monitoring. MOS transistor (MagFET) and shows the operation of
To this purpose, common circuits for current sensing the current sensor, which has been developed in this
use a small resistor in series with the power transistor work. Then, Section 4 shows the results of computer
which translates the transistor current into a voltage to simulations carried out to evaluate the susceptibility of
be further amplified and elaborated. Other current the MagFET-based current sensor. These results are
sensing circuits base their operation on the current compared with those of the SensenFET operating in
mirroring principle: a small transistor (the SenseFET) the same condition. Finally, in Section 5 some
is driven by the same gate source voltage of the power concluding remarks are drawn.
transistor so that its drain current is proportional to the
power transistor current. Such integrated current 2 A CONVENTIONAL CURRENT SENSOR:
sensors show low power dissipation, need reduced THE SENSEFET CIRCUIT
silicon area and provide reasonable accuracy.
However, any current sensor electrically connected to A common way of sensing the current flowing through
power transistor terminals like those mentioned above, a power transistor consists in mirroring it using a
is exposed to interference collected by cables. circuit like that shown in Fig. 1, where an elementary

1
EMC Competence Center, Istituto Superiore Mario Boella, via P.C. Boggio 61, 10129 Turin, Italy,
e-mail: aiello@ismb.it, tel.: +39 011 2276705, fax: +39 011 2276299.
2
Microelectronics EMC Group, Eln. Dpt., Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Turin, Italy,
e-mail: franco.fiori@polito.it.
let’s consider a splitted-drain MOS transistor
I D1 I D2 metal strip (MagFET) placed very close to a metal strip which
PAD carries the current to be monitored, and let’s further
assume such a sensing transistor biased in saturation.
MAGFET In this condition, the power transistor current induces
the Hall effect into the channel of the sensing
D
D1

D2
D transistor that unbalances the MagFET drain currents.
In particular, previous works have shown that
the current unbalance (ΔI) can be expressed as
2D Power
MAGFET Mos ΔI = S I I B B⊥ = S I I B Fc I x (1)
Figure 2: MagFET symbol and layout view. where IB is the MOS split-drain bias current with zero
magnetic field; Fc is a conversion factor defined as the
2400 ratio of the magnetic flux lines density is the split-
2200 drain transistor to the metal strip flowing current (Ix).
2000
Furthermore, SI is the MAGFET sensitivity that
depends on the geometry of the device (length L and
1800
B [μT]

1600

1400
width W), which can be written as
1 L
S I = μ Hch GH . (2)
1200

1000

800
2 W
0 20 40 60
Distance [μm]
80 100 120 In this expression, GH is a geometrical correction
Figure 3: Vertical Magnetic Field evaluated at the factor (GH=0.676 for square transistor) and µHch is the
plane of MagFET for Ix=1A. Hall carrier mobility given by the product of the
effective carrier mobility µn (process-based) and the
transistor (the SenseFET) of the same type of those Hall factor rH. This last factor is almost independent of
used to build up the power transistor is driven by the temperature (rH = 1.05 for current sensor operating
same gate-source voltage of the power transistor itself temperature dropping in the range 20°C < T < 120°C
while the drain-source voltage is kept equal to that of [4]), so that current sensing circuits based on MagFET
the switched-on power transistor by means of a voltage are suitable to be embedded in power transistors and
follower. Such a biasing circuit makes the SenseFET smart-power system-on-chips that usually experience
drain current (Isense) proportional to that of the power large temperature variations.
transistor (Ix) through a constant mirroring factor, In this work, the conversion factor Fc that relates the
which is given by the ratio of the two transistors areas normal magnetic field strength with the current Ix has
(the same channel length is considered). To this been evaluated performing electromagnetic
purpose, it is worth mentioning that the accuracy of simulations for a metal strip of thickness t=4µm and
such a circuit is surely limited by the transistors width w=10µm [5]. Computer simulations have been
mismatch, which occurs whenever a current mirror repeated for several metal-strip to MagFET distances
with high mirroring factor is fabricated. in the range 0 - 130µm and the results are shown in
However, the accuracy of such a current sensor can be Fig. 3. On the basis of these considerations and
significantly reduced by disturbances affecting the referring to a square MagFET (W=L=10µm) and metal
power transistor nominal signals and for this reason strip to MagFET distance Δ = 10µm, the conversion
the possibility of building up a current sensor with no factor is equal to Fc=1.845mT/A and the overall
electrical connection with the power transistor conversion factor is about ΔI/Ix = 2.5.10-9.
terminals and limited bandwidth has been investigated. On the basis of the above mentioned parameters and
To this purpose, the idea of monitoring the power assuming the current to be monitored ranging from 0A
transistor current by sensing the magnitude of the to 10A, the dynamic range of the MagFET differential
related magnetic field has been considered. output current takes values in the range 0-50nA.
Furthermore, a sensing resolution of at least 100mA is
required [6]. As a consequence, a differential trans-
3 A NEW CURRENT SENSOR BASED ON
resistance amplifier with gain greater than 100dBΩ,
THE MAGFET TRANSISTOR low-noise and minimum input offset voltage is needed.
An alternative way of monitoring the power transistor Based on that a telescopic cascade amplifier driven by
current is that of sensing the magnetic field, which is the MagFET output currents has been considered (see
related to such a current, through the Hall effect that Fig. 4) because it keeps the MagFET drain terminal at
takes place in the channel of a MOS transistor equal constant voltage while providing a very high
surrounded by the magnetic field. To this purpose, gain and low noise.
VDD VCM
f3
M5 S S
M6 f3 fR1-fR2
VBIAS3 f1 f1-f2
C4
I f1
M5I S S
M6 f3 C3 fR2
VBIAS2 fR2
VCM
f2
fR1-fR2 C1 f3 f2
VOUT2 VOUT1 C2 f3 f3
S1 VOUT1 f3 fR1 - +
VCM VO-DIFF
VBIAS1 M3 f1 M4 f3 fR1
+ -

VOUT2 C6 f3
S2 f3
f2 f2 f3
C5
VCM
fR2 C7
f3 f1 fR2
MAGFET
f1 C8 f1-f2
VBIAS-MAG
f3 fR1-fR2
f3
VCM
VSS
Figure 4: MagFET’s output current trans-resistance Figure 5: Switched capacitor amplifier for offset and
amplifier flicker noise cancellation

Aiming at the cancelation of offset and flicker noise VDD


the output voltages of the cascode gain stage is then VSS Cbp
provided to a switched capacitor amplifier (the
schematic view is shown in Fig. 5). The first stage Ccore
(cascade amplifier) and the second stage (SC

package model
substrate model
amplifier) are controlled by the same timing unit CURRENT
which works on three successive phases. During Φ1, SENSOR
bias T
C4 and C8 are charged up to the sum of offset voltage
of the 1st stage and that of the opamp of the 2nd stage
(VOFF). During Φ2, C1 and C5 are charged up to the
50W
sum of the input voltages including both wanted
information and upsets. A reset phase ΦR1 (ΦR2) ASIC
+
-
precedes the above mentioned acquisition phases Φ2 power MOS VRF VPS
(Φ1). Finally, in the phase Φ3 the switches in the
circuit are driven to perform the difference between Figure 6: Schematic view of the circuit including
the voltages acquired in Φ1 and Φ2, that results in the the current sensor, which has been considered for
amplified output VoDIFF (see Fig. 5). Thus, the 2nd stage computer simulations. RFI is superimposed to the
performs offset and noise cancellation. drain voltage using the DPI method.

4 SUSCEPTIBILITY TO RFI OF In this framework, time domain simulations were


INTEGRATED CURRENT SENSORS performed using ELDO (a SPICE-like simulator) and
the RFI-induced upset of the current sensor output
In this section the susceptibility of the above described signal (Isense in the SenseFET circuit and the output
current sensors to RFI added to the nominal signals of voltage VoDIFF of the MagFET SC amplifier) has been
a power transistor is investigated. In particular, the recorded. These simulation results are shown in Figs.
case of a power transistor integrated in the same die 7, 8, 9 where the minimum, maximum and average
with a bunch of analog and digital blocks including a value of the output signal RFI-induced upset versus
current sensor is considered, and it is assumed that all RFI amplitude is reported. In particular, Figs. 7, 8, 9
signal circuits share the same power supply rails. have been obtained considering CW interference at
Analyses have been carried out referring to the 20MHz, 100MHz, 200MHz respectively. With
schematic view of Fig. 6 which includes a 2 mm2 reference to these results it comes out that the
power transistor, the substrate parasitic model, the immunity of the MagFET-based current sensor
package parasitic model and the schematic view of the (wireless sensor) is greater than that of the SenseFET
current sensor to be analyzed. Furthermore, all circuits (wired sensor). However, it should be noticed that both
of the SoC except the power transistor and the current current sensors are more susceptibility to RFI in the
sensor have been roughly modeled by an on-chip frequency range around 100MHz. To this purpose,
capacitance connected to the power supply and ground further analyses based on small signal simulations
rails. Simulations have been carried out with the power have shown that RFI added to the power transistor
transistor switched-on and the RFI added to the drain drives the parallel resonance of the power supply
terminal using the direct power injection method [7]. package parasitic inductances (VDD-VSS) and the on-
chip parasitic capacitance Ccore (see Fig. 6).
80 100

60
50
40
Current sensed error (%)

Current sensed error (%)


20
0

−50
−20 max MagFET max MagFET
min MagFET min MagFET
−40 avg MagFET avg MagFET
−100
max SenseFET max SenseFET
−60 min SenseFET min SenseFET
avg SenseFET avg SenseFET
−80 −150
0 5 10 15 20 0 2 4 6 8 10
Disturbance amplitude [V] Disturbance amplitude [V]

Figure 7: Maximum, minimum and average value of Figure 9: Maximum, minimum and average value of
the current-sensed error by MagFET and SenseFET the current-sensed error by MagFET and SenseFET
versus RFI amplitude. CW interference at 20MHz. versus RFI amplitude. CW interference at 200MHz.

40 0

−20
20
Current sensed error (%)

−40
0

−60
[dB ]

VDD
V

−20
Drain
−80
max MagFET
−40 min MagFET
−100
avg MagFET
max SenseFET
−60
min SenseFET −120
avg SenseFET
−80 −140 6 7 8 9
0 0.5 1 1.5 2 2.5 3 10 10 10 10
Disturbance amplitude [V] Frequency [Hz]
Figure 8: Maximum, minimum and average value of Figure 10: AC analysis: RFI magnitude resulting at the
the current-sensed error by MagFET and SenseFET switched-on power MOS drain terminal and at the
versus RFI amplitude. CW interference at 100MHz. current sensor power supply (VDD) referred to VSS

Around this resonance (about 100MHz in the circuit


under analysis) the amplitude of RFI that results added References
to the current sensor power supply voltage takes
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drain terminal, as it is shown in Fig. 10. Electromagnetic Compatibility of Integrated
Circuits – Past, Present and Future”, IEEE Trans.
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[3] R. S. Popovic, Hall Effect Devices - Second
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sensors for power transistor current monitoring has and Philadelphia, 2004.
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current sensor which is electrically connected by metal IEEE Trans. on Eln. Dev., Vol.46, n.8, Aug.
strips to the power transistor terminals has been 1999.
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counterpart. of Electromagnetic Immunity – Part 4: Direct RF
Power Injection Method.