Revised April 2004

NREL/SR-520-35885

PV Inverter Products Manufacturing and Design Improvements for Cost Reduction and Performance Enhancements
Final Subcontract Report November 2003

R. West
Xantrex Technology Inc. San Luis Obispo, California

National Renewable Energy Laboratory
1617 Cole Boulevard Golden, Colorado 80401-3393
NREL is a U.S. Department of Energy Laboratory Operated by Midwest Research Institute • Battelle Contract No. DE-AC36-99-GO10337

Revised April 2004

NREL/SR-520-35885

PV Inverter Products Manufacturing and Design Improvements for Cost Reduction and Performance Enhancements
Final Subcontract Report November 2003

R. West
Xantrex Technology Inc. San Luis Obispo, California

NREL Technical Monitor: D. Mooney
Prepared under Subcontract No. NDO-1-30628-02

National Renewable Energy Laboratory
1617 Cole Boulevard Golden, Colorado 80401-3393
NREL is a U.S. Department of Energy Laboratory Operated by Midwest Research Institute • Battelle Contract No. DE-AC36-99-GO10337

This publication was reproduced from the best available copy Submitted by the subcontractor and received no editorial review at NREL

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...........................1................ 9 3..... Schematic and Bill of Materials............................. 19 TASK 3................................................2 DSP2 Circuit Design....................................... 7 TASK 3.......1 Single-phase Magnetics Design....................................................3 Single-phase Heat Removal System Design..................................3 Three-Phase Simulator Board .......................2 Single-phase Simulator Board Layout and Fabrication ...............2 Three-phase Simulator Board Fabrication .................................2.........................................2 DSP1 Circuit Design...6.................................. 18 3................ 12 TASK 3..........3 Three-Phase Heat Removal System Design ........................2 DSP3 Circuit Design........................................ 23 i .... 9 TASK 3.. 1 2...........................TABLE OF CONTENTS FIGURES............................... 20 3..................................................................................9.......................6.............. 17 TASK 3......................................................... 14 3..................................................... 9 3................................................. 8 3................1 Three-Phase Simulator Board Circuit Design ..............................1 FIRST YEAR OVERVIEW ........................ 4 3 PROJECT PERFORMANCE ...................................................................................1 BACKGROUND ................10 Three Phase Inverters and DSP3 Software Integration.......................................................... 21 TASK 3.4 Single-phase Enclosure Design ........... 20 3...2.............................2 DSP3 Control Board Design and Prototype ................................................................. 21 TASK 3...........5 Single-phase Inverter Manufacturability Modifications ............6.2.............................................................. 15 3...............1......................2 Three-Phase Power Bridge Design ................................................ 22 3................ 10 TASK 3...................................9.......................4 DSP3 Control Board Firmware Shell Design ....................3..................... 14 3...... 7 3.................................5.. 7 3.....9 DSP2 Control Board Design and Prototype ............... 18 3........ Schematic and Bill of Materials..............................................................................................................................3 DSP1 Circuit Board Assembly Fabrication ................ 13 TASK 3..............................................1 Three-Phase Magnetics Design . 8 3............................................................................ 1 1................................... 3 2.......... 22 TASK 3................5........................................................11 3............................................................................. 1 2 OVERVIEW...5.............................2 Single-phase Power Bridge Design ........................................1.............................3 DSP3 Control Board Assembly Fabrication ............................................................................................................................................ 22 3..........................................................................................1.............................................1 Three-Phase Inverter Manufacturability Modifications ....................................................................3......................................3 INVERTER PHOTOGRAPHS ............................. iv 1 INTRODUCTION .............2 OBJECTIVES ....1 DSP1 Embedded Controller Specification ....................................................................................7.......................................................................................... 1 2.......................7 Single-Phase Simulator board..................................1 Single-phase Simulator Board Circuit Design...................................................4 Three-Phase Enclosure Design ..............5....... 18 3............................................6 DSP1 Control Board Design and Prototype ........... 14 3..................................... 9 3.............. 1 1.........................................................1 DSP2 Embedded Controller Specification ........... Schematic and Bill of Materials.............11 3....7...........................................................................................................................................................................................................................................8 DSP1 Control Board Software Shell Design .....2 SECOND YEAR OVERVIEW ........................1 DSP3 Embedded Controller Specification .......................

.......10...................................................................11..........................................................10........................................11.......11..10.............................................................. 27 DC Bus Minimum Voltage Limit ............................................. 28 Voltage and Frequency Limits for Utility Interaction ................................12 3........................................................................... 45 ii .................. 42 PV2..10.... 43 PV2.... 29 Current Imbalance.........................17 3..................................4 3.....................11.........................................................................5A Test Results....5A Inverter Operational Modes .............5A Test Setup ...........................5A Hardware Updates .......................................24 3.................................11......................5 3...............................10....................................11 Grid-Tied Inverter Operation .........................................................................................................................5A................................................................ 30 Operating States ...................... 45 PV2..................................................... 42 DSP1 Firmware Updates.........................................5A Third Party Certification ................................................................... 30 Operator Interface LCD ........................................... 25 Test Results ....................23 3.....11...................................................................................................................................................................................6 3............................11...........15 3............. 28 Device Over-Temperature .............18 3.............. 31 Fault Detection andAnnunciation ................. 23 Hardware Updates.....................................27 3...........................................25 3........................................................................................................1 3...................... 27 Line Voltage / Frequency Detection........ 43 PV2...........................................11 3...............................22 3................................................................................ 27 Third Party Certification ....16 3.......11......... 29 DC Bus Over-Voltage Detection .........................................................................11............10.... 39 PV25A Power Data ............................ 26 Auto-Phase Sequence Detection ............................10...28 TASK 3...2 3.... 27 Power Quality ...........10.................. 38 PV10A Power Data ....................5A Inverter Software Protection .........................................3 3...............................................................................................................................................10.............4 3..3 3...............................................10...............................3........................... 41 PV2..................10..................8 3...........21 3................................. 45 PV2.....................9 3....... Single-phase Inverter and DSP1 Software Integration .....9 3.................... 23 DSP3 Firmware Updates..........................................10...............10............10...............................................2 3.......1 3.........10...............................7 3................ 24 Test Setup....................10................ 41 PV2. 34 Notes to the Data Sheets ...... 40 Proposed Changes...........................................................................10.........................................................11.........26 3....................................5A Grid-Tied Inverter Operation ........................................................................5 3...5A DC Bus Minimum Voltage Limit . 25 Inverter Operational Modes ............................................................10 3..........10.6 3....................................5A Power Quality... 43 PV2...............10....................................................... 23 Test Methods ......10..................20 3...... 27 Inverter Software Protection ..........................................10.......14 3............................................. 43 PV2...............8 3.................................................. 28 Island Detection ......................5A Test Methods ...........10 3......................13 3............... 25 Auto-Frequency Detection...................................... 33 TEST DATA.......................10....................10...7 3....... 41 PV2......................................10.............................................. 30 Over Current ....... 45 PV2...10.................................10..........................................10........10..............11....................................................................................................................................................................11 3..............19 3....................

..............20 PV2............11........................11...........16 PV2............... 54 3...........................11...............4 Software Module Listing ...15 PV2.................16 SNL Testing.....23 PV2..13.................13 PV2......... 66 TASK 3..22 PV2........11.....11............. 47 3.....3 Change Management...................................................................5A Island Detection.............5A Operator Interface LCD ...........................11..............................................................14 Create Standard Serial Communications Description Document... 48 3.13..........................5A Performance Test Data Sheets ................3....................................................................12 UL Listing Submittal ..........................24 PV2.......... 46 3...........25 PV2..... 56 3.........12 PV2....................................................................... 77 TASK 3.............................................................5A Line Voltage / Frequency Detection ................ 59 3... Single-Phase Inverter Prototype....11..............................................5A Power Factor and THD Test Data............................. 77 iii .............................................13..............................13.................................................................................... 77 4 SUMMARY .5A Conversion Efficiency Data ........................ Three-Phase Inverter Prototype ........................................5A Notes to the Data Sheets..............................13 Create Standard Software Module Catalog ..........................................................................18 PV2..................... 57 3..........................5A Proposed Changes ..................................... 50 3............5A Over Current............11..........11.............................................................................5A Operating States ...5A DC Bus Over-Voltage Detection ...........15 SNL Testing................................................................1 Coding Standards ........21 PV 2..14 PV2.............................. 58 3.... 47 3.......11............5A Voltage and Frequency Limits for Utility Interaction .................... 55 3.................................................................................11......... 47 3.......................................11...................................................... 47 3.............................17 PV2........................................................................................11.. 56 TASK 3...............................................................11..............5A Fault Detection and Annunciation................ 61 TASK 3..........2 Coding Reviews ................ 46 3..........................5A Device Over-Temperature ...................... 54 3. 52 3........................................... 56 TASK 3..................19 PV2..... 45 3..................

...................................................................................................................................................................................................................................................................................................... DSP1 Control Board Analog Function Check List............................. Low Priority Node Claims First ............................... DSP3 Control Board Analog Function Check List.....................................................................21 Figure 10: ISO OSI Model ................ DSP3 Control Board..................6 Figure 4..................................... Enclosure Cost Reduction............................. SIM3 Start-Up and Function Check List .................................................18 Table 13.............. Summary PV2...............................................................................................72 Figure 14: Multi-Packet Transfer.................5A Cost Savings .......................................5A Power Bridge Assembly.... Magnetic Component Cost Reduction...... 10kW Inverter Comparison Photograph...... PV2.....................................14 Table 11..................66 Figure 11: Address Claiming—Different Addresses ............................4 Figure 2..........................68 Table 15.............................................................................................13 Table 9......... High Priority Node Claims First .................................FIGURES Figure 1.....................................................81 iv ........................................................9 Table 6.............5A Inverter Showing Heatsink .....14 Table 10..................................8 Table 4.5 Figure 3................................................... Photograph of PV2.............. Power Bridge Parts Normalized Cost Reductions ......................................................................................... DSP1 Control Board............................................................70 Figure 12: Address Claiming—Same Addresses.18 Table 12....................................................10 Table 8...................................................... Magnetic Component Cost Reductions ..................................................................................................... DSP1 Cost Reduction ........................................19 Table 14: NAME Fields ............................17 Figure 8................................................. 20kW/25kW Inverter Comparison Photograph .. SIM1 . Back of PV2....................................................................................................................... SIM3 ................................................................ Summary Comparison PV20208 and PV25A ............81 Table 17...........................................15 Figure 7...............................................................................................................................80 Table 16.......................................................................................10 Table 7..............................11 Figure 5........................... 2500W Inverter .................................74 TABLES Table 1............................................71 Figure 13: Address Claiming—Same Addresses........................................................ Heat Removal Parts Normalized Cost Reductions ................................. Magnetic Components Normalized Costs ........... DSP3 Control Board Normalized Cost Reduction ............................................. Photograph of Three-Phase Simulator Board...............................5A....... Single-Phase Simulator Board........................................................... Enclosure Normalized Cost Reduction ..... Magnetic Components Normalized Cost Reductions......7 Table 2.7 Table 3..........................................8 Table 5......................................................................................................................................................................................20 Figure 9......12 Figure 6................................................................................................... Summary Comparison PV10208 and PV10A .......

Achieve cost reductions through increased volume of common components. To accomplish these goals.1 FIRST YEAR OVERVIEW In the first year of this subcontract.1 INTRODUCTION 1. Decrease manufacturing and component parts costs. Xantrex has addressed the PV manufacturing goals of improving PV manufacturing processes and products while reducing costs and providing a technology that supports significant manufacturing scale-up. (Xantrex) is a leading manufacturer of power conversion equipment for the renewable energy industry. Increase PV inverter product reliability. Xantrex has developed both hardware and software functional blocks that can be applied across a number of different product lines.1 BACKGROUND Xantrex Technology Inc. weight and conversion losses. The weight. “next generation” power conversion equipment for the PV industry. Reduce the time to market for new products 1. Improve reliability through design standardization. and production test variations. Three different DSP based control boards. for three 1 . low cost Digital Signal Processing (DSP) embedded controller.2 • • OBJECTIVES Capture the newest Digital Signal Processor (DSP) technology to create high impact. Two of the three inverters were designed as direct replacements for existing inverters. Xantrex has been able to: • • • • • Reduce Non-Recurring Engineering (NRE) costs for new development. size. This standardized approach to both hardware and software control platforms will provide significant market advantage over foreign competition. and the higher efficiency of producing more products with fewer design. manufacturing. Throughout this subcontract work. highimpact PV inverter products for grid-tied applications. Xantrex developed the hardware for three advanced. The control for all of the inverters is based on a high performance. The specific objectives of this development work were to: • • • 2 OVERVIEW 2. Decrease testing costs through standardization of subassemblies. Using this approach. Create a common resource base for three PV product lines. reduced assembly labor. cost and conversion losses of these new inverters were reduced by nearly 50% compared to the current technology. Reduce inverter size.

Xantrex has designed and fabricated the following complete prototype hardware. In the first subcontract year. improve performance. 2 . Final NREL deliverables will still be based on the 20kW minimum power requirement but the nominal power for this product will be specified at 25kW. Borrowing from existing technology and manufacturing experience. grid-interactive inverter DSP 1 – DSP based control board for single-phase inverters using an H-bridge topology DSP 2 – DSP based control board for 1-phase hybrid systems using an H-bridge topology DSP 3 – DSP based control board for 3-phase inverters using a 6-switch bridge topology SIM 1 – Test system for simulating single-phase inverter hardware at the control interface SIM 3 – Test system for simulating three-phase inverter hardware at the control interface The original minimum targeted power rating for the larger three-phase inverter was 20kW.5A – 2500W single-phase. The reference designator names given below will be used throughout this report: PV10A – 10kW three-phase. These control boards were designed for universal application at virtually any power level for any inverter with the same electrical topology. The designs are targeted for larger production volumes and increases in manufacturing efficiencies in order to reduce manufacturing and component part costs. Thermal tests results indicate a nominal power capability of 2. grid-interactive inverter PV2. grid-interactive inverter PV25A – 25kW three-phase. Thermal tests results indicate a nominal power capability of 25kW. Final NREL deliverables will still be based on the 2000W minimum power requirement but the nominal power for this product will be specified at 2500W.5A reference designator is more appropriate.5kW. grid-tied inverter hardware platforms and one cost reduced single-phase grid-tied inverter hardware platform were developed. and increase reliability. therefore the PV2. therefore the PV25A reference designator is more appropriate. two cost reduced threephase. The original minimum targeted power rating for the single-phase inverter was 2kW.different types of PV inverter topologies were developed to support a number of current and future inverter products.

The overall purpose of the second year work was to bring improved.2. a Serial CAN (controller area network) Bus Communications Standard was drafted for the same effect. The control firmware code was completed and debugged for the PV10A and PV25A three-phase inverter prototypes and PV2. procurement and manufacturing efficiencies. 3 . cost reduced PV inverter products to pre-production status. This is an iterative design process where the DSP controller code is written. The second year was primarily dedicated to the development of the DSP firmware code and more importantly the integration of this control firmware and the target hardware. The same prototypes were evaluated for UL listing. A significant part of the hardware/firmware integration work involved “debugging” parts of the program code where the program locks up or does not perform the desired functions. The PV25A and the PV2. or program code. cost reduced.5A single-phase inverter prototype. Also.2 SECOND YEAR OVERVIEW The first year of this subcontract was primarily dedicated to hardware development. PV products to market by improving development. A number of diverse tasks were performed to bring three new. high impact. was produced in the second year. This was the area of greatest technical risk.5A were successfully tested at Sandia National Labs. higher reliability. This was accomplished by incrementally adding control functions to the software shells developed in the previous year. This effort culminated in the testing of each of the three inverters for full specification compliance. tested for the expected response in the target hardware and then modified again until the desired results are obtained. In a loosely related task Xantrex created a Standard Software Module Catalogue to improve the time to market for the PV inverter products addressed in this contract and for any future inverter development. The bulk of the DSP firmware.

2.3 INVERTER PHOTOGRAPHS Figure 1. 10kW Inverter Comparison Photograph Left .The PV10A developed under this contract Size Reduction 58% Weight Reduction 47% Conversion Loss Reduction 49% Cost Reduction 56% 4 .The existing Xantrex PV10208 Right .

5 .The PV25A (25kW) developed under this contract Photographs are to scale Size Reduction 70% Weight Reduction 54% Conversion Loss Reduction 49% Cost Reduction 53% Comparisons have been normalized per kilowatt for these two machines. 20kW/25kW Inverter Comparison Photograph Left .Figure 2.The existing Xantrex PV20208 (20kW) Right .

Photograph of PV2. 2500W Inverter 6 .Figure 3.5A.

in the two 3phase inverters. to 29 lbs. The cost goals were exceeded. For reference we will refer to the new.88 PV20208 .03 . Magnetic Component Cost Reductions Significant reductions were also made in weight.57 . PV25A Percentage Cost Reduction 12% 22% Table 2. 3-phase inverters. secondary line filter chokes and power supply transformers. TASK 3.62 . including primary line filter chokes. 7 . the Models PV5208 (5kW).3 PROJECT PERFORMANCE This project was organized into sixteen tasks. All costs are based on 100 piece purchase quantities. substantial weight reductions were had and the power conversion efficiency of both has been enhanced.17 .00 PV25A .14 . Component \ Model Primary Line Filter Choke Primary Line Filter Choke Power Supply Transformers Total Magnetics Costs PV10208 .00 PV10A .78 Table 1. Magnetic Components Normalized Costs Models PV10208 vs. reduced cost versions of the existing PV10208 and PV20208 as the PV10A and PV25A respectively. For example. PV10A PV20208 vs.33 . The comparison is made between the current Xantrex product offering and the two new products being developed under this contract.58 .09 1. Two new models rated at 10kW and 25kW were developed to replace these four models. PV15208 (15 kW) and the PV20208 (20 kW) currently offered by Xantrex Technology Inc.06 1. the PV10208 primary line filter choke weight was reduced from 72 lbs.67 . PV10208 (10 kW).1 Three-Phase Inverter Manufacturability Modifications The purpose of this task was to reduce the manufacturing costs of four. Table 2 illustrates the percentage cost savings had with the magnetic components designed for the new inverters.37 .1 Three-Phase Magnetics Design The goal of this subtask was to reduce the cost of magnetic components.1. by 10%. Table 1 compares the normalized costs of the associated magnetics components. This has been accomplished by using “Super-HF” core materials.04 . Goals and objectives were laid out in order to monitor and evaluate the results of this development work. 3.

00 .1.47 1. This has been accomplished by using simplified.2 Three-Phase Power Bridge Design The purpose of this subtask was to reduce the cost of the inverter power bridges for the 10kW and 20kW hardware platforms. This goal was exceeded. lower cost IGBT drive circuits. This was accomplished by using higher efficiency IGBT modules that generate less heat and by using a more efficient.1. Power Bridge design.46 Parts % Reduction 59% 53% Table 4. Heat Removal Parts Normalized Cost Reductions 8 . Table 4 summarizes the cost savings had with the new heat removal system designs. “dumb” IGBT modules and a highly integrated. Power Bridge Parts Normalized Cost Reductions 3. more bus capacitance and the requirement for a larger heatsink. This goal was exceeded. The 20kW Bridge is approximately twice the size of the 10kW bridge because of larger power modules.00 .79 % Reduction 53% 21% Table 3. Unit PV10208 PV10A PV20208 PV25A Heat Cost Removal 1.3. The goal of this Subtask was to reduce the cost of the 10kW and 20kW power bridge designs by 10%.41 1. PCB based. high-turbulence forced convection system.00 . Table 3 summarizes the cost savings had with the new integrated power bridge designs. Unit PV10208 PV10A PV20208 PV25A Power Bridge Parts Cost 1.3 Three-Phase Heat Removal System Design The goal of this Subtask was to reduce the cost of the 10kW and 20kW heatsink and associated heat removal system components by 20%.00 . laminated bus.

2. performance and UL 1741 targets. Unit PV10208 PV10A PV20208 PV25A % Cost Reduction 30% 31% Table 5.3. All input and output signals were defined.1. 3. Schematic and Bill of Materials The purpose of this subtask was to translate the controller specification into a hardware design. 3. 3-phase. and will also perform those functions more commonly performed by a microprocessor. This controller card will be used for both the 10kW and 20kW inverters. This goal was exceeded. The goal of this Subtask was to reduce the cost of the control board used on the existing Xantrex PV10208 and PV20208 three-phase inverters by 20%.2. Task 3.2. as well as the controller requirements to meet power. This was accomplished by traditional analog and digital electronic design techniques creating the most cost-effective configuration of the circuit components peripheral to the DSP controller. This was accomplished using an embedded DSP controller and a minimum number of peripheral components.2 DSP3 Control Board Design and Prototype The purpose of this task was to design and fabricate a low cost. Table 6 summarizes the parts cost savings had with the new control board design. This was accomplished by incorporating integral weather shields and insect baffles. 9 . Enclosure Cost Reduction TASK 3. The enhanced DSP performs all of the real time pulse-widthmodulation (PWM) functions of the inverter.2 DSP3 Circuit Design. The goal of this Subtask was to reduce the cost of the 10kW and 20kW enclosure designs by 20%. This specification is applicable for both the 10kW and 20kW inverters. This goal was exceeded. PV grid tie control board that can be applied at virtually any power level. eliminating enclosure door flanges and by using continuous door hinges for both the 10kW and the 20kW designs.1 DSP3 Embedded Controller Specification The purpose of this subtask was to precisely define the functional performance parameters of the DSP3 card. This specification was utilized in the development of the DSP3 circuit design. and the DSP3 control board firmware shell design. universal application. subtask 3.4 Three-Phase Enclosure Design The purpose of this subtask was to lower the total cost of all sheet metal components. high performance.4.2. Table 5 summarizes the cost savings had with the new enclosure designs.

digital: +5 volts Verify Supply Voltage. The goal was to fabricate the DSP3 control board hardware according to the design and specification developed in that subtask.2.3 volts Verify Supply Voltage.38 Table 6. analog: +5 volts Verify Supply Voltage. analog: +3. isolated: +5 volts Verify Reference Voltage: +1.2.00 Cost Reduction 62% . Adjust the AC Voltage Adjust trimpot on the DSP3SIM board fully CW Verify that there are 3 Vpp sine waves on test points 0. verify LED lights Install jumper select for IOPB5.Control Board PV258 series control board and LCD module DSP3 control board. 1.3 volts Verify Supply Voltage.2.2. 1.3 DSP3 Control Board Assembly Fabrication This subtask was a follow on to Subtask 3. including LCD display Total Parts Cost 1. 2 on B09010 Complete √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Table 7. Verify all three sine waves smoothly adjust to 0 volts Change all jumper selects for 25 kW test.2. 2 on B09010 Adjust VR1 CCW. digital: +3. This control board design achieves a cost savings of over 60% compared to the control board components currently used in the PV10208 and PV20208 inverters as shown under the heading of Subtask 3. verify LED lights Install all jumper selects for 10 kW test Adjust the AC Voltage Adjust trimpot on the DSP3SIM board fully CW Verify that there are 3 Vpp sine waves on test points 0. DSP3 Control Board Analog Function Check List 10 .3 volts Install jumper select for IOPB4. The Xantrex DSP3 control board p/n B09010A is a fully functional single board unit used to control all functions. It has a Liquid Crystal Display on board eliminating the need for extra cabling and hardware.65 volts Verify 40.mHz square wave on X1 pin 3 Verify Manual Adjust (MAN): 0 to 3. Table 7 is a check list of the analog functions on the board that were tested in order to ready the board for use in software development: Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description Supply Voltage IN: +/-12 volts Verify Supply Voltage. including the switching of the Power Bridge Assembly and the PWM loop regulation for the PV10A and PV25A inverters. The task resulted in the fabrication of four DSP3 printed circuit board assemblies part number (p/n) B09010A as shown in Figure 4. DSP3 Control Board Normalized Cost Reduction 3.

modeling for the control board input and output signals. The task was accomplished through a twostep design. for the DSP3 control board to facilitate firmware development in a low power environment.Figure 4.2. 3. development and fabrication process resulting in the design. DSP3 Control Board TASK 3.1 Three-Phase Simulator Board Circuit Design The purpose of this subtask was to translate the controller I/O specifications into a hardware design for the SIM3 simulator board.3. This was accomplished by using adjustable amplitude sinewave generators and DC sources to simulate scaled analog DSP input signals. This circuit design was used to fabricate the simulator as shown in Subtask 3.3. 11 . Controller outputs were terminated into characteristic load impedances and test points were made available.3 Three-Phase Simulator Board The purpose of this task was to develop a simulator board. This was accomplished by traditional analog and digital electronic design techniques. fabrication and assembly of one SIM3 simulator PCB assembly. the SIM3.

3. Photograph of Three-Phase Simulator Board.3. Digital: +12 volts Voltage Reference: +2. SIM3 Item 1 2 3 4 5 6 7 8 Description Supply Voltage: +12 volts Supply Voltage: -12 volts Supply Voltage: +5 volts Supply Voltage. Figure 5 shows a photograph of the completed three-phase simulator board assembly.76kHz square wave on U4 pin 10 Verify AC Voltage Adjust (VR1): 0 to 2.5 volts With VR1 fully clockwise check: Complete √ √ √ √ √ √ √ √ 12 .5 volts Verify 245.2 Three-phase Simulator Board Fabrication The goal of this Subtask was to fabricate a three-phase simulator board based upon the designs developed in Subtask 3. The result of this subtask has been the fabrication of a completed simulator board assembly.1. Figure 5. This goal has been met.3. Table 8 verifies the performance and function of the three-phase simulator board.

data direction.9 10 11 12 13 14 15 16 24 volt sine wave @VA 24 volt sine wave @VB 24 volt sine wave @VC 120° phase shift between each sine wave Adjust VR1 CCW. U24. serial communications interface. fifteen C language source files.4 DSP3 Control Board Firmware Shell Design The goal of this subtask was to create the pre-integration firmware code. √ √ √ √ √ √ √ √ Table 8. This code initializes all of the microprocessor’s internal registers (system and core. Verify output of sensor U23 is accurate with the ambient temperature. and the external hardware. watchdog. SIM3 Start-Up and Function Check List TASK 3. pulse-width modulation. analog-to-digital. The code has functions to perform 50 versus 60 Hertz detection. With unit in run mode. U24. 13 . a state-machine-based limits checking and shutdown. verify 0 volts on the output of U21. This task brought the firmware to a point where the hardware/firmware integration phase could proceed with the greatest efficiency. reference sine wave generation. and event manager registers). This shall be supported using the simulator board from Task 3. Verify all three sine waves adjust to 0 volts With unit in standby. The purpose of this task was to design the internal configuration and basic function of the embedded controller. and some LCD display functions. RAM (Random Access Memory). The pre-integration code consists of two assembly language source files. verify sine wave on the output of U21. U22. U22. photovoltaic power tracking. This has been accomplished and we are ready to begin the hardware/firmware integration phase of the project. and thirty-four ‘include’ files. various RMS and other power calculations and data logging functions.

5A.94 . the new single-phase 2500W unit will be designated as the PV2. This cost goal was exceeded.2 Single-phase Power Bridge Design The goal of this Subtask was to reduce the cost of the existing power bridge board used in the ST2500XR inverter by 10%. DC to high frequency AC and rectification of the high frequency AC to DC.1 Single-phase Magnetics Design The goal of this subtask was to reduce the cost of all magnetic components in the single-phase inverter by 10%. Magnetic Component Cost Reduction 3.82 Table 9. bus capacitors and power modules are components and circuits where commonality and cost reductions are expected. grid-tied inverter hardware platforms. 3. This goal was exceeded.5A . Component \ Model Output Transformer(s) Output Choke Power Supply Transformer Total Magnetics Costs SW2512 . are in a full bridge boost 14 . The ST2500XR bridge is effectively a three conversion design. control power supplies.5. Table 9 compares the normalized costs of the associated magnetics components.5 Single-phase Inverter Manufacturability Modifications The purpose of this task was to reduce the costs of manufacturing the Xantrex single-phase. The comparison is made between the current Xantrex SW Series product offering and the new product being developed under this contract.11 . PV2. Magnetic Components Normalized Costs Models SW2512 vs. Table 10 illustrates the percentage cost savings had with the magnetic components designed for the new inverter. Two conversions. All costs are based on 100 piece purchase quantities.5.03 . The new design offers a cost reduction of 31%.5A Percentage Cost Reduction 18% Table 10. The reduction is attributed to the differences in the topologies used for each design.TASK 3. For future reference. Specifically.03 1.67 . IGBT (Insulated Gate Bipolar Transistor) drive circuits. The current SW product most closely represents the topology of the new single-phase inverter. One new platform is intended as a next generation replacement for both the Xantrex ST and 4000 series of grid tie inverters.04 .00 PV2. The new platform will be designed to maximize manufacturing efficiency by utilizing common cost reduced components and common manufacturing techniques wherever possible.

this goal was not attained. This design not only reduces cost. the jump from forced convection to natural convection is much more costly than demonstrated here. The power that can be dissipated in each device can be stated as: Pd=∆T/ΣRφ 15 . This can be done because multiple power switching devices are paralleled to achieve low conduction losses and the spread the losses over a large area. The new design uses a single stage to convert DC voltage to AC current employing a 60Hz transformer driven by a full bridge. Back of PV2.5A Inverter Showing Heatsink The specific purpose of the cooling system is to remove the heat from switching devices. separate power supplies and drive circuits are needed for each. Typically. Figure 6. The intent of this development task is satisfied because the value of the product is enhanced through higher reliability and silent operation. 3. In the strictest sense. There is a maximum junction temperature that must not be exceeded or the device will fail. The reduction in parts and lower operating temperatures further enhances product reliability. so cost is reduced. The heat removal system cost was increased by 32% but the performance was greatly improved. The new design uses a heat sink cooled by “fanless” natural convection. This greatly adds to the parts cost of the inverter. This DC voltage is then converted to the 120VAC output voltage. but provides more efficient power conversion. This topology does not require the large number of isolated power supplies and drive circuits required with the ST2500XR topology. All of the heat in the switching device is efficiently transferred to the heat sink.3 Single-phase Heat Removal System Design The goals of this Subtask were to redesign the heat removal system with no increase in current costs and no reduction in performance for the single-phase inverter.5. Since the DC to DC converter is isolated from the DC to AC converter.circuit used on the front end of the inverter to boost the input DC voltage up to a high DC bus voltage.

The assembly for the power bridge board is also simplified by using surface mount power components. inverter reliability is increased. a likely component to fail. and an inverter that operates silently. without a fan.3 (. the switching devices in this design. The above calculations show that the selected heat sink material will be more than adequate to cool. This also means reduced parts cost.80 +. ΣRφ = sum of the thermal resistances between the devices and the heat sink 16 . This conservative thermal design will result in lower switch temperatures.75 + .3°C This is well below the 175°C max temperature of the devices being used. This will increase the life expectancy of all of the internal components like capacitors and the switches themselves. Because the cooling system doesn’t need a fan.74)] +30 + 45 = 80. which means lower enclosure temperatures.Where: Pd = power dissipated ∆T = difference between the junction temperature and the ambient temperature = Tj -Ta = φjc + φthermal clad pcb + φsil-pad Calculating for junction temperature: Tj = Pd(φjc + φthermal clad pcb + φsil-pad) + Ths + Ta = [2.

For an equitable cost comparison. This was accomplished using an enclosure with two compartments. the PV2. 17 . is much improved. including the cost of the weather shield. This goal was exceeded. where the forced convection airflow deposits dust on sensitive components.5. The actual reduction.Figure 7. Table 11 shows the normalized costs and percentage cost savings had with the new single-phase inverter enclosure design. Also. The performance over the Xantrex ST Series. one vented with louvers containing environmentally robust magnetics components and one sealed containing environmentally sensitive electronic devices. PV2. the ST outdoor weather shield is added to the ST sheet metal component costs.5A Power Bridge Assembly 3.4 Single-phase Enclosure Design The purpose of this subtask was to lower total cost of all sheet metal components for the single-phase inverter.5A enclosure is weatherproof by design and does not require an optional plastic weather shield. was 25%. The result of this subtask was expected to be a 20% reduction in sheet metal costs for the single-phase inverter when compared to the Xantrex ST series.

6 DSP1 Control Board Design and Prototype The purpose of this task was to design and fabricate a low cost. In the following table. 1-phase. Task 3.40 Cost Reduction 60% Table 12. Table 12 illustrates the summary cost reduction for the single-phase inverter control board. and the DSP3 control board firmware shell design. This was accomplished using an embedded DSP controller and a minimum number of peripheral components. The enhanced DSP performs all of the real time pulse-width-modulation (PWM) functions of the inverter as well as those functions more commonly performed by a microprocessor. subtask 3. Enclosure Normalized Cost Reduction 25% TASK 3. universal application. high performance.8. 3. The comparative parts cost reduction was greater than 60%. These goals were exceeded.1 DSP1 Embedded Controller Specification The purpose of this subtask was to precisely define the functional performance parameters of the DSP1 card. the parts costs for the two control boards have been normalized for the purpose of analysis. DSP1 Cost Reduction 18 . These costs used were based on 100 piece pricing for both units. Schematic and Bill of Materials The goal of this subtask was to design a DSP1 control board according to the functional specification and to show a parts cost reduction of least 20% for the DSP1 control board over that of the control hardware for the UPG Model 4000 inverter. Unit 4000 control board DSP1 Control Board Cost 1.Unit ST2500XR *With weather shield PV2.00 .75 Table 11.6. 3. This specification was utilized in the development of the DSP1 circuit design. performance and UL 1741 targets.2. as well as the controller requirements to meet power. All input and output signals were defined.6.00 .2 DSP1 Circuit Design. PV grid tie control board that can be applied at any power level with any inverter using the same electrical topology.5A Enclosure Sheet Metal Cost Cost Reduction 1.6.

3 3.305 48 VDC Simulated Rises when heated 11.3 0.113 3.4 3.7 Amps simulated Has some bounce Noisy w/switch open 240 VAC Simulated Comments Table 13. and the PWM loop regulation for the single-phase inverter.3 3.305 Measured Level 4.1 -15.95 15. The goal was to fabricate the DSP1 control board hardware according to the design and specification developed in that subtask.4 3.6.65 60 Hz SW 0 0 0 0.4 24 0 Push Push Push 0.01 0.3 DSP1 Circuit Board Assembly Fabrication This subtask is a follow on to Subtask 3. The task resulted in the fabrication of the DSP1 printed circuit board assemblies. DSP1 Control Board Analog Function Check List 19 . including the switching of the Power Bridge Assembly.3.6.28 1.2.1 -15.964 0.62 60 Hz SW 0 0 0 0.95 15.117 48 0.3 3. This control board has a cost savings of over 60% compared to the control board components currently used in the model 4000 inverters.1 -15.02 1 1 1 1 0.3 0.117 3.3 3.3 3.3D +3.3 0.96 1.04 1. It has a Liquid Crystal Display on board eliminating the need for extra cabling and hardware.2.3 3.95 15.004 1.65 Expected Level 4.6. as shown under the heading of Subtask 3.96 0.3A Line Voltage Sense Line Voltage Offset Sync Signal UP Switch Down Switch Select Switch LEM Output Overcurrent Signal Overvoltage Signal PDPINT Signal DC Voltage Sense Temperature Sensor Simulator Ratio Scale Signal 4. Table 14 shows a check list of the analog functions on the board that were tested in order to ready the board for use in software development: Parameter Input Voltage (+5) Input Voltage (+15) Input Voltage (-15) +3. The Xantrex DSP1 control board is a fully functional single board unit used to control all functions.305 1 1 1 10 0 100 1 1 0.

2.Figure 8. modeling for the control board input and output signals. This circuit design was used to fabricate the simulator as shown in Subtask 3. fabrication and assembly of one SIM1 simulator PCB assembly. This was accomplished by traditional analog and digital electronic design techniques. DSP1 Control Board TASK 3. for the DSP1 control board to facilitate firmware development in a low power environment. SIM1. 3. 20 . The task resulted in the design.7 Single-Phase Simulator board The purpose of this task was to develop a simulator board. Controller outputs are terminated into characteristic load impedances and test points are made available. The result is a simulator board built to test the DSP1 control board and is intended to shorten the firmware development time by more than 20%. This was accomplished by using adjustable amplitude sinewave generators and DC sources to simulate scaled analog DSP input signals.7.7.1 Single-phase Simulator Board Circuit Design The purpose of this subtask was to translate the controller I/O specifications into a hardware design for the SIM1 simulator board.

3. the DSP reset vector points to the C run-time library. The result of this subtask has been the fabrication of a completed simulator board assembly.1. This task brings the firmware to a point where the hardware/firmware integration phase can proceed with the greatest efficiency.2 Single-phase Simulator Board Layout and Fabrication The goal of this Subtask was to fabricate a single-phase simulator board based upon the designs developed in Subtask 3.8 DSP1 Control Board Software Shell Design The purpose of this task was to setup the internal configuration and basic function of the embedded controller. performs all of the actions necessary in order for the C environment to function. Upon startup.7. There exists one assembly language module (interrupt vectors only). Figure 9. This was accomplished using the simulator board from Task 5. Once that is 21 . SIM1 TASK 3. and six C language modules. This code. The DSP1 hardware platform provides the support for the necessary software modules. This task has resulted in the completion of the preintegration firmware code. This goal has been met.7. Single-Phase Simulator Board. supplied by TI.

This specification was utilized in the development of the DSP2 circuit design. This specification is applicable for residential PV power systems with low voltage battery storage of up to 10kW based on the same electrical topology. This has been accomplished using an embedded DSP controller and a minimum number of peripheral components.9. This was accomplished by traditional analog and digital electronic design techniques creating the most cost-effective configuration of the circuit components peripheral to the DSP controller. The goal of this subtask was to create the pre-integration firmware code. and control does not leave this loop until the unit is reset. This meets the contract goals since performance. Schematic and Bill of Materials The purpose of this subtask was to translate the DSP2 controller specification into a hardware design. This has been accomplished and we are ready to begin the hardware/firmware integration phase of the project. by like end user application. control is then passed to the function called “MAIN”.1 DSP2 Embedded Controller Specification The purpose of this subtask was to precisely define the functional performance parameters of the DSP2 card. high performance. performance and UL 1741 targets. This function performs the hardware initialization as well as the remainder of the software initialization (including the enabling of interrupts).2 3. All input and output signals were defined. subtask 3. various RMS and other power calculations and data logging functions. and some LCD display functions.9. The results of this task shall be the design of the DSP2 controller.9 DSP2 Control Board Design and Prototype The purpose of this task was to design and fabricate a low cost. TASK 3. This is because there is no existing equipment with the extended performance capabilities of this new board. universal application control board for residential PV power systems with low voltage battery storage of up to 10kW based on the same electrical topology. would be the Xantrex SW Series. the DSP2 control board costs were reduced by 14%. The code has functions to perform 50 versus 60 Hertz detection. photovoltaic power tracking. reference sine wave generation. 3. as well as the controller requirements to meet power.9. The costs used were based on 3000 piece pricing for both units. a state-machine-based limits checking and shutdown. This loop provides the inverter’s functionality.done. 22 . This controller card will be used for residential PV power systems with low voltage battery storage of up to 10kW based on the same electrical topology There were no specific contract cost reduction goals for the DSP2 board.2 DSP2 Circuit Design. and then control is passed to the main loop. When compared to the Xantrex SW Series control board. features and flexibility were all enhanced with the new design and a cost reduction was achieved. The closest comparison.

independent of weather conditions. Rather.1 Grid-Tied Inverter Operation A PV10A and a PV25A inverter have been operated through a series of tests devised to compare operation of each unit to the corresponding performance specifications as defined in document DSP3 FS 102502. This allows for the complete control of the input parameters. the over temperature fault limit. In these cases. and has met or exceeded that performance criterion.10. which is necessary to demonstrate the inverter performance over a wide range of normal and fault conditions. The expected result of this task was to test the 10kW and 20kW inverters per the corresponding performance specifications and meet or exceed the specified performance criteria. analysis.2 Test Methods Performance of the inverters was verified through a combination of testing. Functional Specification for DSP3 Based Grid Tied Inverters.10. In some cases. although minor technical deviations from the specification predictions were observed. 3. Testing of the 10kW and 20kW inverters began with low power operation while verifying the stable. changes to the specification have been proposed. the conversion efficiency.10. the inverter control board was connected to a computer via the JTAG interface. All of the elements of the enhanced DSP3 controller and the manufacturability changes were integrated for testing and debugging. it was supplied from an adjustable DC power source with a variable source resistance. and to monitor and change device parameters. safe operation of the inverters.3 DSP3 Firmware Updates The DSP3 firmware was previously demonstrated to successfully operate the inverters in the grid-tied configuration with nominal input and output conditions. the maximum power point tracking (MPPT) range. Each inverter has been tested per the corresponding performance specifications as proposed. 3. An explanation of the task methodology follows. The Joint Test Action Group (JTAG) defined an interface called the JTAG interface for testing and configuring individual devices on printed circuit boards. In some cases. and review of previously obtained data. without the need to remove the devices from the board. 3.TASK 3. As a result of firmware and hardware optimization. The PWM controller 23 . Output power was increased to demonstrate basic. and the sleep threshold have been modified. the performance of the inverters was found to be desirable. The input power was not derived from a photovoltaic (PV) source. the input voltage range for full power operation. This test method allows a computer-based system to connect to modern CPUs such as DSPs while they are running. full power operation of the inverters.10 Three Phase Inverters and DSP3 Software Integration The purpose of this task was to make the target hardware function correctly with the embedded DSP control firmware.

re-start power production if the fault condition has been cleared.10. cease power production when fault conditions arise. This circuit was replaced with a thermal switch to safely complete the tests.maintained the output current waveforms within the performance specification requirements for THD and Power Factor. • • • The latest source code incorporates the changes and additions to the firmware that were made to facilitate performance to these requirements. Detect the power available from the photovoltaic array. During test of the PV25A.4 Hardware Updates Modifications to the circuitry of both the PV10A and the PV25A inverters were made to complete the functional testing. command the inverter to run and track the maximum power point when the available power is sufficient for the inverter to drive the grid. the temperature sensing circuit failed to detect an over temperature condition. The PV10A successfully utilized the same circuit without failure. The semiconductor temperature sensor was found to be sensitive to electromagnetic interference. The design was changed to substitute a passive thermistor for the semiconductor sensor in both the PV10A and PV 25A. 24 . and. after a prescribed delay. and halt operation of the inverter when sufficient power is not available. annunciate the nature of the fault. A variety of functions are performed simultaneously. which may be summarized as follows: • Maintain the output current waveform within the requirements of the performance specification while the input and output parameters vary over a wide range of normal operating conditions. 3. The result of this task has been to expand the functions of the controller to operate the inverters over a broad range of input and output conditions. resulting in the failure of power components. Detect any fault condition that may arise. Calculate and display the inverter operational statistics and mode. due to either external conditions or malfunction within the inverter.

Phillips model 3394A. each inverter was able to track down only to that limit. Power Analyzers. The algorithm is a perturb and observe function. 0-600 Volt. Functional Specification for DSP3 Based Grid Tied Inverters. the Maximum Power Point Tracking (MPPT) algorithm is operative. The inverters were able to track the maximum power point of the DC source within ±4 Volts DC. In the power tracking mode. Oscilloscope. Voltmeters.5 • • • • • • 3. Performance to this requirement was tested utilizing a DC power source with DC current limiting and a source resistance of 1 ohm. and resume tracking when the MPP was raised. 0-100 Amp. 25 . with source resistor. of document DSP3 FS 102502.10. The MPPT continuously seeks the PV array operating point that yields the most output power. 30KVA. The following specification compliance discussion applies equally to the PV10A and PV25A inverters unless noted otherwise.10. 3-phase. Technical Requirements. POWER TRACKING MODE This is the mode in which the inverter normally operates when there is sufficient power from the PV array for the inverter to deliver power to the grid. 3. Fluke Models 39 and 41.3. Transformer. 208 Volt. When the MPP was below the calculated DC bus minimum voltage limit. Fluke model 77. 0-12 ohm. The inverter transitions to the power tracking mode when the wake-up test is successfully completed.7 Inverter Operational Modes The inverter controller is based upon a state machine that allows the inverter to operate in one of 4 main modes.6 Test Setup DC power Source. 50A.10. The voltage and current limit point were varied to achieve a maximum power point (MPP) from 300 to 550 VDC. Variac. The DC voltage and the current limit point were varied to simulate the output of a PV array as the solar conditions change. 208 Volt Delta to 120/208 Volt Wye. 3-phase. Test Results The following equipment was utilized in the testing of the inverters: The technical requirements and predictions for the two inverters are specified in section 5.

26 70 . the inverter enters the shutdown mode. or to reset the DSP via the JTAG interface. Both inverters operate in a stable manner in the manual mode. The firmware code for 50 Hz operation selects an alternate numerical sine wave table that has been calculated by the same means as the 60 Hz table. Operation has not been tested 50 Hz.8 Auto-Frequency Detection The DSP controller firmware has algorithms for both 50 Hz and 60 Hz operation. in order to clear the shutdown mode. and to create fault conditions.67mS. Both inverters functioned successfully in all of these conditions. 16. All other firmware functions are performed utilizing the same exact code. 3. A potentiometer on the controller circuit board is available to adjust the inverter power level while in this mode. SHUTDOWN Whenever a latching fault is detected. It is necessary to remove and reapply the AC power to the inverter. and changes a system timer for a nominal period of 20 mS v.10. Upon initial power-up. each inverter successfully detected the operating frequency of 60 Hz. to provide them with manual control of basic inverter functionality. It is also executed after the detection and response to any recoverable fault. Both inverters functioned successfully when latching fault conditions were imposed. and when an inverter is in manual mode and is commanded to stop.500 400 VOLTS 300 200 100 20 30 40 50 60 10 AMPS Characteristics of Simulated Array MANUAL MODE This mode is intended for maintenance and test personnel only. The output current was adjusted from 5% to 100% of rated output current power while the input was varied over the full range specified. The manual mode was utilized during the testing of the inverters in order to maintain operating conditions independent of the MPPT circuit. STANDBY MODE The controller executes the standby mode when there is insufficient energy from the PV array to provide positive power transfer.

Each inverter was powered up with the input wiring configured first for clockwise rotation of the AC line voltage.10. Both inverters successfully calculated the VMIN BUS value.10 Power Quality Output power quality is maintained by hardware components and firmware optimized to exceed the requirements of IEEE-519/929.12 DC Bus Minimum Voltage Limit In order to minimize Total Harmonic Distortion (THD).10. documented. 27 .10 of document DSP3 FS 102502. Both inverters successfully demonstrated compliance with the data sheet predictions relating to power quality.7. 3. This allows proper operation of the inverter when installed in either phase sequence arrangement. This limit is dynamically adjusted to compensate for utility voltage fluctuations throughout the day. 3. and performed the power tracking function while preventing the DC bus voltage from going below the calculated VMIN POWER TRACKER voltage.3. Functional Specification for DSP3 Based Grid Tied Inverters.13 Inverter Software Protection The PV grid tied inverter incorporates a variety of protection functions designed to protect the inverter from damage. Some of these protection functions are triggered by software while others are triggered by hardware.10. and then again with counter-clockwise phase rotation. 3. The inverters successfully detected the rotation and delivered output current with the correct rotation to deliver power to the utility grid. That exercise has been successful completed. 3. and submitted in Deliverable D2. the inverter detects the line voltage phase sequence rotation. the minimum DC bus voltage is limited to a numerical value that is a function of the peak-to-peak AC line voltage. These requirements are defined in section 5. Both of the inverters successfully performed these functions.10.10. and sets the switching order of the power bridge devices. Both cause software to annunciate the condition to the operator interface.9 Auto-Phase Sequence Detection Upon initial power-up.11 Third Party Certification The inverters were submitted to UL for preliminary mechanical and electrical evaluation. as detailed in the following sections.

frequencies. which destabilize balanced loads and drive the inverter induced voltage and frequency output outside of the acceptable limits. If the voltage or frequency exceeds the high or low limits.14 Line Voltage / Frequency Detection The inverter continuously measures the line voltage and frequency in all operating states except for shutdown.7 Hz. precision. = 208 Vrms. these tests did successfully verify that the fault detection firmware performed the desired detection and responses.10. An alternate test method was used to substantially achieve the same results. <= Base . 3. <= 88% of nominal. shutdown within 6 cycles. shut down within 120 cycles. The precise adjustment and measurement of utility frequency and voltage requires a high power. After the line voltage and frequency have returned to the normal range for a period of 5 minutes. The line voltage fault detection for undervoltage and overvoltage has been verified with the units running. the inverter ceases to deliver power to the grid and annunciates the detected fault. as specified in UL1741. utilizing a variable transformer. This specialized equipment was not available. <= 50% of nominal. overfrequency. shut down within 120 cycles. the inverter resumes normal operation.0. 3. = 60. These fault conditions are also related to the island detection methods. Theses limits are programmed into the DSP controller. and response times was not possible. 28 . grid simulator.15 Voltage and Frequency Limits for Utility Interaction These limits are preset to the levels described below.0 Hz.3. An oscillator was used to inject a 60 Hz signal to the DSP controller. The frequency at which the frequency fault response occurred was measured on an oscilloscope. shut down within 2 cycles. Frequency detection and fault response were verified with the inverter bridges disconnected from the AC line. They are equivalent to those found in the IEEE-929 and UL1741 standards: Extreme High Voltage: High Voltage: Nominal Voltage: Low Voltage: Extreme Low Voltage: High Frequency: Base Frequency: Low Frequency: >= 137% of nominal. undervoltage. shut down within 2 cycles. low distortion.5 Hz. as well as load destabilization algorithms in compliance with UL1741. >= Base + 0.10. Although exact measurement of the trip voltages. Detection of islanding from the utility grid is achieved via AC overvoltage. shutdown within 6 cycles.10. >= 110% of nominal. and underfrequency detection functions. A review of the firmware source code has verified that the set-points and response times are programmed to the desired values.16 Island Detection The potential for an island condition occurs when the utility power is interrupted while the inverter is delivering power. 3-phase.

When the heatsink temperature exceeds a predefined level it will declare an over-temperature condition. When a hardware fault signal occurs the system will immediately shut down the inverter and annunciate the fault to the operator interface. This fault condition is latching and requires service attention.10. The performance specification states that the overtemperature fault will occur at a heatsink temperature of 90 degrees Centigrade. the destabilized load will drive the inverter beyond the programmed limits for AC line voltage and/or frequency. The voltage and frequency fault detection and the output current phase shift have been successfully verified. the occurrence of this fault usually indicates the inverter is pushing current against the PV array.17 Device Over-Temperature The DSP3 controller monitors the heatsink temperature via a solid-state temperature sensor. Each inverter was subjected to a DC overvoltage condition and safely shut down. and the unit will be powered down. causing the inverter to shut down within two seconds. If an island situation occurs. the inverter resumes normal operation. in the controller firmware. Actual testing in island conditions has not been performed on the PV10A and the PV25A. the AC line voltage will no longer be present. Voltage frequency and magnitude are measured every cycle and compared to the programmed limits. This method of island protection is identical to that as performed by the existing PV10 and PV20 inverters. After the inverter has cooled to the normal range for a period of 5 minutes. The inverter ties the PV array conductors directly to the DC bus. 3. Output currents are shifted twice per second. Upon restoration of the AC line voltage. When the overvoltage condition was eliminated and power was removed and reapplied. When an over-temperature condition is detected. the inverter will shut down and annunciate this fault to the operator interface. When the inverter shuts down due to an island condition. causing the PV voltage to increase. Therefore. the inverter ceases to deliver power to the grid and annunciates the over-temperature fault on the LCD display.Load destabilization is accomplished with an upward and downward current phase shift relative to phase voltage. That limit has been set to 75 degrees C. 3. Shifting the current phase angles in this manner will destabilize balanced resonant loads that have been disconnected from the utility. 29 .18 DC Bus Over-Voltage Detection The inverters have bus over-voltage hardware and software detection. the inverters resumed normal operation. If the PV system has been correctly designed. the open-circuit voltage should never exceed 600VDC.10. In the event the PV voltage exceeds 600VDC. which have passed testing to UL1741. to enhance the product reliability. the inverter will proceed through the normal power-up initialization process.

At very low operating currents. DC Voltage . When the imbalance condition was eliminated and power was removed and reapplied. the inverter resumes normal operation This function was tested by operating the inverters in the manual mode and overriding the software limit.This shows the inverter’s DC input in volts. the inverters resumed normal operation.This is the current operating state of the inverter as defined in 3. The inverters are designed to prevent output current imbalance in all operating conditions. 3.3.20 Over Current This fault indicates that the output current of the bridge has exceeded the maximum allowed.19 Current Imbalance This fault condition checks for imbalance in the three AC current measurements. This fault condition is normally checked only in the Power Tracking state.10. The DSP3 board checks the three AC line RMS current values to ensure each one is within 10% of the median (middle) value for 120 continuous cycles. In normal operation. The display functions as follows: System Status .10. After a period of 5 minutes.8. This line is only displayed in the power tracking or manual running modes. the inverter shuts down and annunciates this fault to the operator interface.1 AC Power in Watts . This fault is latching and must be cleared by removing and reapplying the power to the inverter.10. A window on the inside of the door protects the LCD.21 Operator Interface LCD The LCD interface is standard equipment. and the inverter successfully responded with the desired current imbalance fault. the current imbalance may exceed 10%. 3. The display consists of a 1 line. and the input voltage was reduced until the output current diminished. the inverter ceases to deliver power to the grid and annunciates the detected fault on the LCD display. the firmware was modified. 16-character liquid crystal display located on the DSP3 controller board. This line is only displayed in the power tracking or manual running modes. In order to test this feature. The current imbalance detection was enabled for all levels of output current. In this case. 2 to 3 seconds for each parameter (line of text). 30 . This value is filtered to compensate for noise fluctuations. A viewing slot is cut in the front door of the enclosure. when the output current is at least 20% of the full rated output current. the maximum current may be exceeded. Under this condition the current balance is no longer maintained. This value is filtered to compensate for noise fluctuations. the inverters correctly detected and responded to the fault. When the current imbalance fault is detected. When the output current was manually adjusted beyond the current limit point. During some AC line transient conditions. the DSP3 controller will prevent the output current from exceeding the maximum limit by overriding the Peak Power Tracker and limiting the AC current command. The display shows 4 different parameters in rotation.This shows the real time power output of the inverter.

Line 4: Cumulative Output Energy. The states defined below are used to perform the various modes of operation defined above.22 Operating States The following is a list of states defining the inverter state machine. The total is stored in nonvolatile memory once every hour.10. and retrieved for display.## KWHR” The inverters correctly calculated and displayed the cumulative output energy.This parameter continually calculated whenever the inverter is in the power tracking state or running in the manual mode. and is retrieved from nonvolatile memory whenever the inverter transitions to the power tracking state or begins running in the manual mode. Line 2: AC Power: “##### WATTS AC” The inverters correctly computed the AC power output and displayed that quantity while in the power tracking and manual running modes. Line 3: DC Voltage: “### VOLTS DC” The inverters correctly measured and displayed the DC input voltage while in the power tracking and manual running modes.Cumulative Output Energy in Kilowatt-Hours . The cumulative energy value. and whenever the inverter transitions to the fault state or the standby state. accrued from the time of commissioning. DISPLAYED PARAMETERS Line 1: System Status • “STANDBY” • “WAKE UP TEST” • “POWER TRACKING” • “SLEEP TEST” • “MANUAL MODE” • “SHUTDOWN” • “OVER TEMPERATURE” • “OVERCURRENT” • “DC OVERVOLTAGE” • “AC FREQ FAULT” • “AC VOLTAGE LOW” • “AC VOLTAGE HIGH” • “AC CURRENT IMBAL” The inverters correctly displayed all of the above status parameters. was successfully stored in nonvolatile memory. 31 . “#### ###. 3.

Both inverters successfully invoked the standby state. The power tracking range has been set to 300 to 550 volts. and the highest voltage for full rated output power is 500VDC. The inverter is idle. then the state machine will automatically transition to the Manual Current state whenever IOPB4 is set to 1. Once these conditions are met and the goal state is Power Tracking. The inverter will remain in this state until the PV voltage exceeds the PV Wake-Up value. These values allow for maximum harvest of energy from standard PV array configurations and maintain suitable margin for reliable inverter operation. This function is also commonly defined as Peak Power Tracking (PPT). The inverter correctly sensed the input conditions and transitioned between Standby. The control system commands output current to the utility. The line contactor is open and the devices are not switching. Both inverters have demonstrated the successful implementation of the power tracking state. the state machine will transition to the 32 . While in the standby state. Once the voltage on the array exceeds the wakeup voltage value for 5 minutes. and Power Tracking. SYSTEM WAKE-UP TEST This state only occurs during the transition from standby to power tracking. The power tracker algorithm optimizes output power given a variety of solar irradiance and array temperature conditions. the sleep test begins. the state machine will automatically transition to System Wakeup Test state. or the inverter has responded to a fault condition. This generally indicates the PV array is not energized. If the goal state is set to manual mode. If this condition persists continuously for five minutes. The specification target for the power tracking range was 300 to 570 Volts. the inverter will check to see if the voltage has exceeded the start voltage. When the output power drops below 2% of the full rated power of the inverter. including optimization algorithm for adjusting the wake up voltage. the inverter will commence the wake up test. If the PV voltage does not reach the start voltage limit. POWER TRACKING This is the main operating state of the inverter. With an absolute maximum open circuit voltage limit of 600VDC. This indicates that the array is on the threshold of having enough energy capacity to support the operating losses of the inverter. Condition: The PV array voltage is greater than the wake-up voltage level. no PV array will generate maximum power at 570 Volts. will transition to the power tracking state. Wake Up Test. SLEEP TEST This state only occurs during the transition from power tracking to standby. while calculating the output power to the grid.STANDBY Condition: The PV array does not have enough power capacity to maintain the inverter system operating losses. the state machine will transition back to the standby state. and has returned to standby because the fault has cleared. and if so. once the input voltage exceeds the wake-up voltage.

The fault condition is displayed on the LCD. It allows the inverter to deliver a fixed output current. if the inverter power output rises above the sleep test value. LATCHING FAULTS Current imbalance and DC bus overvoltage are latching faults. These faults caused the inverter to go into the shutdown state. the DSP controller performs a power-down and disconnects the inverter from the utility. each fault was cleared and the state machine transitioned to the standby state. and transitioned to the Shutdown state. 3.10. Both inverters operate correctly in the manual mode when the IOPB4 jumper is set to the 1 position. and successfully detected and responded to these conditions. and once the value was returned to a normal operating range for 5 minutes. This manual interaction is required. SHUTDOWN When a DC overvoltage fault condition or a line current imbalance fault condition was created. the inverter will transition back to Power Tracking.Standby state. MANUAL CURRENT This state is only available in the manual operating mode. The controller continued to monitor the specific parameter. because faults of this nature usually indicate a catastrophic hardware failure. regardless of available PV array power. When the inverter experiences a fault condition. 33 . While in the sleep test state. the inverter successfully detected and annunciated the fault. the system successfully returned to a normal operating state once the fault condition was removed. FAULT CONDITIONS AC Line Frequency AC Line Voltage Low AC Line Voltage High Device Overtemperature DC Bus Over Voltage Current Imbalance Over Current AUTO-RECOVERABLE FAULTS For those faults defined as recoverable.23 Fault Detection and Annunciation The inverters were tested for all fault conditions defined by the specification. It was necessary to remove and re-apply AC power to the inverter to reset either of these faults.

208 VDC 75° C. Nominal Standby Raise DC Bus 600VDC Nominal 50% Load Minimum Reduced Overload Manual Adjustment Normal Operation Detects 60 Hz Detects Phase Reverse Line-Phase Rotation Rotation √ √ (4) √ 183 V (2) 230 V (2) 59.99 0.10.99 >= 0.4 28 Amps 28. 208 VDC LIMIT CONTROLLER ID: 3 Measured 10. 208 VDC Minimum limited by (VAC*root2*1.1 Second Dalay Signal Injection > 60.5 Hz (2) √ 76 602 √ 32 √ √ 34 .0 >= 0.3.97 >= 0.0 0.99 >= 0.1 Second Delay 100% Load Verify Phase-angle Sequencing 100% Load 350 VDC.5 4.99 1.85 0.5 Hz 0.99 1.4 <= 5% 3.3 Hz 0.24 TEST DATA PV10A TEST DATA PV10A TEST DATA BRIDGE ID: 1 Test Nominal Power Rating Maximum Line Current Test Conditions 350 VDC 330VDC 208 VAC 550 VDC 350 VDC 100% Load 75% Load 350 VDC 50% Load 25% Load 100% Load 75% Load 500 VDC 50% Load 25% Load 100% Load 350 VDC.07) + 25 50% Load 100% Load >= 96% 75% Load >= 96% 350 VDC 50% Load >= 94% 25% Load >= 94% Standby <= 30W Self-Adjusting Increasing DC Voltage 208 VAC 5 Minutes < 200 Watts Decreasing Power 5 Minutes < 183VAC 2 Second Delay Vary Line Voltage > 229VAC 2 Second Delay < 59.7 10.98 0.95 4.7 <= 5% 3.85 0.5 10 KW 10.0 4.0 0.3 Hz (2) 60.5 4.2 340-550 VDC 349-508 (3) (1) (1) (1) (1) 4 320 Power Factor Current Distortion Phase-A Current Distortion Phase-B Current Distortion Phase-C Current Distortion Phase-A Current Distortion Phase-B Current Distortion Phase-C Power Tracking Range DC Bus Minimum Voltage Limit Conversion Efficiency Standby Losses Wake-up Voltage Wake-up Delay Sleep Threshold Sleep Shutdown Delay Under-Voltage Fault Over-Voltage Fault Under-Frequency Fault Over-Frequency Fault Anti-Islanding Protection Over-temperature Fault DC Bus Over-Voltage Fault Line Current Imbalance Fault Line Overcurrent Fault Frequency Detection Auto-Phase Sequence Detection 100% Load 500 VDC.

2 to 28. Run. 35 . Adjust input for > 1000W for > 5 minutes.Test Test Conditions Standby Wake Up Test Power Tracking Low DC Voltage Raise DC Voltage Normal Operation LIMIT “STANDBY / KWHR” “WAKE UP TEST / KWHR” “POWER TRACKING / WATTS AC / VOLTS DC / KWHR” “SLEEP TEST / WATTS AC / VOLTS DC / KWHR” “STANDBY / KWHR” “SHUTDOWN” “OVER TEMPERATURE” Re-Starts “OVER CURRENT” Re-Starts “AC FREQ FAULT” Re-Starts “AC VOLTAGE LOW” Re-Starts “AC VOLTAGE HIGH” Re-Starts “AC CURRENT IMBAL” Latches off “OVER VOLTAGE” Latches Off 1. allow unit to complete sleep test. Display Over Temperature Over Current AC Frequency Fault AC Voltage Low AC Voltage High AC Current Imbalance DC Overvoltage Manual Operation Manual Current Initial wake-up Voltage Wake-up Test Timer Adjust input for < 500 Watts AC.1 320 324 320 Shutdown State Controller. Force Overcurrent Fault Conditions Adjust output current Test data sheets have been prepared and completed for both inverters.9) + 5 = 320 VDC Re-start: Wake-up Voltage Re-start: Wake-up Voltage 325 VDC 320 VDC Measured √ √ √ Sleep Test / Standby Reduce DC Voltage √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 1. These data sheets address each of the requirements and predictions stated in the performance specifications.4 to 28 Amps (350*.

0 >= 0.0 1.3 Hz 0.1 Second Dalay Signal Injection > 60.7 25 KW 25.0 >= 0. 208 VDC 75° C.8 340-550 VDC 348 – 507 (3) (1) (1) (1) (1) 5 318 Power Factor Current Distortion Phase-A Current Distortion Phase-B Current Distortion Phase-C Current Distortion Phase-A Current Distortion Phase-B Current Distortion Phase-C Power Tracking Range DC Bus Minimum Voltage Limit Conversion Efficiency Standby Losses Wake-up Voltage Wake-up Delay Sleep Threshold Sleep Shutdown Delay Under-Voltage Fault Over-Voltage Fault Under-Frequency Fault Over-Frequency Fault Anti-Islanding Protection Over-temperature Fault DC Bus Over-Voltage Fault Line Current Imbalance Fault Line Overcurrent Fault Frequency Detection Auto-Phase Sequence Detection 100% Load 500 VDC.0 3.4 70 Amps 71A >= 0.0 25.99 1.8 4.8 2.1 Second Delay 100% Load Verify Phase-angle Sequencing 100% Load 350 VDC.5 Hz 0. Nominal Standby Raise DC Bus 600VDC Nominal 5% Load Minimum reduced Overload Manual Adjustment Normal Operation Detects 60 Hz Detects Phase Reverse Line-Phase Rotation Rotation √ √ (4) √ 182 V (2) 229 V (2) 59.0 0.99 >= 0.85 1.0 1.5 <= 5% 2. 208 VDC CONTROLLER ID: 4 LIMIT Measured 25. 208 VDC Minimum limited by (VAC*root2*1.3 Hz (2) 60.07) + 25 50% Load 100% Load >= 96% 75% Load >= 96% 350 VDC 50% Load >= 94% 25% Load >= 94% Standby <= 30W Self-Adjusting Increasing DC Voltage 208 VAC 5 Minutes < 500 Watts Decreasing Power 5 Minutes < 183VAC 2 Second Delay Vary Line Voltage > 229VAC 2 Second Delay < 59.7 3.85 1.5 Hz (2) √ (5) 600 √ 75 A √ √ 36 .0 1.99 1.PV25A TEST DATA BRIDGE ID: 1 Test Nominal Power Rating Maximum Line Current Test Conditions 350 VDC 330VDC 208 VAC 550 VDC 350 VDC 100% Load 75% Load 350 VDC 50% Load 25% Load 100% Load 75% Load 500 VDC 50% Load 25% Load 100% Load 350 VDC.1 <= 5% 2.

allow unit to Wake-up Voltage complete sleep test. Force Overcurrent Fault Conditions Adjust output current Wake-up Test Timer Initial wake-up Voltage Adjust input for < 500 Re-start: Watts AC.9)+5 = 320 VDC 324 VDC Measured √ √ √ Sleep Test / Standby Reduce DC Voltage √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 3. Adjust input for > 1000W for > 5 minutes. Re-start: Wake-up Voltage 320 VDC 318 37 .3 to 71 318 323 Shutdown State Controller.PV25A TEST DATA Test Test Conditions Standby Wake Up Test Power Tracking Low DC Voltage Raise DC Voltage Normal Operation LIMIT “STANDBY / KWHR” “WAKE UP TEST / KWHR” “POWER TRACKING / WATTS AC / VOLTS DC / KWHR” “SLEEP TEST / WATTS AC / VOLTS DC / KWHR” “STANDBY / KWHR” “SHUTDOWN” “OVER TEMPERATURE” Re-Starts “OVER CURRENT” Re-Starts “AC FREQ FAULT” Re-Starts “AC VOLTAGE LOW” Re-Starts “AC VOLTAGE HIGH” Re-Starts “AC CURRENT IMBAL” Latches off “OVER VOLTAGE” Latches Off 3.5 to 70 Amps (350*. Display Over Temperature Overcurrent AC Frequency Fault AC Voltage Low AC Voltage High AC Current Imbalance DC Overvoltage Manual Operation Manual Current Run.

6 % 95. resulting in the failure of power components. The power conversion efficiency of the PV25A has not been tested for lack of a power analyzer with the required precision. NOTE 2 – MPPT RANGE The proposed MPPT range for the inverters was 300 to 570 VDC. Due to firmware and hardware constraints. the inverters have been set up for a MPPT range of 300 the 550 VDC.5 KW 5. the same level as is used in the PV10 and PV20 inverters. prior to completion of full functionality of the inverters. The data collected earlier for the PV10A indicates a peak efficiency of 96%.25 Notes to the Data Sheets NOTE 1 . These values allow for maximum harvest of energy from standard PV array configurations and maintain suitable margin for reliable inverter operation.CONVERSION EFFICIENCY Efficiency measurements on the PV10A inverter have been documented previously. with full rated output power available up to 500 VDC input. the temperature sensing circuit failed to detect an over temperature condition. efficiency curves will be close to identical.SLEEP THRESHOLD The specification states that the sleep test shall be invoked.5 KW MEASURED EFFICIENCY 95. in each inverter. when the output current is less than 0. This circuit was replaced with a 38 .3 % PREDICTED EFFICIENCY 96 % 96 % 94 % 94 % The measurements at 75% and 100% of full rated output power fall fractionally short of the predicted value given in the DSP3 functional specification while the efficiencies at 50% and 25% of rated power exceed the predicted values.OVER TEMPERATURE LIMIT During test of the PV25A. OUTPUT POWER 10 KW 7. This added "flatness" of the power vs. NOTE 3 . efficiency curve due to the enhanced performance at lighter loads is desirable and is viewed by the design team as an equitable tradeoff for the fractional reduction in full power efficiency.10.3.9 % 95.5 Amps. The design methodology for the PV10A and PV25A are very similar and it is anticipated that the power vs. The sleep test thresholds have been set to a power level of 2% of rated full power output. NOTE 4 . with a maximum peak open circuit input voltage of 600 VDC.0 KW 2. The nature of photovoltaic modules is that the peak power voltage is always considerably lower than the open circuit voltage.5 % 94. This value is too low because reactive current at very low power levels can prevent the inverters from going into the sleep test mode. It is proposed that the final validation of the efficiency parameter for the PV25A be had during the performance testing at Sandia National Laboratories.

thermal switch to safely complete the tests. The PV10A successfully utilized the design circuit without failure. However, it is proposed that this circuit be updated to utilize a thermistor, rather than the solid-state temperature sensor, to increase reliability. Additionally, the set point proposed in the specification is 90°C. The firmware has been created with an over temperature set point of 75°C. This can be easily adjusted if field testing suggests the need. 3.10.26 PV10A Power Data The output power of 10 kilowatts was achieved with a reading of 3.3 kW on phase-A and Phase-B, and a reading of 3.4 kW on Phase-C, for a total of 10 kW. The following data demonstrate the full rated output power and the Power Factor (PF):

PV10A Power Factor (PF) at 25% of rated output current was almost as high as at 100% power:

PV10A output current sinusoidal waveforms at full rated output power:

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3.10.27 PV25A Power Data The output power of 25 kilowatts was achieved with a reading of 8.2 kW on phase-A, and a reading of 8.5 kW on Phase-B and Phase-C, for a total of 25.2 kW. The following data demonstrate the full rated output power and the Power Factor (PF):

PV25A power factor at 25% of rated output current was almost as high as at 100% power:

PV25A output current sinusoidal waveforms at full rated output power:

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3.10.28 Proposed Changes
Parameter Conversion Efficiency, 50%-100% load Conversion Efficiency, 25% load Max Power Tracking Range Full Power Input Range Sleep Threshold Overtemperature Fault Specification Prediction 96% 94% 300-570 VDC Not Specified ILINE < 0.5 Adc THEATSINK > 90°C Proposed 95.5% 94% 300-550 VDC 330-500 VDC POUT < 2% THEATSINK > 75°C

As a result of firmware and hardware optimization, the input voltage range for full power operation, the maximum power point tracking (MPPT) range, the over temperature fault limit, the conversion efficiency, and the sleep threshold have been modified. The reduction in the upper limits of the DC input voltage is a moot point because no known PV technology with an open circuit voltage of 600Vdc has a max power point above 480Vdc. The sleep threshold was improved to prevent the inverter from not entering the sleep mode at night. The reduction in heatsink temperature was implemented to improve overall product reliability. The overall goals of this specification compliance task for the 3-phase inverters have been met. All of the "hard" DSP3 performance specifications required for third party approval have been met. All of the test results verifying the predicted "soft" inverter performance parameters were met with a few minor exceptions. The exceptions are highlighted in the test data and discussion, and summarized above. TASK 3.11 PV2.5A, Single-phase Inverter and DSP1 Software Integration

The purpose of this task was to make the target hardware function correctly with the embedded DSP control firmware. All of the elements of the enhanced DSP1 controller and the manufacturability changes have been integrated for testing and debugging. Testing of the 2kW single-phase inverter began with low power operation while verifying the stable, safe operation of the inverters. Output power was increased to demonstrate basic, full power operation of the inverters. The expected result of this task was to test the 2kW inverter per the corresponding performance specifications and meet or exceed the specified performance criteria. An explanation of the task methodology follows. 3.11.1 PV2.5A Grid-Tied Inverter Operation

The PV2.5A inverter has been operated through a series of tests devised to compare operation of each unit to the corresponding performance specifications as defined in document DSP1 FS 102502, Functional Specification for DSP1 Based Grid Tied Inverter. In some cases, the performance of the inverter was found to be desirable, although minor technical deviations from the specification predictions were observed. In these cases, changes to the specification have been proposed. As a result of firmware and hardware optimization, specifications for the input voltage range and the maximum power point tracking (MPPT) range have been modified. Each inverter has been tested per the corresponding performance specifications as proposed, and has met or exceeded the specified performance criteria.

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the inverter control board was connected to a computer via the JTAG interface.11. This test method allows a computer-based system to connect to the Digital Signal Processor (DSP) while the inverter is running. and. The latest source code incorporates the changes and additions to the firmware that were made to facilitate performance to these requirements. due to either external conditions or malfunction within the inverter. Detect any fault condition. The PWM controller maintained the output current waveforms within the performance specification requirements for THD and Power Factor.3. and review of previously obtained data.2 PV2. annunciate the nature of the fault.11.5A Test Methods Performance of the inverter was verified through a combination of testing. This allows for the complete control of the input parameters. 3. analysis. which may be summarized as follows: • Maintain the output current waveform within the requirements of the performance specification while the input and output parameters vary over a wide range of normal operating conditions. it was supplied from an adjustable DC power source with a variable source resistance. which is necessary to demonstrate the inverter performance over a wide range of normal and fault conditions. Calculate and display the inverter operational statistics and mode. In some cases. without the need to remove the devices from the board. Rather. The input power was not derived from a photovoltaic (PV) source. The result of this task has been to expand the functions of the controller to operate the inverter over a broad range of input and output conditions. A variety of functions are performed simultaneously. command the inverter to run and track the maximum power point when the available power is sufficient for the inverter to drive the grid. independent of weather conditions. which may arise. re-start power production if the fault condition has been cleared.3 DSP1 Firmware Updates The DSP1 firmware was previously demonstrated to successfully operate the inverter in the grid-tied configuration with nominal input and output conditions. and to monitor and change device parameters. Detect the power available from the photovoltaic array. cease power production when fault conditions arise. The Joint Test Action Group (JTAG) defined an interface called the JTAG interface for testing and configuring individual devices on printed circuit boards. and halt operation of the inverter when sufficient power is not available. after a prescribed delay. • • • • 42 .

In the power tracking mode.11. lower-resistance devices. Phillips model 3394A Power Analyzer. of document DSP1 FS 102502.11.5A inverter were made to complete the functional testing. 3. The algorithm is a perturb and observe function. The state machine for the DSP1 controller is derived directly from the state machine in the DSP3 controller that has also been developed under this contract. The voltage rating and the extremely high speed of these FETs results in the requirement that the inverter input voltage be maintained below 100VDC.4 PV2. Without a detailed marketing analysis. 0-600 Volt.3. the power FETs were replaced with higher-speed.11. Voltech model PM3000A 3. Functional Specification for DSP1 Based Grid Tied Inverter. Fluke Models 41 Power Analyzer. 3.5A Inverter Operational Modes The inverter controller is based upon a state machine that allows the inverter to operate in one of four main modes. In order to meet the efficiency goal for the inverter. 0-100 Amp.5A Test Results The technical requirements and predictions for the inverter are specified in Section 5. The DC voltage and the current limit point were varied to simulate the output of a PV array as the solar conditions change.11. it was assumed that the value of higher conversion efficiency was greater than the value of an extended PV input voltage range. The inverter transitions to the power tracking mode when the wake-up test is successfully completed.7 PV2.5A Test Setup The following equipment was utilized in the testing of the inverter: DC power Source. The MPPT continuously seeks the PV array operating point that yields the most output power. Technical Requirements. the Maximum Power Point Tracking (MPPT) algorithm is operative. Performance to this requirement was tested utilizing a DC power source with DC current limiting and a source resistance of 1 ohm.6 PV2. 43 . with source resistor. 0-12 ohm Voltmeters.5 PV2. POWER TRACKING MODE This is the mode in which the inverter normally operates when there is sufficient power from the PV array for the inverter to deliver power to the grid.5A Hardware Updates Modifications to the circuitry of the PV2. Fluke model 77 Oscilloscope.

in order to clear the shutdown mode. STANDBY MODE The controller executes the standby mode when there is insufficient energy from the PV array to provide positive power transfer. or to reset the DSP via the JTAG interface. A set of pushbuttons on the controller circuit board is available to select this mode. The inverter operates in a stable manner in the manual mode. The manual mode was utilized during the testing of the inverter in order to maintain operating conditions independent of the MPPT circuit. and to adjust the inverter power level while this mode is selected. 10 44 40 . The inverter functioned successfully when latching fault conditions were imposed. and to create fault conditions. the inverter enters the shutdown mode. The output current was adjusted from 5% to 100% of rated output current power while the input was varied over the full range specified. It is necessary to remove and reapply the AC power to the inverter. to provide them with manual control over all basic inverter functionality. The inverter functioned successfully in all of these conditions. SHUTDOWN Whenever a latching fault is detected. and when an inverter is in manual mode and is commanded to stop.80 VOLTS 60 40 20 20 30 Volt/Amp Characteristics of Simulated Array MANUAL MODE This mode is intended for maintenance and test personnel only. It is also executed after the detection and response to any recoverable fault.

This limit is dynamically adjusted to compensate for utility voltage fluctuations throughout the day.11. the inverter ceases to deliver power to the grid and annunciates the detected fault.12 PV2.5A Third Party Certification The inverter was submitted to UL for preliminary mechanical and electrical evaluation.11 PV2. The inverter successfully calculated the VMIN BUS value.11. Functional Specification for DSP1 Based Grid Tied Inverter. as detailed in the following sections. If the voltage or frequency exceeds the high or low limits. After the line voltage and frequency have returned to the normal range for a period of 5 minutes.8. of document DSP1 FS 102502. These requirements are defined in section 5. The line voltage fault detection for undervoltage and overvoltage has been verified with the units running. Since line voltage fluctuations are relatively slow. The precise adjustment and measurement of utility frequency and voltage requires specialized equipment that is not available to us at this time. 3.8 under this subcontract. utilizing a variable transformer.5A Power Quality Output power quality is a maintained by hardware components and firmware optimized to exceed the requirements of IEEE-519/929. this value is averaged using a first order filter. frequencies. Frequency detection and fault response was verified with the inverter bridges disconnected from the AC line. 3. Performance Specifications.9 PV2.10 PV2.5A DC Bus Minimum Voltage Limit In order to minimize Total Harmonic Distortion (THD). The inverter successfully performed these functions. Some of these protection functions are triggered by software while others are triggered by hardware. The frequency at which the frequency fault response occurred was measured on an oscilloscope. and response 45 . That exercise has been successful completed.11. The inverter successfully demonstrated compliance with the data sheet predictions relating to power quality.5A Inverter Software Protection The PV grid tied inverter incorporates a variety of protection functions designed to prevent damage to the inverter. which destabilize balanced loads and drive the inverter induced voltage and frequency output outside of the acceptable limits.3. Although exact measurement of the trip voltages. and submitted in Deliverable D2. Both cause the software to annunciate the condition to the operator interface.11. 3. the inverter resumes normal operation. An oscillator was used to inject a 60 Hz signal to the DSP controller. the minimum DC bus voltage is limited to a numerical value that is a function of the peak-to-peak AC line voltage. 3. documented.11.8 PV2.5A Line Voltage / Frequency Detection The inverter continuously measures the line voltage and frequency in all operating states except for shutdown. These fault conditions are also related to the island detection methods.

The method is identical to that as performed by the existing Xantrex PV10208 and PV20208 inverters. When the inverter shuts down due to an island condition. If an island situation occurs. shutdown within 6 cycles.5A Island Detection The potential for an island condition occurs when the utility power is interrupted while the inverter is delivering power. Shifting the current phase angles will destabilize balanced resonant loads that have been disconnected from the utility. the AC line voltage will no longer be present. overfrequency. 46 . <= 88% of nominal. causing the inverter to shut down within two seconds.13 PV2.14 PV2.0 Hz. Load destabilization is accomplished with an upward and downward current phase shift relative to phase voltage.5A Voltage and Frequency Limits for Utility Interaction These limits are preset to the levels described below. A review of the firmware source code has verified that the set-points and response times are programmed to the desired values. 3.16. shut down within 120 cycles. <= Base .7 Hz. shut down within 2 cycles. >= 110% of nominal. and underfrequency detection functions. which have passed testing to UL1741.16. = 240 Vrms. When the AC line voltage is restored. >= Base + 0. SNL Testing. shutdown within 6 cycles. shut down within 120 cycles. <= 50% of nominal.times was not possible. shut down within 2 cycles. as well as load destabilization algorithms in compliance with UL1741. The voltage and frequency fault detection and the output current phase shift have been successfully verified. This method of island protection is proprietary and will not be disclosed in detail. the destabilized load will drive the inverter beyond the programmed limits for AC line voltage and/or frequency. Single-Phase Inverter Prototype. Actual testing in island conditions will be performed during Task 3. 3. the inverter will proceed through the normal power-up initialization process. Full compliance of the line voltage and frequency detection and response will be verified during Task 3.11. They are equivalent to those found in the IEEE-929 and UL1741 standards: Voltage: Extreme High Voltage: High Voltage: Nominal Voltage: Low Voltage: Extreme Low Voltage: Frequency: High Frequency: Base Frequency: Low Frequency: >= 137% of nominal.0. SNL Testing. Single-Phase Inverter Prototype. = 60. these tests did successfully verify that the fault detection firmware performed the desired detection and responses.11.5 Hz. Theses limits are programmed into the DSP controller. Detection of islanding from the utility grid is achieved via AC overvoltage. and the unit will be powered down. undervoltage.

When a hardware fault signal occurs the system will immediately shut down the inverter and annunciate the fault to the operator interface. 16-character liquid crystal display located on the inverter cover and connected to the DSP1 controller board through a ribbon cable. the maximum current may be exceeded. 3. 3.18 PV2.17 PV2.3. the open-circuit voltage should never exceed 100Vdc. the inverter will shut down and annunciate this fault to the operator interface.5A Operator Interface LCD The LCD interface is standard equipment. In normal operation. If the PV system has been correctly designed. The display functions as follows: 47 .16 PV2. During some AC line transient conditions. In the event the PV voltage exceeds 100VDC. Operating the inverter in the manual mode and overriding the software limit tested this function. The inverter ties the PV array conductors directly to the DC bus. When the output current was manually adjusted beyond the current limit point. When an over-temperature condition is detected. lower-resistance devices. 2 to 3 seconds for each parameter (line of text). A window on the inside of the door protects the LCD. 3. The voltage rating and the extremely high speed of these FETs results in the requirement that the inverter input voltage be maintained below 100VDC. In this case. In order to enhance the inverter efficiency.11. the occurrence of this fault usually indicates that the inverter is connected to an incompatible array. The inverter was subjected to a DC overvoltage condition and safely shut down. When the overvoltage condition was eliminated and power was removed and reapplied.11. or four “12 volt” modules. the inverter will disconnect from the utility grid and annunciate the fault condition on the LCD display. When the heatsink temperature exceeds a predefined level. it will declare an over-temperature condition. the inverter correctly detected and responded to the fault. configured in a series string of two modules for the “24 volt” modules.5A DC Bus Over-Voltage Detection The inverter has bus over-voltage hardware and software detection.5A Over Current This fault indicates that the output current of the bridge has exceeded the maximum allowed. The display consists of a 1 line. Therefore. This voltage is compatible with all present production singlecrystal and poly-crystalline modules.11. This fault condition is latching and requires service attention.15 PV2. the power FETs were replaced with higher-speed.11.5A Device Over-Temperature The DSP1 controller monitors the heatsink temperature via a solid-state temperature sensor. The display shows 4 different parameters in rotation. the DSP1 controller will prevent the output current from exceeding the maximum limit by overriding the Peak Power Tracker and limiting the AC current command. the inverter will shut down and announce the over current fault. the inverter resumed normal operation.

This line is only displayed in the power tracking or manual running modes.This parameter is stored in nonvolatile memory. This line is only displayed in the power tracking or manual running modes.1 AC Power in Watts . 48 .6.19 PV2. The states defined below are used to perform the various modes of operation defined above.This shows the real time power output of the inverter.This is the current operating state of the inverter as defined in 3.System Status . DC Voltage . Line 4: Cumulative Output Energy.This shows the inverter’s DC input in volts. Cumulative Output Energy in Kilowatt-Hours . Line 2: AC Power: “##### WATTS AC” The inverter correctly computed the AC power output and displayed that quantity while in the power tracking and manual running modes.11. Line 3: DC Voltage: “### VOLTS DC” The inverter correctly measured and displayed the DC input voltage while in the power tracking and manual running modes. This value is filtered to compensate for noise fluctuations. “#### ###. 3.## KWHR” The inverter correctly calculated and displayed the cumulative output energy.5A Operating States The following is a list of states defining the inverter state machine. and retrieved for display. DISPLAYED PARAMETERS Line 1: System Status • • • • • • • • • • • • “STANDBY” “WAKE UP TEST” “POWER TRACKING” “SLEEP TEST” “MANUAL MODE” “SHUTDOWN” “OVER TEMPERATURE” “OVERCURRENT” “DC OVERVOLTAGE” “AC FREQ FAULT” “AC VOLTAGE LOW” “AC VOLTAGE HIGH” The inverter correctly displayed all of the above status parameters. This value is filtered to compensate for noise fluctuations. The cumulative energy value was successfully stored in nonvolatile memory.

and Power Tracking. once the input voltage exceeds the wake-up voltage. SYSTEM WAKE UP TEST This state only occurs during the transition from standby to power tracking. Condition: The PV array voltage is greater than the wake-up voltage level. the state machine will transition back to the standby state. then the state machine will automatically transition to the Manual Current state. Wake Up Test. Once these conditions are met and the goal state is Power Tracking. The inverter successfully invoked the standby state.STANDBY Condition: The PV array does not have enough power capacity to maintain the inverter system operating losses. In order to facilitate testing. This generally indicates the PV array is not energized. Once the voltage on the array exceeds the wakeup voltage value for 5 minutes. The inverter will remain in this state until the PV voltage exceeds the PV Wake-Up value. The line contactor is open and the devices are not switching. the inverter will commence the wake up test. and has returned to standby because the fault has cleared. the wake-up test time was set to 30 seconds for the balance of the tests. If the PV voltage does not reach the start voltage limit. or the inverter has responded to a fault condition. The inverter correctly sensed the input conditions and transitioned between Standby. will transition to the power tracking state. While in the standby state. The inverter is idle. This indicates that the array is on the threshold of having enough energy capacity to support the operating losses of the inverter. the state machine will automatically transition to the System Wakeup Test state. 49 . the inverter will check to see if the voltage has exceeded the start voltage. and if so. If the goal state is set to manual mode.

3.11. When the inverter experiences a fault condition. MANUAL CURRENT This state is only available in the manual-operating mode. The control system commands output current to the utility. This reset time was adjusted to 30 seconds to facilitate testing of the inverter. while calculating the output power to the grid. 50 . The fault condition is displayed on the LCD.5A Fault Detection and Annunciation The inverter was tested for all fault conditions defined by the specification. if the inverter power output rises above the sleep test value. and once the value was returned to a normal operating range for 5 minutes. The inverter operates correctly in the manual mode when selected by use of the push-buttons on the control board. regardless of available PV array power. It allows the inverter to deliver a fixed output current. the inverter successfully detected and annunciated the fault. the DSP controller performs a power-down and disconnects the inverter from the utility. The power tracker algorithm optimizes the photovoltaic array output power given a variety of solar irradiance and temperature conditions. It was necessary to remove and re-apply AC power to the inverter to reset either of these faults. While in the sleep test state. the state machine will transition to the Standby state.POWER TRACKING This is the main operating state of the inverter. the system successfully returned to a normal operating state once the fault condition was removed. The controller continued to monitor the specific parameter. the sleep test begins. FAULT CONDITIONS AC Line Frequency AC Line Voltage Low AC Line Voltage High Section Device Overtemperature DC Bus Over Voltage Over Current AUTO-RECOVERABLE FAULTS For those faults defined as recoverable. If this condition persists continuously for five minutes. SLEEP TEST This state only occurs during the transition from power tracking to standby. This function is commonly defined as Peak Power Tracking (PPT). and transitioned to the Shutdown state. SHUTDOWN When a DC overvoltage fault condition was created. the shutdown feature was disabled. the inverter will transition back to Power Tracking. allowing the inverter to reset automatically in the case of DC overvoltage.20 PV2. The inverter has demonstrated the successful implementation of the power tracking state. In order to facilitate testing. When the output power drops below 2% of the full rated power of the inverter. and successfully detected and responded to these conditions. each fault was cleared and the state machine transitioned to the standby state.

This fault caused the inverter to go into the shutdown state. This fault was then re-assigned as a non-latching fault. Latching faults can only be cleared with a manual reset or removal and reapplication of AC power. Manual interaction is required. 51 .LATCHING FAULTS DC bus overvoltage is a latching fault. because a DC overvoltage fault may be indicative a catastrophic hardware failure. to facilitate testing.

5 KW 10.92 2.97 0.1 Second Dalay Signal Injection 0.8 91.21 PV 2.4 52 – 86 Note 1 90. 240 VDC 75°C.1 Second Delay Verify Phase-angle Sequencing 68 VDC.4 Amps >= 0.5A TEST DATA BRIDGE ID: 1 Test Nominal Power Rating Maximum Line Current Power Factor Test Conditions 68 VDC 68 VDC 100% Load 75% Load 50% Load 25% Load 100% Load 240 VAC Prediction 2.51 10.85 CONTROLLER ID: 3 Measured 2.99 68 VDC >= 0.3.6 0.2 91.6 52 .7 92. Nominal Raise DC Bus 100VDC Nominal Manual Adjustment >10. The data sheets address each of the requirements and predictions stated in the performance specifications.11.5 Hz 100% Load 100% Load Standby Overload Minimum limited by 55-85 VDC Line Voltage >= 90% >= 90% 92% 68 VDC Peak >= 90% >= 90% <= 20W 61 68 VAC 5 Minutes < 50 Watts 5 Minutes 2 Second Delay Vary Line Voltage 2 Second Delay 0.99 0.99 0.5 2 62 5 Note 2 √ 5 Note 3 Note 3 Note 3 Note 3 Current Distortion Power Tracking Range DC Bus Minimum Voltage Limit Conversion Efficiency Standby Losses Wake-up Voltage Wake-up Delay Sleep Threshold Sleep Shutdown Delay Under-Voltage Fault Over-Voltage Fault Under-Frequency Fault Over-Frequency Fault Anti-Islanding Protection Over-temperature Fault DC Bus Over-Voltage Fault Line Overcurrent Fault 68 VDC <= 5% 50% Load 100% Load 75% Load 50% Load 25% Load Standby Increasing DC Voltage Decreasing Power < 183VAC > 229VAC < 59.5A Performance Test Data Sheets Test data sheets have been prepared and completed for the inverter.4Arms √ √ 100 10.3 Hz > 60. PV2.

5A TEST DATA Test Test Conditions Standby Wake Up Test Low DC Voltage Raise DC Voltage LIMIT “STANDBY / KWHR” “WAKE UP TEST / KWHR” “POWER TRACKING / WATTS AC / VOLTS DC / KWHR” “SLEEP TEST / WATTS AC / VOLTS DC / KWHR” “STANDBY / KWHR” “OVER TEMPERATURE” Re-Starts “OVERCURRENT” Re-Starts “AC FREQ FAULT” Re-Starts “AC VOLTAGE LOW” Re-Starts “AC VOLTAGE HIGH” Re-Starts Measured √ √ √ Power Tracking Normal Operation Sleep Test / Standby State Controller. Manual Operation Manual Current Adjust Output Current 53 .PV2. Display Reduce DC Voltage √ √ √ √ √ √ √ √ √ √ √ √ √ Over da3ferature Overcurrent AC Frequency Fault AC Voltage Low AC Voltage High Note 2.

1 Amps. The new DC input range is targeted for 48V nominal arrays.SLEEP THRESHOLD The specification states that the sleep test shall be invoked. NOTE 2 .5A Notes to the Data Sheets NOTE 1 .11.11.22 PV2. To optimize conversion efficiency for this design. with a maximum open circuit voltage of 100 VDC. when the output current is less than 0. with a maximum peak open circuit input voltage of 150 VDC. in each inverter.23 PV2.MPPT RANGE The proposed MPPT range for the inverter was 45 to 125 VDC.3. the inverter has been set up for a MPPT range of 45 the 85 VDC. the same level as is used in the PV10208 and PV20208 inverters. 3.5A EFFICIENCY 93 92 EFFICIENCY 91 90 89 88 237 474 768 1007 1237 1475 1722 2027 2266 2324 WATTS AC 54 . This value is too low because reactive current at very low power levels can prevent the inverter from going into the sleep test mode. The sleep test threshold has been set to a power level of 2% of rated full power output.5A Conversion Efficiency Data 94 PV2.

3.11.24 PV2.5A Power Factor and THD Test Data Power Factor: Output current sinusoidal waveform: Output current numerical data demonstrating Total Harmonic Distortion (%THD-R): Output voltage during full power operation: 55 .

A list was complied showing the UL compliance level of every component part and material used in the inverters. which allow developers to verify the 56 .3.13 Create Standard Software Module Catalog The Xantrex philosophy towards software allows for the creation. With these modifications. concepts or relationships to be dealt with simultaneously. Software at Xantrex is constructed such that individual modules are available for use in future products. and the sleep threshold have been modified. Modules are deployed as individual units within the major functional components of the software. the input voltage range. TASK 3. the PV2. A submittal package was prepared for each inverter. Also. This method increases the reliability of software. These tests are known as unit tests.1 Adc Proposed 45-85 VDC 100 VDC POUT < 2% As a result of firmware and hardware optimization. verification and maintenance of a reusable software code base for Xantrex products. These abstracted modules allow themselves to be tested independently of other modules.5A inverter has successfully demonstrated specification conformance.11. A few minor design oversights were discovered in the preliminary evaluations. To accomplish this. TASK 3. and summarized above. Abstraction allows for only a few ideas. PV25A and the PV2. The PV10A.5A Proposed Changes Parameter Max Power Tracking Range Max Open Circuit Voltage Sleep Threshold Specification Prediction 45-125 VDC 150 VDC ILINE < 0. The overall goals of this specification compliance task for the 1-phase inverter have been met. The preliminary UL electrical and mechanical evaluations were completed an all inverters. The exceptions are highlighted in the test data and discussion. all software is designed using abstractions. A report was completed by UL for each inverter product.12 UL Listing Submittal The purpose of this task was to complete the preliminary UL electrical and mechanical evaluations for all three inverter prototypes. improving stability and allowing for increased functionality to be isolated to a minimum amount of modules. All of the test results verifying the predicted "soft" inverter performance parameters were met with a few minor exceptions. The use of an abstract interface allows modules to be changed independently of each other as well as independently from the other software components that rely on them. the maximum power point tracking (MPPT) range. The software falls under the controlled processes at Xantrex and is used across products and platforms as needed to meet the requirements of each Xantrex product. voltage maps of each circuit board were prepared to enable UL to evaluate voltage clearance and creepage requirements. All of the "hard" DSP1 performance specifications required for third party approval have been met.25 PV2.5A inverters were submitted to UL for listing evaluation.

blank lines. variable usage and scope. Updating a reusable abstracted module is a process that can affect many products at the same time. The two tools are also linked so that logged issues can only be updated in a specific code based/version. symbol prefixing and post fixing. and which version the updates will be represented in. file names. The standard describes a common way for software developers to write code for any Xantrex product. This process requires various standards and tools to be used to control and manage the changes. is the mechanism for all developers to “speak the same language”. It also defines a format or style used for code writing. The coding standard in essence. creating meaningful names (by following a defined naming standard). and commenting.13. processes and tools mentioned here are used to create a stable code base at the project and corporate level for software modules. and use of specific keywords. statement placement. The goals for a coding standard are to: • • • Improve readability Improve portability Minimize the probability of coding error 57 . To facilitate easy reading and consistency amongst development of these modules. This standard defines items including. indentation. A coding standard consists of a set of rules that addresses weaknesses in the language standard. coding standards are set in place. Every software development team should have an agreed-upon and formally documented coding standard. An issue-tracking tool is used to log and then prioritize all changes to be implemented. Since the coding standards provide the mechanism for all the software to look and read the same. braces. 3. Software version management means knowing what. why. Once a unit test is written. This method is proven by many in the software community to catch most issues within software modules prior to release. all code reviewers can work together to catch potential issues in a module quickly and consistently. location of certain information). The creation of reusable and manageable software is detailed yet needed and desired at Xantrex. Software source control provides automatic versioning and source code management. spacing. white space. function names. The linkage between the tools helps to assure that developers only update software if an issue from the tracker has been assigned to them. Having coding standards that are common to all software development allows code reviews to occur quickly and efficiently. but not limited to file layout (headers.abstracted module to the given requirements without requiring the overhead of an entire software build. Controlling these changes becomes an important process for management. All of the standards. by whom and when updates are added.1 Coding Standards All reusable software modules adhere to the coding standard at Xantrex. running the module's unit test validates any changes to a module quickly and properly. Creating an abstracted module requires the isolation and layout of ideas and relationships. The coding standards increase reliability along with reusability and reduce maintenance overhead.

2 Coding Reviews The principal goal of inspections is the detection of defects and the examination of design issues. function arguments.g. Defects include (but are not limited to): logical errors. The review team is only expected to have a limited understanding of the code functionality. how infinite loops should be represented. This method allows for easy and fast determinations of the size and type of a value or function as well as where it is defined. 58 . the program's organization is detailed so that standard libraries and reusable modules are created in a standard way. how to comment code.13. Due to the nature of this standard. The code reviews are not limited to a single location and can involve developers any where in the world. the diff command in SourceSafe). and noncompliance with company or program standards.• • • Increase the efficiency of code reviews Enhance the overall quality of the software Reduce development time The most involved part of the coding standard is prefixing of variables and packages. they must: • • • Know and understand the language of the code being reviewed Be familiar with the appropriate coding standards Summarize the code changes by using a comparison tool (e. This allows for fast visual identification of package dependencies. and handling returns from functions. As well. • • • • • • Benefits of conducting a code review: Increase the chance of catching bugs Many different defects may be detected in a single session The quality of the software is improved Knowledge about the code is shared among the team The coding standard is enforced The code inspection team is comprised of at least 3 people (including the author of the code). 3. temporary variable naming. anomalies in the code. The author of the code conducts the code review along with several of his/her peers. Each member of the team must prepare for the review ahead of time. Send these results to the reviewers via e-mail (see Appendix A). the coding standard contains a section on standard practices. and many other practices. This includes file headers and filename extensions. that the first element in enumerations should be explicitly set. These requirements specify the minimum amount of code space left in a target at the end of a project. creation of shadow ports for handling input and output devices. Other parts of this standard include a standard layout for functions. The standard practices are guidelines into preventing common problems in software that have been found through past experiences. For the code reviewers. The team systematically analyzes the code and points out potential defects.

Automated tools reduce the number of items in the log. The changes to be managed lie within and are controlled by Xantrex and pertain to the creation and management of software modules. The author uses the logged results to update the reviewed module(s). The resulting log is used for capturing metrics to improve future development and future reviews. The second is for source control where software modules are maintained in a database and access is controlled and the software protected from misplacement. The results of any automated checking must be brought into the inspection meeting for the team to review. The logged issues are also added to the issue-tracking tool in order to control and manage the changes. The CCB decides what changes are to be made to the system definition during the course of the project. This flow of information pertains to three main functional groups: Engineering. prior to reviews. Issues found by the inspection team are logged and retained for future follow-up. QA and Engineering log defects in modules or products. Change management is obtained by the use of change management software. 3. known potential issues. With the assistance of an industry standard tool. ISSUE TRACKING In order to properly deploy and use an issue tracking system. and more.3 Change Management One meaning of managing change refers to the making of changes in a planned and managed or systematic fashion. monitors. the inspection team should know how the code works and what its purpose is. modules are verified through the tool to determine common problems. improper modifications and more. A final part of the review process that all developers/reviewers perform is known as “lint” checking. issues. automated syntax-checking tools are used. By the end of the review. All defects are reviewed by the CCB and then assigned to a developer as necessary. the software tool is used in conjunction with a flow of information.13. Whenever possible. the programming language and the complexity of the code) The inspection meeting is relatively short (no more than 2 hours). The first tool is used for issue/change management where an issue pertaining to a product or module is logged and assigned to developers for updates as needed. and controls: • The conversion of design objects into system configuration items (project files) 59 . The aim is to more effectively implement new methods and systems in an ongoing organization.• Prepare to spend about 1-2 hours on the review (the length of the review will depend on the experience of the team. All reusable software requires a lint report to be accompanied by the module. Quality Assurance (QA) and the Change Control Board (CCB). Reviews are held regularly to ensure updates are reviewed and to prevent the buildup of code. These tools operate in synchronicity to obtain a third higher-level function for managing and controlling change. Xantrex employs two tools in the area of change management. reduce the workload on the inspection team and speed up the review process. The CCB approves. limit checking.

• Changes to the system The CCB is responsible for approving and assigning change requests that will have a substantial impact to the deliverable (either in terms of time or feature set). This provides an easy. Change requests are classified by type. Using source control allows only a single file to be modified by a single developer at any point in time. This means login is mandatory to reach Xantrex software. a release of software can be labeled and used to denote a specific version. This ensures updates to files/modules occur systematically and are not lost due to the same file being modified by two different developers. Large projects require multiple developers to operate on a single code base. access to the software is limited to only those added to the list of users for the source control database. these changes are reflected to all projects sharing this file. Files and project histories are kept from creation to most recent. As this version is updated and a new release is performed. project-oriented version control environment. the change request moves through a series of controlled steps. automated versioning. the issue is known as a Change Request (CR). Differences between these can be viewed at any point in the life of the files. As well. and the promotion of common files (reusable code) to be used for new products and links to the issue tracking tool’s change records. severity and priority. The source control software retains file and project history. Program Manager/Team Lead. The differences between these two label/versions can now be reviewed as needed. Team members consist of (but are not limited to) CCB member. With these mechanisms in place. SOURCE CONTROL All software modules are under source control and follow change management procedures. For the above process to work. Procedures for working with the source control tool also enforce software be worked on network drives only. Labels can be applied to the histories in order to freeze a point in time and hence have a point to go back to. Security to the software at Xantrex is high and important to protect the company’s intellectual property. its life will follow a Status-Action workflow. Once logged. Added benefits include security. the engineering team develops a clear definition of roles and responsibilities of each participant in the development project. Test Engineer(s). These and other types of details are used to collect metrics on various types of issues enhancing software development for future products. If the module is updated. all developers' software is backed up regularly. revision histories at the file or project level. For example. By requiring proper login to the database of software as well as workstations. Product Managed/Business Champion. a new label can be applied denoting the new version. The workflow of the change request is comprised of a set of control mechanisms and rules that must be adhered. 60 . since the IT group performs daily back-ups of network drives. Source control promotes reusability by providing the mechanism to allow for file/modules to be shared amongst projects. QA manager. Engineer(s). Once a change/issue is logged.

PACKAGE NAME: CALC Description: Contains common mathematical operations that have no or minimal amount of bearing on the intended target these operations may execute on. All hardware specific coding is hidden behind an abstraction. Some provided functionality includes: • Setup • Conversion starting • Channel value retrieval CapDrv Provides service functions for utilization of timer capture facilities. or drivers. These hardware abstractions are organized into modules. Contains all hardware specific drivers. Some provided functionality includes: • Setup • Start and stop • Interrupt handling • Count retrieval 61 . In turn. PACKAGE NAME: HAL Description: Hardware Abstraction Layer. the more reusable software is desired. including filtering and scaling of data representing real world values. This code base will grow as new products are developed. Scaling of data allows for all data to be represented as real world numbers (minimal interpretation needed). that collect all similar processor peripheral functions into a single cohesive unit. The modules listed here are the first to be added to the database and used across multiple product platforms. A list of driver interfaces follows. This package also provides an interface to a CRC16 interface and various data clamping operations. using a reusable module means the reliability of a product is immediately increased. AdcDrv Provides service functions for access to the Analog to Digital Converter (ADC). In practice. and then any hardware driver written to implement this interface may be used.4 Software Module Listing This section describes the active Software Module Listing for Xantrex. Software used in more than one product means the module is tested in more than one place reducing the number of potential issues. the application code relies on the public interface published for the driver. The abstraction is managed by maintaining a layer of software known as the Application Programming Interface (API) that is common to all hardware drivers of a given function. Isolation of hardware details behind an abstract interface allows the hardware to be changed independently of the application code. Modules here are also referred to as packages. This becomes a self-motivating factor when creating new products with reusable modules.13.3. As the software becomes more involved and feature rich to provide high tech and high quality reliable products to users. These operations included data conditioning algorithms.

Some provided functionality includes: • Setup • Read and write a byte • Read and write a page • Erase • Blank determination • Ready determination FlashDrv Provides service functions for reprogramming flash memory. Some provided functionality includes: • Setup • Programming • Erasing IoDrv Provides generic digital I/O service functions.EeDrv Provides service functions for access to EEPROM. Some provided functionality includes: • Pin handling – read and write • Port handling – read and write 62 .

PllDrv Provides service functions for the Phase-Locked Loop (PLL). Some provided functionality includes: • Setup • Transmitter enable and disable • Receiver enable and disable • Send value • Receive value • Interrupt handling SpiDrv Provides service functions for the Serial Peripheral Interface (SPI). Some provided functionality includes: • Setup • Output enable and disable • Interrupt handling • Period update • Duty cycle update • Start and stop SciDrv Provides service functions for the Serial Communications Interface (SCI). Some provided functionality includes: • Setup • Read value • Write value • Interrupt handling • Enable and disable 63 . Some provided functionality includes: • Setup PwmDrv Provides service functions for the Pulse Width Modulator (PWM).

TmrDrv Provides service functions for CPU timers. Some provided functionality includes: Setup • Start and stop • Hold and resume • Period update • Status retrieval • Interrupt handling
PACKAGE NAME: HSMBASE (HIERARCHICAL STATE MACHINE)

Description: This package provides the base class for the state machine engine. Specific application state charts can be created and implemented to use the common HSM base class. A common engineering problem is the specification and design of large and complex reactive systems (i.e. event driven). Many articles have been written on solving this common issue by providing insight to various state chart methodologies. The basis is to eliminate conditional branches (if-else or switch-case) in order to make the code much easier to understand (and test) and to reduce the number of execution paths (improved reliability and maintenance). Developers use the HSMBase by creating a project specific module that implements the desired state operation. The states are represented in a state chart by using UML notation. This project specific module inherits from the HSMBase class to achieve the functionally required to perform the state changes.
PACKAGE NAME: PROTOCOLS

Description: This package contains various communication protocols used for inter-processor and external communication interfaces. The medium on which these protocols operate is abstracted and hence provides a flexible range of implementations. Protocols range in use and features and are diversified to provide a useful choice of options based the products environment and requirements.
PACKAGE NAME: SERVICES

Description: Referring to the HAL abstraction, the Services package provides another level of abstraction above the HAL abstraction in order to further isolate the hardware, allowing changes to be further separated and independent of the application code.

64

The following diagram shows the abstraction use of the services layer:

Application

Services

HAL/Drivers

Services layer placement

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TASK 3.14

Create Standard Serial Communications Description Document

Xantrex Technology, Inc. has developed a serial communications protocol for interconnecting power management products including inverters, chargers, user interface panels, automatic generator starters and DC measurement nodes (battery monitors). The protocol is logically divided into layers per the ISO Open Systems Interconnection (OSI) Model as shown in Figure 10. All the layers are based on open standards to facilitate integration with third-party products. The two lowest layers, namely the physical (PHY) and data link layers (DLL), are based on the Bosch-developed Controller Area Network (CAN) 2.0 that is used extensively in the transportation and heavy equipment markets. CAN has been formalized into the ISO 11898 standard. The middle layers that include the network and transport layers in Xantrex’s implementation are based on the ISO 11783 standard with extensions from the National Marine Electronics Association (NMEA) 2000 protocol standard. In turn, ISO 11783 is based on the SAE J1939 recommendations. The current version of the protocol does not provide session or presentation layers.
Level Transfer Unit Application Protocol Presentation Protocol Session Protocol Transport Protocol

1 2 3 4 5 6 7

Application Layer Presentation Layer Session Layer Transport Layer Network Layer Data Link Layer (DLL) Physical Layer Node 1

Application Layer Presentation Layer Session Layer Transport Layer Network Layer Data Link Layer (DLL) Physical Layer Node 2

APDU PPDU SPDU TPDU Packet Frame Bit

Network Layer Data Link Layer (DLL) Physical Layer

Network Layer Data Link Layer (DLL) Physical Layer Subnet

Node - Subnet Protocols

Subnet Protocols

Node 1 - 2 Message Path

Figure 10: ISO OSI Model

66

Of course. there is no concept of a node address. In this way. CAN was designed originally for automotive control applications where performance and reliability are critical to its acceptance and success. ISO 11898 specifies the requirements for the data link and physical layers of a CAN-based network. small packets also mean that CAN is not designed for high bandwidth applications like streaming audio or video.PHYSICAL AND DATA LINK LAYERS – ISO 11898 CAN The ISO 11898 standard is based on the original Bosch CAN Specification. Peer-to-peer communications means that all the nodes (ECUs/devices) on the network are equal in terms of their ability to access the network. a node listens to its own transmission bit-by-bit and arbitrates with other nodes for access to the network. CAN controllers provide bit filters that allow nodes to “listen” for specific identifier bit patterns at the hardware implementation level. This means that nodes must examine message identifiers in order to determine whether they should really “listen” to a message or not. If the node does not get this acknowledgement then it will retry the message at the next idle period. To provide robustness and reliability. If a node is transmitting a “1” but detects a “0” then it has lost the arbitration and will stop transmitting and wait for the next idle period. In ISO 11783 (NMEA 2000 and SAE J1939). If. Typically. All nodes receive all messages. Using priority-based arbitration. even the sender. A logic “1” bit is recessive (low priority) while a logic “0” bit is dominant (high priority). one node cannot direct a message to another specific node. it waits for the network to be idle and then begins its transmission. the transmitting node is sure that its transmission was successfully sent on the network. Therefore. Twenty-nine (29) identifier bits make up of a portion of every CAN packet. these bits are re-interpreted as the parameter group number (PGN). CAN’s limited packet size means that node’s cannot “hog” the bus and degrade overall network performance. There is no polling or token passing. In the CAN protocol. The CAN protocol supports automatic retry and acknowledgement. the CAN protocol supports multiple methods of error detection including 67 . after detecting that the network is idle. two nodes begin transmitting simultaneously then the node transmitting the packet with the lower priority will cease transmitting and the node with the higher priority packet will continue. After a node has transmitted all the bits in a message. The levels of the identifier bits determine the priority. ISO 11898 provides for ▪ ▪ ▪ ▪ ▪ ▪ Peer-to-peer communications Limited packet size (8 data bytes) Priority-based arbitration No node addressing Automatic retry and acknowledgement Robustness and reliability through multiple methods of error detection and fault confinement. when a node wishes to transmit. it immediately waits for an acknowledgement from at least one other node.

68 Description . Set to zero. etc. security. which essentially enhances the ISO11898 data link layer and adds a network management component in order to support node addresses and multi-packet transfers. These issues are resolved by the ISO 11783 Standard. If the error counts become too high then the node isolates (confines) itself from the network so that it will not adversely affect the other nodes. Examples of functions for the security device class would be siren. The NAME is divided into 10 fields as shown in Table 14. The node addresses range from 0 to 253 allowing for 254 nodes on a given network. In the ISO 11783 specification. The network management portion of ISO 11783 specifies the way nodes determine their addresses. Industry Group Defined and assigned by ISO 3 Device Class Instance Indicates occurrence of a particular device class. The specifications for fault confinement provides that all nodes will maintain a count of transmit and receive errors. off-the-shelf operating systems that include CAN drivers and excellent CAN diagnostic tools. however. 1 Function Defined and assigned by ISO. is the availability of implementation resources including microcontrollers (MCUs) and digital signal processors (DSPs) with builtin CAN controllers. which allows a node to direct its message to all other nodes and a null address (254). Table 14: NAME Fields Field Name Size in Bits Self-Configurable If “1” then the node uses self-configurable addressing. Depends 4 on industry. Reserved Reserved for future use by ISO. In addition to error detection. etc. Device Class Defined and assigned by ISO. May depend on device 8 class. ISO 11898 (CAN) specifies a low-level protocol that does not provide for node addressing and does not support messages longer than eight (8) bytes. power management. There is also a broadcast address (255). which allows a node to self-configure its own address using the network management component of 11783. engine control. control panel.▪ ▪ ▪ ▪ Bit level checking Cyclical redundancy check (CRC) Bit stuffing and Frame (message) format checking. The specification states that each node shall have a unique 64-bit NAME that is stored in a non-volatile location. 1 Address otherwise command or non-configurable. Perhaps the most enticing reason to use CAN. communications. the CAN protocol specifies that nodes will support fault confinement. motion sensor. NETWORK AND TRANSPORT LAYERS – ISO 11783 & NMEA 2000 As mentioned in the previous section. Examples of device classes 7 would be navigation. the data link layer provides the ability to address messages to a particular node or all nodes (broadcast).

If it claims a different address than node 1. a selfconfigurable node acquires its operating address based on the priority of its NAME and the NAMEs of other nodes on the network. command-configurable or self-configurable address. (Both NMEA 2000 and the SAE J1939 committees perform similar assignments for their respective market areas. When node 2 is powered up. it will succeed after waiting 250 milliseconds. Assigned by ISO. as shown in the figure. Allows multiple nodes to be associated with a given 3 function. there may be multiple motion sensors in a security system. The node-addressing scheme specified by ISO 11783 is straightforward. it will attempt to claim an address. it will attempt to acquire an address by transmitting an address claimed message. 5 For example. A non-configurable address means that the node’s address is set at the factory and may not be changed. Description Most of the field values are defined and/or assigned by the ISO 11783 committee.) As implied by the first field in the NAME. Finally. As no other nodes are on the network. Consider the case of two self-configuring nodes attached to the same network as represented in Figure 11.Field Name Function Instance Node Instance Manufacturer Code Identity Number Size in Bits Indicates a specific occurrence of a particular function. If node 2 attempts to claim the same address as node 1 then node 1 will compare its NAME with that of node 2. a node may be classified as having a nonconfigurable. then node 1 will simply re-send its original claim so that node 2 is aware of node 1. If node 1’s NAME is a lower priority then node 1 will it have to send a new address claimed message with a different address from node 2 as shown in Figure 13. 11 Assigned by the node manufacturer to prevent two nodes 21 on a given network from having the same NAME. 69 . If node 1’s name is a higher priority than node 2 then node 1 will re-send its address claimed message forcing node 2 to claim a different address as shown in Figure 12. When power is applied to the first node. A command-configurable node’s address has a default value that may be changed (commanded) by another node (perhaps a diagnostic unit) using a specific message.

Node 1 updates its node list to include node 2. NAME2 Node 2 responds to its own request. Address Claimed SA=y. DA=FF. NAME1 Request Addr Claimed SA=x. Node 1 attempts to claim its address. On Bus Request Addr Claimed SA=x. Address Claimed SA=x. DA=FF Address Claimed SA=x. NAME2 Node 2 attempts to claim its address. node 2 has successfully claimed address y. node 1 has successfully claimed address x. Node 2 requests the address claims of all other nodes. NAME2 On On Bus Initialized Node 2 powers up and performs internal initialization. After waiting 250 ms. a diffrent address from node 1. DA=FF. Node 1 requests the address claims of all other nodes. Address Claimed SA=y. DA=FF Node 1 responds with its address claim. On Initialized Address Claimed SA=x.Node 1 Node 2 Off Off Node 1 powers up and performs internal initialization. Figure 11: Address Claiming—Different Addresses 70 . Node 1 responds to its own request. DA=FF. DA=FF. NAME1 After waiting 250 ms. DA=FF.

NAME1 Node 1 attempts to claim its address. DA=FF. NAME2 On Bus Request Addr Claimed SA=x. DA=FF. On Initialized Address Claimed SA=x. DA=FF. node 1 has successfully claimed address x. DA=FF. node 2 has successfully claimed address y. DA=FF. Node 1 re-claims the same address to let node 2 know that it has priority. Node 1 updates its node list to include node 2. After waiting 250 ms.Node 1 Node 2 Off Off Node 1 powers up and performs internal initialization. NAME1 Node 2 updates its node list to include node 1. DA=FF Address Claimed SA=x. Node 2 attempts to claim a different address. Node 1 responds to its own request. After waiting 250 ms. Node 1 compares its NAME with that of node 2 and realizes that node 2 does not have priority. NAME1 Figure 12: Address Claiming—Same Addresses. NAME2 Node 2 attempts to claim its address. Node 2 requests the address claims of all other nodes. Address Claimed SA=x. Node 2 responds to its own request. On On Bus Initialized Node 2 powers up and performs internal initialization. Request Addr Claimed SA=x. DA=FF. Address Claimed SA=x. the same address as node 1. NAME2 Node 1 responds to Node 2's request. DA=FF Address Claimed SA=y. High Priority Node Claims First 71 . NAME1 Address Claimed SA=x. DA=FF. Address Claimed SA=y. Node 1 requests the address claims of all other nodes.

the same address as node 1. Request Addr Claimed SA=x. No Address After waiting 250 ms. DA=FF. Node 1 attempts to claim a different address. Node 1 responds to its own request. Address Claimed SA=y. NAME2 On Bus Request Addr Claimed SA=x. Node 2 responds to its own request. DA=FF. NAME1 Address Claimed SA=x. DA=FF. DA=FF. Low Priority Node Claims First 72 . NAME2 Node 2 attempts to claim its address. DA=FF. Node 1 requests the address claims of all other nodes. node 1 has successfully claimed address x. DA=FF Address Claimed SA=x. Node 1 updates its node list to include node 2. DA=FF After waiting 250 ms. After waiting 250 ms. Figure 13: Address Claiming—Same Addresses. Node 1 attempts to claim its address. NAME1 Address Claimed SA=x. On Initialized Address Claimed SA=x. Node 2 requests the address claims of all other nodes. Node 2 updates its node list to include node 1.Node 1 Node 2 Off Off Node 1 powers up and performs internal initialization. Address Claimed SA=y. Node 1 compares its NAME with that of node 2 and realizes that node 2 has priority. DA=FF. Node 1 requests the address claims of all other nodes. NAME1 On Bus Request Addr Claimed SA=x. node 2 has successfully claimed address y. NAME1 On On Bus Initialized Node 2 powers up and performs internal initialization. DA=FF Address Claimed SA=y. NAME2 Node 2 responds to Node 1's request. DA=FF. node 1 has successfully claimed address x. Node 1 responds to its own request.

This situation is easy to avoid either through careful planning and address assignment by function or by insisting that all nodes use self-configurable addressing. All nodes regardless of their addressing type (non. Once again. The only other addition to the software is some simple logic (algorithm) that handles the address claimed messages and updates the node list. In a practical system. In addition to network management. A node requires seven (7) bytes of memory for every other node on the network in order to maintain a node list (NAME and address). If a selfconfigurable node has a higher priority than a non or command-configurable node then it will claim its address and the lower priority node will send a cannot claim address message indicating that it cannot participate on the network. is added to the network it will claim its address and the lower priority nodes will have to re-claim different addresses.During the claiming process. 73 . both of the nodes maintain a node list. the number of nodes will be less than fifty and that amounts to a maximum of 350 bytes for the node list. This enhancement to the CAN data link layer allows a node to send a message with a maximum size of 1785 bytes. Figure 14 shows an example of a multi-packet exchange between two nodes. The nodes already have to send and receive messages so sending/receiving an address claimed message adds nothing to the performance requirements. this is a straightforward algorithm that is not difficult to implement and will not adversely affect a node’s performance on the network. the ISO 11783 data link layer also provides specific messages and methods for sending and receiving multi-packet messages. with a NAME that is of a higher priority than one or more of the existing nodes. If a new node. Each node requires seven (7) bytes of non-volatile storage for its NAME and address. which indicates the address and NAME of all the nodes on the network. The actual software implementation of self-configurable addressing is trivial and adds minimal overhead to a node’s processing and memory requirements. command or self-configurable) send an address claimed message so that all of them may maintain their node lists.

Node 2 accepts packets and allows transfer of last packet. PGN Data (3 bytes) End of Message ACK SA=y. nBytes=24 nPkts=4. nxtPkt=4. PGN Data Transfer SA=x. pktSeq=4. PGN Node 2 accepts request to transfer allowing one packet. nPkts=1. Node 1 transmits last packet. PGN Data (7 bytes) Clear to Send SA=y. PGN Clear to Send SA=y. DA=x. DA=x. Ctrl=17. DA=x. DA=y. nPkts=4. nPkts=2. Node 2 accepts packet and acknowledges that the transfer is complete. PGN Data Transfer SA=x. nxtPkt=1. DA=y. nBytes=24. Node 2 SA=y On Bus Request to Send SA=x. nxtPkt=2. PGN Data (7 bytes) Clear to Send SA=y. Node 2 accepts packet and allows transfer of 2 more packets. Node 1 transmits next two packets. DA=y. nPkts=1. PGN Data Transfer SA=x. pktSeq=2. DA=y. Ctrl=19. Ctrl=17. DA=x. Figure 14: Multi-Packet Transfer 74 . pktSeq=3. PGN Data (7 bytes) Data Transfer SA=x. Ctrl=16.Node 1 SA=x On Bus Node 1 requests to initiate a multipacket transfer of 24 bytes (4 packets) of data corresponding to PGN. Ctrl=17. pktSeq=1. Node 1 transmits first packet. DA=y.

The maximum fastpacket message size is limited to a maximum of 223 bytes. the NMEA Standard provides specifications for ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Network powered devices Network power supplies Galvanic isolation of devices Cable options IEC 60945 compliance sections 8 (environment). In addition to the specifications in the ISO Standards. The NMEA specification implies the use of DeviceNet cabling. For larger draws. 9 and 10 (EMC) Connector options Fast-packet messaging Self-configurable addressing A 200 meter network backbone at 250 kbps -40 to 85 degrees Celsius operating temperature range A certification process. Xantrex has added modular RJ45 connectors to the list of potential connector options. CAN transceiver) must be powered by the network and that the circuit be optically isolated from the rest of the node’s circuitry. This reduces the number of wire routing. provides power to connected nodes. via network power supplies or designated nodes. In conjunction with the CAT 5 cable above.e. NMEA’s fast-packet transfer method does not incur that overhead and so allows large messages to be sent more quickly. The DeviceNet connectors are reliable. installation and reliability issues. Galvanic isolation reduces grounding issues by requiring that every node’s network interface circuit (i. the node must have its own power source. 75 .. network powered devices. The NMEA specification also provides for a couple of connector options including DeviceNet™ and terminal strips/blocks. The first point. The NMEA specification allows a single node to draw a maximum of 1Ampere. NMEA requires that all network cables be shielded in order to comply with IEC 60945 sections 9 and 10 on electromagnetic compatibility (EMC) standards. robust and useful where nodes may be regularly detached or serviced. Terminal blocks/strips are useful in low maintenance applications. These connector specifications both provide the ability to remove a node without disrupting the other nodes on the network. Xantrex has added category 5 (CAT 5) cable to the list of wiring possibilities. For unshielded. the NMEA 2000 Standard may be considered a superset of the ISO 11783 Standard. means that the network itself. cost-sensitive applications.” The thick cable is typically used as a network backbone while the thin cable is used for drops to the nodes. Fast-packet messaging is a NMEA addition to ISO 11783’s support for multi-packet transfers.As mentioned in the introduction. ISO multi-packet transfers incur some overhead (additional messages) in order to provide long message transfer services. There are two varieties of cable: “thick” and “thin.

Configuration parameters for an inverter might include ▪ Warning and fault set points for input voltage. PV array. etc. the NMEA 2000 Standards specify a product certification process. at the application level. automatic generator starters and user interfaces (panels). NMEA also provides a certification tool and services. battery. may be commanded to disconnect from the grid.) ▪ Load sensing Status messages are broadcast periodically so that other devices on the network may “listenin” and possibly take advantage of the information.e. APPLICATION LAYER The application layer defines the contents and semantics of the messages that are exchanged by the power management devices.Unlike the SAE J1939 Recommendations. Command messages are sent by a user interface device to other devices in order to change their behavior. for example. In order to verify. if an inverter indicates a fault. Statistics messages are normally requested for diagnostic purposes. chargers. Configuration messages are typically requested/transmitted by a user interface device from/to a configurable device such as an inverter or charger.. A grid-connected inverter. This information may be useful in diagnosing the power system. for example. fuel cell. current and/or frequency ▪ Warning and fault set points for temperature ▪ Grid-connect mode ▪ DC source type (i. a backup inverter may detect it and may be able to take over. may keep track of the number of input under voltage conditions that have occurred. An inverter. SAE’s lack of certification has led to a variety of incompatible SAE J1939 implementations. the protocol supports a single acknowledgement message that is able to indicate either positive or negative acknowledgement. For example. The messages are organized into several categories including ▪ Configuration ▪ Status ▪ Statistics ▪ Command ▪ Request and ▪ Acknowledgement. that a command or configuration message has been received. The protocol currently supports a single request message that allows a user interface device to request any configuration. status or statistics message from any other device. which currently include inverters. 76 .

With the advent of DSP technologies for power electronics applications. analog feedback and status sensors are fed directly into the DSP and multiple PWM outputs directly provide the drive logic for the inverter power switches. MODULAR PRODUCT ARCHITECTURES As part of this contract. All of the functions necessary to implement real-time sinewave regulation are included within these embedded controllers. Sandia National Laboratories has determined that this contract development was completed on a best effort basis and according to good engineering practice.TASK 3. The control board reference designators and product groups are: 77 . Three-Phase Inverter Prototype The purpose of this task was to test the 20-kW three-phase inverter prototype at Sandia National Laboratories to demonstrate the machines conformance to specifications. The key enabling technology involves the application of new Digital Signal Processor (DSP) controllers. An abbreviated performance specification was used as the test plan. To this end. The approach was to design a relatively large number of products based on a relatively small number of functional modules to achieve high manufacturing efficiencies and to enhance product reliability. Pulse Width Modulated (PWM) regulation tasks. 4 SUMMARY This focus of this development was the cost reduction and performance enhancement of utility interactive inverters for photovoltaic applications.16 SNL Testing.. DSP devices can perform repetitive math operations much faster than traditional microcontrollers. Most existing inverter control designs use a microcontroller in conjunction with parts-heavy analog circuitry to perform the high-frequency. This NREL development work is largely based on the development of this DSP technology for use with inverters for renewable and distributed energy applications. The unit shall be returned to Xantrex. was used as the test plan. These DSP controllers are highly integrated and task-specific. TASK 3. DIGITAL SIGNAL PROCESSING DSP controllers have been recently developed for motor control markets and applications. Single-Phase Inverter Prototype The purpose of this task was to test the 2kW single-phase inverter prototype at Sandia National Laboratories to demonstrate the machines intended performance. three prototypes have been developed. three-phase 10kW and 25kW inverters and a 2. The requirements for motor control and inverter topologies are very similar. three DSP based control boards were developed for three different product groups.5kW singlephase inverter.15 SNL Testing. The specific emphasis is on new products designed for high-volume manufacture. An abbreviated performance specification. written by Xantrex. Sandia National Laboratories has determined that this contract development was completed on a best effort basis and according to good engineering practice.

the number of mechanical fasteners used was reduced from 64 to 34. Using this approach and inverter electrical architectures and mechanical packaging designs targeted for high-volume manufacture.5kW single-phase inverter will be the first product to use the DSP1 control board. 78 . modular subassemblies designed with a limited number of component parts are interconnected with the fewest number of hand-wired connections. Standardizing on component parts can reduce the costs of purchasing. These are only two of many significant indicators that illustrate the improvements in product manufacturability. variable speed cooling fan drive and IGBT drive circuits can be used within these product groups and others. and manufacturing. By so doing. The DSP2 control board is currently being used in the development of new Xantrex mobile inverter products. REDUCTION IN ASSEMBLY LABOR The three Xantrex inverter products were designed for high volume manufacture. The control power supplies. This approach was successfully used in the development of the NREL inverters. Also. an 80% reduction in assembly costs was achieved. As products become more sophisticated. Modularity on a lower tier was also achieved by designing for the fewest number of different component parts to be used on a relatively large number of products. The 10kW and 25kW three-phase inverters will be the first two products to use the DSP3 control board. Other non-control related functional blocks are incorporated in the design of the three “NREL” inverters. the number of hand-wired connections was reduced from 115 to 27. stocking. in the 10kW inverter. non-recurring engineering charges associated with the product firmware development are substantially reduced as well as the time-to-market for new products. Testable. kiting. More importantly. The 2. the firmware being developed for all three controllers is based on functional software modules or blocks of code that are task specific and can be imported from one application to another. One of the NREL contract requirements is to generate a catalogue of “reusable” functional software modules. By way of example. Development of these mobile products is beyond the scope of this contract but the use of the DSP2 control board serves to illustrate the commercialization potential of this modular design approach.• • • DSP3 Three-Phase Grid-Tie Inverters 5kW to 100kW DSP1 Single-Phase Grid-Tie Inverters 1kW to 5kW DSP2 Hybrid System Inverter/Chargers 1kW to 20kW All control boards use the same DSP controller. more than half of the engineering development time can be spent on firmware development.

the overall number of electrical component parts has been reduced and the number of wired connections has been reduced. The three-phase 25kW inverter exhibits almost identical improvements. 79 .PRODUCT RELIABILITY ENHANCEMENTS Although product reliability was not a key contract goal and no operational field history for the new inverters is available. The cost of the 10kW inverter was reduced by 56% and the cost of the 25kW inverter was reduced by 53%.5kW. RESULTS The following tables illustrate the success of this development work. The 2. The 2. The comparison is made between the existing Xantrex Model PV10208 product and the 10kW inverter developed under this contract. adds significant value in renewable energy applications. Tables 15 and 16 give a summary of the improvements and cost reductions for the three-phase inverters. The size and weight reductions also add value by providing less cumbersome product solutions for system designers.5kW inverter has no basis for comparison but should benefit equally form this design approach. Table 17 gives a summary cost reduction for the single-phase inverter. the new inverter product architectures should support higher product reliabilities. single-phase product is more difficult to compare because the existing Xantrex product has a different electrical topology and feature set but the benefits of this design approach are equally supported. as reflected in the 50% conversion loss reduction. CONCLUSIONS The contract goals were to achieve and overall cost reduction of 10% to 20% for the three inverters and with no compromise in performance. Internal component operating temperatures have been reduced considerably. Not only were the contract cost reduction goals exceeded by a wide margin but the performance and reliability of the products were also enhanced. The conversion efficiency improvement.

7 % -39.6 % -55.8 % -07.7 % Material Cost Breakdown -34.8 % -34.0 % -56.6 % -25.8 % -80.8 % -39.6 % -46.9 % -45.0 % -58.8 % Table 15.Cost Summary Total Unit Cost Materials Labor Total Materials Bridge Heat Removal Enclosure Magnetics Control Hardware Shipping Materials Physical Summary Volume Weight Performance Summary Conversion Losses -49.0 % -57. Summary Comparison PV10208 and PV10A 80 .

Summary PV2. Summary Comparison PV20208 and PV25A Material Cost Breakdown Total Unit Material Cost Magnetics Power Bridge Heat Removal Enclosure -29 % -18 % -31 % +31 % -25 % Table 17.3 % -52.9 % -41.2 % Table 16.5A Cost Savings 81 .8 % -69.6 % -17.0 % Material Cost Breakdown -31.1 % -38.9 % -52.5 % -35.5 % -31.6 % -84.7 % -67.Cost Summary Total Unit Cost Materials Labor Total Materials Bridge Heat Removal Enclosure Magnetics Control Hardware Shipping Materials Physical Summary Volume Weight Performance Summary Conversion Losses -48.6 % -51.6 % -54.

The existing Xantrex PV10208 Right .The PV10A developed under this contract 82 .Photograph of illustrating 10kW three-phase grid-interactive inverter improvements Left .

The existing Xantrex PV20208 (20kW) Right .The PV25A (25kW) developed under this contract Inverters are shown with front doors removed 83 .Photograph of illustrating higher power phase grid-interactive inverter improvements Left .

Photograph of 2500W single-phase grid-interactive inverter Inverter shown with front cover removed 84 .

weight and conversion losses. FUNDING NUMBERS PV Inverter Products Manufacturing and Design Improvements for Cost Reduction and Performance Enhancements: Final Subcontract Report. inverter. November 2003 6. SUBJECT TERMS: PV. LIMITATION OF ABSTRACT 14. searching existing data sources. and completing and reviewing the collection of information. PRICE CODE 20. were to: 1) Capture the newest digital signal processor (DSP) technology to create high-impact.5-kW inverter has no basis for comparison. to Washington Headquarters Services. Reduce inverter size. SECURITY CLASSIFICATION OF ABSTRACT 17. DISTRIBUTION CODE National Technical Information Service U. Send comments regarding this burden estimate or any other aspect of this collection of information. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 8. 1. West 7. PERFORMING ORGANIZATION REPORT NUMBER National Renewable Energy Laboratory 1617 Cole Blvd. Department of Commerce 5285 Port Royal Road Springfield. REPORT TYPE AND DATES COVERED April 2004 4. including the time for reviewing instructions. 15. 2) Create a common resource base for three PV product lines. and the higher efficiency of producing more products with fewer design. Mooney 12a. DC 20503. SECURITY CLASSIFICATION OF REPORT Unclassified NSN 7540-01-280-5500 Unclassified Unclassified UL Standard Form 298 (Rev. AGENCY USE ONLY (Leave blank) 2. thin film. and production test variations.S. CO 80401-3393 11. but should benefit equally from this design approach. This standardized approach to both hardware and software control platforms will provide significant market advantage over foreign competition. solar cell. VA 22161 13. but the performance and reliability of the products were also enhanced. 3) Achieve cost reductions through increased volume of common components. Not only were the contract cost reduction goals exceeded by a wide margin.REPORT DOCUMENTATION PAGE Form Approved OMB NO. AUTHOR: PVP46101 NDO-1-30628-02 R. Golden. module. Suite 1204. and the cost of the 25-kW inverter was reduced by 53%. Arlington. SUPPLEMENTARY NOTES 10. The size and weight reductions also add value by providing less cumbersome product solutions for system designers. 4) Increase PV inverter product reliability. DISTRIBUTION/AVAILABILITY STATEMENT 12b. manufacturing. Paperwork Reduction Project (0704-0188). “next generation” power conversion equipment for the PV industry. as reflected in the 50% conversion loss reduction. conversion loss 18. adds significant value in renewable energy applications. 0704-0188 Public reporting burden for this collection of information is estimated to average 1 hour per response. The cost of the 10-kW inverter was reduced by 56%. including suggestions for reducing this burden. California 9. NUMBER OF PAGES 16. SPONSORING/MONITORING AGENCY REPORT NUMBER NREL/SR-520-35885 NREL Technical Monitor: D. digital signal processor (DSP). REPORT DATE 3. San Luis Obispo. The contract goals were to achieve an overall cost reduction of 10% to 20% for the three inverters and with no compromise in performance. Washington. The 2. Directorate for Information Operations and Reports. manufacturing. VA 22202-4302. ABSTRACT (Maximum 200 words): The specific objectives of this subcontracted development work by Xantrex Technology Inc. TITLE AND SUBTITLE Final Subcontract Report November 2003 5. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Xantrex Technology Inc. and to the Office of Management and Budget. Z39-18 298-102 . The conversion efficiency improvement. next generation. 1215 Jefferson Davis Highway. SECURITY CLASSIFICATION OF THIS PAGE 19. gathering and maintaining the data needed. 2-89) Prescribed by ANSI Std. reduced assembly labor.

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