This project is mainly used to find and rectify the faults of three phase induction motor using PIC (peripheral interface controller) Microcontroller. Here we are taken seven types of faults, and they are 1. OVER VOLTAGE 2. UNDER VOLTAGE 3. UNBALANCED VOLTAGE 4. SINGLE PHASING 5. BLOCKED ROTOR 6. OVER LOAD 7. NO FAULT( Initial Condition) Faults other than blocked rotor can be rectified automatically by using PIC, i.e., over voltage, under voltage, unbalanced voltage, single phasing, over load and initial condition can be rectified automatically by using PIC,i.e., PIC giving signal to the relay driver unit, if there is any fault relay will cut off the supply from the induction motor, but there is no any possibility in case of blocked rotor faults, if the blocked rotor fault occurs PIC showing there is a blocked rotor faults in induction motor, then alarm will be on then we can rectify the faults manually.

Now many techniques are used to find and rectify the faults, here we are using PIC technique this method is very faster and precise than the other techniques and also it is easy to implemented. The program of PIC is written by using fuzzy logic.

1. It is real world thinking program. 2. It is easy to implement. 3. It is taking minimum number of codes. 4. It is easy to understand.

 Combination Of Hardware and Software Hardware  To establish a Physical Connection between two parts Software  Issue when and where commands to control the Hardware.  Uses Microprocessor or Microcontroller Application  Developing products to do one task only


3 Single Phase Supply

Potentia l Transfor mer

Rectifie r



Control Unit


Current Transfor mer

I/V Conver ter

Rectifie r& Filter



• • • Control unit consist of relay unit(6v electromagnetic relay). According to the voltage & current value,the relay will operate. If ‘v’&‘I’ is less than the specified value,then the relay will be idle.

If ‘v’&‘I’ is more than the specified value,then the relay will operate and cut- off the three phase induction motor from the supply.

• • • • Voltage is measured by using POTENTIAL TRANSFORMER. This voltage is stepped-down according to the PIC specification. Current is measured by using CURRENT TRANSFORMER. This current is converted according to the PIC specification.

With the advent of low-cost personal computers and various easily accessible software packages, computer- aided teaching tools have come essential an part of both classroom lectures and laboratory experiments in electrical

machinery education the computer models and simulations of induction motors, as teaching tools, support the classroom teaching by enabling the instructor, through the computer-generated graphics, to illustrate easily steady-state operation of the motor under

various loading conditions.The computational tools as a part of laboratory experiments enhance laboratory experience by providing students with the opportunity to verify the results of laboratory experiments and compare them with those obtained by computer simulations. Such a comparison opportunity helps students realize the limitations of hardware experiments and, as a counterpoint, appreciate that computer models cannot substitute for actual hardware experiments that might not exactly represent the operation of induction motors because of some modeling assumptions. Moreover, an undergraduate electric machinery course that integrates up-to-date computer hardware and software tools in both lecture and laboratory sections also meets the expectations of today’s students who want to use computers and simulation tools in every aspects of a course, and thus, possibly attracts MORE STUDENT Electrical machinery courses at the undergraduate level typically consist of classroom and laboratory sections. The classroom section covers the steady-state operation of the induction motor in which the per-phase equivalent circuit is used to compute various motor quantities, such as input current and power, power factor, developed torque, and efficiency. The computations associated with the steady-state operation require the knowledge of equivalent circuit parameters. These parameters are obtained by performing three tests, namely dc, no-load, and blocked-rotor tests on the motor in a typical laboratory experiment.

The laboratory section includes these tests and a load experiment that allows students to become familiar with the induction motor operation and to gain invaluable hardware and measurement experiences. The authors’ experience while teaching induction motors at Drexel University, Philadelphia, PA, indicates that students generally have difficulty when they come to the laboratory to carry out these experiments even though the corresponding theory is extensively covered in the classroom section with a detailed hand-out describing laboratory facilities and the procedure of the experiments, given to them at least a week before the laboratory.

Students are not familiar with a laboratory. Environment that contains large machines and relatively complex measurement methods and devices as compared with other laboratories they have been to before. The time constraints during the laboratory exercise are also a difficult adjustment. Ina usual two-hour laboratory section, students are required to setup and perform four induction motor experiments, to take the necessary measurements, and to investigate steady-state performance of the motor under various loading conditions. Because of the time limitations, students often rush through the experiments in order to finish them on time, which unfortunately prevents them from getting a true feeling of motor operation and from appreciating what has been accomplished during the laboratory practice. Therefore, simulation tools must be developed for induction motor experiments to serve as useful preparatory exercises before students come to the laboratory. The objective of this paper is to present simulation models of these induction motor experiments in an effort to design a computational laboratory The dc, no-load, and blocked-rotor simulation models are developed as stand-alone applications using MATLAB/Simulink[8] and Power System Blocked. For the load experiment, students are required to write a computer program using MAT Lab’s M-file programming for the perphase equivalent circuit of the induction motor to compute operating quantities.

The steady-state operating characteristics of a three-phase induction motor are often investigated using a per-phase equivalent circuit as shown in Fig. In this circuit, and represent stator resistance and leakage reactance, respectively;and denote the rotor resistance and leakage reactance referred to the stator, respectively;

resistance stands for core losses; represents magnetizing reactance; and denotes the slip. The equivalent circuit is used to facilitate the computation of various operating quantities, such as stator current, input power, losses, induced torque, and efficiency. When power aspects of the operation need to be emphasized, the shunt resistance is usually neglected; the core losses can be included in efficiency calculations along with the friction, windage, and stray losses. The parameters of the equivalent circuit can be obtained from the dc, noload, and blocked-rotor tests. In the following, both experimental setup and Simulink/PSB models of each test are described. The PSB is a useful software package to develop simulation models for power system applications in the MATLAB/Simulink environment. With its graphical user interface and extensive library, it provides power engineers and researchers with a modern and interactive design tool to build simulation models rapidly and easily. MATLAB and Simulink/PSB have been widely used by educators to enhance teaching of transient and steady-state characteristics of induction machines. Of course, other commercial software packages, such as Maple and MathCAD, are commonly used in electrical engineering education with their advantages and disadvantages .The reason that MATLAB with its toolboxes was selected is that it is the main software package used in almost all undergraduate courses in the authors’ institutions as a computation tool to reinforce electrical engineering education. Therefore, students can easily access to MATLAB, and they already have the basic programming skills to use the given Simulink models and to write computer programs when required before coming to the machinery class.

No-Load Test
The no-load test on an induction motor is conducted to measure the rotational losses of the motor and to determine some of its equivalent circuit parameters. In this test, a rated, balanced ac voltage at a rated frequency is applied to the stator while it is running at no load, and input power, voltage, and phase currents are measured at the no-load condition. Fig illustrates the experimental setup of the no-load test conducted at Drexel University’s IPSL. Fig shows the Simulink/PSB realization of the no-load test, where a three-phase balanced Y-connected ac source whose per-phase voltage is 120 V/60 Hz is applied to the stator terminal of the induction motor. The electrical inputs of the induction motor block are the three electrical connections of the stator (terminals A-B-C), while the electrical outputs (terminals a-b-c) are the three electrical connections of the rotor, which is short-circuited. The input block (terminal Tm) is the mechanical torque at the machine’s shaft. This torque is set to be zero to simulate the no-load condition. The equivalent circuit parameters obtained from experimental data and the number of poles is specified using the induction motor-block dialogue box. Three current measurement blocks are used to measure the instantaneous current of each phase. The output of each current measurement block is connected to a root-mean-square (rms) block, called signal rms, to determine the rms value of each phase current. This

block computes the rms value of the input signal over a running window of the one cycle of the specified fundamental frequency (60 Hz). Three display boxes read these rms values. Similarly, a voltage measurement block, an rms block, and a display box are used to measure the phase A voltage. The outputs of the voltage measurement block and the current measurement block of phase A are connected to a power measurement block, called the active and reactive power measurement, that computes the active power and reactive power. The output of this block is connected to a scope and to a display block to obtain the waveforms and the values of and. The output terminal of the induction motor block (terminal m-SI) allows for the measurement of several variables, such as speed and electrical torque. A machine measurement block is used to get the mechanical speed. Through the scope and display block, the waveform and the steady-state value of the rotor speed can easily be measured in rad per second, or the corresponding data can be written to MATLAB’s workspace to make use of other graphical tools available in MATLAB. Fig shows the evolution of the mechanical speed during the no-load simulation. The rotor speed reaches its steady-state value (188.5 rad/s for the tested motor) quickly, indicating that MATLAB/Simulink is an appropriate tool to investigate steady-state behavior of induction motors as well. One can see that there are some differences between the hardware setup and Simulink/PSB model. For example, the per-phase-based real and reactive input power is measured in the simulation model, while in the experiment the total three-phase real input power is measured. However, this difference is not significant since under the three-phase balanced operation; computations are usually completed using the per-phase quantities. Similarly, the per-phase voltage is measured in the simulation, as opposed to the line-to-line voltages measured in the hardware experiment. These measurements enable the approximate computation of the sum of the magnetizing reactance and the stator leakage reactance as follows.

where is the per-phase voltage , is the phase measured reactive power, and is the average phase current measured . Using measured input power and the stator resistance obtained from the dc test, rotational losses of the motor given by the sum of the friction, windage, and core losses can be found, as follows:

Blocked-Rotor Test
The blocked-rotor test on an induction motor is performed to determine some of its equivalent circuit parameters. In this test, the rotor of the induction motor is blocked, and a reduced voltage is applied to the stator terminals so that the rated current flows through the stator windings. The input power, voltage, and current are measured. For some design-class induction motors, this test is conducted under a test frequency, usually less than the normal operating frequency so as to evaluate the rotor resistance appropriately. The experimental setup of the blocked-rotor test is not shown here since it is similar to that of the no-load test shown in Fig. The only difference is that a synchronous generator coupled with a dc motor and auto transformer were installed in

the circuit in order to perform the blocked-rotor test at various frequencies and to control input voltage to the stator. Fig. shows the Simulink/PSB model of the blocked-rotor test. This model is almost the same as that of the no-load test shown in Fig. However, there is a slight difference between the two models. In the blocked-rotor model, the inertia of the induction motor is set to infinity in order to simulate the blocked-rotor condition. Several measurements blocks are used to measure the current, voltage, and active/reactive powers. The mechanical torque to the rotor is set to an arbitrary nonzero value [in this case, 5 Newton-meter (N.m)], which will not affect the

blocked-rotor condition since the inertia isinfinite. Because of the infinite inertia, rotor speed remains at zero during the blocked-rotor simulation. Various test frequencies for blocked-rotor simulation can be easily achieved by changing the frequencies of the -connected voltage sources rather than using a synchronous generator coupled with a dc motor. The measurement data from the blocked rotor test enables one to determine approximately the blocked-rotor resistance and reactance at the test frequency

where is the blocked-rotor resistance, and is the blocked-rotor reactance at the test frequency.

If the test frequency is different from the rated frequency, one can compute the total equivalent reactance at the normal operating frequency as follows since the reactance is directly proportional to the frequency.

When the three tests are completed, equivalent circuit parameters can easily be computed. 1) The stator resistance is directly computed from the dc test. 2) The no-load test gives the sum of the magnetizing reactance and the stator leakage reactance . 3) The blocked-rotor test gives that of the stator and rotor leakage reactance. One needs to refer to test codes to find out the empirical proportions for stator and leakage reactance given for three-phase induction motors by class.When the classification of the motor is not known, one assumes that. The magnetization reactance can now be evaluated using, as follows:

As for the rotor resistance , a better approximation is required since it has a more significant effect on the motor performance when compared with the other circuit parameters.


the equivalent circuit under blocked-rotor condition, the following expression achieves the desired approximation


To illustrate the effectiveness of the proposed simulation models, one compares the equivalent circuit parameters determined by simulations with those obtained from hardware experiments. The motors used for this purpose are the three-phase 60-Hz Y-connected, and the 5-Horse Power (HP) induction motors of 200-V rating 1735 r/min located at Drexel University’s IPSL. A set of hardware experiments are first performed (i.e., dc, no-load, and blocked-rotor tests) on four induction motors to obtain appropriate equivalent circuit parameters for software simulations. The resulting parameters are presented in Table I.


For each induction motor tested the Simulink/PSB models of the dc, no-load, and blocked-rotor tests were run. The simulation data of no-load and blocked-rotor tests for motor 1 is shown in Table II, where various quantities, such as voltage, current, and power required to compute equivalent circuit parameters, are presented. The dc test simulation data for motor 1 is as follows: 12.66 V and 15.74 A. The simulation data for the other three motors is similar to that of Motor 1 and, thus, is not given here. Table III gives the equivalent circuit parameters computed, using the simulation data and the corresponding errors relative to those obtained experimentally. The error computations assume that equivalent circuit parameters determined experimentally are accurate. The results indicate that relative errors are negligible, and the proposed simulation models accurately predict equivalent circuit parameters. The largest error occurs in the stator and rotor leakage reactances, since one assumes that two reactances have equal contributions to the blocked-rotor reactance, which might not be the real case.










Unbalanced Fault
+ v -


signal rms

Vbn RMS3

+ v -

s ignal


Vcn Scope2 200 230.9 240 Demux
+ v -

+ v -

signal rms

1 2 m 1 2


Van ubnormal


Ideal Switch3
is_abc A B m C Te Tm m wm g Pase A m


Display 0.6725 1.394 1.211 Display1


Ideal Switch4

Van normal

Vbn normal

Asynchronous Machine SI Units
1 g 2 m signal rms

Vcn Normal

Ideal Switch1
1 2 m

signal rms

RMS signal rms RMS1 Scope1 ia

Vcn Ubnormal


RMS2 2 Constant Signal To Workspace ib Signal To Workspace1 ic Signal To Workspace2

Ideal Switch2

Pulse Generator2

Pulse Generator1





+ v -

Van Vbn
signal rms


+ v signal rms

Vcn Scope2

+ v -

signal rms




is_abc Pase A A B m C Te Tm m wm

+ v -

Display Scope 0


AC Voltage Source


AC Voltage Source1

Asynchronous Machine SI Units
1 g 2 m signal rms

Ideal Switch1
1 2 m

signal rms


signal rms



AC Voltage Source3


RMS2 2 Constant ia Signal To Workspace ib

Ideal Switch2

Pulse Generator1

Pulse Generator2

Signal To Workspace1 ic Signal To Workspace2





Microcontroller Core Features
• High-performance RISC CPU. • Only 35 single word instructions to learn. • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM data memory. • Pinout compatible to the PIC16C73B/74B/76/77. • Interrupt capability (up to 14 sources). • Eight level deep hardware stack. • Direct, indirect and relative addressing modes. • Power-on Reset (POR). • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST). • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation. • Programmable code-protection. • Power saving SLEEP mode. • Selectable oscillator options. • Low-power, high-speed CMOS FLASH/EEPROM technology. • Fully static design. • In-Circuit Serial Programming  ICSP)via two pins. ( • Single 5V In-Circuit Serial Programming capability. • In-Circuit Debugging via two pins. • Processor read/write access to program memory. • Wide operating voltage range: 2.0V to 5.5V. • High Sink/Source Current: 25 mA. • Commercial and Industrial temperature ranges. • Low-power consumption. - < 2 mA typical @ 5V, 4 MHz - 20  typical @ 3V, 32 kHz A - < 1 A typical standby current.

Peripheral Features
• Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, Can be incremented during sleep external Crystal/clock. • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler. • Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit • 10-bit multi-channel Analog-to-Digital converter • Synchronous Serial Port (SSP) with SPI(Master Mode) and I2C(Master/Slave) • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection. • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) Brown-out detection circuitry for Brown-out Reset (BOR). via

This document contains device-specific information. Additional information may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data sheet. The PIC16F876/873 devices come in 28-pin packages and the PIC16F877/874 devices come in 40- pin packages. The 28-pin devices do not have a Parallel Slave Port implemented. The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2, respectively.





There are three memory blocks in each of these PICmicro MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. Additional information on device memory may be found in the PIC microMid-Range Reference Manual.

Program Memory Organization
The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory and the PIC16F873/874 devices have 4K x 14. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.



Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers and theSpecial Function Registers. Bits RP1(STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some “high use” Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.



The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.


Legend: x = unknown, u = unchanged, q = value depends on condition, - = nimplemented read as ’0’, r = reserved.Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.


The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. OPTION_REG REGISTER (ADDRESS 81H, 181H)

The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.


The PIE1 register contains the individual enable bits for the peripheral interrupts.

The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt


The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt.

The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watch-dog Reset (WDT) and an external MCLR Reset.


The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 2-5 shows the two uationsor the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0>  CH). The lower example in the figure shows how the P PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).

A computed GOTO is accomplished by adding an offset to the program counter ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, “Implementing a Table Read" (AN556).

The PIC16CXX family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stackwhen a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution.PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).


Program Memory Paging
PIC16CXX devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by CLATH<4:3>.

When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack) Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).

These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: • OSC Selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • SLEEP • Code protection • ID locations • In-Circuit Serial Programming • Low Voltage In-Circuit Serial Programming • In-Circuit Debugger These devices have a watchdog timer, which can be shut off only through configuration bits. It runs off its Own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in

reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation’s these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. For additional information, refer to Application Note, AN007, “Power-up Trouble Shooting”, (DS00007).

Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Power up Timer operates on an internal RC oscillator. The hip is kept in reset as long as the PWRT is active. The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation.

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

Brown-Out Reset (BOR)
The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100µ S), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a reset may not occur. Once the brown-out occurs, the device will remain in brown-out reset until VDD rises above VBOR. The power-up timer then keeps the device in reset for TPWRT (parameter #33, about 72mS). If VDD should fall below VBOR during TPWRT, the brown-out reset process will restart when VDD rises above VBOR with the power-up timer reset. The power-up timer is always enabled when the brown-out reset circuit is enabled regardless of the state of the PWRT configuration bit.

Time-out Sequence
On power-up, the time-out sequence is as follows: The pWRT delay starts (if enabled) when a POR reset occurs. Then OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, and HS). When the OST ends, the device comes out of RESET. If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in parallel. Table 12-5 shows the reset conditions for the STATUS, PCON and PC registers, while Table 12-6 shows the reset conditions for all the registers.

Power Control/Status Register (PCON)
The Power Control/Status Register, PCON, has up to two bits depending upon the device. Bit0 is Brown-out Reset Status bit; BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred. The BOR bit is a "don’t care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Configuration Word). Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.

Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT timeout generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT pre scale (actually a post scalar, but shared with the Timer0 pre scale) may be assigned using the OPTION_REG register.



This is the first in a series of six articles intended to share information and experience in the realm of fuzzy logic (FL) and its application. This article will introduce FL. Through the course of this article series, a simple implementation will be explained in detail. Each article will include additional outside resource references for interested readers.

The concept of Fuzzy Logic (FL) was conceived by Lotfi Zadeh, a professor at the University of California at Berkley, and presented not as a control methodology, but as a way of processing data by allowing partial set membership rather than crisp set membership or non-membership. This approach to set theory was not applied to control systems until the 70's due to insufficient small-computer capability prior to that time. Professor Zadeh reasoned that people do not require precise, numerical information input, and yet they are capable of highly adaptive control. If feedback controllers could be programmed to accept noisy, imprecise input, they would be much more effective and perhaps easier to implement. Unfortunately, U.S. manufacturers have not been so quick to embrace this technology while the Europeans and Japanese have been aggressively building real products around it.

In this context, FL is a problem-solving control system methodology that lends itself to implementation in systems ranging from simple, small, embedded micro-controllers to large, networked, multi-channel PC or workstation-based data acquisition and control systems. It can be implemented in hardware, software, or a combination of both. FL provides a simple way to arrive at a definite conclusion based upon vague, ambiguous, imprecise, noisy, or missing input information. FL's approach to control problems mimics how a person would make decisions, only much faster.

FL incorporates a simple, rule-based IF X AND Y THEN Z approach to a solving control problem rather than attempting to model a system mathematically. The FL model is empirically-based, relying on an operator's experience rather than their technical understanding of the system. For example, rather than dealing with temperature control in terms such as "SP =500F", "T <1000F", or "210C <TEMP <220C", terms like "IF (process is too cool) AND (process is getting colder) THEN (add heat to the process)" or "IF (process is too hot) AND (process is heating rapidly) THEN (cool the process quickly)" are used. These terms are imprecise and yet very descriptive of what must actually happen. Consider what you do in the shower if the temperature is too cold: you will make the water comfortable very quickly with little trouble. FL is capable of mimicking this type of behavior but at very high rate.

FL requires some numerical parameters in order to operate such as what is considered significant error and significant rate-of-change-of-error, but exact values of these numbers are usually not critical unless very responsive performance is required in which case empirical tuning would determine them. For example, a simple temperature control system could use a single temperature feedback sensor whose data is subtracted from the command signal to compute "error" and then time-differentiated to yield the error slope or rate-of-change-of-error, hereafter called "error-dot". Error might have units of degs F and a small error considered to be 2F while a large error is 5F. The "error-dot" might then have units of degs/min with a small error-dot being 5F/min and a large one being 15F/min. These values don't have to be symmetrical and can be "tweaked" once the system is operating in order to optimize performance. Generally, FL is so forgiving that the system will probably work the first time without any tweaking.FL was conceived as a better method for sorting and handling data but has proven to be a excellent choice for many control system applications since it mimics human control

logic. It can be built into anything from small, hand-held products to large computerized process control systems. It uses an imprecise but very descriptive language to deal with input data more like a human operator. It is very robust and forgiving of operator and data input and often works when first implemented with little or no tuning.

FL offers several unique features that make it a particularly good choice for many control problems. 1) It is inherently robust since it does not require precise, noise-free inputs and can be programmed to fail safely if a feedback sensor quits or is destroyed. The output control is a smooth control function despite a wide range of input variations. 2) Since the FL controller processes user-defined rules governing the target control system, it can be modified and tweaked easily to improve or drastically alter system performance. New sensors can easily be incorporated into the system simply by generating appropriate governing rules. 3) FL is not limited to a few feedback inputs and one or two control outputs, nor is it necessary to measure or compute rate-of-change parameters in order for it to be implemented. Any sensor data that provides some indication of a system's actions and reactions is sufficient. This allows the sensors to be inexpensive and imprecise thus keeping the overall system cost and complexity low. 4) Because of the rule-based operation, any reasonable number of inputs can be processed (1-8 or more) and numerous outputs (1-4 or more) generated, although defining the rule base quickly becomes complex if too many inputs and outputs are chosen for a single implementation since rules defining their interrelations must also be defined. It would be better to break the control system into smaller chunks and use several smaller FL controllers distributed on the system, each with more limited responsibilities.

5) FL can control nonlinear systems that would be difficult or impossible to model mathematically. This opens doors for control systems that would normally be deemed unfeasible for automation.

1) Define the control objectives and criteria: What am I trying to control? What do I have to do to control the system? What kind of response do I need? What are the possible (probable) system failure modes? 2) Determine the input and output relationships and choose a minimum number of variables for input to the FL engine (typically error and rate-of-change-of-error). 3) Using the rule-based structure of FL, break the control problem down into a series of IF X AND Y THEN Z rules that define the desired system output response for given system input conditions. The number and complexity of rules depends on the number of input parameters that are to be processed and the number fuzzy variables associated with each parameter. If possible, use at least one variable and its time derivative. Although it is possible to use a single, instantaneous error parameter without knowing its rate of change, this cripples the system's ability to minimize overshoot for a step inputs. 4) Create FL membership functions that define the meaning (values) of Input/Output terms used in the rules. 5) Create the necessary pre- and post-processing FL routines if implementing in S/W, otherwise program the rules into the FL H/W engine. 6) Test the system, evaluate the results, tune the rules and membership functions, and retest until satisfactory results are obtained.

The concept of linguistic or "fuzzy" variables. Think of them as linguistic objects or words, rather than numbers. The sensor input is a noun, e.g.

"temperature", "displacement", "velocity", "flow", "pressure", etc. Since error is just the difference, it can be thought of the same way. The fuzzy variables themselves are adjectives that modify the variable (e.g. "large positive" error, "small positive" error,” zero" error, "small negative" error, and "large negative" error). As a minimum, one could simply have "positive", "zero", and "negative" variables for each of the parameters. Additional ranges such as "very large" and "very small" could also be added to extend the responsiveness to exceptional or very nonlinear conditions, but aren't necessary in a basic system. FL does not require precise inputs, is inherently robust, and can process any reasonable number of inputs but system complexity increases rapidly with more inputs and outputs. Distributed processors would probably be easier to implement. Simple, plain-language IF X AND Y THEN Z rules are used to describe the desired system response in terms of linguistic variables rather than mathematical formulas. The number of these is dependent on the number of inputs, outputs, and the designer's control response goals.

In the last article the concept of linguistic variables was presented. The fuzzy parameters of error (command-feedback) and error-dot (rate-ofchange-of-error) were modified by the adjectives "negative", "zero", and "positive". To picture this, imagine the simplest practical implementation, a 3-by-3 matrix. The columns represent "negative error", "zero error", and "positive error" inputs from left to right. The rows represent "negative", "zero", and "positive" "error-dot" input from top to bottom. This planar construct is called a rule matrix. It has two input conditions, "error" and "error-dot", and one output response conclusion (at the intersection of each row and column). In this case there are nine possible logical products (AND) output response conclusions. Although not absolutely necessary, rule matrices usually have an odd number of rows and columns to accommodate a "zero" center row and column region. This may not be needed as long as the functions on either side of the center overlap somewhat and continuous dithering of the output is acceptable since the "zero"

regions correspond to "no change" output responses the lack of this region will cause the system to continually hunt for "zero". It is also possible to have a different number of rows than columns. This occurs when numerous degrees of inputs are needed. The maximum number of possible rules is simply the product of the number of rows and columns, but definition of all of these rules may not be necessary since some input conditions may never occur in practical operation. The primary objective of this construct is to map out the universe of possible inputs while keeping the system sufficiently under control.

The first step in implementing FL is to decide exactly what is to be controlled and how. For example, suppose we want to design a simple proportional temperature controller with an electric heating element and a variable-speed cooling fan. A positive signal output calls for 0-100 percent heat while a negative signal output calls for 0-100 percent cooling. Control is achieved through proper balance and control of these two active devices.

A simple block diagram of the control system.

It is necessary to establish a meaningful system for representing the linguistic variables in the matrix. For this example, the following will be used: "N" = "negative" error or error-dot input level "Z" = "zero" error or error-dot input level "P" = "positive" error or error-dot input level "H" = "Heat" output response "-" = "No Change" to current output "C" = "Cool" output response Define the minimum number of possible input product combinations and corresponding output response conclusions using these terms. For a three-by-three matrix with heating and cooling output responses, all nine rules will need to be defined. The conclusions to the rules with the linguistic variables associated with the output response for each rule are transferred to the matrix.


Typical control system response shows what command and error look like in a typical control system relative to the command set point as the system hunts for stability. Definitions are also shown for this example.

Linguistic rules describing the control system consist of two parts; an antecedent block (between the IF and THEN) and a consequent block (following THEN). Depending on the system, it may not be necessary to evaluate every possible input combination (for 5-by-5 & up matrices) since some may rarely or never occur. By making this type of evaluation, usually done by an experienced operator, fewer rules can be evaluated, thus simplifying the processing logic and perhaps even improving the FL system performance.

The rule structure. After transferring the conclusions from the nine rules to the matrix there is a noticeable symmetry to the matrix. This suggests (but doesn't guarantee) a reasonably well-behaved (linear) system. This implementation may

prove to be too simplistic for some control problems; however it does illustrate the process. Additional degrees of error and error-dot may be included if the desired system response calls for this. This will increase the rule base size and complexity but may also increase the quality of the control. Figure 4 shows the rule matrix derived from the previous rules.

In the last article, the rule matrix was introduced and used. The next logical question is how to apply the rules. This leads into the next concept, the membership function. The membership function is a graphical representation of the magnitude of participation of each input. It associates a weighting with each of the inputs that are processed, define functional overlap between inputs, and ultimately determines an output response. The rules use the input membership values as weighting factors to determine their influence on the fuzzy output sets of the final output conclusion. Once the functions are inferred, scaled, and combined, they are de fuzzified into a crisp output which drives the system. There are different memberships functions associated with each input and output response. Some features to note are: SHAPE - triangular is common, but bell, trapezoidal, have sine and, exponential have been used. More complex functions are possible but require greater computing overhead to implement.. HEIGHT or magnitude (usually normalized to 1) WIDTH (of the base of function), SHOULDERING (locks height at maximum if an outer function. Shouldered functions evaluate as 1.0 past their center) CENTER points (center of the member function shape) OVERLAP (N&Z, Z&P, typically about 50% of width but can be less).

The features of a membership function illustrates the features of the triangular membership function which is used in this example because of its mathematical simplicity. Other shapes can be used but the triangular shape lends itself to this illustration. The degree of membership (DOM) is determined by plugging the selected input parameter (error or error-dot) into the horizontal axis and projecting vertically to the upper boundary of the membership function(s).

A sample case consider an "error" of -1.0 and an "error-dot" of +2.5. These particular input conditions indicate that the feedback has exceeded the command and is still increasing.

The degree of membership for an "error" of -1.0 projects up to the middle of the overlapping part of the "negative" and "zero" function so the result is "negative" membership = 0.5 and "zero" membership = 0.5. Only rules associated with "negative" & "zero" error will actually apply to the output response. This selects only the left and middle columns of the rule matrix. For an "error-dot" of +2.5, a "zero" and "positive" membership of 0.5 is indicated.

This selects the middle and bottom rows of the rule matrix. By overlaying the two regions of the rule matrix, it can be seen that only the rules in the 2-by-2 square in the lower left corner (rules 4,5,7,8) of the rules matrix will generate non-zero output conclusions. The others have a zero weighting due to the logical AND in the rules.

As inputs are received by the system, the rule base is evaluated. The antecedent (IF X AND Y) blocks test the inputs and produce conclusions. The consequent (THEN Z) blocks of some rules are satisfied while others are not. The conclusions are combined to form logical sums. These conclusions feed into the inference process where each response output member function's firing strength (0 to 1) is determined.

Degree of membership for the error and error-dot functions in the current example Data summary from previous illustrations:

"error" = -1.0: "negative" = 0.5 and "zero" = 0.5 "error-dot" = +2.5: "zero" = 0.5 and "positive" = 0.5 ANTECEDENT & CONSEQUENT BLOCKS (e = error, er = error-dot or error-rate) Now referring back to the rules, plug in the membership function weights from above. "Error" selects rules 1,2,4, 5,7,8 while "error-dot" selects rules 4 through 9. "Error" and "error-dot" for all rules are combined to a logical product (LP or AND, that is the minimum of either term). Of the nine rules selected, only four (rules 4,5,7,8) fire or have non-zero results. This leaves

fuzzy output response magnitudes for only "Cooling" and "No_Change" which must be inferred, combined, and defuzzified to return the actual crisp output. In the rule list below, the following ddefinitions apply: (e)=error, (er)=error-dot. 1. If (e < 0) AND (er < 0) then Cool 0.5 & 0.0 = 0.0 2. If (e = 0) AND (er < 0) then Heat 0.5 & 0.0 = 0.0 3. If (e > 0) AND (er < 0) then Heat 0.0 & 0.0 = 0.0 4. If (e < 0) AND (er = 0) then Cool 0.5 & 0.5 = 0.5 5. If (e = 0) AND (er = 0) then No_Chng 0.5 & 0.5 = 0.5 6. If (e > 0) AND (er = 0) then Heat 0.0 & 0.5 = 0.0 7. If (e < 0) AND (er > 0) then Cool 0.5 & 0.5 = 0.5 8. If (e = 0) AND (er > 0) then Cool 0.5 & 0.5 = 0.5 9. If (e > 0) AND (er > 0) then Heat 0.0 & 0.5 = 0.0

• • • • • 3HP induction motor. At fault conditions, Y phase cutoff from the supply,this is achieved by using ideal switch. Input current=20-30A. Losses nearly 500 W. Output power=1.75KW.

• • • • • 3HP induction motor. Input voltage=115V. Torque is continuosly varied. Motor not tends to rotate. This type of motor destroy the drive application.

• • • • 3HP induction motor. Input voltage is varied continuously. Torque & speed is also varied continuously. This type of faults totally destroys the drive application at all.

• • • • In blocked rotor conditions, the speed of the induction motor is zero. It simply acts as a secondary short-circuited transformer. The whole power is utilised to produce the losses. Here, the output power is wattless(useless).

• • • • • Input voltage>230V. Input current is high. Both the stator & rotor losses is high. Torque is plenty, due to high starting torque ,there is an advantage in starting,but there is always high amount of losses. Output power is so much reduced.


5v Power Supply
J11 2 1 C ON2 2 3 S W S P DT C 1 100uF/16V 4 7 0 u F /2 5 V C 2 C3 0 .1 u F D 1 LE D GN D 2 GND R1 330E S W 1 1 1 L M 7 8 0 5 C /T O 2 2 0 IN U1 OU T 3 V C C

Almost all the electronic devices and circuits require a D.C, source for all the operation. One form of D.C. source is batteries. But they are costly and require frequent replacement. The easily available and most economical source is A.C. into a suitable D.C. such a device is called power supply. The power supply consists of the following the three sub divisions 1. Rectifier 2. Filter 3. Voltage regulator

A rectifier is a device which offers a low resistance to the current in one direction and a high resistance in the opposite direction. Such a device is capable of converting A.C. voltage into a pulsating D.C. voltage. The rectifier employs one or more diodes. It may be either a vacuum diode or a semiconductor diode. There are two types 1. Half wave rectifier 2. Full wave rectifier

3. Bridge rectifier

Bridge rectifier is a full wave rectifier. It consists of four diodes , arranged in the form of a bridge . it utilizes the advantages of the full wave rectifier and at the same time it eliminates the need for a centre tapped transformer. The supply input and the rectified output are the two diagonally opposite terminals of the bridge. During the positive half cycle, the secondary terminal A is positive w.r.t. terminal B. now the diodes D1 and D3 are forward biased and hence do not conduct. The current flows from terminal A to terminal B through D1, load resistance RL and the diode D3 and then through the secondary of the transformer. During the negative half cycle, terminal B is positive w.r.t point A. now diodes D2 and D4 are forward biased and hence conduct. Diode D1 and D3 are reversed biased and hence do not conduct. The current flows from terminal B to terminal A through diode D2, the load resistance RL and diode D4 and then through the secondary of the transformer. On both positive and negative half cycles of the A.C. input, the current flows through the load resistance RL in the same direction. The polarity of the voltage developed across RL is such that the end connected to the junction of the diodes D1 and D2 will be positive.

1. Centre tapped transformer is not necessary.

2. D.C. saturation of the transformer does not take place since the two currents flow in the opposite direction through transformer secondary. 3. Transformer utilization factor is increased. 4. PIV rating across each diode is Vm.

1. The circuit requires a four diodes and hence additional voltage drop that reduce the output voltage through the transformer secondary.
2. It’s rarely used with thermionic diode value because of heater supply problem.

Output from the rectifier unit having harmonic contents , so we can provided the filter circuit, filter circuit is used to reduce the harmonics. Here we can use the pi filter .pi filter consists of capacitance and inductance (i.e. two capacitance in parallel and one inductance in series). These eliminates the harmonics from both voltage and current signals.

Voltage regulator is used to maintain the constant voltage with the variation of the supply voltage and the load current, mainly we can use the two types of voltage regulator they are 1. series voltage regulator 2. zener diode voltage regulator .


+5V R4 10K R3 1K 1 A D C _C H 0

R2 4 .7 K


Q1 3B C 5 4 7

R T1 10K

These temperature control circuit is mainly consists of transistor and resistance, it is used to maintain the constant temperature with the variation of passive circuit parameters.



D1 1N4007

NO NC Q1 2N 2222


M C P o rt P i n


Relays are components which allow a low-power circuit to switch a relatively high current on and off, or to control signals that must be electrically isolated from the controlling circuit itself. Newcomers to electronics sometimes want to use a relay for this type of application, but are unsure about the details of doing so. Here’s a quick rundown. To make a relay operate, you have to pass a suitable .pull-in. and .holding current (DC) through its energizing coil. And generally relay coils are designed to operate from a particular supply voltage. Often 12V or 5V, in the case of many of the small relays used for electronics work. In each case the coil has a resistance which will draw the right pull-in and holding currents when it’s connected to that supply voltage. So the basic idea is to choose a relay with a coil designed to operate from the supply voltage you’re using for your control circuit (and with contacts capable of switching the currents you want to control), and then provide a suitable .relay driver. Circuit so that your lowpower circuitry can control the current through the relay’s coil. Typically this will be somewhere between 25Ma and 70mA. Often your relay driver can be very simple, using little more than an NPN or PNP transistor to control the coil current. All your low-power

circuitry has to do is provide enough base current to turn the transistor on and off, as you can see from diagrams A and B. In A, NPN transistor Q1 (say a BC337 or BC338) is being used to control a relay (RLY1) with a 12V coil, operating from a +12V supply. Series base resistor R1 is used to set the base current for Q1, so that the transistor is driven into saturation (fully turned on) when the relay is to be energized. That way, the transistor will have minimal voltage drop, and hence dissipate very little power. As well as delivering most of the 12V to the relay coil. How do you work out the value of R1? It’s not hard. Let’s say RLY1 needs 50mA of coil current to pull in and hold reliably, and has a resistance of 240ohmso it draws this current from 12V. Our BC337/338 transistor will need enough base current to make sure it remains saturated at this collector current level. To work this out, we simply make sure that the base current is greater than this collector current divided by the transistor’s minimum DC current gain hFE. So as the BC337/338 has a minimum hFE of 100 (at 100mA), we’d need to provide it with at least 50mA/100 = 0.5mA of base current. In practice, you’d give it roughly double this value, say 1mA of base current, just to make sure it does saturate. So if your control signal Vin was switching between 0V and +12V, you’d give R1 a value of say 11kohm, to provide the 1mA of base current needed to turn on both Q1 and the relay. If our relay has a coil resistance of say 180ohm, so that it draws say 67mA at 12V, we’d need to reduce R1 to say 8.2kohm, to increase the base current to about 1.4mA. Conversely if the relay coil is 360ohmand draws only 33mA, we could increase R1 to 15kohm, giving about 0.76mA of base current. Each time we go for about twice the relay coil current divided by Q1.s hFE. Get the idea? As you can see a power diode D1 (1N4001 or similar) is connected across the relay coil, to protect the transistor from damage due to the back-EMF pulse generated in the relay coil’s inductance when Q1 turns off. The basic NPN circuit in diagram A is fine if you want the relay to energies when your control voltage Vin is high (+12V), and be off when Vin is low (0V). But what if you want the opposite? That’s where you’d opt for a circuit like that shown in diagram B, using a PNP transistor like the BC327 or BC328. This is essentially the same circuit as in A, just swung around to suit the PNP transistor’s polarity. This time transistor Q2 will turn on and energies the relay when Vin is low (0V), and will turn off when Vin is high (+12V). Otherwise everything works just

as before, and the value of base resistor R2 is worked out in the same way as for R1. In fact because the minimum hFE of the BC327/328 PNP transistors is also 100 at 100mA, you could use exactly the same values of R2 to suit each relay resistance/current. The simple transistor driver circuits of A and B are very low in cost, and are generally fine for driving most relays. However there may be occasions, such as when your control circuit is based on CMOS logic, where the base current needed by these circuits is a bit too high. For these situations the circuit shown in C might be of interest, because it needs rather less input current. As you can see it uses a readily available and very low cost 555 IC as the relay driver, plus only one extra component: bypass capacitor C1. Although we normally think of the 555 as a timer/oscillator, it’s actually very well suited for driving a small relay. Output pin 3 can both source and sink 200mA (enough to handle most small relays comfortably), and the internal flip-flop which controls its output stage is triggered swiftly between its two states by internal comparators connected to the two sensing inputs on pins 2 and 6. When these pins are taken to a voltage above 2/3 the supply voltage, the output switches low (0V); then they are taken below 1/3 the supply voltage, the output swings high. And the 555 can happily work at 5V, as you can see, so it’s very suitable for driving a 5V relay coil from this supply voltage.

Sign up to vote on this title
UsefulNot useful

Master Your Semester with Scribd & The New York Times

Special offer: Get 4 months of Scribd and The New York Times for just $1.87 per week!

Master Your Semester with a Special Offer from Scribd & The New York Times