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CONTENTS

PAGE NO. Chapter Chapter-1 Chapter-2 2.1 2.2 i) ii) iii) Chapter-3 3.1 3.2 3.3 3.4 3.5 3.6 Chapter-4 4.1 4.2 4.3 4.4 Chapter-5 Chapter-6 6.1 6.2 6.3 6.4 ABSTRACT............................................................ Introduction........................................................... Hardware Block diagram...................................................... Hardware description......................................... MAX232.............................................................. LDR..................................................................... Analog to Digital Converters............................ I2C-BUS I2C-BUS Concept................................................ General characteristics....................................... Start&stop condition.......................................... Transfering data................................................. Synchronisation.................................................. Arbitration........................................................ ADDRESSING FORMATS OF I2C-BUS 7-bit addressing.................................................... 10-bit addressing.................................................. Fast mode............................................................ High speed mode................................................ Design Calculation I/0 EXPANDERS Features................................................................. General description.............................................. Bus Expanders,Hubs,buffers& repeaters…… Electrical connections of lines ……………… 43 44 45 29 31 35 36 39 18 20 21 22 24 25 12 13 13 15 16 7 9

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Chapter-7 7.1 i) ii) 7.2 7.3 7.4 i) ii) iii) iv) v) vi) Chapter-8 8.1 8.2 8.3 Chapter-9 9.1 9.2 9.3 9.4 9.5

Memory Types Volatile Memory…………………………………….. RAM…………………………………………….. DDR SDRAM………………………………….. Non-Volatile memory…………………………. Flash Memory…………………………………. EEPROM Features …………………………………….. Pin diagram………………………………….. Device operation…………………………….. Device Addressing ……………………………. 53 54 56 57 58 59 62 64 65 70 72 73 75 85 92 93 50 50 51 52 52

Data Security…………………………………
Read Operation…………………………………. RTC Features………………………………………….. Pin Description…………………………………. Block Diagram………………………………….. Software Implementation Keil software…………………………………. Wait for read operation……………………. Wait for write operation…………………….. EEPROM coding…………………………….. RTC coding………………………………….. CONCLUSION................................................ REFERENCES...............................................

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ABSTRACT

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For analysis and archiving purposes. the data can be transferred to a PC with a graphical user interface program through a USB link. The measurements of temperature. The option will be provided and data will be retrieved from EPROM and it will be display on pc. where the user is asked to enter choice from the menu options related to EEPROM and LM35.ABSTRACT: I2C bus for interfacing serial EEPROM and LM35 using microcontroller: The circuit is also provided with an RS232 port for connecting with PC to send commands for reading/writing EEPROM or setting date/time in RTC. User can store data in EEPROM. using analogue and digital components. atmospheric pressure and relative humidity remotely by using the appropriate sensors are not only important in environmental or weather monitoring but also crucial for many industrial processes. A screen shot of the message sent to PC by microcontroller immediately after power ON is shown in the figure at the left. The analogue outputs of the sensors are connected to a microcontroller through an ADC for digital signal conversion and data logging. or when he wants to know the Environmental conditions. 4 . Communication with PC is done through Hyper Terminal. A device for weather monitoring has been developed as described in this paper to monitor and display the temperature. pressure and relative humidity of the atmosphere. An LCD display is also connected to the microcontroller to display the measurements.

CHAPTER-1 INTRODUCTION 5 .

industry standard. communication bus (a path for electronic signals) developed by Philips Semiconductors in the early 1980s. I2C has expanded its communications role to include a wide range of applications. including memories. with some venturing up into the low megahertz range. sensors of many types. It provides a low-cost. and real-time clocks. The I2C (Inter-Integrated Circuit) Bus is a two-wire. Over the past decade. and much more. but powerful. 6 . Its low cost and powerful features make I2C ideal for low to medium speed chip-to-chip communications. real-time clocks. I2C was created to reduce the manufacturing costs of electronic products. data entry devices. Examples of simple I2C-compatible devices found in embedded systems include EEPROMs. thermal sensors. I2C is easy to use to link multiple devices together since it has a built-in addressing scheme. To maintain the performance of these systems. low to medium speed. so a failure or a data trend leading to a potential failure can be rapidly identified. It is a simple. application-specific data interfaces. These companies offer a variety of electronic devices. adequate environmental monitoring must be performed. The I2C Bus is a time-proven. most available i2c devices operate at speeds up to 400kbps. Initial applications for I2C included volume and contrast control in radios and televisions.INTRODUCTION: Communication network systems are rapidly growing in size and complexity. this monitoring must be performed cheaply to keep system costs low. I2C is supported by a large and growing number of semiconductor and system manufacturers. short distance protocol. displays. low band width.I2C is an effective technology that can lower product costs and increase product performance. I2C is also used as a control interface to signal processing devices that have separate. input and output devices. Furthermore. communication protocol used in a wide variety of electronic products. chip-to-chip communication link within these products. These systems have many high speed integrated circuits with critical operating parameters and must provide extremely reliable service with zero down time.

I2C has expanded its communications role to include a wide range of applications. the I2C bus is used in many other application fields than just audio and video equipment. but powerful. Today. Maxim. and other manufacturers offer hundreds of I2C-compatible devices. Initial applications for I2C included volume and contrast control in radios and televisions. The I2C bus has been adopted by several leading chip manufacturers like Xicor. I2C has expanded its communications role to include a wide range of applications. . I2C was created to reduce the manufacturing costs of electronic products. Atmel. communication bus (a path for electronic signals) developed by Philips Semiconductors in the early 1980s. Philips. Over the past decade. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus. This design concept solves the many interfacing problems encountered when designing digital control circuits. 7 .In all. Infineon Technologies. low to medium speed. Xicor. It provides a low-cost. National Semiconductor. Over the past decade. ST Microelectronics. Texas Instruments. The bus is generally accepted in the industry as a de-facto standard. I2C has become a de facto world standard that is now implemented in over 1000 different ICs and is licensed to more than 50 companies. Analog Devices and others. Siemens. chip-to-chip communication link within these products. Initial applications for I2C included volume and contrast control in radios and televisions. The I2C (Inter-Integrated Circuit) Bus is a two-wire. Intel.

CHAPTER-2 HARDWARE 8 .

1 BLOCK DIAGRAM: 9 .2.

These receivers have a typical 10 .PC RS 232 MAX 232 Micro Controller I2C Protocol EEPROM ADC LDR 2. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels.2 Hardware description: i) MAX232: The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/EIA-232-F voltage levels from a single 5-V supply.

Modems. Battery-Powered Systems.threshold of 1..8 ma Typical. Available With the MAX202. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. Upgrade With Improved ESD (15-kV HBM) and 0. Terminals. ±30-V Input Levels. and can accept ±30-V inputs. Two Drivers and Two Receivers. a typical hysteresis of 0.1-F Charge-Pump Capacitors.28 Operates From a Single 5-V Power Supply With 1. ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A)..3 V.0-F Charge-Pump Capacitors Operates Up To 120 kbit/s. Pin diagram: 11 . FEATURES: • • • • • • • • • Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V. Applications: • • • • • TIA/EIA-232-F. and Computers.5 V. Low Supply Current .

it waits until the write operation is finished. ii) LDR (Light dependent resistance): 12 . Wait: then. the program writes the contents of a predefined buffer to the memory starting from address 0x00 of Block3. The software implemented to manage read and write operations between the STR71x I2C interface and the M24C08 is divided in three parts: Write: first.In this application note the software modules are developed in C language. Read: finally it reads the data already written. with RVDK environment.

A photo resistor or light dependent resistor or cadmium sulfide (CdS) cell is a resistor whose resistance decreases with increasing incident light intensity. and added whose ground state energy is closer to the conduction band. A photoelectric device can be either intrinsic or extrinsic. An intrinsic semiconductor has its own charge carriers and is not an efficient semiconductor. thereby lowering resistance. since the electrons do not have as far to jump. also called dopants. street lights. and outdoor clocks. and hence the photon must have enough energy to excite the electron across the entire band gap. Extrinsic devices have impurities. silicon. The resulting free electron (and its hole partner) conduct electricity. It can also be referenced as a photoconductor.. longer wavelengths and lower frequencies) are sufficient to trigger the device. Inexpensive cadmium sulfide cells can be found in many consumer items such as camera light meters. lower energy photons (i.e. A photo resistor is made of a high resistance semiconductor. photons absorbed by the semiconductor give bound electrons enough energy to jump into the conduction band. alarms. 13 .g. In intrinsic devices the only available electrons are in the valence band. Applications: Photo resistors come in many different types. e. If light falling on the device is of high enough frequency. clock radios.

such as rotary encoders. or 16 bit ADCs are common in microcontrollers. A/D or A to D) is a device which converts continuous signals to discrete digital numbers. The reverse operation is performed by a digital-to-analog converter (DAC). some non-electronic or only partially electronic devices. APPLICATIONS: AD converters are used virtually everywhere where an analog signal has to be processed. Slow on-chip 8.. for example. such as binary. However. Ge:Cu photoconductors are among the best far-infrared detectors available. Typically. iii) Analog to digital converter: An analog-to-digital converter (abbreviated ADC. 10.They are also used in some dynamic compressors together with a small incandescent lamp or light emitting diode to control gain reduction. 12. stored. 14 . and are used for infrared astronomy and infrared spectroscopy. and are crucial for new applications like software defined radio. or transported in digital form. Fast video ADCs are used. Lead sulfide and indium antimonite LDRs are used for the mid infrared spectral region. an ADC is an electronic device that converts an input analog voltage (or current) to a digital number. The digital output may use different coding schemes. can also be considered ADCs. Very fast ADCs are needed in digital oscilloscopes. in TV tuner cards. Gray code or two's complement binary.

Chapter-3 I2C BUS 15 .

devices can also be considered as masters or slaves when performing data transfers. any device addressed is considered a slave. Obviously an LCD driver is only a receiver. Each device is recognized by a unique address — whether it’s a microcontroller. serial data (SDA) and serial clock (SCL). It should be noted that these relationships are not permanent. At that time. bipolar). let’s consider the case of a data transfer between two microcontrollers connected to the I2C-bus . This means that more than one device capable of controlling the bus can be connected to it. 16 .This highlights the master-slave and receiver-transmitter relationships to be found on the I2C-bus. carry information between the devices connected to the bus. but only depend on the direction of data transfer at that time. In addition to transmitters and receivers. whereas a memory can both receive and transmit data. LCD driver. memory or keyboard interface — and can operate as either a transmitter or receiver.1 I2C bus concept: The I2C-bus supports any IC fabrication process (NMOS.3. Two wires. As masters are usually micro-controllers. CMOS. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. depending on the function of the device. Fig1: Example of i2c-bus configuration using two micro controller The I2C-bus is a multi-master bus.

This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line. 2. Even in this case. Microcontroller A (master) addresses microcontroller B (slave) Microcontroller A (master-receiver) receives data from microcontroller B (slave-transmitter) Microcontroller A terminates the transfer. or by another master when arbitration occurs. To avoid the chaos that might ensue from such an event — an arbitration procedure has been developed. The possibility of connecting more than one microcontroller to the I2C-bus means that more than one master could try to initiate a data transfer at the same time. each master generates its own clock signals when transferring data on the bus. the master (microcontroller A) generates the timing and terminates the 17 . sends data to microcontroller B (slaver) Microcontroller A terminates the transfer. If two or more masters try to put information onto the bus. Suppose microcontroller A wants to send information to microcontroller B: • • • Microcontroller A (master). Generation of clock signals on the I2C-bus is always the responsibility of master devices. If microcontroller A wants to receive information from microcontroller B: • • • transfer. the first to produce a ‘one’ when the other produces a ‘zero’ will lose the arbitration.The transfer of data would proceed as follows: 1. addresses microcontroller B (slave) Microcontroller A (master-transmitter). Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line.

When the bus is free. connected to a positive supply voltage via a pull-up resistor (see Figure 2). The output stages of devices connected to the bus must have an open-drain or open-collector in order to perform the wired-AND function. or up to 400 kbit/s in the fast-mode. both lines are HIGH. Data on the I2C-bus can be transferred at a rate up to 100 kbit/s in the standard-mode.3. The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400pF.2 GENERAL CHARACTERISTICS: Both SDA and SCL are bidirectional lines. Fig2: Connection of i2c bus devices to the i2c bus 18 .

0 for Electrical Specifications). 19 .BIT TRANSFER: Due to the variety of different technology devices (CMOS. the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of VDD (see Section 15. unique situations arise which are defined as START and STOP conditions (see Figure 3). Fig3: bit transfer on the i2c bus 3. Data validity: The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.3 START and STOP conditions: Within the procedure of the I2C-bus. bipolar) which can be connected to the I2C-bus. One clock pulse is generated for each data bit transferred. NMOS.

microcontrollers with no such interface have to sample the SDA line at least twice per clock period in order to sense the transition. Data transfer then continues when the receiver is ready for another byte of data and releases clock line SCL. However. it can hold the clock line SCL LOW to force the transmitter into a wait state. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. Each byte has to be followed by an acknowledge bit. 3.A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. In some cases. The bus is considered to be free again a certain time after the STOP condition. The bus is considered to be busy after the START condition. for example servicing an internal interrupt. it’s permitted to use a different format from the I2C-bus format (for CBUS compatible devices for example). Data is transferred with the most significant bit (MSB) first (Figure 5) If a receiver can’t receive another complete byte of data until it has performed some other function. This situation indicates a START condition. The number of bytes that can be transmitted per transfer is unrestricted. A message which starts with such an address 20 .4 TRANSFERRING DATA: Byte format: Every byte put on the SDA line must be 8-bits long. START and STOP conditions are always generated by the master.

21 . The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (Figure 6). Fig5: Data transfer on the i2c bus Acknowledge: Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master.can be terminated by generation of a STOP condition. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. even during the transmission of a byte.

The master can then generate a STOP condition to abort the transfer. When a slavereceiver doesn’t acknowledge the slave address (for example. 3. The slave leaves the data line HIGH and the master generates the STOP condition. Data is only valid during the HIGH period of the clock. except when the message starts with a CBUS address. Usually. This is indicated by the slave generating the not acknowledge on the first byte to follow. A defined clock is therefore needed for the bit-by-bit arbitration procedure to take place. some time later in the transfer cannot receive any more data bytes. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition. 22 . the data line must be left HIGH by the slave. it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave.Fig6: Acknowledge on the i2c bus Of course.5 Synchronization: All masters generate their own clock on the SCL line to transfer messages on the I2C-bus. it’s unable to receive because it’s performing some real-time function). If a master-receiver is involved in a transfer. If a slave-receiver does acknowledge the slave address but. set-up and hold times must also be taken into account. the master must again abort the transfer. a receiver which has been addressed is obliged to generate an acknowledge after each byte has been received.

a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period. When all devices concerned have counted off their LOW period.Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. and all the devices will start counting their HIGH periods. Devices with shorter LOW periods enter a HIGH wait-state during this time. once a device clock has gone LOW. The first device to complete its HIGH period will again pull the SCL line LOW. There will then be no difference between the device clocks and the state of the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and. and its HIGH period determined by the one with the shortest clock 23 . The SCL line will therefore be held LOW by the device with the longest LOW period. the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. the clock line will be released and go HIGH. Fig7:Clock synchronization during the arbitration procedure However. In this way. it will hold the SCL line in that state until the clock HIGH state is reached (Figure 7).

Its first stage is comparison of the address bits (addressing information is in Sections 9. Because address and data information on the I2C-bus is used for arbitration.3. Two or more masters may generate a START condition within the minimum hold time (tHD.0 and 13. it’s possible that the winning master is trying to address it.6 Arbitration: A master may start a transfer only if the bus is free. its data output is switched off. arbitration continues with comparison of the data. A master which loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. STA) of the START condition which results in a defined START condition to the bus. while another master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level. no information is lost during this process. Arbitration can continue for many bits. while the SCL line is at the HIGH level. If a master also incorporates a slave function and it loses arbitration during the addressing stage. The losing master must therefore switch over The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line. in such a way that the master which transmits a HIGH level.0). If the masters are each trying to address the same device. 24 . Arbitration takes place on the SDA line.

which means that a HIGH output level is then connected to the bus? This will not affect the data transfer initiated by the winning master. or with only a limited hardware I2C interface on-chip can slow down the bus clock by extending each clock LOW period. Since control of the I2C-bus is decided solely on the address and data sent by competing masters. there is no central master. 25 . arbitration isn’t allowed between: • • • A repeated START condition and a data bit A STOP condition and a data bit A repeated START condition and a STOP condition. on either a byte level or a bit level. the arbitration procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C-bus. On the bit level. If it’s possible for such a situation to occur. On the byte level. In other words. the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. The speed of any master is thereby adapted to the internal operating rate of this device. Special attention must be paid if. Slaves can then hold the SCL line LOW after reception and acknowledgement of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure. nor any order of priority on the bus. Use of the clock synchronizing mechanism as a handshake: In addition to being used during the arbitration procedure. a device may be able to receive bytes of data at a fast rate. during a serial transfer. a device such as a microcontroller without. but needs more time to store a received byte or prepare another byte to be transmitted. the clock synchronization mechanism can be used to enable receivers to cope with fast data transfers.

Chapter -4 Addressing Formats of I2C-bus 26 .

Various combinations of read/write formats are then possible within such a transfer. A data transfer is always terminated by a STOP condition (P) generated by the master.1 7-BIT ADDRESSING: Data transfers follow the format shown in Figure 8.4. it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. a ‘one’ indicates a request for data (READ). After the START condition (S). if a master still wishes to communicate on the bus. a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) —a ‘zero’ indicates a transmission (WRITE). Fig8: complete data transfer Possible data transfer formats are: 27 . However.

 Master reads slave immediately after first byte : At the moment of the first acknowledge. The transfer direction is not changed. The STOP condition is generated by the master  Combined format: During a change of direction within a transfer. Master-transmitter transmits to slave-receiver. This acknowledge is still generated by the slave. the START condition and the slave address are both repeated. the master-transmitter becomes a masterreceiver and the slave-receiver becomes a slave-transmitter. but with the R/W 28 .

to control a serial memory. NOTES:  Combined formats can be used. it has previously sent a not acknowledge (A). data can be transferred. After the START condition and slave address is repeated.bit reversed. 29 . During the first data byte. The concept is accepted world-wide as a de facto standard and hundreds of different types of I2C-bus compatible ICs are available from Philips and other suppliers. are taken by the designer of the device. the internal memory location has to be written.  All decisions on auto-increment or decrement of previously accessed memory locations etc.  I2C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the  Sending of a slave address.  Each byte is followed by an acknowledgement bit as indicated by the A or A blocks in the sequence. If a master receiver sends a repeated START condition. for example. EXTENSIONS TO THE I2C-BUS SPECIFICATION: The I2C-bus with a data transfer rate of up to 100 kbit/s and 7-bit addressing has now been in existence for more than ten years with an unchanged specification.

A ‘zero’ in the least significant position of the first byte means that the master will write information to a selected slave. then the next byte contains data transmitted from a slave to a master Formats with 10-bit addresses Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. The 10-bit addressing does not affect the existing 7-bit addressing. A ‘one’ in this position means that the master will read information from the slave. Definition of bits in the first two bytes The 10-bit slave address is formed from the first two bytes following a START condition (S) or a repeated START condition (Sr). Possible data transfer formats are: 30 .2 10-BIT ADDRESSING: The 10-bit addressing does not change the format in the I2C-bus specification.1. Devices with 7-bit and 10-bit addresses can be connected to the same I2Cbus. The first seven bits of the first byte are the combination 11110XX of which the last two bits (XX) are the two most-significant bits (MSBs) of the 10-bit address. If the R/W bit is ‘zero’. Using 10 bits for addressing exploits the reserved combination 1111XXX for the first seven bits of the first byte following a START (S) or repeated START (Sr) condition as explained in Section 9. only the four combinations 11110XX are used for 10-bit addressing. then the second byte contains the remaining 8 bits (XXXXXXXX) of the 10-bit address. The remaining four combinations 11111XX are reserved for future I2C-bus enhancements. Although there are eight possible combinations of the reserved address bits 1111XXX. the eighth bit of the first byte is the R/W bit that determines the direction of the message. If the R/W bit is ‘one’. and both 7-bit and 10-bit addressing can be used in a standard-mode system (up to 100 kbit/s) or a fast-mode system (up to 400 kbit/s).4.

transmitter with a 10-bit slave address. It is possible that more than one device will find a match and generate an acknowledge (A1). The transfer direction is not changed (shown below). The matching slave will remain addressed by the master until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. • Master-receiver reads slave. • Up to and including acknowledge bit A2.• Master-transmitter transmits to slave-receiver with a 10-bit slave address. the procedure is the same as that described for a master-transmitter addressing a slave-receiver. but only one slave will find a match and generate an acknowledge (A2). each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own address and tests if the • Eighth bit (R/W direction bit) is 0. The transfer direction is changed after the second R/W bit (Figure 30). After the repeated 31 . • When a 10-bit address follows a START condition. All slaves that found a match will compare the eight bits of the • Second byte of the slave address (XXXXXXXX) with their own addresses.

or the 11110XX slave address (for 7-bit devices) does not match). The same master occupies the bus all the time. After a repeated START condition (Sr). all the other slave devices will also compare the first seven bits of the first byte of the slave address (11110XX) with their own addresses and test the eighth (R/W) bit. This slave then checks if the first seven bits of the first byte of the slave address following Sr are the same as they were after the • START condition (S) and tests if the eighth (R/W) bit is 1. 32 . A master transmits data to one slave and then transmits data to another slave. However. The same master occupies the bus all the time. Combined format.START condition (Sr). the slave considers that it has been addressed as a transmitter and generates acknowledge A3. a matching slave remembers that it was addressed before. A master transmits data to a slave and then reads data from the same slave. • The slave-transmitter remains addressed until it receives a STOP condition (P) or until it receives another repeated START condition (Sr) followed by a different slave address. – Combined format. If there is a match. none of them will be addressed because R/W = 1 (for 10-bit devices). The transfer direction is changed after the second R/W bit.

3. 2. Combined formats can be used. Figure shows how a master-transmits data to a slave with a 7-bit address and then transmits data to a second slave with a 10-bit address. or each repeated START condition (Sr). data can be transferred. Each byte is followed by an acknowledgement bit as indicated by the A or A blocks in the sequence. for example. to control a serial memory. the internal memory location has to be written. All decisions on auto-increment or decrement of previously accessed memory locations etc. The same master occupies the bus all the time. 33 . 4. NOTES: 1. After each START condition (S). During the first data byte. are taken by the designer of the device. After the START condition and slave address is repeated. I2C-bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address. a 10-bit or 7-bit slave. • Address can be transmitted. 10-bit and 7-bit addressing combined in one serial transfer.Combined format.

the SDA and SCL I/O pins must be floating so that they don’t obstruct the bus lines The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the fast-mode I2Cbus.3 FAST-MODE: In the fast-mode of the I2C-bus. the pull-up device for each bus line can be a resistor.) or a switched resistor circuit as shown below 34 . for bus loads between 200pF and 400pF. logic levels and maximum capacitive load for the SDA and SCL lines quoted in the previous I2C-bus specification are unchanged.4. There is no need for compatibility with other bus systems such as CBUS because they cannot operate at the increased bit rate • • • • The inputs of fast-mode devices must incorporate spike suppression and a Schmitt trigger at the SDA and SCL inputs The output buffers of fast-mode devices must incorporate slope control of the falling edges of the SDA and SCL signals If the power supply to a fast-mode device is switched off. the protocol. For bus loads up to 200pF. format. the pull-up device can be a current source (3mA max. Changes to the previous I2C-bus specification are: • • The maximum bit rate is increased to 400 kbit/s Timing of the serial data (SDA) and serial clock (SCL) signals has been adapted.

yet they remain fully downward compatible with Fast.4 Mbit/s. new devices may have a Fast or Hs-mode I2C-bus interface. High speed transfer: To achieve a bit transfer of up to 3.4.4 Mbit/s the following improvements have been made to the regular I 2 C-bus specification: 35 .4 High Speed Mode (HSM): High-speed mode (Hs-mode) devices offer a quantum leap in I2C-bus transfer speeds. Hs-mode devices can transfer information at bit rates of up to 3.or Standard-mode (F/S-mode) devices for bidirectional communication in a mixed-speed bus system. although Hs-mode devices are preferred as they can be designed-in to a greater number of applications. Depending on the application.

• Hs-mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2. • The inputs of Hs-mode devices incorporate spike suppression and a Schmitt trigger at the SDAH and SCLH inputs. • • The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate. these pins can be used for other functions.This current-source circuit shortens the rise time of the SCLH signal. This relieves the timing requirements for set-up and hold times. The figure below shows the physical I 2 C-bus configuration in a system with only • Hs-mode devices. Hs-mode master devices can have a built-in bridge (1) . although this is only allowed after the acknowledge bit in Hs-mode transfers. Pins SDA and SCL on the master devices are only used in mixedspeed bus systems and are not connected in an Hs-mode only system. Optional pull-down transistors on the SCLH pin can be used to stretch the LOW level of the SCLH signal. This reduces the capacitive load of the SDAH and SCLH lines resulting in faster rise and fall times. which speeds-up bit handling capabilities. The arbitration procedure always finishes after a preceding master code transmission in F/Smode. the high speed data (SDAH) and high-speed serial clock (SCLH) lines of Hs-mode devices are separated by this bridge from the SDA and SCL lines of F/S-mode devices. During Hsmode transfer. Only the current-source of one master is enabled at any one time.• Hs-mode master devices have an open-drain output buffer for the SDAH signal and a combination of an open-drain pull-down and current-source pull-up circuit on the SCLH output (1) . 36 . and only during Hs-mode. In such cases. Hs-mode slaves have open-drain output buffers on the SCLH and SDAH outputs. The output buffers of Hs-mode devices incorporate slope control of the falling edges of the SDAH and SCLH signals. • No arbitration or clock synchronization is performed during Hs-mode transfer in multi-master systems. As an option.

Pull-up resistors Rp maintain the SDAH and SCLH lines at a HIGH level when the bus is free and ensure the signals are pulled up from a LOW to a HIGH level within the required rise time. 37 .Optional series resistors Rs protect the I/O stages of the I2C-bus devices from high-voltage spikes on the bus lines and minimize ringing and interference. the resistor Rp can be replaced by external current source pull-ups to meet the rise time requirements. the rise time of the SCLH clock pulses in Hs-mode transfers is shortened by the internal current-source pull-up circuit MCS of the active master. For higher capacitive bus-line loads (>100 pF). Unless proceeded by an acknowledge bit.

the number of devices on the bus. and the length of the bus must be considered. These variables determine the total amount of capacitive load on the bus.CHAPTER-5 DESIGN CALCULATION Design Calculations for the I2C Bus: When designing an I2C network. physical characteristics of the bus wiring. which the I2C 38 .

CBUS = tR/2. If the electrical characteristics of the wiring used for the I2C bus are known. the maximum rise time is 1µs. This IC allows the total bus capacitance to increase to 4000pF and the maximum current on the bus to 30mA. the Philips 82B715.2 • CBUS………………….. RPULLUP = tR/2. 2000Ω would be a good starting value for the pull-up resistors.The value of the bus pull-up resistors are chosen based on the bus capacitance. using a digital storage oscilloscope. 39 . For standard mode (100 kHz). then 10Pf per device is a good estimate. the maximum rise time is 300nS. One such IC. or approximately 1600Ω. then it is easy to determine the total bus capacitance. Another way to find the total bus capacitance is to pick preliminary values for the pull-up resistors and analyze the rise time on the bus. So for a 5V bus. provides a 10x current gain.2 • R………………. Driving Longer Distances If the bus length in the application exceeds a few feet. selection of pull-up resistor values that satisfy the I2C specifications is a bit harder. The rise time is the time that the signal takes to go from 10% to 90% of the final value. In this case. the minimum pull-up resistance that could be used is 5V/3mA. Figure 4 shows how the bus extender IC’s are connected.specification limits to 400pF. If the capacitance of each device is not known. the rise time specification for the I2C bus must be known. Equation 1 can be rearranged to find the required value of the pull-up resistors as shown in Equation 2. All that is required is to figure out the capacitance contribution of each device on the bus. For most applications. bus extender IC’s are available that allow you to use a longer bus in your design.(1) Next. the total bus capacitance can be determined using Equation 1.(2) The I2C specification limits the amount of current on the bus to 3mA. For high speed mode (400 kHz). which indirectly places a limit on the value of the pull-up resistors. Then. which is dependent on the bus frequency.

CWIRE = 464 ns/(2. A 24 ft. length of wire was used to connect two PIC16F873 devices with 200Ω pull-up resistors on the SDA and SCL lines. per foot. is calculated in Example 1. The wiring capacitance. the characteristics of the wire that was used to test the application firmware provided in this application note. will be used in the calculations that follow. The SCL line was observed on an oscilloscope and the rise time was determined to be 464ns.Fig: I2C BUS EXTENSION BLOCK DIAGRAM It may be possible to eliminate the need for the bus extenders since PICmicro I/O pins can sink or source greater than 3mA. Example Design Calculations As a design example.2)(200 Ω)(24 ft)=44 pF/ft 40 .

5 to 6 V • Low standby current consumption of 10 µA maximum 41 .1 FEATURES: • Operating supply voltage 2.Chapter-6 I/O EXPANDERS 6.

The two wire bus reduces PCB complexity through trace reduction and routing simplification. 42 . or space-saving SO16 or SSOP20 packages The I2C I/O expander as shown in this diagram allows system layout to be greatly simplified.• I2C-bus to parallel port expander • Open-drain interrupts output • 8-bit remote I/O port for the I2C-bus • Compatible with most microcontrollers • Latched outputs with high current drive capability for directly driving LEDs • Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A) • DIP16.

The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus).Fig: System With I C I/O Expanders Advantages: • Easy board routing • Board-space savings • Processor-pin savings • Low cost • Industry standard 6.2 GENERAL DESCRIPTION: The PCF8574 is a silicon CMOS circuit. By sending an 43 .

hubs. sectional bus isolation. 3. the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device. Fig: Bus expanders. Hubs. address conflict resolution and voltage-level translation as shown in this diagram.3v and 5v buses. buffers and repeaters Advantages: • Can isolate a section on the I2C bus through enable (EN) pin. hubs. • Permits I2C bus expansion. buffers and repeaters permit bus expansion. 6.interrupt signal on this line.5v. • Supports voltage-level translation between 2. 44 . which is essential in mixed-voltage I2C systems.3 Bus Expanders. Buffers and Repeaters: I2C bus expanders. • Resolves I2C address conflicts.

I2C-bus devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected. 45 .4 ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THE BUS LINES: I2C-bus devices with fixed input levels of 1. Pull-up resistors must be connected to a 5 V ± 10% supply.5 V and 3 V can each have their own appropriate supply voltage.6.

When devices with fixed input levels are mixed with devices with input levels related to VDD, the latter devices must be connected to one common supply line of 5V ± 10% and must have pull-up resistors connected to their SDA and SCL pins as shown in Fig.35.

Input levels are defined in such a way that: • The noise margin on the LOW level is 0.1VDD • The noise margin on the HIGH level is 0.2VDD • As shown in Fig.36, series resistors (RS) of e.g. 300 Ω can be used for protection against high-voltage spikes on the SDA and SCL lines (resulting from the over of a TV picture tube, for example). flash-

46

Maximum and minimum values of resistors Rp and Rs for Standard-mode I2C-bus devices For Standard-mode I2C-bus systems, the values of resistors Rp and Rs in Fig.33 depend on the following parameters: • Supply voltage • Bus capacitance • Number of connected devices (input current + leakage current). The supply voltage limits the minimum value of resistor Rp due to the specified minimum sink current of 3mA at VOLmax = 0.4 V for the output stages. VDD as a function of Rp min is shown in Fig.37. The required noise margin of 0.1VDD for the LOW level, limits the maximum value of Rs. The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of Rp due to the specified rise time. Fig.39 shows Rp max as a function of bus capacitance.

Fig.37 .

FIG.39

47

CHAPTER-7

MEMORY TYPES

48

is computer memory that requires power to maintain the stored information. Content addressable memory and dual-ported RAM are usually implemented using volatile storage.e. The word random thus refers to the fact that any piece of data can be returned in a constant time. The volatile memory type devices are DRAM. SRAM 1) Random-access memory (RAM): RAM is a form of computer data storage. Today it takes the form of integrated circuits that allow the stored data to be accessed in any order (i. at random). Volatile memory 2. which rely on the physical movement of the recording medium or a reading head. unlike nonvolatile memory which does not require a maintained power supply. also known as volatile storage or primary storage device. This contrasts with storage mechanisms such as tapes. In these devices. Non Volatile memory 7.Memory types: There are two types of memories 1. the movement takes longer than the data transfer. Most forms of modern random access memory (RAM) are volatile storage.. including dynamic random access memory (DRAM) and static random access memory (SRAM). magnetic discs and optical discs. Early volatile storage technologies include delay line memory and Williams’s tube. 49 . and the retrieval time varies depending on the physical location of the next item. regardless of its physical location and whether or not it is related to the previous piece of data.1 Volatile Memory: Volatile memory.

Thus with a bus frequency of 100 MHz. including most types of ROM and a kind of flash memory called NOR-Flash. DDR SDRAM gives a maximum transfer rate of 1600 MB/s. Random Access Memory). This can significantly reduce power consumption.e. DDR2 picks up where DDR1 leaves off. However. where the information is lost after the power is switched off. EEPROM. With data being transferred 64 bits at a time. DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). 2) DDR SDRAM : DRAM is a class of memory integrated circuits used in computers. EPROM.6 Volt.The word RAM is mostly associated with volatile types of memory (such as DRAM memory modules). It achieves nearly twice the bandwidth of the preceding "single data rate" SDRAM by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2. 50 . To store the information we are also using a external memory devices like ROM.5v. many other types of memory are RAM as well (i. and is available at clock rates of 400 MHz and higher. Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz.. DDR SDRAM operates at a voltage of 2.

In the EPROM to erase the programme we are using UV-Radiation.3 FLASH MEMORY: Flash memory (sometimes called "flash RAM") is a type of constantly-powered nonvolatile memory that can be erased and reprogrammed in units of memory called blocks. e.. EEPROM. the flash memory can be written to in block (rather than byte) sizes. 51 . So to avoid this we are using a EEPROM.7. flash memory is not useful as random access memory (RAM) because RAM needs to be addressable at the byte (not the block) level. PROM: Program Read Only Memory is abbreviated as PROM. Flash memory is often used to hold control code such as the basic input/output system (BIOS) in a personal computer. This cost is high. which is slower than flash memory updating. On the other hand. EPROM. unlike flash memory. Non-volatile memories are PROM. Non-Volatile is a type of memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed.2 Non-Volatile memory. When BIOS needs to be changed (rewritten). It is a variation of electrically erasable programmable read-only memory (EEPROM) which.This will be use only one time . This is a type of Memory . To erase the programme we require 15-20 min. and Flash Memories. is erased and rewritten at the byte level. 7. EPROM: This is a type of memory . calibration tables or device configuration. making it easy to update.g.

52 .536 x 8 • Two-wire Serial Interface • Schmitt Triggers.000 Write Cycles – Data Retention: 40 Years • Automotive Devices Available • Die Sales: Wafer Form.8V) Compatibility • Write Protect Pin for Hardware and Software Data Protection • Self-timed Write Cycle (5 ms Max) • High Reliability – Endurance: 100.8 (VCC = 1.6V) • Internally Organized 65.5V) – 1.7 (VCC = 2.7.7V to 5. 400 kHz (2.7V) and 100 kHz (1.4 EEPROM: i) Features: • Low-voltage and Standard-voltage Operation – 2. Waffle Pack and Bumped Die. Filtered Inputs for Noise Suppression • Bidirectional Data Transfer Protocol • 1 MHz (5V).8V to 3.

The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the entire family is available in 2. The device’s cascadable feature allows up to four devices to share a common two-wire bus.7V to 5. The devices are available in space-saving 8-pin PDIP. 8-lead Leadless Array (LAP). 8-lead EIAJ SOIC. 8-lead JEDEC SOIC.6V) versions.536 words of 8 bits each.288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65. 8-lead TSSOP.8V to 3. In addition.8V (1.7V (2.ii) PIN DIAGRAM: The AT24C512 provides 524. Fig: Pin diagram 53 . and 8-lead SAP packages.5V) and 1.

Atmel recommends connecting the pin to GND. when connected to GND.SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. When WP is connected high to VCC. Switching WP to VCC prior to a write operation creates a software write protect function. allows normal write operations. all write operations to the memory is inhibited. Memory Organization: AT24C512. 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. as many as four 512K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section. This pin is Open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF. 54 . If the pin is left floating. A0): The A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other AT24Cxx devices. If the pins are left floating. the A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. DEVICE/ADDRESSES (A1. WRITE PROTECT (WP): The write protect input. Random word addressing requires a 16-bit data word address. Atmel recommends connecting the address pins to GND. If coupling is >3 pF. When the pins are hardwired.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command. the stop command will place the EEPROM in a standby power mode. Data on the SDA pin may change only during SCL low time periods. After a read sequence. ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. 55 . The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. Data changes during SCL high periods will indicate a start or stop condition as defined below.iii) Device Operation : CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.

the EEPROM will output a “0”. Upon a compare of the device address. “0” sequence for the first five most significant bits as shown. A0 to allow as many as four devices on the same bus. MEMORY RESET: After an interruption in protocol. (b) Look for SDA high in each cycle while SCL is high and then (c) Create a start condition as SDA is high. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. 56 . any two wire part can be reset by following these steps: (a) Clock up to 9 cycles.The device address word consists of a mandatory “1”. If a compare is not made. power loss or system reset. These bits must compare to their corresponding hardwired input pins. This is common to all two-wire EEPROM devices.STANDBY MODE: The AT24C512 features a low power standby mode which is enabled: a) Upon power-up and b) After the receipt of the STOP bit and the completion of any internal operations. iv) Device Addressing: The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation . The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. the device will return to a standby state. Fig: Device Address The 512K uses the two device address bits A1.

The EEPROM will respond with a “0” after each data word received. to the nonvolatile memory. Fig: Byte Write PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes. then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle. 57 . the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Upon receipt of this address. the EEPROM will output a “0”. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (Figure 8 ). tWR.v) DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows the user to Write Protect the whole memory when the WP pin is at VCC. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Following receipt of the 8-bit data word. after the EEPROM acknowledges receipt of the first data word. the microcontroller can transmit up to 127 more data words. Instead. such as a microcontroller. A page write is initiated the same way as a byte write. The microcontroller must terminate the page write sequence with a stop condition. The addressing device. but the microcontroller does not send a stop condition after the first data word is clocked in.

The address roll over during read is from the last byte of the last memory page. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation.The data word address lower 7 bits are internally incremented following the receipt of each data word. Once the device address with the Read/Write select bit set to “1” is clocked in and acknowledged by the EEPROM. This address stays valid between operations as long as the chip power is maintained. The address roll over during write is from the last byte of the current page to the first byte of the same page. to the first byte of the first page. incremented by “1”. internally generated. reaches the page boundary. This involves sending a start condition followed by the device address word. There are three read operations: Current address read. 58 . When the word address. acknowledge polling can be initiated. allowing the read or write sequence to continue. Random address read Sequential read. the current address data word is serially clocked out. The Read/Write bit is representative of the operation desired. If more than 128 data words are transmitted to the EEPROM. retaining the memory page row location. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled. vi) Read Operations: Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the device address word is set to “1”. the data word address will “roll over” and previous data will be overwritten. the following byte is placed at the beginning of the same page. The higher data word address bits are not incremented. Only if the internal write cycle has completed will the EEPROM respond with a “0”. The microcontroller does not respond with an input “0” but does generate a following stop condition.

Once the device address word and data word address are clocked in and acknowledged by the EEPROM. The EEPROM acknowledges the device address and serially clocks out the data word. 59 .RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. The microcontroller now initiates a current address read by sending a device address with the Read/Write select bit high. the microcontroller must generate another start condition. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 11 on page 11).

Chapter-8 RTC 60 .

Month. minutes. bidirectional bus. full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. The DS1307 has a built-in power-sense circuit that detects power failures and automatically switches to the battery supply. Day of the week.RTC: The DS1307 serial real-time clock (RTC) is a low-power.1 FEATURES:  Real-Time Clock (RTC) Counts Seconds. hours. The clock operates in either the 24 hour or 12-hour format with AM/PM indicator. The end of the month date is automatically adjusted for months with fewer than 31 days. Minutes. and year information. Nonvolatile (NV) RAM for Data Storage  I2C Serial Interface  Programmable Square-Wave Output Signal  Automatic Power-Fail Detect and Switch Circuitry  Consumes Less than 500nA in Battery Backup Mode with Oscillator Running  Optional Industrial Temperature Range: -40°C to +85°C  Available in 8-Pin DIP or SO  Underwriters Laboratory (UL) Recognized 61 . and Year with Leap-Year Compensation Valid Up to 2100  56-Byte. month. Address and data are transferred serially through an I2C. The clock/calendar provides seconds. Hours. day. including corrections for leap year. Battery-Backed. date. Date of the Month. 8.

-0. -40°C to +85°C (Industrial) Storage temperature range…………………………………. 62 .0V Operating Temperature Range (non condensing)…………0°C to +70°C (Commercial).-55°C to +125°C.Fig: pin diagram ABSOLUTE MAXIMUM RATINGS: Voltage range on any pin relative to ground…………………………..5V to +7. +260°C for 10 seconds.. Soldering temperature…………………………………….

the SQWE bit set to 1. Note: For more information on crystal selection and crystal layout considerations. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12. The SDA pin is open drain and requires an external pull-up resistor. 63 . SWQ/OUT: Square Wave/Output Driver. 8kHz. the SQW/OUT pin outputs one of four square-wave frequencies (1Hz. When enabled.25 x VBAT nominal. SDA is the data input/output for the I2C serial interface. 4kHz. refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. 32kHz).8.5pF. GND: Ground SDA: Serial Data Input/Output.768 kHz oscillator.2 Pin description: X1 X2: Connections for Standard 32. If a backup supply is not required. X1 is the input to the oscillator and can optionally be connected to an external 32. The nominal power-fail trip point (VPF) voltage at which access to the RTC and user RAM is denied is set by the internal circuitry as 1. UL recognized to ensure against reverse charging current when used with a lithium battery. SCL: Serial Clock Input. The output of the internal oscillator. X2 is floated if an external oscillator is connected to X1. VBAT: Backup Supply Input for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between the minimum and maximum limits for proper operation. SCL is the clock input for the I2C interface and is used to synchronize data movement on the serial interface.768kHz Quartz Crystal. A lithium battery with 48mAhr or greater will back up the DS1307 for more than 10 years in the absence of power at +25°C. Diodes in series between the battery and the VBAT pin may prevent proper operation. VBAT may be grounded.

VCC: Primary Power Supply.3 Block diagram: 64 .The SQW/OUT pin is open drain and requires an external pull-up resistor. the timekeeping function continues unaffected by the lower input voltage. SQW/OUT operates with either VCC or VBAT applied. read and writes are inhibited. 8. However. When voltage is applied within normal limits. the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VTP.

External circuit noise coupled into the oscillator circuit may result in the clock running fast.768 kHz crystal. Additional error will be added by crystal frequency drift caused by temperature shifts. 65 . The oscillator circuit does not require any external resistors or capacitors to operate. Figure 3 shows a functional schematic of the oscillator circuit. . Fig: oscillator ckt showing internal biasing network CLOCK ACCURACY: The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Table 1 specifies several crystal parameters for the external crystal.Oscillator: The DS1307 uses an external 32. the startup time is usually less than one second. If using a crystal with the specified characteristics.

When high. 66 . CLOCK AND CALENDAR: The time and calendar information is obtained by reading the appropriate register bytes. When cleared to 0. The RAM registers are located in address locations 08h to 3Fh.RTC AND RAM ADDRESS MAP: The RTC registers are located in address locations 00h to 07h. Bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. Bit 7 of Register 0 is the clock halt (CH) bit. The DS1307 can be run in either 12-hour or 24-hour mode.) Illogical time and date entries result in undefined operation. During a multibyte access. the end of RAM space.e. if 1 equals Sunday.. The day-ofweek registers increments at midnight. In the 24-hour mode. The hours value must be re-entered whenever the 12/24-hour mode bit is changed. the oscillator is disabled. and so on. then 2 equals Monday. when the address pointer reaches 3Fh. bit 5 is the second 10-hour bit (20 to 23 hours). the oscillator is enabled. Therefore. it is important to enable the oscillator (CH bit = 0) during initial configuration. Values that correspond to the day of week are user-defined but must be sequential (i. The time and calendar are set or initialized by writing the appropriate register bytes. Table 2 shows the RTC registers. When this bit is set to 1. In the 12-hour mode. it wraps around to location 00h. Please note that the initial power-on state of all registers is not defined. bit 5 is the AM/PM bit with logic high being PM. The contents of the time and calendar registers are in the BCD format. the 12-hour mode is selected. the beginning of the clock space.

Bits 1. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. . If SQWE = 0. 0: Rate Select (RS1.Fig: Timekeeper Registers The DS1307 control register is used to control the operation of the SQW/OUT pin. the logic level on the SQW/OUT pin is 1 if OUT = 1 and is 0 if OUT = 0. These bits control the frequency of the square-wave output when the square-wave output has been enabled. enables the oscillator output. This bit. Bit 7: Output Control (OUT). when set to logic 1. RS0). the clock registers update on the falling edge of the square wave. This bit controls the output level of the SQW/OUT pin when the square wave output is disabled. 67 . Bit 4: Square-Wave Enable (SQWE). With the square wave output set to 1Hz. The following table lists the square-wave frequencies that can be selected with the RS bits.

CHAPTER-9 SOFTWARE IMPLEMENTATION 68 .

Single-board Computers. you can write and test applications before target hardware is available. linker. UART. 69 . assembler. A/D Converter. Real-time Kernels. and memory options for you. Macro Assemblers. CAN. • Numerous example programs are included to help you get started with the most popular embedded 8051 devices. simply select the microcontroller you use from the Device Database and the µVision IDE sets all compiler. and PWM Modules) of your 8051 device. The industry-standard Keil C Compilers. SPI. and Emulators support all 8051 derivatives and help you get your projects completed on schedule. • . I/O Ports. with simulation.1 KEIL SOFTWARE: Keil development tools for the 8051 Microcontroller Architecture support every level of software developer from the professional applications engineer to the student just learning about embedded software development. • When starting a new project. Simulation helps you understand hardware configurations and avoids time wasted on setup problems. Debuggers. Additionally. D/A Converter.9. Interrupts. The Keil µVision Debugger accurately simulates on-chip peripherals (I²C.

Project Manager. Keil Cx51 is clearly the best choice for your 8051 project. Compiler extensions provide full access to all CPU resources and support up to 16MB memory. Efficient interrupt code and direct register bank control 4. With support for all 8051 devices and full compatibility with emulators and third party tools. Use of on-chip arithmetic units 13. Assembler. The Keil µVision® IDE fully integrates Cx51 Version 8 and provides control of the Compiler. Memory banking for code and variables beyond 64KB 8. Keil Cx51 generates code with the efficiency and speed of handoptimized assembly. New compiler and linker optimizations shrink programs into the smallest single-chip devices. Fast 32-bit IEEE floating-point math 3. Use of multiple data pointers 12. intelligent environment. Use of AJMP and ACALL instructions 7. Sophisticated syntax checking and detailed warnings 6. Common code block subroutine optimization 11. Global program wide register optimization 10.The Keil Cx51 ANSI C Compiler supports all classic and extended 8051 device variants. Support for all 8051 derivatives and variants 2. Generic and memory-specific pointers 14. Cx51 Compiler Highlights: 1. Reentrant functions and register bank independent code 15. Register parameters and dynamic register variables 9. and Debugger in a single. Extensive debug and source browse information 70 . Real-Time OS. Bit-addressable objects 5.

9.2 WAIT FOR READ OPERATION:

Example: This example shows a write of data values 0x05 and 0xE0 to address 0x00 and 0x01 of M24C08 Block3 respectively.

71

9.3 Wait for Write Operation:
Before starting any new operation with the EEPROM, we wait until the write operation is finished. The EEPROM will send the ACK bit if busy with the write operation, so the processor has to send the EEPROM address continuously until the EEPROM sends the ACK bit. To initiate the communication, the STR71x I2C has to generate a START condition and then send the M24C08 Address (with R/W bit cleared). After checking the correct status of the previous transmission, the Master writes, in the Data Register (DR), the address of the first byte. We want to read from the M24C08. The previous byte transmission check is done by looping on the BTF flag in the Status Register 1 (SR1). Then the STR71x I2C has to regenerate the START condition and then write the slave address in the Data Register (DR). This address must be the same as the address sent after the first START condition except that the least significant bit (R/W) must be set. Then a previous byte transmission check is done by looping on the ENDAD flag in Status Register 2 (SR2). After this, the STR71x I2C becomes a receiver for all bytes sent from the M24C08. To receive a new data byte, the previous byte reception has to be completed correctly. The byte reception check is done by looping on the BTF flag in Status Register 1 (SR1). This flag is cleared by reading the Data Register (DR). To close the communication, before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.

72

Begin Generate START Condition Send Slave Address((R/W)bit=0)

Send the EEPROM’s address to read from Re-Generate START

Send Slave Address((R/W)bit=1)

Wait until the byte is received NO 2nd last byte to receive

Disable ACK NO

Last byte to receive

Enable STOP condition generation

Receive next byte NO

End of reception

End 73

unsigned char ReadI2c(bit ACK_Bit). void start(void).h> #include<intrins. unsigned char ReadBYTE(unsigned int Addr).h> #include<stdio. void Initserial(void). rec(). void WriteI2c(unsigned char Data).h> #include<absacc. 74 . #define ACK 1 #define NO_ACK 0 unsigned char i.h> call(). unsigned char Data).EEPROM Programme: #include<reg51. void WriteBYTE(unsigned int Addr. void space(). void comp(unsigned char). void convert(unsigned char). void send(unsigned char). void stop(void). void enter(). void DelayMs(unsigned int count). void convert(unsigned char). void next(). void display(unsigned char[]).

while(TI==0). TI=0. void main(void) { unsigned char val[]="enter the values:/".loc.x++) { z=call(). unsigned char EData.sbit SDA=P0^2.x<5.y. loc+=0x0000. 75 . space(). y=0. y++. Initserial().z. } for(x=0. enter(). while(val[x]!='/') { SBUF=val[x]. DBYTE[0x20+y]=z. x++. unsigned char res[]="Address 0x00:/". } next().Data. unsigned char x. sbit SCL=P0^3.

//TI=1 . space().for(x=0. x++. while(res[x]!='/') { SBUF=res[x]. } y=0.EData).x<5. x=0. //printf("ADDRESS 0x00:\t").x++) { EData=ReadBYTE(0x0000+y). convert(EData). } //TI=1. 76 .Data). //TI=0. //printf("%02bX\t". loc++. DelayMs(10).x++) { loc+=0x0000. WriteBYTE(loc. TI=0. y++. Data=DBYTE[0x20+y]. while(TI==0). DelayMs(10). for(x=0.x<5.

SDA=0. } /*start I2c*/ void start(void) { SDA=1. //TI=0.y++. } next(). SCL=0. if(SDA==1) { if(SCL==1) { _nop_(). _nop_(). } } else CY=1. while(1). SCL=1. 77 . _nop_(). enter(). _nop_(). _nop_(). CY=0. _nop_().

_nop_(). } /* write I2C */ void WriteI2c(unsigned char Data) { for(i=0. _nop_(). _nop_(). _nop_(). SCL=1. _nop_(). _nop_(). } SCL=1.i<8. 78 .i++) { SDA=(Data&0x80)? 1:0.} /*stop I2c*/ void stop(void) { SDA=0. SCL=0. Data<<=1. SCL=1. _nop_(). SDA=1.

i<8.i++) { SCL=1. } if(ACK_Bit==1) SDA=0. else SDA=1. return Data. _nop_(). _nop_(). } /*Read I2c */ unsigned char ReadI2c(bit ACK_Bit) { unsigned char Data=0. SCL=0. _nop_(). 79 . } _nop_(). _nop_(). SCL=0. for(i=0. Data<<=1._nop_(). _nop_(). SCL=1. Data=(Data|SDA). SDA=1. _nop_(). SCL=0.

WriteI2c(0XA0). WriteI2c(Data). WriteI2c(0xA1)./*read 1 byte data from I2c*/ unsigned char ReadBYTE(unsigned int Addr) { unsigned char Data. Data=ReadI2c(NO_ACK). WriteI2c((unsigned char)Addr&0xFF). WriteI2c((unsigned char) (Addr>>8)&0XFF). start(). } /*data function*/ void DelayMs(unsigned int count) { 80 . stop(). WriteI2c((unsigned char) Addr & 0XFF). WriteI2c((unsigned char)(Addr>>8)&0xFF). } /*write 1byte to I@c*/ void WriteBYTE(unsigned int Addr. start(). return(Data). WriteI2c(0xA0). stop().unsigned char Data) { start().

81 . TH1=0XFD.z. y=SBUF. z=z^0X30. y=y^0X30.unsigned int i. while(count) { i=115. rec(). } /*call*/ call() { unsigned char y. TMOD=0X20. rec().a. TR1=1. y=y<<4. count--. while(i>0) i--. } } /*initialize serial port */ void Initserial(void) { SCON=0X50. z=SBUF.

while(TI==0). while(TI==0). SBUF=a. while(TI==0). } void enter() { SBUF=0X0D. TI=0.a=y|z. TI=0. TI=0. } void next() { SBUF=0X0A. a=SBUF. } rec() { unsigned char a. } void space() { SBUF=0X20. while(TI==0). RI=0. 82 . TI=0. return(a). while(RI==0).

} else { x=x+0x37. send(x). TI=0. while(TI==0). y=x. } void comp(unsigned char x) { if(x<=9) { x=x|0x30.} 83 . x=x&0xf0. x=x&0x0f. comp(x). send(x). comp(x). x=y.} void convert(unsigned char x) { unsigned char y. } } void send(unsigned char y) { SBUF=y. x=x>>4.

h> #include<stdio. char * Int2Month(unsigned char month). void WriteRTC(unsigned char * buff). {"Fri"}.h> void DelayMs(unsigned int count).RTC Programme: /**/#include<reg51. {"Sat"}}. void ReadRTC(unsigned char * buff). const unsigned char * DayStr[7] = {{"Sun"}. {"Thu"}. char * Int2Day(unsigned char day). {"Mon"}. void InitSerial(void). 1 0 84 .h> #include<intrins. #define ACK #define NO_ACK unsigned char i. {"Tue"}.h> #include<absacc. {"Wen"}.

minute. sbit SCL = P0^0.. {"Apr"}.. {"Oct"}. {"Nov"}. {"Dec"}}.. {"Aug"}. {"Mar"}. {"Feb"}. {"Jul"}. ReadRTC(&RTC_ARR[0]).. RTC_ARR[0] = RTC_ARR[0] & 0x7F. {"Jun"}.const unsigned char * MonthStr[12] ={{"Jan"}.year void main() { InitSerial(). // enable oscillator (bit 7=0) WriteRTC(&RTC_ARR[0]). // Buffer for second.. sbit SDA = P0^1. // connect to SDA pin (Data) // connect to SCL pin (Clock) unsigned char RTC_ARR[7]. // Set RTC 85 . {"Sep"}. {"May"}..

printf("Day : %s\r\n".Int2Day(RTC_ARR[3])). DelayMs(1000). temp=((bcd>>8)*100)|((bcd>>4)*10)|(bcd&0x0f). // clear Hyper terminal DelayMs(100)._nop_().RTC_ARR[6]). } } unsigned char BCD2HEX(unsigned int bcd) { unsigned char temp. 86 ._nop_().RTC_ARR[0]). SCL = 1. return temp.RTC_ARR[5]. printf("month: %s\r\n". printf("Data : %02bX-%02bX-%02bX\r\n". put char(0x0C).Int2Month(RTC_ARR[5])). } void Start(void) { SDA = 1.RTC_ARR[1].while(1) { ReadRTC(&RTC_ARR[0]). TI=0.RTC_ARR[2]. TI=1. printf("Time%02bX:%02bX:%02bX\r\n". _nop_(). SDA = 0.RTC_ARR[4]. _nop_().

i++) { SDA = (Data & 0x80) ? 1:0. _nop_()._nop_(). } void WriteI2C(unsigned char Data) { for (i=0. SCL=1. _nop_().SCL=0. Data<<=1._nop_().SCL = 0. _nop_(). SDA = 1. _nop_()._nop_()._nop_(). SCL = 1. } SCL = 1.i<8. } void Stop(void) { SDA = 0. SCL = 0. } 87 .

} void ReadRTC(unsigned char * buff) { 88 . for (i=0. SDA = 1. _nop_(). SCL = 1.i<8. _nop_(). Data = (Data | SDA). // Send ACK else SDA = 1. // Send NO ACK _nop_().unsigned char ReadI2C(bit ACK_Bit) { unsigned char Data=0._nop_(). } if (ACK_Bit == 1) SDA = 0. return Data. SCL = 0. SCL = 0.i++) { SCL = 1._nop_(). Data<<= 1.

} // Second // Minute // hour // Day // date // month *(buff+6)=ReadI2C(NO_ACK).Start(). *(buff+0)=ReadI2C(ACK). WriteI2C(*(buff+4)). WriteI2C(0xD0). WriteI2C(0xD0). WriteI2C(*(buff+2)). *(buff+5)=ReadI2C(ACK). WriteI2C(*(buff+0)). *(buff+1)=ReadI2C(ACK). // year void WriteRTC(unsigned char *buff) { Start(). WriteI2C(*(buff+1)). Stop(). *(buff+4)=ReadI2C(ACK). WriteI2C(*(buff+5)). WriteI2C(0x00). WriteI2C(0x00). WriteI2C(0xD1). *(buff+2)=ReadI2C(ACK). *(buff+3)=ReadI2C(ACK). WriteI2C(*(buff+3)). 89 . Start().

} char * Int2Day(unsigned char day) { return DayStr[day-1]. TR1 } = 1. TH1 = 0xFD.WriteI2C(*(buff+6)).05592MHZ) // TH1 // Timer 1 on 90 . while(count) { i = 115. while(i>0) i--. } void DelayMs(unsigned int count) { unsigned int i. } } void InitSerial(void) { SCON = 0x50. } char * Int2Month(unsigned char month) { return MonthStr[BCD2HEX(month)-1]. count--. // setup serial port control TMOD = 0x20. Stop(). // hardware (9600 BAUD @11.

high-accuracy weather monitoring system. a comparison on the features of different types of monitoring systems has been carried out and it shows that the proposed system is of better choice in terms of cost. portability.Conclusion: A framework has been presented that incorporates the uses of sensors in developing a low-cost. 91 . The proposed system has been tested through extensive experiments and the results have proven the accuracy and reliability of the proposed system. memory capacity and logging interval-setting capability. using analogue and digital components. Besides.

. In Proceedings of Transducers 95 (2). J. Jun. 1994. O. Plath. Cannes.REFERENCES Bu. and S. Vandahl. p. Kim. T. In Proceedings of IEEE Ultrasonics Symposium. F. T. M. Luck.. S. C. Siliconbased thermal comfort sensing device. W. Buff. Sweden. Y. T. Muller. Shim. H. p. November 1994.Stockholm. Remote sensor system using passive SAW sensors. U. Eurosensors IX. 1995. Y.104–107. 92 . Kim. Y. Schmeckebier. Rusko. and F.585-588.