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Design of Current Limiting Circuit in Low Dropout Linear Voltage Regulator

LIN Chuan, FENG Quan-yuan
Microelectronics Institute, Southwest Jiaotong University, Chengdu, 610031, China Email: lin_langai@163.com; TEL: 028-86466365, 028-86466028
Abstract- A current limiting circuit applied in low dropout linear voltage regulator is designed and simulated. It can limit the maximum output current and the output short current of the regulator within 320mA and 30mA, respectively, and well realize the purpose of overcurrent protection. Prototype of the circuit can be fabricated using the 0.5µm CMOS process. Index Terms- Current Limiting; Foldback; LDO; Linear Voltage Regulator

1.

When overcurrent hasn’t taken place, the voltage regulator should regulate the output voltage UO normally, and the current limiting circuit should have little effect on it.

2.

A current limiting circuit should first include output current detecting devices or block to detect if output current IO has exceeded the maximum rated value.

3.

After the current limiting circuit starts up, it should cut off the negative feedback loop of the regulator. Then the regulator cannot regulate the output voltage any more.

1. INTRODUCTION Nowadays, LDO (Low Drop-out) linear voltage regulator has been widely used in portable equipments. In order to prevent damage to the IC when an overload is placed or the output of the regulator is shorted, current limiting circuits are usually included in LDO linear voltage regulator [1~3]. So far, there are few papers published about the design of current limiting circuit, especially foldback current limiting circuits in LDO linear voltage regulator. It is, however, discussed in many patents [4~5]. A current limiting circuit used in LDO linear voltage regulator is designed and simulated in this paper. This circuit can be fabricated using 0.5µm CMOS process and can be easily adjusted. The simulation results show that the circuit can well realize the purpose of overcurrent protection. It can limit the maximum rated output current and the output short current within 320mA and 30mA, respectively.
2. DESIGN OF CURRENT LIMITING CIRCUIT 2.1

4.

After foldback current limiting circuit starts up, IO will decrease as UO decreases. As the output is shorted, IO will be limited to a value much less than the maximum rated value. Besides, a good current limiting circuit should take some

other factors into consideration, such as: low quiescent current and power consumption, few devices, low cost, and so on. 2.2 Design Principle of Current Limiting Circuit The current limiting circuit presented in the paper is showed in Fig. 1. It comprises output current sampling circuit, constant current limiting circuit and foldback current limiting circuit. Signals VB1 and VB2 are generated by the self-biasing circuit of the error amplifier (We only give the second stage of the amplifier in Fig. 1). The potential of VB2 is constant, and VSG_MP3=VDD-VB1 holds constant as well. MN1 and MP2 make up of the second stage of the error amplifier. AO1 is its input as well as the output of the first stage and AMP_OUT is its output as well as the output of the error amplifier. MPW is pass element. LCE is the enable control signal. When it is at high potential, MP1 is off and the circuit works normally.

Design Requirement of Current Limiting Circuit A current limiting circuit used in LDO linear voltage

regulator should at least meet the requirements as follows:

This work was supported by National Science Foundation of P. R. China. Grant No. 60371017

0-7803-9433-X/05/$20.00 ©2005 IEEE.

APMC2005 Proceedings

2. which lifts VAMP_OUT up and hence reduces output current IO. If the W/L rate of MP7 is designed to be quite large. When the output current exceeds the maximal rated value.1 Output Current Sampling Circuit Output current IO is sampled by MP5. INVO is at relatively low potential. If MP6 is on. INVO is at high potential and MP4 is off. As load resistor 2 I S LMN 3 1/ 2 ) + Vth _ MN 3 + I S R2 − U O µ C oxW MN 3 (2) k1 = 2 k1 LMN 3 1/ 2 IS (W / L ) M P 5 ) = . 2.2.2 Constant Current Limiting Circuit Suppose when the output current is at its maximal rated value. whose source and gate are connected with source and gate of the pass element. VAMP_OUT will be lifted up. It can be simply expressed as: . So IO is limited to a constant value. So IO is a degressive function of VGS_MN4 as long as MN4 and MP6 are on. IMN4 and VSG_MP6= IMN4R1 will increase as well. we can obtain a small current IS which is proportional to IO. so constant current limiting circuit has no control on the gate of the pass element. In addition. and MP2 is cut off.3 Foldback Current Limiting Circuit According to the relationship of output current ID and VGS of a MOS transistor. respectively. and MP4 is on. which causes IO to decrease. VG_MN2< V0G_MN2. Thus the output of the first stage of the amplifier AO1 is at high potential. When output current is under maximal rated value. The relation of the sampling current IS and IO is as follows: decreases. MN2 and MP3 compose an inverting amplifier.2. UO drops. respectively. we have VD_MP5=VSG_MP7+VOUT. the corresponding VG_MN2 is V0G_MN2 and the sampling current is I0S. then VSG_MP7 ≈ Vth_MP7, less difference of VD_MP5 and VOUT will and reduce the effect of channel modulation and enable MP5 to sample output current accurately.2. if we make the rate of W/L of MP5 very small. so the negative feedback in the linear voltage regulator is cut off and the regulator cannot regulate the output normally any longer. k2 = ( µ C oxWMN 3 I0 (W / L ) M P W (3) (4) and we get: VGS _ MN 4 = k2 IO1/ 2 + Vth _ MN 3 + k1R2 IO − U O VGS _ MN 4 = k2 IO1/ 2 + Vth _ MN 3 + k1 R2 IO − RL IO If MN4 is on. we have: (1) I S (W / L ) MP 5 = I O (W / L ) MPW VGS _ MN 4 = VGS _ MN 3 + I S R2 − U O =( Make Therefore. IS> I0S. whose input and output are the gate of MN2 and INVO. as VGS_MN4 increases. and the sampling voltage fed from the output to the error amplifier is less than the reference voltage any more. At this time. sampling current IS< I0S.Fig 1 A current limiting circuit in a LDO linear voltage regulator 2. VG_MN2> V0G_MN2.

UO will also decrease. The current limiting circuit comprises only 8 MOS transistor and 2 resistors. R2. the maximal rated output current can be adjusted. we know that MN4 will become on when UO drops to some value.I O = f (VSG _ MP 6 ) = f o g (VGS _ MN 4 ) = h(VGS _ MN 4 ) (5) When output current is under its maximal rated value. And at last. for which the regulated output voltage is 1. we can see that when overcurrent takes place. Few devices and low cost. The circuit is easy to adjust. SIMULATION RESULTS AND DISCUSSION The designed current limiting circuit is applied in a LDO linear voltage regulator. MP6 and R1. When used in a LDO linear regulator. As UO drops to about 1. MN4. 2. the circuit has some extra advantages as follows: 1. constant current limiting circuit works first and limits IO to a constant value. constant current limiting circuit works first and limits IO to 320mA. the maximal rated value of IO is 320mA and the output short current is 30mA. which causes IO to decrease. Lee. VG_MP6=VDD. The short output current is 30mA. 3 that Iq is less than 8. according to equation (4). then foldback current limiting circuit starts to work and lifts VAMP_OUT up.4V. 2 shows the relationship of UO and IO in LDO linear regulator. VGS_MN4 will increase and cause IO to decrease. If RL decreases further. 2. so we achieve the purpose of foldback current limiting. As load RL decreases. Besides. 3 shows the relationship of quiescent current Iq of the current limiting circuit and output current IO. Fig. VGS_MN4< VTH_MN4.” Texas Instruments Application Report,Oct. which can reduce the size of the chip and hence reduce the cost.8V. By adjusting W/L rate of MN2. MN4 is off. REFERENCES [1] Bang S. the value of IO is minimal. Fig. Then UO drops as RL decreases. We can see from Fig. The simulation results by HSPICE are showed in Fig. 3. 2 and Fig. CONCLUSION Fig. foldback current limiting circuit starts up and reduces IO further. When the output is shorted. The circuit has only two current limbs which are both proportional to sampling current IS. From Fig. 4. 1999 . so MP6 is off and foldback current limiting circuit has no control on the gate of the pass element. IMN4=0. From equation (3). Then INVO is at high potential and MP4 is off again. In a word. “Understanding the Terms and Definitions of LDO Voltage Regulators. When overcurrent takes place. MP6 is on. output short current can be easily adjusted. equation (4) and (5) will be in balance. MN3 and MP3. IMN4 will increase further. So very low Iq which is proportional to IO is achieved. and as UO drops further. by adjusting W/L rate of MN3. 2 The relationship of output voltage and output current The circuit designed in the paper has solved some critical techniques in current limiting circuit. 3 The relationship of quiescent current and output current Fig. 3. it can well realize the purpose of overcurrent protection. IO will decrease as RL and UO decreases.5µA when IO is less than 200mA. When VSG_MP6= IMN4R1> VTH_MP6.

1999 [3] Chester Simpson. 2002 [5] Robert M.[2] Bang S. “Booster circuit for foldback current limited power supplies. Oct. Lee. “Technical Review of Low Dropout Voltage Regulator Operation and Performance.” United States Patent.” Texas Instruments Application Report,Aug. 1999 [4] Wen Li Luo. 1999 . Nov. Paterno.30. 6466422 B2. “Linear and Switching Voltage Regulator Fundamentals.” United States Patent.” National Semiconductor Application Note.15. “Current Limit Protection Circuit for a Voltage Regulator. 5994884.