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NoC – Network on Chip



What are SoC’s and NoC’s?
According to Wikipedia: --“System-on-chip refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip).” --“Network-on-a-chip (NoC) is a new paradigm for Systemon-Chip (SoC) design. The NoC solution brings a networking method to on-chip communications and claims roughly a threefold performance increase over conventional bus systems.”

•Design with IP reuse is mandatory . DSPs.System on Chip (SoC) •With many tens of million transistors available on a single chip. the System-onChip (SOC) has become a reality. Integrated processor cores. on-chip memories. etc…are commonly in use. . IP-blocks.

Traditional SoC nightmare  Variety of dedicated interfaces  Design and verification complexity  Unpredictable performance  Many underutilized wires DMA Control signals CPU DSP CPU Bus A B C IO Bridge Peripheral Bus IO IO .

Evolution of on-chip communication .

Network on Chip: A paradigm Shift in VLSI From: Dedicated signal wires To: Shared network s s Module s s Modul e s Modul e s s PointTo-point Link s Computing Module s Network switch .

via switches • Efficient sharing of wires • Parallelism .NoC essential s s Module s s Modul e s Modul e s s s s • Communication by packets of bits • Routing of packets through several hops.

power. noise.Critical problems addressed by NoC 1) Global interconnect design problem: delay. scalability. reliability 2) System integration productivity problem 3) Chip Multi Processors (key to power-efficient computing) .

From buses to networks .

Regular Network on Chip PE PE PE PE PE PE Router PE PE PE PE .

Generic On-Chip Router .

Data abstractions .

fat tree. repeaters.g. transaction Routing Static/dynamic. signaling. end-to-end flow control Flow control (handshake) Handling of contention Correction of transmission errors Wires. ring. best-effort Congestion control.Layers of abstraction in network modeling  Software layers  Application. receivers.. mesh. distributed/source. drivers. Addressing Logical/physical. flow. circuits.. source/destination. deadlock avoidance Quality of Service e. torus. OS Network topology e.g.… Switching Circuit / packet switching etc. guaranteed-throughput.  Network & transport layers        Data link layer     Physical layer  . crossbar.

OSI Layered Model • Open System Interconnect (OSI) Model is general purpose network model • NoC employs at present Physical layer. Data Link Layer and Network Layer in detail .

Typical NoC design flow Place Modules Determine routing and adjust link capacities .

NoC Topology The connection map between PEs  Adopted from large-scale networks and parallel computing  Topology classifications:   Direct topologies Indirect topologies .

Direct topologies  Each switch (SW) connected to a single PE  As the # of nodes in the system increases. the total bandwidth also increases PE PE SW SW 1 PE is connected to only a single SW PE SW SW PE .

Indirect topologies A set of PEs are connected to a switch (router) Fat tree topology SW Butterfly topology SW SW SW SW SW SW PE PE PE PE PE PE PE PE .

of Aizu 19 . Univ.NoC Switching Strategies Switching determines how flits and packets flows through routers in the network  There are two basic modes: Circuit switching  Packet switching  Adaptive Systems Laboratory.

but rather data     and information about the data. Circuit-switched networks require no overhead for packetization.Circuit Switching  Network resources (channels) are reserved before a packet is sent  Entire path must be reserved first  The packets do not contain routing information. packet header processing or packet buffering Once circuit is setup. router latency and control overheads are very low Very poor use of channel bandwidth if lots of short packets must be sent to many different destinations More commonly seen in embedded SoC applications where traffic patterns may be static and involve streaming large amounts of data between different IP blocks .

 Packet is sent from one router to the next only if the receiving router has buffer space for entire packet  Buffer size in the router is at least equal to the size Forward packet by packet of a packet Buffer Buffer Switch Buffer Switch packet Switch Store and Forward switching data flit header flit . We then arbitrate for access to network resources dynamically.Packet Switching Store and Forward (SAF)  We can aim to make better use of channel resources by buffering packets.

(2000) “Network on chip: An architecture for billion transistor era”  De Micheli and Benini (2002) “Networks on chip: A new paradigm for systems on chip design” .Bibliography  Wikipedia – System on Chip  Wikipedia – Network on Chip  Guerrier and Greiner (2000) “A generic architecture for on- chip packet-switched interconnections”  Hemani et al.

Thank You .