Microprocessor based System Design

Ravi S Gupta

• • • • • • • • • • • • • • • • • Goals of the Course Historical Perspective - Microprocessors The Technology Aspect: Moore’s Law Inside a Microprocessor Processor system architecture Computer Classification Advantages of Microprocessor based system design Disadvantages of Microprocessor based system design Microcontroller Digital Signal Processor Functional and Architecture description of 8085 Pin description of 8085 Memory Interfacing Addressing Modes in 8085 Instruction Set of 8085 Interrupts of 8085 Timing Diagram of 8085

Goals and Objectives
In this course, you will: Learn how the hardware (HW) and software (SW) components of a microprocessor-based system work together to implement digital systems. Learn both HW and SW aspects of integrating digital devices (memory, I/O interfaces, etc.) into microprocessor systems. Get practical hands-on experience in system design and assembly language programming.

operation principles.Goals and Objectives In the classroom lectures. their internal building blocks. you will learn more about the hardware architecture aspects of microprocessors. interfacing with other digital systems etc… In the laboratory sessions. . you will learn more about the machine code and assembly language programming of microprocessors. and implementation of digital systems using these devices.

Microprocessors are found almost everywhere .




Prior to the 4004. But it was amazing that everything was on one chip.also known as a CPU or central processing unit -. The 4004 powered one of the first portable electronic calculators.all it could do was add and subtract.Microprocessor History A microprocessor -. and it could only do that 4 bits at a time. engineers built computers either from collections of chips or from discrete components (transistors).is a complete computation engine that is fabricated on a single chip. The first microprocessor was the Intel 4004. . The 4004 was not very powerful -. introduced in 1971.

a complete 8-bit computer on one chip.000 times faster! . All of these microprocessors are made by Intel and all of them are improvements on the basic design of the 8088. introduced in 1979 and incorporated into the IBM PC (which first appeared around 1982). The Pentium 4 can execute any piece of code that ran on the original 8088. you know that the PC market moved from the 8088 to the 80286 to the 80386 to the 80486 to the Pentium to the Pentium II to the Pentium III to the Pentium 4. but it does it about 5. The first microprocessor to make a real splash in the market was the Intel 8088. introduced in 1974. If you are familiar with the PC market and its history.The first microprocessor to make it into a home computer was the Intel 8080.

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. of the smallest wire on the chip. while a 32-bit ALU can manipulate 32bit numbers.• The date is the year that the processor was first introduced. For comparison. An 8-bit ALU can add/subtract/multiply/etc. • Transistors is the number of transistors on the chip. As the feature size on the chip goes down. You can see that the number of transistors on a single chip has risen steadily over the years. • MIPS stands for "millions of instructions per second" and is a rough measure of the performance of a CPU. a human hair is 100 microns thick. • Clock speed is the maximum rate that the chip can be clocked at. two 8-bit numbers. in microns. • Microns is the width. the number of transistors rises. • Data Width is the width of the ALU.



etc. input and output devices to it. • The popular input devices are keyboard and floppy disk and the output devices are printer. To perform a function or useful task we have to form a system by using microprocessor as a CPU and interfacing memory. LED/LCD displays. input device. . CRT monitor. output device and interfacing devices are called peripherals.Inside a Microprocessor • The microprocessor is a semiconductor device (Integrated Circuit) manufactured by the VLSI (Very Large Scale Integration) technique. output device and interfacing devices. • The Microprocessor based system (single board microcomputer) consists of microprocessor as CPU. A system designed using a microprocessor as its CPU is called a microcomputer. register arrays and control circuit on a single chip. input device. It includes the ALU. The memories. semiconductor memories like EPROM and RAM.

CPU ALU Input CU Output Memory CPU-> Central Processing Unit ALU -> Arithmetic and Logical Unit CU -> Control Unit Block Diagram of a computer with the Microprocessor as CPU .

Microprocessor based system .

Processor System Architecture The typical processor system consists of:  CPU (central processing unit)  ALU (arithmetic-logic unit)  Control Logic  Registers. etc…  Memory  Input / Output interfaces Interconnections between these units:  Address Bus  Data Bus  Control Bus .

unidirectional – data bus: the data value being communicated. where instructions are executed – High-level language: a = b + c – Assembly language: add r1 r2 r3 – Machine language: 0001001010111010101 .Bus and CPU Bus: A shared group of wires used for communicating signals among devices. – address bus: the device and the location within the device that is being accessed. like Reset the device CPU: Core of the processor. bidirectional – control bus: describes the action on the address and data buses.

They are used to store data temporarily during the execution of a program. REGISTER ARRAY and CONTROL UNIT. It performs arithmetic and logic operations. • ALU (Arithmetic and Logical Unit): Computing functions are performed on data in this area of microprocessor. • REGISTER ARRAY: It is a group of various registers. .Central Processing Unit Microprocessor consists of ALU. • CONTROL UNIT: It controls the flow of data between the microprocessor and peripherals (I/0 ports and memory) by sending proper timing and control signals.

Memory and I/O • Memory: Where instructions (programs) and data are stored. – The I/P device enters data and instructions under the control of a program such as a monitor program. device control logic. – stores binary information. controller or adapter) hardware connects actual device to bus – The CPU views the I/O device registers just like memory that can be accessed over the bus. . etc. – provides the instructions and data to the microprocessor on request. called instructions and data.a. – Device interface (a. I/O registers are connected to external wires. – stores results and data for the microprocessor. – The O/P device accepts data from the microprocessor as specified in a program.k. • I/O devices: Enable system to interact with the world. However.

Mini computers are used in research. Their word length is typically 64-bits. etc. The storage capacity and speed requirements of microcomputers are moderate. graphic applications. scientific calculations etc. data processing.Computer classification Computers are divided into three categories as per the superiority and number of microprocessors used. . • Mainframe computers are designed to work at very high speed and they have very high storage capacity. • Mini computers are having more storage capacity and more speed than micro computers. These are: • A microcomputer is a small computer containing only a single central processing unit (CPU). These are used for research. data processing. Their word length varies between 8 and 32 bits and used in small industrial and process control systems.

• Automation of industrial processes and office administration. there is flexibility to alter the system by changing the software alone. compact in size and cost less. Also it is more reliable. • Intelligence has been brought to systems.Advantages of Microprocessor based system • Computational/processing speed is high. • Since the devices are programmable. • Operation and maintenance are easier. • Less number of components. .

. • The analog signals cannot be processed directly and digitizing the analog signals introduces errors. • The speed of execution is slow and so real time applications are not possible.Disadvantages of Microprocessor based System • It has limitations on the size of data. • The applications are limited by the physical address space. • Most of the microprocessors does not support floating point operations.

• Sometimes microcontroller is called single chip micro-computer.Microcontrollers • Integration of Microprocessor along with I/O ports and minimum memory in a single package is named as microcontroller. ROM/RAM Memory Micro Processor I/O Ports Peripheral Timer . • Peripherals like programmable timer is also included in a single package.

generally in real time. • Signal – a variable parameter by which information is conveyed through an electronic circuit.Digital Signal Processors • A Digital Signal Processor is a special-purpose CPU (Central Processing Unit) that provides ultrafast instruction sequences. such as shift and add. and multiply and add. • Digital – operating by the use of discrete signals to represent data in the form of numbers. • A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing. which are commonly used in math-intensive signal processing applications. . • Processing – to perform operations on data according to programmed instructions.

. – Only parallel processing. no multitasking.• Characteristics of Digital Signal Processors: – Separate program and data memories. – analog input-->ADC-->DSP-->DAC--> analog output. – Takes digital data from ADC (Analog-Digital Converter) and passes out data which is finally output by converting into analog by DAC (Digital-Analog Converter). – The ability to act as a direct memory access device if in a host environment.

• The Microprocessor can be represented in terms of its: – Hardware Model. .8085 Model •A model is a conceptual representation of a real object. and – Programming Model.

8085 Hardware Model Accumulator Register Array ALU 8-bit Data Bus Memory Pointer Reg Control Signals 16-bit Address Bus Flags Instruction Decoder Timing and Control .

8085 Programming Model .

The programming model consists of following components: • Arithmetic logic unit and Registers • Accumulator • Flags • Program Counter • Stack Pointer .

temporary register.ARITHMETIC LOGIC UNIT (ALU) • The arithmetic logic unit is the heart of the microprocessor. OR. • It is used to perform certain arithmetic operations such as addition. arithmetic and logic circuits and five flags. • ALU is used in computing function. . EX-OR etc. and the result is stored in the accumulator and the flags are set or reset according to the result of the operation. • ALU includes the accumulator. subtraction etc and logical operations such as AND.

Registers Registers are used to store data temporarily during the execution of a program. Different types of registers are: • General purpose Registers • Accumulator • Program Counter (pc) • Stack pointer (sp) • Flag Register .

DE. • These registers are programmable meaning that a programmer can use them to load or transfer data from the registers by using instructions. E. and HL.General Purpose Register • There are six 8 bit general purpose register labeled as B. . H & L. D. • These registers can be used as a single 8 bit registers or in pairs like BC. C.

and. Subtraction etc.ACCUMULATOR REGISTER • It is an 8 bit register. • It is a part of ALU. • It is used to store 8-bit data and to perform arithmetic and logic operations. • Accumulator is identified as Register A. or. . ex-or etc) • The result of an operation is stored in the accumulator. (Arithmetic operations such as addition. logical operations.

• This register is a memory pointer. to point to the next memory location.PROGRAM COUNTER (PC) • It is a 16 bit register microprocessor uses this register for sequencing the execution of instructions. • The function of the program counter is to point to the memory address from which the next byte is to be fetched • When a byte (machine code) is being fetched the program counter is incremented by one. .

• The beginning of the stack is defined by loading a 16-bit address in the stack pointer register.STACK POINTER (SP) • It is a 16 bit register and it is used as a memory pointer. • It points to a memory location in user memory called stack. .

• Flag registers are used in the decision making process of the microprocessor. • The microprocessor uses them to test for data conditions. .FLAG REGISTER • The ALU has 5 flip flops that are set or reset according to data conditions in the accumulator and other registers. • It is a single bit register which stores 8 bit register so that the programmer can examine these flags for data conditions.

.Basically. if odd number of 1‟s then the flag is reset. AUXILLARY FLAG: If an arithmetic operation produces carry out from the lower order 4bits then the flag is set. otherwise the flag is reset. ZERO FLAG: The zero flag is set if the ALU operation results in zero and reset if the resultant operation is not zero. if the resultant operation is plus then the flag is reset. PARITY FLAG: After the arithmetic and logical operation if the result as even number of 1‟s then the flag is set. there are five types of flags: • SIGN FLAG • ZERO FLAG • CARRY FLAG • PARITY FLAG • AUXILLARY FLAG SIGN FLAG: After the execution of arithmetic or logical operation. CARRY FLAG: If the carry is generated from MSB (most significant bit) in a arithmetic operation then carry flag is set otherwise reset. if the resultant operation is minus then the flag is set.

Problem on Carry flag: Hexadecimal Addition: AA+7C Hexadecimal Addition: 3A+7C .

Problem on Zero flag: Hexadecimal Addition: 84+7C Hexadecimal Addition: 3A+7C .

Problem on Parity flag: Hexadecimal Addition: 3A+78 Hexadecimal Addition: 3A+7C .

Problem on Auxillary-Carry flag: Hexadecimal Addition: 3A+7C .

TIMING AND CONTROL UNIT • This unit synchronizes all the microprocessor operations with the clock and generates the control signals necessary for communication between the microprocessor and peripherals. .

• The decoder decodes the instruction and establishes the sequence of events to follow. it is loaded in the instruction register.INSTRUCTION REGISTER AND DECODER • The instruction register and the decoder are part of the ALU. • When an instruction register is fetched from memory. .

8085 Architecture The internal logic design of a µP known as its architecture reveals what exactly is happening and how different operations are executed inside the micro processing unit (MPU). .

– It is manufactured with N-MOS technology. – The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7. – It supports external interrupt request. – Data bus is a group of 8 lines D0 – D7.Salient features The salient features of 8085 µp are: – It is a 8 bit microprocessor. DE. – Six 8-bit general purpose register arranged in pairs: BC. – A 16 bit stack pointer (SP). – It requires a signal +5V power supply and operates at 3. – It is enclosed with 40 pins DIP (Dual in line package).2 MHZ single phase clock. . – It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory locations through A0-A15. HL. – A 16 bit program counter (PC).

Busses Accumulator Temp Register ALU & Flags CPU Registers Addr,Data Buffer Timing Unit



Instruction Register & Decoder Interrupt Control Serial Control

Address Buffer and Address/Data Buffer: • These buffers are used to increase the driving capacity of address/data busses. • In the simplest form these form emitter follower with large current amplification. Timing and Control Unit: • It includes an on chip oscillator and a control sequencer. • The control sequencer is micro programmed; it has a ROM that stores all the micro routines needed for executing the instructions.

Pin Descriptions of 8085

. These are: • (1) Power supply and frequency signals • (2) Data and Address buses • (3) Control bus • (4) Interrupt signals • (5) Serial I/O signals • (6) DMA signals • (7) Reset signals.The signals of 8085 can be classified into seven groups according to their functions.

Pin Descriptions of 8085 address (8 bits) .

Pin Descriptions of 8085 address and data (8 bits) dual .use pins !! .

X2 (Input)) Crystal or R-C / L-C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. . The input frequency is divided by 2 to give the internal operating frequency.• Pins 1 and 2 (X1.

The signal is synchronized to the processor clock. .  Can be used as a system RESET. SIM instruction affects this pin. SID (Input)  Serial input data line: RIM instruction affects this pin. SOD (output)  Serial output data line. Q) What is the state of registers when they are reset? • Pin 4 and 5 (SOD and SID) It consists of a set of SIPO and PISO flip-flops.• Pin 3 (RESET OUT (Output))  Indicates CPU is being reset.

• Pins 6 to 11 (Interrupts)  These pins form the interrupt control section.5 and INTR and 1 acknowledgement INTA.  This bus is unidirectional one. RST 6. RST 7. • Pins 29 and 33 (S0 & S1)  Data Bus Status. • Pins 21 to 28 (A8-A15)  These pins form the higher order address bus. There are 5 hardware interrupt request TRAP. TRAP has got the highest priority while INTR has least.5. These interrupts are serviced on the order of priority. • Pins 12 to 19 (AD0-AD7)  These pins form the lower order address bus multiplexed with the data bus to form Address/Data bus AD0-AD7. Encoded status of the bus cycle: .5. RST 5.  This bus is bidirectional one.

32 and 34 (WR. then data transfer takes place and if not. • Pins 36 and 37 (RESETIN and CLKOUT)  A low signal on pin 36 resets the PC. the device sends back a low on READY pin. read (load) either from memory or from I/O device.  Pin 37 is the system clock. If the device is ready. • Pin 30 (ALE (Output)) Address Latch Enable: This is an important pin which supports multiplexing of A0-A7 with D0-D7. IO/M)  These pins are to write (store).• Pins 31. . IR etc and sends a reset signal (RESET OUT) to peripherals through Pin 3.  As an example. • Pin 35 (READY)  This is another important pin on 8085. if IO/M = 0.RD. At first the uP asks the device to get ready. RD=0 & WR = 1 means it is memory read operation. RD & WR both together cannot be activated. It permits the use of cheaper (slow) peripherals. Is connected to pin 37 which can be used to synchronize all the peripherals with the uP. The signal generated by the on-chip oscillator after passing through divide by 2 flip-flop. thus enabling the use of slower devices (speed matching).  If READY = 0 the processor generates WAIT states till it gets ready.

.Generation of Control Signals • The figure below shows the generation of active low MEMR and MEMW signals. along with active low IOR and IOW signals.

. The DMA controller issues a signal HOLD to CPU requesting the uP for DMA. uP regains the bus control.• Pins 38 and 39 (HLDA and HOLD) These 2 pins form the DMA (Direct Memory Access) section. it is wise to bypass CPU. CPU acknowledges back by issuing HLDA and gives control of busses to DMA controller. the intervention of CPU reduces the speed of operation. In order to transfer huge amounts of data. Once DMA is completed. HLDA I/O Device HOLD uP/CPU DMA Memory • Pins 20 and 40  Vss Ground Reference.  Vcc +5 volt supply. In certain situations.

Demultiplexing the bus: AD0-AD7 16 Demultiplexing the address / data bus 8 .

The ALE signal is connected to the enable (G) pin of Latch and the o/p control (OC) is connected to Gnd.• The arrangement uses a Latch 74LS373 and ALE signal from 8085 for the purpose. . for the next of the period the latch will be disabled as ALE (G) remains low. The data bus now carries the data D0-D7. • During T1 of every M/C cycle ALE goes high and remains low for the remaining portion of that M/C cycle. In other words till the next ALE (in next M/C cycle) the previous low order address remains on latch. the latch follows its i/p (A0 – A7). Thus during T1 of each and every M/C cycle. The bus AD0AD7 is connected to the input of latch. However.

. 4.768 bits • 12 address input signals • 8 input/output data signals • Memory access – r/w: selects read or write – enable: read or write only when asserted m × n memory … m words … n bits per word memory external view r/w enable 2k × n read and write memory A0 Ak-1 … … Qn-1 Q0 .Memory: basic concepts • Stores large number of bits – m x n: m words of n bits each – k = Log2(m) address input signals – or m = 2^k words – e.096 x 8 memory: • 32.g.

by a processor in an embedded system • Traditionally written to. “programmed”. before inserting to embedded system • Uses – Store software program for generalpurpose processor • program instructions can be one or more ROM words – Store constant data needed by system – Implement combinational circuit External view enable A0 … 2k × n ROM Ak-1 … Qn-1 Q0 .ROM: “Read-Only” Memory • Nonvolatile memory • Can be read from but not written to.

Example: 8 x 4 ROM • • • • Horizontal lines = words Vertical lines = data Lines connected only at circles Decoder sets word 2’s line to 1 if address input is 010 • Data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line • Word 2 is not connected with data lines Q2 and Q0 • Output is 1010 Internal view 8 × 4 ROM word 0 enable 3×8 decoder word 1 word 2 word line A0 A1 A2 data line programmable connection wired-OR Q3 Q2 Q1 Q0 .

Implementing combinational function • Any combinational circuit of n functions of same k variables can be done with 2^k x n ROM Truth table Inputs (address) a b c 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Outputs y z 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 8×2 ROM 0 0 0 1 1 1 1 1 y 0 1 1 0 0 1 1 1 z word 0 word 1 enable c b a word 7 .

each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read external view r/w enable 2k × n read and write memory A0 Ak-1 … … Qn-1 Q0 internal view I3 I2 I1 I0 4×4 RAM enable 2×4 decoder A0 A1 Memory cell rd/wr To every cell Q3 Q2 Q1 Q0 .RAM: “Random-access” memory • • • Typically volatile memory – bits are not held without power supply Read and written to easily by embedded system during execution Internal structure more complex than ROM – a word consists of several memory cells. each storing 1 bit – each input and output data line connects to each cell in its column – rd/wr connected to every cell – when row is enabled by decoder.

compose several smaller memories into one larger memory – Connect side-by-side to increase width of words – Connect top to bottom to increase number of words • added high-order address line selects smaller memory containing desired word using a decoder – Combine techniques to increase number and width of words 2m × 3n ROM enable Increase number of words 2m+1 × n ROM 2m × n ROM A0 Am-1 Am enable … 1×2 decoder … … 2m × n ROM … … … Qn-1 Q0 A 2m × n ROM … … … 2m × n ROM … … 2m × n ROM Increase width of words A0 Am Increase number and width of words enable outputs … Q3n-1 Q2n-1 Q0 . simply ignore unneeded high-order address bits and higher data lines When available memory is smaller.Composing memory • • • Memory size needed often differs from size of readily available memories When available memory is larger.

The address of the decoder circuits should be clearly shown.INTERFACING EXAMPLES • Draw the circuit diagram of an 8085 system. having a 4 KB EPROM and two 8 KB RAM ICs. The starting address of the EPROM is 0000H and that of RAM is 8000H. Answer : • • • • EPROM 4 KB(Address lines required is 12 – A0 to A11 ) RAM-I 8 KB(Address lines required is 13 – A0 to A12 ) RAM-II 8 KB(Address lines required is 13 – A0 to A12 ) Mapping of Addresses to Memory Ics .

. . 1 0 0 . . .x A11 0 0 . 1 Hex Addres s 0000 0001 . 1 0 0 . 1 0 0 . . 1 A10 0 0 . . . 1 A7 0 0 . . . . 0 1 1 . . 1 A0 0 1 . . . 1 0 0 . . . . 1 0 0 . 1 0 0 .x A12 xx . 1 A2 0 0 . 1 A4 0 0 . 9FFF RAM-I 8 KB xx . . 1 0 0 . . .x . 1 0 0 . 1 A5 0 0 . 1 A6 0 0 . . 1 0 0 . 0 0 0 . . . 1 A8 0 0 . . 1 0 0 . . . . . 0FFF 4000 4001 . .x 0 0 . . 1 0 0 . 1 RAM-II 8 KB xx . 1 0 1 . . 1 0 0 . 1 Binary Address A9 0 0 . 0 A13 xx . . 1 0 0 . . . . . 0 1 1 . . 1 A14 0 0 . 1 0 0 . . . . . . . . . 1 0 0 . 1 0 0 . . . . 1 A3 0 0 .ICs A15 EPRO M 4 KB 0 0 . 1 0 1 . 5FFF 8000 8001 . . . 1 0 0 . 1 0 0 . 1 0 0 . . 1 A1 0 0 . . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 .

16-bit data. 8-bit/16-bit address. Symbolically. • An instruction comprises of an operation code (called ‘opcode’) which specifies the nature of the task to be performed by an instruction and the address of the data (called ‘operand’). a memory location. a register/pair. an instruction looks like . The operand may be 8-bit data.Instruction Formats of 8085 • An instruction is a command given to the uP to perform a specific task or function on a given data. on which the o pcode operates.

e. the opcode and the operand are in the same byte i.Based on length 8085 instruction set can be classified into 3 types: • In 1-byte instruction. • Example: ADD B • A 2-byte instruction looks like this: • Example: ADI 00H ..

the instructions can be classified into five groups: • data transfer (copy) group • arithmetic group • logical group • branch group • stack.• While a 3-byte instruction looks like the following: • Example: LDA 4400H Functionally. . I/O and machine control group.

there are five addressing modes. • Register addressing. known as ‘addressing modes’. • Implicit addressing.Addressing Modes in 8085 Each instruction indicates an operation to be performed on certain data. . For 8085 microprocessor. • Immediate addressing. • Register indirect addressing. These are: • Direct addressing. There are various methods to specify the data for the instructions.

• IN/OUT instructions (like IN 08H.Direct Addressing: • In this mode.) also falls under this category. . STA 5513H. • Examples of this type are: • LDA 4000H. the address of the operand is specified within the instruction itself. etc. etc. OUT 08H.

Register Addressing:
• In this mode of addressing, the operand are in the general purpose registers. • Examples are: MOV A, B ; ADD D, etc.

Register Indirect Addressing:
• In this mode, instead of specifying a register, a register pair is specified to accommodate the 16-bit address of the operand. • MOV A, M; ADD M are examples of this mode of addressing.

Immediate Addressing:
• The operand is specified in the instruction in this mode. Here, the operand address is not specified. • MVI A, 07; ADI 0F are examples of Immediate Addressing mode.

the operand is fully absent. .Implicit Addressing: • In this mode of addressing. CMA. RAL. • Examples are RAR. etc.

How to identify addressing mode? • Letter ending with I -> Immediate • Letter ending with X -> Indirect • Letter involving M -> May be Indirect or Register Indirect • Letter involving D -> Direct • Letter involving only Register -> Register .

INSTRUCTION SET: • The 8085 microprocessor instruction set has 74 operation codes that result in 246 instructions. L ) • Rp = Register pair (BC. H. DE. C. L ) • Rs = Register source (A. E. • M = Memory location • n = 8/16-bit Data • R = 8085 8-bit register (A. D. L ) • Rd = Register destination (A. D. E. B. C. SP) • ( ) = Contents of . D. B. • We should be able to grasp an overview of these frequently used instruction listed below along with the following notations. E. C. B. HL. H. H.

.Data Transfer (copy) Group: • The different types of data transfer operations possible are cited below: • The term ‘data transfer’ is a misnomer-actually data is not transferred. but copied from source to destination.

• MOV : Move • MVI : Move Immediate • LDA : Load Acc Directly from Memory • STA : Store Acc Directly in Memory • LHLD : Load H & L Registers Directly from Memory • SHLD : Store H & L Registers Directly in Memory An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits). • LXI : Load Register Pair with Immediate data • LDAX : Load Acc from Address in Register Pair • STAX : Store Acc in Address in Register Pair • XCHG : Exchange H & L with D & E .The data transfer instructions move data between registers or between memory and registers.

n8 M[HL] <. (L)  (E) Flags NIL NIL NIL NIL NIL NIL NIL NIL NIL NIL NIL NIL NIL .n8 (Rp) <.[Rp] [Rp] <.(Rs) (Rd) <. (H) <. n16 LDA addr STA addr LHLD addr SHLD addr LDAX Rp STAX Rp XCHG Operation (Rd) <.DATA TRANSFER GROUP Instruction MOV Rd.(L). M MOV M.n16 (A) <. n8 MVI M. n8 LXI Rp.[addr] [addr] <.(A) (H)  (D). Rs MOV Rd. Rs MVI Rd. [addr + 1] <.(Rs) (Rd) <.[addr + 1] [addr] <.[addr].(H) (A) <.(A) (L) <.M[HL] M[HL] <.

subtract.Arithmetic Group: • The arithmetic instructions add. • ADD : Add to Accumulator • ADI : Add Immediate Data to Accumulator • ADC : Add to Accumulator Using Carry Flag • ACI : Add Immediate data to Accumulator Using Carry • SUB : Subtract from Accumulator • SUI : Subtract Immediate Data from Accumulator • SBB : Subtract from Accumulator Using Borrow(CY)Flag • SBI : Subtract Immediate from Accumulator Using Borrow (Carry) Flag • INR : Increment Specified Byte by One • DCR : Decrement Specified Byte by One • INX : Increment Register Pair by One • DCX : Decrement Register Pair by One • DAD : Double Register Add. increment. or decrement data in registers or memory. Add Content of Register Pair to H & L Register Pair .

(A) – (r) (A) <.(A) + (r) + CY (A) <.M[HL] (A) <.(A) + n + CY Decimal adjust Acc (HL) <.(A) + M[HL] (A) <.CY Flags All All All All All All Flags All All All All All All All CY (Result >16bits) .(A) .n .M[HL] – CY (A) <.ADDITION Instruction ADD r ADD M ADI n ADC r ADC M ACI n DAA DAD rp Operation (A) <.(A) + n (A) <.(A) + (r) (A) <.(HL) + (rp) SUBTRACTION Instruction SUB r SUB M SUI n SBB r SBB M SBI n Operation (A) <.(A) + M[HL] + CY (A) <.(A) – n (A) <.(A) .(A) – (r) – CY (A) <.(A) .

(rp) + 1 (rp) <.(r) + 1 M[HL] <.1 (rp) <.M[HL] .INCREMENT AND DECREMENT Instruction INR r INR M DCR r DCR M INX rp DCX rp Operation (r) <.(rp) – 1 Flags Not CY Not CY Not CY Not CY None None .1 M[HL] <.M[HL] + 1 (r) <.(r) .

DAA) adds 6010 to the high-order 4-bits.e. .DAA Working • Execution of DAA instruction converts the content of the accumulator into two BCD values... The system utilises the AC flag for this conversion by following the procedures stated below: • (a) If the lower order 4-bits (D3 – D0) of the accumulator is greater than 910 or if the AC flag is set. then this instruction (i.e. DAA) adds 0610 to the low-order 4-bits. • (b) If the higher order 4-bits (D7 – D4) of the accumulator is greater than 910 or if the CY flag is set. then this instruction (i.

DAA instruction execution will add 6610 to the result. but both AC and CY flags are set. hence execution of DAA adds 0610 to the above 4D = 0 1 0 0 1 1 0 1 06 = 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 = 53BCD • (ii) Let ACC = 99BCD. Thus. Add 19BCD to this 34BCD = 0 0 1 1 0 1 0 0 19BCD = 0 0 0 1 1 0 0 1 53BCD = 0 1 0 0 1 1 0 1 = 4D H • Since the lower 4-bits represent D (> 910). . Add 79BCD to this 99BCD = 1 0 0 1 1 0 0 1 79BCD = 0 1 1 1 1 0 0 1 178BCD = 0 0 0 1 0 0 1 0 = 12 H 1 1 CY AC • Here both higher order (0001) and lower order (0010) 4-bits are less than 910.Examples follow to explain the above: • (i) Let ACC contains 34BCD.

Logical Group:
This group performs logical (Boolean) operations on data in registers and memory and on condition flags. The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the accumulator ON or OFF. • ANA : Logical AND with Accumulator • ANI : Logical AND with Accumulator Using Immediate Data • ORA : Logical OR with Accumulator • OR : Logical OR with Accumulator Using Immediate Data • XRA : Exclusive Logical OR with Accumulator • XRI : Exclusive OR Using Immediate Data

ANDING Instruction ANA r ANA M ANI n Operation (A) <- (A)  (r) (A) <- (A)  M[HL] (A) <- (A)  n ORING Instruction ORA r ORA M ORI n Operation (A) <- (A)  (r) (A) <- (A)  M[HL] (A) <- (A)  n XORING Instruction XRA r XRA M XRI n Operation (A) <- (A)  (r) (A) <- (A)  M[HL] (A) <- (A)  n Flags All All All Flags All All All Flags All All All

COMPARISON Instruction CMP r CMP M CPI n CMA CMC STC Operation Compare A and r Compare A and M[HL] Compare A and n A = A’ CY = CY’ CY = 1 Flags All All All None CY CY

Rules for comparison: If (A) < (Reg/Mem): CY flag is set and Z flag is reset. If (A) = (Reg/Mem): CY flag is reset and Z flag is set. If (A) > (Reg/Mem): CY flag and Z flag is reset

CY A.ROTATE Instruction RLC RRC RAL RAR Operation CY = A7. A(7-1) CY. A = A0. A Flags CY CY CY CY . CY = CY. A = A. A7 CY = A0. A = A(6-0).





The unconditional branching instructions are as follows: • JMP : Jump • CALL : Call • RET : Return Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows: • NZ : Not Zero (Z = 0) • Z : Zero (Z = 1) • NC : No Carry (C = 0) • C : Carry (C = 1) • PO : Parity Odd (P= 0) • PE : Parity Even (P= 1) • P : Plus (S = 0) • M : Minus (S = 1) .Branch Group: The branching instructions alter normal sequential program flow. either unconditionally or conditionally.

The conditional branching instructions are specified as follows: Jumps JC JNC JZ JNZ JP JM JPE JP0 Calls CC CNC CZ CNZ CP CM CPE CPO Returns RC (Carry) RNC (No Carry) RZ (Zero) RNZ (Not Zero) RP (Plus) RM (Minus) RPE (Parity Even) RPO (Parity Odd) .

(PC) +3 PC <.BRANCH GROUP Instruction JMP addr (unconditional) J conditional addr Operation (PC) <.addr If condition is true (PC) <.(HL) Flags Nil Respective flags will be checked PCHL None .addr Else (PC)<.

Stack Group: The following instructions affect the Stack and/or Stack Pointer: • PUSH : Push Two bytes of Data onto the Stack • POP : Pop Two Bytes of Data off the Stack • XTHL : Exchange Top of Stack with H &L • SPHL : Move content of H & L to Stack Pointer .

(HL) ((SP)) <-> (L) ((SP+1)) <-> (H) SP <.SP +1 RpH <.SP -1 (SP) <.(SP) SP <. n16 SPHL XTHL PUSH Rp Operation (SP) <.RpH SP <.SP -1 (SP) <.(SP) SP <.n16 (SP) <.SP +1 A <.SP +1 FlagReg <.FlagReg SP <.(SP) SP <.RpL SP <.SP +1 Flags None None None None PUSH PSW None POP Rp None POP PSW None .SP -1 (SP) <.STACK INSTRUCTIONS Instruction LXI SP.(A) RpL <.(SP) SP <.SP -1 (SP) <.

1) <.1) <.SP + 2 If True : PCL <.SP – 2 PC <.PCH (SP .(SP + 1) SP <.addr If True: (SP .1) <.1) <.PC + 3 PCL <.(SP) PCH <.addr False: PC <.PCL SP <.SP – 2 PC <.PCH (SP .Instruction CALL addr (uncondotional) = (PUSH PC + JMP addr) C conditional addr Operation (SP .PC + 1 Flags None None RET (unconditionally) = (POP PC) R condition None None .(SP) PCH <.PCL SP <.(SP + 1) SP <.SP + 2 False: PC <.

Fig: Use of CALL-RET in a subroutine .

(addr) (addr) <.A Flags None None .I/0 instructions: The I/0 instructions are as follows: • IN : Initiate Input Operation • OUT : Initiate Output Operation Instruction IN addr(8) OUT addr Operation A <.

(n * 8) in Hex None .PCH (SP -2) <.Machine Control instructions: The Machine Control instructions are as follows: • EI : Enable Interrupt System • DI : Disable Interrupt System • HLT : Halt • NOP : No Operation Instruction Operation Flags RST n = (CALL) (SP -1) <.PCL SP <.SP -2 PC <.

it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. an – The Microprocessor may respond to it as soon as possible. . • What happens when uP is interrupted ? – When the Microprocessor receives an interrupt signal. – Each interrupt will most probably have its own ISR.Interrupts • An interrupt is considered to be emergency signal that may be serviced.

• Interrupt is a process where an external device can get the attention of the microprocessor. • Classification of Interrupts – Interrupts can be classified into two types: • Maskable Interrupts (Can be delayed or Rejected) • Non-Maskable Interrupts (Can not be delayed or Rejected) – Interrupts can also be classified into: • Vectored (the address of the service routine is hardwired) • Non-vectored (the address of the service routine needs to be supplied externally by the device) . – The process starts from the I/O device – The process is asynchronous.

• An interrupt which can be disabled by software means. • They represent – – – – – TRAP. is called a maskable interrupt.5 and INTR interrupts respectively.5.5. RST 7.• There are five (5) interrupt pins of 8085— from pin 6 to pin 10. and an interrupt which cannot be masked is an unmaskable interrupt. • These five interrupts are ‘hardware’ interrupts. RST 5. . RST 6.

• 8085 has eight (8) software interrupts from RST 0 to RST 7. . the vector address for RST 5 is calculated as 5 × 8 = 4010 = 28H Therefore Vector address for RST 5 is 0028H. The instructions. hex codes and the vector locations are tabulated • Instruction HEX code addresses • RST 0 0000H • RST 1 0008H • RST 2 0010H • RST 3 0018H • RST 4 0020H • RST 5 0028H • RST 6 0030H • RST 7 0038H The vector address for a software interrupt is calculated as follows: Vector address = interrupt number × 8 For example.

00FFH). – The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives. – The IVT is usually located in memory page 00 (0000H . • All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).Interrupt Vectors and the Vector Table • An interrupt vector is a pointer to where the ISR is stored in memory. .

SIM Instruction: Execution of SIM instruction allows copying of the contents of the accumulator into the interrupt masks. Set Interrupt Mask Instruction .

Read Interrupt Mask Instruction . pending interrupts and interrupt masks are loaded into the accumulator. the status of SID.RIM Instruction: When RIM instruction is executed in software.

The 8085 Maskable/Vectored Interrupt Process • The 8085 has 4 Masked/Vectored interrupt inputs.5 (RST 5 and a half). – RST 5.5. RST 7. That’s why they have names like RST 5. . RST 6.5. • They are automatically vectored according to the following table: – The vectors for these interrupt fall in between the vectors for the RST instructions.5 • They are all maskable.

• The Interrupt Enable flip flop controls the whole maskable interrupt process. – Through individual mask flip flops that control the availability of the individual interrupts.5 and RST 7. • These flip flops control the interrupts individually.Masking RST 5. RST 6. .5 • These three interrupts are masked at two levels: – Through the Interrupt Enable flip flop and the EI/DI instructions.5.


. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table. The interrupt process should be enabled using the EI instruction. 2. and reset the interrupt flip flop. the microprocessor will complete the executing instruction.The 8085 Maskable/Vectored Interrupt Process 1. The 8085 checks for an interrupt during the execution of every instruction. 4. 3. If there is an interrupt. and if the interrupt is enabled using the interrupt mask.

At the end of the service routine. 6. 8. 7.The 8085 Maskable/Vectored Interrupt Process 5. it saves the address of the next instruction on the stack. The service routine must include the instruction EI to re-enable the interrupt process. . the RET instruction returns the execution to where the program was interrupted. The microprocessor jumps to the specific service routine. When the microprocessor executes the call instruction.

Summary of 8085 Interrupts: .

the address bus.e.Timing Diagrams: • Timing Diagrams represent the interrelationship among the 3 major buses i. • The actual significance of timing diagrams are: – To understand the operation of a processor – To formulate the software timings . the data bus and the control bus when an instruction is being executed.

. • In 8085.Instruction Cycle [IC]: • It is the time taken by the processor to complete the execution of an instruction. • An IC consists of Fetch Cycle (FC) and an Execute Cycle (EC). an IC may consists of 1 to 5 machine cycles. Thus IC = FC + EC.

Instruction cycle
• When a processor executes a program, the instructions (1 or 2 or 3 bytes in length) are executed sequentially by the system. The time taken by the processor to complete one instruction is called the Instruction Cycle (IC). • Depending on the type of instruction, IC time varies.

Machine Cycle [MC]
• It is the time taken by the processor to access a peripheral device. • Each READ or WRITE operation performed by the CPU with memory or an I/O device is known as a machine cycle. • In 8085, a MC may consists of 3 to 6 T states.

T-state / T-cycle
• It is one sub-division of the operation performed in one clock period. • These subdivisions are internal states synchronized with system clock.

[T3] • Decode the instruction and generate the necessary control signals.[T4] .[T2] • Transfer the instruction to IR inside uP.[T1] • Read the instruction (op-code) from memory.Fetch Cycle Steps: • Send the address of instruction on address bus.

. • A typical FC may consist of 3T states. the opcode residing in that memory location) is read in the second T-state. is sent to the memory. while in the third T-state this opcode is sent via the data bus to the instruction register (IR).Fetch Cycle: • The time required to fetch an opcode from a memory location is called Fetch Cycle. . residing in the PC. The content of the addressed memory (i.e. In the first Tstate. the memory address.

Execution Cycle Steps: • Decode the fetched instructions in ID. • Fetch the operands and execute the instruction. • Generate the required control signals necessary for the next operation. .

IO/M 0 0 0 1 1 1 0 0 S1 1 1 0 1 0 1 1 0 S0 1 0 1 0 1 1 0 0 MC Opcode Fetch Memory Read Memory Write IO read IO write INT ACK BI HLT . 8085 issues 3-status lines: IO/M. S1 and S0.• To differentiate between the different machine cycles.

except during the bus idle machine cycle. .Lower byte address on the multiplexed bus The lower byte of address (AD0 – AD7) is available on the multiplexed address/data bus during T1 state of each machine cycle. Higher byte address on A8 – A15 The higher byte of address (A8 – A15) is available during T1 to T3 states of each machine cycle. except during the bus idle machine cycle.

it appears at the beginning of T2.Appearance of data in the read and write machine cycles Data transfer from memory or I/O device to microprocessor or the reverse takes place during T2 and T3 states of the machine cycles. whereas in the write machine cycle. . data appears at the beginning of T3 state. In the read machine cycle.

Status signals during opcode fetch and memory read machine cycles: The status signals are IO/ M. S0 and S1. These three status signals remain active right from the beginning till the end of each machine cycle. Their conditions indicate the type of machine cycle that the system is currently passing through. .

. microprocessor reads data from either memory or I/O device while when WR is active. Data transfer (reading/writing) takes place during T2 and T3 states of read cycle or write cycle.RD and WR signals during the Read cycle and Write cycle When RD is active. it writes data into either memory or I/O device.

Opcode Fetch machine cycle .

S0. DCR C. All these occur in T1 state. whether to enter into T5 and T6 or to enter T1 of the next machine cycle. etc. The length of this machine cycle varies between 4T to 6T states—it depends on the type of instruction. MOV C. identifies the nature of machine cycle (by IO/M. S1) and activates the ALE signal. In this. • In T3. the processor takes the decision. • Examples are ADD B. data on the data bus is put into the instruction register (IR) and also raises the RD signal thereby disabling the memory. B.• The first machine cycle of every instruction is the Opcode Fetch. the processor places the contents of the PC on the address lines. • In T2 state. RD signal is activated so that the identified memory location is read from and places the content on the data bus (D0 – D7). This indicates the kind of instruction to be executed by the system. RRC. . on the basis of decoding the IR. • One byte instructions that operate on eight bit data are executed in T4. • In T4.

Memory Read/Write machine cycle .

IO Read/Write machine cycle .

For Students: • Workout on Timing Diagrams related to BI cycle and INTA cycle. . • Apply all these to your instruction set. • Also apply the T-states to calculate delay programs in microprocessor.

Peripheral IC’s • 8255: Programmable Peripheral Interface • 8155/8156: Programmable I/O Ports and Timer • 8355/8755: Programmable I/O Ports with ROM/EPROM • 8279: Programmable Keyboard/Display Interface • 8259: Priority Interrupt Controller • 8257: Programmable DMA Controller • 8253/8254 : Programmable Interval Timer • 8251 : USART .

. 8-bit I/O ports : PA. and PC (CU + CL) • One control word register into which control word is written. • 3.PPI: 8255 • Features: • 40 pin parallel I/O devices (programmable). PB.

Block Diagram .

The two address lines. along with CS signal. This is explained below: . determine the selection of a particular port or control register.

The characteristics of BSR mode are: • BSR mode is selected only when D7 = 0 of the Control Word Register (CWR). • Individual bits of Port C can either be Set or Reset. • At a time. . • BSR control word doesn’t affect ports A and B functioning. • Concerned with bits of port C.Control Word of 8255: 0 1 BSR Mode I/O Mode BSR mode stands for Bit Set Reset mode. only a single bit of port C can be Set or Reset. • Is used for control or on/off switch.

CW Register in BSR Mode .

Problem1 • Write a BSR control word to set bits PC7 and PC0 and to reset them after 1 second delay. .

01H. (Assume the DELAY is for 1 second) MVIA. (This sets PC0 bit of Port C) CALL DELAY. (Accumulator loaded with 01H to set PC0 bit of Port C) OUT 83H. 00H. . (This resets PC7 bit of Port C) RET. (Accumulator loaded with 0FH to set PC7 bit of Port C) OUT 83H. 0EH. (This resets PC0 bit of Port C) MVIA.Solution 1 • Subroutine Program: BSR: MVIA. (Accumulator loaded with 0EH to reset PC7 bit of Port C) OUT 83H. (Accumulator loaded with 00H to reset PC0 bit of Port C) OUT 83H. 0FH. (This sets PC7 bit of Port C) MVIA.

I/O Mode .

CW Register in I/O Mode .

whose features are: • Outputs are latched. • Ports don’t have handshake or interrupt capability. . • Inputs are not latched. • Sixteen possible input/output configurations are possible. CU. • All ports (A.Mode 0: • This is a basic or simple input/output mode. B. CL) can be programmed in either input or output mode.

Identify port addresses in following figure. • 3. . Write a program to read DIP switches & display the reading from port B at port A & from CL to port CU. Identify Mode 0 control word to configure port A & CU as input ports & port B & CL as output ports.Problem 2 • 1. • 2.

rotate & place data in the upper half of ACC RLC . 83H . RLC . RLC . HLT . display data at port CU. Mask the upper 4 bits of port C. Read switches at port C ANI 0FH . OUT 83H . Read switches at port B OUT 80H : display the reading at port A IN 82H . OUT 82H . Write word in control register to initialize the ports IN 81H . these bits are not input data RLC . LOAD ACC with control word.Solution 2 MVI A.

• I/Ps and O/Ps are latched. This 4-bit port is used for handshaking in each group. • There are two groups in this mode—group A and group B. taking the help of pins of Port C. input or outputting of data is carried out by taking the help of handshaking signals. also known as strobe signals. The basic features of this mode are: • Ports A and B can function as 8-bit I/O ports. Port C is called status port. • Interrupt logic is supported. . • In this mode. They can be configured separately. Each group consists of an 8-bit port and a 4-bit port.Mode 1: • In this mode. • Handshake signals are exchanged between CPU and peripheral prior to data transfer.

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