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SEMICONDUCTOR TECHNICAL DATA



0 to 18 V PCBin 3 14 PCAin • Pin–for–Pin Replacement for CD4046B VCOout 4 13 PC2out • Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited INH 5 12 R2 • Phase Comparator 2 switches on Rising Edges and is not Duty Cycle Limited C1A 6 11 R1 C1B 7 10 SFout VSS 8 9 VCOin BLOCK DIAGRAM SELF BIAS PHASE PCAin 14 2 PC1out CIRCUIT COMPARATOR 1 PHASE 13 PC2out PCBin 3 COMPARATOR 2 1 LD VOLTAGE 4 VCOout VCOin 9 11 R1 CONTROLLED 12 R2 VDD = PIN 16 OSCILLATOR 6 C1A VSS = PIN 8 (VCO) 7 C1B INH 5 SOURCE FOLLOWER 10 SFout VSS 15 ZENER REV 3 1/94 MOTOROLA CMOS LOGIC DATA Motorola. PLASTIC CASE 648 and maintains 90° phase shift at the center frequency between PCAin and PCBin signals (both at 50% duty cycle). frequency discrimination. tone decod- ing. Phase comparator 2 (with leading edge sensing logic) provides digital error signals. R1. The linear VCO produces an output signal VCO out whose SOIC frequency is determined by the voltage of input VCO in and the capacitor and CASE 751G resistors connected to pins C1A. Input PCAin can be used directly coupled to large voltage signals. PC2 out and LD. The self–bias circuit adjusts small voltage signals in the linear region of the amplifier. The CASE 620 comparators have two common signal inputs. and zener diode. 1995 MC14046B 1 . voltage–to–frequency PIN ASSIGNMENT conversion and motor speed control. The zener diode can be used to assist in power supply regulation.   The MC14046B phase locked loop contains two phase comparators. source follower. The inhibit input Inh. MC14XXXBCP Plastic disables the VCO and source follower to minimize standby power MC14XXXBCL Ceramic MC14XXXBDW SOIC consumption. Inc. data synchronization and conditioning. and maintains a 0° phase shift between PCA in and PCB in signals (duty cycle is DW SUFFIX immaterial). fre- quency synthesis and multiplication. The source–follower ORDERING INFORMATION output SFout with an external resistor is used where the VCO in signal is needed but no loading can be tolerated. PCAin and PCBin. and R2. Applications include FM and FSK modulation and demodulation. when high. C1B. LD 1 16 VDD • Buffered Outputs Compatible with MHTL and Low–Power TTL • Diode Protection on All Inputs PC1out 2 15 ZENER • Supply Voltage Range = 3. or indirectly coupled (with a series capacitor) to small voltage signals. a L SUFFIX CERAMIC voltage–controlled oscillator (VCO). Phase P SUFFIX comparator 1 (an exclusive OR gate) provides a digital error signal PC1out. TA = – 55° to 125°C for all packages.

5 Vdc) “1” Level VIH 5.2 — – 1.95 — 14.36 — – 0.91 µA/kHz) f + IDD R R1 = 1.0 — 6.0 Vdc 2.50 — 7.5 — Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.37 µA/kHz) f + IDD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ and 50% Duty Cycle) #Noise immunity specified for worst–case input combination.2 — 3.0 — 150 µAdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Per Package) Inh = PCAin = VDD. CL on VCOout. PCBin = VDD 15 — 20 — 0.36 — mAdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.0 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 1.0 — 0.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 0.95 — 4.6 Vdc) 5.8 — – 1.9 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 1.0 — 5. Noise Margin for both “1” and “0” level = 1.51 0.35 3/4 R1 + R2 + 1.05 — 0 0.5 Vdc) Source 5.05 Vdc Vin = VDD or 0 10 — 0. MC14046B MOTOROLA CMOS LOGIC DATA 2 .0 3.75 4.46 µA/kHz) f + IDD mAdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Inh = “0”.0 MΩ.7 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 4.5 or 4. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ †Temperature Derating: Plastic “P and D/DW” Packages: – 7.4 — ± 0.95 10 — 9.05 — 0.0 0.0 µAdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Current Iin 15 — — — Input Capacitance Cin — — — — 5.5 — — pF ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Quiescent Current IDD 5.05 — 0 0.00001 ± 0. R2 = RSF = ∞.05 — 0.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 9.5 or 13.2 – 0. All Inputs Vin – 0.5 — – 1.4 Vdc) Sink IOL 5.05 — 0.65 3/4 RSF + 1 x 10–3 (CL + 9) VDD f + 1 x 10–1 VDD2 ǒ 100% Duty Cycle of PCAin 100 Ǔ + IQ where: IT in µA.5 Vdc) 10 1. RSF in MΩ.05 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ “1” Level VOH 5. Iout = 0 µA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Total Supply Current† IT 5.35 — (VOH = 13. per Package† PD 500 mW ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature Range TA – 55 to + 125 _C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range Tstg – 65 to + 150 _C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Maximum Ratings are those values beyond which damage to the device may occur.5 Vdc min @ VDD = 15 Vdc ǒ Ǔ ǒ Ǔ †To Calculate Total Current in General: IT [ 2.0 or 9.62 — – 0.95 — Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = 0 or VDD 10 9. CL = 50 pF. 10 IT = (2.25 — 0.0 – 0.0 — 3.015 20 — 600 or 0 V.05 — 0 0. per Pin Iin ± 10 mAdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation.0 Vdc min @ VDD = 5.1 ± 0. VCOin.6 x VCOin – 1.0 7. and R1.0 (VO = 13.5 Vdc) 15 – 1.5 Vdc) 15 4.05 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 — 0. 15 IT = (4.7 — – 0. 10 — 10 — 0.14 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOH = 9.0 IT = (1.65 VDD – 1. R2. f in kHz.6 — 1.0 — 4.25 — 11 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Drive Current IOH mAdc (VOH = 2.5 to VDD + 0.0 Vdc) 10 7.2 x VDD VCOin – 1.5 Vdc) 10 – 0.95 — 9.50 3.1 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VOL = 0.5 to + 18 Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage.005 5.5 2.4 8.3 2.0 4.5 Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Current.88 — 0.5 Vdc) 15 11 — 11 8.5 Vdc) 5.0 Vdc) 10 — 3.0 – 1.25 — – 0.5 — 3.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Rating Symbol Value Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage VDD – 0.25 1.010 10 — 300 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Zener = VCOin = 0 V.95 5.0 mW/_C From 65_C To 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD – 55_C 25_C 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Voltage “0” Level VOL 5.5 — 1.8 — 2.95 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Voltage # “0” Level VIL Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VO = 4.5 or 1.0 – 1.1 ± 1.5 Vdc) 15 — 4. CL in pF.0 5.0 — 7.5 – 0.5 or 0.64 — 0.0 Vdc min @ VDD = 10 Vdc 2. VDD in Vdc.5 — 2.95 15 — 14. fo = 10 kHz.0 — 0.9 — – 0.0 — 4.0 or 1.75 — 3.5 – 3.95 — 15 14.0 — 1.0 — 4.

2 0.12 — %/_C (R2 = ∞ ) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 — 0.5 ns 10 — 50 75 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL = (0.2 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ — PCBin Rin 15 150 1500 — MΩ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Input Sensitivity Vin 5.0 V.4 1.0 V ± 2.6 — (VCOin = 7.5 ns/pF) CL + 15 ns 10 — 90 150 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH = (1.0 mA) * The formula given is for the typical characteristics only.0 — 0.4 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ R1 = 5.0 — MΩ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 0.0 — 1.2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Linearity — % ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VCOin = 2.3 V. R1 > 400 kΩ) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 — 1.2 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VCOin minus SFout.5 0. and R2 = ∞) 15 1.0 kΩ.5 V. RSF > 50 kΩ) 10 — 0.5 V ± 0. TA = 25°C) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Minimum Maximum ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD Characteristic Symbol Vdc Device Typical Device Units ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Rise Time tTLH ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH = (3. RSF > 500 kΩ) 10 — 1.5 V ± 5.5 ns/pF) CL + 25 ns 5. RSF > 50 kΩ) 15 — 0.0 V ± 2.0 ns/pF) CL + 30 ns 5. R1 ≥ 1000 kΩ) 15 — 1. RZ — — 100 — Ω MOTOROLA CMOS LOGIC DATA MC14046B 3 .0 — (VCOin = 5.3 V.8 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ZENER DIODE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Zener Voltage (Iz = 50 µA) VZ — 6.0 — (VCOin = 7. R1 > 10 kΩ) 5.0 — 200 300 mV p–p AC Coupled — PCAin ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 — 400 600 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ C series = 1000 pF.04 — 15 — 0.0 0.7 7.0 — 1.0 — 100 175 tTHL = (0.65 2.0 — 180 350 tTLH = (1.4 — 15 0.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS* (CL = 50 pF.0 V.7 — MHz (VCOin = VDD.0 1.9 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Temperature — Frequency Stability — 5.0 7.0 — 0.5 V.75 ns/pF) CL + 12.5 V ± 0.1 0.0 1.015 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Linearity (R2 = ∞ ) — % ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VCOin = 2.65 2.55 ns/pF) CL + 9.0 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Duty Cycle ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ — 5 to 15 — 50 — % ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Resistance — VCOin Rin 15 150 1500 — MΩ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SOURCE–FOLLOWER ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Offset Voltage — 5.5 V ± 5. PCBin — 5 to 15 See Noise Immunity ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VOLTAGE CONTROLLED OSCILLATOR (VCO) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Frequency fmax 5. RSF > 50 kΩ) 5. f = 50 kHz 15 — 700 1050 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Coupled — PCAin.1 — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (VCOin = 5.5 ns ÎÎÎ 15 — 37 55 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PHASE COMPARATORS 1 and 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Resistance — PCAin Rin 5. C1 = 50 pF 10 1.0 2.3 V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Dynamic Resistance (Iz = 1.1 ns/pF) CL + 10 ns 15 — 65 110 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Fall Time tTHL ns ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL = (1.2 15 — 1.65 2.

The frequency of VCOout. Figure 2. 1 fmin = (VCO input = VSS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ R2(C1 + 32 pF) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Note: These equations are intended to be 1 fmax = + fmin (VCO input = VDD) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ a design guide. frequency (fmin). High Low ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lock frequency range (2fL). The frequency range of the input signal on which the loop will stay locked if it was ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ initially in lock. 2fL = full VCO frequency range = fmax – fmin. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Phase angle between PCAin and PCBin. laboratory experimentation may Where: 10K R1 1M v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ be required for fixed designs. 90° at center frequency (f0). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ and 180° at ends of lock range (2fL) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Locks on harmonics of center frequency. VCO in PLL system adjusts to center VCO in PLL system adjusts to minimum ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ frequency (f0). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Capture frequency range (2fC). Design Information MC14046B MOTOROLA CMOS LOGIC DATA 4 . Since calculated component R1(C1 + 32 pF) values may be in error by as much as a ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v v factor of 4. approaching 0_ Always 0_ in lock (positive rising edges). PHASE COMPARATOR 1 Input Stage 00 01 X X 11 10 PCAin PCBin PC1out 0 1 PHASE COMPARATOR 2 Input Stage X X 00 00 00 01 10 10 01 01 10 PCAin PCBin 11 11 11 3–State PC2out 0 1 Output Disconnected LD 0 1 0 (Lock Detect) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Refer to Waveforms in Figure 3. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Figure 1.01 µF ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ components is typically less than ± 20%. Yes No ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Signal input noise rejection. Phase Comparators State Diagrams ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic Using Phase Comparator 1 Using Phase Comparator 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ No signal on input PCAin. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Depends on low–pass filter characteristics fC = fL v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (see Figure 3). Part to part 10K R2 1M v v frequency variation with identical passive 100pF C1 . The frequency range of the input signal on which the loop will lock if it was initially ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ out of lock. fC fL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Center frequency (f0). when VCOin = 1/2 VDD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCO output frequency (f).

5 wn ) KfKNVCO) for a typical design ωn ^ 10 (at phase detector input) f VCO (R3C2 ^ R3C2S ) 1 + R3C21S ) 1 F(s) + ζ 0. see: (1) F. the ratio of R3 to R4 sets the damping. John Wiley and Son. reprinted by Motorola Inc. New York. (3) Garth Nash. 9 SOURCE 10 SFout FOLLOWER VCOin RSF PCAin 14 EXTERNAL PHASE 2 OR 13 9 VCO 4 VCOout @ FREQUENCY f′ 3 LOW–PASS COMPARATOR PC1out 11 12 6 7 @ FREQUENCY Nf′ = f FILTER PCBin OR CIA CIB PC2out R1 R2 CI EXTERNAL ÷N COUNTER Typical Low–Pass Filters Ǹ Typically: + fmax (a) R3 (a) R3 OUTPUT OUTPUT R4 C2 6N – N INPUT INPUT 2 pD f 2 p fL C2 2fC [p 1 R3 C2 R4 (R3 ) 3. General Phase–Locked Loop Connections and Waveforms MOTOROLA CMOS LOGIC DATA MC14046B 5 . May. Przedpelski. “Phase–Lock Loop Design Fundamentals”. (4) A.707 S(R3C2 ) R4C2) ) 1 F(s) Waveforms Phase Comparator 1 Phase Comparator 2 VDD VDD PCAin PCAin VSS VSS VOH VOH PCBin PCBin VOL VOL VOH VOH PC1out LD VOL VOL VOH VOH VCOin PC2out VOL VOL VOH VCOin VOL Note: for further information. B. (2) G. Moschytz. In Figure B. 000W) C2 + 100N Df – R4 C2 fmax2 C2 ∆ f = fmax – fmin NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. “Miniature RC Filters Using Phase–Locked Loop”. BSTJ.1)(R3) for optimum results. Motorola Inc. Figure 3. LOW–PASS FILTER Ǹ Ǹ Filter A Filter B Definitions: N = Total division ratio in feedback loop KfKVCO KfKVCO wn + wn + Kφ = VDD/π for Phase Comparator 1 Kφ = VDD/4 π for Phase Comparator 2 NR3C2 NC2(R3 R4) ) 2 p D fVCO KVCO + Nw VDD – 2 V 2 p fr z + 2K K n z + 0. S. AN–535. The value for CC should be such that the corner frequency of this network does not significantly affect ωn. R4 ^ (0. A capacitor CC is then placed from the midpoint to ground. Gardner. AR254. 1965. 1966. “Phase–Locked Loop Design Articles”. “Phase–Lock Techniques”.

65 G 0.21 0.53 SEATING F 0.35 6.020 0.25 (0.08 N K D 0. OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– NOTES: 1.93 B 0. DIMENSION B DOES NOT INCLUDE MOLD FLASH.050 BSC 1.40 1.015 0. 1 8 5.05 19.040 0.51 1.25 (0. CONTROLLING DIMENSION: INCH.44 D 0.01 0.008 0.77 –T– PLANE G 0.010) M T A M S 0. DIMENSION L TO CENTER OF LEAD WHEN –B– FORMED PARALLEL. DIMENSIONING AND TOLERANCING PER ANSI Y14.015 0. 3.100 BSC 2.100 BSC 2.74 D 16 PL M 0_ 10 _ 0_ 10 _ 0.01 MC14046B MOTOROLA CMOS LOGIC DATA 6 .110 0. 1 8 4.740 0.250 0.5M. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.50 7.050 BSC 1.010) M T B S M 0_ 15 _ 0_ 15 _ N 0.015 0.50 SEATING PLANE E 0.065 1.39 0. DIMENSION F MAY NARROW TO 0.49 –T– C ––– 0.62 BSC D 16 PL 0.040 0.70 1.5M.145 0.51 1.270 6.54 BSC E M H 0.030) WHERE THE LEAD ENTERS THE CERAMIC C L BODY.85 S C 0.02 1.18 4.008 0. 1982.010) M T A S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: –A– 1.295 6.55 B 0.785 19. DIMENSIONING AND TOLERANCING PER ANSI Y14. INCHES MILLIMETERS DIM MIN MAX MIN MAX F C L A 0.30 G L 0.10 7.27 BSC H K M J 0.38 J K 0.295 0.80 3.300 BSC 7.770 18.27 BSC F 0.021 0.76 (0.170 3.125 0.020 0. B 4. 16 9 3.25 (0.54 BSC H 0.69 4.38 K 0.21 0. CONTROLLING DIMENSION: INCH.015 0. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 1982.130 2.055 0.31 F G J 16 PL L 0. 16 9 2.200 ––– 5.80 19.240 0.39 0.305 7.040 0. 2.020 0. ROUNDED CORNERS OPTIONAL.175 3.750 0.

80 6.00 0. subsidiaries. and specifically disclaims any and all liability. P 8 PL 4.50 0. even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.006) 1 8 0. and distributors harmless against all claims. INTERNET: http://Design–NET. is an Equal Opportunity/Affirmative Action Employer.127 (0.40 1. including “Typicals” must be validated for each customer application by customer’s technical experts. representation or guarantee regarding the suitability of its products for any particular purpose.010) M T B S A S R 0.25 0. employees. 1982.054 0. Inc.10 0.49 0.20 0.008 0. N. Box 20912. and expenses. DIMENSIONS A AND B DO NOT INCLUDE –B– MOLD PROTRUSION. 16 9 2. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application. Phoenix.068 D 0.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.25 (0. Ltd. or authorized for use as components in systems intended for surgical implant into the body.5M.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION..com 51 Ting Kok Road.009 K 0.75 0..244 0.010 0.35 1.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola does not convey any license under its patent rights nor the rights of others.016 0.229 0.. Tokyo 135. any claim of personal injury or death associated with such unintended or unauthorized use.019 C F 0. Motorola. 5.25 0. intended. Inc.35 0.25 0. affiliates. 8B Tai Ping Industrial Park. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution.386 0. nor does Motorola assume any liability arising out of the application or use of any product or circuit. 3. Japan. including without limitation consequential or incidental damages.27 BSC 0.00 0. All operating parameters. damages.010) M B S PER SIDE.004 0.150 0. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0. and reasonable attorney fees arising out of.19 0. OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– NOTES: 1.049 –T– SEATING G 1. Buyer shall indemnify and hold Motorola and its officers. Hong Kong. MAXIMUM MOLD PROTRUSION 0.sps. Arizona 85036.80 4. 03–81–3521–8315 MFAX: RMFAX0@email. DIMENSIONING AND TOLERANCING PER ANSI Y14. P. JAPAN: Nippon Motorola Ltd. or other applications intended to support or sustain life.K.T. costs. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.009 D 16 PL M 0_ 7_ 0_ 7_ P 5.O.393 K R X 45 _ B 3.25 0. or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Motorola and are registered trademarks of Motorola. CONTROLLING DIMENSION: MILLIMETER.15 (0. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.050 BSC PLANE M J J 0.mot. Motorola products are not designed. Motorola makes no warranty.25 (0.157 C 1. directly or indirectly. Tai Po.80 10.014 0. Tatsumi–SPD–JLDC. 852–26629298 *MC14046B/D* ◊ MOTOROLA CMOS LOGIC DATA MC14046B MC14046B/D 7 . 6F Seibu–Butsuryu–Center. G MILLIMETERS INCHES DIM MIN MAX MIN MAX F A 9.

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