JOURNAL OF COMPUTING, VOLUME 3, ISSUE 3, MARCH 2011, ISSN 2151-9617

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The Evolution of Synchronous Sequential

Circuits Based on Description of gate levels
P. Soleimani, S. Mirzakuchaki, and R. Sabbaghi-Nadooshan

Abstract— Evolvable hardware (EHW) is a new concept for automatic design of electronic systems instead of manual design that has been
used by electronic engineering. Final purpose of EHW is to build the electronic circuit. Conventional method, specify that the design and the
implementation of the electronic circuit how does, but evolutionary design method only denotes the implementation of the circuit.
This paper, proposes a method to design and optimize the synchronous sequential circuits. Evolutionary strategy has been used as evolutio-
nary algorithm. In this approach, to increase the speed of evolution, each combinational parts of sequential circuit have been evolved sepa-
rately. Finally, the sequential circuit has been assembled. The results show our method can reduce the number of generations and the time of
evoluation for designing and decreasing the number of logic gates which have been used in combinational parts of sequential circuit.

Index Terms—algorithm, hardware description languages, evolvable Hardware, optimization, simulation

——————————  ——————————

1 INTRODUCTION

E HW uses evoluationary algorithm to design and de-

termine restructure of hardware systems. Evoluatio-
nary methods provide the design the electronic cir-
2 THE PROPOSED METHOD
cuit automatically. Sometimes, evolved circuit shows the As Fig.1, the structure of sequential logic circuits com-
characteristics that are not accessible with conventional prises a set of two sections of combinational logic circuit
method easily. and D flip-flops [7].
Simpler structure of combinational circuits rather In this approach, for designing combinational parts, we
than sequential circuits and the lack of feedback in this present two types of rectangular arrays of logic gates.One
circuits is caused to more researches have been done in of them is for building next state logic and the other is for
this field. However, relatively few efforts have been de- output logic (see Fig. 2).
voted to evolving sequential logic circuits [1]. For exam- As Fig. 3-4, these arrays have R rows and C columns and
ple Thomson [2] evaluated Robotics. Manovit [3] synthe-
sized frequency detector, odd parity detector, module-5
counter, serial adder. Aporntewan [4] evolved serial ad-
der, 0101 detector, module-5 counter, Reversible 8-
counter with genetic algorithm. Solimon [5] designed 3-
bit up-counter, and Shanthi [6] evolved module-6 coun-
ter, ‘lion’ circuit.
This paper is organized in 9 sections: sections 2
consider the main idea of the proposed method. Section 3
describes evolutionary strategy algorithm structure. Sec-
tion 4 describes details of process to define structure of
chromosomes. Section 5 describes fitness evaluation Fig. 1. Discription on the circuit parts [7].
process to evaluate the performance of evolved circuits. their gates are chosen from OR, AND, NOT and XOR
Simulation test bed has been described in section 6. Sec- gates. Except NOT gate, the other gates have two inputs
tion 7 summarizes the experiment of proposed method on and one output. Each gate input can be taken from prima-
the 1010 sequential circuit. Section 8 simulates results for ry inputs, DFFs outputs or output of each gate that is
1010 detector circuit. Finally in section 9, the conclusion of neighbor to the left.
this paper is presented. In our approach, one multiplexer is added to the inputs of
gates in each cell array (see Fig.5), input of DFFs and be-
———————————————— fore primary output. Then, by determining the proposed
 P. Soleimani is with the Department of electronic engineering, Islamic structure of chromosome encoding (Section 4) and by
Azad University, Central Tehran Branch.
using evolutionary strategy algorithm, we have evaluated
 S. Mirzakuchaki is with the Department of electronic engineering, Iran
University, of Science and Technology.
 R. Sabbaghi-Nadooshan is with the Department of electronic engineering. ,
Islamic Azad University, Central Tehran Branch.
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Fig. 5. Block diagram of cell array after adding the multiplexer to array.

Fig. 2. Block diagram of proposed method.

2 2 2
1 1 1
3 3 3

Primary Next
inputs 2 2 2 states
1 1 1
and 3 3 3 of DFFs
Present
states
2
of DFFs 2 1 1 2 1
3

Fig. 3. Schematic of the rectangular array structure has been used

in the combitional logic circuit to build next State.

2 2
1 2 1 1
3 3

Primary Primary Fig. 6. Structure of Multiplexer

inputs 2 2 2
Outputs
1 1 1
and 3 3 3

Present third stage, the best chromosome has been selected based
states
of DFFs 2 1
2
1
2
1
on the best fitness value. At the fourth stage, the chromo-
some that has been selected in the previous stage is eva-
3 3

luated for evolution stop condition. If the stop condition

Fig. 4. Schematic of the rectangular array structure has been used
in the combitional logic circuit to build primary outputs.
the different states of logic gates connection for each ar-
ray separately, to achieve correct functionality and mini-
mum number of logic gates. The structure of multiplexer
has been used, is shown in Fig.6.
Evolving of each array separately, has been lead to in-
crease the speed of evolution the circuit and decrease the
run time.
3 EVOLUTIONARY STRATEGIES ALGORITHM
Evolutionary strategies (ES) is one of the evolutionary
algorithm that so called (1+) algorithm.  is the size of
population. At first stage, all of the chromosomes have
been produced, randomly. At the second stage, the fitness
value of any chromosome has been computed. At the
has been not achieved, the new population is produced
by  iteration mutation of the best chromosome.
Hence, the number of member of new generation is +1.
The steps 2-4 have been repeated until to reach to the evo-
lution stop condition.
4 CHROMOSOME ENCODING
The chromosome defines the construction of the logic
circuit and the connectivity between logic gates.
In this approach, we use two types of chromosome with
different lengths. One of them is for evolution of input
combinational logic part, and the other is for evolution of
output combinational logic part. For encoding of the first
chromosome that has been shown at subcircuit A in Fig.2,
we put a multiplexer to input of each gate and DFFs and
change connection between gates and DFFs by changing
the selection bits of multiplexers. Inputs of multiplexers
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of logic gates are taken from primary inputs, present
states of DFFs, outputs of all gates that is the neighbor left
column and constant values that set equal ‘0’ and ‘1’. Al-
so, inputs of multiplexers of DFFs are taken from primary
inputs and outputs of all logic gates that are on the all left
columns. For encoding of the second chromosome that
has been shown as subcircuit B in Fig. 2, we put a multip-
lexer to input of each gate and before primary outputs.
We change connection between gates by changing the
selection bits of multiplexers. Inputs of multiplexers of
logic gates are taken from primary inputs, present states
of DFFs, outputs of all gates that is the neighbor left col-
umn and constant values that set equal ‘0’ and ‘1’. Also
inputs of multiplexers of primary output are taken from
primary inputs and outputs of all logic gates that are on
the all left columns.
Fig. 7 Structure of chromosome encoding.
Hence we have used the selection bits of multiplexers as
chromosome genes as shown in Fig. 7.
5 FITNESS EVALUATION PROCESS
In this section, the fitness evaluation process has been
explained. We used finite state machine (FSM) for evalua-
tion of sequential circuits. In this method, first the desired
state is set in the circuit flip flops and then we change the
value in primary inputs and compare the output of circuit
with the desired ones. At any state, desired output for
input combinational logic circuit is the next state of the
DFFs but desired output for output combinational logic
circuit is primary output (output columns of STT). If in
any state, the corresponding output and desired output
are equal, then the fitness value is increased.
In proposed method, we measured fitness function by
71
two main criteria: design and optimization. In the first
criteria, functionality of the circuit is evaluated. The goal
of first criteria is to evolve a circuit that has 100% functio-
nality. Then in the second criteria, optimization has been
performed by reducing the numbers of logic gates that is
used in the target circuit. Fitness optimization is activated
once design fitness value reaches 100% functionality.
The design criterion of any individual is evaluated as
these steps:
1. The initial value for design fitness has been considered
to zero.
2. The primary inputs and present state of DFFs have
been set externally. Then the value of output of the circuit
is measured after sending a clock signal to DFF.
3. The corresponding output with desired output has
been compared. We can use this equation to measure fit-
ness:
FDesign=FDesign+ number of equal output bits. (1)
4. The steps 2-3 have been repeated for the remaining
states of FSM and functionality of circuit has been eva-
luated.
The optimization criterion has been calculated as follow
steps:
1. The initial value for optimization criterion has been
considered as:
FOptimization = R*C (2)
2. For each individual, total number of logic gates have
been calculated. So, we can use this equation to find op-
timization fitness:
FOptimization = (R*C) - number of logic gates that is used in
new circuit. (3)
Now, the final fitness of individual could be calculated by
using this equation:
Ffinal = FDesign+ FOptimization (4)
Both of the procedures described above are applied for
evaluation of both combinational parts of sequential logic
circuit.
6 SIMULATION TEST BED
In this paper, we used Modelsim as VHDL hardware
programming language simulator and MATLAB software
for implement ES. In addition we used simulator link TM
MQ toolbox in this software.
It can access to Modelsim, open HDL code, run it for dif-
ferent inputs that are determined in MATLAB code and
save outputs in the variables of MATLAB codes. Fig. 8
shows block diagram of this process. Hence, this toolbox
is as a link between Modelsim and MATLAB.
7 EXPERIMENT ON THE 1010 SEQUENTIAL CIRCUIT
In this section, the proposed method is experimented on
the 1010 sequential circuit. State transition graph of this
circuit has been shown in Fig. 9. Also, in Fig. 10 step1
shows the symbolic state table of FSM and state assign-
ment to each state.
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Fig. 8. Structure of relationship between MATLAB and Modelsim [8].
shown in Fig. 11. Also, the graph for reach 100% functio-
nality (fitness value=-100) of input combinational logic
circuit has been depicted in Fig. 12 and for output combi-
national logic circuit has been depicted in Fig. 13. The re-
sults that have been achieved by proposed method in
compare with [9] have been shown in Table 1. The solu-
tion reported in [9], uses almost 3 times more gates than
the circuit created by the proposed method, but the solu-
tion reported in [7] uses equal number of gates in compare
with our method. However, the type of the gates have
been used in two method are different.
In this method, the maximum number of the generation
for evaluation of input combinational logic circuit was 101
generations but for output combinational logic circuit was
80 generations. We reached to above results after 10 runs
that in compare with the method was presented in [7], our
method uses less generations and less time of evaluation
to reach 100% functionality and optimization.

Fig. 9. 1010 Detector (a) state transition graph, b state transition table,
(c) state assignment [7].

Fig. 11. Evolved optimal circuit solution for 1010 detector.

Fig.10. Process of STT of 1010 sequential circuit where .i in-

put=input+present state bits, .o defined the number of outputs calcu-
lated, outputs=next state+output bits, .p is the number of product terms.

In step2, STT of the target circuit is shown. In step3, STT

of the circuit is divided into input combinational logic
subcircuit A and output combinational logic subcircuit
B. (similar to [7]).
This circuit has four states that has been lead to use two
DFFs. As we explained in previous sections, we evaluated
Fig. 12. Fitness function behavior of input combinational logic cir-
each subcircuit A and B, separately. Finally, the sequen- cuit.when the fitness value reaches to -100 after 101 generations.
tial circuit is assembled.

8 RESULTS
In this section, structure of the evolved circuit has been
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[3] C. Manovit, C. Aporntewan and P. Chongstitvatana, “Synthesis of
Synchronous Sequential Logic Circuits from Partial Input/Output
Sequence”, vol.1478, pp.98-105,1998.
[4] C. Aporntewan, P. Chongstitvatana, “An On-Line Evolvable
Hardware for Learning Finite-State Machine,” in Proceeding of int,
pp.13-15, 2000.
[5] A. T. Soliman, H.M. Abbas, “Synchronous Sequential Circuits Design
using Evolutionary Algorithm,” vol.4, pp.2013-2016, 2004.
[6] A. P. Shanthi, L. K. Singaram, “Evolution of Asynchronous
Sequential Circuits,” in Proceeding of the 2005 NASA/DoD
Conference on Evolvable Hardwares, pp.93-96, 2005.
[7] B.Ali, A.Almaini and T.Kalganova, “Evolutionary Algorithms and
Their Use in the Design of Sequential Logic Circuits,” in Genetic
Program, Evolvable Machine, vol.5,pp.11-29, 2004.
[8] http://www.Mathworks.com
[9] A. E. A. Almaini, Electronic Logic Systems, Prentice-Hall, 3rd
Fig. 13. Fitness function behavior of output combinational logic cir- ED.1994,UK.
cuit.when the fitness value reaches to -100 after 80 generations.

TABLE 1 P. Soleimani received the B.S. degree in bio electronic engineer-

SOLUTION OBTAINED FOR 1010 DETECTOR ing from the Science and Research Branch, Islamic Azad University,
Tehran, Iran in 2007. She is MS candidate in electronic engineering
from Central Tehran Branch of Islamic Azad University. Her research
interest includes Evolvable Hardware, digital signal processing.

S. Mirzakuchaki received the BS in Electrical Engineering from

the University of Mississippi in 1989, and the MS and PhD in Elec-
trical Engineering from the University of Missouri-Columbia, in 1991
and 1996, respectively. He has been a faculty member of the Col-
lege of Electrical Engineering at the Iran University of Science and
Technology, Tehran, since 1996. His current research interests in-
clude characterization of semiconductor devices and design of VLSI
circuits. Dr. Mirzakuchaki is a member of IEEE and IET (formerly
IEE) and a Chartered Engineer.

R. Sabbaghi-Nadooshan received the B.S. and M.S. degree in

electrical engineering from the Science and Technology University,
Tehran, Iran, in 1991 and 1994 and the Ph.D. degree in electrical
engineering from the Science and Research Branch, Islamic Azad
University, Tehran, Iran in 2010. From 1998 he became faculty
member of Department of Electronics in Central Tehran branch,
Islamic Azad University, Tehran, Iran. His research interests include
9 CONCLUSION interconnection networks, Networks-on-Chips, Hardware design and
embedded systems.

This paper, presented a method to design and optimize

the synchronous sequential circuits. In this method, we have
used ES as the evolutionary algorithm and describe digital
circuit based on gate level. Combinational blocks have been
produced from AND, OR, XOR and NOT gates and each of
them evaluated separately. The achieved results by proposed
method have been compared with other method [7, 9]. This
comparison shows our method can design sequential logic
circuits 3 times better than [9] and almost equal to [7] and
need to less time for evaluating. For future works it can be
considered the evolution of the large scale sequential circuits
by using proposed method that is used more in industry.

REFERENCES
[1] H.Liang, W.Luo and X.Wang, “A tree-step decomposition method for
the evolutionary design of sequential logic circuits,” in Genet
Program Evolvable Mach, vol.10,pp.231-262, 2009.
[2] A.Thompson, “Evolving Electronic Robot Controllers that Exploit
Hardware Resources,” vol.929, pp.640-656, 1995.