Deadbeat control method for single-phase UPS inverters with compensation of computation delay

O.Kukrer H.Komurcugil

Abstract: In existing deadbeat control techniques for single-phase UPS inverters, the pulse width of the inverter output voltage is limited by the computation time of the controlling processor. This limits the utilisation of the DC source voltage and slows the response of the control system. A deadbeat control technique is presented which eliminates these limitations by allowing the application of the newly computed pulse width with time delay. During this delay, the previously applied pulse width is preserved until it is updated by the new pulse width. This method requires the use of a load-dependent reference function for the inverter output voltage. However, the error in the load voltage caused by using a fixed reference function is shown to be negligible. Computer simulations are performed to verify the theoretical results and for comparison with existing methods. Experimental results are also presented to support the theoretical considerations.



With the development of power semiconductor devices that can switch at very high speeds, feedback control techniques have been considered for inverters in UPS systems. Classical open-loop techniques of obtaining sinusoidal output voltages (e.g. sinusoidal PWM) are incapable of providing a satisfactory response with nonlinear or fast-changing loads. Feedback control approaches for UPS inverters can be broadly classified as continuous-time [1, 2] and discrete-time [3–8]. Continuous-time control strategies are implemented using analogue techniques and are not as reliable as discrete-time stategies. The instantaneous feedback control technique [1] has a reasonably fast transient response. However, this approach has the disadvantage that harmonics are generated in the output voltage at frequencies around the switching frequency. Discrete-time control strategies are mostly based on the deadbeat control theory [3–8]. For single-phase inverter systems, the pulse width in a switching interval which would drive the output voltage to a specified
© IEE, 1999 IEE Proceedings online no. 19990215 Paper first received 16th December 1997 and in revised form 6th July 1998 The authors are with the Department of Electrical and Electronic Engineering, Eastern Mediterranean University, G. Magosa, Mersin 10, Turkey
IEE Proc.-Electr. Power Appl., Vol. 146, No. 1, January 1999

sinusoidal reference is computed on-line [3–5]. The voltage pulse is subsequently applied to the output filter as soon as its computation is complete. A disadvantage of this approach is that the maximum pulse width is limited by the computation time of the processor. The two-level PWM technique [5] improves the time made available for computation. Alternatively, for a given computation time, the switching frequency can be increased to almost twice that with the three-level technique [3]. These approaches have yet another drawback concerning the dynamics of the closed-loop system. Analysis of this approach reveals that there are two poles in the feedback system. One pole is located at the origin at the rated load, with the gains calculated at the rated load. The second pole has a magnitude of slightly less than unity. Owing to this pole, even though the deadbeat response of the voltage could be obtained, the response of the other state variable (capacitor current) is very slow and oscillatory. The oscillations of the capacitor current during transients may give rise to undesirable electromagnetic interference (EMI) problems. This deteriorates the overall performance of the system. In this paper, a discrete-time deadbeat control strategy is proposed that completely eliminates the computation delay problem. With this approach, the time made available to the processor is considerably greater than with existing methods. Therefore, much higher switching frequencies are possible. Basically, this control strategy depends on the application of the manipulated inverter voltage with a delay in the sampling interval, while the previously applied inverter voltage is preserved until then. Deadbeat control is applied to all the state variables of the system to locate all poles at the origin. Although this gives rise to the problem of a changing reference function for the inverter voltage as the load changes, it is shown that the change is very small and can be tolerated. Computer simulations are performed to verify the theoretical results and for comparison with established methods. Experimental results are also presented to show the effectiveness of the proposed method for practical systems.


Single-phase UPS inverter with resistive load

the state equation of the system is where x = [v i]T. 146. The control voltage vi(kT) for the kth sampling interval is assumed to be applied after a time delay γT. Ackermann’s formula [9] can be used to find the gains that satisfy this requirement as The gains are normally calculated for the rated load of the inverter (Ro). 1 shows a single-phase bridge inverter with an LC-filter at its output. Let v* and i* be the reference functions for the capacitor voltage and current. this becomes where g = g(T) and is defined in eqn.1 System modelling The discrete-time deadbeat control method is developed here. which is nonsingular. If we define error variables as then the equation for the error variables becomes Fig. with no delay in the application of the manipulated variable. 9. No. the 2 × 2 matrix eA(1–γ)T [g g] is nonsingular. January 1999 Fig. While the computations are performed. poles of the closed-loop system would shift away from the origin. (k + 1)T] . and only if.2 Control method where 2. 9 has to be established first.. The robustness of the control system depends on the sensitivity of the poles to load variations. The closed-loop system state equation is Since the system is state-controllable. t2] in which the input vi is constant as follows: where or where where U is the 2 × 2 identity matrix. 2 it is assumed that the inverter output voltage vi is averaged. Control computations are assumed to be completed within this delay period. poles of the closed-loop system can be placed at any desired locations. 1. Mo has rank equal to 3 if. 1 can be discretised in an interval [t1. With the capacitor voltage v and the current i as state variables. respectively. the system in eqn. it is assumed that the control voltage vi [(k – 1)T] for the previous sampling interval is applied to the filter. all the poles are required to be at the origin. Hence. where T is the sampling period. 6. and = (T). u = vi and If we define a new state variable as then the system in eqn. For deadbeat control. Controllability of the system in eqn. The load is assumed to be resistive R. 6 can be put into the following form: Eqn. Vol.2 Switching strategy in sampling interval The pulse width of the actual inverter output voltage is calculated as The error at the end of the kth sampling interval is obtained as 124 … .-Electr.2 Control strategy Assume that linear state feedback of the form is applied to the system in eqn. 2. 2. 10 can be performed to give Using the definitions in eqn. Power Appl. 9 is completely state-controllable. The controllability matrix of this system is The matrix operations in eqn. Note that the latter matrix is the controllability matrix of the system. Fig. In eqn. 2 shows a switching interval [kT. As the load resistance changes. since the system is of the third IEE Proc. It is not possible to obtain analytically the loci of the poles as the load changes.

However. 23 can be made small if ωL << R. January 1999 125 . 27 is quite tedious. 24) for the total variables: in which the matrices . R must be measured online and vi*(k) be calculated as R changes. using eqn. the state equation for the errors for the case R ≠ Ro is If the first element of the vector z(k + 1) is equated to zero (for the deadbeat control of output voltage v). following a procedure similar to one proposed elsewhere [8]. The error in the output voltage resulting from this approximation when the load resistance changes (R ≠ Ro) can be calculated using the state equation (eqn. 25 and then fixed. 24. 3 Reference functions Substituting the feedback law in eqn. The phasor equation for the filter-load system with R ≠ Ro in the steady-state can be written as When R = Ro. Note that the inverter voltage reference is a function of the load resistance R. 18 is written for three consecutive sampling intervals. Now assume that the reference functions are evaluated for R = Ro using eqn. Eqn. 13. 27 can be solved to obtain the steady-state errors in the state variables and the inverter voltage. and the gain vector Kn is evaluated at Ro. 2 with such a load would be described by where hL is a vector that is a function of the load current. eqn. this reference is specified first. Then. Even though this could be accomplished with the proposed control IEE Proc. the phasor equation is Substituting eqn. This condition can be met by a suitable design of the system.3 Extension to general load The proposed control strategy can be easily modified for a general load. Given that then we obtain and f*(k) contains the terms with the reference functions in eqn. 28 gives where ω = 1/√(LC). 25 and the definitions in eqn. this would increase the computation time and restrict the switching frequency. (In Section 4. we make the observation that the second term in eqn. vi* can then be calculated at Ro and stored in the controller memory.. loci are computed for a sample system chosen for computer simulations. 13 is then modified as where ∆vi′ is a correction term introduced to take care of the load current. Note that in this model R would be taken as infinity. continuous-time approximations can be utilised if the sampling frequency is much higher than the fundamental output frequency. The closed-loop system becomes where D is a vector that is a function of the load current. Solution of this equation would result in complicated expressions for i*(k) and vi*(k). 27 note that the matrices e and B are evaluated at R. the closedloop system becomes where The reference functions for the state variables and the inverter voltage (x* and vi*) are given by the following equation (resistive load case): Since the output voltage v is required to follow a specified reference v*. Power Appl. On the other hand. 20. The system in eqn. c and d are computed at R ≠ Ro. 1. the steady-state errors can be estimated by making continuous-time approximations. 3. The control law in eqn. and c is the closed-loop system matrix in eqn. then ∆vi′ (k) can be solved from the resulting equation in terms of its previous values. To overcome this difficulty. This implies that. In eqn. Reference functions for the case R = Ro are given by where o denotes that these quantities are computed at R = Ro. Here. 29 in eqn. 26. we obtain strategy. a brief outline of this modification is described. No. analytical solution of eqn. If eqn.) 2.order. and the results would be difficult to interpret. A general load (linear or nonlinear) can be represented by the current iL(t) it draws from the capacitor (current source load). On the other hand.-Electr. Vol. 14. 146. in order to be able to apply this reference. The references for the capacitor current i and the inverter voltage vi can then be solved from eqn.

with firing angles of 86° and 266° in the positive IEE Proc. January 1999 . Power Appl.4918 and k3 = –0.-Electr. No. Vol. The loci clearly show that the system stays stable for all possible values of the load resistance.54 0. 4 and 5 show the load voltages with R = Ro = 2Ω and R = 2000Ω.6 15.99 15.023V and 1. b R < Ro Fig. 13).5 as k1 = –7. the error caused by using a fixed reference function for the inverter voltage is negligible.0kHz and Ro = 2Ω. Hence. C = 200µF. 146.51 V1 (V) 15. δ is defined as A sample calculation given below and simulation results show that this error is negligibly small. Figs. solving for ∆V comparison of total harmonic distortions (δ) and fundamental amplitudes of these waveforms with Hua’s [5]. the system becomes overdamped and the model used for feedback control becomes invalid. 13 can be written in terms of phasors as where k1. 1. Note that the computed load voltage waveform confirms the estimation of error in the load voltage.7657. Table 1: Computed total harmonic distortions (δ) and fundamental amplitudes of load voltage DCCD Two-level method Fig. L = 500µH.10 V1 (V) 14. Fig. Also note that Then. k2 = –7..8Ω. Vm = 15V. The load is a triac-controlled resistive load. 4 Computer simulations Fig.01°. 3 shows the loci of the closed-loop poles as R changes.04 δ(%) 0.3 Root loci of closed-loop deadbeat control system a R > Ro. The theoretical error in the output voltage for R = 2000Ω is calculated using eqn.∆Vi can be eliminated in eqn. and fundamental amplitudes are more accurate. The gains are computed for R = Ro and γ = 0.5 Load voltage waveform for R = 2000 Ω It can be observed that the deadbeat control approach here (DCCD) has superior steady-state performance over existing deadbeat control approaches. Total harmonic distortions are considerably lower.4 Load voltage waveform for R = 2 Ω Hua’s inverter system [5] is chosen for the comparison of simulation results.6 Fig. fs = 9. When R is less than 0. Furthermore. k2 and k3 are the elements of Kn. The parameters of this system are Vs = 40V. Table 1 shows the 126 δ(%) R = 2Ω R = 2000Ω 0. 33 as The load voltage amplitude and phase shift with respect to V* for this case are 15. respectively. this case is excluded from this analysis. 6 shows the response of the load voltage to a nonlinear load .12 0. respectively. In the steady-state eqn.6072. 30 using the control equation (eqn.

0%. Vol. Experimental results were obtained that correspond to the simulation cases. respectively.. 127 IEE Proc. Total harmonic distortions of these waveforms were measured as 1. 146. January 1999 . 10 shows the output voltage waveform for openloop operation of the inverter with the nonlinear load. A 16MHz Intel 87C196KR microcontroller was used to control the inverter.-Electr. the response time is considerably shorter than Hua’s [5]. Figs. 1. 9.8 Experimental load voltage waveform for R = 2000 Ω Fig. PWM control signals were accurately generated using the PWM mode of the microcontroller’s peripheral transaction server (PTS).4% [5]. respectively. The total harmonic distortion of voltage is 8. The reason for higher values of δ here is the greater change in load voltage resulting from the delayed application of the control voltage vi(k) .9 Experimental load voltage waveform for nonlinear load Fig.and negative half-cycles. The experimental distortions are higher than the simulation values because of the additional distortion caused by noise disturbances in the practical system. No. respectively. 5 Experimental results Operation of the proposed control strategy was experimentally verified on a microcontroller-based system. 8 and 9 show the experimental output voltage waveforms for the R = 2Ω. In Fig.10 Experimental load voltage waveform for nonlinear load in openloop operation Fig. Power Appl. The distortion caused by noise is noticeable on the experimental waveforms.1%. Fig. 7. It can be observed that the experimental results are in good agreement with the simulation results.5%.7% and 11. The distortion of this voltage is unacceptably large. note that the transient response of the voltage is quite similar to the simulation. compared with Hua’s 6. On the other hand.6 Load voltage and current waveforms for nonlinear load Fig. R = 2000Ω and the triac load cases. This improvement is because the pulse width is only restricted by the sampling period. 1.7 Experimental load voltage waveform for R = 2 Ω Fig.

The mathematical model obtained for the proposed control system is observed to involve a load-dependent reference function for the inverter output voltage.: ‘Instantaneous feedback controlled PWM inverter with adaptive hysteresis’... Power Electron. 1988. New Jersey.. and HOFT. Power Electron. R. CHUARAYARATIP. Theoretical and simulation results have been verified through experiments. IEEE Trans.. 1991. (4). pp. 769–775 2 ABDEL-RAHIM. T. N. (1). IEEE Trans. Power Appl. and HANEYOSHI. pp. 1995. 1990. pp. IEEE Trans. Ind. C.. Y. 146. Proceedings of IEEE Power electronics specialist conference... and HOFT. 6 Conclusions voltage. Ind. R. A. (1). K.. K. Computer simulation results are compared with those of similar deadbeat control strategies. MIYASHITA. 1996. 11. Electron. Y. the time made available to the controlling processor is increased. resulting from the delay in the application of control. Transient response to nonlinear loads is faster. 310–317 6 KAWABATA.G. Vol.: ‘Deadbeat control of a three-phase inverter with an output LC-filter’.. Englewood Cliffs.: ‘Digital control of three-phase PWM inverter with LC filter’. Power Electron. and QUAICOE. IEEE Trans. 1996. (2).: ‘Deadbeat control of PWM inverter with modified pulse patterns for uninterruptible power supply’. pp. 7 References Deadbeat control of single-phase UPS inverters with delayed application of the control voltage has been described. 16–23 9 OGATA. 1985. 10. but has greater undershoot or overshoot in load 1 KAWAMURA.. T. pp. IEEE Trans.P. Appl.: ‘Discrete-time control systems’ (Prentice–Hall. 295–300 5 HUA. leading to the possibility of more functions being implemented on the processor with reduced hardware complexity. The approach presented here leads to improved steady-state performance. 532–541 3 GOKHALE. pp. 1.. (4).E.. J. Furthermore. (3). 1985) 128 IEE Proc. 62–72 8 KUKRER.. 21–28 7 KAWABATA. the use of a fixed reference evaluated at the rated load is seen to lead to a negligible error in the load voltage. This approach allows the use of much higher sampling frequencies than existing deadbeat control strategies. the output filter size can be reduced for the same output waveform distortion by increasing the sampling frequency. 28–36 4 KAWAMURA. However. 1984.. Since higher frequencies are possible with the proposed method. T. (1). 11. MIYASHITA. A. January 1999 . T. R. and YAMAMOTO.: ‘Analysis and design of a multiple-feedback loop control strategy for singlephase voltage-source UPS inverters’.showing the effectiveness of closed-loop control for such loads. O..: ‘Dead beat control of three phase PWM inverter’. IEEE Trans. T. 6. Power Electron. pp.. and YAMAMOTO.. 35. pp.-Electr.: ‘Deadbeat microprocessor control of PWM inverter for sinusoidal output waveform synthesis’. 5.: ‘Two-level switching pattern deadbeat DSP controlled PWM inverter’. IA-20. IEEE Trans. Power Electron.M. No.

Sign up to vote on this title
UsefulNot useful