SFF SDR development platform

Model-based design tutorial

Version 3.1—May 2010

Revision history
Version
1.0 1.1 2.0 3.0 3.1

Date
2008-05-01 2008-06-01 2009-04-14 2009-09-08 2010-05-12 First edition.

Modifications

Corrections of erroneous information and instructions. Updated to account for releases 3.0.0 and 3.1.0 of the ADP software tools. First official release. Updated to account for release 3.2.0 of the ADP software tools. Updated to account for release 4.1.1 of the ADP software tools.

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Lyrtech Inc. All rights reserved.

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........................... 24 Stopping and disconnecting ............................................................................................................................................................................................................. 19 Configuring the simulation parameters .......................................................................................................................................................................... 16 Goals .............................................................................. 1 Purpose and structure.................................................. 5 Software requirements .......................... 19 Targeting the FPGA ............................................................................................................................................................................................................................................................................................................................................................................................................................... 3 Requirements ................................................................................................................................................................................................................................................................................... 6 Using the platform’s DSP ............................................ 1 Glossary of terms ........................................................................................................................................................................... 25 v ......................................................................................................................................................... 19 Tutorial 3—Incorporating an FPGA in a Simulink simulation ........................... 5 Accessing the platform’s documentation .................................................................................................................................................. 25 Tutorial 4—Using VPSS for streaming application in the FPGA model ........................................................................................................................................................................................................................................................................................................................................................................ 7 Tutorial 1—Audio loopback simulation .................................................................. 16 Running the model on your platform ......................................................................................................................... 19 Goals .........Table of contents Introduction............................................................................................ 7 Creating a new model .............. 10 Running the model on your platform ................................................................................................................................................................................................................................................................................................................................................................................................................................................................... 11 Tutorial 2—Processing an audio signal with a FIR filter ............................................................................................................................. 23 Observing the results .................................................................................................................... 5 Preliminary readings .............. 7 Goals ......................................................................... 16 Modifying an existing model ...................................................... 23 Running the model ................................................................................................................................................................................................. 2 Technical support .................................................. 17 Using the platform’s FPGA .......... 7 Targeting the DSP .... 19 Creating a new model ....................................... 23 Saving the model ............................................................ 7 Simulating the model ..................... 1 Conventions ............................................... 5 DSP development software............................................................................................. 5 General .......... 5 FPGA development software ........................... 24 Using the platform’s mixed processor architecture.............

..................................................... 36 Building the model ......................................................................................................................................................... 28 Running the model on the platform ........................................................................................................................................................................................................................................ 28 Modifying an existing model ........................... 38 Connecting to the target and running the model ......................................................................................................................................................................................................................................... 39 vi ................. 36 Tutorial 7—Using the data conversion and RF modules in a DSP model............ 25 Creating a new model .................................................................................................................................. 33 Modifying an existing model ............................................................................................. 33 Goals .................................................................................................. 28 Goals ....................................................................................................... 36 Saving the model .................................... 27 Building an FPGA model...............................................................Goals ....................................................................................................................................................................... 27 Observing the results ......................................................................................................................................................................................... 36 Observing the results ........................................... 36 Goals ..................................................................... 30 Using the data conversion and RF modules .. 25 Saving the model ......................................................................................... 36 Modifying an existing model ....................... 33 Building the FPGA model ............................................................................................................................................................................................................................................................................... 27 Tutorial 5—Using the VPSS to stream data in a DSP model .......... 33 Tutorial 6—Using the DAC in an FPGA model .................................................................................... 39 Stopping and disconnecting .............................................................................................................................................................................................................. 38 Observing the results .........................................................

3…). The guide includes of number of specific elements that you should understand prior to reading it. 1 . c…) are be used to indicate secondary steps in a complex procedure. The document treats of DSP designs and FPGA designs and. The abbreviation N/A is used to indicate something that is not applicable or not available at the time of press. This symbol is used to call your attention to information that may prove useful in operating your product. and options) appear in bold font style (for example. text boxes. The diamond (◊) is used to indicate single-step procedures. once your are done. b. Lowercase letters (a. but is not vital to correct operation. This symbol is used to call your attention to important information. commands. Capitals are used to identify keys on the keyboard (for example. File). Purpose and structure This step-by-step approach can prove useful in mastering the intricacies of model-based design with your platform. The abbreviation NC is used to indicate no connection. All software user interface words (for example. as they will help you understand the way the information is organized. Conventions In a procedure containing several steps. you will be able to perform a narrow-band FM transmission to the FRS handset supplied with the low-band platform. the operations that you must perform are numbered (1. CTRL+V). dialog boxes. crucial to the correct operation of your product. 2. names of menus.Introduction Introduction This document goes over one of the applicative examples supplied with the SFF SDR development platforms.

Stands for hardware description language. Lyrtech development platforms. Host CPU of the cPCI chassis system. Design loaded by default on Lyrtech boards used for FPGA design. Base design Board software development kit Chassis Computer communication development cPCI cPCI chassis system cPCI CPU Default design Digital signal processing Digital signal processor (DSP) Example Eurocard HDL 2 . and HDL code for the FPGA through an understanding of all Lyrtech boards’ major interfaces. Abbreviated BSDK. library. this kit gives users the possibility to quickly become fully functional developing C/C++ or assembly code for the DSP. and tampering. moisture. Refers to a European standard format for printed-circuit boards that can be connected together in a standardized subrack. Digital signal processing is the study of signals in a digital representation and the processing methods of these signals. Refers to developing custom communications applications to communicate with Lyrtech boards. examples come in two flavors: application examples and functional examples. refers to a 3U or 6U Eurocard-based industrial computer where the all boards are connected through a passive PCI backplane. Refer to the following table as to their definitions. Short for CompactPCI. For this reason.Introduction Glossary of terms Throughout this document. responsible for processing and communications between the hardware in the cPCI chassis and the remote computer connected to the cPCI chassis system. Refers to examples used to demonstrate functions or applications supplied with the board software development kit. or application provides to allow requests for services to be made of it by other computer programs or to allow data to be exchanged between them. Refers to the rigid framework onto which the CPU board. The algorithms required for DSP are sometimes performed using specialized devices that use specialized microprocessors called digital signal processors (DSP). Table 1 Glossary of terms Term Application programming interface (API) Definition An application programming interface is the interface that a computer system. Empty design or template that is incapable of data processing and is not instantiated in the custom logic of the board’s FPGA. generally in real time. you will find references to the following terms. A digital signal processor is a specialized microprocessor designed specifically for digital signal processing. Refers to the chassis-CPU board-case system. It also supports the shell-like case—the housing that protects all the vital internal equipment from dust. and other equipment are mounted.

Refers to all the Lyrtech board-specific tools and software used for development with the boards in MATLAB and Simulink and the Lyrtech model-based design kit(s). Abbreviated TX. Any data transmitted by the referent is a transmission. and FPGA software development. Refers to development performed with and for the board with a software development kit. first refer to the documentation accompanying the product. These API are supplied with the Lyrtech board. Model-based design Reception Reference design Software development Transmission VHDL VHSIC Technical support Lyrtech is firmly committed to providing the highest level of customer service and product support. Any data received by the referent is a reception.com. The host may be a standard computer or the CPU board of the cPCI chassis system where the Lyrtech board is installed.lyrtech.Introduction Term Host Definition A host is defined as the device that configures and controls a Lyrtech board. but third parties may enhance or modify the design as necessary. It is intended for others to copy and contains the essential elements of a working system (in other words. Software development for a board comes in three flavors: host software development. If you experience any difficulties using our products or if it fails to operate as described. You can develop applications on the host for Lyrtech boards through the use of an application programming interface (API) that comprises protocols and functions necessary to build software applications. 3 . DSP software development. Abbreviated RX. Stands for VHSIC hardware description language. If you find yourself still in need of assistance visit the technical support page in the Support section of our Web site at www. it is capable of data processing). Blueprint of an FPGA system implanted on Lyrtech boards. Stands for very-high-speed integrated circuit.

Introduction 4 .

we recommend that you familiarize yourself with the following.Requirements Requirements Before you can use your SFF SDR development platform in developing model-based designs. For details about the exact software versions supported by your SFF SDR development platform. refer to your platform’s quick start guide. the following software must be installed on your computer: General • • • • • Advanced development platform (ADP) software tools MATLAB Simulink Signal Processing Blockset Signal Processing Toolbox You should be familiar with MATLAB and Simulink before proceeding. Software requirements To complete all the tutorials in this guide. DSP development software • • Code Composer Studio Real-Time Workshop FPGA development software • • System Generator for DSP ISE Foundation Preliminary readings Before going through this guide. you must meet the requirements outlined below. to help you gain a working knowledge of the SFF SDR development platform’s capabilities: • • • SFF SDR development platform user’s guide SFF SDR development platform model-based design guide FAQ supplied with the platform 5 .

6 . SFF SDR. point to All Programs. Your default Web browser starts and displays a page containing links to all the documents supplied with the SFF SDR development platform. Point to Lyrtech.Requirements Accessing the platform’s documentation 1 2 On the Windows Start menu. and then click Documentation.

The Models Properties dialog box appears. They are not intended to represent actual results. On the File menu. it rather forces the block to run at a frequency relative to other blocks’ Sample Time values. Targeting the DSP To target the DSP of your platform with the model-based design kit (MBDK) from Lyrtech. in the Model pre-load function group. Simulate the model. This means that specifying a Sample Time of 1 does not force the block to run at 1 Hz. It is the sampling frequency of the audio path used later on in this tutorial. At the MATLAB command prompt. The Fs_DSP variable appears as 32000 when you open the model for the first time. point to New. The results presented in this chapter are only supplied for illustration purposes. Right-click anywhere in the model window.Using the platform’s DSP Using the platform’s DSP In this chapter. and then click Model. you will learn how to use Real-Time Workshop and Code Composer Studio to target the Texas Instruments DM6446 DSP of your platform. you must always perform certain procedures: 1 2 3 Create a new model or modify an existing model. Run the model on the platform. Tutorial 1—Audio loopback simulation Goals • • • Demonstrate how to use Simulink to build a simple design and perform a simulation Demonstrate how to configure the audio codec Demonstrate how to configure a Simulink model to monitor data and perform remote operations Creating a new model 1 2 3 4 Start MATLAB. On the Callbacks tab. and then click Model Properties on the shortcut menu that appears. type simulink. Fs_DSP = 32000. 5 Use the sample time as a relative time base. 7 .

mat file to save your MATLAB workspace parameters. and then reopen it. If no I/O block forces the DSP to run at a specific sample rate. block B runs twice as fast as block A. Alternately. the time to execute a frame) is imposed by the following formula: Frame time = Sample Time × Frame Size By default. the DSP runs the code as fast as possible. for example). You can also use a . In other words. This configures the default simulation parameters of your SFF SDR development platform. If you also specify a Frame Size. the DSP is free running. Connect the blocks as illustrated. In other words. Refer to Simulink Help to learn more about model properties. 24 kHz) run at the same sample rate. its associated code is executed twice as fast as that of block A. This means that all the other blocks having the same sample time as the I/O block (e.Using the platform’s DSP For example.e. exit the model. However. Using the model properties is a good way to ensure that all your parameters remain with your . 6 To add the Fs_DSP variable to the MATLAB workspace parameters.g. 8 . then the Sample Time is associated to the effective sample rate configured in the block (24 kHz. type Fs_DSP = 32000 at the MATLAB command prompt. if you insert an I/O block such as an audio ADC block in your model. if you specify a Sample Time of 2/48000 for block A and block B has a sample time of 1/48000.mdl file. then the actual frame time (i. Insert the following blocks in the new model: Signal processing Blockset—Signal Processing Sinks • 1 × Vector Scope • 1 × Spectrum Scope Lyrtech SFF SDR DP Blockset—DSP—Onboard • 1 × DSP Options • 1 × Audio Codec Configuration • 2 × Audio Codec I/O The following dialog box appears when you add the DSP Options block in your model: Figure 1 MBDK DSP default configuration dialog box 7 8 9 Click Yes. the Sample Time is 1.

they are executed at the base sample time). Refer to Simulink Help to learn more about this function. In the model at hand. point to Port/Signal Displays. point to Port/Signal Displays. indicating that all the blocks have the same sample time (i. and then click Port Data types. Selecting Signal Dimensions is a good way to have an overview of the dimensions of the signals. 12 On the Format tab. Selecting Port Data types is a good way to have an overview of the data types of every link in your model. and then click Sample Time Colors. point to Port/Signal Displays. Selecting Sample Time Colors is a good way to have an overview of the sample times of every block in your model.Using the platform’s DSP Figure 2 Connecting blocks in the model 10 Configure the blocks as follows Audio Codec Configuration • Sampling Frequency: 32 kHz • Frame Size: 128 • Sample Time: 1/Fs_DSP Audio Codec I/O • Frame Size: 128 • Data Type: Single • Select the Normalize ADC samples check box • Sample Time: 1/Fs_DSP • Direction: Input Audio Codec I/O1 • Frame Size: 128 • Data Type: Single • Select the Normalize Audio Data Samples check box • Select the Enable Data Saturation check box • Sample Time: 1/Fs_DSP • Direction: Output 11 On the Format menu. all the blocks become red. particularly when they are frame based. 13 On the Format tab. Refer to Simulink Help to learn more about this function.e. and then click Signal Dimensions. Refer to Simulink Help to learn more about this 9 .

Using the platform’s DSP function. Right-click anywhere in the windows and click Autoscale on the shortcut menu that appears. Select the simulation’s mode as Normal. The following results are expected. Click the play button. Alternately. Figure 4 Time domain and frequency domain simulation results 10 . The values on the x and y axes are accurate in terms of frequency and time because the sample time value is equal to the sample time of the audio codec sampling frequency. click Update Diagram. Figure 3 Updated model Simulating the model 1 2 3 4 On the model’s toolbar. 14 Press CTRL+D on your keyboard. on the Edit menu. Two windows appear. configure the simulation’s stop time as 1.

Configuring the hardware implementation model 1 2 If not already open. on the model’s Simulation menu. This parameter.tmf. however. The Configuration Parameters dialog box opens. The following appear. click Configuration Parameters. Select Solver.tlc and that Template makefile is rt_sdr. Select Hardware Implementation. On the Solver list. 11 . The following appears. select Fixed-step. you must perform the procedures outlined in this section. determines the default time range of Simulink scopes when their Time range parameters are auto. click Configuration Parameters. The Configuration Parameters dialog box opens.Using the platform’s DSP Running the model on your platform To take your simulation model and implement it on the SFF SDR development platform. Real-Time Workshop configuration parameters Figure 5 3 Verify that System target file is rt_sdr. The Configuration Parameters dialog box appears. On the Type list. Configuring the Real-Time Workshop target 1 2 On the model’s Simulation menu. regardless of the Stop time parameter. Select Real-Time Workshop. on the model’s Simulation menu. select discrete. The code generated by the MBDK DSP solution runs indefinitely. Configuring model Solver parameters 1 2 3 4 If not already open. click Configuration Parameters.

b Expand Real-Time Workshop. Verify that your model is configured properly: a On the model’s Simulation menu. click Configuration Parameters. and then select Interface. The Configuration Parameters dialog box closes. Click OK. the ### Created Executable :{model name} message appears in the MATLAB window. and then click Build Model. ◊ On the toolbar of the model window. When the build is successful. Connect headphones or speakers to the line out connector. Press the hardware reset button. click the build button. click External. Refer to the platform’s user’s guide for the location of this button. You can also point to Real-Time Workshop on the model’s Tools menu. press CTRL+B on your keyboard. On the model’s Simulation menu. Connect an audio source such as an MP3 player to the line in connector. the building folder is always your current MATLAB folder.◊ Alternately.Using the platform’s DSP Figure 6 Hardware Implementation parameters 3 4 Make sure that the Device type is TI C6000. Building the model When building a DSP model. Running the model 1 2 3 4 5 6 Make sure that your platform is on and that an Ethernet cable is connected to its Ethernet port. c Verify that the following parameters are configured as illustrated: 12 .

For details about targeting the DSP with the MBDK DSP solution. refer to the model-based design guide of the SFF SDR development platform. Your audio signal is displayed on the time and vector scopes.out file is loaded to the DSP of the platform. For a better real-time display quality in the scope. and then click Connect to Lyrtech development platform. Lyrtech development platform detection dialog box Figure 8 9 When the . the model starts automatically. Select a platform that is not in a locked state. Observing results The scopes react according to the signal fed to the platform. proceed as follows: 1 On the Tools menu. In the model window.Using the platform’s DSP Figure 7 Interface selection d 7 8 Click OK. 13 . The actual aspect of the scope depends on the audio signal. click External mode Control Panel. Use the auto-scale feature. click the connect to model button. if necessary. The Lyrtech development platform detection dialog box appears.

Using the platform’s DSP Figure 9 External mode control panel 2 3 Click Signal & Triggering. and disconnecting 1 2 3 Click Disconnect from target. As a rule. Click Close. 14 . when frame based. the Data Logging Size (in the DSP Options block) should be greater than the Duration value multiplied by the frame size and the number of scopes. Saving. Figure 10 External Signal & Triggering 4 5 Click Apply. Close the model. stopping. In the External Signal & Triggering window. You must not be connected to the platform to modify this parameter. type 1 in the Duration text box.mdl. Save the model as my_tutorial1.

Tutorial 2—Processing an audio signal with a FIR filter Goals • • Demonstrate how to use the FDA design block Describe various data types supported by the MBDK DSP solution• Using the platform’s DSP Modifying an existing model 1 2 Open the my_tutorial1.mdl file (if you have not completed tutorial 1).mdl file or the tutorial1. Connecting the blocks Figure 11 4 Configure the blocks as follows: Data Type Conversion block • Output data type mode: single • Input and output to have equal: Real World Value (RWV) Buttons block • Sample Time: 128/Fs_DSP • Select the Button 1 check box 15 . Insert the following blocks in your model: Simulink—Math Operation • 1 × Add Simulink—Signal Routing • 1 × Switch Simulink—Signal Attributes • 1 × Data Type Conversion Signal Processing Blockset—Filtering—Filter Designs • 1 × Digital Filter Design Lyrtech SFF SDR DP Blockset—DSP—Onboard • 1 × Buttons 3 Connect the blocks as illustrated.

point to Real-Time Workshop. you can click the connect to target button. as is the case of most MP3 files). Observing the results You should see and hear the differences in your signal between when you press button S5 and when you do not (assuming that your signals are at frequencies higher than 3 kHz. On the model’s Simulation menu. and disconnecting 1 2 3 Click Disconnect from target. and then click Build Model. Connect an audio source such as an MP3 player to the line in connector. Alternately. select Hz. specify 10 for Wpass and 1 for Wstop. Connect headphones or speakers to the line out connector. In the Magnitude Specifications group. In the Response Type group. and 3300 for Fstop. In the Design Method group. Alternately. Refer to the platform’s user’s guide for the button’s location. click Connect to target. stopping. Alternately. When the Designing filter… Done message appears at the bottom of the window. 3000 for Fpass. 16 . In the Frequency Specifications group. Saving. Click the play button.Using the platform’s DSP • Clear the Button 2 to Button 5 check boxes Switch block • Criteria for passing first input: u2 > Threshold 5 Double-click the Digital Filter Design block. close the Digital Filter Design window. Click Design Filter. select Specify order. In the Frequency Specifications group. select FIR. Running the model 1 2 3 4 5 6 Make sure that your platform is on and that an Ethernet cable is connected to its Ethernet port. Press the hardware reset button. select Lowpass.mdl. and then select Least-square. Refer to the platform’s user’s guide for the location of this button. specify 32000 for Fs. Save the model as my_tutorial2. 6 7 8 9 10 11 12 13 Running the model on your platform To take your simulation model and implement it on the SFF SDR development platform. Close the model. on the Units list. In the Filter Order group. The Digital Filter Design block implements a digital FIR or IIR filter that you design with the filter design and analysis tool (FDA Tool). you must perform the following procedures: Building the model ◊ On the model’s Tools menu. you can press CTRL+B on your keyboard. and then specify 4 in the text box. press CTRL+T on your keyboard.

you will be called upon to create an FM modulator simulation with System Generator for DSP. • • • Make sure that System Generator for DSP is installed on your computer before proceeding with the • tutorials of this chapter. The results presented in this chapter are only supplied for illustration purposes. On the File menu. To achieve this goal. you will learn how to use the platform’s FPGA in your models. Targeting the FPGA To target the FPGA on your platform with the MBDK. Creating a new model 1 2 3 4 Start MATLAB. 17 . They are not • intended to represent your actual results. For illustration purposes. Demonstrate how to use the System Generator for DSP’s DDS v5_0 block. shortening simulation time. Run the model on the platform.Using the platform’s FPGA Using the platform’s FPGA In this chapter. The model used in this chapter will be reused and adapted later on to demonstrate transmissions to an FRS handset (supplied with the platform). and click Model Properties on the shortcut menu that appears. point to New. Simulate the model. You will design the simulation for narrow-band FM with a 100 kHz carrier frequency. No floating-point data types are available. In System Generator for DSP all the data paths are always sample based. that model is configured with an FPGA system clock of 1 MHz. Tutorial 3—Incorporating an FPGA in a Simulink simulation Goals • • Demonstrate how to use System Generator for DSP to perform a simulation. you must perform certain procedures. just as with the DSP: 1 2 3 Create a new model or modify an existing model. Right-click anywhere in the model window. At the MATLAB command prompt. type simulink. but all the data type are • fixed point. and then click Model.

controlled by the data port.bit) for the FPGA. 7 Connect the blocks as illustrated. A sampling time of 1 would produce the same bitstream file (. which is then sent to the data port of the DDS v5_0 block. Refer to System Generator for DSP Help for details. A constant corresponding to the carrier frequency is added to the amplitude from the Sine Wave block. thus changes as the amplitude of the sine wave changes. In a Simulink model. The Fs_FPGA variable is created and becomes the frequency of the system clock. Using a variable allows you to switch all the sample times of your design simultaneously. while sometimes it is useful to do so in terms of seconds. For the spectrum scope and time scope. the sample time is merely a tag on each “step” of an algorithm. 5 On the Callbacks tab. The sampling frequency specified in each block is not imposed on the FPGA clock. it is sometimes useful to see the results of the simulation in terms of clock cycles. The frequency output. type Fs_FPGA = 1e6.Using the platform’s FPGA The Model Properties dialog box appears. Use a sample time of 1 for clock cycle information and a clock period cycle for the time domain and frequency domain information. 6 Insert the following blocks in the new model: Simulink—Simulink Sink • 1 × Scope Simulink—Signal Attributes • 1 × Data Type Conversion Simulink—Signal Routing • 1 × Manual Switch Signal Processing Blockset—Signal Processing Sources • 1 × Sine Wave • 1 × DSP Constant Signal Processing Blockset—Signal Processing Sinks • 1 × Spectrum Scope Xilinx Blockset—Index • 1 × System Generator • 1 × Gateway In • 2 × Gateway Out • 1 × CMult • 2 × Const • 1 × AddSub • 1 × DDS v5_0 DDS stand for direct digital synthesizer. 18 . It is the main block used in this model. in the Model pre-load function group.

specify Buffer Size as 2^12 • On the Axis Properties tab. select the Buffer Input check box • On the Scope Properties tab. 19 . click the parameters button. In the Axes group. double-click the scope block. specify Frequency display limits as User-defined • On the Axis Properties tab.Using the platform’s FPGA Figure 12 Connecting blocks in the model 8 Configure the blocks as follows: Data Type Conversion block • Output data type mode: int16 • Input and output to have equal: Real World Value (RWV) Sine Wave block • Amplitude: 2^15-1 • Frequency: 3000 • Sample Time: 1/Fs_FPGA • Output Data Type: single Spectrum Scope block • On the Scope Properties tab. modify Number of axes to 2. Click OK. In the window that appears (below). specify the Minimum X-limit as 90 and the Maximum X-limit as 110 System Generator block • Simulink System Period: 1/Fs_FPGA Gateway In block • Number of bits: 16 • Binary point: 0 • Sample period: 1/Fs_FPGA Gateway Out block • Clear the Translate into output port check box Const block • Clear the Sampled Constant check box DDS v5_0 block • Function: sine and cosine • Output Frequencies: Programmable • Explicit Sample Period: Inferred from inputs • Clear the Provide enable port check box To get two inputs from one scope.

13 Double-click the AddSub block. To determine how many bits the port needs. 15 Double-click the Constant block connected to the AddSub block.2)). 10 Double-click the DDS v5_0 block. A lower clock frequency means less points to calculate. specify the number of bits as 23.5e3/1e6)*2^(23–15) as the Value. select Block RAM. select type Boolean and constant value 1. use 1 MHz. This impacts the number of bits of the input data type at the data input port. We want a 100 kHz carrier frequency from a DDS with a 1 MHz clock. specify the output type as Signed. type ceil(log2(1e6/0. 11 On the Advanced tab. The last value configures the peak frequency deviation. specify the constant value as (100e3/1e6)*2^23. 16 Select Signed. This lowers the spurious in the output signal by increasing the resolution (bits) of the output. The formula for the modulation index is: 20 . 12 On the 12 Implementation tab. This is the actual clock rate of your hardware clock. • Frequency Resolution (Hz): 0. 17 Double-click the CMult block. The relation is simple: fout P = inc_data_port Pinc_max DDSclock For details on phase incrementation and DDS. indicating that the answer is 23 bits. refers to System Generator for DSP Help. • Spurious free dynamic range (dB): 16*6. • Noise shaping: Phase dithering. Frequency modulation (FM) conveys information by varying the frequency of a carrier signal.Using the platform’s FPGA Figure 13 Getting two inputs from one scope 9 In the Constant block connected to the WE of the DDS v5_0 block. and the binary point as 0. The frequency modulation index indicates by how much the modulated variable varies around its unmodulated level. and the binary point as 0. and the binary point as 16. The carrier frequency is configured through the Constant block connected to the AddSub block. at the MATLAB command prompt. This noise shaping technique is necessary as the SFDR is between 60 dB and 102 dB. As a rule. specify (1.2. specify the following: • DDS clock rate (MHz): 1. specify the number of bits as 16. It is related to the frequency modulation index. The value sent to the data input port is called phase increment. For the purposes of this example. 14 On the Output Type tab. thus a faster simulation. select User-Defined Precision. the number of bits as 23. 1 bit equals 6 dB of SFDR.

Running the model ◊ Click the play button. The boundaries of the design are the points where System Generator for DSP blocks exist. to the corresponding value produced in the hardware. System Generator for DSP produces simulation results that are bit-true and cycle-true to the hardware it generates. To say that a simulation is bit-true means that.1) K = c 1. The peak value of our 16-bit sine wave is 215–1. we need a carrier frequency deviation of 1. The phase increment corresponding to 1. the modulation indices must be smaller than 1. 21 . a value produced in a simulation is identical. interfaces between the System Generator block and non-System Generator for DSP blocks). In Solver options section. press CTRL+T on your keyboard. specify 1 in the Stop time text box. Alternately. you can see a typical FM spectrum around the carrier frequency of 100 kHz.5. click Configuration Parameters. bit for bit. corresponding values are produced at corresponding times. Observing the results On the spectrum scope. Alternately.Using the platform’s FPGA D b= f fm Where fm is the highest modulating frequency and Δf is the carrier frequency deviation. When the System Generator for DSP generates hardware. On the time scope. To say that a simulation is cycle-true means that. We are looking for the constant value K where: (215 .5 # 610 m # 2 23 10 3 Configuring the simulation parameters 1 2 3 4 On the model’s Simulation menu. select Variable-step as the type and discrete as the solver. at the boundaries. therefore. you can see that both DDS output signals are in quadrature with each other. The highest modulating frequency coming from the sine wave is 3 kHz.mdl.5 kHz is equal to (1. you can press CTRL+E on your keyboard. Click OK. Let us use 0.5 kHz. In the Simulation time group. such as FRS. For narrow-band FM.5×103/1×106)×223.g. the Gateway In or Gateway Out blocks become top-level input or output ports. at the boundaries (e. Saving the model ◊ Save the model file as my_tutorial3.

Using the platform’s FPGA Figure 14 Spectrum scope view of FM with a 0. Close the model.5 spectrum index and Time scope quadrature signal Stopping and disconnecting 1 2 Click the stop simulation button. 22 .

you will use the VPSS in transferring data from a DSP to an FPGA. you will use the platform’s codec’s synchronization mechanism and the custom registers. Simulink—Sinks • 1 × Scope • 4 × Terminator Signal Processing Blockset—Signal Processing Sources • 1 × Sine Wave • 3 × DSP Constant Lyrtech SFF SDR DP Blockset—FPGA—Onboard • 1 × FPGA Configuration • 1 × Custom Register • 2 × VPSS Xilinx Blockset—Basic Elements • 1 × System Generator • 3 × Const • 1 × Mux 23 . The Model Properties dialog box appears. To do so. The Fs_FPGA variable’s value is 37. Insert the following blocks in the model. point to New. which becomes the system clock’s frequency. On the File menu. type Fs_FPGA = 37. At the MATLAB command prompt. and then click Model. On the Callbacks tab. type simulink. Tutorial 4—Using VPSS for streaming application in the FPGA model Goals • • • Demonstrate how to achieve codec synchronization Demonstrate how to use the VPSS in a DSP model Demonstrate how to use custom registers to receive DSP control signals Creating a new model 1 2 3 4 5 6 Start MATLAB.5e6. Right-click anywhere in the model window. in the Model pre-load function group.5e6. and then click Model Properties on the shortcut menu that appears.Using the platform’s mixed processor architecture Using the platform’s mixed processor architecture In this chapter.

5 MHz • Select the Synchronize Audio Codec with FPGA System Clock check box • Clock divider: 4 Custom register block • Register ID: 0 • Direction: Read • Output Arithmetic Type: Unsigned • Output Width: 1 • Binary Point: 0 • Sample period: 1024/Fs_FPGA VPSS block • Direction: one RX (the one with the Sine Wave block) and one TX (the one with the scope) • Output Arithmetic Type: Signed • Output width: 32 • Binary Point: 0 • Sample period: 1024/Fs_FPGA System Generator block • Simulink system period: 1/Fs_FPGA Const block for the ren and wen inputs of the VPSS (2) block • Clear the Sampled constant check box • Type: bool • Value: 1 Const block for input d1 of Mux block • Type: Signed • Value: 0 • Sample Time: 1024/Fs_FPGA 24 . Figure 15 Connecting the blocks in the model 8 Configure the blocks as follows: Sine Wave block • Amplitude: 2^15–1 • Frequency: 3000 • Sample time: 1024/Fs_FPGA FPGA configuration block • Clock Source: 37.Using the platform’s mixed processor architecture 7 Connect the blocks as illustrated.

the System Generator block opens a Perl session and uses ISE Foundation tools to create a bitstream from the model’s generated code. where name_of_FPGA_model corresponds to the name of your FPGA model.mdl. the FPGA system clock and the codec clock are the same. When the process is complete. when the building process is complete. To build the bitstream. The code generation process starts for each block of the FPGA model (except for Simulink I/O blocks. select Real-Time Hardware Implementation. This folder also contains the bitstream corresponding to your model. only present for simulation purposes). then Lyrtech.Using the platform’s mixed processor architecture • For data streaming applications. a message appears to inform you of the fact. When the code generation is complete. 1 Configure the FPGA configuration block. c On the Synthesis tool list. select VHDL. Proceed to the next section.bit. The name of the bitstream is name_of_FPGA_model_evm. • Because the Synchronize Audio Codec with FPGA System Clock check box is selected in the FPGA configuration block. specify the folder where the generated FPGA code must be created. b On the Clock Source list. d On the Hardware description language list. b In the Target directory text box.5e6 or less. e In the FPGA clock period and Simulink system period text boxes. click Generate. configure your ren and wen as always asserted. specify 1e9/37. Configure the System Generator block to build the FPGA model. a On the Clock Type list.out of the following DSP model. 25 . point to Hardware Co-Simulation. 2 3 Observing the results This bitstream will be use with the . Saving the model ◊ Save the model as my_tutorial4. select XST. Proceed as follows to do so. you must provide to the MBDK FPGA solution and System Generator for DSP the necessary information to build the model. Building an FPGA model Before you can build an FPGA model. select the hardware clock used by the System Generator for DSP design. a On the Compilation list. and then click SFF SDR DP.

Connecting the blocks in the model Figure 16 26 . Insert the following blocks in the model: Simulink—Signal Routing • Manual Switch (×1) Lyrtech SFF SDR DP Blockset—DSP—Onboard • Custom Register (×1) • VPSS (×2) Lyrtech SFF SDR DP Blockset—DSP—Miscellaneous tools • Set bitstream (×1) • Lyrtech priority manager (×1) 4 Connect the blocks as illustrated. Remove the Digital Filter Design block and Switch block from the model.Using the platform’s mixed processor architecture Tutorial 5—Using the VPSS to stream data in a DSP model Goals • • • • Demonstrate how to use the VPSS in a DSP model Demonstrate how to use the Custom Register for DSP control signal Demonstrate how to achieve codec synchronization in a DSP model Demonstrate how to load a bitstream from the DSP model Modifying an existing model 1 2 3 Open the my_tutorial2.mdl file.

5 MHz/1024 = 36621 Hz). and then click Model Properties on the shortcut menu that appears. On the model’s Format menu. and then click Down until the block is below the VPBE block. 27 . On the Callbacks tab. If it is not. in the Model pre-load function group. Lyrtech priority manager Figure 17 Select the name the VPFE block (by default.Using the platform’s mixed processor architecture 5 Configure the blocks as follows: Custom Register block • Register ID: 0 • Direction: Write to FPGA • FPGA Data Type: Unsigned • FPGA Binary Point: 0 • DSP Data Type: Int32 • Sample period: 128/Fs_DSP Audio Codec Configuration block • Sampling frequency: Defined with FPGA configuration block VPBE block • Packet size: 128 • Data Type: Single • Sample period: 1/Fs_DSP VPFE block • Packet size: 128 • Data Type: Single • Sample period: 1/Fs_DSP Data Type Conversion block • Output data type mode: int32 6 7 8 9 Right-click anywhere in the model window. VPSS Bus or VPSS Bus 1). point to Block Displays. open the Lyrtech priority manager block. This maintains the scope accurate as this is the new sampling frequency of the codec (37. Update your model and make sure that VPBE is smaller than VPFE. type Fs_DSP = 36621. and select Sorted.

28 . and then click Build Model. Alternately. Alternately. Before building the model. Connecting to the target and running the model 1 2 3 4 5 6 Make sure that the SFF SDR development platform is on and that and Ethernet cable is connected to its Ethernet port. Click the play button. save the model as my_tutorial5. Press the hardware reset button.mdl. you can press CTRL+B on your keyboard.Using the platform’s mixed processor architecture Figure 18 Lyrtech priority manager The sorted order of blocks shows the sequence in which each part of the processing is called. Observing the results Toggle the manual switch of the DSP model. Connect an audio source such as an MP3 player to the line in connector. This mutes the audio signal when the manual switch is positioned for the VPFE. Alternately. and then reopen it. 10 Double-click Set Bitstream. On the model’s Simulation menu. point to Real-Time Workshop. Running the model on the platform To take your simulation model and implement it on the SFF SDR development platform. Alternately. close the model. the VPSS port becomes deadlocked. Connect headphones or speakers to the line out connector. and then select the bitstream created during tutorial 4. In the case of the VPBE and VPFE. Refer to the platform’s user’s guide for the location of this button. click Connect to target. proceed as follows: Building the model ◊ On the model’s Tools menu. verify that the value of Fs_DSP is 36621. Normally hearing audio in both switch positions indicates that the VPSS is functioning properly. If it is not. Press the S5 button of the digital processing module. you can click the toolbar’s connect to target button. press CTRL+T on your keyboard. it is useful because if the VPFE is performed before the VPBE. you can type Fs_DSP = 36621 at the MATLAB command prompt.

and disconnecting 1 2 3 Click the disconnect from target button. Close the model.Using the platform’s mixed processor architecture Stopping.mdl. Save the model as my_tutorial5. stopping. 29 .

Using the platform’s mixed processor architecture 30 .

mdl.mdl and my_tutorial4. Tutorial 6—Using the DAC in an FPGA model Goals • • Demonstrate how to use the DAC block Demonstrate how to synchronize with the DAC clock Modifying an existing model 1 2 3 Open models my_tutorial3. Connecting the blocks in the model Figure 19 4 5 Remove the two Gateway Out blocks from the model. Connect the blocks as illustrated. the Spectrum Scope block. Insert the following blocks in the model: 31 . the two Gateway Out blocks. and the Scope block from the tutorial 3 model into the tutorial 4 model. Move the DDS v5_0 block and its Constant block. the Add block.Using the data conversion and RF modules Using the data conversion and RF modules This chapter will help you learn how to include all three modules of your platform into your designs.

Connect the blocks as illustrated. Connecting the blocks in the model Figure 20 8 Configure the blocks as follows: DSP Constant block • Value: ceil((462.5625e6-432e6)/80e6*2^29) • Sample period: 2560/Fs_FPGA Custom Register block • Register ID: 1 • Direction: Read • Output Arithmetic Type: Unsigned • Output Width: 29 • Binary Point: 0 • Sample period: 2560/Fs_FPGA ADACMaster III output (DAC) blocks • Channel ID: One A and one B • Sample period: 1/Fs_FPGA • Binary point: 15 • Mode: DAC 9 Insert the following blocks in the model: Xilinx Blockset—Basic Elements • 1 × Convert • 2 × Upsampler • 1 × Inverter 32 .Using the data conversion and RF modules Signal Processing Blockset—Signal Processing Sources • 1 × DSP Constant Lyrtech SFF SDR DP Blockset—FPGA—Onboard • 1 × Custom Register (×1) Lyrtech SFF SDR DP Blockset—FPGA—Add-on hardware modules • 2 × ADACMaster III • 1 × RF module configuration • 1 × RF module 6 7 Duplicate the Mux and Zero constant twice.

and then configure all the sample time values to 2560/Fs_FPGA. refer to the FPGA configuration block’s Help. modify DDS clock rate to 80. and then configure all the sample time values to 2560/Fs_FPGA. 15 On the Basic tab. 19 Double-click the FPGA configuration block. modify the Number of bits to 29. 21 Select the Synchronize audio codec with FPGA system clock check box. and then configure all the sample time values to 2560/ Fs_FPGA. 26 Double-click the Custom Register blocks. The Fs_FPGA variable’s value is 80e6. For details about valid clock divider values. 24 Double-click the VPSS blocks. Figure 21 Connecting the blocks in the model 11 Configure the block as follows: Upsampler block • Sampling Rate: 2560 • Select the Copy samples check box Convert block • Type: Bool 12 Right-click anywhere in the model window. 16 On the Advanced tab. select Clock source LYRIO+ Sync Bus 1 clock.25 kHz. 13 On the Callbacks tab. 14 Double-click the DDS v5_0 block. 17 Double-click the AddSub block. which becomes the frequency of the system clock. 25 Double-click the Sine Wave block. The Model Properties dialog box appears. in the Model pre-load function group.Using the data conversion and RF modules Signal Processing Blockset—Signal Processing Sources • 1 × DSP Constant Simulink—Sinks • 2 × Terminator 10 Connect the blocks as illustrated. and then configure its sample time value to 2560/Fs_FPGA. and then click Model Properties on the shortcut menu that appears. 23 Double-click the DSP Constant blocks. 22 Specify the clock source value as 80 MHz and the clock divider value as 10. 33 . This creates a codec clock running at 31. select the Negate sine check box. 18 On the Output Type tab. 20 On the FPGA system clock list. type Fs_FPGA = 80e6.

In the System Generator dialog box. Tutorial 7—Using the data conversion and RF modules in a DSP model Goals • • Demonstrate how to configure the RF module to perform an FRS transmission. Save your model as my_tutorial6. Demonstrate how to achieve codec synchronization in a DSP model. close the model. Before building the FPGA model. and then specify 1e9/80e6 as the FPGA clock period.Using the data conversion and RF modules • The negative sine is necessary to get an upper sideband signal from the analog quadrature modulator of the RF module. click Generate. This can be ascertained with a spectrum analyzer. Insert the following blocks in the model: Lyrtech SFF SDR DP Blockset—DSP—Onboard • 1 × Custom Register Lyrtech SFF SDR DP Blockset—DSP—Add-on hardware modules • 1 × RF module • 1 × ADACMaster III control Signal Processing Blockset—Signal Processing Sources • 1 × DSP Constant Simulink—Signal Attributes • 2 × Data Type Conversion 34 . Observing the results The bitstream generated with the System Generator block is used with the . Modifying an existing model 1 2 Open the my_tutorial5. • The number of bits of the DDS data import port is explained in tutorial 3. • The mult is discarded from tutorial 3 because K’s value for FRS specifications nears 1.out file of the following tutorial. If it is not. Saving the model ◊ Save the model as my_tutorial6. and then reopen it. Alternately.mdl. you can type Fs_FPGA = 80e6 at the MATLAB command prompt.mdl file if you did not complete tutorial 5). Proceed to tutorial 7.mdl file (or the tutorial5.mdl. Building the FPGA model 1 2 3 Double-click the System Generator block. verify that the value of Fs_FPGA is 80000000.

mdl to tutorial5. Connecting the blocks in the model Figure 22 9 Configure the blocks as follows: Custom Register block • Register ID: 1 • Direction: Write to FPGA • FPGA Data Type: Unsigned • FPGA Binary Point: 0 • DSP Data Type: Int32 • Sample period: 128/Fs_DSP RF module block • Select the TX check box • TX base frequency: 432 MHz • Reference Clock Source: Onboard 10 MHz • Sample Time: 128/Fs_DSP VPBE and VPFE blocks • Data Type: Int32 Audio Codec I/O In block • Clear the Normalize Audio Data Samples check box 35 . The Model Properties dialog box appears. and then modify the Fs value for 31250. according to your situation).mdl.3 4 5 6 7 8 Using the data conversion and RF modules Right-click anywhere in the model window. This maintains the scope accurate because this is the new sampling frequency of the codec (80 MHz/2560 = 31250 Hz). Drag the Digital filter design tool block from the my_tutorial2. Open the my_tutorial2. in the Model pre-load function group. Double-click the Digital filter design tool block. and then click Model Properties on the shortcut menu that appears.mdl (or from tutorial2. On the Callbacks tab.mdl to the my_tutorial5.mdl file (or the tutorial2. type Fs_DSP = 31250. Connect the blocks as illustrated.mdl file if you did not complete tutorial 2).

you must always work at an IF higher than 3 MHz.5625e6 -432e6) /80e6*2^29) • Data Type: int32 • Sample Time: 128/Fs_DSP • The equation used in calculating the DSP constant is the same as the one presented in tutorial 3 for setting the carrier frequency. Connect headphones or speakers to the line out connector. PLL Reference Time Base: External • On the Clock and PLL tab. Building the model 1 2 Save the model as my_tutorial7. Connect an audio source such as an MP3 player to the line in connector. Because the conversion module gets its clock signal form the RF module. Refer to the platform’s user’s guide for the location of this button. ADC/DAC Clock Source: Use PLL • On the Clock and PLL tab. Press the hardware reset button. close the model.mdl. FPGA design. If it is not. Before building the model.5625 MHz (controlled by the DSP constant) and heterodyned with a frequency of 432 MHz. which is obtained from intermediate frequency (IF) 30. Connecting to the target and running the model 1 2 3 4 36 Make sure that the SFF SDR development platform is on and that an Ethernet cable is plugged to its Ethernet port. Alternately. point to Real-Time Workshop. • Because the DAC and ADC are AC coupled. 10 Right-click the RF Module block and select Block properties. the latter must be initialize first. On the model’s Tools menu.5625 MHz. you can press CTRL+B on your keyboard. 11 Double-click the Set Bitstream block. • On the DAC tab. Additional Reference Time Value: 10 • On the Clock and PLL tab. Enter the value 0 in the Priority field. select the Enable DAC check box. and then click Build Model. and DAC: 80 • On the Advanced tab. select Full Bypass. you can type Fs_DSP = 31250 at the MATLAB command prompt. verify that the value of Fs_DSP is 31250. . and then select the bitstream created in tutorial 6.Using the data conversion and RF modules Audio Codec I/O Out block • Clear the Normalize Audio Data Samples check box • Clear the Enable Data Saturation check box ADACMaster III control block • On the DAC tab. Alternately. Required clock for ADC. and then reopen it. Sample time: 128/Fs_DSP DSP Constant block • Value: ceil((462. • On the Clock and PLL tab. on the Operation Mode list. The carrier frequency of FRS channel 1 is 462.

Observing the results Turn on the FRS handset supplied with the platform. Alternately. Alternately. If this is the case. click Connect to target. 37 . Click the play button. you see 00 next to the channel number. press CTRL+T on your keyboard.5 6 Using the data conversion and RF modules On the model’s Simulation menu. the audio signal from the line out connector stops and is output by the FRS handset. When you press button S5 on the digital processing module. you can click the connect to target button. Stopping and disconnecting 1 2 Click the disconnect from target button. and then make sure that there is no privacy code. tune into channel 1. Close the model.