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**CHAPTER 1 INTRODUCTION 1.1 FAST FOURIER TRANSFORM
**

A Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Fourier Transform (DFT) and it’s inverse. There are many distinct FFT algorithms involving a wide range of mathematics, from simple complex-number arithmetic to group theory and number theory. The fast Fourier Transform is a highly efficient procedure for computing the DFT of a finite series and requires less number of computations than that of direct evaluation of DFT. It reduces the computations by taking advantage of the fact that the calculation of the coefficients of the DFT can be carried out iteratively. Due to this, FFT computation technique is used in digital spectral analysis, filter simulation, autocorrelation and pattern recognition. The FFT is based on decomposition and breaking the transform into smaller transforms and combining them to get the total transform. FFT reduces the computation time required to compute a discrete Fourier transform and improves the performance by a factor of 100 or more over direct evaluation of the DFT.

A DFT decomposes a sequence of values into components of different frequencies. This operation is useful in many fields but computing it directly from the definition is often too slow to be practical. An FFT is a way to compute the same result more quickly: computing a DFT of N points in the obvious way, using the definition, takes O( N2 ) arithmetical operations, while an FFT can compute the same result in only O(N log N) operations.

The difference in speed can be substantial, especially for long data sets where N may be in the thousands or millions—in practice, the computation time can be reduced by

2

several orders of magnitude in such cases, and the improvement is roughly proportional to N /log (N). This huge improvement made many DFT-based algorithms practical. FFT’s are of great importance to a wide variety of applications, from digital signal processing and solving partial differential equations to algorithms for quick multiplication of large integers.

The most well known FFT algorithms depend upon the factorization of N, but there are FFT with O (N log N) complexity for all N, even for prime N. Many FFT algorithms only depend on the fact that is an N th primitive root of unity, and thus can be applied to analogous transforms over any finite field, such as number-theoretic transforms. The Fast Fourier Transform algorithm exploit the two basic properties of the twiddle factor - the symmetry property and periodicity property which reduces the number of complex multiplications required to perform DFT. FFT algorithms are based on the fundamental principle of decomposing the computation of discrete Fourier Transform of a sequence of length N into successively smaller discrete Fourier transforms. There are basically two classes of FFT algorithms. A) Decimation In Time (DIT) algorithm B) Decimation In Frequency (DIF) algorithm. In decimation-in-time, the sequence for which we need the DFT is successively divided into smaller sequences and the DFTs of these subsequences are combined in a certain pattern to obtain the required DFT of the entire sequence. In the decimation-infrequency approach, the frequency samples of the DFT are decomposed into smaller and smaller subsequences in a similar manner. The number of complex multiplication and addition operations required by the simple forms both the Discrete Fourier Transform (DFT) and Inverse Discrete Fourier Transform (IDFT) is of order N2 as there are N data points to calculate, each of which requires N complex arithmetic operations.

However. If we can't do any better than this then the DFT will not be very useful for the majority of practical DSP application. If the function to be transformed is not harmonically related to the sampling frequency. As the name suggests. FFTs are algorithms for quick calculation of discrete Fourier transform of a data vector. The algorithmic complexity of DFT will O(N2) and hence is not a very efficient method. there are a number of different 'Fast Fourier Transform' (FFT) algorithms that enable the calculation the Fourier transform of a signal much faster than a DFT. The Radix-2 DIT algorithm rearranges the DFT of the function xn into two parts: a sum over the even-numbered indices n = 2m and a sum over the odd-numbered indices n = 2m + 1: . The FFT is a DFT algorithm which reduces the number of computations needed for N points from O(N 2) to O(N log N) where log is the base-2 logarithm.3 The discrete Fourier transform (DFT) is defined by the formula: N −1 X (K ) = ∑ x(n) •e n=0 Where K is an integer ranging from 0 to N − 1. − j 2ΠnK N . the response of an FFT looks like a ‘sinc’ function (sin x) / x.

when this is generalized to larger radices below. the whole DFT can be calculated as follows: This result. which is simply a size-2 DFT. flipping the sign of the Ok + N / 2 terms. is the core of the radix-2 DIT fast Fourier transform. Thus. The phase factor exp[ − 2πik / N] called a twiddle factor which obeys the relation: exp[ − 2πi(k + N / 2) / N] = e − πiexp[ − 2πik / N] = − exp[ − 2πik / N]. the outputs for N/2 < k < N from a DFT of length N/2 are identical to the outputs for 0< k < N/2. Denote the DFT of the Even-indexed inputs x2m by Ek and the DFT of the Odd-indexed inputs x2m + 1 by Ok and we obtain: However. Note that final outputs are obtained by a +/− combination of Ek and Okexp( − 2πik / N). That is. the size-2 DFT is replaced by a larger DFT (which itself can be evaluated with an FFT). . expressing the DFT of length N recursively in terms of two DFTs of size N/2. It is the two sums are the DFT of the even-indexed part x2m and the DFT of odd-indexed part x2m + 1 of the function xn. Ek + N / 2 = Ek and Ok + N / 2 = Ok. these smaller DFTs have a length of N/2. The algorithm gains its speed by re-using the results of intermediate computations to compute multiple DFT outputs. so we need compute only N/2 outputs: thanks to the periodicity properties of the DFT.4 One can factor a common multiplier out of the second sum in the equation.

(Radix 2 FFT) increases tremendously with increase in N. In many traditional implementations.1. and instead one traverses the computational tree in breadth-first fashion. the twiddle multiplication comes after the Butterfly stage.2 : Decimation In Frequency FFT The 'Radix 2' algorithms are useful if N is a regular power of 2 (N=2p). If we assume that algorithmic complexity provides a direct measure of execution time and that the relevant logarithm base is 2 then as shown in table 1. Fig 1. however.1 Decimation In Time FFT In the DIT algorithm. the twiddle multiplication is performed before the butterfly stage whereas for the DIF algorithm. Fig 1.5 This process is an example of the general technique of divide and conquers algorithms. the explicit recursion is avoided. . ratio of execution times for the (DFT) vs.

Both of these rely on the recursive decomposition of an N point transform into 2 (N/2) point transforms. W nK =e N − j 2ΠnK N The radix-2 decimation-in-frequency FFT is an important algorithm obtained by the divide and conquers approach. 1.3 36. If r= 2.rL where r1=r2=…=rL=r. DFT & Radix – 2 FFT 1.0 12. Both the algorithm take the advantage of periodicity and symmetry property of the twiddle factor. The Fig.2 BUTTERFLY STRUCTURES FOR FFT Basically FFT algorithms are developed by means of divide and conquer method. the socalled 'Decimation in Time' (DIT) and 'Decimation in Frequency' (DIF) algorithms. (N/2) log2 N 4 12 32 80 192 448 Speed improvement Factor 4. because there are several commonly used 'FFT' algorithms. the is depending on the decomposition of an N point DFT in to smaller DFT’s..6 The term 'FFT' is actually slightly ambiguous. If N is factored as N = r1.r3 . The N point DFT is decimated into 2 point DFT by two ways such as Decimation In Time (DIT) and Decimation In Frequency (DIF) algorithm.0 5. where r is called as Radix of FFFt algorithm. then if is called as radix-2 FFT algorithm.2 below shows the first stage of the 8-point .1: Comparison of Execution Times..8 21. There are two different Radix 2 algorithms. N 4 8 16 32 64 128 Complex Multiplications in Direct computations. N2 16 64 256 1024 4096 16384 Complex Multiplication in FFT Algorithm. Number of Points. The basic DFT is of size of 2.6 Table 1.r2. then rL =N.3 8.

1. Fig. 1. where each stage involves N/2 butterflies of the type shown in the Fig.7 DIF algorithm. The decimation. The entire process involves v = log2 N stages of decimation. .3. causes shuffling in data. however.1: First Stage of 8 point Decimation in Frequency Algorithm.

4: Butterfly Scheme. the computation of N-point DFT via this algorithm requires (N/2) log2 N complex multiplications.5. 1. For illustrative purposes. Consequently. − j 2Πnk N Here k Wn = e is the Twiddle factor. that the output sequence occurs in bit-reversed order with respect to the input. We observe. the eight-point decimation-in frequency algorithm is shown in the Figure below. . it is also possible to have both the input and output in normal order. as previously stated.8 Fig. if we abandon the requirement that the computations occur in place. Furthermore. The 8 point Decimation In frequency algorithm is shown in Fig 1.

1.9 Fig.5: 8 point Decimation in Frequency Algorithm .

we have no option but to wait for it to get completely processed for 36 clock cycles before inputting the next set of data.Using three separate stages. and one set of data could be serially streamed into the input registers 8 clock pulses after the previous set. There are various ways to implement these three stages. The net effect is that at a time we can have 3 stages working simultaneously. one for every decimation. N = 8 and hence. This is the other extreme which would require 3 sets of sixteen adders. . Besides. Thus. The second and third stages do not require any CORDIC. which will take 16 (8 for the second and 8 for third stage) clock pulses. of adders and subtractions = 24 clock cycles = 16 b) Proposed method. The complexity of implementation would definitely be reduced and delay would drastically cut down as each stage would be separated from the other by a bank of registers. The proposed three stage pipe line and the iterative architecture method are described below for implementation of DFT. The first stage requires only 2 CORDICs. In our case.Pipeline Architecture . The number of stages v in the structure shall be v = log2 N. The entire process of rotation by 0o or -90o can rather be easily achieved by 2’s complement and BUS exchange which would require much less hardware. The computation of each CORDIC takes 8 clock pulses. A) Iterative Architecture .Using only one stage iteratively three times. although in this structure they will require to rotate data by 0o or -90o using the CORDIC. once for every decimation. the number of stages is equal to 3. while one set of data is being computed. Time Taken for computation No. This is a hardware efficient circuit as there is only one set of adders and subtractions.1 Comparative Study Our V HDL code implements an 8 point decimation-in-frequency algorithm using the butterfly structure.10 CHAPTER 2 ARCHITECTURE 2.

memory register.18μm technology. Time Taken for computation = 8 clock cycles No. of adders and subtractions = 40 2. Butterfly computation block compute the stored data before going to data output process.2. Fig. Thus. . Besides.11 However. Timing constraint is set with operating frequency 50MHz. serial to parallel and parallel to serial converter. Twiddle factor are stored as signed fixed point word.1. 2. it would give improvement of merely 1 clock cycle over the architecture discussed below which we have used in terms of the total time taken.1: Data Process Block This block consist of data input. 2. butterfly computation and data output. 2. Circuit Implementation The radix-2.2. The FFT radix-2 processor architecture consist of a butterfly architecture.1. The data is kept in the register before it is read out. The design is synthesized utilizing 0. this architecture is not taken into consideration as a valid option simply because of the immense hardware required. FFT architecture is divided into three main process blocks.2 Working 2. The block diagram of process block is shown in Fig. The block diagram representation of FFT architecture design is shown in Fig. 8-point FFT was designed using VHDL code and simulated in Model Simulation in order to verify its functionality. The data is read in every rising edge of clock and stored in the memory register. control circuit.

This method is called in-placement memory storage whereby it can reduce the hardware utilization. The output results are written back in same memory location as the previous input stored. It takes two signed fixed-point data from memory register and computes the FFT algorithm. The adder sums the input before being multiplied by the twiddle factor. This design functions as a synchronous design which controlled by “CLK” signal. Moore machine approach is adapted whereby the output signal dependant to the value of next state. 2. Shift register would shift the bits to avoid overflow issue.12 Fig 2. The butterfly architecture is shown in Fig. Output of this butterfly would be kept in the register for the subsequent stage. The input signal “RST” is used to reset the FFT processor including the input buffer which holds data for next stage. The FFT processor event is determined by the control circuit depending on the feedback it receives from the surrounding unit. The multiplier forms the partial product of the complex multiplication and produce two times bigger then input bit.2: FFT Processor Architecture The most important element in FFT processor is a butterfly structure. .2.

RTL is the input to the synthesis. a HDL specification can be executed in order to achieve a high level of confidence in its correctness before commencing design and may simulate one specification for a part in the wider system context(Eg:. HDL can be used to describe electronic hardware at many different levels of abstraction such as Algorithm. such as ASICs and FPGAs as well as conventional circuits.1 INTRODUCTION Hardware Description Language (HDL) is a language that can describe the behavior and structure of electronic system. • FPGA synthesis provides logic synthesis and optimization.13 CHAPTER 3 HARDWATE DESCRIPTION LANGUAGE 3. This depends upon how accurately the specialization handles aspects such as timing and initialization. and Gate Level is the input from the synthesis. . The following are some of the advantages: • One can verify functionality early in the design process and immediately simulate the design written as a HDL description. Algorithm is un synthesizable. Register transfer level (RTL) and Gate level. HDL allows this issue to be addressed in two ways. but fail to work when plunged into a system. but it is particularly suited as a language to describe the structure and the behavior of the digital electronic hardware design. before implementation at the Gate Level allows testing architectural and designing decisions. It is often reported that a large number of ASIC designs meet their specification first time. 3. Design simulation at this high level.Printed Circuited Board Simulation). so one can automatically convert a VHDL description to gate level implementation in a given technology.2 ADVANTAGES OF HDL A design methodology that uses HDLs has several fundamental advantages over traditional Gate Level Design Methodology.

not all constructs are synthesizable. it can be used either to implement the circuit in a programmable device or can be submitted to a foundry for fabrication of an ASIC chip. With this mixed level capabilities one can describe system architectures at a high level or gate level implementation. VHDL stands for VHSIC Hardware Description Language. and it doesn't require a simulator on . It describes the behavior of an electronic circuit or system. an initiative funded by United States Department of Defense in the 1980s that led to creation of VHDL. A HDL description is more easily read and understood than a net-list or schematic description. though VHDL is fully simulatable. from which the physical circuit or system can then be attained. 3. Once the VHDL code has been written.14 • HDL descriptions provide technology independent documentation of a design and its functionality. later upgraded to the VHDL 93. The two main immediate applications of VHDL are in the field of Programmable Logic Devices and in the field of ASICs (Application Specific Integrated Circuits). VHDL was the original and first hardware description language to be standardized by Institute of Electrical and Electronics Engineers.3 VHDL VHDL is a hardware description language. An additional standard. the IEEE 1164. VHDL is a fairly general-purpose language. VHDL is intended for circuit synthesis as well as circuit simulation. through the IEEE 1076 standards. Its first version was VHDL 87. was later added to introduce a multi-valued logic system. However. • HDLs typically support a mixed level description where structural or net-list constructs can be mixed with behavioral or algorithmic descriptions. VHSIC is itself an abbreviation for Very High Speed Integrated Circuits.

4 EDA Tools There are several EDA (Electronic Design Automation) tool available for circuit synthesis. Because of this general-purpose nature. It can read and write files on the host computer. so a VHDL program can be written that generates another VHDL program to be incorporated in the design being developed. Some tools are offered as part of a vendor’s design suite such as Altera’s Quatus II which allows the synthesis of VHDL code onto Altera’s CPLD/FPGA chips. There are many VHDL compilers. 3. which build executable binaries. it is possible to use VHDL to write a test bench that verifies the functionality of the design using files on the host computer to define stimuli. The tools used were either ISE combined with ModelSim.15 which to run the code. implementation and simulation using VHDL. for Xilinx’s CPLD/FPGA chips. interacts with the user. or Xilinx’s ISE suite. and compares results with those expected. The VHDL statements are inherently concurrent and the statements placed in a PROCESS. . FUNCTION or PROCEDURE are executed sequentially. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires).

The subtracted value is multiplied with twiddle factor value before being processed into the next stage. The x(0) until x(7) variables are denoted as the input values for FFT computation and X(0) until X(7) are denoted as the outputs. . The upward arrow will execute addition operation while downward arrow will execute subtraction operation. The pipeline architecture of the 8 point FFT is shown in Fig 4.1: Pipeline architecture of 8 point FFT.1 IMPLEMENTATION OF 8-POINT FFT BLOCKS The FFT computation is accomplished in three stages. Fig 4. There are two operations to complete the computation in each stage.1 consisting of butterfly schemes in it.16 CHAPTER 4 DESIGN OF FFT 4. This operation is done concurrently and is known as butterfly process.

2 DESIGN OF A GENERAL RADIX-2 FFT USING VHDL As we move to higher-point FFTs. Hence we propose an algorithm for an efficient complex multiplier that overcomes the complication of using complex numbers throughout the process. 4. This is because FFT processed both real and imaginary value. Thus each stage requires a clock cycle and totally three clock cycles are needed. This scheduling diagram is derived from the equations obtain in FFT signal flow graph. The rest of the scheduling diagrams can be sketched in the same way as shown in figure 4.2.FFT For stage one.The operation is much simpler compared with FFT. computation is accomplished in three clock cycles denoted as S0 to S2. final computation is done and the result is sent to the variable Y (0) to Y (7). Twiddle factor is a constant defined by the number of point used in this transform. The result from FFT is represented in real and imaginary value because of the multiplication of twiddle factor. the structure for computing the FFT becomes more complex and the need for an efficient complex multiplier to be incorporated within the butterfly structure arises. . Fig 4. Scheduling diagrams are a part of behavioral modeling and Synthesis steps to translate the algorithmic description into RTL (register transfer level) in VHDL design. The figure 2 shows the scheduling diagram of the first stage of IFFT algorithm.17 The implementation of FFT flow graph in the VHDL requires three stages. Equation in each stage is used to construct scheduling diagram.2: Scheduling Diagram of stage one .

besides the butterfly itself.YS = CX – YS + j (SX + CY) Real Part R = CX – YS Imaginary Part I = SX + CY Using the twiddle factor multiplier that has been developed.18 A radix-2 FFT can be efficiently implemented using a butterfly processor which includes. an additional complex multiplier for the twiddle factors. a complex subtraction. . it is possible to design a butterfly processor for a radix-2 Cooley-Tukey FFT. Hence this basic structure of radix-2 FFT can be used as a building block to construct higher N-point FFTs. A radix-2 butterfly processor consists of a complex adder. This structure has been developed as an extension to provide for the computation of higher value index FFTs. Normal Complex Operation: (X+jY) (C+ jS) = CX + jSX + jCY . The complex multiplication with the twiddle factor is often implemented with four real multiplications and 2 add / subtract operations. and a complex multiplier for the twiddle factors.

load and run. The FFT implementation in VHDL consists of three states such as start.1 DESIGN SOFTWARE The implementations have been carried out using the software. As the output consist of real and imaginary values. The serial input of the input variable is declared as real. compile and simulation of digital systems. The hardware language used is the Very High Speed Integrated Circuit Hardware Description Language (VHDL). 5. In the third state is run. . twiddle factor and the data output. The register may be of the array of four or eight variable in the type of real. The output will also requires a clock cycle and obtained by starting from X (0) up to X (7). two registers are used for declare the values.2 FFT IMPLEMENTATION STATES The architectural design consist of data inputs. register. The butterfly process requires two clock cycles for completing a single stage of the butter fly stage. Totally it requires six clock cycles to complete the butter fly process. the outputs of FFT are obtained by one by one. The second state is load where the butterfly process is carried out. The initial state is start where the eight input of the FFT are given through single clock cycles. VHDL is a widely used language for register transfer level description of hardware.19 CHAPTER 5 VHDL IMPLEMENTATION 5. The input data is serially sent to the register memory and each input is given through a clock cycle and is used as an array in further stages through the internal register. ModSim. It is used for design entry. control unit.

20 The controlling unit carried in the FFT process is by clock and reset input in the program. The twiddle factor value is fixed and it defined inside the code itself. The clock input is used to drive the pipeline stage the FFT architecture and reset is carried for resetting the initial state. .

6. and {SoC}s. Modelsim is a simulation tool for programming {VLSI} {ASIC}s.21 CHAPTER 6 RESULTS The simulation of this whole project has been done using the Model Sim of version 6. VHDL and SystemC.2. Modelsim provides a comprehensive simulation and debug environment for complex ASIC and FPGA designs. SystemVerilog. {CPLD}s.1 SIMULATION RESULT OBTAINED FOR START STATE . {FPGA}s. Support is provided for multiple languages including Verilog.

22 6.2 SIMULATION RESULTS OBTAINED FOR LOAD STATE .

23 6.3 SIMULATION RESULTS OBTAINED FOR RUN STATE CHAPTER 7 .

7. The FFT (Fast Fourier Transform) processor plays a critical part in speed and power consumption of the Orthogonal Frequency Division Multiplexing (OFDM) communication system. the accuracy in obtained results has been increased with the help of efficient coding in VHDL. FUTURE SCOPE The future scopes of this project are to implement the proposed FFT architecture using Field-Programmable Gate Arrays (FPGAs) and also obtain the Discrete In time (DIT) algorithm of FFT.2.24 CONCLUSION AND FUTURE SCOPE 7. Compared to previous method it requires only six clock cycles for performing the butterfly process and also. REFERENCES . CONCLUSION This project describes the efficient use of VHDL code for the implementation of radix 2 based FFT pipelined architecture and the wave form result of the various stages has been obtained successfully. Thus the FFT block can be implemented in OFDM.1. The accuracy in results depends upon the equations obtained from the butterfly diagram and then on the correct drawing of scheduling diagrams based on these equations.

pp. C. Tukey . An algorithm for the machine calculation of complex Fourier series. Cooley. Valadimir A. Rama Rao 2. "VHDL Standards. ReConFig '08. 2008.Harikrishna 1. 2009 International Conference on Advances in Recent Technologies in Communication and Computing. Rodellar. : ‘An FFT/IFFT design versus Altera and Xilinx cores ’. [2]. International Conference. Gonzalez-Concejero. [3]. Pawan Verma. " Implementation of an Inter-carrier Interference SelfCancellation Technique for OFDM System in Altera CYCLONE II FPGA . Math of comp. [6].. " VHDL implementation of FFT/IFFT Blocks for OFDM ". in Conference on Convergent Technologies for Asia-Pacific Region (TENCON '06). . J. pp. 95-99. 297-301. V. 1. Peter J." 2008 International Conference on Electronic Design . T. pp. Muhammad Hasrul Mamat. in conference on Reconfigurable Computing and FPGAs.9. 2006.W. vol. 1965. 122-123.25 [1]. 5.W. Harpreet Kaur . [4]. Ashenden. 2001. vol. Sep. K. [5]. J. no." IEEE Design and Test of Computers.18. Labay: ‘An Efficient FFT Architecture for OFDM Communication Systems’./Oct. Vol.

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