Ultralow Distortion, Ultralow Noise Op Amp AD797

FEATURES
Low noise 0.9 nV/√Hz typ (1.2 nV/√Hz max) input voltage noise at 1 kHz 50 nV p-p input voltage noise, 0.1 Hz to 10 Hz Low distortion −120 dB total harmonic distortion at 20 kHz Excellent AC characteristics 800 ns settling time to 16 bits (10 V step) 110 MHz gain bandwidth (G = 1000) 8 MHz bandwidth (G = 10) 280 kHz full power bandwidth at 20 V p-p 20 V/μs slew rate Excellent DC precision 80 μV max input offset voltage 1.0 μV/°C VOS drift Specified for ±5 V and ±15 V power supplies High output drive current of 50 mA

CONNECTION DIAGRAM
OFFSET NULL 1 –IN 2 +IN 3 –VS 4 TOP VIEW

AD797

DECOMPENSATION AND DISTORTION NEUTRALIZATION 7 +VS
8 5

OFFSET NULL

Figure 1. 8-Lead Plastic Dual In-Line Package [PDIP] and 8-Lead Standard Small Outline Package [SOIC_N]

GENERAL DESCRIPTION
The AD797 is a very low noise, low distortion operational amplifier ideal for use as a preamplifier. The low noise of 0.9 nV/√Hz and low total harmonic distortion of −120 dB at audio bandwidths give the AD797 the wide dynamic range necessary for preamps in microphones and mixing consoles. Furthermore, the AD797’s excellent slew rate of 20 V/μs and 110 MHz gain bandwidth make it highly suitable for low frequency ultrasound applications. The AD797 is also useful in IR and sonar imaging applications where the widest dynamic range is necessary. The low distortion and 16-bit settling time of the AD797 make it ideal for buffering the inputs to ΣΔ ADCs or the outputs of high resolution DACs especially when used in critical applications such as seismic detection and spectrum analyzers. Key features such as a 50 mA output current drive and the specified power supply voltage range of ±5 V to ±15 V make the AD797 an excellent general-purpose amplifier.

APPLICATIONS
Professional audio preamplifiers IR, CCD, and sonar imaging systems Spectrum analyzers Ultrasound preamplifiers Seismic detectors ΣΔ ADC/DAC buffers

5

–90

INPUT VOLTAGE NOISE (nV/ Hz)

4
–100 0.001

THD (dB)

–110

0.0003

2

–120

0.0001 MEASUREMENT LIMIT

1

00846-002

0

10

100

1k

10k

100k

1M

10M

–130 100

300

1k

FREQUENCY (Hz)

3k 10k FREQUENCY (Hz)

30k

100k

300k

Figure 2. AD797 Voltage Noise Spectral Density
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.

Figure 3. THD vs. Frequency

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

00846-003

THD (%)

3

00846-001

6

OUTPUT

AD797 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 11 Noise and Source Impedance Considerations........................ 12 Low Frequency Noise................................................................. 12 Wideband Noise ......................................................................... 13 Bypassing Considerations ......................................................... 13 The Noninverting Configuration............................................. 13 The Inverting Configuration .................................................... 14 Driving Capacitive Loads.......................................................... 15 Settling Time............................................................................... 15 Distortion Reduction ................................................................. 15 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20

REVISION HISTORY
7/05—Rev. D to Rev. E Updated Figure 1 Caption ............................................................... 1 Deleted Metallization Photo ........................................................... 6 Changes to Equation 1 ................................................................... 12 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 10/02—Rev. C to Rev. D Deleted 8-Lead Cerdip Package (Q-8).............................Universal Edits to SPECIFICATIONS............................................................. 2 Edits to ABSOLUTE MAXIMUM RATINGS .............................. 3 Edits to ORDERING GUIDE.......................................................... 3 Edits to Table I .................................................................................. 9 Deleted OPERATIONAL AMPLIFIERS Graphic ...................... 15 Updated OUTLINE DIMENSIONS ............................................ 15

Rev. E | Page 2 of 20

0 1.5 1.0015% COMMON-MODE REJECTION POWER SUPPLY REJECTION INPUT VOLTAGE NOISE ±15 V 15 V ±15 V ±15 V ±15 V ±15 V ±5 V.25 0. 3 V rms RLOAD = 1 kΩ f = 20 kHz.9 2.5 ±13 ±13 ±3 80 50 –98 –120 MHz MHz MHz kHz V/μs ns dB dB dB dB nV p-p nV/√Hz nV/√Hz μV rms pA/√Hz V V V V V mA mA dB dB 12.2 0.7 0. 3 V rms ±15 V ±15 V ±15 V ±15 V ±15 V ±15 V ±5 V ±15 V ±15 V ±5 V ±5 V.0 ±11 ±2. ±15 V Min AD797A Typ 25 50 0.0 2.5 1200 120 114 120 130 1200 INPUT CURRENT NOISE INPUT COMMON-MODE VOLTAGE RANGE OUTPUT VOLTAGE SWING RLOAD = 2 kΩ RLOAD = 600 Ω RLOAD = 600 Ω Short-Circuit Current Output Current 3 TOTAL HARMONIC DISTORTION RLOAD = 1 kΩ. E | Page 3 of 20 . ±15 V ±5 V.2 0.7 0.3 2.0 400 600/700 Min AD797B Typ 10 30 0. CN = 50 pF f = 250 kHz. ±15 V ±15 V ±15 V 1.2 1.6 0. ±15 V ±5 V. ±15 V ±15 V 1 1 1 1 14000 Conditions TMIN to TMAX ±5 V.0 2.5 ±12 ±11 ±2.25 0.9 1.5 100 120 20 6 15 5 20000 Max 80 125/180 1. Table 1. Parameter INPUT OFFSET VOLTAGE Offset Voltage Drift INPUT BIAS CURRENT TMIN to TMAX INPUT OFFSET CURRENT OPEN-LOOP GAIN TMIN to TMAX VOUT = ±10 V RLOAD = 2 kΩ TMIN to TMAX RLOAD = 600 Ω TMIN to TMAX @ 20 kHz 1 G = 1000 G = 1000 2 G = 10 VO = 20 V p-p.2 1.0 200 300 Unit μV μV μV/°C μA μA nA nA V/μV V/μV V/μV V/μV V/V DYNAMIC PERFORMANCE Gain Bandwidth Product –3 dB Bandwidth Full Power Bandwidth1 Slew Rate Settling Time to 0.5 3.2 ±12 ±3 ±11 ±2. ±15 V V ±5 V.0 ±12 ±3 ±13 ±13 ±3 80 50 −98 –120 110 450 8 280 20 800 130 120 114 120 50 1.AD797 SPECIFICATIONS @ TA = +25°C and VS = ±15 V dc.9 1.1 Hz to 10 Hz f = 10 Hz f = 1 kHz f = 10 Hz to 1 MHz f = 1 kHz ±5 V.5 114 110 114 110 12.5 30 –90 –110 –90 –110 INPUT CHARACTERISTICS Input Resistance (Differential) Input Resistance (Common Mode) Input Capacitance (Differential) 4 Input Capacitance (Common Mode) 7.5 100 20 5 7.25 80 120 2 20 2 10 2 15 2 7 14000 20000 Max 40 60 0.5 30 ±12 ±11 ±2.5 100 20 5 kΩ MΩ pF pF Rev. RLOAD = 1 kΩ RLOAD = 1 kΩ 10 V step VCM = CMVR TMIN to TMAX VS = ±5 V to ±18 V TMIN to TMAX f = 0. unless otherwise noted. ±15 V 110 450 8 280 20 800 130 120 130 120 50 1.

AOL > 200 kΩ. 4 Differential input capacitance consists of 1.5 Unit mΩ V mA ±5 ±5 V. see Applications section.2 Full Power Bandwidth = Slew Rate/2 π VPEAK. E | Page 4 of 20 .5 pF package capacitance and 18.5 pF from the input differential pair. ±15 V 8.2 ±5 8. Rev. f = 1 kHz V Min AD797A Typ Max 3 ±18 10. 3 Output current for |VS – VOUT| > 4 V.5 Min AD797B Typ Max 3 ±18 10. Specified using external decompensation capacitor.AD797 Parameter OUTPUT RESISTANCE POWER SUPPLY Operating Range Quiescent Current 1 2 Conditions AV = +1.

Note. ESD CAUTION ESD (electrostatic discharge) sensitive device.3 W − (TA–25°C)/θJA Thermal Characteristics 8-Lead Plastic DIP Package: θJA = 95°C/W 8-Lead Small Outline Package: θJA = 155°C/W 2 The AD797’s inputs are protected by back-to-back diodes. proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. E | Page 5 of 20 . Storage Temperature Range (Cerdip) Storage Temperature Range (N. Although these products feature proprietary ESD protection circuitry.9 W (TA–25°C)/θJA 8-Lead Plastic DIP and Cerdip = 1. however.AD797 ABSOLUTE MAXIMUM RATINGS Table 2. permanent damage may occur on devices subjected to high energy electrostatic discharges.7 V. Parameter Supply Voltage Internal Power Dissipation @ 25°C1 Input Voltage Differential Input Voltage2 Output Short-Circuit Duration Ratings ±18 V ±VS ±0. Rev. R Suffix) Operating Temperature Range AD797A/B Lead Temperature Range (Soldering 60 sec) 1 Internal Power Dissipation: 8-Lead SOIC = 0. Therefore. To achieve low noise. If the differential input voltage exceeds ±0.7 V Indefinite Within Max Internal Power Dissipation −65°C to +150°C −65°C to +125°C −40°C to +85°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. the input current should be limited to less than 25 mA by series protection resistors. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. that this degrades the low noise performance of the device. internal current limiting resistors are not incorporated into the design of this amplifier.

5 00846-008 0 0 5 10 SUPPLY VOLTAGE (±V) 15 20 –2. Load Resistance Figure 9. Supply 0 Figure 7. Temperature Rev.5 10 +VOUT –VOUT –1.01μV/DIV) 0 0 5 10 SUPPLY VOLTAGE (±V) 15 20 00846-004 HORIZONTAL SCALE (5sec/DIV) Figure 4. 0.AD797 TYPICAL PERFORMANCE CHARACTERISTICS 20 INPUT COMMON-MODE RANGE (±V) 15 10 5 VERTICAL SCALE (0. Temperature 140 OUTPUT VOLTAGE SWING (V p-p) VS = ± 15V 120 20 100 SOURCE CURRENT SINK CURRENT 80 10 VS = ±5 00846-006 60 00846-009 0 10 100 1k LOAD RESISTANCE (Ω) 10k 40 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 6.0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 5. Output Voltage Swing vs.1 Hz to 10 Hz Noise 20 OUTPUT VOLTAGE SWING (±V) INPUT AS CURRENT (μA) 15 –0. Input Bias Current vs. Output Voltage Swing vs. E | Page 6 of 20 00846-007 . Supply 30 SHORT-CIRCUIT CURRENT (mA) Figure 8. Common-Mode Voltage Range vs.0 5 00846-005 –1. Short-Circuit Current vs.

Settling Time vs. Supply for 0. Frequency –60 FREQ = 1kHz RL = 600Ω G = +10 9 RL = 600Ω G = +10 FREQ = 10kHz NOISE BW = 100kHz OUTPUT VOLTAGE (V rms) 6 THD + NOISE (dB) –80 VS = ±5V –100 VS = ±15V 3 00846-011 0 0 ±5 ±10 SUPPLY VOLTAGE (±V) ±15 ±20 –120 0. E | Page 7 of 20 00846-013 –55°C 00846-010 40 75 .01 0.2 00846-012 0 0 2 4 6 8 10 STEP SIZE (V) 0 10k 100k 1M 10M FREQUENCY (Hz) Figure 12.AD797 11 QUIESCENT SUPPLY CURRENT (mA) 140 POWER SUPPLY REJECTION (dB) 10 +125°C 120 PSR –SUPPLY PSR +SUPPLY COMMON MODE REJECTION (dB) 00846-015 00846-014 100 150 9 80 CMR 60 125 8 +25°C 100 7 6 0 5 10 SUPPLY VOLTAGE (±V) 15 20 20 1 10 100 1k 10k 100k 50 1M FREQUENCY (Hz) Figure 10.8 SETTLING TIME (μs) 0. Supply Voltage 12 Figure 13. Power Supply and Common-Mode Rejection vs. Output Voltage vs.01% 0.0015% OUTPUT VOLTAGE (V p-p) RL = 600Ω 20 0.0 Figure 14. Output Level 30 ±15V SUPPLIES 0. Total Harmonic Distortion (THD) + Noise vs.6 0.1 OUTPUT LEVEL (V) 1 10 Figure 11.01% Distortion 1. Quiescent Supply Current vs. Step Size (±) Figure 15.4 10 ±5V SUPPLIES 0. Large Signal Frequency Response Rev.

Input Offset Current vs.AD797 5 35 120 4 30 GAIN/BANDWIDTH PRODUCT 110 3 SLEW RATE RISING EDGE 25 100 2 SLEW RATE FALLING EDGE 20 90 1 00846-016 GAIN/BANDWIDTH PRODUCT (MHz (G = 1000)) 00846-021 00846-020 INPUT VOLTAGE NOISE (nV/ Hz) SLEW RATE (V/μs) 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 15 –60 –40 –20 0 20 40 60 80 100 120 80 140 TEMPERATURE (°C) Figure 16. Input Voltage Noise Spectral Density Figure 19.01 10 100 1k 10k 100k FREQUENCY (Hz) 1M TEMPERATURE (°C) Figure 18. Temperature 120 PHASE MARGIN 100 WITHOUT RS* WITH RS* 80 100 160 80 PHASE MARGIN (Degrees) OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) 60 140 60 GAIN 40 *RS = 100 WITH RS* 0 100 1k 10k 100k 1M FREQUENCY (Hz) 10M WITHOUT RS* 40 20 120 20 0 00846-017 100 100M 100 1k LOAD RESISTANCE (Ω) 10k Figure 17. Open-Loop Gain and Phase vs. Frequency *See Figure 32 Rev. Magnitude of Output Impedance vs. Open-Loop Gain vs. E | Page 8 of 20 00846-019 . Temperature Figure 21. Resistive Load 100 INPUT OFFSET CURRENT (nA) OVER COMPENSATED 150 10 0 1 WITHOUT CN* –150 UNDER COMPENSATED 00846-018 0. Frequency *See Figure 25 300 MAGNITUDE OF OUTPUT IMPEDANCE (Ω) Figure 20.1 WITH CN* –300 –60 –40 –20 0 20 40 60 80 100 120 140 0. Slew Rate and Gain/Bandwidth Product vs.

Inverter Large Signal Pulse Response 00846-023 Figure 26. E | Page 9 of 20 00846-027 00846-026 . Follower Connection **See Figure 35 1μs 100 90 5V 1μs 100 90 10 0% 10 0% 5V Figure 23.AD797 20pF 1kΩ +VS ** VIN 1kΩ 2 7 100Ω +VS ** 2 7 AD797 6 6 VOUT 600Ω AD797 3 4 VOUT VIN RS* 3 4 ** –VS 00846-025 00846-022 ** –VS * VALUE OF SOURCE RESISTANCE SEE TEXT Figure 22. Follower Large Signal Pulse Response 50mV 100 90 100ns 100 90 50mV 100ns 10 0% 00846-024 10 0% Figure 24. Follower Small Signal Pulse Response Rev. Inverter Connection **See Figure 35 Figure 25. Inverter Small Signal Pulse Response Figure 27.

E | Page 10 of 20 00846-029 .AD797 50mV 100 90 500ns 100 90 50mV 500ns 10 0% 10 0% Figure 28. 16-Bit Settling Time Positive Input Pulse 00846-028 Figure 29. 16-Bit Settling Time Negative Input Pulse Rev.

By exploiting the inherent matching of devices fabricated on the same IC chip. NPN to NPN and PNP to PNP). AD797 Simplified Schematic Rev. high open-loop gain. This single stage has a voltage gain of >5 × 106 and VOS <80 μV. solving it (at Node B) yields: gm R1 C1 BUFFER RL VOUT GAIN = gm x R1 x 5 x 106 a. the first stage gain is rolled off at high frequencies by the compensation network. and not absolute parameter such as beta and early voltage. the distortion cancellation does not affect the stability or frequency response of the amplifier. uses a single ultrahigh gain stage to achieve dc as well as dynamic precision. Therefore. Slew rate and settling performance are usually compromised. and Node C all track in voltage forcing the operating points of all pairs of devices in the signal path to match.9 nV/√Hz) extend to beyond 1 MHz. Previous precision amplifiers used three stages to ensure high open-loop gain (Figure 30) at the expense of additional frequency compensation components. Another unique feature of this circuit is that the addition of a single capacitor. but because it holds up dynamically. This matching benefits not just dc precision. As shown in the simplified schematic (Figure 31). Model of AD797 vs. and dynamic performance is not adequate beyond audio frequencies. which include the properties of the output stage such as output impedance and distortion. Second stage noise and distortion then appears at the input and degrade performance. All of this performance as well as load drive in excess of 30 mA are made possible by Analog Devices’ advanced Complementary Bipolar (CB) process. This can best be explained by referring to a simplified representation of the AD797 using idealized blocks for the different circuit elements (Figure 32).AD797 THEORY OF OPERATION The architecture of the AD797 was developed to overcome inherent limitations in previous amplifier designs. With only 500 μA of output stage bias. E | Page 11 of 20 00846-031 C . I1 I7 I4 VSS Figure 31. PSRR. both distortion and settling time are also reduced. This means new levels of performance for sampled data and imaging systems. while at the same time providing THD + noise of less than −120 dB and true 16-bit settling in less than 800 ns. The AD797 on the other hand. CMRR. the AD797 delivers a 1 kHz sine wave into 60 Ω at 7 V rms with only 1 ppm of distortion. Node A. enables cancellation of distortion due to the output stage. Node B.. As can be seen in Figure 30. That of a Typical Three-Stage Amplifier VCC R2 R3 CN R1 Q4 Q3 A +IN Q1 Q2 –IN I5 Q10 OUT Q7 B Q9 Q5 Q6 CC Q12 Q8 Q11 I6 The terms in A. and low VOS are all guaranteed by pairwise device matching (that is. (~1) VO = voltage at the output 00846-030 GAIN = gm x R1 x A2 x A3 b. A single equation yields the open-loop transfer function of this amplifier. C2 VO gm = C CN VIN jω − CN jω − C jω A A where: gm = the transconductance of Q1 and Q2 gm R1 C1 R2 A2 A3 BUFFER RL VOUT A = the gain of the output stage. The elimination of second stage noise effects has the additional benefit of making the low noise of the AD797 (<0. CN (Figure 31). cancel by simple subtraction. VIN = differential input voltage When CN is equal to CC this gives the ideal single pole op amp response: VO gm = VIN jω C Figure 30.

• Care must be used to account for the effects of rS. The results must be interpreted using valid statistical techniques. eN total = [eN + 4 kTrS + (iN / rS ) 2 ]1 / 2 2 (1) where rS = total input source resistance. the Johnson noise of rS dominates until at higher resistances (rS > 2 kΩ).9 nV/√Hz is achieved with special input transistors running at nearly 1 mA of collector current. current noise (iN).1 Hz to 10 Hz bandwidth. filtering. the amplifiers’ voltage noise dominates. AD797 Block Diagram rS. this case is considered even though it is clear from Equation 1 that eliminating the balancing source resistance lowers the total noise by reducing the total rS by a factor of two. AD549. Several precautions are necessary to get optimum low frequency noise performance.1 Hz is generated with an external ac coupling capacitor. The plot in Figure 7 uses a slightly different technique. Several techniques can be used to make this measurement. At higher values of source resistance. OP07 AD548. 100 • • 10 TOTAL NOISE NOISE (nV/ Hz) RESISTOR NOISE ONLY 1 • 00846-033 0. Selective heating and cooling of these by random air currents appears as 1/f noise and obscure the true device noise. AD743/AD745 NOISE AND SOURCE IMPEDANCE CONSIDERATIONS The AD797’s ultralow voltage noise of 0. which includes contributions from voltage noise (eN). Even a 10 Ω resistor has 0. Table 3.AD797 I1 I2 CN A B A OUT The AD797 is the optimum choice for low noise performance provided the source resistance is kept <1 kΩ. and measuring the amplifier’s noise for a predetermined test time. the instrument being dc coupled. optimum performance with respect to noise alone is obtained with other amplifiers from Analog Devices (Table 3). OP07 AD743/AD745. ohms 0 to <1 kΩ 1 kΩ to <10 kΩ 10 kΩ to <100 kΩ >100 kΩ Recommended Amplifier AD797 AD743/AD745. Noise vs. and the test time is carefully controlled because the measurement time acts as an additional low frequency roll-off. It is important then to consider the total input referred noise (eNtotal). Source Resistance Rev.9 nV/√Hz). This equation is plotted for the AD797 in Figure 33. The usual technique involves amplifying. AD711. At very low source resistance (rS <50 Ω).1 10 100 1000 SOURCE RESISTANCE (Ω) 10000 Figure 33. the current noise component is larger than the resistor noise. Because optimum dc performance is obtained with matched source resistances. A low frequency pole at 0.4 nV/√Hz of noise (an error of 9% when root sum squared with 0. Here an FFT based instrument (Figure 34) is used to generate a 10 Hz “brickwall” filter. LOW FREQUENCY NOISE Analog Devices specifies low frequency noise as a peak-to-peak (p-p) quantity in a 0. The noise bandwidth of the filter is corrected for. The test setup must be fully warmed up to prevent eOS drift from erroneously contributing to input noise. OP27/OP37. Recommended Amplifiers for Different Source Impedances +IN –IN Q1 Q2 CURRENT MIRROR CC 1 I3 C I4 00846-032 Figure 32. E | Page 12 of 20 . Circuitry must be shielded from air currents. Heat flow out of the package through its leads creates the opportunity for a thermoelectric potential at every junction of different metals. and resistor noise (√4 kTrS). As source resistance increases.

The AD797 offers new levels of performance in wideband imaging applications.1 Hz to 10 Hz Noise **Use Power Supply Bypassing Shown in Figure 35 WIDEBAND NOISE Due to its single stage design. Operation on 5 volt supplies allows the use of a 100 Ω or less feedback network (R1 + R2). VIN R2 100Ω 3 AD797 4 6 VOUT RL 600Ω 00846-036 ** BYPASSING CONSIDERATIONS Taking full advantage of the very wide bandwidth and dynamic range capabilities of the AD797 requires some precautions. the equivalent resistance of the feedback network should be as low as possible. Table 4 gives some representative values for the AD797 as a low noise follower.1 μF ceramic bypass capacitors are sufficient in most applications. Voltage Follower Connection **Use Power Supply Bypassing Shown in Figure 35 Low noise preamplification is usually done in the noninverting mode (Figure 38).7 μF tantalum in parallel with 0.7 Ω) carbon resistors can be an improvement. In sampled data systems. This is not true of most dc precision amplifiers where second stage noise contributes to input referred noise beyond the audio frequency range.1μF 4. Figure 35 summarizes bypassing recommendations. which is usually insignificant. In general. it is suitable for driving the AD600/AD602 (Figure 50) while preserving their low noise performance. and experimentation may be necessary for best results.0 μF to 4. The symbol (**) is used throughout this data sheet to represent the parallel combination of a 0.1 μF and a 4.7 μF capacitor.1μF TO 4. and the AD797 should never be operated with unbalanced source resistance >200 kΩ/G. The input source resistance and capacitance also affects the response slightly. Test Setup for Measuring 0. additional input series damping is required for stability with direct input to output feedback. the AD797 outperforms all previously available IC op amps. the 100 Ω balancing resistor (R2) is recommended but is not required for stability. In this case. Table 4 includes recommended values of CL for several gains. Figure 38). when R2 is greater than 100 Ω and CL is greater than 33 pF. When driving heavy loads a larger demand is placed on the supply bypassing. The 30 mA minimum drive current of the AD797 makes it easier to achieve this. For lowest noise. Source resistance matching is assumed.AD797 100kΩ +VS ** 1Ω 2 7 THE NONINVERTING CONFIGURATION Ultralow noise requires very low values of rBB (the internal parasitic resistance) for the input transistors (≈6 Ω). R1 100Ω +VS ** 2 7 1. selective use of larger values of tantalum capacitors and damping of their lead inductance with small value (1. Best response flatness is obtained with the addition of a small capacitor (CL < 33 pF) in parallel with the 100 Ω resistor (Figure 37).7μF KELVIN RETURN USE SHORT LEAD LENGTHS (< 5mm) USE SHORT LEAD LENGTHS (< 5mm) KELVIN RETURN Figure 35.7μF TO 22. Recommended Power Supply Bypassing Rev.5μF 6 AD797 3 4 VOUT ** HP 3465 DYNAMIC SIGNAL ANALYZER (10Hz) 00846-034 –VS Figure 34.7μF 0. E | Page 13 of 20 00846-035 LOAD CURRENT LOAD CURRENT . Because the AD797 shows no unusual behavior when operating near its maximum rated current.1 nV/√Hz). multiple bypassing is recommended in any precision application. where aliasing of out of band noise into the signal band is a problem.0μF 1. a 100 Ω resistor should be placed in series with CL. First. The noise penalty is minimal (eNtotal ≈ 2. OR 0. The feedback resistors can be made as low as possible with due consideration to load drive and power consumption. A 100 Ω resistor in the inverting input (Figure 36) is sufficient. the noise of the AD797 is flat over frequencies from less than 10 Hz to beyond 1 MHz. VS VS –VS Figure 36. Optimum flatness and stability at noise gains >1 sometimes require a small capacitor (CL) connected across the feedback resistor (R1.1μF 4. This implies very little damping of input and output reactive interactions.1 Ω to 4. A 1. With the AD797.

A bypassed balancing resistor (RS and CS) can be included to minimize dc errors.AD797 CL 20pF TO 120pF R1 100Ω 100Ω +VS +VS ** 2 7 IIN 2 7 ** AD797 VIN RS* 3 6 VOUT 600Ω AD797 4 6 VOUT 600Ω CS* 00846-037 3 4 00846-039 RS* –VS ** CS* –VS *SEE TEXT ** *SEE TEXT Figure 37.0 nV/√Hz 1. the goals of both low noise and input buffering are at odds with one another.98 nV/√Hz VIN R1 2 7 AD797 3 4 6 VOUT RL 00846-040 RS* –VS *SEE TEXT ** Figure 40. the noise penalties are minimal.8 nV/√Hz 1. Some examples are presented in Table 4 and Figure 40. Table 5. The value of CL depends on the DAC and again. Inverting Amplifier Connection **Use Power Supply Bypassing Shown in Figure 35 The I-to-V converter is a special case of the follower configuration.2 Ω 16. E | Page 14 of 20 . Values for Inverting Circuit Gain −1 −1 −10 R1 1 kΩ 300 Ω 150 Ω R2 1 kΩ 300 Ω 1500 Ω CL ≈20 pF ≈10 pF ≈5 pF Noise (Excluding rS) 3. the excellent dynamics of the AD797 makes it the preferred choice in many inverting applications.8 nV/√Hz 1. R1.0 nV/√Hz 0. and with careful selection of feedback resistors. to the source. for example as a DAC buffer. Values for Follower with Gain Circuit Gain 2 2 10 20 >35 R1 1 kΩ 300 Ω 33. Nonetheless. Low Noise Preamplifier **Use Power Supply Bypassing Shown in Figure 35 Table 4. Alternative Voltage Follower Connection **Use Power Supply Bypassing Shown in Figure 35 Figure 39.2 nV/√Hz 1.8 nV/√Hz Rev.5 Ω 10 Ω R2 1 kΩ 300 Ω 300 Ω 316 Ω (G − 1) × 10 Ω CL ≈20 pF ≈10 pF ≈5 pF Noise (Excluding rS) 3. the circuit of Figure 39 should be used. if CL is greater than 33 pF. For this reason.0 nV/√Hz 1. When the AD797 is used in an I-to-V converter. a 100 Ω series resistor is required. I-to-V Converter Connection **Use Power Supply Bypassing Shown in Figure 35 CL THE INVERTING CONFIGURATION The inverting configuration (Figure 40) presents a low input impedance. CL R2 +VS ** R2 +VS ** R1 2 7 AD797 VIN 3 4 6 VOUT RL 00846-038 ** –VS Figure 38.

yielding a smaller effective compensation capacitance and. usually 50 pF. RL = 600 Ω) unequaled by most voltage feedback amplifiers. Closed-Loop Gain Figure 43. A special test setup (Figure 43) was developed for this purpose. a larger bandwidth. TO TEKTRONIX 7A26 OSCILLOSCOPE 1MΩ PREAMP INPUT SECTION 226Ω 4. At gains over 10. Capacitive Load Drive Capability vs. THD increases due to reduction in loop gain. SETTLING TIME The AD797 is unique among ultralow noise amplifiers in that it settles to 16 bits (<150 μV) in less than 800 ns. @ 20 kHz. is connected between Pin 8 and the output (C2 in Figure 42). The input signal was obtained from a resonant reed switch pulse generator. 067-0608-00. the switch is simply 50 Ω to ground and settling is purely a passive pulse decay and inherently flat. gain bandwidth can be increased to 450 MHz at G = 1000. The unique design of the AD797 provides for cancellation of the output stage’s distortion. Here a 5000 pF load can be driven cleanly at any noise gain ≥2. Rev. However. 3 V rms.47μF 10nF 0. If more drive is desirable the circuit in Figure 42 should be used. usually no special precautions are necessary.26kΩ (VIA LESS THAN 1FT 50Ω COAXIAL CABLE) 2 20pF A2 AD829 7 4 250Ω 6 VERROR X 5 2x HP2835 3 100nF CAPACITIVE LOAD DRIVE CAPABILITY 2x HP2835 0. therefore. the AD797 provides two effective means of reducing distortion as gain and frequency are increased: cancellation of the output stage’s distortion. and gain bandwidth enhancement by decompensation. E | Page 15 of 20 .47μF +VS –VS 1nF 1kΩ TEKTRONIX CALIBRATION FIXTURE 100Ω 1kΩ 1kΩ NOTE: USE CIRCUIT BOARD WITH GROUND PLANE 100pF VIN 1kΩ 2 20pF 10pF 00846-041 A1 AD797 7 4 6 3 51pF 1μF 0. in contrast to most conventional voltage feedback amplifiers. 33Ω VIN AD797 3 4 6 VOUT C1 00846-042 ** –VS Figure 42. and distortion can be held to −100 dB at 20 kHz for G = 100. When open. available from Tektronix as calibration Fixture No. Measuring this performance presents a challenge. Use of this feature improves distortion performance when the closed-loop gain is more than 10 or when frequencies of interest are greater than 30 kHz. a capacitance equal to the effective compensation capacitance. The selection of plug-in for the oscilloscope was made for minimum overload recovery.AD797 DRIVING CAPACITIVE LOADS The capacitive load driving capabilities of the AD797 are displayed in Figure 41. To achieve this. By applying these techniques. Recommended Circuit for Driving a High Capacitance Load **Use Power Supply Bypassing Shown in Figure 35 At higher gains and higher frequencies.1μF –VS +VS Figure 41. The low repetition rate signal was captured on a digital oscilloscope after being amplified and clamped twice. Settling Time Test Circuit 20pF 1kΩ 200pF +VS ** 1kΩ 2 7 DISTORTION REDUCTION 100Ω The AD797 has distortion performance (THD < −120 dB. Bandwidth enhancement via decompensation is achieved by connecting a capacitor from Pin 8 to ground (C1 in Figure 44) effectively subtracting from the value of the internal compensation capacitance (50 pF).1μF 00846-043 1pF 1 10 100 1k CLOSED-LOOP GAIN 1μF 0.

As shown in Figure 47. Figure 45 shows the AD797’s 20-bit THD performance over the audio band and 16-bit accuracy to 250 kHz.0003 –120 AD797 VIN 3 G = +10 RL = 600Ω 0. the bandwidth is 450 kHz. E | Page 16 of 20 00846-046 THD (%) . 20pF 1kΩ 1kΩ +VS ** 50pF* 7 2 8 C1 AD797 VIN 3 6 b. G = +100 –110 0. Total Harmonic Distortion (THD) vs.01 0.003 THD (dB) –100 0. Recommended Connections for Distortion Cancellation and Bandwidth Enhancement Table 6. C1. Recommended External Compensation Gain 10 100 1000 A/B R1 R2 Ω Ω 909 100 1k 10 10 k 10 A C1 pF 0 0 0 C2 pF 50 50 50 3 dB BW 6 MHz 1 MHz 110 kHz C1 pF 0 15 33 C2 pF 50 33 15 B 3 dB BW 6 MHz 1. R1 –80 G = +1000 RL = 600Ω –90 NOISE LIMIT. Differential Line Receiver **Use Power Supply Bypassing Shown in Figure 35 Rev. At a gain of 1000.001 50pF R2 2 8 0.AD797 The benefits of this begin at closed-loop gains of 100 and up. G = +1000 G = +1000 RL = 10kΩ G = +100 RL = 600Ω NOISE LIMIT. SEE TABLE C2 = 50pF – C1 Figure 44. Table 6 and Figure 45 summarize the performance of the AD797 with distortion cancellation and decompensation. R1 C2 R2 2 8 Figure 45. Differential Line Receiver The differential receiver circuit of Figure 46 is useful for many applications from audio to MRI imaging. Frequency @ 3 V rms for Figure 44b.5 MHz 450 kHz DIFFERENTIAL INPUT 00846-044 AD797 3 4 6 OUTPUT *OPTIONAL ** 1kΩ 1kΩ –VS 20pF Figure 46. It allows extraction of a low level signal in the presence of common-mode noise.0001 00846-045 6 100 300 1k 3k 10k 30k 100k 300k FREQUENCY (Hz) a. the AD797 provides this function with only 9 nV/√Hz noise at the output. A maximum value of ≈33 pF at gains of 1000 and up is recommended.

Output Voltage Noise Spectral Density for Differential Line Receiver Figure 49. this circuit is capable of better than −90 dB THD with a ±5 V. Distortion is only −50 dBc @ 1 MHz at a 2 V p-p output level and drops rapidly to better than −70 dBc at an output level of 200 mV p-p. the circuit drives a 600 Ω load to a level of 7 V rms with less than −109 dB THD and a 10 kΩ load at less than −117 dB THD. E | Page 17 of 20 00846-049 10M 649Ω .AD797 16 22pF R2 OUTPUT VOLTAGE NOISE (nV/ Hz) 14 2kΩ +VS ** 12 +VS 2 7 ** 6 3 7 AD797 10 1kΩ INPUT 3 4 AD811 ** 2 4 6 8 00846-047 –VS 649Ω –VS ** 6 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 47. ** 26.001 –110 MEASUREMENT LIMIT 0. and load drive of a current feedback amplifier to yield a very wide dynamic range general purpose driver.003 Ultrasound/Sonar Imaging Preamp –100 WITHOUT OPTIONAL 50pF CN 0. An Ultrasound Preamplifier Circuit **Use Power Supply Bypassing Shown in Figure 35 Rev. slew rate. The combination of low noise and low gain is difficult to achieve. To optimize dynamic range this buffer should have at most 6 dB of gain. THD (dB) Figure 48.0001 00846-048 300k FREQUENCY (Hz) The AD600 variable gain amplifier provides the time controlled gain (TCG) function necessary for very wide dynamic range sonar and low frequency ultrasound applications.1Ω +VS A General Purpose ATE/Instrumentation Input/Output Driver The ultralow noise and distortion of the AD797 may be combined with the wide bandwidth. Using the component values shown.1 Ω resistors in its feedback path. A General Purpose ATE/Instrumentation Input/Output Driver **Use Power Supply Bypassing Shown in Figure 35 –90 0. Using a 100 kHz sine wave. Total Harmonic Distortion (THD) vs. 500 kHz output signal. The circuit of Figure 49 combines the AD797 with the AD811 in just such an application. it is necessary to buffer the input of the AD600 to preserve its low noise performance.1Ω 2 7 ** AD797 3 4 6 AD600 VOUT ** VS = ±6Vdc 00846-050 INPUT –VS ** Figure 50. The circuit is therefore suitable for driving high resolution A/D converters and as an output driver in automatic test equipment (ATE) systems. Frequency for Differential Line Receiver THD (%) 26.0003 –120 WITH OPTIONAL 50CN –130 100 300 1k 3k 10k 30k 100k 0. Under some circumstances. The input buffer circuit shown in Figure 50 provides 1 nV/√Hz noise performance at a gain of two (dc to 1 MHz) by using 26.

Amorphous Detector Preamp **Use Power Supply Bypassing Shown in Figure 35 ** .AD797 Amorphous (Photodiode) Detector Large area photodiodes (CS ≥ 500 pF) and certain image detectors (amorphous Si) have optimum performance when used in conjunction with amplifiers with very low voltage rather than very low current noise. while the noise is dominated by voltage noise amplified by the ac noise gain. while correctly reproducing the desired output with extremely low THD and IMD. Offset Null Configuration Rev. The response is adjusted for flatness using capacitor CL. clock energy and current steps must be absorbed by the op amp’s output stage. However. E | Page 18 of 20 00846-054 00846-053 Figure 51. as shown by Figure 48. Standard practice is to operate an op amp as an I-to-V converter creating a virtual ground at its inverting input. Capacitor CF shunts high frequency energy to ground.1Hz FREQUENCY)) –30 100 Figure 53. were it not for the fact that most DACs do not operate linearly with voltage on their output. in the configuration of Figure 53. An ideal I-to-V converter for a current output DAC would simply be a resistor to ground. Normally. The AD797’s excellent input noise performance gives 27 μV rms total noise in a 1 MHz bandwidth. CF 82pF 100Ω 10kΩ +VS ** 2 7 3kΩ +VS ** IS CS 1000pF 3 AD797 4 6 AD1862 DAC 00846-051 2 7 ** –VS C1 2000pF 3 AD797 4 6 –VS –40 VOUT NOISE 80 VOLTAGE NOISE (mV rms (0. 100Ω CL 50pF Professional Audio Signal Processing—DAC Buffers The low noise and low distortion of the AD797 make it an ideal choice for professional audio signal processing. Figure 51 shows the AD797 used with an amorphous Si (CS = 1000 pF) detector. A Professional Audio DAC Buffer **Use Power Supply Bypassing Shown in Figure 35 +VS VOUT (dB Re 1V/μA) –50 60 2 7 –60 40 AD797 3 1 4 5 6 –70 20 20kΩ VOS ADJUST –80 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 0 100M 00846-052 –VS Figure 52. Total Integrated Voltage Noise and VOUT of Amorphous Detector Preamp Figure 54.

92) MAX 0. INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56.310 (7.060 (1.31 (0.87) 0.33) MAX 0.02) 8 1 5 4 0.25 (0.17 (0.38) MIN 0.10 PLANE 8° 0.46) 0.130 (3.0098) 0.240 (6.95) 0.27) 0.2440) 4 5.0157) 0.36) 0.195 (4.115 (2.0122) 0. Figure 55.35 (0. E | Page 19 of 20 .430 (10.1968) 4.1497) 1 6.75 (0.0196) × 45° 0.81) 0.015 (0.20) 0.62) 0.210 (5.30) 0.40 (0.015 (0.365 (9.022 (0.060 (1.00 (0.16) 0.0201) COPLANARITY SEATING 0.38) GAUGE PLANE SEATING PLANE 0.014 (0.1574) 3.80 (0.010 (0.0688) 1.280 (7.92) 0. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.25 (0.130 (3.115 (2.00 (0.36) 0.0500) 0.56) 0.0098) 0° 1. MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.80 (0.325 (8.0040) 1.005 (0.14) 0.13) MIN COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES.51 (0.018 (0.25) 0.0099) 0.10 (0.92) 0.25 (0.250 (6.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS.52) 0.27 (0.008 (0.52) MAX 0.20 (0. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev.014 (0.54) BSC 0.2284) 1.0532) 0.0500) BSC 0.070 (1.10) PIN 1 0.78) 0.11) 0.50 (0.30) 0.150 (3.35) 0.AD797 OUTLINE DIMENSIONS 0.300 (7.27 (0.045 (1.1890) 8 5 4.355 (9. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.100 (2.400 (10.80 (0.26) 0.

Inc. C00846-0-7/05(E) Rev. Trademarks and registered trademarks are the property of their respective owners. E | Page 20 of 20 . All rights reserved.AD797 ORDERING GUIDE Model AD797AN AD797ANZ 1 AD797AR AD797AR-REEL AD797AR-REEL7 AD797ARZ1 AD797ARZ-REEL1 AD797ARZ-REEL71 AD797BR AD797BR-REEL AD797BR-REEL7 AD797BRZ1 AD797BRZ-REEL1 AD797BRZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 Z = Pb-free part. ©2005 Analog Devices.

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