A 6-bit 2.

704Gsps DAC for DS-CDMA UWB

*Jae-Jin Jung, **Bong-hyuck Park, **Sang-Seong Choi, ***Shin-Il Lim, *Suki Kim

*Korea University,
" Electronics and Telecommunications Research Institute,
* * * Seokyeong University

Abstract This paper presents a design of a 6-bit
2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB
transceivers. The proposed DAC was designed with a current
steering segmented 4+2 architecture for high frequency sampling
rate. For low glitches, optimized deglitch circuit is adopted for
the selection of current sources. The measured integral
nonlinearity (INL) is -0.081 LSB and the measured differential
nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a
0.13um CMOS technology shows s spurious free dynamic range
(SFDR) of 41dB at fsignal 300Mhz. The prototype DAC consumes
28mW for a Nyquist sinusoidal output signal at a
2.704Gsamples/s. The chip has an active area of 0.76mm2
Index terms- CMOS, DAC, UWB, Deglitch
I. INTRODUCTION
For a DS-CDMA UWB transceiver, one practical approach
for generation of the data signal is to use a high speed and low
resolution DAC(Digital to Analog Converter) followed by a
low pass filter to shape the spectrum. Due to the hardware
complexity of implementing a high order filter, it is desirable
to push the conversion rate of the DAC as high as possible. In
the DS-CDMA UWB proposal, the highest data rate is 1.35
Gbps. So two times oversampling of the data signal
necessitates the DAC operating at 2.704 Gsamples/s.
A high conversion rate makes a DAC susceptible to
parasitic capacitances of the circuit, which may cause digital
ability to drive a resistive load directly without the voltage
buffer. However, it is a difficult to get a certain intrinsic
accuracy specification due to the random mismatches, the
systematic mismatches and the output impedance mismatches
among the current sources in all architectures. For signal
processing applications, the segmented architecture that
combines unity and binary weighted current cells is often used
for various reasons. It allows a tradeoff of reduction in the
glitch energy and differential nonlinearity with an increase in
the decoding logic complexity and the overall layout area.
The goal of the DAC reported here is a high speed 6bit
current-steering segmented architecture DAC for signals from
dc to Nyquist for sampling rate up to 2.704Gsamples/s. The
chip area of DAC is 0.76mm2 in a 0.13um CMOS technology,
single poly, six metal and 1.2V Supply Voltage.
In Section II, the DAC's basic architecture principles are
discussed. In Section III, DAC building blocks are discussed
namely digital block, current source, switch transistor and
deglitch. In Section IV, the impact of the layout is discussed.
In Section V, the measurement results of the chip are showed.
In Section VI, summarizes the conclusions.
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feedthrough, weak isolation, significant glitch energy and slow Digital X D

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transient time. These result in a sharp drop in the spurious free Input 4 e.
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dynamic range (SFDR). Many recent researches have revealed (I) eQ COUTB

its success for high resolution and high speed DAC. [1]-[3]
Various architectures have been used to construct high
2
speed and high resolution DAC. In particular, charge-scaling umm
De 0 Binary
DAC based on capacitor arrays, sigma-delta modulation based
DAC, and current-scaling DAC based on current-source arrays Figure 1. The Block diagram of the Proposed DAC
have all been recently examined in the literature as suitable
candidates.
Current-scaling DAC are based an array of matched current II. Basic architecture
source which are unit decoded or binary weighted. The variety In the binary implementation, the digital inputs directly
architectures are used such as the two stage and segmented control the switches. The current sources associated with the
architecture. Current-scaling DAC have been traditionally switches are binary weighted. The advantage of binary
used for high speed and high resolution applications due to weighted DAC is simplicity as no decoding logic is required.

347
1-4244-0387-1/06/$20.00 (@2006 IEEE
However, there are several major drawbacks which are all
associated major bit transitions. At the mid-code transition, the
most significant bit current source needs to be matched to the
sum of all the other current sources to within 0.5 least
significant bit. This is difficult to achieve. Because of
statistical spread, such matching can never be guaranteed.
Therefore this architecture is not guaranteed monotonic.
Matching is an issue for all bit transitions, but the severity of
the problem is proportional to the weight of the bit, resulting
in a typical differential nonlinearity. In addition, the errors
caused by the dynamic behavior of the switches (such as
charge injection and clock feedthrough) result in glitches in
the output signal. This problem is most severe at the mid-code
transition, as all switches are switching simultaneously. Such a
mid-code glitch contains highly nonlinear signal components,
even for small output signals and will manifest itself as spurs
in the frequency domain.
In the thermometer-code implementation, each unit current
source is connected to a switch controlled by the signal
coming from the binary to thermometer decoder. When the
digital input increases by 1 LSB, one more current source is
switched from the negative to the positive side. Assuming
positive only current sources, the analog output is always
increasing as the digital input increases. Hence, monotonic is
guaranteed using this architecture. There are several other
advantages. The matching requirement is much relaxed. At the
mid-code, a 1 LSB transition causes only one current source to
switch as the digital input only increases by one. This greatly
reduces the glitch problem. Glitches hardly contribute to
nonlinearity in the thermometer coded DAC. This is because
the magnitude of a glitch is proportional to the number of
switches that are actually switching. So for small steps, the
glitch is small, and for a large step, the glitch is large. Since
the number of switches that switch is proportional to the signal
step between two consecutive clock cycles, the magnitude of
the glitch is directly proportional to the amplitude of the signal
step. If the glitch is strictly proportional to the signal step, it
will not cause any nonlinearity in the DAC output signal. One
major drawback of the thermometer coded DAC is area and
power consume, since for every LSB this architecture needs a
current source and decoding circuit as well as the binary to
thermometer decoder.
To achieve a good DNL specification and glitch energy, the
number of bits implemented in the binary weighted part of the
DAC has to be small. However for every extra bit
implemented in the unity decoded part, the number of control
lines needed to select the current sources doubles and the
decoding logic complexity increases significantly. A direct
consequence is often a reduction in the maximum operating
speed. Equally important is the fact that the area used by the
decoding and interconnections inside the matrix increases, and
consequently the process and electric systematic errors
become more difficult to compensate. To get the best of both
architectures, Digital to Analog Converter is implemented
using a segmented architecture.
Fig. 1 shows the floor-plan of the segmented DAC. The
chip consists of a 2 bit binary and 4 bit unary DAC. It is using
348 APCCAS 2006
the matrix decoder for thermometer decoding. If it is used a
current steering segmented 3+3 architecture, the matrix
decoder isn't needed, so that good area and power consume
are achieved. However, A thermometer decoder of 3 bits
requires NAND and NOR gates with three inputs. This
decoder makes it difficult to match timing margin at
2.7Gsamples/s. For high speed conversion rates, current
steering segmented 4+2 architecture is used. The matrix
decoder of 4 bits requires only NAND and NOR gates with at
most two inputs.
DATA DA
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Propagation delay Input buffer output
Figure 2. Input Buffer
III. DAC Building Blocks
The chip consists of a 2 bit binary and 4 bit unary DAC.
Two MSBs are converted to a 3 bit thermometer code, the
intermediate two bits are converted to a 3 bit thermometer
code and two LSBs are binary weighted. A dummy decoder
has been added to minimize latency problems between the
signals generated by the thermometer and matrix decoder and
the unary LSBs. The input buffer has been added to match
timing among input signals.
A. Digital Circuitry
The input buffer has been added to match timing among
input signals and recover the data that lost amplitude. Fig. 2
shows the recovering propagation delay of the input signals.
The synchronization of the input signal of 2.7Gsample/s is
achieved by adding the flip-flop latch.
All the digital blocks were designed full customable instead
of using standard cell libraries and were laid out at transistor
level in order to achieve high conversion rate. The standard
cell libraries have the disadvantage that the achievable
operation speed is limited by timing constraints of the used
cells. The thermometer decoder is implemented with two input
NAND, NOR gates and Inverters. The fan-in and fan-out of
each decoder block are optimized to achieve the 2.7Gsample
timing margin. Dummy block is added as to avoid timing
mismatches.
A six 16 to 1 digital multiplexers at digital input are added
for the purpose of testing DAC which is reduced the data rate
of the test inputs by sixteen times.
 ~1Mswn MPf HP
load Rload
Figure 3. Current Source
B. The Current Source
The dynamic performance degradation of current steering
DAC can be caused by several reasons. Some dynamic
limitations are 1) voltage fluctuation in the output nodes, 2)
feedthrough of the control signals to the output lines, 3)
imperfect synchronization of the control signals of the
switching transistors.
The voltage at the output node of the current sources has to
be maintained constantly. However, during the switching time
a significant voltage variation can be occurred because of the
parasitic capacitance of current source switch. And the
parasitic capacitance of current source switches can produce a
relatively pole. Therefore a large voltage fluctuation at the
output node can degrade the dynamic performance of DAC.
The impedance Zin seen in the drain of the switch transistors
influences on the INL specification of the DAC. The relation
between the impedance and INL specification is give by (1)
with RL the output load resistor, lunit the LSB current and N
the total number of unit current sources. [1]
INL = iunit RLN (1)
Cascaded current source cell is used for high impedance to
achieve the INL specification and reduce voltage variation at
the output node. And current source is made by pmos
transistor for high impedance.
To minimize settling time of the control signal, the current
source switch transistors between LSB and MSB current
source has to have same load capacitance. The W/L ratio of
switch transistors of MSB current source is four times the W/L
ratio of switch transistors of MSB current source because
MSB current is four times of LSB current. To achieve same
load capacitance and W/L ratio, using (2) W/L of switch
transistors are designed.
COX (WMSBLMSB ) = COX (WLSBLLSB )
(2)
KPWIMSB L I 2ILSB
VKP (WMSB I LMSB ) VKP (WLSB I LLSB )
APCCAS 2006
Figure 4. Deglitch & Latch Circuit
C. The Deglitch
To minimize imperfect synchronization of the control
signals at the switches, a new designed driver is used. A major
function of this driver is shifting the crossing point of the
control signals at current source switches. So switch
transistors are never simultaneously in the off state. The driver
also performs the latch. So all current source switch transistors
are synchronized in the turn on and turn off.
To design a driver, MI M6 transistors [Fig. 4] are added in
-
the latch composed inverter chain. The MI M6 transistors
-
control the rising and falling times of control signals. We need
lower crossing point signal because of pmos current sources
and pmos switches are used. Extra nmos transistors are used
for Lower crossing point of differential outputs. The M3,6 and
positive feedback of M4,5 results in a more faster falling time
than rising time of the differential output signals.
Figure 5. Switching scheme
IV. Layout
To compensate for symmetrical and graded errors caused by
the process, temperature and electrical gradients, special
switching schemes [Fig. 5] are implemented. For transistor
matching, the 4 X 4 current sources have been augmented to
the 6 X 6 matrix cell. The dummy rows and columns are used
to provide identical surroundings to the inner matrix cell. The
switch driver and switching transistors are placed in a separate
array from the current matrix cell. To avoid coupling between
349
the digital and the analog signal, this scheme is used. Analog
block and digital block are separated to avoid coupling signal.
Fig. 7 shows the measured integral non linearity (INL) and
differential non linearity (DNL) of the DAC with sampling
rate of 2.704Gsps. The maximum INL and DNL are 0.1 LSB
and 0.1 LSB. Fig. 8 shows the spurious-free dynamic range
(SFDR) better than 41dB for a 2.704 Gsample/s clock speed
and a 300MHz output signal.
The power consumption has been measured for a 300 Mhz
output signal at sample frequency of 2.704Gsample/s. the
DAC dissipates 28mW from a 1.2V power supply.
Table 1 summarize the specification of the proposed D/A
converter
TABLE I. PERFORMANCE SUMMARY

Figure 6. Chip Micrograph Technology 0.13pm IP 6M CMOS

Supply Power 1.2 V
Due to the compact layout of the current cell and decoding Resolution 6 bit
logic, the DAC core has an active area of 0.76mm2. Fig. 6 Sampling Rate 2.704 GHz
shows the chip microphotograph of the DAC. Full Output Scale 300 mVp-p
DNL 0.1 LSB
06
*A t INL 0.1 LSB

A
,fef\X
A A ~vt SFDR 41dB Fout = 300MHz
[n 37dB Fout = 520MHz
010P7'21125
; 2"9
3 74 4 93 57 61
z Area 0.76 mm2
04 Power 28 mW
06

VI. Conclusion
Digital Input Code
In this paper, a 6 bit 2.704Gsample/s Digital to Analog
Converter targeted for direct spectrum code division multiple
D)4 access ultra wide band (DS-CDMA UWB) is presented. For
high speed conversion rate, the 4+2 segmented current
steering structure , input buffer and deglitch circuit is used.
The chip area of DAC is 0.76mm2 in a 0.13um CMOS
z technology, single poly, six metal and 1.2V Supply Voltage.
.04

.06 ACKNOWLEDGMENT
This work was supported by the Electronics and
Digital Input Code
Telecommunications Research Institute (ETRI) and CAD tool
Figure 7. Measured INL and DNL was supported by IC Design Education Center (IDEC).

V. Measurement Results
All measurements have been performed on a single-ended
50 ohm double terminated output. The analog and digital
voltages are 1.2V. The differential output voltage is 300mV.
Reference
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Current-Steering CMOS D/A Converter"
[2] C. H. Lin and K. Bult, "A 10-bit 50OMsample/s CMOS
DAC in 0.6mm2"
[3] Jose Bastos, Michel S. J. Steyaert, Willy Sansen, "A 12-
Bit Intrinsic Accuracy High-Speed CMOS DAC"
[4] A. Van den Bosch, M. Steyaert, Willy Sensen, "An
accurate statistical yield model for CMOS current-
steering D/A converter"
[5] Rudy van de Plassche "CMOS Integrated Analog-to-
Digital and Digital-to-Analog Converters"

350 APCCAS 2006