610
3, MARCH 2010
A 0.02-mm2 9-Bit 50-MS/s Cyclic ADC in 90-nm
Digital CMOS Technology
Yen-Chuan Huang and Tai-Cheng Lee
Abstract—A 9-bit cyclic ADC employs a track-and-evaluation
technique for enhancing the speed of residue evaluation. The pro-
posed multiply-by-two circuit has a shorter evaluation time than
the conventional design due to the application of a partial positive
feedback topology. The residue evaluation and sampling phases are
merged to reduce the conversion latency. Hence, only four clock
cycles are required to perform the 9-bit conversion. The proposed
0.02-mm2 ADC has been fabricated in 90-nm digital CMOS tech-
nology. It operates at 50 MS/s and achieves an SNDR of 50.5 dB
with a power consumption of 6.9 mW from a 1.0-V supply.
Index Terms—Cyclic ADC, partial positive feedback gain stage.
I. INTRODUCTION
T HE sub-sampling ADCs used in communication systems
have become popular because they not only perform
analog-to-digital conversion but also downconvert the signal
into a baseband signal. Therefore, the downconversion stages
can be eliminated to reduce the hardware cost of the receiver.
In the sub-sampling ADC designs, the ADCs operate at tens of
MS/s; however, they deal with a high-frequency input. There-
fore, the acquisition time and hold accuracy of the sampling
network should be carefully designed to avoid high frequency
effects [1], [2]. In recent studies, SAR ADCs have been con-
sidered to have the most power efficient architecture for such
conversion rates [3], [4]. However, the input capacitances of
SAR ADCs are typically large due to the design consideration
of mismatch requirement. Hence, the proceeding stages, such
as variable gain amplifiers or filters, need to provide high
driving capability. In terms of the overall system, power reduc-
tion in such ADCs might lead to the cost of excessive power
consumption in the other circuit blocks. Furthermore, for an
SoC application, if the system requires multiple ADCs to be
integrated in a single chip, maintaining a small area would be
an important concern. However, due to the large capacitance
required in an SAR ADC, the silicon area is significantly large.
To resolve the design issues described above, this paper
presents a low power, small area cyclic (algorithmic) ADC with
a wide input frequency range. The proposed ADC generates
residue voltages by merged sampling and multiplication phases
Manuscript received June 23, 2009; revised October 20, 2009. Current version
published February 24, 2010. This paper was approved by Associate Editor Kari
Halonen. This work was supported by NTU-MediaTek Lab. (MediaTek Inc.).
The authors are with the Department of Electrical Engineering and Graduate
Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
(e-mail: tlee@cc.ee.ntu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2009.2039275
0018-9200/$26.00 © 2010 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO.
Fig. 1. Block diagram of a cyclic ADC.
such that only clock cycles are required for an -bit
conversion. Therefore, the sampling rate is effectively double
that of a conventional design [5]–[7]. The cyclic ADC employs
only one op amp, and therefore, it has an area-efficient design
as compared to an SAR ADC with similar resolutions and
conversion rates.
In Section II, a conventional cyclic ADC architecture is re-
viewed. In Section III, a single stage cyclic ADC is proposed.
The op amp in the architecture is used as a current-switching
track-and-evaluation circuit to sample the high-frequency input
signal and evaluate the residue signal with a partial positive
feedback loop recursively. A detailed analysis of the cyclic ADC
is also included in this section. Finally, Sections IV and V out-
line the experimental results and the conclusion, respectively.
II. CONVENTIONAL CYCLIC ADC ARCHITECTURE REVIEW
Fig. 1 shows a block diagram of a cyclic analog-to-digital
converter [5]. The architecture contains one sample-and-hold
(S/H) stage to sample the input or the residue signal from the
previous step. This residue signal is generated according to the
decision outputs of the comparator, and the gain stage is used
to amplify the residue signal to reuse the full-scale reference
voltage. The cyclic ADC performs this analog-to-digital conver-
sion recursively. Therefore, it requires a small amount of analog
circuitry and achieves the most area-efficient design of any type
of ADC.
The cyclic ADC shown in Fig. 2 employs two op amps in
a closed feedback loop [6]. During the sampling phase , the
input capacitance is precharged to the input signal voltage and
all the other capacitors are reset. At the next phase , the input
charge is injected into the loop and op amp holds the sampled
signal. The comparator compares the hold signal with
to determine the MSB of the output digital codes. The op amp
precharges the capacitor with capacitance to the input
signal voltage after phase , and the stored charge is injected
into the loop to generate a voltage gain of two of the input signal
at the next phase . Simultaneously, the second input capacitor
injects charge into the inverting summing node based
HUANG AND LEE: A 0.02-mm 9-BIT 50-MS/s CYCLIC ADC IN 90-nm DIGITAL CMOS TECHNOLOGY
Fig. 2. A conventional cyclic ADC.
on the comparator’s output ( or 1). Therefore, the output
voltage of amplifier becomes
(1)
This operation is repeated to determine the following bits,
and the conversion process continues until all the bits are gen-
erated. Therefore, the cyclic ADC requires clock cycles
to perform an -bit conversion. This long conversion latency is
the major speed limitation in cyclic ADC designs [5]–[10]. A
high sampling rate is achieved by using two residue gain stages
rather than one S/H and one gain stage [11]. However, in [11],
the cyclic ADC used three op amps to implement the ADC and
the queue S/H for digital calibration, resulting in an increase in
power consumption.
The designs in [5]–[7], [9] employ two op amps to imple-
ment residue sampling and multiplication function. The power
consumption can be further reduced by sharing the op amp be-
tween the two phases, as in [8], [10]. However, the sampling
rate is still limited by the long conversion latency, as described
above.
In the following sections, a residue evaluation stage em-
ploying a partial positive feedback loop is proposed to enhance
the evaluation speed, and the sampling and multiplication
phases are merged to reduce the conversion latency to
clock cycles. An area-efficient cyclic ADC is presented with
a 90-nm digital CMOS technology to verify the proposed
architecture.
III. PROPOSED ARCHITECTURE
The cyclic ADC shown in Fig. 2 generates one digital output
bit per clock cycle. However, the comparator offset may induce
serious nonlinearity in this 1-bit/step architecture, especially in
high resolution ADCs. To reduce the errors caused by the com-
parators, a range-overlap architecture [7], [12] (which is referred
to as 1.5-bit/step hereafter) is used in the proposed cyclic ADC.
The proposed gain stage employs a partial positive feedback
network to amplify the signal and generate the 1.5-bit residue.
The simplified circuit is shown in Fig. 3 to demonstrate the main
611
Fig. 3. Proposed 1.5-bit residue generator.
concept. By charge conservation at the input node of the op amp,
the output voltage can be expressed as
(2)
where represents the decision of the ADC comparators.
Therefore, the amplification of the signal and the addition/sub-
traction of the reference voltage are performed in the charge
domain.
At the end of the evaluation phase, the charge on the nega-
tive-feedback capacitor is equal to if the virtual ground
condition is maintained. Therefore, instead of using an explicit
sampling capacitor to store the residue voltage for the next-step
conversion, the proposed architecture uses the negative-feed-
back capacitor to hold the residue charge. Therefore, by in-
jecting the reference charge at each conversion step, the residue
voltage can be generated in one operation phase rather than two.
Fig. 4 shows the simplified single-ended architecture of the
proposed ADC; the actual design is fully differential. The ADC
contains one op amp, a 1.5-bit sub-ADC, and two capacitor net-
works. Fig. 4 also shows the first three operation phases of the
ADC. During the tracking phase, the voltage across the feedback
capacitor tracks the input signal, and the two capacitor networks,
C_net1 and C_net2, are precharged to the reference voltages.
The op amp is then reset to avoid sample-to-sample memory
effects. When the evaluation phase starts, the 1.5-bit sub-ADC
selects one capacitor from C_net1 to connect the positive-feed-
back path, and the loop determines the residue according to (2).
At the next evaluation phase, the positive-feedback capacitor is
chosen from C_net2 to generate the new residue voltage, and
all the capacitors in C_net1 are reset to the reference voltages.
The evaluation process is repeated until the next tracking phase
occurs. At the rising edge of the next tracking phase, a two-bit
flash ADC completes the last step of conversion of the previous
sample, and the negative-feedback capacitor is again connected
to the input for input tracking. As shown in the timing diagram
in Fig. 4, the conversion latency is only four clock periods for
this proposed 9-bit ADC.
The following subsections contain detailed discussions on the
proposed architecture, including the settling time of the residue
gain stage, a current-switching track-and-hold circuit, and the
track-and-evaluation property of the system.
A. Settling Time of the Proposed Cyclic ADC
As mentioned above, the major advantage of using the feed-
back capacitor to store the residue voltage in the proposed cyclic
ADC is the shortened conversion latency. Another advantage
612 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010

Fig. 4. Proposed 9-bit cyclic ADC architecture and operation phases.

of removing the explicit sampling capacitor is that it reduces (6)

the output loading during evaluation and thus results in a faster
settling time. The differential version of the proposed circuit and represent the parasitic capacitances associated with
shown in Fig. 3 can be redrawn, as shown in Fig. 5(a). Due to the op amp, and represents the compensation capacitance.
low intrinsic gain in the 90-nm technology, a two-stage op amp and are the parameters that relate and to the ca-
with cascode compensation [13], [14] is used for residue evalua- pacitance value . Therefore, the transfer function becomes (7),
tion. To simplify the analysis, the half circuit and the equivalent also shown at the bottom of the page. The closed-loop response
small-signal model of the cell are shown in Figs. 5(b) and is characterized by the pole frequencies in (7). To obtain the pole
5(c), respectively. The differential input voltage initially stored frequencies, the denominator in (7) is expressed as follows:
on the capacitor is expressed as , and the
output voltage is similarly defined as .
Therefore, the closed-loop transfer function is derived as (3),
shown at the bottom of the page, where the capacitance ratio
used in the multiply-by-two circuit, , is taken
into (3). To further simplify the expression, the following as- (8)
sumptions are made:
Therefore,

(4)
(9)
(5)

(3)

(7)
HUANG AND LEE: A 0.02-mm 9-BIT 50-MS/s CYCLIC ADC IN 90-nm DIGITAL CMOS TECHNOLOGY 613

Fig. 5. (a) The fully differential version of the proposed residue generator. (b) The half circuit of the two-stage op amp with cascode compensation. (c) The
equivalent small-signal model of (b).

closed-loop transfer function [15], [16] is (14), shown at the

bottom of the page, where

(15)
(16)
(17)

The transfer function of the flip-over circuit has a form that

is similar to (3), which contains one zero and three poles. If the
assumptions in (4)–(6) are applied to (14), the denominator of
Fig. 6. A conventional MDAC stage in the evaluation mode in a pipelined
ADC.
(14) is simplified to

(10)
(18)
(11)
The loading capacitor is the sampling capacitance for the
In practice, a compensation capacitor that allows the transfer next-step of conversion. In a conventional cyclic or pipelined
function to be approximated as a first-order system is selected. ADC design for a voltage gain of two, and
With the design choice in (12) , and therefore, the feedback factor is 0.5 and
(18) becomes
(12)

the settling time is characterized only by the dominant pole fre-

quency , and (9) gives an estimation of the sum of two
non-dominant pole frequencies as

(13) (19)

Further,
To calculate the transfer function of the conventional flip-over
1.5-bit MDAC stage shown in Fig. 6 [12], which always has (20)
a permanent capacitive loading arising from the next stage, a
similar analysis is applied to the circuit shown in Fig. 6, with
(21)
the transconductance cell model shown in Fig. 5(b) and (c). The

(14)
614 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010

(22)

If the same dominant pole assumption is made as in (12), (20)

becomes

(23)

Assuming that the damping factors in both the conventional

and the proposed circuit are identical and that the transient be-
haviors are similar, the ratio of the dominant pole to the sum of
the non-dominant poles should be the same, i.e.,

(24)

Because larger values are chosen, the transfer functions be-

have more like a well-defined first-order system. In this study,
a value of 10 is chosen for , and is equal to 0.1 according
to the simulation results. Based on (13), (23), and (24), the fol- Fig. 7. Current-switching track-and-hold.
lowing result is obtained if and ,

(25)
Therefore, with the same unit capacitance, faster linear settling
can be achieved in the proposed circuit if both the circuits are
designed to have the same settling behavior.
voltage at the op amp output node and the voltage stored on
the capacitor are not identical at the beginning of the hold
phase. This voltage discrepancy needs to be settled to zero for
complete settling. Assuming that the input signal is ,
the small results in a voltage transient , such that

(26)
B. Current-Switching Track-and-Hold
In this subsection, a current-switching track-and-hold circuit The voltage transient arises from the finite ON resistance of
is proposed for the input sampling. The op amp used in the track- the switch in series with the sampling capacitor. The first-order
and-hold circuit is shared with the MDAC conversion stage. RC sampling network is described by the differential equation
Thus, only one op amp is required to complete both signal sam-
pling and residue evaluation. The operation and settling analysis
of the track-and-hold circuit are included in this section, and the (27)
detailed operating phases of the track-and-hold circuit and the
MDAC stage are discussed in the Section III-C. where is the voltage across the sampling capacitor, and
For a conventional high-speed flip-around sample-and-hold is the ON resistance of the switch. From (27), the switch ON
(S/H) circuit, the linearity of the sampled signal tends to become resistance also creates a difference between the input voltage
worse due to the incomplete settling of the op amp. To relax the and the voltage stored on the capacitor. Therefore, the voltage
design requirement of the op amp, a current-switching circuit difference can be obtained by solving (27).
is proposed. For the illustration purpose, a current-switching
telescopic op amp is shown in Fig. 7. During the tracking
phase, the bias current in the op amp is steered to path I by
applying differential biasing voltages and as a
clock to the cascode transistors 8 . Therefore, the output
node is floating and can be driven by the input signal. Simulta- (28)
neously, the input node of the op amp can be reset to remove
the sample-to-sample memory effects. During the hold phase,
the bias current is steered back to the output stage (path II) to The last term in (28) is the natural response of the system and
form a negative-feedback loop for holding the sampled signal. can be neglected. For an input signal with a frequency of 100
By employing differential clocks, a small voltage difference at MHz, a typical value of 500 fF for the sampling capacitance
the inputs of the cascode transistors can switch the bias current and for the switch ON resistance are selected, such that
completely. Therefore, the switching time between the tracking
phase and the hold phase can be reduced. MHz fF (29)
To obtain the settling time improvement quantitatively,
the following analysis is performed. Fig. 8 shows the output Therefore, is much smaller than unity, and (28) is simpli-
settling waveform of the proposed track-and-hold with a sinu- fied to
soidal input. Due to the advanced clock phase for bottom-plate
sampling and the finite ON resistance of the switch, the initial (30)
HUANG AND LEE: A 0.02-mm 9-BIT 50-MS/s CYCLIC ADC IN 90-nm DIGITAL CMOS TECHNOLOGY 615

Fig. 8. Settling behavior of the track-and-hold circuit.

Combining (26) and (30), the transient settling of a sinusoidal

wave after the proposed track-and-hold becomes

(31)

If is approximately 0.1 ns and the input signal frequency is

assumed to be 100 MHz, is equal to 0.063. Therefore, the
maximum voltage settling for an input sine wave with amplitude Fig. 9. The detailed timing diagram of the proposed cyclic ADC.
is , which is less than 10% of the
full swing range. Assuming that the settling time of the op amp
is dominated by the small-signal time constant , for the error
of the hold signal to be less than 0.5-LSB,

(32)

where is the full-scale voltage, is the difference be-

tween the final and the initial voltages, and is the resolu-
tion. With identical time constants for the proposed track-and-
Fig. 10. The transfer curve of a conventional 1.5-bit MDAC and the curve with
hold circuit and the conventional sample-and-hold circuit, the pre-charging to the input voltage.
required settling time ratio is calculated as

(33)

In this 9-bit system design , (33) is around 0.7, indi-

cating that the settling time of the proposed track-and-hold cir-
cuit can be improved by 30% because of the much smaller tran-
sient settling range. Therefore, the proposed track-and-hold has
a faster settling behavior and thus better linearity performance
than a conventional sample-and-hold circuit.

C. Timing for the Proposed Cyclic ADC

In the timing diagram of the proposed architecture shown in
Fig. 4, no hold phase is allocated for the track-and-hold circuit
to hold the input signal. Therefore, different signal voltages may
be observed between the sub-ADC and the residue gain stage.
This issue becomes serious when the input signal frequency is
high, as in sub-sampling applications. To avoid this signal dif-
ference, which results in a conversion error, similar to pipelined Fig. 11. Worst-case settling time simulations in a track-and-evaluation system
ADCs without a front-end sample-and-hold stage [1], [2], as and in a conventional MDAC stage.
shown in Fig. 9, the proposed cyclic ADC architecture uses an
added delay time between the tracking and the first evalu-
ation phase to reduce the voltage difference seen between the 1.5-bit accuracy rapidly, and the short hold time occupies
sub-ADC and the residue gain stage. The output voltage may only a small fraction of the conversion time.
not settle to its final value during ; however, the sub-ADC
determines the digital codes correctly as long as the error is D. Track-and-Evaluation Characteristic
smaller than . According to the previous analysis, the As shown in Sections III-B and III-C, the hold time of the
output of the track-and-hold circuit only has to settle to a value track-and-hold circuit is small, and the hold phase can almost
that is no more than 10% of the full swing value. Therefore, the be omitted from the conversion process to further shorten the
proposed track-and-hold architecture settles within the required conversion latency. Therefore, the proposed cyclic ADC shown
616
Fig. 12. (a) The two-stage op amp used in the proposed ADC (the CMFB circuit is not shown here). (b) The comparator used in the sub-ADC.
in Fig. 4 is operated like a “track-and-evaluation” amplifier.
Although a similar precharging technique to improve the set-
tling response of the MDAC stages in a pipelined ADC was
demonstrated in [17], additional comparators and precharging
phases are required to apply the precharging technique. The
proposed cyclic architecture shown in Fig. 4 is equivalent to
precharging the loading capacitance to the input voltage before
evaluation. Furthermore, neither additional comparators nor
extra precharging phases are needed, and the circuit complexity
remains the same.
Fig. 10 shows the transfer curve of a 1.5-bit/step architecture
and the curve with the precharging characteristic. The worst set-
tling case occurs while the input level approaches full swing in
the conventional design. However, in the track-and-evaluation
system, the settling time is almost zero with a large input signal
level. The worst settling case now occurs at a signal level of
around and the settling range is , which is 25%
smaller than the conventional one. Fig. 11 shows the worst case
settling waveforms in the track-and-evaluation system and in the
1.5-bit MDAC stage from transistor-level simulations. The op
amp, unit capacitance, and reference voltages are the same, and
the settling time is defined as the residue signal settled within
a 0.5-LSB error in both the cases. Compared with the conven-
tional design, the track-and-evaluation system achieves a faster
transient response. With the track-and-evaluation property and
the larger dominant pole frequency mentioned in Section III-A,
the total improvement is approximately a 15% reduction in the
settling time based on the simulation results.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010
IV. EXPERIMENTAL RESULTS
The proposed 9-bit cyclic ADC was fabricated in 90-nm dig-
ital CMOS technology with using standard threshold voltage
devices only. Because of the low intrinsic gain of the transis-
tors, a two-stage op amp with cascode compensation [13], [14]
was used for residue evaluation. The op amp and the comparator
used in the proposed ADC are shown in Fig. 12. The input stage
of the op amp has a folded cascode topology, and the output
stage is used to implement the current-switching track-and-hold.
Because the 1.5-bit architecture can tolerate a comparator offset
of up to , a simple dynamic comparator with a low-gain
preamplifier is used [18], [19]. The power dissipation of the
preamplifier is less than 0.1 mW.
Fig. 13 shows a photograph of the chip. The active area occu-
pies only m m, excluding the output driving buffers.
The circuit was tested with an on-chip reference voltage driving
buffer while running from a 1.0-V power supply. The power
consumption of the core analog portion is 6 mW, which includes
5.3 mW for the op amp and the biasing network and 0.7 mW
for the comparators used in the 1.5-bit sub-ADC and the 2-bit
flash ADC. The digital portion, including the clock generation
circuit, shift registers, and error correction adder, consumes ap-
proximately 0.9 mW while operating at 50 MS/s.
Fig. 14 shows the measured FFT output spectrum when the
ADC was operating at 50 MS/s. The SNDR values are 50.5
dB and 50.2 dB for 1-MHz and 20-MHz inputs, respectively.
HUANG AND LEE: A 0.02-mm 9-BIT 50-MS/s CYCLIC ADC IN 90-nm DIGITAL CMOS TECHNOLOGY 617

Fig. 13. Chip micrograph.

Fig. 16. Dynamic performance versus sampling rate.

Fig. 14. Measured spectrums with 50 MHz sampling rate and input frequencies Fig. 17. Dynamic performance versus input frequency.
of 1 MHz and 20 MHz.

TABLE I
PERFORMANCE SUMMARY TABLE.

Fig. 15. Measured DNL/INL plot.

Fig. 15 shows the measured DNL/INL. The maximum DNL is

0.43/-0.47 LSB, and the maximum INL is 0.63/-0.60 LSB.
Fig. 16 shows the dynamic performance versus sampling rate
with a low input-frequency signal, and Fig. 17 shows the dy- versus the input frequency. The SNDR only decreases by 1.9 dB
namic performance versus input frequency with the ADC oper- with an input frequency of up to 100 MHz. The figure-of-merit
ating at 50 MS/s. The SNDR decreases rapidly when the sam- (FOM) commonly used for the Nyquist-rate ADC is
pling rate increases above 60 MS/s due to the incomplete set-
tling of the op amp. However, the SNDR shows a flat response (34)
618
TABLE II
PERFORMANCE COMPARISON TABLE.
The proposed cyclic ADC has an FOM of 504 fJ/step. Table I
shows the performance summary for this ADC.
Table II shows the comparison of the proposed ADC with
those of previous works [3], [4], [20], [21]. The proposed ADC
occupies an area smaller than mm , which is the smallest
design compared with similar resolution ADCs. The proposed
ADC also achieves the largest input frequency range, as listed
in Table II. Therefore, the proposed architecture is suitable for
sub-sampling applications where the signal band lies above the
Nyquist frequency.
V. CONCLUSION
An area-efficient cyclic ADC is proposed in this work. This
ADC employs a partial positive-feedback loop in the gain stage
to amplify the residue signal. A current-switching track-and-
hold circuit achieves a fast transient response to deal with a high
frequency input signal. The reduced time constant of the evalua-
tion loop and the track-and-evaluation property of the system are
shown to enhance the evaluation speed. The proposed architec-
ture is demonstrated in 90-nm digital CMOS technology. The
presented cyclic ADC achieves the smallest design compared
with other ADCs with similar sampling-rates and resolutions,
as shown in Table II.
ACKNOWLEDGMENT
The authors would like to acknowledge NTU-MediaTek Lab.
(MediaTek Inc.) for supporting this work and TSMC for chip
fabrication.
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HUANG AND LEE: A 0.02-mm 9-BIT 50-MS/s CYCLIC ADC IN 90-nm DIGITAL CMOS TECHNOLOGY 619

Yen-Chuan Huang was born in Taiwan in 1980. He Tai-Cheng Lee was born in Taiwan in 1970. He re-
received the B.S. and M.S. degrees in electrical engi- ceived the B.S. degree from National Taiwan Univer-
neering from National Taiwan University, Taipei, in sity in 1992, the M.S. degree from Stanford Univer-
2003 and 2005, respectively. He is currently working sity in 1994. and the Ph.D. degree from the University
toward the Ph.D. degree in electronics engineering at of California, Los Angeles, in 2001, all in electrical
National Taiwan University. engineering.
He worked for LSI Logic from 1994 to 1997 as
a circuit design engineer. He served as an Adjunct
Assistant Professor at the Graduate Institute of Elec-
tronics Engineering (GIEE), National Taiwan Uni-
versity, from 2001 to 2002. Since 2002, he has been
with the Electrical Engineering Department and GIEE, National Taiwan Uni-
versity, where he is an Associate Professor. His main research interests are in
high-speed mixed-signal and analog circuit design, data converters, PLL sys-
tems and RF circuits.