UCC28510, UCC28511, UCC28512, UCC28513, UCC28514, UCC28515, UCC28516, UCC28517

SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005

ADVANCED PFC/PWM COMBINATION CONTROLLERS
FEATURES D Provides Control of PFC and PWM Power D D D D
Stages In One Device Leading-Edge PFC, Trailing-Edge PWM Modulation for Reduced Ripple Built-In Sequencing of PFC and PWM Turn-On 2-A Source and 3-A Sink Gate Drive for Both PFC and PWM Stages Typical 16-ns Rise Time and 7-ns Fall Time into 1-nF Loads

DESCRIPTION
The UCC28510 series of combination PFC/PWM controllers provide complete control functionality for any off-line power system requiring compliance with the IEC1000−3−2 harmonic reduction requirements. By combining the control and drive signals for the PFC and the PWM stages into a single device, significant performance and cost benefits are gained. By managing the modulation mechanisms of the two stages (leading-edge modulation for PFC and trailing-edge modulation for PWM), the ripple current in the boost capacitor is minimized. Based on the average current mode control architecture with input voltage feedforward of prior PFC/PWM combination controllers, these devices offer performance advantages. Two new key PWM features are programmable maximum duty cycle and the 2x PWM frequency options to the base PFC frequency. For the PFC stage, the devices feature an improved multiplier and the use of a transconductance amplifier for enhanced transient response. The core of the PFC section is in a three-input multiplier that generates the reference signal for the line current. The UCC28510 series features a highly linearized multiplier circuit capable of producing a low distortion reference for the line current over the full range of line and load conditions. A low-offset, high-bandwidth current error amplifier ensures that the actual inductor current (sensed through a resistor in the return path) follows the multiplier output command signal. The output voltage error is processed through a transconductance voltage amplifier.

PFC Features
− Average-Current-Mode Control for Continuous Conduction Mode Operation − Highly-Linear Multiplier for Near-Unity Power Factor − Input Voltage Feedforward Implementation − Improved Load Transient Response − Accurate Power Limiting − Zero Power Detect

PWM Features
− − − − − Peak-Current-Mode Control Operation 1:1 or 1:2 PFC:PWM Frequency Options Programmable maximum duty cycle Programmable Soft-Start Two Hysteresis Options for Differing Hold-Up Time Requirements

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright  2004, Texas Instruments Incorporated

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1

UCC28510, UCC28511, UCC28512, UCC28513, UCC28514, UCC28515, UCC28516, UCC28517
SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005

DESCRIPTION (CONTINUED)
The transient response of the circuit is enhanced by allowing a much faster charge/discharge of the voltage amplifier output capacitance when the output voltage falls outside a certain regulation window. A number of additional features such as UVLO circuit with selectable hysteresis levels, an accurate reference voltage for the voltage amplifier, zero power detect, OVP/enable, peak current limit, power limiting, high-current output gate driver characterize the PFC section. The PWM section features peak current mode control (with a ramp signal available to add slope compensation), programmable soft-start, accurate maximum duty cycle clamp, peak current limit and high-current output gate driver. The oscillator for the combination controller is available in two versions. In UCC28510, UCC28511, UCC28512, and UCC28513, the PWM and the PFC circuits are switched at the same frequency. In the UCC28514, UCC28515, UCC28516, and UCC28517, the PWM stage frequency is twice that of the PFC frequency. The PWM stage is suppressed until the PFC output has reached 90% of its programmed value during startup. During line dropout and turn off, the device allows the PWM stage to operate until the PFC output has dropped to 47% (UCC28512, UCC28513, UCC28516, and UCC28517) or 71% (UCC28510, UCC28511, UCC28514, and UCC28515) of its nominal value. See available options table on page 1 for a summary of options. The UCC28510 family also features leading-edge modulation for the PFC stage and trailing-edge modulation for the PWM stage in order to reduce the ripple current in the boost output capacitor. The current amplifier implementation associated with this scheme also results in better noise immunity. Available in 20-pin N and DW packages.

SIMPLIFIED APPLICATION DIAGRAM
PRIMARY SECONDARY + RECT VOUT − + D1 − VAC + BIAS UCC2851X 11 12 13 14 15 Z 16 17 18 19 20 Z REF Z PWRGND GT1 SS2 PKLMT CAOUT ISENSE1 MOUT IAC VFF VREF GT2 VCC ISENSE2 VERR GND CT_BUFF D_MAX VSENSE RT VAOUT 10 9 8 7 6 5 4 + 3 2 1 PWM V−LOOP − REF

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UCC28510, UCC28511, UCC28512, UCC28513, UCC28514, UCC28515, UCC28516, UCC28517
SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005

ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)†}
Supply voltage VCC Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Gate drive current (GT1, GT2) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 A Pulsed Sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.5 A Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 A Maximum GT1, GT2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC+0.3 V Input voltage VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 11 V D_MAX, SS2, CAOUT, ISENSE1, MOUT, VFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VREF+0.3 V VAOUT, CT_BUFF, ISENSE2, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V Pin Current RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 mA VFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA CT_BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA VAOUT, VERR, ISENSE2, SS2, CAOUT, IAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum pin capacitance ISENSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 pF Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55 0C to 150 0C Storage Temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 0C to 150 0C Lead temperature 1.6mm (1/16 inch from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 0C Power dissipation PDIP (N) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W SOIC (DW) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute−maximum−rated conditions for extended periods may affect reliability. ‡ Currents are positive into, negative out of the specified terminal. All voltages are referenced to GND.

ELECTROSTATIC DISCHARGE (ESD) PROTECTION
PARAMETER Human body model CDM MAX 2.5 0.5 kV UNITS

AVAILABLE OPTIONS{}
OPTIONS PFC:PWM FREQUENCY RATIO 1:1 1:1 1:1 1:1 1:2 1:2 1:2 1:2 UVLO TURN-ON (V) 16 10.2 16 10.2 16 10.2 16 10.2 UVLO HYSTERESIS (V) 6.3 0.5 6.3 0.5 6.3 0.5 6.3 0.5 PWM UVLO2 TURN-OFF (V) 5.30 5.30 3.55 3.55 5.30 5.30 3.55 3.55 PWM UVLO2 HYSTERESIS (V) 1.45 1.45 3.2 3.2 1.45 1.45 3.2 3.2 PACKAGED DEVICES PDIP−20 (N) UCC28510N UCC28511N UCC28512N UCC28513N UCC28514N UCC28515N UCC28516N UCC28517N SOIC W−20 (DW) UCC28510DW UCC28511DW UCC28512DW UCC28513DW UCC28514DW UCC28515DW UCC28516DW

UCC28517DW † The DW package is available taped and reeled. Add R suffix to device type (e.g. UCC28510DWR) to order quantities of 2000 devices per reel. ‡ All devices are rated from −40°C to +105°C.

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UCC28510, UCC28511, UCC28512, UCC28513, UCC28514, UCC28515, UCC28516, UCC28517
SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x, TA = TJ, VCC = 12 V, RT = 156 kΩ, RCT_BUFF = 10 kΩ (unless otherwise noted)
supply current
PARAMETER Supply current, off Supply current, on TEST CONDITIONS VCC turn-on threshold −300 mV no load on GT1 or GT2 MIN TYP 100 4 MAX 150 6 UNITS µA mA

undervoltage lockout (UVLO)
PARAMETER UCC28510 UCC28512 UCC28514 UCC28516 VCC turn-on threshold UCC28511 UCC28513 UCC28515 UCC28517 UCC2851X UCC28510 UCC28512 UCC28514 UCC28516 UVLO hysteresis UCC28511 UCC28513 UCC28515 UCC28517 TEST CONDITIONS MIN 15.4 TYP 16 MAX 16.6 UNITS

9.7 9.1

10.2 9.7

10.8 10.6

VCC turn-off threshold

V

5.8

6.3

6.8

0.3

0.5

0.8

voltage amplifier
PARAMETER 25°C Input voltage VSENSE bias current Open loop gain High-level output voltage Low-level output voltage gM conductance Maximum source current Maximum sink current Over temperature VSENSE = VREF 2 V ≤ VAOUT ≤ 4 V ILOAD = –150 µA ILOAD = 150 µA IVAOUT = −20 µA to 20 µA TEST CONDITIONS MIN 7.39 7.35 50 5.3 0.00 70 −1 1 TYP 7.50 7.50 100 60 5.5 0.05 100 −3.5 3.5 mA 5.6 0.15 130 V µS MAX 7.61 7.65 300 V nA dB UNITS

PFC stage overvoltage protection and enable
PARAMETER Overvoltage reference window Hysteresis Enable threshold Enable hysteresis TEST CONDITIONS MIN VREF + 0.440 300 1.7 0.08 TYP VREF + 0.490 500 1.9 0.2 MAX VREF + 0.540 600 2.1 0.3 V UNITS V mV

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VCM = 0 V. UCC28514. total variation dc-to-dc ramp peak voltage dc-to-dc ramp amplitude voltage(1) (peak-to-peak) PFC ramp peak voltage PFC ramp amplitude voltage (peak-to-peak) 4. VCAOUT = 3 V ILOAD = –500 µA ILOAD = 500 µA See Note 1 oscillator PARAMETER fPWM.7 V. PWM frequency.2 –0.8 TYP –6 –90 –15 –290 –290 1 0 0 0 –406 MAX −9 −110 −50 −330 −330 1.0 0.5 kHz UNITS kHz voltage reference PARAMETER 25°C Input voltage Load regulation Line regulation Short circuit current Over temperature IREF = −1 mA to −6 mA 10.7 V.8 V ≤ VCC ≤ 15 V Line. VFF = 1. RCT_BUFF = 10 kΩ (unless otherwise noted) current amplifier PARAMETER Input offset voltage Input bias current Input offset current Open loop gain Common−mode rejection ratio High-level output voltage Low-level output voltage Gain bandwidth product(1) VCM = 0 V.50 7. UCC28512.0 V 5. UCC28515.2 –0. Ensured by design.3 0. low-line high-power output current IMOUT.6 0 6. voltage stability Frequency. VFF = 1. IAC = 500 µA. VCM = 0 V. Not 100% tested in production.50 5 1 –25 MAX 7.2 2.39 7. IAC = 150 µA. IAC = 300 µA.UCC28510.5 V.5 TEST CONDITIONS TA = 25°C 10. VFF = 1.25 V VAOUT = 5 V VAOUT = 1. VFF = 4. high-line high-power output current IMOUT.2 −462 1/V µA µA µA µW µA UNITS IMOUT. UCC28516.35 TYP 7. UCC28513.8 V ≤ VCC ≤ 15 V VREF = 0V −20 TEST CONDITIONS MIN 7. IAC-limited output current Gain constant (k) TEST CONDITIONS IAC = 500 µA.0 5. IAC = 150 µA. initial accuracy Frequency. VCC = 12 V. IAC = 150 µA.25 V VAOUT = 0.ti. IAC = 150 µA.5 V VAOUT = 5 V −343 MIN −3 −75 −10 −245 −245 0. Temp MIN 170 −1% 160 4.5 V VAOUT = 0.61 7.7 V. VFF = 1. VFF = 4. high-line low-power output current IMOUT. low-line low-power output current IMOUT.5 V MHz dB MAX 5 −100 100 nA UNITS mV 0 V ≤ VCM ≤ 1.3 V. RT = 156 kΩ.0 4. UCC28511. TEST CONDITIONS VCAOUT = 3 V VCAOUT = 3 V VCAOUT = 3 V 2 V ≤ VCAOUT ≤ 5 V MIN –5 TYP 0 −50 25 90 80 5. VFF = 4. IAC = 500 µA.65 15 10 −50 mV mA UNITS V V peak current limit PARAMETER PKLMT reference voltage PKLMT propagation delay PKLMT to GT1 TEST CONDITIONS MIN –20 150 TYP 0 300 MAX 20 500 UNITS mV ns multiplier PARAMETER IMOUT. VAOUT = 1.8 V.5 TYP 200 MAX 230 1% 240 5.5 3. VCM = 0 V.2 –0.0 4.7 V. IAC = 500 µA.com 5 .4 V.4 V.25 V VAOUT = 0.4 V.5 4.4 V. zero current Power limit (IMOUT × VFF) 1. IAC = 150 µA.25 V VAOUT = 5 V VAOUT = 5 V VAOUT = 2. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x. VFF = 2. www. VFF = 1.0 7. VFF = 4. TA = TJ.5 5.

65 UNITS V 1. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x.5 V.0 6 TYP –10. UCC28514.ti.50 MAX 1.55 V 1. Ensured by design.5 V.5 V. measured on VERR MIN 1.75 5. (UVLO2 = Low.45 1.84 PWM stage soft-start PARAMETER SS2 charge current SS2 discharge current Input voltage (VERR) TEST CONDITIONS VSENSE = 7.UVLO2 = Low MIN –7.com .50 140 UNITS V mV PFC gate driver PARAMETER GT1 pull-up resistance GT1 pull-down resistance GT1 output rise time GT1 output fall time Maximum duty cycle Minimum controllable pulse width CLOAD = 1 nF.15 V MIN 70% TYP 75% MAX 80% UNITS PWM stage pulse-by-pulse current sense PARAMETER Current sense comparator offset voltage TEST CONDITIONS ISENSE2 = 0 V. SS2 = 2.33 90 MAX 0.UCC28510.74 2.20 40 TYP 0. ENABLE = High) IVERR = 2 mA. RT = 156 kΩ.56 3.16 1.5 10 MAX –14. SS2 = 0 V VSENSE = 2.0 14 300 UNITS µA mA mV PWM stage duty cycle clamp PARAMETER Maximum duty cycle TEST CONDITIONS D_MAX = 4. UCC28516. Measured on VAOUT.30 TYP 6. falling edge rising edge MIN 0.3 MAX 7. 6 www.20 3. TEST CONDITIONS −100 mA ≤ ∆IOUT ≤ −200 mA IOUT = 100 mA RLOAD = 10 Ω 93% 120 MIN TYP 5 2 16 7 95% 150 MAX 12 10 25 15 100% 200 ns ns UNITS Ω PWM stage undervoltage lockout (UVLO2) PARAMETER PWM turn-on reference UCC2851X UCC28510 UCC28511 UCC28514 UCC28515 PWM turn-off threshold UCC28512 UCC28513 UCC28516 UCC28517 UCC28510 UCC28511 UCC28514 UCC28515 Hysteresis UCC28512 UCC28513 UCC28516 UCC28517 TEST CONDITIONS MIN 6. VCC = 12 V. UCC28513. UCC28515. RCT_BUFF = 10 kΩ (unless otherwise noted) zero power PARAMETER Zero power comparator threshold Zero power comparator hysteresis TEST CONDITIONS Measured on VAOUT. Not 100% tested in production.35 TYP 1. TA = TJ. UCC28512. UCC28511.30 UNITS 3.

5-V reference output Inverting input to the PFC transconductance voltage amplifier.com 7 . 1. UCC28513. CAOUT is internally connected to the PWM comparator input in the PFC stage Internally buffered PWM stage oscillator ramp output.ti. VCC = 12 V. Ensured by design. RCT_BUFF = 10 kΩ (unless otherwise noted) PWM stage overcurrent limit PARAMETER Peak current comparator threshold voltage Input bias current(1) TEST CONDITIONS MIN 1. typically used to program slope compensation with a single resistor Positive input to set the maximum duty cycle clamp level of the PWM stage Analog ground PFC stage gate drive output PWM stage gate drive output Multiplier current input that is proportional to the instantaneous rectified line voltage Non-inverting input to the PFC stage current amplifier Input for PWM stage current sense and peak current limit PFC multiplier high−impedance current output. TA = TJ.30 50 MAX 1. TEST CONDITIONS −100 mA ≤ ∆IOUT ≤ −200 mA IOUT = 100 mA RLOAD = 10 Ω MIN TYP 5 2 16 7 MAX 12 10 25 15 UNITS Ω Ω ns ns TERMINAL FUNCTIONS TERMINAL NAME CAOUT CT_BUFF D_MAX GND GT1 GT2 IAC ISENSE1 ISENSE2 MOUT PKLMT PWRGND RT SS2 VAOUT VCC VERR VFF VREF VSENSE NO. 15 5 4 6 12 10 18 16 8 17 14 11 2 13 1 9 7 19 20 3 Stage PFC PWM PWM − PFC PWM PFC PFC PWM PFC PFC − − PWM PFC − PWM PFC − PFC I/O O O I − O O I I I I/O I − I I I/O I I I O I DESCRIPTION Output of the current control amplifier of the PFC stage. UCC28514. internally connected to the current amplifier inverting input Voltage input to the PFC peak current limit comparator Power ground for GT1. UCC28516. Not 100% tested in production. typically connected to an optocoupler output Voltage feedforward pin for the PFC stage. UCC28515. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS TA = –40°C to 105°C for the UCC2851x. sources an IAC/2 current that should be externally filtered Precision 7. ENABLE and UVLO2 comparators www.15 TYP 1. UCC28512. RT = 156 kΩ. UCC28511.45 UNITS V nA PWM stage gate driver PARAMETER GT2 pull-up resistance GT2 pull-down resistance GT2 output rise time GT2 output fall time CLOAD = 1 nF.UCC28510. GT2 and high current return paths Oscillator programming pin that is set with a single resistor to GND Soft start for the PWM stage Output of the PFC transconductance voltage amplifier and it is internally connected to the Zero Power Detect comparator input and the multiplier input Positive supply voltage pin Feedback error voltage input for the PWM stage. and input to the OVP.

90. UCC28511.5 V REFERENCE 20 VREF D_MAX 4 VERR ISENSE2 7 8 SS2 13 VCC 9 + DETAILED PIN DESCRIPTIONS CAOUT (Pin 15): This is the output of a wide-bandwidth operational amplifier that senses line current and commands the PFC stage PWM comparator to force the correct duty cycle. The internal buffer can drive a typical 500-µA resistive load at this pin. UCC28514. and above the PFC ramp peak voltage to force zero duty cycle when necessary. UCC28513.7 V VCC ENABLE PWM STAGE SOFT START 7. 8 www. D_MAX (Pin 4): Program the maximum duty cycle at GT2 by applying a dc voltage to this pin. 9.5 V VFF 19 (VFF2 ) MIRROR 2:1 IAC MOUT 18 17 16 ISENSE1 15 CAOUT 6 GND + CURRENT AMP + PWM CLK1 R R S Q PFC ILIMIT + 11 14 PWRGND PKLMT 0.3 V + ILIMIT 10 GT2 R R S Q 3V UVLO 16 V. UCC28515. with the CT_BUFF frequency near 200 kHz.33 V + X ÷ MULT X 12 GT1 8. UCC28516.7 V. this voltage is set with a precision resistor divider powered by VREF. the maximum duty ratio is linearly related to D_MAX.7 V 10. A first order approximation.com .15 V 4V where. 9.75 V + UVLO2 1. is estimated by: D MAX ^ V DX * 1.9 V + RT 2 PFC:PWM Frequency 1:1 = IRT 1:2 = 0. This output can swing close to GND to command maximum duty cycle.2 V.0 V PFCOVP ZERO POWER VCC PWM PFC PWM 1. Between 0. CT_BUFF (Pin 5): The 4-V amplitude oscillator ramp is internally buffered at this pin to allow a resistor to be connected directly from this pin to ISENSE2 for slope compensation. DMAX is a dimensionless ratio VDX is the voltage at D_MAX in volts This pin can also be used to set DMAX to 0 by setting VDX less than 0. Connect current loop compensation components between CAOUT and MOUT. Usually. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 BLOCK DIAGRAM OSC CLK1 CLK2 1x:2x Option Only CT_BUFF 5 6. UCC28512.UCC28510.5 V + CLK1 CLK2 PWM + CLK2 PWM PFC VAOUT 1 gM VOLTAGE ERROR AMP VSENSE 3 + 7.ti.5I RT + IRT D_MAX COMP 1.09 and 0.

Connect a resistor between this pin and the grounded side of the PFC stage current sensing resistor.0 K V VFF 2 I IAC where. GT1 is disabled unless VCC is outside the UVLO region and VREF is on. UCC28513. Set the power range of the PFC stage with a resistor tied between the MOUT pin and the non-grounded end of the PFC current sense resistor. The recommended maximum IAC current is 500 µA. Use a resistor divider between VREF and the non-grounded side of the PFC current sense resistor in order to shift the level of this signal to a voltage that corresponds to the desired overcurrent threshold voltage. GT1 (Pin 12): A 2-A peak source and 3-A peak sink current totem pole MOSFET gate driver for the PFC stage. PWRGND must be externally connected to this pin. but adding a minimal series resistor of about 2 Ω between GT1 and the external MOSFET gate can reduce this overshoot. use a single small circuit trace to electrically connect between the circuits that use the GND return path and the circuits that use the PWRGND return path. UCC28516.UCC28510. identical to the driver at GT1. All voltages measured with respect to ground are referenced to this pin.5-V level shift between ISENSE2 and the input to the PWM comparator provides greater noise immunity.com 9 . in volts−1. A resistor between IAC and the line voltage converts the instantaneous line voltage waveform into a current input for the analog multiplier. measured across the PFC current sense resistor. The threshold for peak limit is 0 V. The multiplier output is a current and the current amplifier input is high impedance. with the peak limit threshold set to 1. The multiplier output current is given by: I MOUT + V VAOUT * 1. ISENSE1 (Pin 16): This pin is the non-inverting input terminal of the current amplifier. UCC28515. UCC28514. GT2 (Pin 10): A 2-A peak source and 3-A peak sink current totem pole MOSFET gate driver for the PWM stage. PKLMT (Pin 14): Program the peak current limit of the PFC stage using this pin. MOUT (Pin 17): The output of the multiplier and the input to the current amplifier in the PFC stage are internally connected at this pin. The resistor connected to this pin should have a value that equals the value of the resistor that is connected between the MOUT pin and the ungrounded side of the PFC current sense resistor.3 V for peak current mode control. Figure 36 shows the typical relationship of the capacitance on the ISENSE2 pin and the minimum controllable limit of the pulse width on the gate2 output. Some overshoot at GT1 can be expected when driving a capacitive load. www. The bypass capacitors for VCC and VREF should connect to this pin with as little lead length as possible. For best results.ti. PWRGND (Pin 11): Ground for the output drivers at GT1 and GT2. Connect impedance between the MOUT pin and the CAOUT pin to compensate the PFC current control loop. UCC28512. IAC (Pin 18): This multiplier input senses the rectified ac line voltage. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 DETAILED PIN DESCRIPTIONS (CONTINUED) GND (Pin 6): Signal ground for the integrated circuit. UCC28511. If the VERR is at the voltage that corresponds to a minimum controllable duty cycle and then is reduced further the pulse width collapses to near zero. ISENSE2 (Pin 8): A voltage across the PWM stage external current sense resistor generates the input signal to this pin. An internal 1. K is the multiplier gain constant. The oscillator ramp can also be summed into this pin for slope compensation. This ground should be tied to GND externally via a single Kelvin connection.

the current at VAOUT is proportional to the difference between the VREF and VSENSE voltages by a factor of gM. which serves as the PFC feedback connection point. The recommended range of resistors is 45 kΩ to 500 kΩ for a frequency range of 600 kHz to 65 kHz. which protects the part if VREF is short-circuited to ground. In all options. RT is in Ω fS is in Hz SS2 (pin 13): A capacitor between SS2 and GND programs the softstart duration of the PWM stage gate drive.5 V maximum to prevent overshoot. In the UCC28510. when operating outside the linear range. according to the following equation: RT + 31 1 1 Hz * 2. as measured at CT_BUFF. UCC28514.4 V. the zero power detect comparator ensures the PFC stage gate drive is turned off. VSENSE is internally connected to the PFC OVP. UCC28516 and UCC28517. The input voltage feedforward signal for the multiplier is then generated across an external single-pole R/C filter connected between VFF and GND. The internal reference is current limited to 25 mA. UCC28512. connect the GND side of the oscillator-programming resistor closer to the GND pin.35 V of its steady-state value.7-V UVLO threshold. the multiplier output current goes to zero. Instead.33 V. an internal 10. Connect the voltage compensation components between VAOUT and GND. VCC (Pin 9): Chip positive supply voltage that should be connected to a stable source of at least 20 mA between 12 V and 17 V for normal operation. VREF should be bypassed directly to GND with a ceramic capacitor between 0. 10 www.5 10 *6 3V Amp CSS2 is in Farads In the event of a disable command or a UVLO2 dropout. VSENSE (Pin 3): Inverting input to the PFC transconductance voltage amplifier. Decisive activation and deactivation of the voltage control recovery is internally implemented with about 120 mV of hysteresis at VSENSE. This pin is clamped to a maximum of 3 V and can demand 100% duty cycle at GT2. VAOUT (Pin 1): This transconductance voltage amplifier output regulates the PFC stage output voltage and operates between GND and 5. UCC28515. In the UCC28514. UCC28512 and UCC28513. When this output falls below 0. VERR (Pin 7): The voltage at this pin controls the GT2 duty cycle and is connected to the feedback error signal from an external amplifier in the PWM stage. At low line. UCC28513. do not connect a capacitor to this pin in an attempt to stabilize the voltage. In the linear range.3 mA. the magnitude of the current of VAOUT is increased in order to enhance the slew rate for rapid voltage control recovery in the PFC stage. UCC28511. A slew rate enhancement feature enables VAOUT to sink or source up to 3. SS2 quickly discharges to ground to disable the PWM stage gate drive.1 µF and 10 µF for stability. VREF (Pin 20): This is the output of an accurate 7.UCC28510. measured at CT_BUFF. The voltage is dc (nominally 3 V). respectively. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 DETAILED PIN DESCRIPTIONS (CONTINUED) RT (Pin 2): A resistor between RT and GND programs the oscillator frequency. the PFC stage operates at the same frequency as the PWM stage. The typical pull-up current flowing out of this pin is 10 µA. Bypass VCC directly to GND with a 0. the PFC stage operates at half the frequency of the PWM stage.ti. UCC28516. with a typical load regulation of 5 mV ensured for an external load of up to 6 mA. When the UVLO2 comparator enables the PWM stage. Enable and UVLO2 comparators as well. this pin sources or sinks up to 30 µA.5-V reference that powers most of the internal circuitry and can deliver over 10 mA. When this output goes below 1 V. VREF is disabled and remains at 0 V when VCC is below the 9. UCC28515.5-µA current source charges the external capacitor at SS2 to 3 V to ramp the voltage at VERR during startup. the PWM stage operates at the frequency that is measured at CT_BUFF. the VFF voltage should be set to 1. This allows the GT2 duty cycle to increase from 0% to the maximum clamped by the duty cycle comparator over a controlled time delay tSS given by: C SS2 + t SS 10. UCC28511.1 µF or larger ceramic capacitor to absorb supply current spikes caused by the fast charging of the external MOSFET gate capacitances.0 10 *12 f S 10 *7 W where. Outside this range. VFF (Pin 19): The output current from this pin comes from an internal current mirror that divides the IAC input current by 2.com . Resistor RT programs the oscillator frequency fS. When VSENSE operates within +/− 0.

com 11 . UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION L1 D2 D3 PRIMARY SECONDARY + R3 R1 R2 VAC R9 R8 R7 PGND PGND U1 UCC2851X GT2 10 11 PWRGND 12 GT1 13 SS2 R12 AGND C5 14 PKLMT 15 CAOUT C7 R14 VCC ISENSE2 VERR GND 9 8 7 6 5 4 3 2 1 C10 R21 C12 C11 U3 TL431 R24 R26 R20 R18 GND2 AGND PGND R19 U2 C13 R25 C14 R23 C4 R16 R11 R10 D5 C3 AGND REF R17 R22 D6 C1 Q1 R4 R5 Q2 GND2 − R6 T1 D4 C2 VOUT + D1 – C6 R13 R15 C8 C9 16 ISENSE1 CT_BUFF 17 MOUT 18 IAC 19 VFF 20 VREF REF D_MAX VSENSE RT VAOUT AGND GND2 Figure 1. UCC28512. UCC28511. UCC28514.ti. UCC28515.UCC28510. UCC28513. UCC28516. Typical Application Circuit: Boost PFC and Flyback PWM Power System www.

UCC28514. A comparison between the ripple current in the energy storage capacitor with traditional TEM/TEM modulation versus LEM/TEM modulation is shown in Figure 2. The PWM controller has all of the features for an isolated peak current program mode controlled converter. Equivalent PFC+PWM Power Supply System and the Comparison of the Energy Storage Capacitor Current for Traditional TEM/TEM with LEM/TEM Controllers. The LEM/TEM combination reduces the ripple current in the energy storage capacitor of the PFC stage. UCC28515. PFC BOOST CONVERTER i IN L1 i D1 D1 BUCK DERIVED CONVERTER i Q2 Q2 iL L2 i ES Q1 D AC – + VAC T ON OFF ON OFF TEM/TEM C ES D2 C OUT LOAD T Q1 OFF ON i D1 Q2 ON OFF i Q2 i ES i ES = i D1 − iQ2 LEM/TEM Figure 2. UCC28513.com . UCC28511. The two controllers are synchronized at a fixed frequency so that the PFC controller is leading edge modulated (LEM) and the PWM controller is trailing edge modulated (TEM). UCC28516. UCC28512. The PFC controller has all of the features for an average current mode controlled PFC.UCC28510. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION The UCC28510 series of combination controllers include a power factor correction (PFC) controller that is synchronized with a pulse width modulator (PWM) controller integrated into one chip. 12 www.ti.

However the capacitor current of the 1:2 option is less than a system that is TEM/TEM modulated. with little or no regulation. select the PFC versus PWM switching frequency based on the allowable switching loss of the intended PWM stage.20 PFC:PWM FREQUENCY RATIO 1:1 UCC28510 UCC28511 UCC28512 UCC28513 1:2 UCC28514 UCC28515 UCC28516 UCC28517 Select the UVLO option first. Other topology combinations can be used with this controller. The 16-V turn-on options are intended for applications where the bias voltage is self-generated from an auxiliary winding.45 3. The PWM stage can be designed for either continuous or discontinuous mode operation. www.UCC28510. Situations where the switching losses of the PWM stage permit higher switching frequencies can benefit from the 1:2 option. the diode in the PFC stage often has high reverse recovery currents that restrict the switching frequency of the PFC stage. For example. The PFC boost stage is typically designed for continuous conduction mode (CCM) of operation at full rated load in order to minimize line filter requirements. bias supply topology and gate drive voltage requirements. Then. UCC28512.ti. UCC28516. The energy storage capacitor ripple current for a system that is controlled by the 1:2 option will be larger than if it were controlled by a 1:1 option. UCC28514. UCC28513. Table 1.2 PWM HYSTERESIS (V) 1. the 1:2 option would be a good choice for PWM stages that have Schottky diode output rectifiers. The 10. A narrow range permits a highly optimized PWM stage. based on biasing topology. as necessary. The UVLO turn-on threshold is selected based on line range. Last. This device is available in two under voltage lock out (UVLO) turn-on thresholds. However. UCC28515. The programmable PWM duty ratio limit feature is especially useful when using two-transistor forward and flyback topologies for the PWM stage. UCC28511. Available Options UVLO TURN-ON THRESHOLD (V) 16 10.2 16 10. 1:1 and 1:2. Two options are available for the PFC:PWM switching frequency. select the PWM UVLO option based on bulk ripple voltage and load transients. However. two combinations of PFC/PWM switching frequencies as shown in Table 1. The best minimization of the energy storage capacitor ripple current occurs with the 1:1 option. Eight different options are available for the UCC2851x. The PWM UVLO hysteresis level option is selected based on the desired operational range of the energy storage capacitor voltage. the wider range permits larger energy storage capacitor voltage ripple and load transients. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION selection of controller options The UCC2851x is optimized for the most common combination of PFC/PWM stages.com 13 . Both versions are synchronized as LEM/TEM oscillators. as well. two PWM UVLO hysteresis levels and.2-V turn-on / 0. which is a boost PFC stage cascaded by a buck-derived PWM stage.5-V hysteresis options are intended for applications where the bias voltage is derived from an auxiliary supply source and is regulated.

VC1. the current limit and duty ratio limits of the PWM stage can clamp at a higher level than the average power clamp in the PFC stage. such as efficiency and permissible current harmonics could be given at the onset. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION design procedure The following discussion steps through the typical design process of a PFC/PWM converter system that is controlled by one of the UCC28510 options. If the instantaneous load nearly equals the average load. Thus. The PFC stage must always be designed to supply sufficient average power to the PWM stage. UCC28515. output power and ac line voltage range.5 line cycles. Each stage has an associated efficiency and each stage has its own set of fault limiting controls that must be properly set in order to achieve the desired line harmonic and load regulation performance. Typically. the minimum PFC duty ratio is given by: D 1(min) + 1 * 2 VAC MIN V C1 (1) 14 www. D1. or if the available line power is nearly equal to the output power of the power system.ti. UCC28511. is at least the period of 1. then the control elements for the PWM stage. Once the energy storage voltage. The cycle-by-cycle current limit of the PFC stage should be programmed to activate at a slightly larger power level at low ac line voltage than the average power clamp in order to allow for PFC current sense tolerances. UCC28514. Iteration typically begins after either simulating and/or testing the completed PFC/PWM system. then the fault clamps for the PWM stage can be programmed to limit power at a level that is slightly less than or equal to the average power clamp of the PFC stage. UCC28513. The general structure of the PFC/PWM stage power system is two switched-mode converters connected in cascade. This will allow power factor correction for the full range of maximum rated load. is determined. the voltage across C1 must be larger than the peak ac line voltage by enough to permit controllability in the event of load transients. is set. UCC28512. For CCM operation of the PFC stage.UCC28510. The need for power factor correction arises from either an agency requirement. all of the current limits and duty cycle limits are programmed to clamp power at a slightly lower level (10%) than the average power clamp on the PFC stage. then the control elements for the PFC stage. or developed throughout the product design cycle. This design procedure refers to the typical application in Figure 1. Keep in mind that a general design process is often iterative. A design begins with a list of requirements for output voltage. UCC28516. The design process begins with the power stage elements. developing the internal parameters Select the energy storage voltage VC1 (the voltage on the PFC output capacitor). the hold-up time. this will be around 5% which is about 400 V for a universal ac line application of 85 VAC to 265 VAC. Other details. tHU.com . if the instantaneous load has high peaks that are much shorter than the hold-up time. the range of the PFC stage duty ratio. In order to simplify the design procedure. Typically. Hold-up time requirements are also necessary at the early stages of design. such as IEC−61000. simultaneously. Since the PFC stage is a boost converter. The margin for the clamping action should allow for measurement tolerances and efficiency. Conversely. the average and the peak loads of the PWM stage are assumed to be equal.

Select an appropriate topology for the PWM stage using the information about the power requirements and the magnitude of VC1. based on the topology. In most cases. PWM hysteresis option and output voltage requirements of the PWM stage.0 10 *12 f S(pwm) 10 *7 (3) 31 Most applications require that the PWM stage regulates at the minimum energy storage capacitance voltage. k1R. V C1(min) + 1 * k 1R V C1(nom) (4) At this point. UCC28514. or in order to optimize the design of L1. Adjustments in switching frequency may result from meeting switching loss requirements in Q1 and D3. k1R = 0. Maximum duty ratio D2(max) and iQ2(peak) should be calculated for the minimum energy storage voltage in order to estimate the peak current stresses for transformer T1 and any other inductive element in the PWM stage. UCC28516. A good starting frequency for a MOSFET based PFC stage is in the range of 100 kHz to 200 kHz. UCC28516.ti. the PWM stage topology must have transformer isolation and the topology must require only one pulse-width signal. Base the estimation for the switching frequency of the PWM stage on the maximum voltages and currents of the power MOSFETs and power diodes. www.53. of the energy storage voltage. as described by equation 2. k 1R ^ 0. sudden step changes during steady state operation.com 15 . D2(max) and the associated peak Q2 drain current.29 for UCC28510. For simplicity. UCC28515 0. UCC28511. The PWM stage can be optimized best with the small PWM hysteresis range because the maximum primary current of transformer T1 (which occurs at minimum VC1) is smallest with the small PWM hysteresis range.53 for UCC28512. iQ2(peak)). UCC28514. depending on maximum line voltage and maximum line current. Select an approximate switching frequency for the PFC stage. Select the small PWM hysteresis option if the system load has moderate step changes or slow load changes during steady state operation. enough information is available to estimate which member of the UCC28510 family should be selected. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION Select the regulation constant. UCC28515. UCC28512. R20 + 1W 1 Hz * 2. UCC28513. UCC28511. Also estimate whether or not it is appropriate to operate the PWM stage at the same switching frequency as the PFC stage or if the PWM stage can operate at twice the switching frequency of the PFC stage. UCC28513. UCC28517 (2) There are effectively two options for k1R that directly relate to the two PWM hysteresis options. the typical application in Figure 1 shows a flyback converter in the PWM stage. Program the oscillator frequency of the PWM stage with the value of R20. Topologies that have these features include: • • • • single-transistor forward converter single-transistor flyback converter two-transistor forward converter two-transistor flyback converter Estimate the nominal and the maximum duty ratios of the PWM stage (D2(nom) .UCC28510. Select the large PWM hysteresis option if the system load has large.29 and k1R = 0.

16 www. L1. The PFC stage inductor. Q1. The PWM stage is an isolated dc-to-dc topology with the same stresses and loss mechanisms that are typical for the selected topology. Also. the natural step response of the PWM stage is required to estimate the soft start capacitor. C3. due to their dependence on the choice PWM stage topology. The selection process of the PFC stage elements C1.com . C3.UCC28510. If the line current has excessive crossover distortion. UCC28514. Gate drive resistor R9 is necessary to limit the source and sink current from the GT1 pin.3) will reduce the distortion but the line current will have more switching ripple. R5. UCC28511. D5. is chosen to be about 0. D4. a larger ripple factor (perhaps 0. Some circumstances require additional gate drive components for improved protection and performance. In general. is required between the GT2 pin and the gate of Q2 for the same reason. Details concerning the PWM stage elements C2. Initially. Diode D2 allows capacitor C1 to charge during initial power up without saturating L1 and it is selected to withstand the peak inrush current and peak of the maximum ac line voltage. UCC28516. R2. L1. C5.ti. Q2. R10. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION power stage elements The power stage elements include the following elements: C1−3. the inductance can be estimated by approximating the input power equal to the output power. L1 + V AC(min) 2 D 1(min) k RF P IN T S(pfc) (5) where. UCC28513. is selected to have a maximum current ripple at the minimum ac line voltage.[10] A similar gate drive resistor. and the bias supply capacitor. Additional inrush current limiting circuitry in series with the ac line could be required. Typically a ripple factor. except for capacitor C1 due to PFC/PWM stage synchronization. UCC28515. k RF + and T s(pfc) is Di L1(p−p) i L1(max) 1 switching frequency of the PFC Inductor L1 must be designed to withstand the maximum ac rms line current without saturation at the peak ac line current. Select power MOSFET Q1 and diode D3 with the same criteria that is normally used for fixed switching frequency PFC design. They must have sufficient voltage rating to withstand the energy storage voltage. An estimation of the average steady state duty ratio of the PWM stage and the Q2 switch current will be needed for stress estimations in the PFC stage. D1−5. the selection process for the PFC stage elements is the same as for a typical fixed switching frequency PFC design.2. UCC28512. Q2 and T1 will not be discussed in detail here. D1−3 and Q1 are discussed in detail here. kRF. Diode bridge D1 is selected to withstand the rms line current and the peak ac line voltage. depending on agencies or situations. VC1 and they must have sufficient current ratings. T1.

is selected to operate over a 1-V dynamic range (VDYNAMIC). Draw a horizontal line from the intersection to the vertical axis and read the ratio of IC1(rms) to IQ2. So. To use the graphs.UCC28510. I C1(rms) I Q2 t 8 2 3 D 2(nom) p 2 V C1(nom) V AC(min) ) D 2(nom) (9) The ratio of IC1(rms) to IQ2 can be found by using the appropriate graph. UCC28513. The sense resistor must also have a large enough power rating to permit safe operation with the maximum RMS line current. www. The bias voltage is established with R14 and R7.ti. i L1(max) + The PFC ILIMIT comparator threshold is at the ground reference for the controller device. UCC28512. UCC28515. An initial estimate can be made using the inequality in equation 9. then consult Figure 3 or Figure 4 for better accuracy. UCC28514. R2. that is produced by the combined action of the PFC stage and the PWM stage. IC1(rms). UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION The current sense resistor for the PFC stage. UCC28516. UCC28511. R7 + R14 1 VREF *1 iL1(max) R2 (7) The capacitance value of the energy storage capacitor. locate the ratio of VAC to VC1 along the horizontal axis then. C1 is selected to meet hold-up time requirements (tHU) by the equation: C1 + 2 V C1 2 P OUT t HU (8) k R1 2 * k R1 Capacitor C1 must be rated for the selected energy storage voltage and it must be able to withstand the rms ripple current. draw a vertical line to the intersection of the curve for the duty ratio of the PWM stage. the PFC current sense voltage.0 V when the instantaneous PFC current is at its maximum.5 Di L1(p−p) 2 P IN V AC(min) (6) where. measured at PKLMT must be biased with a positive voltage to cross 0.com 17 . R2 + V DYNAMIC i L1(max) ) 0. and resistor R14 is arbitrarily chosen around 10 kΩ. Figure 3 for the 1X:1X oscillator option or Figure 4 for the 1X:2X oscillator option. The average Q2 drain current during the interval that GT2 activates MOSFET Q2 is used to find IC1(rms). as shown in equation 7.

4 0. UCC28511.3 VAC/VC1 0.6 1. UCC28513.6 1.4 0.6 0.com . UCC28512.1 0.6 DPWM = 0. fPFC:fPWM = 1:2 2.4 0. Graph for Finding IC1(rms) for the 1X:2X Oscillator Option 18 www.0 1.5 0.8 0.7 DPWM = 0.4 0.1 0. fPFC:fPWM = 1:1 1. Graph for Finding IC1(rms) for the 1X:1X Oscillator Option IC1(rms)/IQ2 vs VAC.0 0.5 0.8 DPWM = 0.0 0.3 DPWM = 0.4 1.8 1.2 0.6 0.5 DPWM = 0.0 0. UCC28515.2 1. UCC28516.3 Figure 4.2 0.2 0.4 0.7 DPWM = 0.7 DPWM = 0.4 DPWM = 0.0 DPWM = 0.3 0.4 1.2 0. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION IC1(rms)/IQ2 vs VAC. UCC28514.0 0.7 DPWM = 0.6 VAC/VC1 Figure 3.5 0.6 0.ti.UCC28510.6 0.0 0.2 1.

0 v V VAOUT(t) v 5 V. UCC28513. Select the components R1 and R15 to use the iIAC(t) range and the VVFF range under the condition that the maximum of the VVAOUT range. Typically. second. stabilize the voltage loop that controls the energy storage capacitor voltage. R5 + V TH PWM stage i Q2(peak) I LIMIT (10) In many cases. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION The current sense resistor for the PWM stage. its voltage is the threshold voltage of the peak current comparator (nominally 1. UCC28515. 1. The voltage loop must be slower than twice the ac line frequency so that it will not compromise the power factor.4 V v V VFF v V VREF * 1. except for the VFF voltage and MOUT current limitations. Notice that the voltage at the VFF pin will be proportional to the average of the IAC current.3 V).4 V (11) www. VAOUT and VFF pins. 0 v i IAC(t) v 500 mA.4 V or VVFF.com 19 . PFC stage control The PFC stage is designed in a three-step process. power factor correction may still occur if the VAOUT level is within the functioning range of the multiplier. set the dynamic range of the multiplier. We urge you to refer to Reference [11] for details.4-V level controls the divider. is selected so that at maximum current.4 V at low ac line voltage is set as the design boundary. Use as much of the dynamic range of the multiplier as possible. Coordinate the selection process to use the full range of the multiplier and obtain the desired power limiting features.[12] In this product series. The input line filter design has been omitted from this procedure due to the vast array of requirements and circumstances. Power factor correction occurs during that condition because the multiplier section functions as a two-input multiplier. described in equation 11. UCC28512. UCC28514. the divide-by-square function is internally implemented so that it divides by the greater of 1. the upper boundary of VVFF will remain within the range if the functional ac line voltage range varies by less than 4. If the 1. First. stabilize the average current control loop and third. VVFF=1. an input line filter will be necessary in order to meet the requirements of an agency or application. The selection process is similar to the selection process for UC3854. UCC28516. UCC28511.3:1. The current control loop must have wide bandwidth in order to follow the instantaneous rectified line voltage.UCC28510. rather than a three-input multiplier. multiplier The dynamic range of the multiplier is a function of the currents and/or voltages of the IAC.ti. R5.

0V Always change R8 if R12 is changed R12 PFC current loop control This controller uses average current loop control for the PFC stage. R12. to average the VFF voltage with sufficiently low ripple to meet a third harmonic distortion budget. MIN). R8.4V VVAOUT(max) = 5. UCC28513. may need to be increased slightly if the energy storage capacitor voltage sags under maximum load. equal to the value of R12 as shown in in Table 2. Table 2.5% third harmonic distortion to the input waveform [4].UCC28510. The left side of the inequality in equation 12 will usually be true since the capacitance of C1 is quite large. Finally. select R15 for the minimum VFF voltage. set the value of the resistor on the ISENSE1 pin. This would be due to tolerances in the components and the multiplier. An attenuation factor of 0.[5] This method assumes that both the natural frequency of the system and the zero of the linearized boost PFC are much lower than both the switching frequency and the desired crossover frequency. R12. Second. the multiplier output resistor. There are many ways to design a controller that will stabilize the PFC current loop. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION The selection process begins with the selection of R1 so that the peak IAC current at high ac line is about 500 µA. The current control loop must typically be fast enough to track the rectified sinusoidal ac line voltage. The method that is described here achieves good results for most applications. Experimentally. as described in equation 12.022 for 3% THD C8 2 p AC R1 FF(2) k V R12 2 R8 pk V R2 FF(min) *1V AC(min) VAOUT(max) k = 1/V VAC(min) = minimum RMS input voltage VVFF(min) = 1. 1 * D PWM(min) L1 C1 and C1 2P IN V C1 2 tt 2 p f CO(pfc) tt 2 p f S(pfc) (12) 20 www. so that the voltage across R12 equals the voltage across sense resistor R2 under the condition of maximum power. in Table 2. also shown in Table 2. select the MOUT resistor in Table 2. minimum ac line voltage (VVFF.4 V A FF(2) + 0. REFERENCE DESIGNATOR R1 2V I 2 AC(max) EQUATION set i NOTES + 500 mA IAC(peak) IAC(peak) V R1 VFF(avgmin) 0. In order to minimize current amplifier offsets. Third.com . and VAOUT at its maximum level of 5 V. see Table 2.9 R15 2 I V R15 V f AC(min) 1 A set V VFF(avgmin) + 1.022 will meet the criteria.ti. UCC28516. UCC28514. UCC28511. For a system with a 3% THD target. UCC28512. UCC28515. it is typical to allow the feedforward circuit to contribute 1. select C8. fCO(pfc).

75 V. Many applications require a duty ratio limit for the PWM stage in order to prevent transformer saturation. Resistor R17 represents the gain in the conversion from the output current of opto-isolator U2 and the VERR input. UCC28516. V VREF R16 + *1 R19 1 V ) 4 V D PWM(max) (13) Soft-start The soft-start capacitor. On the primary side.ti. UCC28512. U2. Program the maximum duty ratio using the following ratio of resistors R16 to R19. which is connected to SS2. UCC28515. then select C6 to place a zero at the crossover frequency and select C7 to provide a pole at half of the switching frequency. The equations are in Table 3. Upon selecting the crossover frequency. and a pull-up resistor. similar to ripple on the VFF voltage. which form a summing node at ISENSE2. The secondary elements include C12 to C14. In order to avoid loop saturation. compensation and isolation functions. or if the compensator gain at the crossover frequency is large (over ~40 dB). U2 and U3. controls the soft-start ramp of the PWM stage. C5. Slope compensation is programmed using resistors R18 and R11. VERR is connected to the node between the opto-isolator output. D6. For the purposes of 50 Hz to 60 Hz power factor correction. the right side of the inequality should be at least five times larger than the middle term. Table 3. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 APPLICATION INFORMATION The left side of the inequality should be at least a factor of 10 lower than the middle term.com 21 .UCC28510. Second harmonic ripple from the sensed VC1 voltage directly results in third harmonic distortion on the ac line. good results can be achieved with the crossover frequency set to about 10 kHz. PWM stage control The control elements of the PWM stage are the same as a typical isolated current program mode converter. The soft-start ramp begins when the VSENSE voltage exceeds 6. the soft-start ramp rate must be less than or equal to the open loop response of the PWM stage converter. select R13 to set the gain at the crossover frequency. UCC28511. The voltage at CT_BUFF is a saw-tooth waveform that swings between 1 V and 5 V. UCC28513. REFERENCE DESIGNATOR 2 R13 R12 1 p 1 f S(pfc) R13 p f EQUATION CO(pfc) V L1 C1 V R2 CT_BUFF(p−p) V CT_BUFF(p−p) NOTES +4V VC1 is the output voltage of the PFC C6 C7 R13 p 2 f CO(pfc) PFC voltage loop The voltage loop must crossover at a lower frequency than twice the ac line frequency so that voltage corrections will not interfere with power factor correction. A lower crossover might be necessary if the switching frequency of the PWM stage is below 100 kHz. www. R17. UCC28514. which perform the error amplifier. R22 to R25.

Section A + Figure 6. UCC28511. TI literature number SLUU117.com . 6.com for further details.UCC28510. UCC28512. UCC28514. UCC28516. UCC28513. + Figure 5. 7. Section B 22 www. 8-W bias rail supply design is discussed in UCC28517EVM. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 REFERENCE DESIGN Universal line input 100-W PFC output with 12 V.ti. UCC28515.ti. The schematic is shown in Figures 5. Please refer to the SLUU117 document on http://www.

UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 REFERENCE DESIGN Note: D10 and D9 are Schottky diodes from Vishay. UCC28513. UCC28515. UCC28516. Section C www.com 23 . BYS10−25 Figure 7. part no. UCC28511.ti. UCC28512.UCC28510. UCC28514.

5 0.0 14.0 12.0 3. UCC28512.UCC28510.com .60 7.40 −50 REFERENCE VOLTAGE vs TEMPERATURE −25 0 25 50 75 100 125 VCC − Supply Voltage − V Temperature − °C Figure 10 Figure 11 24 www.5 4.8 3.5 2.0 1.8 4. UCC28514.50 7.0 18. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS STARTUP CURRENT vs TEMPERATURE 140 UCC 28510/12/14/16 ICC − Supply Current − mA 5. UCC28516.54 7.58 7.0 6.5 1.52 7.56 7.5 ICC − Supply Current − mA 3.0 −50 −25 SUPPLY CURRENT vs TEMPERATURE ICC(off) − Startup Current − µA 130 120 110 100 UCC 28511/13/15/17 90 0 25 50 75 100 125 Temperature − °C Temperature − °C Figure 8 Figure 9 SUPPLY CURRENT vs SUPPLY VOLTAGE 4.0 8.2 80 −50 −25 0 25 50 75 100 125 3.0 16.4 4.0 0.46 7.48 7. UCC28513.0 10.42 7. UCC28511.6 4.ti.6 3. UCC28515.0 4.0 2.2 V UVLO Turn-On Threshold VREF − Reference Voltage − V 7.44 7.0 16 V UVLO Turn-On Threshold 10.0 4.0 3.4 3.2 4.

0 VCC = 12 V VREF − External Load Current − mA IREF − External Load Current − mA Figure 12 PFC UVLO THRESHOLDS vs TEMPERATURE (UCC28510/2/4/6) 18 UVLO On 16 10 14 UVLO Threshold − V UVLO Threshold − V 12 UVLO Off 10 8 6 4 2 2 0 −50 −25 0 25 50 75 100 125 0 −50 −25 0 UVLO Hysteresis 8 12 Figure 13 PFC UVLO THRESHOLDS vs TEMPERATURE (UCC28511/3/5/7) UVLO On UVLO Off 6 4 UVLO Hysteresis 25 50 75 100 125 Temperature − °C Temperature − °C Figure 14 Figure 15 www.0 20.475 7. UCC28515. UCC28514.500 7.465 7.UCC28510.480 7.0 2. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS VREF vs LOAD CURRENT 7.460 0 10 20 30 40 0.0 VCC = 15 V VCC = 10 V VREF CURRENT LIMIT 8.470 7.0 VREF − V 4.0 5.com 25 .495 VREF − Reference Voltage − V 7.0 6.0 15.0 7.485 7.0 3.0 10.0 1. UCC28516.0 5.0 0.490 7. UCC28511.ti. UCC28512. UCC28513.

UCC28512. UCC28515.com . UCC28516.Oscillator Frequency − kHz 600 500 400 300 200 100 0 10 100 RT − Timing Resistor − kΩ 1000 0 OSCILLATOR FREQUENCY vs RT OVER VCC (11 V TO 15 V) (−40°C TO 105°C) 100 10 100 RT − Timing Resistor − kΩ 1000 Figure 18 Figure 19 26 www.ti. UCC28514. UCC28511.Oscillator Frequency − kHz f .UCC28510. UCC28513. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS PWM UVLO2 THRESHOLDS vs TEMPERATURE (UCC28510/1/4/5) 8 7 6 5 4 3 2 UVLO2 Hysteresis 1 0 −50 −25 0 25 50 75 100 125 Temperature − °C 1 0 −50 UVLO2 On 8 7 6 UVLO2 Threshold − V 5 4 3 PWM UVLO2 THRESHOLDS vs TEMPERATURE (UCC28512/3/6/7) UVLO On UVLO2 Threshold − V UVLO2 Off UVLO Off UVLO Hysteresis 2 −25 0 25 50 75 100 125 Temperature − °C Figure 16 Figure 17 OSCILLATOR FREQUENCY vs RT 1000 800 700 f .

ti. GT2 RISE AND FALL TIMES vs TEMPERATURE tR 14 12 10 8 6 4 2 0 −50 −25 0 25 50 75 100 125 tR: RSERIES = 10 Ω tF Temperature − °C Figure 22 Figure 23 www.85 V) 100 GT1. UCC28514.UCC28510. tF − Rise and Fall Time − ns tF: RSERIES = 2 Ω 18 16 GT1. GT2 PULL-UP. PULL-DOWN RESISTANCE vs TEMPERATURE 8 7 GT1 Maximum Duty Cycle − % RDS(on) − Gate Resistance − Ω 99 6 5 4 3 2 1 0 Pull-up 98 97 96 Pull-down 95 94 0 100 200 300 400 500 −50 −25 0 25 50 75 100 125 GT1 Switching Frequency − kHz Temperature − °C Figure 20 Figure 21 GT1 RISE/FALL TIME vs CLOAD AND RSERIES (VCC = 12 V) 45 40 tR.com 27 . UCC28515. tF − Rise and Fall Time − ns 35 30 25 20 12 10 5 0 0 2 CLOAD − nF 4 6 tF: RSERIES = 10 Ω tR: RSERIES = 2 Ω tR. UCC28516. UCC28513. UCC28511. UCC28512. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS GT1 MAXIMUM DUTY CYCLE vs PFC SWITCHING FREQUENCY (CAOUT = 0.

0 0.8 1.com . UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS GT2 MAXIMUM DUTY CYCLE vs D_MAX VOLTAGE 100 100 kHz IMOUT − Multiplier Output Current − µA 90 GT2 Maximum Duty Cycle − % 80 70 60 50 800 kHz 40 30 20 10 0 1.4 V 1.8 V 200 150 100 50 IAC = 500 µA VFF = 4. UCC28513.0 VAOUT − Voltage Error Amplifier Output − V VFF − Feedforward Voltage − V Figure 26 Figure 27 28 www.5 3. VFF = 1.0 3. UCC28515.5 5.5 4.0 3. UCC28514. UCC28512.8 IMOUT x VFF − µW 400 350 300 350 200 150 VAOUT = 2 V IAC = 300 µA.4 V IAC = 300 µA VFF = 2.0 2.5 0 1 2 3 4 5 VAOUT = 3 V VAOUT = 4 V Multiplier Gain − K 1.5 2.5 3. UCC28516.ti.5 5.5 D_MAX Voltage − V 200 kHz 500 kHz 350 MULTIPLIER OUTPUT CURRENT vs VOLTAGE ERROR AMPLIFIER OUTPUT 300 350 IAC = 150 µA VFF = 1.8 V 100 50 IAC = 500 µA.UCC28510.0 4.7 V 0 1.6 1. VFF = 2.5 2 2.0 2.0 Figure 25 MULTIPLIER CONSTANT POWER PERFORMANCE 500 450 VAOUT = 5 V 1.0 1. VFF = 4.0 5.0 1.5 4.7 V 0 4. UCC28511.0 Figure 24 MULTIPLIER GAIN vs VOLTAGE ERROR AMPLIFIER OUTPUT 2.0 5.2 IAC = 150 µA.4 1.0 4.0 VAOUT − Voltage Error Amplifier Output − V 6.

2 7. UCC28513. Phase − Degree 90 60 30 0 −30 −60 −90 1 102 104 Frequency − Hz 106 0 108 −50 −25 0 25 50 75 100 125 Gain gm − VEA Transconductance − µs 120 VOLTAGE AMPLIFIER TRANSCONDUCTANCE vs TEMPERATURE 100 80 60 40 20 Temperature − °C Figure 28 Figure 29 VOLTAGE AMPLIFIER OUTPUT CURRENT CAPABILITY 4 40 30 VEA − Output Current − µA 20 10 0 −10 −20 −30 −40 7. UCC28515.ti. UCC28511.8 VSENSE − Voltage Normalized to VREF − V 8.0 7.0 VOLTAGE AMPLIFIER OUTPUT CURRENT IN LINEAR REGION OF OPERATION Voltage Amplifier Output Current − mA 3 2 1 0 −1 −2 −3 −4 VSENSE − Voltage Normalized to VREF − V 7.8 8.UCC28510. UCC28516.4 7.0 Figure 30 Figure 31 www. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS CURRENT AMPLIFIER OPEN LOOP GAIN AND PHASE 150 120 Phase Gain − dB.2 7.0 7. UCC28512. UCC28514.com 29 .6 7.6 7.4 7.

UCC28510.ti. UCC28514.com . ISINK − mA 3 2 1 0 −1 −2 ISINK ICHG − µA. UCC28511. IDISCHG −mA 10 15 Figure 33 SOFTSTART CURRENTS vs TEMPERATURE IDISCHG (mA) 5 0 −5 ICHARGE (µA) −3 −4 −5 −50 ISOURCE −10 −15 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Temperature − °C Temperature − °C Figure 34 Figure 35 30 www. Phase − Degree 120 Phase 250 300 VOLTAGE AMPLIFIER VSENSE BIAS CURRENT vs TEMPERATURE 200 90 60 Gain 150 100 30 0 50 −30 10 103 Frequency − Hz 0 105 107 −50 −25 0 25 50 75 100 125 Temperature − °C Figure 32 VOLTAGE AMPLIFIER SLEW CURRENTS vs TEMPERATURE 5 4 VEA ISOURCE. UCC28513. UCC28516. UCC28515. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS VOLTAGE AMPLIFIER OPEN LOOP GAIN AND PHASE 180 VAOUT Load = 15 pF IIB − VEA VSENSE Bias Current − nA 150 Gain − dB. UCC28512.

UCC28515.UCC28510. UCC28516. UCC28513. UCC28514.com 31 .ti. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 TYPICAL CHARACTERISTICS TYPICAL MINIMUM ON TIME vs CAPACITANCE 60 Absolute Maximum Limit of Capacitance Allowed 50 Duty Cycle − % 40 30 20 10 0 0 100 200 300 400 500 Capacitance − pF Figure 36 www. UCC28512. UCC28511.

L.H. 2001 11. UCC28516. UCC28513. UCC38500/1/2/3 BiCMOS PFC/PWM Combination Controller. Evaluation Module and associated User’s Guide. Texas Instruments Literature Number SLUP093 5. leading edge trailing edge modulation Tracking boost topology for dynamic output voltage adjustments High PF. Optimizing the Design of a High Power Factor Switching Preregulator. Dixon. Noon 6. Texas Instruments Literature Number SLUS419C 3. 2001 Power Supply Design Seminar Manual SEM1400. Design Note. UC3854 compatible.ti. A Design and Application Guide for High Speed Power MOSFET Gate Drive Circuits. Dixon. Application Note. 2002 RELATED PRODUCTS PART NUMBER UCC38500/1/2/3 UCC3817/18 UCC3819 UC3854 UC3854A/B UC3855A/B UC3853 UCC38050 UC3852 DESCRIPTION BiCMOS PFC/PWM combination controller BiCMOS power factor preregulator Programmable output power factor preregulator High Power Factor Preregulator Enhanced high power factor preregulator High performance power factor preregulator High power factor preregulator Transition mode PFC controller High power factor preregulator COMMENTS 1:1 leading edge. 50% PWM Max dc High PF. 35 VCC max Improved high PF. UC3854A/B and UC3855A/B Provide Power Limiting with Sinusoidal Input Current for PFC Front Ends. Texas Instruments Literature Number SLUA177 9. Design Note.UCC28510. Optimizing Performance in UC3854 Power Factor Correction. High Power Factor Preregulator for Off-line Power Supplies. Power Supply Seminar SEM−600. UCC28515. trailing edge modulation. UCC28512. Design Note. Understanding and Optimizing Electromagnetic Compatibility in Switchmode Power Supplies. Texas Instruments Literature Number SLUP087 4. UCC28517EVM. UCC28514. Designing High-Power Factor Off−Line Power Supplies. UCC28517 SLUS517C − DECEMBER 2002 − REVISED SEPTEMBER 2005 REFERENCES 1. industry standard PFC controller. industry standard PFC controller. 22 VCC max ZVT output for lower EMI emission & higher efficiencies 8-Pin package. Laszlo Balogh. 2002 Power Supply Design Seminar Manual SEM1500. simplified architecture to minimized external components Constant on-time transition mode PFC controller Constant off-time transition mode PFC controller. Texas Instruments Literature Number SLUA196 10. UCC28511. L. 30 VCC max 32 www. UC3854 Controlled Power Factor Correction Circuit Design .Texas Instruments Literature Number SLUA144 7. Bob Mammano and Bruce Carsten. Power Supply Seminar SEM−700. UC3854A and UC3854B Advanced Power Factor Correction Control ICs. Texas Instruments Literature Number SLUS419C 2. Datasheet. Power Supply Seminar SEM−1500 Topic 2.H. by James P. Texas Instruments Literature Number SLUA172 8.com .

com 16-Mar-2011 PACKAGING INFORMATION Orderable Device UCC28510DW UCC28510DWG4 UCC28510N UCC28510NE4 UCC28511DW UCC28511DWG4 UCC28511DWR UCC28511DWRG4 UCC28511N UCC28511NE4 UCC28512DW UCC28512DWG4 UCC28512DWR UCC28512DWRG4 UCC28512N UCC28512NE4 UCC28513DW UCC28513DWG4 UCC28513DWR Status (1) Package Type Package Drawing SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC DW DW N N DW DW DW DW N N DW DW DW DW N N DW DW DW Pins 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 Package Qty 25 25 20 20 25 25 2000 2000 20 20 25 25 2000 2000 20 20 25 25 2000 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 .ti.PACKAGE OPTION ADDENDUM www.

PACKAGE OPTION ADDENDUM www.com 16-Mar-2011 Orderable Device UCC28513DWRG4 UCC28513N UCC28513NE4 UCC28514DW UCC28514DWG4 UCC28514DWR UCC28514DWRG4 UCC28514N UCC28514NE4 UCC28515DW UCC28515DWG4 UCC28515DWR UCC28515DWRG4 UCC28515N UCC28515NE4 UCC28516DW UCC28516DWG4 UCC28516DWR UCC28516DWRG4 UCC28517DW Status (1) Package Type Package Drawing SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC PDIP PDIP SOIC SOIC SOIC SOIC SOIC DW N N DW DW DW DW N N DW DW DW DW N N DW DW DW DW DW Pins 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 Package Qty 2000 20 20 25 25 2000 2000 20 20 25 25 2000 2000 20 20 25 25 2000 2000 25 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 .ti.

or 2) lead-based die adhesive used between the die and leadframe. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. OBSOLETE: TI has discontinued the production of the device. TI and TI suppliers consider certain information to be proprietary.1% by weight in homogeneous materials. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. -. and a lifetime-buy period is in effect. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances. TI Pb-Free products are suitable for use in specified lead-free processes. (2) Eco Plan .1% by weight in homogeneous material) (3) MSL. PREVIEW: Device has been announced but is not in production. and peak solder temperature. but TI does not recommend using this part in a new design. NRND: Not recommended for new designs. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.com 16-Mar-2011 Orderable Device UCC28517DWG4 UCC28517DWR UCC28517DWRG4 Status (1) Package Type Package Drawing SOIC SOIC SOIC DW DW DW Pins 20 20 20 Package Qty 25 2000 2000 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. and makes no representation or warranty as to the accuracy of such information. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible).The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0. Efforts are underway to better integrate information from third parties.PACKAGE OPTION ADDENDUM www. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. including the requirement that lead not exceed 0. Where designed to be soldered at high temperatures. LIFEBUY: TI has announced that the device will be discontinued. TBD: The Pb-Free/Green conversion plan has not been defined.The planned eco-friendly classification: Pb-Free (RoHS). and thus CAS numbers and other limited information may not be available for release. or Green (RoHS & no Sb/Br) . Device is in production to support existing customers. Samples may or may not be available.com/productcontent for the latest availability information and additional product content details. Addendum-Page 3 .please check http://www. TI bases its knowledge and belief on information provided by third parties.ti.ti. Pb-Free (RoHS Exempt). Peak Temp.

0 24.4 24.4 24.0 24.0 330.0 K0 (mm) 2.4 24.8 10.PACKAGE MATERIALS INFORMATION www.4 24.7 2.0 12.0 12.0 W Pin1 (mm) Quadrant 24.0 13.0 24.0 24.7 2.0 24.0 12.0 12.0 12.0 330.0 330.0 13.8 10.com 23-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOIC SOIC SOIC SOIC SOIC SOIC SOIC DW DW DW DW DW DW DW 20 20 20 20 20 20 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.4 10.7 2.8 10.0 330.0 13.8 10.8 10.8 B0 (mm) 13.0 13.4 24.8 10.4 24.7 2.0 13.0 24.7 2.0 330.0 24.0 330.0 12.ti.7 P1 (mm) 12.0 Q1 Q1 Q1 Q1 Q1 Q1 Q1 UCC28511DWR UCC28512DWR UCC28513DWR UCC28514DWR UCC28515DWR UCC28516DWR UCC28517DWR 2000 2000 2000 2000 2000 2000 2000 Pack Materials-Page 1 .0 13.7 2.

PACKAGE MATERIALS INFORMATION www.0 346.0 346.0 41.0 346.0 346.0 346.0 Height (mm) 41.0 346.0 346.0 346.0 346.0 41.ti.0 41.0 Width (mm) 346.0 41.0 346.0 Pack Materials-Page 2 .0 346.0 41.0 346.com 23-Jul-2010 *All dimensions are nominal Device UCC28511DWR UCC28512DWR UCC28513DWR UCC28514DWR UCC28515DWR UCC28516DWR UCC28517DWR Package Type SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing DW DW DW DW DW DW DW Pins 20 20 20 20 20 20 20 SPQ 2000 2000 2000 2000 2000 2000 2000 Length (mm) 346.0 41.

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