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ORGANIC TRANSISTORS
—
METHODIK ZUR SCHALTUNGSANALYSE FÜR
ORGANISCHE TRANSISTOREN
Der Technischen Fakultät der
Universität ErlangenNürnberg
zur Erlangung des Grades
DOKTOR – INGENIEUR
vorgelegt von
Jürgen Krumm
Erlangen – 2008
Als Dissertation genehmigt von
der Technischen Fakultät der
Universität ErlangenNürnberg
Tag der Einreichung: 26.11.2007
Tag der Promotion: 03.03.2008
Dekan: Prof. Dr.Ing. habil. J. Huber
Berichterstatter: Prof. Dr.Ing. W. H. Glauert
Prof. Dr.Ing. habil. R. Weigel
I
Danksagung
Diese Arbeit entstand als Ergebnis meiner wissenschaftlichen Tätigkeit am Lehrstuhl für
Rechnergestützten Schaltungsentwurf der FriedrichAlexanderUniversität ErlangenNürnberg.
Ich bedanke mich bei Herrn Prof. Dr.Ing. Wolfram H. Glauert für die hervorragende Be
treuung und Begutachtung dieser Arbeit. Für die freundliche Übernahme des Zweitgutachtens
danke ich Herrn Prof. Dr.Ing. Dr.Ing. habil. Robert Weigel. Bei den folgenden Personen
bedanke ich mich für die vielen fachlichen Diskussionen bzw. für das Korrekturlesen von
Kapiteln meiner Arbeit: Ahmed Amar, Dr. Robert Blache, Dr.Ing. Markus Böhm, Dr. Hen
ning Rost, Katharina Schätzler, Wolfgang Schirmer und Dr. Dietmar Zipperer. Ferner gilt
mein Dank den Lehrstuhlkollegen Elke Eckert, Wolfgang Magerl und Klaus Schneider, mit
denen ich an verschiedenen Projekten aus der Polymerelektronik arbeiten durfte. Besonders
bedanken möchte ich mich auch bei meinen Zimmerkollegen Thomas Bürner, Werner Haas
und Reinhard Hofmann für das nette Arbeitsumfeld. Für die organisatorische Hilfe im Vor
feld und während der Promotionsprüfung bedanke ich mich bei Frau Roswitha Rauch, der
Sekretärin des Lehrstuhls.
Schließlich danke ich meiner Familie für ihre Unterstützung.
Erlangen, Mai 2008
Jürgen Krumm
II
Contents III
Contents
1 Introduction 1
1.1 Circuit Simulation in the Optimization of OFETs . . . . . . . . . . . . . . . 2
1.2 Aim of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Scientiﬁc Contribution of this Work . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Outline of this Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Concepts of LowCost Organic Electronics 7
2.1 State of the Art in Organic Circuits . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Organic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Oligomers and Polymers . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Unipolar and Ambipolar Semiconductors . . . . . . . . . . . . . . . 9
2.2.3 Charge Transport Models . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Organic FieldEffect Transistors . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.1 Device Characteristics of an OFET . . . . . . . . . . . . . . . . . . 11
2.3.2 Differences between MOSFET and OFET . . . . . . . . . . . . . . . 13
2.4 Printing and RolltoRoll Fabrication . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Chapter Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 OFET Modeling for Circuit Simulation 19
3.1 Model Requirements for Circuit Simulation . . . . . . . . . . . . . . . . . . 19
3.2 Existing Models for OFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 ShichmanHodges Model (Level1 Model) . . . . . . . . . . . . . . 22
3.2.2 Model for Polycrystalline TFTs . . . . . . . . . . . . . . . . . . . . 27
3.2.3 Model for Amorphous TFTs . . . . . . . . . . . . . . . . . . . . . . 32
3.2.4 Analytic VRH Models . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.5 General Tablebased Models . . . . . . . . . . . . . . . . . . . . . . 43
3.2.6 Dresden Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.7 Modeling of Complementary OFETs . . . . . . . . . . . . . . . . . 46
3.2.8 Modeling of Ambipolar OFETs . . . . . . . . . . . . . . . . . . . . 48
IV Contents
3.3 Popular Procedures for Parameter Extraction . . . . . . . . . . . . . . . . . . 50
3.3.1 Procedures for the Level1 Model . . . . . . . . . . . . . . . . . . . 50
3.3.2 Extraction Procedures for TFT Models . . . . . . . . . . . . . . . . 59
3.3.3 Parameter Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4 Automation of Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.1 Existing Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 V
Sat
Method 69
4.1 Extraction based on V
Sat
Method . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 Modeling based on V
Sat
Method . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.1 V
Sat
Type TableBased Model . . . . . . . . . . . . . . . . . . . . . 73
4.2.2 Linvar Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3 Experimental Results on Transistor Fitting . . . . . . . . . . . . . . . . . . . 76
4.3.1 Analysis of a Level1 Transistor . . . . . . . . . . . . . . . . . . . . 76
4.3.2 Analysis of Model for Polycrystalline TFTs . . . . . . . . . . . . . . 77
4.3.3 Effect of Contact Resistance on Level1 Model . . . . . . . . . . . . 81
4.3.4 Compensation of Contact Resistance . . . . . . . . . . . . . . . . . . 82
4.3.5 Analysis of a PDHTT Transistor . . . . . . . . . . . . . . . . . . . . 87
4.3.6 Modeling of a P3HT Transistor . . . . . . . . . . . . . . . . . . . . 87
4.3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5 Analysis of OFETBased Logic Circuits 93
5.1 Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.1 Basic Circuit Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.1.2 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.2 Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.3 Characterization of Robustness . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.1 Method of Equilibrium Zones . . . . . . . . . . . . . . . . . . . . . 99
5.3.2 Concept of Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.3 Unity Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.3.4 Method of Maximum Squares . . . . . . . . . . . . . . . . . . . . . 106
5.3.5 VTC Gain Considerations . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.6 Discussion of Characterization Methods . . . . . . . . . . . . . . . . 110
5.4 Timing Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.5 Automation of Circuit Characterization . . . . . . . . . . . . . . . . . . . . 115
Contents V
5.5.1 Tools for Characterization of Logic Circuits . . . . . . . . . . . . . . 115
5.5.2 General Characterization Tools . . . . . . . . . . . . . . . . . . . . . 116
5.5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6 Analysis Concept 121
6.1 Typical Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2 Novel Analysis Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.2.1 Data Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2.2 Modeling System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.3 Analysis Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.2.4 Simulator Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3 Analysis Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.1 Analysis of an Inverter in CurrentSource Conﬁguration . . . . . . . 136
6.3.2 Analysis of NORGates in CurrentSource Conﬁguration . . . . . . . 143
6.3.3 Analysis of Parameterdependent Gate Behavior . . . . . . . . . . . 146
6.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7 Summary and Further Work 151
7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.2 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
A List of Symbols 155
B List of Acronyms 161
C Glossary 163
D Symbols and Truth Tables for Logic Circuits 167
E Simulation Software 169
Bibliography 170
VI
VII
Abstract
In this work, a novel computeraided methodology for the analysis of the performance of
organic transistors (OFETs) in logic circuits is described. The basic idea of the concept is to
provide an integrated environment which includes data management, modeling of transistors,
and the automatic analysis of organic circuits. Existing OFET models as well as procedures
and software tools for extracting their model parameters are analyzed. A novel formalism
which compares the quality of models is deﬁned using a model quality chart. Furthermore, a
novel method of extracting basic model parameters in dependence on the gatesource voltage
is detailed. It aids in visualizing which type of model best maps a given transistor. Two
transistor models are presented: a tablebased model and an analytical model. Procedures for
characterizing static and dynamic behavior of basic logic circuits are discussed as well as tools
for deriving appropriate performance ﬁgures. Novel methods of extracting the robustness
of logic gates are presented. Several examples demonstrate the application of the analysis
methodology to organic logic circuits and OFET modeling issues, respectively.
Kurzfassung
In dieser Arbeit wird eine neue, Computergestützte Methodik zur Performanceanalyse von
organischen Transistoren (OFETs) in Logikschaltungen beschrieben. Das Konzept basiert
auf der Grundidee, eine integrierte Umgebung für die Datenverwaltung, die Modellierung
von Transistoren und die automatische Analyse organischer Schaltungen bereitzustellen. Ex
istierende OFETModelle sowie Prozeduren und SoftwareWerkzeuge zur Extraktion der zuge
hörigen Modellparameter werden untersucht. Ein neuer Formalismus, um die Qualität einzel
ner Modelle mit Hilfe einer Qualitätscheckliste zu vergleichen, wird deﬁniert. Ein neues Ver
fahren zur Extraktion grundlegender Modellparameter in Abhängigkeit von der GateSource
Spannung wird beschrieben. Das Verfahren visualisiert, durch welchen Modelltyp ein ge
gebener Transistor am besten abgebildet werden kann. Zwei Transistormodelle werden vorge
stellt: ein Tabellenmodell und ein analytisches Modell. Verfahren und SoftwareWerkzeuge,
um das statische und dynamische Verhalten grundlegender Logikschaltungen zu charakter
isieren und zugehörige Kennzahlen zu ermitteln, werden diskutiert. Neue Methoden zur Bes
timmung der Gatterrobustheit werden vorgestellt. Mehrere Beispiele zeigen die Anwendung
der Analysemethodik bei organischen Logikschaltungen bzw. bei Fragestellungen der OFET
Modellierung.
VIII
1
Chapter 1
Introduction
The ﬁeld of lowcost organic electronics is a relatively new topic of research in the domain
of semiconductor technology. Activities started in the 1980s by demonstrating organic ﬁeld
effect transistors (OFETs) which make use of special organic compounds for the semiconduct
ing channel instead of crystalline silicon. These OFETs cannot compete with siliconbased
transistors regarding switching speed or packing density but provide prospects of consider
ably reducing fabrication costs, largearea manufacturing (i.e. direct application of electronic
structures onto large substrates), or implementing mechanically ﬂexible integrated circuits.
These advantages generate applications of OFETs where fabrication costs or ﬂexibility are
more important than e.g. switching speed of the transistors. One example is the implemen
tation of extremely lowcost radiofrequency identiﬁcation (RFID) tags. Fabrication costs
below one Cent would e.g. boost application of RFID devices as price tags in supermarkets.
Owing to their complex fabrication, siliconbased RFID tags cannot reach this price target.
Currently, lowcost organic electronics is in the early stages of development and optimiza
tion of devices and processes. Various materials and fabrication processes are continuously
tested and optimized. Circuit simulation is an important part in this process as it provides
insight into the performance potential of existing or hypothetical OFET generations in OFET
based circuits. In the course of circuit simulation, devices are modeled and the electrical
performance of typical application circuits is analyzed. Employing circuit simulation in the
process of optimizing devices consists of numerous iterations of modeling devices, simulating
application circuits, and extracting performance ﬁgures from simulation results. Therefore,
efﬁcient methods of modeling OFET devices and analyzing OFETbased circuits by use of
circuit simulation are needed in order to automate the analysis process as much as possible.
This thesis describes a methodology for efﬁcient modeling of OFETs and analysis of
OFETbased logic circuits. The basic idea is to provide a uniform analysis environment which
seamlessly integrates transistor modeling, circuit analysis of OFETbased circuits, and neces
sary data management.
2 Chapter 1. Introduction
1.1 Circuit Simulation in the Optimization of OFETs
Fig. 1.1 shows where circuit simulation can be used in the evaluation of an OFET process.
The ﬂow consists of manufacturing OFETs, characterizing their electrical performance or
longterm stability, and subsequently improving the process, which leads to new iterations of
the procedure.
Circuit Simulation
leads to
includes
includes
Models
Benchmark
Testbenches
improvements
Process
fabrication
Device
characterization
Device
analysis
Performance
circuits
extraction
Parameter
OFET
Testbench
Circuit
Reporting
modeling
generation
characterization
Fig. 1.1: Generic analysis ﬂow showing the evaluation of the electrical performance of novel
OFET technologies by use of circuit simulation.
In the depicted ﬂow, device characterization and performance analysis include circuit sim
ulation (shaded box in the ﬁgure) where device parameters like threshold voltage or charge
carrier mobility are extracted. From these parameters, simulation models are generated for
the OFET devices. Depending on the fabrication technology, different transistor models are
needed. Devices fabricated in a certain layer setup (bottom gate / bottom contact structure
[2, 3], see Section 2.3.1) e.g. display substantial contact resistance between the electrodes
and the channel. Models and their parameters are used in the analysis of benchmark circuits.
The term benchmark circuit refers to the fact that these circuits are used for the evaluating
and comparing different device generations. Benchmarking should be carried out with typical
application circuits like OFETbased logic circuits. Analysis of benchmark circuits requires
suitable testbenches. A testbench is a circuit setup containing the benchmark circuits and ad
1.1. Circuit Simulation in the Optimization of OFETs 3
ditional circuitry used for extracting performance ﬁgures. Performance ﬁgures related to logic
circuits are e.g. robustness of the desired logic function against interfering noise at the inputs
and outputs of the gates, circuit speed, power consumption, etc. These performance ﬁgures
can be established using a technique called circuit characterization or cell characterization.
Circuit characterization provides information on the electrical properties of the circuits un
der consideration like input capacitances, timing data, or power consumption at reasonable
operating conditions.
The performance ﬁgures of the analyzed circuits can be compared with data derived by
analyzing earlier device generations. This approach is helpful when measuring the improve
ments between different device generations but is also useful in selecting the most efﬁcient
solution from a list of possible circuit concepts for a given process.
Traditional software tools from the domain of electronic design automation (EDA) easily
cover the circuit simulation tasks depicted in Fig. 1.1. Several problems arise when working
with standard software:
2 Existing software for model extraction is currently not well adapted to OFET devices.
OFETbased transistor models are missing and would have to be included into the ex
tractors.
2 Tools for circuit characterization are normally adapted to highspeed stateoftheart
circuits. They do not include simple analyses like the determination of the maximum
square noise margin (see Section 5.3.4). Including new analyses into existing tools is
often difﬁcult as the source code of the programs is not disclosed or would have to be
reworked.
2 Collaboration between different tools is necessary. Data from the model extractor would
have to be transferred to the testbenches used by the characterization tool and charac
terization results would have to be displayed and archived for documentation and later
reuse.
2 Data organization is up to the user. The optimization of OFET devices and organic logic
gates leads to many iterations of measurement, model extraction, and circuit analysis.
The respective data have to be stored in an efﬁcient way. Prior analysis results must
be accessible later on in order to explore the effects of optimization steps in the fab
rication process. Moreover, analysis procedures might change because new ﬁgures of
merit are introduced. In such a case, prior analyses need to be repeated with the new
characterization ﬂow.
2 The characterization ﬂow depends on the different tools used in the analysis process.
These tools are coordinated by control scripts. As soon as vendors change their tools
4 Chapter 1. Introduction
the characterization ﬂow has to be updated, including the control scripts. Moreover,
migration to other tools would also require recoding of scripts. Additionally, the users
need to understand the inner workings of the tools in order to include them in their
analysis ﬂow.
Therefore, it is desirable to integrate the required tools into a coherent, generic, and ﬂex
ible framework. Coherent means that the framework seamlessly integrates the different tools
and also covers data management. Generic means that the tools are integrated using abstract
interfaces so that they can easily be replaced. Novel tools can then be integrated by including
appropriate interfaces. Flexible means that the users can add novel characterization scripts by
use of easily adaptable interfaces.
1.2 Aim of this Thesis
In this thesis, a computeraided methodology for modeling of OFETs and analyzing their
performance in logic circuits is presented. Development of the methodology leads to research
in the following domains:
2 Modeling: Examination of OFET models suitable in circuit simulation and of proce
dures for extracting their parameters.
2 Circuit characterization: Deﬁnition of characterization criteria for circuits. In this work,
lowcomplexity logic circuits are in focus.
2 Analysis concept: Development of an analysis ﬂow for carrying out parameter extrac
tion for OFET models and logic gate characterization as well as data management.
1.3 Scientiﬁc Contribution of this Work
Progress in the simulationbased modeling and circuit analysis of organic transistors could be
made in this work. First, a checklist to assess the quality of a modeling approach for OFET
devices in logic circuits has been deﬁned in the model quality chart (MQC). The MQC allows
its users to compare different modeling approaches. Formalisms like the MQC did not exist
before in the domain of organic electronics.
Second, a novel methodology for extracting device parameters in a twostep approach has
been developed. In a ﬁrst step, the transistor characteristics draincurrent (I
D
) vs. drainsource
voltage (V
DS
) are inspected. For each I
D
curve, the transition point V
Sat
between linear and
saturation region is extracted using a onedimensional search. V
Sat
and the measurement data
are then used for calculating three basic transistor parameters: threshold voltage V
T
, process
1.4. Outline of this Work 5
conductance K
P
, and channellength modulation λ. The gatevoltage dependent shapes of
these parameters extracted for a series of I
D
curves are characteristic for different model types.
Therefore, they can be used for identifying the model which maps best the measured curves.
This approach contrasts with other analysis procedures which concentrate on the problem
which set of parameters maps best the measured curves for a given model. In a second step,
the extracted V
GS
dependent parameters can be mapped to simulation models, e.g. the ones
developed in this work: a tablebased model and a ﬁttingbased analytic model.
Third, progress has been made in the analysis of OFETbased logic gates. A novel ap
proach has been introduced to deﬁne the robustness of logic gates by inspecting the gain of
the ﬁx point in the voltagetransfer characteristic. An existing method to qualitatively deﬁne
the compatibility of valid logic level ranges has been extended to yield noise margins.
A computeraided methodology has been developed to run data storage, OFET model
ing, automatic testbench generation, and circuit characterization within a single environment.
The novelty of the concept is the integration of these tasks by use of appropriate data struc
tures. Moreover, a graphical scripting system has been integrated into the concept so to allow
nonexpert users to ﬂexibly compose their own characterization schemes. Existing tools and
analysis methods have been adapted to the analysis of OFETbased logic circuits.
1.4 Outline of this Work
In Chapter 2, the basics of lowcost organic electronics are sketched with focus on OFETs
and OFETbased logic circuits. Chapter 3 deals with the modeling of OFETs. Here, general
requirements on transistor models are described and existing models for organic transistors are
discussed. Moreover, existing procedures and tools for modeling of transistors are reviewed.
A novel methodology for translating measured transistor characteristics into model parameters
and two new transistor models based on this methodology are detailed in Chapter 4. Here,
selected analysis examples are presented where the methodology is applied. Next, OFET
based logic circuits and the way how to characterize their static and dynamic behavior are
discussed in Chapter 5. Existing tools for circuit characterization are presented. A novel
analysis concept is then detailed in the ﬁrst part of Chapter 6. This concept implements
a computeraided methodology for modeling of OFETs and analysis of OFETbased logic
circuits. In the second part of the chapter, sample sessions demonstrate the application of the
analysis concept in a prototype implementation. Chapter 7 concludes the work by presenting
a summary of the work and an outlook to further developments.
6 Chapter 1. Introduction
7
Chapter 2
Concepts of LowCost Organic
Electronics
In recent years, electronic devices based on organic materials have appeared in real appli
cations. Displays composed of organic light emitting diodes (OLEDs) provide images with
increased brilliance when compared to more traditional display technologies. Small OLED
based displays have already been commercially introduced. In organic photovoltaics, solar
cells are developed where organic semiconductors are used as the active layer. Moreover,
organic materials are considered for use in nonvolatile memories. Another important focus
are integrated circuits (ICs) based on OFETs, which are currently in the development stage.
In the following, the concepts of organic electronics will be brieﬂy introduced. More detailed
descriptions can be found in the references provided in the respective paragraphs. The dis
cussion will focus on items relevant for lowcost organic transistors (OFETs), which are the
basic building blocks of organic integrated circuits.
2.1 State of the Art in Organic Circuits
The major advantage of organic electronics is ease of fabrication instead of improved electrical
performance of a device. A large number of organic materials can be deposited from solution,
enabling e.g. application of highspeed and highthroughput printing methods. With increased
fabrication speed and output, lower fabrication costs are possible.
Organic ICs e.g. target smart price tags (also called RFID tags or transponders) as applica
tion. These transponders can be electronically interrogated using a reader and radio frequency
communication. The organic RFID transponders draw their energy from the RF ﬁeld of the
reader and consist of an antenna, organic rectiﬁers and an OFETbased logic block for trans
mitting their information to the reader.
8 Chapter 2. Concepts of LowCost Organic Electronics
Prototype RFID tags with organic logic chips have lately been presented [4, 5], partially
fabricated using cleanroom techniques. Yet, fullyprinted circuits currently lag behind these
complexities and performances. In the domain of lowcost mass printed circuits, stateof
theart results were obtained with gravure printed polyﬂuorene (F8T2) as semiconductor and
offset printed PEDOTPSS as sourcedrain material [6]. Measurement results of a sevenstage
ring oscillator
1
were presented with an oscillation frequency of 1.2 Hz at a supply voltage of
48 V. Details about the early stages of the underlying fabrication process were presented in
[7]. Another group [8] reported results for a printed sevenstage ring oscillator with polytri
arylamide (PTAA) as semiconductor. The oscillation frequency was 67 Hz at a supply voltage
of 30 V.
2.2 Organic Semiconductors
In the following, a brief introduction into organic semiconductors and popular models to de
scribe their chargetransport mechanisms is given.
2.2.1 Oligomers and Polymers
Organic semiconductors are the most important materials for the functional layer of organic
transistors used in organic electronics. They are molecules consisting of a repetition of carbon
based compounds with low molecular weight (called repetition units or monomers). Depend
ing on the number of repetition units n, organic semiconductors belong to one of two cate
gories: oligomers or polymers. An oligomer is a compound with n usually less than about 10
to 15. Most oligomers cannot be deposited from solution because they are not very soluble in
common solvents [9]. Instead, they are deposited e.g. by vacuum deposition. Semiconduct
ing oligomers show superior electrical performance (e.g. switching speed) when compared to
semiconducting polymers. Popular oligomers with semiconducting properties are e.g. pen
tacene or oligothiophenes. A polymer on the other hand is a compound with a higher number
of repetition units. More precisely, a polymer can be deﬁned as a compound where adding a
new repetition unit will not alter its chemical and electrical behavior [10]. In order to make
polymers soluble in a variety of solvents and provide ﬁlm forming properties, side chains are
chemically attached to the polymer chain so to allow deposition e.g. by printing methods. A
popular organic semiconductor is the ptype semiconducting polymer poly(3hexylthiophene)
or P3HT in short. The basic building block of P3HT is thiophene, a ring of four carbon atoms
and one sulfur atom. A hexyl (C
6
H
13
) side chain is added to the thiophene ring in order to
1
An oscillator circuit where seven inverters are cascaded and the output of the last inverter is fed back to the
input of the ﬁrst inverter.
2.2. Organic Semiconductors 9
allow P3HT to be soluble in organic solvents. Fig. 2.1 shows the chemical structure of P3HT.
In the ﬁgure, n denotes the number of repetition units.
) (
S
S
C
6
H
13
C
6
H
13
n
Fig. 2.1: Chemical structure of poly(3hexylthiophene).
Semiconducting polymers have a conjugated polymer backbone, i.e. an alternating se
quence of single and double carboncarbon bonds. Conjugation leads to the presence of delo
calized molecular orbitals in the material where electrons belong to a group of atoms instead
of a single bond or atom [11]. These electrons are important for charge transport.
2.2.2 Unipolar and Ambipolar Semiconductors
The majority of organic semiconductors displays unipolar ptype transport, i.e. hole trans
port. There also exist unipolar ntype transport materials which show electrical performance
and lower stability under normal environmental conditions, however. Recently, ambipolar
semiconductors (e.g. [12, 13]) have been reported where both ntype and ptype charge trans
port is possible. These materials are nevertheless in the early stages of research. They are
either intrinsically ambipolar or consist of mixtures of ptype and ntype conducting semicon
ductors.
2.2.3 Charge Transport Models
Numerous models have been developed to deal with the mechanisms of charge transport
within organic semiconductors. The most popular of these are listed in the following.
Band Transport
By combining atoms into molecules, molecular orbitals are created. The highest molecular
orbital ﬁlled with electrons is denoted as HOMO (highest occupied molecular orbital) and the
lowest molecular orbital devoid of electrons as LUMO (lowest unoccupied molecular orbital).
HOMO and LUMO in organic semiconductors are used analogous to the opposing edges of
the valence and conduction bands in more traditional semiconductors. They are separated by
an energy gap.
10 Chapter 2. Concepts of LowCost Organic Electronics
Generally, the electronic properties of a semiconductor are strongly inﬂuenced by the
positions and distances of the opposing edges of the valence and conduction band. Charge
transport of holes in the valence band and of electrons in the conduction band is limited by
scattering of the charge carriers at lattice vibrations or impurities. The mobility of charge
carriers decreases with elevated temperature because lattice vibrations are less pronounced at
lower temperatures.
Hopping Transport
Many organic semiconductors are regarded as disordered systems where band transport does
not seem reasonable between different molecules. Here, hopping transport provides a better
description of charge transport. In this model, free movement of charge carriers is not possible.
Instead, they hop between neighboring hopping sites. When a charge carrier hops to another
site, its presence there leads to a local deformation of the polymer. The pair of charge carrier
and deformation is called polaron and is modeled as a single quasiparticle. In order to move
between sites, the polaron has to overcome an energy barrier. The probability of crossing this
energy barrier and hopping between sites increases with elevated temperatures.
Multiple Trapping and Release
In the model of multiple trapping and release (MTR), charge carriers are assumed to travel by
band transport. This transport is impeded by the presence of traps near the band edges. These
traps are energy levels within the bandgap which are caused by the presence of impurities or
structural defects [14]. When a charge carrier “falls” into such a trap, it is not available for
charge transport until it gets released again after a certain amount of time, e.g. by thermal
activation. The trapping time depends on the temperature and the energetic depth of the trap.
Grain Boundary Model
In polycrystalline organic semiconductors, the semiconductor ﬁlm is composed of crystallites
which are separated by amorphous grain boundaries. While the charge carriers are assumed
to move freely in bands in the crystallites, they get trapped and released at traps in the grain
boundaries. These traps are due to the structural disorder at the interfaces of neighboring
grains. The traps in the grain boundaries get charged by capturing charge carriers. This
trapping creates a depletion region which in turn leads to the formation of an energy barrier.
Charge carriers have to overcome this energy barrier in order to travel across the depletion
region. The grain boundary model can be assumed as a special variation of MTR where traps
concentrate at the grain boundaries.
2.3. Organic FieldEffect Transistors 11
2.3 Organic FieldEffect Transistors
Organic semiconductors ﬁnd application in organic ﬁeldeffect transistors. OFETs have many
similarities with more traditional MOSFETs but also considerably differ from these. In the
following, the basic properties of OFETs and their differences to MOSFETs are brieﬂy dis
cussed.
2.3.1 Device Characteristics of an OFET
In Fig. 2.2, circuit symbol as well as output characteristics I
D
vs. V
DS
and transfer charac
teristics I
D
vs. V
GS
of an OFET are sketched. For the output characteristics, V
DS
is swept
in the range of interest at constant V
GS
values. The transfer characteristics are obtained by
applying a ﬁxed V
DS
and sweeping V
GS
in the range of interest.
The schematic plots show the behavior of an ntype (electron transport) OFET with pos
itive voltages. Ptype (hole transport) FETs operate similarly with inverted voltages and cur
rents. The drain current is modulated by the voltage differences between the three device
electrodes drain (D), gate (G), and source (S). In principle, an OFET operates as a voltage
dependent resistor between drain and source which is controlled by the gatesource and drain
source voltage. In logic circuits, this resistor can be regarded as a nonlinear switching element
which cannot be completely switchedoff as shown by the logarithmic transfer characteristics
in Fig. 2.2c.
0
0
VDS
VDS
D
G
S
ID
VGS
VGS
ﬁxed VDS
VGS1
VGS2
VGS3
VGS4
b) a) c)
ID log ID
Fig. 2.2: a) FET symbol with terminal voltages and drain current, b) schematic output char
acteristics I
D
vs. V
DS
, and c) logarithmic transfer characteristics I
D
vs. V
GS
.
12 Chapter 2. Concepts of LowCost Organic Electronics
In OFETs, the drain current I
D
is usually proportional to certain material and structural
properties. These material properties are chargecarrier mobility µ or the relative permittivity
ε
r
of the insulator capacitance. Structural properties are channel width W, channel length
L, or the thickness of the insulating layer t
is
. Using these parameters, I
D
(here again dis
cussed for an ntype device) can be approximated by the wellknown ShichmanHodges [15]
equations
I
D
=
W
L
µC
is
(V
GS
−V
T
)V
DS
−
1
2
V
2
DS
: V
DS
< V
GS
−V
T
1
2
W
L
µC
is
(V
GS
−V
T
)
2
: V
DS
> V
GS
−V
T
(2.1)
The voltages V
DS
and V
GS
are deﬁned according to Fig. 2.2. V
T
is the threshold voltage.
It can roughly be deﬁned as the voltage at which the channel begins to switch on. C
is
is the
capacitance per unit area of the insulator and reads C
is
= ε
0
ε
r
/t
is
. I
D
saturates at high V
DS
values (V
DS
 ≥ V
GS
− V
T
) because the voltage drop across the channel no longer leads to
accumulation of charge carriers. In a ﬁrstorder approximation, the channel region there is
regarded as being pinchedoff. Consequently, the drain current saturates.
OFETs belong to the class of thinﬁlm transistors where the semiconducting channel is
deposited as a thin ﬁlm on the substrate. Owing to this fact, OFETs are also referred to as
OTFTs (Organic ThinFilm Transistors, e.g. [9]). Fig. 2.3 shows a graphical representation of
frequently used OFET structures. These structures are distinguished according to the positions
of the electrodes. In topgate structures, the gate electrode is deposited on top of all other
layers. In bottomgate structures, conversely, it is deposited ﬁrst on the substrate. Each device
setup has special requirements on the compatibility between the different materials used in
the fabrication process (layer materials, solvents, resists, developers).
Topgate devices provide the advantage of encapsulating the semiconducting layer be
tween the substrate and the insulator. Bottomgate devices are often fabricated using the
wellestablished technology of silicon wafers. Silicon is used for the gate electrode while
silicon dioxide grown on top of the silicon acts as the insulating layer [16].
Chargecarrier mobilities of amorphous organic transistors are usually very low, i.e. in
the range µ < 0.1 cm
2
/Vs [17] as opposed to crystalline silicon transistors with electron mo
bilities µ > 500 cm
2
/Vs. This restriction leads to OFETs with large channel widths in the
millimeter range so to allow drain currents of 1 µA and above. Therefore, OFETs are often
realized as interdigitated structures. Fig. 2.4 shows an OFET (topgate structure) with ﬁve ﬁn
gers in top view. The geometrical device parameters (channel length and width) are indicated
in the drawing.
Parameters for fullyprinted as well as cleanroomfabricated devices are given in Table 2.1.
For the printed devices, the semiconductor was PTAA while the cleanroom fabricated devices
2.3. Organic FieldEffect Transistors 13
Semiconductor
Drain Source
Insulator
Substrate
Gate
Semiconductor
Insulator
Gate
Substrate
Drain Source
Gate
Source Drain
Insulator
Substrate
Semicon.
b) Bottom–gate bottom–contact c) Bottom–gate top–contact a) Top–gate
Fig. 2.3: Schematic view of different OFET classes: a) topgate structure, b) bottomgate
bottomcontact structure, and c) bottomgate topcontact structure.
Gate
Source
Drain
Channel width W
Channel length L
Fig. 2.4: Schematic top view of an OFET with an interdigitated ﬁnger structure.
was manufactured using P3HT. As can be seen from the listed data, considerable differences
between the two processes exist.
Table 2.1: Parameters for fullyprinted [18] and cleanroom fabricated [19] OFETs.
Parameter fullyprinted cleanroom fabricated
relative insulator permittivity ε
r
2.2 to 50 3
insulator thickness t
is
0.110 µm, depends on ε
r
300 nm
electrode thickness > 300 nm 40 nm
semiconductor thickness > 500 nm 50 nm
2.3.2 Differences between MOSFET and OFET
In the following, the operation modes of MOSFETs and OFETs will be compared. First, the
wellknown MOSFET is shortly presented and is then compared with an OFET in order to
show the differences between the two transistor types. Ptype transistors will be used in the
discussion.
14 Chapter 2. Concepts of LowCost Organic Electronics
MOSFET Operation
In ptype MOSFET devices, the channel region is a substrate with ntype doping, i.e. with
electrons as majority carriers (see Fig. 2.5). An oxide is grown on top of the channel region
and serves as the insulator. The drain and source region are both ptype doped with holes as
majority carriers. Therefore, there exist pn junctions at the interface between the electrodes
and the channel when zero voltages are applied at drain, gate, and source. By applying a
negative voltage between gate and source, the channel is depleted. When V
GS
reaches the
threshold voltage V
T
, the concentration of minority carriers (holes) begins to exceed the con
centration of majority carriers (electrons) and the device operates in inversion mode where
the channel region is ptype conducting. Under these conditions, the pn junctions between the
source electrode and the channel as well as the drain electrode and the channel no longer exist
and current can ﬂow between drain and source through the channel. By applying a positive
V
GS
, majority carriers (electrons) are accumulated and the channel is switched off. No mat
ter which polarity V
DS
has, always one of the two pn diodes at source and drain is biased in
reverse direction and blocks current ﬂow.
Drain Source p+ p+
n−Substrate
Gate Oxide
Gate
Fig. 2.5: Schematic cross section of a ptype MOSFET (p+ and n+ denote heavily ptype and
heavily ntype doped regions).
OFET Operation
In a ptype OFET, the semiconducting channel is deposited as a thin ﬁlm on an insulating
substrate or the dielectric. The semiconductor is not doped but intrinsically provides hole
transport. Source and drain electrodes are metals or metallike conductors with (ideally) little
resistance to the channel region for transport of holes. By applying a negative V
GS
, holes
injected from the source electrode are accumulated in the channel. Conversely, a positive V
GS
depletes the channel and leads to higher channel resistance, which leads to low current.
2.4. Printing and RolltoRoll Fabrication 15
Comparison
Table 2.2 provides a comparison between siliconbased MOSFET and OFET technologies.
Table 2.2: Comparison between siliconbased MOSFET and OFET technologies.
Property MOSFET OFET
Operation mode strong inversion accumulation
Transport mechanism band transport various models, but still
under debate
Source/drain contacts pn junctions for majority
carriers, one of these is re
verse biased
lowresistance contacts for
majority carriers
Substrate provides channel region,
semiconducting
no electric function, insu
lating
Typical Chargecarrier
mobility
400 to 500 cm
2
/Vs for
electrons
≤ 0.1 cm
2
/Vs in amor
phous semiconductors
Fabrication method lithographic process, using
cleanroom facilities
various, from photolitho
graphy to printing
Semiconductor silicon various conjugated poly
mers/oligomers
Insulator mainly silicon dioxide numerous possibilities
Electrodes / Intercon
nect
various metals, polysilicon
(as gate)
various metals and organic
conductors
Critical dimension < 1 µm > 1 µm
2.4 Printing and RolltoRoll Fabrication
Based on the selection of constituent materials, OFETbased circuits can be fabricated in
a variety of deposition (e.g. vapor deposition, spincoating) and structuring methods (e.g.
photolithography, shadow masks). The reader is referred to [20, 21] for a review of fabrication
techniques used in organic electronics.
The most advantageous fabrication techniques are printing methods, which are not appli
cable in conventional siliconbased processes. Printing techniques like ﬂexography, gravure
printing, screen printing, or inkjet printing, etc. can be used. These lead to high fabrication
volume and throughput as well as lowcost fabrication, which are speciﬁc features of lowcost
organic electronics.
Use of printing techniques comes at the cost of some restrictions. The feature sizes are
currently limited to the micrometer range instead of a nanometer scale used with conventional
16 Chapter 2. Concepts of LowCost Organic Electronics
silicon transistors [18]. Printing materials have to be chosen carefully so to remain compatible
with the respective printing technology regarding e.g. viscosity, drying behavior, etc. [21, 22].
Some printing techniques can be used in rolltoroll manufacturing, where the printing
substrate is fed through a printing machine from one roller to another. In comparison to batch
processing of IC wafers, rolltoroll manufacturing can reach higher throughput. In order to
explain rolltoroll manufacturing, gravure printing will be discussed in the following with the
help of Fig. 2.6. In gravure printing, a ﬂexible foil is continuously unwound froma roll, travels
between a rotating gravure cylinder and an impression cylinder, and is ﬁnally rewound into
another roll. In the printing process, the surface of the rotating gravure cylinder is wetted by
an ink or soluble polymer in a tank. The ink (in organic electronics: semiconductor, insulator,
metallike electrode material, etc.) is scraped by a doctor blade so that only the quantity ﬁlling
up the recessed parts of the cylinder remains. This ink is transferred to the desired positions
of the printing substrate while the cylinder rolls across it.
Printing substrate
Gravure cylinder
Ink
Impression
cylinder
Roll
Roll
Doctor blade
Fig. 2.6: Schematic gravure printing process (adaption from [23]).
2.5. Chapter Conclusions 17
2.5 Chapter Conclusions
As was shown in Section 2.3.1, MOSFETs and OFETs operate similarly. From the modeling
point of view, the two types of transistors differ in operation mode (strong inversion vs. accu
mulation), transport mechanisms (band transport vs. various possibilities from band transport
to hopping), and technological choices (materials, fabrication methods). Yet, output and trans
fer characteristics are comparable. Therefore, MOSFETbased models of transistors are used
as ﬁrstorder approximations of OFETs in circuit simulation. Nevertheless, the OFET tech
nology features numerous fabrication methods and materials for the various transistor layers.
This situation creates many factors complicating modeling because different transport mech
anisms (bandlike, hopping) and effects at the interfaces between the semiconductor and the
electrodes (presence of contact effects) or between the semiconductor and the insulating layer
(presence of traps, hysteresis) might arise. Hence, a generic simulation environment needs to
adapt to different modeling approaches and procedures for parameter extraction.
18 Chapter 2. Concepts of LowCost Organic Electronics
19
Chapter 3
OFET Modeling for Circuit Simulation
Circuit simulations of lowcost organic circuits are useful in the development and optimization
of devices and processes. Simulations provide relevant performance ﬁgures during device
optimization. They can be used without fabricating and measuring real devices. However,
employing circuit simulation in this ﬁeld requires accurate OFET models.
This chapter discusses models suitable for circuit simulation as well as procedures and
tools for extracting the respective model parameters. First, requirements are deﬁned which
determine the strengths and weaknesses of transistor models. These requirements are useful
when comparing models and identifying their deﬁciencies. Next, existing OFET models pre
sented in literature on device modeling are discussed. Finally, frequently used procedures and
tools for the extraction of transistor parameters are reviewed.
3.1 Model Requirements for Circuit Simulation
Transistor models need some properties in order to be useful in the simulation of OFET
based logic circuits. Model performance in digital circuits usually depends on a small set
of parameters of the DC characteristics such as threshold voltage and drive current [24]. A
“good” agreement between I
D
V
DS
measurements and simulation is traditionally considered
to be enough [25]. The level of accuracy can be deﬁned by the meansquare error between
measurement and simulation [25, 26, 27]. However, users of transistor models prefer more
sophisticated rating criteria in order to identify the strengths and weaknesses of individual
models. Tsividis and Suyama [25] studied requirements on transistor models useful in the
simulation of circuits. Their research focused on model requirements for analog circuits but
the results can also be adapted to models for OFETbased digital circuits. In this work, the
idea of Tsividis and Suyama is adapted to the assessment of OFET devices. The adaption
consists of grouping the requirements into ﬁve sections, dropping criteria more important for
20 Chapter 3. OFET Modeling for Circuit Simulation
analog models, and adding new criteria dealing with the accuracy of predicted voltage levels,
noise margin, or stress effects. Good candidates for modeling OFET devices should comply
with as many requirements as possible of the following model quality chart (MQC):
2 Accuracy — A candidate model should give reasonably accurate results for
⊲ IV characteristics,
⊲ speed predictions for logic circuits,
⊲ propagation delays at the individual nodes within the circuit,
⊲ voltage levels and noise margin determinations,
⊲ a reasonable range of bias voltages and temperatures.
2 Capacitance Modeling — The model should include proper modeling of the transistor
capacitances like gatesource and gatedrain capacitances. The accurate simulation of
timedependent voltage levels and signal shapes depends on the correct modeling of
these capacitances.
2 Compactness — The model equations should depend on as few parameters as possible:
⊲ There should be a strong relationship between model parameters and parameters
reﬂecting device structure and fabrication processing (channel thickness, number
of trap states, etc.).
⊲ Such a model would be especially useful in statistical circuit analysis where effects
of variations in fabrication and parameter distribution are accounted for.
⊲ In order to be of service in statistical circuit analysis, empirical parameters without
physical meaning should be avoided.
⊲ The model accuracy should not depend on the geometrical dimensions of each
device, so one set of model parameters should be valid for all devices of the same
type and fabrication process.
2 Parameter Extraction — The process of parameter extraction must be easy and straight
forward:
⊲ The number of required test devices and measurement procedures for the parame
ter extraction should be kept as small as possible.
⊲ Ideally, model parameters are directly resolved using analytical reasoning without
much computational effort.
3.2. Existing Models for OFETs 21
⊲ Alternatively, if generalpurpose optimization techniques are used, they must not
fail due to numerical instabilities.
2 Stress Effects — The candidate model should implement hysteresis effects present in
OFET devices like the threshold voltage shift due to bias stress [3, 28, 29, 30].
Although OFETbased modeling does currently not meet all of the above requirements,
the MQC is a useful tool in the discussion of strengths and weaknesses of different model
ing approaches. Currently, the following issues prevent complete compliance with the MQC
criteria:
2 The physics of OFETs are not fully understood yet. Experiments presented in literature
are often carried out on devices fabricated on silicon wafers and by photolithographic
means. Such devices are not comparable to devices fabricated with lowcost manufac
turing techniques. For the latter, fabrication speed and cost are more important than
device quality and repeatability.
2 Devices consist of nonuniform and complicated materials. This contrasts modeling
of crystalline silicon transistors made of uniform and wellcharacterized materials [31].
Under these circumstances, deriving a small set of physicsrelated parameters is difﬁcult
and often leads to empirical modeling of the devices.
2 OFETs can be fabricated using a variety of device structures and fabrication processes.
This situation gives rise to many individual effects. One example of such effects is the
series resistance between the electrodes and the transistor channel. Depending on the
device structure, the series resistance inﬂuences the transistor current [28, 32]. A large
variety of candidate materials for the semiconductor, the dielectric, and the interconnect
lines also leads to additional variables in the modeling process.
3.2 Existing Models for OFETs
In the following, transistor models are presented which have already been applied to OFETs.
Some of these models were developed for more traditional semiconductor materials while
others are especially designed for speciﬁc types of OFETs. The following review makes
use of the model quality chart (MQC) in order to compare weaknesses and strengths of the
individual models. However, the reader should note that the models are difﬁcult to compare
regarding accuracy as they have been developed for different device setups, i.e. different
material combinations, device structures, and fabrication methods.
22 Chapter 3. OFET Modeling for Circuit Simulation
The models reviewed in the following sections can roughly be divided into different cate
gories. These categories are:
1. Models adapting wellknown approaches for silicon transistors based on the shapes
of the output characteristics or structural similarities (Level1 in Section 3.2.1, TFT
models in Section 3.2.2 and Section 3.2.3).
2. A model speciﬁcally developed for OFETs, i.e. the model of variable range hopping
(VRH) in four variants in Section 3.2.4.
3. Models sacriﬁcing any physical background (tablebased models in Section 3.2.5, Dres
den model in Section 3.2.6) but instead focusing on quick and accurate reproduction of
measured output characteristics.
4. Models for ambipolar OFETs in Section 3.2.8, which are combinations of other models.
A special situation arises from Necliudov’s [32] application of the TFT model for amor
phous silicon to OFETs (Section 3.2.3). Here, the generic adaption of a siliconbased model
is combined with OFETspeciﬁc contact effects. Brederlow and colleagues [33] developed a
similar approach but focused on a physicsrelated description of the contact effect and mod
eled the intrinsic transistor with standard MOSFET equations. In this work, the model in [33]
has nevertheless been listed in the section dealing with the TFT model for amorphous silicon
as the model description was too short for a thorough analysis within the framework of this
thesis.
3.2.1 ShichmanHodges Model (Level1 Model)
Apopular and simple transistor model was developed by Shichman &and Hodges in the 1960s
for the general class of IGFETs (insulated gate ﬁeldeffect transistors) [15]. In the following,
the name “Level1 model” will also be used for this approach. The name originates from
SPICE, where ShichmanHodges modeling is selected for MOSFETs by setting the transistor
parameter LEVEL=1 [34].
Some researchers employ the Level1 equations as a ﬁrstorder approximation of the out
put characteristics of OFETs (e.g. [3, 35]). The equations are also used in Section 2.3.1 for a
discussion of the electrical behavior of OFETs.
Although the Level1 model has been developed with operation in strong inversion mode
in mind, the resulting currentvoltage relationship also approximates thinﬁlm transistors op
erating in accumulation mode as has been shown in [36].
3.2. Existing Models for OFETs 23
3.2.1.1 Model Equations
Fig. 3.1a shows the output characteristics of an OFET, which can be divided into three regions:
cutoff (not visible in the plot), linear, and saturation. In the following text, equations for the
three regions will be presented by use of an ntype transistor but the resulting equations are
applicable to both ntype and ptype devices.
For an ntype transistor with true Level1 behavior, no current ﬂows for V
GS
less than the
threshold voltage V
T
. The device is then in the cutoff region (see Fig. 3.1b). Above threshold,
the current increases with a squarelaw dependence on V
DS
in the linear region until it reaches
the boundary between linear and saturation region (shown by the dotted line in Fig. 3.1a). In
the saturation region, the current is proportional to the drainsource voltage.
a) Output characteristics b) Transfer characteristics
Linear Region Saturation Region
Cutoff
Region Region
Saturation
Region
Linear
0
0
V
DS
= V
GS
−V
T
V
GS
↑
V
T
I
D I
D
V
DS
V
GS
V
DS
= const
Fig. 3.1: Schematic output characteristics of a transistor with Level1 behavior: a) output
characteristics I
D
vs. V
DS
with linear and saturation region separated by a dotted curve, and
b) linear transfer characteristic I
D
vs. V
GS
with threshold voltage V
T
.
The equations of Level1 transistors were already introduced in (2.1) but will be repro
duced here in order to separate the different operation regions:
1. Cutoff region:
I
D
= 0 with V
GS
< V
T
(3.1)
2. Linear region:
I
D
= µ·C
is
·
W
L
V
GS
−V
T
−
V
DS
2
V
DS
·(1+λV
DS
) with 0 < V
DS
< V
GS
−V
T
(3.2)
24 Chapter 3. OFET Modeling for Circuit Simulation
3. Saturation region:
I
D
=
1
2
µ · C
is
·
W
L
(V
GS
−V
T
)
2
· (1 +λV
DS
) with 0 < V
GS
−V
T
< V
DS
(3.3)
The parameters used in (3.1) to (3.3) are µ for the chargecarrier mobility, C
is
for the
capacitance per unit area of the gate dielectric, V
T
for the threshold voltage, λ for the channel
length modulation parameter, W and L for the width and length of the transistor channel. For
convenience reasons in hand calculations, the process conductance parameter K
P
[37] was
introduced as
K
P
= µC
is
. (3.4)
The device conductance parameter β further extends K
P
by taking into account the geometry
of the transistor. It is deﬁned as
β = K
P
W
L
= µC
is
W
L
. (3.5)
The process conductance parameter K
P
reﬂects the driving capabilities of the transistor
device. The threshold voltage on the other hand deﬁnes how much gatesource voltage is
needed to induce charge carriers in the transistor channel. The channellength modulation
parameter has been introduced in the original IGFET equations to account for a channel
length reduction in saturation. This reduction is associated with the pinchoff of the transistor
channel at some point near the drain electrode. The pinchoff leads to a reduction of the
effective channel length which in turn increases the slope of I
D
vs. V
DS
in the saturation
region. The value of λ deﬁnes this slope according to (3.3). λ = 0 corresponds to a slope of
zero in the saturation region.
Reasonable parameter values for Level1 devices are given in Table 3.1. As there is not just
one mainstream OFET technology but many different processes currently in the development
stage, parameter values for the various fabrication technologies considerably differ. Therefore,
it is not possible to provide typical values, and Table 3.1 can only provide a general idea of
reasonable parameter ranges.
Table 3.1: Level1 parameters for ptype P3HT device [19].
Parameter Value
process conductance K
P
< 9 pA/V
2
threshold voltage V
T
0,2 V
channellength modulation λ 5 · 10
−3
1/V
The inﬂuence of Level1 parameters on modeled output characteristics is demonstrated
using Fig. 3.2, where output and transfer characteristics of variations of all three Level1 pa
3.2. Existing Models for OFETs 25
rameters are shown. The reference device was an ntype FET with the following parameters:
K
P
= 1 nA/V
2
, V
T
= 2 V, λ = 0, W/L = 2000. The parameters have been chosen for demon
stration purposes. In Fig. 3.2ab, the effect of varying the process conductance is depicted.
Increasing K
P
from 1 pA/V
2
to 1.5 pA/V
2
will proportionally increase the drain current I
D
.
In Fig. 3.2cd, the inﬂuence of the threshold voltage is demonstrated. Here, V
T
is raised
from 2 V to 10 V. The impact of this increase is best seen in the I
D
vs. V
GS
plot where
the onset of drain current shifts from V
GS
= 2 V to 10 V. In Fig. 3.2ef, the impact of the
channellength modulation λ is shown.
3.2.1.2 Discussion
In Table 3.2, a rating of Level1 modeling with respect to the model quality chart (MQC)
from Section 3.1 is shown. Due to the multitude of materials and processing routes, there is
no uniform shape of the current/voltage characteristics of OFET devices [30]. Therefore, the
accuracy of the Level1 approach has been rated from bad to medium. It can adequately repro
duce OFET types where the mobility only weakly depends on the gatesource voltage. Other
modeling approaches are better suited for devices with e.g. variable mobility. Modeling of
capacitances is not part of the basic equations. It should be noted, however, that Level1 imple
mentations in SPICE simulators include nonlinear modeling of capacitances which is similar
to OFETrelated capacitance values expectable from numerical analysis (see Section 3.2.4.2).
As the Level1 model is based on a physical background (gradual channel approxima
tion) and only few parameters are necessary in the equations, compactness of the model has
been rated as good. Numerous approaches can be used for deriving these parameters (see
Section 3.3.1). Therefore, parameter extraction has also been rated as good. Stress effects are
not included in the model.
Table 3.2: MQC for basic Level1 model.
Requirement Rating
Accuracy bad to medium
Capacitance Modeling not included
Compactness good
Parameter Extraction good
Stress Effects not included
In literature on modern MOSFET modeling [38], the Level1 approach is only considered
as a convenient ﬁrstorder approximation because the relatively simple equations facilitate
parameter extraction. More advanced models require concurrent ﬁtting of several parameters
to more sophisticated equations, which complicates the extraction process.
26 Chapter 3. OFET Modeling for Circuit Simulation
f)
d)
b) a)
e)
c)
0.0u
0.5u
1.0u
1.5u
2.0u
2.5u
3.0u
3.5u
−10 0 10 20 30 40 50
0.0
0.5u
1.0u
1.5u
2.0u
−10 0 10 20 30 40 50
0.0u
0.5u
1.0u
1.5u
2.0u
2.5u
0 10 20 30 40 50
0.0u
0.5u
1.0u
1.5u
2.0u
2.5u
3.0u
3.5u
0 10 20 30 40 50
0.0u
0.5u
1.0u
1.5u
2.0u
0 10 20 30 40 50
30 40 50
80n
70n
60n
50n
40n
30n
20n
10n
0n
0 10 20
I
D
[
A
]
I
D
[
A
]
I
D
[
A
]
I
D
[
A
]
I
D
[
A
]
I
D
[
A
]
V
GS
[V]
V
GS
[V]
V
GS
[V]
λ = 0.000 1/V
V
T
= 2 V
V
DS
= 50 V
V
DS
= 50 V
V
DS
= 50 V
K
P
=1.5 pA/V
2
V
T
= 10 V
λ = 0.005 1V
K
P
=1.0 pA/V
2
V
DS
[V]
V
DS
[V]
V
T
= 2 V
λ = 0.005 1/V
λ = 0.000 1/V
V
GS
= 50 V
40 V
20 V
30 V
V
GS
= 10 V
V
T
= 10 V
K
P
=1.0 pA/V
2
K
P
=1.5 pA/V
2
V
DS
[V]
Fig. 3.2: I
D
vs. V
DS
and I
D
vs. V
GS
for variations of the Level1 parameters: ab) variation
of K
P
, cd) variation of V
T
, and ef) variation of λ.
3.2. Existing Models for OFETs 27
3.2.2 Model for Polycrystalline TFTs
The Level1 model presented in Section 3.2.1 was designed for crystalline silicon transistors
and does not account for V
GS
dependent mobilities. Therefore, more sophisticated modeling
approaches for organic transistors have been presented in literature such as the grain bound
ary model for polycrystalline transistors. This model is based on the fact that vapordeposited
organic semiconductors like pentacene organize themselves into grains of singlecrystalline
structure [39]. Charge carriers are impeded by traps when they move across boundaries of
adjacent grains. Those traps can cause carrier scattering and momentum transfer to phonons
in the crystal [39]. The existence of traps leads to trapping of carriers, which in turn is re
sponsible for a depletion of charge carriers at the grain boundaries [40] and the formation of
a barrier potential.
Polycrystalline silicon thinﬁlm transistors (PsiTFTs) show comparable behavior. In
these devices, the mobility is described by an empirical equation
1
µ
eff
=
1
µ
g
+
1
µ
gb
, (3.6)
with µ
eff
being the effective mobility (i.e. net mobility), µ
g
the mobility inside the single
crystalline grain, and µ
gb
the mobility obtained at the grain boundaries.
The drain current above threshold can be calculated with
I
d
=
W
L
V
DS
0
{C
is
[V
GS
−V
T
−V (x)] · µ
eff
} dV, (3.7)
where V (x) is the drainsource voltage at position x along the length of the channel. The
other variables have their usual meaning.
Popular simulation models for polycrystalline silicon do not provide an exact solution to
(3.7) but instead express the mobility by an empirical equation, e.g. [41] for the PsiTFT
model from the Rensselaer Polytechnic Institute (RPI, Troy, NJ, USA). Such an approach
eventually leads to an adaption of the basic model presented in Section 3.2.1 with a V
GS

dependent mobility [42]. The nature of charge transport in organic semiconductors is still a
matter of debate. Nonetheless, some groups (e.g. Horowitz and coworkers [43], Frisbie and
coworkers [44, 45]) established theories for organic crystals and polycrystalline structures
where charge transport within a single grain can be viewed as bandlike. Transport across
grain boundaries and the semiconductor interface to the electrodes, however, is impeded by
the presence of traps.
The PsiTFT model has been used in [46] for modeling of the abovethreshold current of
OFETs.
28 Chapter 3. OFET Modeling for Circuit Simulation
3.2.2.1 Model Equations
In the following, simpliﬁed equations for the RPI PsiTFT model will be presented. A more
detailed description can be found in [47]. The RPI model assumes the effective chargecarrier
mobility µ
eff
to be determined by an empirical law
1
µ
eff
=
1
µ
′
1
+
1
µ
0
, (3.8)
with µ
0
being an upper mobility limit for high gate biases similar to µ
g
in (3.6) and µ
′
1
deter
mined by an empirical power law for low V
GS
values as
µ
′
1
∼ µ
1
V
mµ
GST
. (3.9)
Here, µ
1
is the lowﬁeld mobility and m
µ
is a mobility parameter. Both quantities can be
extracted from currentvoltage measurements. For convenience reasons, V
GST
= V
GS
−V
T
is
used.
The drain current is composed of three contributors:
1. the subthreshold leakage current I
leak
,
2. the subthreshold current I
sub
,
3. the above threshold current I
a
.
Fig. 3.3 shows a schematic plot
1
of the drain current and its three contributors in logarith
mic scale vs. the gatesource voltage V
GS
. The derivation of the equations for I
leak
, I
sub
, and
I
a
are detailed by Jacunski and colleagues [47]. In this work, only simpliﬁed equations will
be presented in order to show the V
GS
 and V
DS
dependence of the contributing currents.
The subthreshold leakage current I
leak
in the RPI model has not been used in the modeling
of OFETs so far. Therefore, the equations will not be reproduced here.
The subthreshold current in the PsiTFT model reads
I
sub
= µ
s
· C
is
W
L
(η
i
V
th
)
2
exp
V
GST
η
i
V
th
¸
1 −exp
−V
DS
η
i
V
th
. (3.10)
Here, µ
s
is the subthreshold mobility and η
i
is the subthreshold ideality factor. Both param
eters are extracted using measurements of the drain current. The other parameters have their
usual meaning.
1
Model data: µ
eff
= 1 · 10
−3
cm
2
/Vs, C
is
= 1 · 10
−7
F/cm
2
, V
T
= 1 V, α
sat
= 1.1, µ
s
= 1 · 10
−11
cm
2
/Vs,
η
i
=3.34, I
0
= 1 · 10
−13
A, W/L = 1000. A simple ﬁtting equation for the leakage current has been used, which
reads I
leak
= I
0
exp(−(V
GS
−V
T
)/6).
3.2. Existing Models for OFETs 29
10.0f
100.0f
1.0p
10.0p
100.0p
1.0n
10.0n
100.0n
1.0u
10.0u
−4 −2 0 2 4 6 8 10
V
GS
[V]
I
a
I
sub
I
leak
I
D
[
A
]
Fig. 3.3: Operation regions of a simulated PsiTFT.
The slope of the subthreshold current I
sub
in (3.10) in decimal logarithmic scale is given by
log e/(η
i
V
th
). For OFETs, it is the reciprocal of the subthreshold swing [48] or subthreshold
slope [49] S. [49] deﬁnes the subthreshold slope as the necessary variation of the gatesource
voltage for modulating the subthreshold current by one decade. Alternatively, the IEEE stan
dard on the characterization of OFETs [48] deﬁnes the subthreshold swing as the maximum
slope of the logarithmic transfer characteristic in the subthreshold region. The subthreshold
slope is given in V/dec and typically ranges from 1 to 5 V/dec for ptype organic semicon
ductors [49]. In comparison to crystalline silicon with a typical subthreshold slope of approx
imately 60 mV/dec at room temperature, a large range of gatesource voltage is required to
achieve low off currents [49].
The abovethreshold drain current I
a
is given by [26]
I
a
=
µ
eff
C
is
W
L
V
GST
V
DS
−
V
2
DS
2αsat
for V
DS
< α
sat
(V
GST
)
µ
eff
C
is
W
L
(V
GST
)
2
α
sat
2
for V
DS
≥ α
sat
(V
GST
)
(3.11)
Here, µ
eff
is the V
GS
dependent mobility from (3.8), α
sat
is an empirical parameter accounting
for a V
GS
dependent modulation of the transition point between the linear and the saturation
region.
30 Chapter 3. OFET Modeling for Circuit Simulation
The total drain current is calculated by
I
D
= I
leak
+
1
1
I
sub
+
1
I
a
. (3.12)
With the reciprocal subterm, a uniﬁed equation for the subthreshold region, abovethreshold
region and transition region between the two can be used.
The effective control voltage V
GST
used in the RPI model is deﬁned by
V
GST
=
V
GS
−V
T
for V
GS
−V
T
> 2η
i
V
th
2η
i
V
th
else
. (3.13)
Here η
i
is the subthreshold ideality factor introduced in (3.10). (3.13) effectively limits
V
GST
to values above 2η
i
V
th
. Without limiting V
GST
, values close to zero could be reached in
(3.11). These values would introduce an incorrect singularity in the transition region.
A reasonable parameter set for a P3HT transistor in topgate conﬁguration is listed in
Table 3.3 (details on how the values were obtained are given in Section 4.3.6).
Fig. 3.4 provides plots where the parameters m
µ
and α
sat
are varied. Reference parameters
for the plots were α
sat
= 1.0, m
µ
= 0.0, V
T
= 2.0 V. These were chosen so that the drain
currents of the PsiTFT device and the Level1 device presented in Section 3.2.1 are identical.
By varying α
sat
and m
µ
, the changes introduced by the PsiTFT equations with respect to the
original Level1 modeling can be studied.
3.2.2.2 Discussion
A rating of the polycrystalline grain boundary model is presented in Table 3.4. The model
takes a V
GS
dependent mobility into account. Therefore, accuracy has been rated as good (see
Section 4.3.6 for an example of model accuracy). Modeling of capacitances is not included
in the model. Compactness has been rated as good because only a small number of parame
ters is needed for modeling the abovethreshold behavior. One can argue, however, that the
underlying RPI model uses only an “effective medium approach” [50] where the stochastic ar
rangement of grains of different sizes is modeled by a single effective medium with equivalent
properties. Hence, the model equations can be considered as statistical descriptions. This fact
complicates ﬁnding the relationship between model parameters and those parameters which
reﬂect device structure and fabrication processes. Nevertheless, compactness has been rated
as good as only a small amount of parameters is necessary. Parameter extraction is difﬁcult
because of the biasdependent mobility as will be discussed in Section 3.3.2. This property
leads to a rating of medium. Similar to Level1 modeling, stress effects are not included in
3.2. Existing Models for OFETs 31
Table 3.3: PsiTFT parameters for topgate ptype P3HT device (other parameters not used).
Parameter Value
capacitance C
is
per unit area 1 · 10
−7
F/cm
2
lowﬁeld mobility µ
1
2.5 · 10
−5
cm
2
/Vs
zerobias threshold voltage V
T
2.9 V
saturation variation parameter α
sat
0.8
lowﬁeld mobility exponent m
µ
0.886
channellength modulation parameter λ 0.005 V
−1
b)
d)
a)
c)
1.5u
0 10 20 30 40 50
0 10 20 30 40 50
2.0u
1.0u
0.5u
0.0u
4.0u
3.5u
3.0u
2.5u
2.0u
1.5u
0.5u
1.0u
0.0u
0 10 20 30 40 50
0 10 20 30 40 50
4.0u
3.5u
3.0u
2.5u
2.0u
1.5u
1.0u
0.5u
0.0u
2.0u
1.5u
1.0u
0.5u
0.0u
I
D
[
A
]
I
D
[
A
]
I
D
[
A
]
I
D
[
A
]
V
DS
[V]
α
sat
= 1.0
V
DS
[V]
α
sat
= 0.5
m
µ
= 0.0
m
µ
= 0.1
V
GS
[V]
α
sat
= 1.0
V
GS
[V]
α
sat
= 0.5
m
µ
= 0.1
m
µ
= 0.0
Fig. 3.4: I
D
vs. V
DS
and I
D
vs. V
GS
for variations of the PsiTFT parameters α
sat
and m
µ
:
ab) variation of α
sat
, cd) variation of m
µ
.
32 Chapter 3. OFET Modeling for Circuit Simulation
the model.
Table 3.4: MQC for PsiTFT.
Requirement Rating
Accuracy good
Capacitance Modeling not included
Compactness good
Parameter Extraction medium
Stress Effects not included
The effective medium approach has also been used for studying the grainsizedependent
mobility for pentacenebased OFETs [51] in order to yield an effective mobility
µ
eff
= µ
g
1
1 +nβ exp(qV
B
/kT)
, (3.14)
with µ
g
being the grain intrinsic mobility, n the number of grain boundaries along the chan
nel, β the ratio between an effective grainboundary size and the channel length, and V
B
the
potential barrier between grains. For polycrystalline silicon TFT (PsiTFT) devices, similar
relationships have been exploited to derive closedform draincurrent equations in the form of
[52]
I
D
=
W
L
µ
eff
C
is
(V
GS
−V
T
)V
D
. (3.15)
Here, the drain current in the linear region is modeled. Results in [51] suggest that µ
eff
non
linearly depends on the effective grain size and the gatesource voltage. Studies on the V
GS
dependence of PsiTFT devices in [52] yielded a sixthorder polynomial needed for modeling
of the potential barrier V
B
(V
GS
). To the knowledge of the author of this work, this model
has not been applied to polycrystalline OFETs so far. It is suggested to further explore this
approach.
3.2.3 Model for Amorphous TFTs
Necliudov and colleagues [32] describe a model which improves the ﬁtting between the Level
1 model and experimental data for vapordeposited pentacene OFETs. The model is based on
the assumption that above threshold, most of the charge carriers induced in the channel are
trapped and only a small fraction contributes to charge transport. A V
GS
dependent mobility
reﬂects this property. The model is derived from the TFT model for amorphous silicon TFTs
(aSi TFT). In aSi TFTs, no longrange order of the silicon material exists. Instead, the atoms
are organized in a random network, which leads to many energy states in the forbidden band
gap. These states are localized and statistically distributed. They arise from unterminated
3.2. Existing Models for OFETs 33
bonds or variations of bond angle and bond length. Fig. 3.5 provides a schematic view of
the energy band diagrams of crystalline and amorphous silicon. In crystalline silicon, there is
a clear band gap without states between the edges of the valence band (E
V
) and conduction
band (E
C
). In amorphous silicon, no clearlydeﬁned band gap exists.
band band
valence conduction
band band
valence conduction
d
e
n
s
i
t
y
o
f
s
t
a
t
e
s
energy
energy
d
e
n
s
i
t
y
o
f
s
t
a
t
e
s
a) crystalline
b) amorphous
states
localized
forbidden
band gap
E
V
E
C
E
C
E
V
Fig. 3.5: Schematic energy band diagram of a) crystalline silicon and b) amorphous silicon
(adaption from [53]).
Charge carriers trapped in bandgap states do not contribute to the drain current of the
FET. Hence, the effective mobility of aSi TFTs is below the one of singlecrystalline silicon
devices. Moreover, it depends on the gate voltage because at higher gate voltages, more trap
states are ﬁlled and therefore, more charge carriers of the ones injected at the source electrode
can contribute to the current ﬂow.
3.2.3.1 Model Equations
The gatevoltage dependent mobility µ is described by a ﬁtting function as
µ = µ
0
V
GS
−V
T
V
AA
γ
. (3.16)
Here, µ
0
, V
AA
, and γ are ﬁtting parameters obtained from experimental data, where γ is a
power parameter and V
AA
is the characteristic voltage for the chargecarrier mobility [54].
34 Chapter 3. OFET Modeling for Circuit Simulation
[32] reported results for topcontact (TC) and bottomcontact (BC) pentacene devices.
Bottomcontact devices showed nonlinear output characteristics at gatesource voltages around
zero. These devices were modeled with constant source and drain series resistors and pairs of
Schottky diodes. Fig. 3.6 shows the conﬁguration. The approach is an adaption of the RPI
model for amorphous silicon thinﬁlm transistors (RPI aSi TFT) [55] to organic transistors.
It is a ﬁtting model which neglects the physical background of the equations.
S
R
S
R
D
G
D
Fig. 3.6: Equivalent circuit of a bottomcontact OFET with diodes and series resistors for
modeling nonlinear contact resistance.
The Schottky diodes are modeled with an empirical extension to the basic Shockley equa
tion. The extension introduces an ideality factor η which accounts for the inﬂuence of non
ideal effects (η > 1) on the diode current [50]. This current I is
I = I
S
¸
exp
V
ηV
th
−1
. (3.17)
Here, I
S
is the saturation current, V the voltage drop across the diode, and V
th
is the thermal
voltage. η determines the steepness of the IV characteristic of (3.17).
3.2. Existing Models for OFETs 35
3.2.3.2 Experimental Extraction Results
Necliudov and colleagues obtained contact resistances in the range of 50 kΩ to 100 kΩ for
channel widths of 220 µm and a diode ideality factor η = 10 for a pentacene device with bot
tom contacts. Detailed information on the parameters necessary for calculating the saturation
current is not given in [32]. Nevertheless, adequate extraction procedures for standard aSi
TFTs are available e.g. in in [56, 57].
Table 3.5 provides model parameters for pentacene devices fabricated in both bottomgate
topcontact (TC) and bottomgate bottomcontact (BC) conﬁguration [32].
Table 3.5: Typical model parameters of topcontact (TC) and bottomcontact (BC) pentacene
OFETs [32].
Type W/L R
S,D
V
T
µ
0
γ V
AA
η
TC 220 µm /30 µm 100 kΩ 5 V 10 cm
2
/Vs 0.45 300 kV 
BC 220 µm /20 µm 50 kΩ 13 V 10 cm
2
/Vs 0.38 19 kV 10
3.2.3.3 Discussion
The calculated mobility of aSi TFTs in (3.16) effectively resembles the mobility calcula
tion for polycrystalline silicon (PsiTFT) in (3.9) so that comparable results can be expected.
However, the PsiTFT model also includes a variation factor α
sat
for the onset of saturation
(see (3.11)) in the output characteristics I
D
vs. V
DS
. The aSi RPI model also includes such a
factor, but Necliudov and colleagues did not use it maybe because α
sat
is difﬁcult to separate
from contact effects.
In Table 3.6, a rating of the model for aSi TFTs according to the model quality chart
deﬁned in Section 3.1 is provided. The accuracy of the model with respect to pentacene tran
sistors is good as demonstrated in [32]. Modeling of capacitances and biasinduced stress is
not included in the model. The model needs only six technology parameters (R
C
= R
S
= R
D
,
η, V
T
, µ
0
, γ, V
AA
), which increases its compactness (rating good). Contact effects inﬂuence
the shape of currentvoltage characteristics in a nonlinear way. Therefore, parameter extrac
tion schemes which rely on curve ﬁtting are difﬁcult to employ. This property complicates
parameter extraction (rating bad). Necliudov et al. point out that they use the contact resistors
and diodes mainly to approximate the shape of the output characteristics in the linear region.
However, a more precise procedure would consist of measuring the contact resistances and
barriers beforehand and compensating their effects in the calculations of the other parameters.
Moreover, it was pointed out elsewhere [58] that although a FET with double, opposite diodes
at the electrodes provides a good I/V description, it lacks a physical basis. Therefore, other
36 Chapter 3. OFET Modeling for Circuit Simulation
research teams use transistor conﬁgurations with only two Schottky diodes instead of four in
order to model nonlinear contact effects. One diode is placed at the source electrode and the
other at the drain electrode in opposite direction. For example, Brederlow and colleagues [33]
proposed a conﬁguration with a transistor
2
, two contact resistors and two contact Schottky
diodes, as shown in Fig. 3.7. In normal operation, one diode is forwardbiased while the other
operates in reverse breakdown operation. As an additional feature, the barrier height of each
diode is assumed to be gatevoltagedependent in [33]. Details about the V
GS
dependence of
the contact diodes can be found in the cited paper. Procedures for dealing with nonlinear
contact effects and for extracting diode parameters can be found e.g. in [46, 59].
Source
Drain
Gate
Fig. 3.7: Equivalent circuit for contact model with reverse and forwardbiased diodes (adap
tion from [33]).
Table 3.6: MQC for aSi TFT with contact diodes/resistors.
Requirement Rating
Accuracy good
Capacitance Modeling not included
Compactness good
Parameter Extraction bad
Stress Effects not included
Necliudov and colleagues [32] analyzed pentacenebased OFETs in bottomgate conﬁg
uration which were fabricated using lithographic processes. In a recent work by Bartzsch
et al. [60], the aSi TFT model was successfully applied to allprinted ptype F8T2 transis
tors. The F8T2 devices could be modeled with ohmic contact resistance (R
S
= R
D
= 70 kΩ).
Modeling of contact diodes was not needed for reproducing the measured output characteris
tics. The reported device parameters are somewhat unexpected. As an example, V
AA
= 1 GV
and γ = 1 · 10
−10
of the investigated device suggest that the gatesource voltage does not
noticeably affect the chargecarrier mobility in (3.16).
2
However, the transistor is modeled by a MOSFET model instead of a TFT model. The approach is focused
on the modeling of the contacts.
3.2. Existing Models for OFETs 37
3.2.4 Analytic VRH Models
In the following, different interpretations of the variable range hopping (VRH) model are
presented. In the VRH approach, thermally activated tunneling of carriers between localized
states, i.e. hopping, is assumed. The ﬁrst analytical treatment of VRHdriven charge transport
in organic semiconductors was carried out by Vissenberg and Matters [61]. Meijer and co
workers [62] provided qualitative equations dealing with the VRHcontrolled current in the
linear region of OFETs. Calvetti et al. then provided full treatment of output characteristics
of OFETs based on the VRH approach, including calculations of device capacitances [63].
The model treated linear and saturation region and was later enhanced with equations for
subthreshold current by the same group [64].
In another approach, Fadlallah and colleagues [65] derived similar equations as in [63].
This time, however, the Universal Mobility Law (UML) described by Brown et al. in [3] was
used.
More recent studies by Schliewe and coworkers [66] are also based on the VRH approach,
but with emphasis on modeling the effect of the bulk conductivity on the drain current in the
linear region.
3.2.4.1 Meijer SwitchOn Model
The switchon model from Meijer and colleagues [62, 67] approaches transistor behavior
by use of a switchon voltage V
SO
instead of the threshold voltage V
T
. V
SO
represents the
gate voltage at which accumulation of charge carriers begins (see also discussion on p. 59).
In the switchon model, the conductivity of the transistor channel is determined using an
adaption of the variablerange hopping model [61]. The adaption employs the percolation
deﬁned conductivity [67]
σ(δ, T) = σ
0
δN
t
(T
0
/T)
4
sin(π
T
T
0
)
(2α)
3
B
C
T
0
T
(3.18)
in the gradualchannel approximation. Here, σ
0
is a prefactor of the conductivity, δ is a func
tion of the temperaturedependent charge carrier occupation, N
t
is the density of localized
states, T
0
is a parameter representing the width of the exponential distribution, α is an effec
tive overlap parameter between localized states, and B
C
is a critical number for the onset of
percolation (2.8 in threedimensional amorphous systems).
38 Chapter 3. OFET Modeling for Circuit Simulation
Meijer and colleagues calculated the drain current from (3.18) according to:
I
DS
=
W
L
V
DS
εsε
0
σ
0
q
T
2T
0
−T
2k
B
T
0
εsε
0
×
(
T
0
T
)
4
sin
“
π
T
T
0
”
(2α)
3
B
C
T
0
T
×
εsε
0
2k
B
T
0
C
i
(V
GS
−V
SO
)
εsε
0
2T
0
T
−1
.
(3.19)
Here, ε
s
and ε
0
are the relative permittivity of the semiconductor and the free permittivity of
vacuum, respectively.
In the switchon model, the four parameters σ
0
, α
−1
, T
0
, and V
SO
are used for modeling
of the output characteristics. Meijer’s results [67] show agreement between experimental
data and simulations of poly(2,5thienylen vinylene) (PTV), solutionprocessed pentacene,
and poly(3hexylthiophene) (P3HT). Typical values for samples of these semiconductors are
given in Table 3.7.
Table 3.7: Representative parameters [67] for solutionprocessed OFETs modeled by the Mei
jer switchon model.
Material T
0
[K] σ
0
[10
6
S/m] α
−1
[Å] V
SO
[V]
PTV 382 5.6 1.5 1
Pentacene 385 3.5 3.1 1
P3HT 425 1.6 1.6 2.5
3.2.4.2 Brescia VRH model
While Meijer and coworkers used their VRH equations only as a tool to study the physical
properties of different materials, Calvetti and colleagues [63] from the University of Brescia,
Italy, elaborated an analytical model useful for circuit simulators like SPICE. The drain current
reads
I
D
= β
W
L
T
2T
0
(V
GS
−V
SO
)
2T
0
/T
−(V
GS
−V
DS
−V
SO
)
2T
0
/T
(3.20)
for an ntype device in the linear region (V
GS
−V
SO
> V
DS
) and
I
D
= β
W
L
T
2T
0
(V
GS
−V
SO
)
2T
0
/T
(3.21)
in the saturation region for V
GS
− V
SO
≤ V
DS
. The reader should note that in the original
publication [63], the ﬂatband voltage V
FB
is used for denoting the onset of accumulation. For
consistency reasons, however, V
SO
will be used in the following. The parameter β is deﬁned
3.2. Existing Models for OFETs 39
as
β =
σ
0
q
T
2T
0
−T
C
2T
0
/T−1
is
(2k
B
T
0
ε
s
ε
0
)
T
0
/T−1
(T
0
/T)
4
sin(πT/T
0
)
(2α)
3
B
C
T
0
/T
. (3.22)
In this equation, the parameters have their meaning as deﬁned in Section 3.2.4.1. Calvetti et al.
also used the parameters in Table 3.7 and assumed ε
s
= 3.0 as well as C
is
= 1.3 ×10
−4
F/m
2
.
The Brescia model also treats the calculation of dynamic model behavior by specifying
equations for the induced charges Q
S
, Q
D
, and Q
G
at the terminals source, drain, and gate.
The calculations give rise to somewhat lengthy expressions. As an example, Q
G
reads
Q
G
= −WLC
is
Q
Gnum
Q
Gden
, (3.23)
Q
Gnum
=
T
2T
0
+ T
(V
2T
0
T
+1
GST
−V
2T
0
T
+1
GDT
) +
k
B
T
q
(V
2T
0
T
GST
−V
2T
0
T
GST
), (3.24)
Q
Gden
=
T
2T
0
(V
2T
0
T
GST
−V
2T
0
T
GDT
) +
2T
2T
0
−T
k
B
T
0
q
(V
2T
0
T
−1
GST
−V
2T
0
T
−1
GDT
). (3.25)
Here, V
GST
= V
G
− V
S
− V
SO
, and V
GDT
= V
G
− V
D
− V
SO
. From Q
G
, the gatesource
and gatedrain capacitances can be derived using
C
GS
=
Q
G
V
GS
V
GD
=const
, C
GD
=
Q
G
V
GD
V
GS
=const
. (3.26)
Fig. 3.8 shows a comparison of calculated capacitances C
GS
and C
GD
in the Brescia VRH
model with capacitances calculated by the Meyer model used in MOSFET models, both nor
malized to C
g
= WLC
is
. Gate charge in the Meyer MOSFET model was calculated using
Q
G
=
2
3
C
is
V
3
GST
−V
3
GDT
V
2
GST
−V
2
GDT
. (3.27)
The plots were calculated for an OFET with pentacene as active layer. As indicated by the
plots, conventional Meyer model predicts capacitances with slightly different values than com
puted with the Brescia capacitance model. The reader should note, however, that these calcu
lations do not include the contribution of the overlap capacitance of the source/drain ﬁngers
(see Fig. 2.4). If e.g. the drain/source ﬁngers are assumed to have the same widths as the
length of the channel, additional overlap capacitances C
GSO
= C
GDO
= C
g
/2 would have
to be included. Consequently, the curves in Fig. 3.8 would have to be shifted up by 0.5. A
comparison of the curves shows that Meyerbased modeling of capacitances already provides
reasonable ﬁrstorder approximation. Meyermodeling of C
GS
will lead to voltagedependent
capacitances (without considering overlap capacitances) which are 2% to 12% below the val
ues predicted by the Brescia model. For C
GD
, the Bresciamodeled values can lag behind the
40 Chapter 3. OFET Modeling for Circuit Simulation
Meyermodeled capacitance values by up to 40%.
Meyer
VRH
Meyer
VRH
0.55
0.6
0.65
0.7
−30 −25 −20 −15 −10 −5
0
0.1
0.2
0.3
0.4
−30 −25 −20 −15 −10 −5
C
G
S
/
C
g
V
GS
[V]
C
G
D
/
C
g
V
GS
[V]
Fig. 3.8: Comparison of capacitance ratios C
GS
/C
g
and C
GD
/C
g
calculated with the Brescia
(solid lines) and Meyer model (stars), respectively. T
0
= 385 K (for pentacene) was used in
the VRH calculations.
Calvetti and colleagues also derived equations for the subthreshold region [64]. These
equations were found by numerical simulations of the twodimensional potential and charge
distribution within the channel in the subthreshold region. The simulations showed that in
the subthreshold region, the conductivity is modulated by the depletion of the carriers in the
semiconductor layer. Moreover, the drain current in subthreshold operation can be determined
using the gradual channel approximation. However, the resulting relations are quite compli
cated and will not be reproduced here. They can be found in [64].
3.2.4.3 UML Model
The model from Fadlallah and coworkers [65] is based on the observation by Brown and
colleagues [3] that the conductivity σ of charge carriers in a semiconductor ﬁlm is given by
an empirical equation
σ = K
′
N
γ
A
, (3.28)
where N
A
is the dopinginduced charge density in the semiconductor, K
′
and γ are ﬁtting
parameters. The chargecarrier mobility µ is then approximated by the simple power law
µ = KN
γ−1
A
. (3.29)
3.2. Existing Models for OFETs 41
Here, K is another ﬁtting parameter. Brown et al. showed that this empirical power law can
be applied to a variety of polymer materials. Hence, the law is referred to as the Universal
Mobility Law (UML) in [65]. (3.29) can be employed for the mobility in the gradual channel
approximation in order to get
I
D,lin
=
K
(2m+ 1)(2m+ 2)
W
L
C
2m+1
is
(2k
B
Tε
0
ε
s
)
m
V
2(m+1)
GST
−(V
GST
−V
DS
)
2(m+1)
(3.30)
for the linear region (V
GS
− V
T
> V
DS
) of a ptype OFET. Here, m = γ − 1 and the voltage
V
GST
= V
GS
−V
T
while the other parameters have their usual meaning. The drain current in
the saturation region (V
GS
−V
T
< V
DS
) is given as
I
D,sat
=
K
(2m+ 1)(2m+ 2)
W
L
C
2m+1
is
(2k
B
Tε
0
ε
s
)
m
(V
GS
−V
T
)
2m+2
[1 +λ(V
DS
−V
GST
]. (3.31)
The cutoff current (for V
GS
> V
T
) is assumed to be independent of both the drainsource
voltage and the gatesource voltage and is modeled by
I
D,off
= I
00
W. (3.32)
I
00
is the current density in the cutoff region and W is the channel width of the device.
Modeling of capacitances on the basis of the UML model is also presented in [65]. The
threshold voltage V
T
was assumed to be equivalent to the switchon voltage V
SO
of the device
so to get the total charge on the gate electrode of
Q
G
= C
is
WL
(2m+ 2)
(2m+ 3)
·
V
2m+3
GDT
−V
2m+3
GST
V
2m+2
GDT
−V
2m+2
GST
. (3.33)
Here, V
GDT
= V
G
− V
D
− V
SO
, V
GST
= V
G
− V
S
− V
SO
. It should be noted that ensuring
V
GST
≥ 0 and V
GDT
≥ 0 is necessary in the calculations in order to yield a correct charge in
(3.33). The gatesource capacitance is
C
GS
=
∂Q
G
∂V
GS
V
GD
=const
= −C
is
· W · L · V
2m+1
GST
·
2m+ 2
2m+ 3
×
(2m+ 2)V
2m+3
GDT
−(2m+ 3)V
2m+2
GDT
V
GST
+ V
2m+3
GST
(V
2m+2
GDT
−V
2m+2
GST
)
2
. (3.34)
42 Chapter 3. OFET Modeling for Circuit Simulation
Similarly, the gatedrain capacitance is equivalent to
C
GD
=
∂Q
G
∂V
GD
V
GS
=const
= −C
is
· W · L · V
2m+1
GDT
·
2m + 2
2m + 3
×
(2m+ 2)V
2m+3
GST
−(2m+ 3)V
2m+2
GST
V
GDT
+ V
2m+3
GDT
(V
2m+2
GDT
−V
2m+2
GST
)
2
. (3.35)
Fadlallah and colleagues carried out validations of the Eldo implementation in order to
test the convergence in transient simulations of a ring oscillator. The ring oscillator consisted
of inverters in diode conﬁguration (load transistor with gate and drain at negative supply, both
transistors with PTAA as semiconducting material). A comparison between measured and
simulated oscillation signals was not given in the publication.
The UML model and the Brescia model are almost identical if the following parameter
translation is used:
K =
σ
0
q
T
0
T
4
sin(π
T
T
0
)
(2α)
3
B
C
T
0
T
, m =
T
0
T
−1. (3.36)
The UML model provides treatment of the channellength modulation while the Brescia
model contains more sophisticated equations dealing with the subthreshold currents. More
over, the Brescia model works with the term 2k
B
T
0
ε
s
ε
0
while the UML model resorts to
2k
B
Tε
s
ε
0
.
3.2.4.4 Hamburg VRH Model
In another approach, Schliewe and colleagues [66] derived VRH equations for the steadystate
drain current:
I
D
= −
W
L
aC
is
b + 2
r
b+2
(V
SO
−V
GS
) −r
b+2
(V
SO
−V
GD
)
. (3.37)
Here, a and b are parameters derived from the relationship between the mobility and the gate
voltage
µ(x) = a(V
SO
−V
Gx
)
b
. (3.38)
V
Gx
represents the voltage between the gate and the position x along the semiconductor
insulator interface, V
SO
is the switchon voltage. r is a step function which allows using one
3.2. Existing Models for OFETs 43
uniﬁed equation for the linear and saturation region. It is deﬁned as
r(V ) =
V, V ≥ 0
0, V < 0.
(3.39)
(3.37) and (3.30) are equivalent for
a =
K
2m+ 1
C
2m
is
(2k
B
Tε
0
ε
s
)
m
, b = 2m. (3.40)
3.2.4.5 Discussion
The analytical VRH models presented in this section are physicsbased models which qualita
tively predict transistor behavior. In this way, they differ from other models discussed earlier
in this chapter. The other models simply extend existing approaches developed for inorganic
technologies.
Table 3.8 provides a rating of the physical models with respect to the model quality chart
presented in Section 3.1. Accuracy has been rated as good according to the data provided in
[62, 63, 65, 66, 67]. Modeling of capacitances is included. The physical models work with a
limited set of parameters, which improves their compactness and leads to a rating of good in
this category. Parameter extraction has been rated as medium because it is more difﬁcult than
in the case of Level1 modeling. Stress effects are not included in any of the analytical VRH
models.
Table 3.8: MQC for analytical VRH models.
Requirement Rating
Accuracy good
Capacitance Modeling good
Compactness good
Parameter Extraction medium
Stress Effects not included
3.2.5 General Tablebased Models
Tablebased models avoid the problems of parameter extraction. These models store tables
of output characteristics in a compressed form. The tables are then used in the simulations in
order to derive the behavior of a device. Such approaches completely disregard physicsbased
parameters and instead focus on accurate reproduction of measured values.
44 Chapter 3. OFET Modeling for Circuit Simulation
In Table 3.9, tablebased models have been rated according to the model quality chart
developed in Section 3.1. Accuracy in reproducing a reference device is excellent because
its characteristics are stored in a table. Modeling of capacitances can also be carried out
accurately by use of tables if the simulation environment supports tables for nodal charges
(e.g. Tanner TSpice [68]). Parameter extraction is not required.
Compactness has been rated as bad because tablebased modeling generally does not pro
vide parameters which can be accessed by the users. Moreover, these internal parameters
are without physical meaning or relations to device structure. This fact complicates those
statistical modeling approaches where correlations between variations of physical and/or ge
ometrical device properties and output characteristics are analyzed. Therefore, stress effects
are also difﬁcult to include in the models.
Owing to the missing inﬂuence on the output characteristics, tablebased modeling is not
suited for the exploratory study of parameter variations. However, it can be a viable tool in
combination with twodimensional transistor simulators because it provides rapid modeling
without the need to derive model parameters.
Table 3.9: MQC for table models.
Requirement Rating
Accuracy good
Capacitance Modeling good
Compactness bad
Parameter Extraction not needed
Stress Effects not included
3.2.6 Dresden Model
Gay and colleagues [69] fromthe Dresden University of Technology developed a model which
completely disregards the physical background of modeling. Instead, it resorts to powerful
ﬁtting functions and focuses on the simulation of analog circuits which require accurate tran
sistor models [25].
3.2.6.1 Model Equations
The Dresden model is based on the observation that the individual curves of the output charac
teristics I
D
vs. V
DS
are similar in shape. A curve for a particular gate voltage V
GS,0
is used as
a template and is described by a reference or shape function f and powerful ﬁtting functions
3.2. Existing Models for OFETs 45
that map f to alternate geometries and V
GS
values. The drain current is described as
I
D
= K
G
· f
¸
V
DS
τ(V
GS
)
· h(V
GS
). (3.41)
Here, K
G
is a geometry factor which scales arbitrary transistors to the geometry of a reference
transistor for which the function f is derived. K
G
is calculated according to
K
G
=
W/L
W
R
/L
R
, (3.42)
where W/L and W
R
/L
R
are the widthtolength ratios of the actual and the reference de
vice, respectively. f approximates the currentvoltage shape of the reference transistor at a
predeﬁned gate voltage V
GS,0
. It is deﬁned as
f(V
DS
) = −10
X
f
with X
f
=
¸
i
a
i
exp(−b
i
V
DS
). (3.43)
Here, a
i
and b
i
are ﬁtting parameters used for approximating the reference curve. The scale
function h scales the drain current with respect to different V
GS
values where h(V
GS,0
) = 1.
The approximation function is
h(V
GS
) = 10
X
h
with X
h
=
¸
i
c
i
· exp(−d
i
· V
GS
). (3.44)
Here, c
i
and d
i
are ﬁtting parameters. The delay function τ is used for stretching the reference
function f with respect to different V
GS
values where τ(V
GS,0
) = 1. τ is deﬁned as
τ(V
GS
) = 10
Xτ
with X
τ
=
¸
i
p
i
· exp(−q
i
· V
GS
). (3.45)
Again, p
i
and q
i
are ﬁtting parameters.
The parameters a
i
and b
i
in the reference function f are ﬁtted to measured drain current
points. c
i
, d
i
and p
i
, q
i
are then concurrently extracted with an optimization scheme.
Device variability is introduced by additional parameters in the drain current equations:
I
D
= K
s
· K
G
· f
V
DS
τ + τ
s
· h(V
GS
−V
ON
). (3.46)
Here, K
S
is a current scale factor, V
ON
is used for shifting the switchon voltage, and τ
s
is
used for shifting the delay of the transition between the linear and the saturation region. Gay
and colleagues modeled these three parameters with normal distributions, which they obtained
from measurements.
46 Chapter 3. OFET Modeling for Circuit Simulation
Fig. 3.9 shows the output characteristics and the ﬁtting functions for a pentacene device
generated with parameters from Table 3.10.
3.2.6.2 Discussion
In the Dresden model, the function f from (3.43) is used for compressing the measured values
into a more tractable form. Gay et al. use power series in order to approximate the shape of
measured drain current values. They thereby ignore any physical background responsible for
the shape of the curves.
The numerous parameters in the model can be derived easily but are not based on any
physical assumption or meaning. Therefore, there is no direct relationship to material or
process properties.
The Dresden model accounts for dynamic hysteresis effects by adding an RC network
which simulates the delayed transport of mobile charges within the insulator [69]. Moreover,
statistical variation of individual devices is addressed.
Table 3.11 contains ratings for the Dresden models according to the model quality chart
presented in Section 3.1. Accuracy has been rated as good according to the comparisons be
tween the model and measurement data presented in [69]. The compactness has been rated
as bad because many ﬁtting coefﬁcients (14 in the example from Table 3.10) without physical
meaning are needed. In the parameter extraction, curve ﬁtting is necessary. The ﬁtted param
eters are not independent of each other because there is no “true” set of parameters describing
the transistor. When different V
GS0
values are used (i.e. different shape functions f), differ
ent coefﬁcients result. Therefore, the parameter extraction has been rated as medium. Stress
effects are included in the model by simple RC networks. Hence a rating of medium has been
given. Explicit modeling of capacitances is not mentioned in [69]. Judging from results pre
sented in [69], constant capacitors for C
GS
and C
GD
are probably used. The Dresden model
easily copes with contact effects. Nevertheless, there is no link between the ﬁtting coefﬁcients
and physical or structural parameters. As an example, the inﬂuence of contact resistances is
hidden in the ﬁtting coefﬁcients from which it cannot readily be extracted. Moreover, phys
ically meaningful parameters like the threshold voltage are missing. Therefore, the Dresden
model is of limited use for device technologists who want to explore the inﬂuence of future
process changes on electrical device parameters.
3.2.7 Modeling of Complementary OFETs
The modeling of transistors used in complementary organic circuits is no special problem as
dedicated models for the ntype and ptype transistors can be used.
3.2. Existing Models for OFETs 47
Table 3.10: Fitting parameters for typical bottomgate bottomcontact pentacene transistor
[69] with pronounced contact resistance.
Shape function f Scale function h Delay function τ
a
1
1.2737 b
1
0.4115 c
1
3.8416 d
1
0.2432 p
1
1.9399 q
1
0.1215
a
2
6.7432 b
2
1.2e4 c
2
0.8047 d
2
0.0175 p
2
1.1035 q
2
0.0277
a
3
1.0077 b
3
1.9633 – – – – – – – –
0.5
1.5
2.5
3.5
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
4.0
3.0
2.0
1.0
0.0
1.0
−4.0
−6.0
−8.0
0.0
−10u
−20u
−30u
−40u
−50u
−60u
−70u
0u
−14 −12 −10 −8 −6 −4 −2 0
−10 −8 −6 −4 −2
−10 −8 −6 −4 −2 0
0
−2.0
−10.0
−12.0
−14.0
−16.0
−18.0
−14 −12 −10 −8 −6 −4 −2 0
I
D
[
A
]
h
(
V
G
S
)
f
(
V
G
S
)
τ
(
V
G
S
)
V
DS
[V]
V
GS
[V]
V
GS
[V]
x 10
−8
x
Fig. 3.9: Transfer characteristic and Dresdentype ﬁtting functions for a sample pentacene
transistor ([69]).
48 Chapter 3. OFET Modeling for Circuit Simulation
Table 3.11: MQC for Dresden model.
Requirement Rating
Accuracy good
Capacitance Modeling not included
Compactness bad
Parameter Extraction medium
Stress Effects medium
3.2.8 Modeling of Ambipolar OFETs
OFETs normally operate as unipolar devices where only one type of carriers (holes in ptype
and electrons in ntype semiconductors) contributes to the current ﬂow. Ambipolar devices
are a special class of OFETs where both holes and electrons can contribute to the current
ﬂow, depending on the bias voltages at drain, gate, and source. The operation of ambipolar
devices will be explained in the following with the aid of [13, 58]. Here, a zero threshold
voltage and positive drain and gate voltages will be assumed. When the gate voltage lies in
the range between the drain and source voltage, the drain side of a standard unipolar transistor
normally gets pinched off. In ambipolar devices instead, charge carriers of opposite polarity
are accumulated in this region. The device is then effectively composed of two regions in
series as shown in Fig. 3.10: a holeaccumulating region of length L
p
is seriesconnected to
an electronaccumulating region of length L
n
.
With the assumption of equal currents in both regions, i.e.
1
2
W
L
p
C
is
µ
p
(V
DS
−V
GS
)
2
=
1
2
W
L
n
C
is
µ
n
V
2
GS
, (3.47)
and a total length
L
n
+ L
p
= L, (3.48)
the drain current for V
DS
> 0 is
I
D
=
1
2
W
L
C
is
[µ
n
V
2
GS
+ µ
p
(V
DS
−V
GS
)
2
]. (3.49)
(3.49) is equivalent to a ptype and an ntype transistor of equal dimensions W and L in
parallel. For the ptype device, however, the position of the drain and source electrodes is
ﬂipped owing to the requirement that V
S,p
> V
D,p
, where V
S,p
and V
D,p
are the effective
source and drain voltages of the ptype device. During a V
DS
sweep with a ﬁxed V
GS
, the
ntype device is operated in normal FET mode while the ptype device has a constant gate
drain voltage V
GD,p
. Hence, the latter displays a diodelike drain current, which increases
3.2. Existing Models for OFETs 49
holes
electrons
c
h
a
r
g
e
d
e
n
s
i
t
y
0
position along the channel
p
o
t
e
n
t
i
a
l
drain
source
L
p
L
n
V
DS
V
GS
Fig. 3.10: Schematic charge and potential distribution in the channel of an ambipolar OFET
with V
S
< V
G
< V
D
(adaption from [58]).
with decreasing gate voltages. Therefore, a diodelike characteristic adds to the normal drain
current, which also increases with reduced gatesource voltage.
For V
DS
< 0, the situation is reversed and the ptype device acts as the normal transistor
and the ntype device contributes current in diodelike form.
Fig. 3.11 shows the schematic output characteristics of an ambipolar OFET. For the I/V
curves, a ptype transistor and an ntype transistor in parallel with µ
n
= µ
p
= 10
−4
cm
2
/Vs
have been assumed. In order to show the individual contributions of the two transistors,
V
T,n
= 10 V and V
T,p
= 8 V have been chosen.
Models developed in literature on ambipolar OFETs can be reduced to a parallel combina
tion of a ptype and an ntype transistor. Schmechel et al. [70] used simple Level1 equations
(see Section 3.2.1) to map draincurrent behavior. Meijer and coworkers [13] employed an
analytic VRH model (see Section 3.2.4) in order to explain the increasing inﬂuence of the
gatesource voltage. Both models can be implemented using a parallel combination of the re
spective unipolar devices, i.e. ptype and ntype Level1modeled devices for the Schmechel
approach as well as ptype and ntype VRHmodeled devices for the Meijer approach.
50 Chapter 3. OFET Modeling for Circuit Simulation
4.0u
3.0u
2.0u
1.0u
0.0u
−1.0u
−2.0u
−3.0u
−4.0u
−30 −20 −10 0 10 20 30
V
GS
= 20 V
0 V
20 V
0 V
5 V
15 V 10 V
V
DS
[V] →
I
D
[
A
]
→
Fig. 3.11: Schematic output characteristic for an ambipolar OFET with gatesource voltage
swept from 20 to 20 V.
3.3 Popular Procedures for Parameter Extraction
Users of transistor models are interested in simple extraction procedures for relevant model
parameters like threshold voltage or mobility. Numerous approaches can be used for extract
ing important parameters. In the following, frequently used procedures will be presented. A
more thorough analysis of suitable extraction procedures for the threshold voltage and other
important device parameters can be found e.g. in [27, 71, 72, 73, 74, 75].
3.3.1 Procedures for the Level1 Model
In this section, popular extraction methods for parameters of the Level1 model are listed.
These methods are also frequently used in the extraction of OFET parameters.
Threshold Voltage
The threshold voltage V
T
is one of the three parameters of the Level1 model. V
T
can be ex
tracted in numerous ways. In the following, some frequently cited methods will be presented.
3.3. Popular Procedures for Parameter Extraction 51
1. Extraction in the Linear Region
V
T
can be extracted by plotting the channel conductance
g
d
=
∂I
D
∂V
DS
≈ β(V
GS
−V
T
) (3.50)
for “small values” of V
DS
[76]. In literature on parameter extraction, voltages in the order of
10 mV are proposed for V
DS
[71]. Fig. 3.12 illustrates a simulated sample curve
3
for (3.50).
0.0
0 10 20 30 40 50
1.0u
2.0u
3.0u
4.0u
5.0u
6.0u
0.0
10.0u
20.0u
30.0u
40.0u
50.0u
60.0u
70.0u
80.0u
90.0u
0 10 20 30 40 50
slope β · V
DS
V
T
I
D
[
A
]
V
GS
[V]
V
T
slope β
g
d
[
A
/
V
]
V
GS
[V]
Fig. 3.12: Plot of channel conductance g
d
vs. V
GS
and drain current I
D
vs. V
GS
. Both plots
are for V
DS
= 10 mV. Data has been taken from a simulated device which operates according
to the Level1 equations.
Extrapolating the channel conductance curve to zero leads to the threshold voltage as g
d
=
0 A/V at V
GS
equal to V
T
in (3.50).
The drain current I
D
can also be used for extracting the threshold voltage V
T
without
the need to derive g
d
(also shown in Fig. 3.12). Again, V
T
is obtained by inspecting the
extrapolated intersection of I
D
with the V
GS
axis at zero current. The extrapolation is done
at the point of maximum slope, i.e. where the transconductance g
m
= ∂I
D
/∂V
GS
reaches its
maximum [71].
By extrapolating g
d
or I
D
in the linear region, series resistance at source and drain of the
device can be neglected as a drainsource voltage V
DS
≪ 1V is used. On the other hand, the
transfer characteristic of real OFET devices can considerably deviate fromthe idealistic Level
1 model. This generally complicates ﬁnding the most useful extrapolation point required in
the intercept calculations.
3
Model data: ntype device, K
P
= 1 nA/V
2
, V
T
= 8 V, λ = 1 · 10
−3
1/V, W/L = 200.
52 Chapter 3. OFET Modeling for Circuit Simulation
2. Extraction in the Saturation Region
In the saturation region, V
T
can be extracted by inspecting the transconductance g
m
. The
transconductance of a transistor denotes the variation of the output current resulting from a
variation of the input voltage and is calculated in the saturation region by
g
m
=
∂I
D
∂V
GS
V
DS
=const
= β(V
GS
−V
T
). (3.51)
In (3.51), the channellength modulation is neglected by setting λ = 0. Extrapolation of the
transconductance curve to zero leads to the threshold voltage V
T
[76].
Alternatively, the square root of the drain current can be used. From (3.3)
I
D
=
β
2
(V
GS
−V
T
), (3.52)
results when again neglecting the channellength modulation. The threshold voltage V
T
is
extracted by extrapolating
√
I
D
to zero [77]. Fig. 3.13 depicts the extraction procedure for the
g
m
and
√
I
D
method.
0.0
10.0u
20.0u
30.0u
40.0u
50.0u
60.0u
70.0u
80.0u
0 10 20 30 40 50
0.0
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
35.0m
40.0m
0 10 20 30 40 50
V
T
slope β
V
GS
[V]
g
m
[
A
/
V
]
V
T
slope
β
2
V
GS
[V]
√
I
D
[
√
A
]
Fig. 3.13: Plot of the transconductance g
m
vs. V
GS
and the square root of the transfer charac
teristic. Data have been taken from a simulated device with Level1 equations.
Mobility
With the threshold voltage established, other parameters like the chargecarrier mobility µ can
be analyzed. µ is an important parameter in the assessment of device performance and is often
used as a benchmark number (see e.g. [78]) in the comparison of different semiconductors.
In this section, extraction methods for the mobility are presented.
3.3. Popular Procedures for Parameter Extraction 53
1. Extraction in the Linear Region
From the slope of g
d
or I
D
in Fig. 3.12, the device conductance parameter β can be established
[77]. According to (3.5),
µ =
β
C
is
L
W
. (3.53)
It can also be calculated at individual points using the transconductance parameter
g
m
≈ βV
DS
(3.54)
in the linear region. Solving this equation with respect to β and inserting (3.53) [79] leads to
µ =
L
W
g
m
C
is
V
DS
. (3.55)
2. Extraction in the Saturation Region
In the saturation region, the slopes of the g
m
and
√
I
D
curves as shown in Fig. 3.13 can be
used for deriving the device conductance parameter β. (3.53) can then be employed in the
extraction of the mobility µ.
Alternatively, the mobility can be calculated at individual points. By inspecting the transcon
ductance g
m
from (3.51), the mobility can be calculated using (3.53) [80] with
µ = g
m
·
L
W
1
C
is
(V
GS
−V
T
)
. (3.56)
In [78], the mobility is calculated by deriving (3.52) with respect to the gatesource voltage
∂
√
I
D
∂V
GS
=
W
2L
µC
is
(3.57)
and solving for the mobility
µ = 2C
is
L
W
∂
√
I
D
∂V
GS
2
. (3.58)
In order to solve (3.56) V
T
has to be available while (3.58) and (3.55) are independent of
V
T
. Nevertheless, calculation of the derivatives is needed.
Channel length Modulation
The channel length modulation parameter λ can be extracted from the saturation region of the
output characteristics when the threshold voltage and the device conductance β are known.
54 Chapter 3. OFET Modeling for Circuit Simulation
The saturation current is given as
I
DSat
= β(V
GS
−V
T
)
2
(1 +λV
DS
). (3.59)
This relationship gives rise to two approaches. First, the channel conductance including
the channel length modulation
g
d
=
∂I
D
∂V
DS
= λβ(V
GS
−V
T
)
2
(3.60)
can be used for calculating the channellength modulation. This results in a value of
λ =
∂I
D
∂V
DS
β(V
GS
−V
T
)
2
. (3.61)
It can also be derived graphically by inspecting the slope of the channel conductance in the
saturation region with respect to the drainsource voltage V
DS
as shown in Fig. 3.14.
0.0
5.0u
10.0u
15.0u
20.0u
25.0u
30.0u
35.0u
40.0u
45.0u
0 10 30 40 50 20
V
DS
[V]
≈ 490 nA/V
g
d
[
A
/
V
]
Fig. 3.14: Extrapolation of λ from the channel conductance (g
d
) vs. drainsource voltage V
DS
plot.
Contact Resistance
The Level1 model does not include the inﬂuence of contact resistances between the transistor
channel and the source and drain electrodes. Nevertheless, the role of contact resistances in
transistor modeling is very important as will be shown in the following. Contact resistances
3.3. Popular Procedures for Parameter Extraction 55
can be modeled by adding series resistors to the transistor as shown in Fig. 3.15.
G
M V
DS
D
DP
SP
R
S
R
D
V
GS
S
Fig. 3.15: Elementary Level1 transistor with contact resistors at drain and source.
The schematic in Fig. 3.15 contains a transistor M. The device has two series resistors
R
S
and R
D
which account for the contact resistance at the source and drain electrodes to the
channel. Both resistors affect the transistor voltages in a way such that the actual gatesource
voltage V
′
GS
between nodes G and SP is
V
′
GS
= V
GS
−I
D
· R
S
(3.62)
and the actual drainsource voltage V
′
DS
between nodes DP and SP is
V
′
DS
= V
DS
−I
D
· (R
S
+ R
D
). (3.63)
In the following, the inﬂuence of the series resistors will be analyzed. First, R
D
shall be
neglected (R
D
= 0 Ω) and for simpliﬁed calculations, λ shall be dropped (λ = 0), too. The
drain current in the saturation region can then be expressed by inserting (3.62) and (3.5) into
(3.3):
I
D
=
β
2
(V
′
GS
−V
T
)
2
=
β
2
(V
GS
−I
D
· R
S
−V
T
)
2
. (3.64)
The solution for this equation is given by [81]
I
D
=
1 + 2βR
S
V
GST
−
√
1 + 4βR
S
V
GST
2βR
2
S
, (3.65)
with V
GST
= V
GS
− V
T
. The source resistance R
S
reduces the effective device conductance
56 Chapter 3. OFET Modeling for Circuit Simulation
parameter β. Fig. 3.16 illustrates this behavior.
40 V
20 V
30 V
0.0
1.0m
1.2m
1.4m
1.6m
1.8m
2.0m
0 10 20 30 40 50
0.8m
0.6m
0.4m
0.2m
V
GS
= 50 V
V
DS
[V]
I
D
[
A
]
Fig. 3.16: Effect of the source resistance on the drain current: simulated curves for a transistor
with R
S
(dashed lines) and the same transistor without the contact resistance (solid lines).
If only R
D
is considered (R
S
= 0 Ω), the drain current in the saturation region does not
change but the boundary between the linear and saturation region shifts as demonstrated by
the following equation (V
Sat
= effective saturation voltage, V
′
Sat
= saturation voltage between
DP and SP):
V
Sat
= V
′
Sat
+ β · V
2
GST
· R
D
V
GST
=V
′
Sat
= V
GST
+ βV
2
GST
· R
D
. (3.66)
An effective threshold voltage V
∗
T
can be derived from (3.66) by noting that
V
∗
T
= V
T
−βR
D
V
2
GST
. (3.67)
(3.67) shows that the effective threshold voltage V
∗
T
depends on V
GST
by a squarelaw
relationship for R
S
= 0 Ω. Its inﬂuence on the drain current is shown in Fig. 3.17.
If both series resistors are active (R
S
> 0 Ω and R
D
> 0 Ω) and V
′
GST
= V
′
GS
−V
T
then
V
Sat
= V
′
Sat
+ I
DSat
· (R
S
+ R
D
) = V
′
GST
+ β(R
S
+ R
D
)V
′2
GST
. (3.68)
The above discussion shows that the contact resistance degrades device performance by
reducing the effective drainsource and gatesource voltages. There exist various methods of
determining the contact resistance. In the following, three frequently used methods will be
3.3. Popular Procedures for Parameter Extraction 57
40 V
30 V
20 V
0.0
0.6m
1.0m
1.2m
1.4m
1.6m
1.8m
2.0m
0 10 20 30 40 50
0.8m
0.4m
0.2m
V
GS
= 50 V
V
DS
[V]
I
D
[
A
]
Fig. 3.17: Effect of drain resistance on the drain current: simulated curves for a transistor with
R
D
(dashed lines) and the same transistor without the contact resistance (solid lines).
presented.
1. Determination by Channel Length Variation
Using a systematic variation of the channel length, the resistance between source and drain
can be measured in the linear region as
R
M
=
V
DS
I
D
=
L
W
1
µC
is
(V
GS
−V
T
)
+ R
c
= G
0
· L + R
c
. (3.69)
Here, R
c
is the contact resistance (R
C
= R
S
+ R
D
) while G
0
is the contribution of the
transistor independent of its channel length. The latter is deﬁned as
G
0
=
1
W · µC
is
(V
GS
−V
T
)
. (3.70)
The contact resistance can then be established by measuring the draincurrent characteris
tics for transistor devices with identical transistor widths but varying lengths and extrapolating
R
c
from the R
M
vs. L plot to L = 0 µm. Fig. 3.18 shows a sample curve for the approach.
2. Determination with Potential Proﬁling
This method is directly applicable to transistors with a bottomgate bottomcontact structure
where the semiconductor is deposited last and the potential proﬁle along the channel can be
58 Chapter 3. OFET Modeling for Circuit Simulation
30 V
40 V
50 V
0.0
1.0M
1.5M
2.0M
200.0u 150.0u 100.0u 50.0u 0.0
0.5M
R
C
V
GS
= 20 V
V
DS
= 1 V
L [m]
R
M
[
Ω
]
Fig. 3.18: Measured resistance (R
M
) vs. channel length (L) of devices with ﬁxed channel
width: squares are the values according to (3.69) and solid lines are obtained from SPICE
simulations at V
DS
= 1 V.
measured by use of potential probes ([44, 82]). Alternatively, sampling electrodes similar
to fourpoint probes [83] have to be present in the channel in order to measure the channel
potential at predeﬁned locations. A sample proﬁle for a device operating in the linear region
is depicted in Fig. 3.19. On the y axis, the potential proﬁle is plotted with x being the position
along the channel. At the source contact, x = 0 µm and at the drain contact, x = L. L is the
length of the transistor channel. The value R
S
for the source contact resistance and the value
R
D
for the drain contact resistances can be readily extracted from the potential drop at source
and drain.
3. Determination with the SJ method
The idea of the SJ method (named after its inventors Suciu and Johnston [84]) is to assume
that I
D
can be modeled in the linear region by
I
D
= β(V
GS
−V
T
)V
′
DS
= β(V
GS
−V
T
)(V
DS
−I
D
· R
C
), (3.71)
with V
′
DS
being the actual drainsource voltage at the transistor and R
C
the sum of source and
drain resistance (R
S
+ R
D
). The explicit form of (3.71) is
I
D
=
β(V
GS
−V
T
)
1 +R
C
β(V
GS
−V
T
)
V
DS
. (3.72)
3.3. Popular Procedures for Parameter Extraction 59
position
0 L
source drain
e
l
e
c
t
r
i
c
p
o
t
e
n
t
i
a
l
y
x
R
S
· I
D
R
D
· I
D
Fig. 3.19: Schematic potential proﬁle along the channel of a bottomgate bottomcontact tran
sistor (adaption from [82]).
(3.72) can be rearranged to yield
x
I
D
/V
DS
=
1 +R
C
β · x
β
≡ E(x) = E
0
+ ∆Ex, (3.73)
where x = V
GS
−V
T
and I
D
/V
DS
is the reciprocal of the resistance R
M
which can be measured
by taking I
D
from a real device. (3.73) is equivalent to
x · R
M
= E
0
+ ∆Ex, (3.74)
with E
0
= 1/β and ∆E = R
C
. Fig. 3.20 illustrates the resulting curve E(x).
Suciu and Johnston emphasize that their approach is an analytical extraction procedure
which does not need any optimization procedures. Although the inﬂuence of the source re
sistance R
S
on the gatesource voltage V
GS
is neglected in the calculations, the error can be
minimized by taking the measurements at small I
D
values.
3.3.2 Extraction Procedures for TFT Models
The most important parameter in the model for PsiTFTs is the threshold voltage from which
the other parameters depend in an extraction procedure. Jacunski et al. [47] give two practical
deﬁnitions of the threshold voltage:
1. The voltage above which the drain current no longer exponentially depends on V
GS
.
2. The voltage above which a MOSlike drain current expression can be used.
60 Chapter 3. OFET Modeling for Circuit Simulation
0.0
2.0M
4.0M
6.0M
8.0M
10.0M
12.0M
14.0M
50.0 40.0 30.0 20.0 10.0 0.0
V
DS
= 1 V
∆E = R
C
E
0
=
1
β
V
GS
[V]
E
(
x
)
Fig. 3.20: Plot of the extraction function E(x) for the contact resistance.
Threshold voltages obtained by the ﬁrst deﬁnition can considerably differ from voltages de
rived with the other solution as there is a broad transition range from subthreshold operation in
the ﬁrst deﬁnition to accumulation operation from the second deﬁnition. The second method
was also adopted by the IEEE standard on the characterization of OFET devices [48]. This
standard deﬁnes the threshold voltage as the minimum gate voltage required to induce the
channel. The value is extracted from I
DS
vs. V
GS
measurements.
The deﬁnitions in [47] demonstrate the difﬁculties in exactly describing the threshold volt
age. In the case of conventional silicon MOSFETs, the threshold voltage is deﬁned as the
gatesource voltage where the strong inversion layer starts to form. For inorganic thinﬁlm
transistors, an additional onvoltage V
ON
was introduced [41]. V
ON
is found by inspecting
the log I
D
vs. V
GS
curve at low drainsource voltages. The on voltage is the point where
log I
D
reaches its minimum and becomes linear. According to [41], the physical meaning of
V
ON
in polycrystalline silicon TFTs is that at V
GS
= V
ON
the transistor channel starts form
ing. However, induced carriers are still trapped in bandgap states. At a gate bias equal to
the threshold voltage V
T
, induced charges begin to appear as mobile carriers in the channel.
Fig. 3.21 illustrates the differences between V
ON
and V
T
.
[62, 85] simply deﬁne V
ON
as the switchon voltage. This voltage is the value of V
GS
where the lowest drain current is measured. A similar deﬁnition is used in the RPI model.
In the grainboundary model, the mobility µ depends on the gatesource voltage (see (3.8)
and (3.9)). Therefore, obtaining the threshold voltage V
T
by plotting
√
I
D
vs. V
GS
as usually
applied in literature on parameter extraction leads to incorrect values. Extracted threshold
voltages tend to be more favorable than the true parameter. Fig. 3.22 illustrates this behavior.
3.3. Popular Procedures for Parameter Extraction 61
100.0f
1.0p
10.0p
100.0p
1.0n
10.0n
100.0n
1.0u
10.0u
100.0u
−4 −2 0 2 4 6 8 10
0.0
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
35.0m
V
T
V
ON
I
D
[
A
]
V
GS
[V]
3
√
I
D
[
3
√
A
]
Fig. 3.21: Deﬁnition of V
ON
and V
T
.
The plot shows log I
D
and
√
I
D
of a simulated transistor. In the simulation, I
D
∼ (V
GS
−V
T
)
3
in saturation and V
T
= 1 V was used. The parameter set of the device is identical to the one
used in Fig. 3.21. An extraction with squareroot plotting leads to the incorrect threshold
voltage of V
T
≈ 3 V.
100.0f
1.0p
10.0p
100.0p
1.0n
10.0n
100.0n
1.0u
10.0u
100.0u
−4 −2 0 2 4 6 8 10
0.0
1.0m
2.0m
3.0m
4.0m
5.0m
6.0m
7.0m
V
T
V
GS
[V]
I
D
[
A
]
√
I
D
[
√
A
]
Fig. 3.22: Extraction of the threshold voltage by use of the
√
I
D
vs. V
GS
method on a transistor
with I
D
∼ (V
GS
−V
T
)
3
in the saturation region.
62 Chapter 3. OFET Modeling for Circuit Simulation
The preceding discussion shows that knowing the power factor α in the current expression
I
D
∼ (V
GS
−V
T
)
α
for the saturation current is necessary in order to correctly extract the
threshold voltage V
T
.
The power factor α can e.g. be derived by plotting log I
D
vs. log (V
GS
− V
T
). The slope
of the resulting line yields α. In PsiTFT modeling, α = m
µ
+2 and should not be intermixed
with α
sat
. Here m
µ
is the mobility parameter of the device in (3.9). Extraction of α with
loglog plotting requires knowledge about the exact value of V
T
. It can therefore not be used
for extracting α and then the threshold voltage V
T
. Variations about the exact V
T
value lead
to bent curves in the log I
D
vs. log (V
GS
−V
T
).
Fig. 3.23 shows two log I
D
vs. log (V
GS
−V
∗
T
) plots for one single device where threshold
voltages of V
∗
T
= 1 V and of 1 V have been assumed. The actual I
D
curve has a threshold
voltage of V
T
= 1 V and a power factor α = 3. The left plot shows a curve with a slope of
three above the x value of approximately 0.3 and a steeper slope below that value. The latter is
due to the interaction between the abovethreshold and the subthreshold current. The second
plot has been calculated with an anticipated threshold voltage of 1 V and does not show a
linear shape. This result demonstrates that the anticipated threshold voltage affects extraction
of the power factor α.
−8.0
−7.5
−7.0
−6.5
−6.0
−5.5
−5.0
−4.5
−4.0
−3.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4
log(V
GS
−V
∗
T
)
l
o
g
I
D
V
∗
T
= 1 V
V
∗
T
= −1 V
Fig. 3.23: Extraction of the power factor α for I
D
∼ (V
GS
−V
T
)
α
. The V
∗
T
values are used in
the x axis calculations.
3.3. Popular Procedures for Parameter Extraction 63
Uniﬁed Extraction Method
An analytic approach for both polycrystalline and amorphous TFT transistors called Uniﬁed
Extraction Method (UEM) has been proposed by Estrada et al. in [56]. The method was
originally developed for aSi TFTs [57] and deﬁnes an extraction function H such that
H(V
GS
) =
V
G
0
I
DSat
(V
GS
)dV
GS
I
DSat
≈
V
G
−V
T
α + 1
, (3.75)
Here, I
DSat
(V
GS
) = K(V
GS
− V
T
)
α
, K is a conductance parameter, and α is an empirical
power factor. An ntype transistor and V
G
> V
T
is assumed in the following discussions.
The procedure consists of the following steps:
1. Compute H(V
GS
) from measured I
DSat
(V
GS
) characteristics.
2. Fit a line to H(V
GS
) and extract values for α and V
T
from the slope and the intercept
point of H with the V
GS
axis.
3. Calculate the conductance parameter K according to K = I
DSat
/(V
GS
−V
T
)
α
.
The method can also be extended to polycrystalline silicon TFTs (PsiTFT) by translating
the parameters used in (3.75) to parameters of PsiTFTs. Details of the process are given in
[56]. The method is also useful in the calculation of the channellength modulation λ and
series resistance R = R
S
+ R
D
(R
S
/R
D
is the source/drainside series resistance). In [46],
UEM
4
has also been used for extracting parameters for pentacenebased devices in bottom
gate conﬁguration. The method also accounts for constant and diodelike contact resistances.
Details about the extraction scheme can be found in [46].
An alternate way of correctly deriving the threshold voltage and power factor is demon
strated in Section 4.3.2.
3.3.3 Parameter Fitting
As an alternative to an analytic extraction, ﬁtting procedures can be used for deriving model
parameters. Such schemes employ an optimization engine to ﬁnd a feasible set of parameters
to describe given output characteristics. Usually, the leastsquares sum of the difference be
tween model prediction and original data is used for measuring the quality of a ﬁt [25, 86]. In
contrast to the graphicsbased and analytic procedures described earlier, parameter ﬁtting can
be applied to any model with a valid analytical description. However, the ﬁtting engine needs
initial values for the parameters to extract. Another drawback of parameter ﬁtting is that the
4
Later in [46], UEM was renamed to Uniﬁed Model and parameter Extraction Method (UMEM).
64 Chapter 3. OFET Modeling for Circuit Simulation
solver could ﬁnd a local minimum or a physically incorrect set of parameters. The interested
reader is referred e.g. to [87] for a discussion of optimization algorithms.
Discussion of Parameter Fitting
Analytical extraction generally requires special measurement setups and knowledge on feasi
ble models to use in order to derive model parameters. Parameter ﬁtting does not depend on
such setups and is more general. However, extraction problems often consist of many param
eters to ﬁnd. This situation complicates parameter ﬁtting as extraction engines often get stuck
at local minima in multidimensional ﬁtting problems. Moreover, the extraction process needs
a sensible starting point for the extraction. Nevertheless, a numerical solver is far easier to
implement in computer software than an analytical or graphical extraction scheme.
3.4 Automation of Modeling
For the users of circuit simulation in the optimization of OFET devices, automatic parameter
extraction is important. Each time a new device generation is introduced, transistor models
have to be generated so that automation of the modeling process is desirable. Automation
takes place in the form of dedicated modeling tools and should include one or more of the
following features:
2 Data Management – Largescale measurement series need to be managed.
⊲ From the measurement sets, statistically meaningful parameters need to be ex
tracted.
⊲ Additional data describing the actual measurements must accompany the measure
ment data in order to facilitate backtracking of measurement data and extraction
results. This kind of data includes e.g. the name of the sample from which mea
surements were taken, geometrical dimensions of the devices, date of measure
ment, operator, etc.
2 Selection tools – The most appropriate modeling approaches for given output character
istics need to be identiﬁed. This requires tools which aid in selecting the most suitable
model for given I
D
V
GS
characteristics. For example, the V
Sat
method (which will be
presented in Chapter 4) can assist in selecting appropriate model types by plotting the
V
GS
dependence of the principal parameters K
P
, V
T
, and λ.
2 Availability of different modeling approaches – Modeling tools should provide different
approaches for modeling so to allow users to try out different model types and extrac
tion schemes. This can be handled by providing generic modeling interfaces where
3.4. Automation of Modeling 65
dedicated model generators can be linked in. These generators can e.g. contain sophis
ticated graphical user interfaces or capabilities for data analysis.
2 Collaboration with Circuit Characterization Tools – The models are primarily used in
circuit simulation of reasonable circuits like logic gates. Therefore, it is desirable to
embed modeling tools in the circuit characterization environment. In this way, time
consuming integration of model data into circuit simulations can be avoided.
3.4.1 Existing Tools
There are numerous tools for extracting parameters of transistor models. The degree of au
tomation in these tools ranges from providing an input mask where graphical the extraction of
the parameters can be done by the users to fully automated extraction procedures.
Generalpurpose extractors like the commercial tool Synopsys Aurora [88] consist of a
conﬁgurable solver and provide a scriptbased computation engine as well as a graphical user
interface. In the case of Aurora, parameters are extracted by curve ﬁtting with a Levenberg
Marquardt solver using constraints. The tool allows the users to carry out the extraction in
a series of steps. In each step, a set of parameters to optimize and default values for other
parameters can be deﬁned. Setups like the following are possible: A coarse version of the
threshold voltage V
T
is extracted in the ﬁrst extraction step using I
D
−V
GS
measurements and
a sensible range for V
T
. In the next step, the device mobility is extracted. Finally, a general
ﬁt uses previously extracted parameter values as starting points and centers the parameters at
the minimum error between model output and measured curves. Tools like Aurora do not pro
vide datamanagement capabilities or direct links to circuit characterization tools. Moreover,
appropriate models have to be selected by inspecting the error between modeling results and
original data.
Some SPICE simulators (e.g. Synopsys StarHspice [26] or Tanner TSpice [68]) include
conﬁgurable optimizers which can be used for ﬁtting the curves. These optimizers are con
trolled by use of special statements in the textual netlists. Tools like Cadence/OrCAD PSpice
[89] or Synopsys SaberDeveloper include graphical frontends which can be used for a graph
ical ﬁt of the curves. The simulators are directly linked to circuit characterization tools and
carry out the actual simulations needed in the characterization process. However, they do not
provide data management or convenient selection of appropriate models.
More specialized extractor tools like AIMEXTRACT [90] provide graphical user inter
faces and external ﬁt programs for dedicated models. These external ﬁt programs are con
ﬁgured with text ﬁles containing references to the required measurement data and parameter
setups. In AIMEXTRACT, the parameters are extracted by an undisclosed multistep plan.
The drawback of the extraction plan is that the ﬁtting results depend on the input parameters.
66 Chapter 3. OFET Modeling for Circuit Simulation
Experiments done by the author of this work revealed that e.g. the initially given thresh
old voltage is used in calculations within subsequent parameter extractions inside the model
extractor for PsiTFT devices. The tool is highly specialized because it can only extract pa
rameters of certain models. Moreover, it does not provide data management or assistance in
selecting appropriate models.
The commercial package Agilent ICCAP [91] provides a framework for model extrac
tion. The tool centers on the management of device and circuit characteristics and provides
modeling, management as well as control of measurement instruments, and simulation facili
ties. All processes can be automated using a builtin control language. Modeling complexity
ranges from the extraction of parameters of primitive models to models described by SPICE
netlists. ICCAP collaborates with external simulators in order to test the accuracy of ex
tracted model parameters or to characterize a circuit using circuit simulations. The simulators
are integrated via an open simulator interface. ICCAP already includes a large set of models
and specialized extraction procedures for the derivation of their parameters.
3.4.2 Discussion
In summary, tools for circuitlevel transistor modeling are either very general or specialize on
certain models. The general tools can be conﬁgured very ﬂexibly but specialized modeling
tools provide more convenient extraction schemes. With the exception of ICCAP, none of the
abovementioned tools provides the analysis capabilities needed for the extraction schemes
presented in Section 3.3. Conversely, the commercial tool ICCAP provides both very gen
eral and highly specialized extraction schemes in one software package. However, all tools
investigated in this section lack the treatment of dedicated OFET models or sophisticated data
management.
3.5 Chapter Summary
The following aspects of OFET modeling were discussed in this chapter:
2 Different chargetransport mechanisms in OFETs are currently under debate. Many
issues need to be resolved in order to fully understand the inner workings of organic
transistors. Modeling is complicated by the fact that different OFET technologies exist,
where the availability of many materials and manufacturing methods leads to various
effects which have to be accounted for.
2 Owing to the early stage in the process of understanding charge transport in organic
semiconductors, many modeling approaches for OFETs are based on wellknown mod
els derived for more traditional semiconductor technologies like crystalline silicon or
3.5. Chapter Summary 67
thinﬁlm transistors. Other models sacriﬁce a physical basis in favor of accurate mod
eling, e.g. for simulation of analog circuits. One model with a true OFETrelated phys
ical basis is the model of variable range hopping (VRH). Modeling of capacitances and
stress effects is also still in the beginning. Only one model presented in this chapter
honors stress effects by introducing an RC network in order to introduce hysteresis in
the switching behavior of transistors.
2 The model quality chart (MQC) was deﬁned in this chapter in order to allow ratings and
comparisons of the various models with respect to accuracy, modeling of capacitances,
compactness, parameter extraction and stress effects. OFET models were then analyzed
by use of MQC tables. Table 3.12 lists the results obtained by the discussion of these
models.
Table 3.12: MQC values for models presented in this work.
Requirement Level1 PsiTFT aSi TFT VRH Table Dresden
& contacts
Accuracy bad to good good good good good
medium
Capacitance – – – good good –
modeling
Compactness good good good good bad bad
Parameter good medium bad medium not medium
extraction needed
Stress Effects – – – – – medium
2 Accuracy in Table 3.12 has been rated according to the data sets used for developing the
respective models. As will be shown in Section 4.3.5 and Section 4.3.6, models have
their peculiar shortcomings when dealing with different device technologies. Therefore,
it is not possible to select one modeling approach equally useful for all types of devices.
Extraction methods are normally centered on ﬁnding the bestﬁtting parameters for a
given set of parameters and a given model. Whether the model matches the data can
only be seen at the end of the extraction procedure. From the user’s point of view, it
would be desirable to have this information before any lengthy extractions are carried
out. In this respect, the traditional question which set of parameters best maps measured
curves for a given model translates into the question which model potentially maps the
given curves.
68 Chapter 3. OFET Modeling for Circuit Simulation
2 There exist many tools and measurement procedures for deriving parameters of popular
models. However, these tools require skilled users and appropriate data sets. In order to
provide maximum use, a generic framework for analyzing the performance of OFETs
in logic circuits should assist users in the derivation of appropriate model sets. Here,
features like data management, selection of bestﬁtting models, implementation of user
friendly ﬁtting approaches, and collaboration with the circuit characterization part of the
framework are important. Existing extraction tools do not provide these characteristics.
The issues of extracting reasonable threshold voltages and selecting proper models will
be addressed in the following chapter, where a novel modeling and analysis tool named V
Sat
method is discussed. Chapter 6 then contains a description of a computerized methodology
for ﬂexible transistor modeling and characterization of OFETbased logic circuits.
69
Chapter 4
V
Sat
Method
In this chapter, a novel approach to extracting model parameters of transistors is detailed. The
method is based on two observations made by the author of this work.
The ﬁrst observation is that most models presented in Section 3.2 are variations of the
Level1 model. In these models, constant parameters are replaced by variable parameters,
which e.g. depend on the gatesource voltage. The idea of the novel extraction method is to
decompose a measured set of output characteristics I
D
vs. V
DS
into individual output curves,
one for each given V
GS
value. The basic parameters V
T
, K
P
, and λ of the Level1 model are
then calculated for each of these curves. By plotting the extracted parameters vs. V
GS
, the
bestﬁtting model type can be identiﬁed because the different models have characteristic V
GS
dependences of their parameters.
The second observation is that the threedimensional problem of extracting the basic pa
rameters V
T
, K
P
, and λ for a single output characteristic can be reduced to a onedimensional
problem of ﬁnding V
T
and calculating K
P
and λ from it. V
T
can be determined by searching
the transition point between the linear and the saturation region, i.e. the saturation voltage
V
Sat
, and calculating V
T
from the relationship V
Sat
= V
GS
−V
T
. Owing to the role of V
Sat
in
the extraction process, the extraction method has been named V
Sat
method.
The extraction procedure and its application in transistor modeling are detailed in the
following sections. First, the extraction scheme is described. Then, two transistor models are
presented which directly integrate the V
Sat
method. Finally, experimental results showing the
application of the extraction procedure and novel modeling techniques are discussed.
70 Chapter 4. V
Sat
Method
4.1 Extraction based on V
Sat
Method
Automatic extraction of model parameters with the V
Sat
method is based on the following
assumptions:
2 The model parameters depend on V
GS
.
2 Individual I
D
vs. V
DS
curves with constant V
GS
can be covered by Level1 modeling
from (3.1) to (3.3).
2 Appropriate models for given characteristics can be found by plotting the basic Level1
parameters K
P
, V
T
, and λ vs. V
GS
The V
Sat
method relies on the determination of the saturation voltage V
Sat
, i.e. the drain
source voltage of an I
D
vs. V
DS
curve where the transition from the linear to the saturation
region takes place. V
Sat
can be determined by varying a guess of it in the available V
DS
range,
calculating V
T
, K
P
, an λ from the guessed V
Sat
, and observing the meansquare error between
the resulting Level1 model and the measurement data or by employing a onedimensional
optimization routine.
The values necessary for calculating the model parameters are shown in Fig. 4.1. They
are obtained as follows: From V
Sat
and the respective drain current I
Dsat
, the maximum drain
voltage V
DMax
and the respective drain current I
DMax
, the parameters K
P
and λ can be de
rived using the following equations.
V
T
= V
GS
−V
Sat
, (4.1)
f =
I
DMax
−I
DSat
V
DMax
−V
Sat
, (4.2)
I
DS0
 = I
DSat
 −f · V
Sat
, (4.3)
K
P
= 2I
DS0
/V
2
Sat
, (4.4)
λ =
f
I
DS0

. (4.5)
Here, f is the slope of I
D
between V
Sat
and V
DMax
, all other parameters have their usual
meaning. Absolute values are used so that positive values are guaranteed for both ntype and
ptype transistors. f can be calculated from the I
D
values at V
DMax
and V
Sat
. Alternatively,
f can also be derived by calculating the linear regression of the I
D
points between V
Sat
and
V
DMax
. The latter procedure is more robust against measurement noise as more points are used
in the calculation of the slope. I
DS0
is the drain current in the saturation region with λ = 0.
It can be used to calculate K
P
by exploiting the relationship I
DS0
=
1
2
W
L
K
P
V
2
Sat
. λ can be
4.1. Extraction based on V
Sat
Method 71
derived from I
DMax
−I
DSat
=
1
2
W
L
K
P
V
2
Sat
· λ · (V
DMax
−V
Sat
) which leads to f = λ· I
DS0
.
V
Sat
I
DS0
I
DSat
slope f
I
′
D
I
D
V
DS
I
DMax
V
DMax
Fig. 4.1: Important points on the I
D
vs. V
DS
curve for calculating model parameters according
to the V
Sat
method. The dashed curve I
′
D
denotes the drain current for λ = 0. V
GS
is constant
for the curve.
Fig. 4.2 shows a plot of the meansquare error vs. the guessed saturation voltage V
Sat
of two different simulations
1
. In the underlying experiment, drain currents were simulated
with a V
DS
increment of 0.1 V and 1.0 V. Then, V
Sat
was guessed by varying the unknown
value between 3 V and 10 V with a step size of 0.1 V. The meansquare error was calculated
according to
¯ ε =
1
n
n
¸
i
[I
D,m
(V
DS,i
) −I
D,s
(V
DS,i
, V
Sat
)]
2
. (4.6)
Here, n is the total amount of measured points, I
D,m
is the measured or interpolated drain
current (index m for “measured”). I
D,s
is the drain current according to the Level1 model
and the parameters extracted with the V
Sat
method (index s for “simulated”).
Both curves show minima at V
Sat
≈ 8.4 V. The curve labeled “original data with V
DS
increment of 0.1 V” is smoother. The other curve has local minima which can cause an
optimizer to get stuck at these points (e.g. V
Sat
= 6 V). The plot also shows that the resulting
parameter accuracy depends on the sampling density of the measured I
D
points. Moreover,
the presence of local minima complicates the application of many numerical optimization
methods. However, the optimal solution can be found by the abovementioned procedure of
varying V
Sat
in a ﬁxed interval in steps of e.g. 0.1 V and selecting the V
Sat
value for the
minimum meansquare error ¯ ε.
1
Level1 model, simulation data: β=10 nA/V
2
, V
T
= −6.4 V, λ = 0.01 1/V, V
GS
= 2 V.
72 Chapter 4. V
Sat
Method
0.0
0.5
1.0
2.0
2.5
3.0
3.5
3 4 5 6 7 8 9 10
4.0
1.5
guessed V
sat
[V]
× 10
−15
¯ε
[
A
2
]
original data with V
DS
increment of 1.0 V
original data with V
DS
increment of 0.1 V
Fig. 4.2: Dependence of the modeling error on the measurement grid.
The reader is referred to Section 4.3 for a demonstration of the V
Sat
method with measured
output characteristics.
Discussion
The V
Sat
method approaches modeling in a mixture of ﬁtting and analytical methods. First,
the threshold voltage V
T
is derived by a numerical extraction of the saturation point of an I
D
vs. V
DS
plot. Then, the other parameters K
P
and λ are analytically calculated from V
T
. This
approach reduces the threedimensional ﬁtting problem to a onedimensional search which
can be carried out fully automatically.
Application of the V
Sat
method entails using the whole range of drainsource voltages
V
DS
. Therefore, effects introduced by series resistances affect the extracted parameters, e.g.
reduce effective voltages due to voltage drops across the series resistors. Existing methods
of extracting V
T
therefore often resort to I
D
vs. V
GS
curves with small drainsource voltages
V
DS
below 1 V.
The V
Sat
method generates intermediate parameters used to identify appropriate modeling
approaches. For example, the Level1 model yields parameters which are independent of
V
GS
while the threshold voltage V
T
in the PsiTFT model linearly depends on V
GS
and on
a conductance factor K
P
with a powerlaw dependence (see Section 4.3.2 for more details).
By plotting them against V
GS
, the parameters aid in the selection of appropriate modeling
approaches because the parameter curves in the individual models have characteristic shapes
4.2. Modeling based on V
Sat
Method 73
with respect to V
GS
.
4.2 Modeling based on V
Sat
Method
The V
Sat
method can be used as the ﬁrst step of a twostep extraction procedure similar to the
intermediate model approach developed by Kondo and coworkers to extract parameters of
MOSFET transistors [92].
In the intermediate model approach, model parameters are extracted by a twostep con
cept. In the ﬁrst step, intermediate parameters are extracted from measured IV data. In
a second step, these intermediate parameters are transformed into parameters of the target
model. Splitting the extraction process into two steps allows deviceindependent extraction
routines for the intermediate parameters. Mapping the intermediate parameters to the parame
ters of the target model is then devicedependent. Kondo and colleagues emphasize that once
an acceptably accurate intermediate model has been established, model designers only need
to derive a mapping procedure for the parameters of the target model.
The original approach by Kondo and colleagues is used to extract one set of parameters
for a complete set of output characteristics. It works with the subthreshold and linear region.
Conversely, the V
Sat
method is used to derive distinct sets of Level1 parameters for individual
abovethreshold curves of I
D
vs. V
DS
measured at constant V
GS
values. The distinct parameter
sets are then related to extract a common parameter set for all measured V
DS
and V
GS
values.
In the following, two modeling approaches based on data derived by the V
Sat
method will
be discussed: a tablebased model and an analytical model called Linvar model. The latter
model utilizes the concept of intermediate parameters.
4.2.1 V
Sat
Type TableBased Model
The V
GS
dependent parameters V
T
, K
P
, and λ can be directly recorded in a table generated
by the V
Sat
method. During circuit simulation, the model parameters are then taken from this
table or are interpolated / extrapolated from existing values. A table model has been written
in this work in XSPICE [93]. The reader is referred to Section 6.3 for a demonstration of
its application. This type of model is easy to implement and does not require sophisticated
compression equations like the model in [31]. Moreover, the parameter table does not store
measurement values like other modeling approaches do. Instead, the V
GS
dependent param
eters of the Level1 model are tabulated vs. the gatesource voltage. With this approach,
parameters of the model can be changed without the need to store a new set of output char
acteristics for the table model. On the other hand, the table model only works correctly if the
individual I/V curves can be approximated by Level1 modeling. This is not possible when
74 Chapter 4. V
Sat
Method
e.g. diodelike contact effects are present.
Discussion
Table 4.1 provides ratings for the tablebased model with respect to the model quality chart
presented in Section 3.1. Accuracy was rated as good because the model can map output
characteristics when the individual curves are Level1shaped. Modeling of transistor capac
itances or stress effects is not included. Compactness has been rated as bad because many
values are needed. In the parameter extraction, only the V
Sat
method is necessary. Therefore,
the parameter extraction has been rated as good.
Table 4.1: MQC for V
Sat
type tablebased model.
Requirement Rating
Accuracy good
Capacitance Modeling not included
Compactness bad
Parameter Extraction good
Stress Effects not included
4.2.2 Linvar Model
The V
GS
dependence of the extracted parameters can be approximated by analytical equa
tions. The Linvar model has been developed in this work to provide such a relationship. The
model parameters are assumed to be variables linearly depending on V
GS
. Hence the name
Linvar model is used. Other dependences (polynomial, exponential) were analyzed in [94],
but these functions add more parameters and therefore reduce the compactness of the model.
Experimental studies on OFETs based on poly(3hexyl)thiophene (P3HT) (see Section 4.3.2)
showed that a linear dependence represents a good compromise between compactness (num
ber of parameters) and accuracy (meansquare error with respect to measurements) of the
model.
Model Equations
In the Linvar model, the V
GS
dependent parameter sets are mapped to the following functions:
4.2. Modeling based on V
Sat
Method 75
K
P
(V
GS
) = KP
0
+ f
k
· V
GS
, (4.7)
V
T
(V
GS
) = V
T0
+ f
T
· V
GS
, (4.8)
λ(V
GS
) = λ
0
+ f
λ
· V
GS
. (4.9)
Assuming ntype devices for the discussion, the equations of the Linvar model are:
1. Cutoff region with V
GS
< V
T
:
I
D
= 0. (4.10)
2. Linear region with 0 < V
DS
< V
GS
−V
T
(V
GS
):
I
D
= K
P
(V
GS
) ·
W
L
V
GS
−V
T
(V
GS
) −
V
DS
2
V
DS
· [1 +λ(V
GS
)V
DS
]. (4.11)
3. Saturation region with 0 V < V
GS
−V
T
(V
GS
) < V
DS
:
I
D
=
1
2
K
P
(V
GS
) ·
W
L
[V
GS
−V
T
(V
GS
)]
2
· [1 +λ(V
GS
)V
DS
]. (4.12)
In order to map the existence of a subthreshold or bulk current, a resistor R
par
parallel
to the transistor channel is added between source and drain. The resistance value can be
determined using the difference between a measured I
D
point for zero V
GS
and the model
prediction without R
par
. The resistor can be normalized to a widthindependent contribution
using
R
′
par
= R
par
· W
ref
, (4.13)
where W
ref
is the width of the modeled device. The drainsource current then becomes
I
DS
= I
D
+ V
DS
· R
′
par
/W. (4.14)
Discussion
The main advantage of the Linvar model is its simpliﬁed parameter extraction scheme. The
procedure is especially suitable for automatic extraction. On the other hand, the Linvar model
simply represents a ﬁtting model. Therefore, the parameters do not directly reﬂect process or
material properties. The model is restricted to devices where the parameters show linear de
pendence on V
GS
. The extraction scheme does not take contact resistances at drain and source
into account. These elements have to be derived beforehand in order to extract meaningful
values for K
P
, λ and V
T
.
76 Chapter 4. V
Sat
Method
In Table 4.2, a rating of the Linvar model with respect to the model quality chart pre
sented in Section 3.1 is shown. Accuracy was rated as medium as the model only matches
a restricted set of device structures. In particular, only devices with linear V
GS
dependence
of the parameters are mapped. Capacitance modeling or stress effects are not included in the
modeling. Although the model relies only on a small set of parameters, compactness was
rated as medium because these parameters are only ﬁtting parameters. On the other hand, pa
rameter extraction is rated as good because easytouse ﬁtting parameters are used. Owing to
the application of the V
Sat
method, no starting values are needed for the parameters to extract
and the extraction process is reduced to a onedimensional search.
Table 4.2: MQC for Linvar model.
Requirement Rating
Accuracy medium
Capacitance Modeling not included
Compactness medium
Parameter Extraction good
Stress Effects not included
4.3 Experimental Results on Transistor Fitting
In the following, experimental results on the analysis of transistor parameters with the V
Sat
method are presented. First, the characteristic behavior of commonly used transistor models
will be explored. Then, the effect of constant contact resistance is treated. A method is
demonstrated how these parasitic elements can be compensated for in the analysis. Finally,
the application of the Linvar model on measurement curves is presented.
4.3.1 Analysis of a Level1 Transistor
The V
Sat
method is based on the Level1 model (see Section 3.2.1) which provides simple
equations to predict the behavior of transistors. In the V
Sat
method, the saturation voltages
of individual I
D
V
DS
curves are extracted. Subsequently, all extracted saturation voltages are
plotted versus their respective V
GS
values. In the case of a Level1 transistor, a line with unity
slope can be expected because V
Sat
= V
GS
− V
T
. From V
Sat
, the threshold voltage V
T
can
readily be extracted and the other Level1 parameters are calculated using (4.2) through (4.5).
Fig. 4.3 shows the output characteristics of a Level1 transistor
2
, the extracted saturation
voltage V
Sat
as well as the derived parameters process conductance K
P
and channellength
2
Original model data: ptype transistor, V
T
=3 V, K
P
=10 pA/V
2
, λ= 10 mV
−1
.
4.3. Experimental Results on Transistor Fitting 77
modulation λ. The threshold voltage has not explicitly been plotted because it can be derived
from the saturation voltage V
Sat
. As expected, the saturation voltage V
Sat
has a slope of one
and intersects the zero V
GS
point at −V
T
. K
P
and λ are independent of the gatesource bias
and coincide with the given model parameters.
The example shows that the V
Sat
method can well extract a true Level1 transistor. How
ever, the extractor needs enough points between the supposed saturation voltage and the maxi
mumV
DS
 in order to safely detect the linear I
DS
line of the saturation curve. To demonstrate
this requirement, the above transistor is analyzed with the V
GS
values ranging from 0 to 20 V
in steps of 2 V and V
DS
also ranging from 0 to 20 V only, but in steps of 1 V. Fig. 4.4 shows
the resulting plot for the V
Sat
curve, the Linvarmodel approximation for the parameters K
P
,
V
T
and λ. At V
DS
 > 15 V, the curves start to considerably deviate from the expected be
havior. The data shows that the V
Sat
prediction gets inaccurate for V
GS
values approaching
20 V.
4.3.2 Analysis of Model for Polycrystalline TFTs
The TFT model for polycrystalline silicon (PsiTFT, see Section 3.2.2) is a semiempirical
model with a physical background [41]. It effectively extends the Level1 model by adding
a V
GS
dependent mobility and a factor for the variation of the saturation voltage (α
sat
). The
output characteristics as well as extracted curves for a simulated polycrystalline thinﬁlm
transistor
3
are depicted in Fig. 4.5.
Level1 parameters derived from the extracted curves do not directly correspond to the
model parameters of the PsiTFT model. This is due to the modiﬁcations of the model with
respect to the original Level1 model (see Section 3.2.2). In the PsiTFT model, the satu
ration voltage is calculated by V
Sat
= α
sat
(V
GS
− V
T
). Therefore, the slope of the curve in
Fig. 4.5b can be used to derive α
sat
≈ 1.7. From this slope, the threshold voltage is derived
by V
T
= −V
Sat
(V
GS
= 0 V)/α
sat
= 1 V.
With V
T
and α
sat
established, the power factor m
µ
for the mobility can be estimated by
plotting log I
D
vs. log (V
GS
− V
T
) for a ﬁxed V
DS
in the saturation region. The slope of the
loglog curve corresponds to 2 + m
µ
owing to I
D
∼ (V
GS
− V
T
)
2+mµ
. Fig. 4.5f depicts the
loglog curve. This approach leads to a slope of 3.2, which coincides with 2 + m
µ
. Finally,
µ
0
can be obtained by inserting a measured current value into the model equation and solving
for µ
0
. The V
GS
dependence of K
P
in Fig. 4.5c can be used for qualitative examinations. In
the ﬁgure, K
P
displays weakly superlinear behavior which suggests a power factor m
µ
> 1.
Fig. 4.5d shows λ, the parameter for the channellength modulation. The deviation from
3
Model data: µ
0
= 1·10
−3
cm
2
/Vs, C
is
= 1 · 10
−7
F/cm
2
, V
T
= 1 V, α
sat
= 1.7, m
µ
= 1.2,
µ
s
= 1 · 10
−11
cm
2
/Vs, η
i
= 3.34, I
0
= 1 · 10
−13
A, W/L = 1000
78 Chapter 4. V
Sat
Method
a)
−30 −25 −20 −15 −10 −5 0
6.0p
8.0p
10.0p
12.0p
−20 −15 −10 −5 0
b)
5.0m
6.0m
7.0m
8.0m
9.0m
10.0m
11.0m
12.0m
13.0m
14.0m
15.0m
−20 −15 −10 −5 0
−25
−20
−15
−10
−5
0
−20 −15 −10 −5 0
−1.0u
−1.5u
−2.0u
−2.5u
−3.0u
−3.5u
saturation curve
−0.5u
0.0
14.0p
d) c)
V
DS
[V]
V
GS
=20 V
V
GS
=18 V
V
GS
=16 V
V
GS
= 0 V
K
P
[
A
/
V
2
]
λ
[
V
−
1
]
V
GS
[V]
V
GS
[V]
V
GS
[V]
I
D
[
A
]
V
S
a
t
[
V
]
Fig. 4.3: Plot of important parameters of a Level1 transistor with ptype behavior:
a) output characteristics, b) saturation voltage, c) process conductance, and d) channellength
modulation.
4.3. Experimental Results on Transistor Fitting 79
a) b)
d) c)
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
−20 −15 −10 −5 0
9.5p
9.6p
9.7p
9.8p
9.9p
10.0p
10.1p
10.2p
10.3p
10.4p
10.5p
−20 −15 −10 −5 0
2.0
2.5
3.0
3.5
4.0
−20 −15 −10 −5 0
5.0m
6.0m
7.0m
8.0m
9.0m
10.0m
11.0m
12.0m
13.0m
14.0m
15.0m
−20 −15 −10 −5 0
V
GS
[V]
K
P
[
A
/
V
2
]
λ
[
V
−
1
]
V
GS
[V]
V
GS
[V] V
GS
[V]
V
S
a
t
[
V
]
V
T
[
V
]
Fig. 4.4: V
Sat
type extraction with an insufﬁcient V
DS
range: a) extracted saturation volt
age, b) derived process conductance, c) threshold voltage, and d) channellength modulation.
Dashed lines show the expected curves.
80 Chapter 4. V
Sat
Method
a)
c)
e)
b)
d)
f)
−2.5m
−2.0m
−1.5m
−1.0m
0.0
−50 −40 −30 −20 −10 0
−0.5m
0.0
1.0n
1.5n
2.0n
2.5n
−20 −15 −10 −5 0
0.5n
0.0
5.0m
10.0m
15.0m
20.0m
−20 −15 −10 −5 0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
0 0.5 1 1.5 2 2.5 3 3.5
0.0
5.0
10.0
15.0
20.0
−20 −15 −10 −5 0
−40.0
−35.0
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
−20 −15 −10 −5 0
V
DS
[V]
V
GS
[V]
V
GS
[V] log(V
GS
−V
T
) –>
V
GS
[V]
V
GS
[V]
I
D
[
A
]
K
P
[
A
/
V
2
]
λ
[
V
−
1
]
l
o
g
(
I
D
)
[
]
V
T
[
V
]
V
S
a
t
[
V
]
Fig. 4.5: Behavior of a polycrystalline thinﬁlm transistor: a) output characteristics,
b) saturation voltage, c) process conductance, d) threshold voltage, e) channellength mod
ulation, and f) logarithmic drain current.
4.3. Experimental Results on Transistor Fitting 81
constant behavior near zero V
GS
can be attributed to the inﬂuence of the subthreshold current
according to (3.12).
The plots from Fig. 4.5 can be used to check whether the PsiTFT model matches a mea
sured device. If the loglog plot of I
D
vs. V
GS
−V
T
does not yield a straight line, the PsiTFT
model does not correctly map the output characteristics of the respective device.
4.3.3 Effect of Contact Resistance on Level1 Model
The ideal behavior of the Level1 model can be weakened by the presence of contact resis
tance at the interface between the source/drain electrodes and the channel region. Contact
resistance is often encountered e.g. in bottomgate bottomcontact transistors where the elec
trodes disturb the formation of the semiconductor ﬁlm and trap states occur. These trap states
lead to diodelike contact resistance which can be difﬁcult to model. Diodelike resistances
also occur when the work functions of the electrode material and the semiconductor in the
transistor channel are not aligned.
Constant resistors at the source and drain electrodes are more tractable form of contact
resistance. Their presence in a Level1type transistor has already been discussed brieﬂy in
Section 3.3.1. At this point, their inﬂuence on extracted parameters will be analyzed. A device
model according to Fig. 4.6 will be assumed. R
DC
and R
SC
represent the drainside and
sourceside contact resistances while M maps the ideal Level1 transistor. The V
Sat
extractor
treats M as a unit with R
DC
/ R
SC
and derives V
GS
dependent Level1 parameters for the
combined device. The extraction results are effective parameters that can be used to see how
contact resistance affects the output characteristics.
GATE
DRAIN
SOURCE
R
SC
R
DC
M
Fig. 4.6: Schematic of a transistor with contact resistances at drain and source.
In the analysis, R
DC
and R
SC
shall be varied independently and the ideal transistor M
shall have the same model parameters as in Section 4.3.1. Fig. 4.7 shows extraction results
82 Chapter 4. V
Sat
Method
for different R
DC
values. R
DC
alone (R
SC
= 0 Ω) strongly inﬂuences the saturation voltage
as can be seen from Fig. 4.7a. In the plot, the V
GS
dependent saturation voltage is shown. The
data demonstrates that small values of R
DC
in the range of 100 kΩ do not noticeably affect
transistor behavior for the given device. However, higher R
DC
values shift the saturation point
to more negative values.
A V
Sat
type parameter extraction shows that the drainside resistor strongly inﬂuences
(viz. shifts) V
T
and K
P
. K
P
decreases with R
DC
. Consequently, increasing R
DC
also de
creases the attainable current as demonstrated by Fig. 4.7d. The effect of R
DC
will also be
more pronounced for increasing V
GS
 owing to the fact that the drain current also increases
as well as the voltage drop at R
DC
.
The sourceside contact resistance (R
SC
) can also be varied with R
DC
being removed
(R
DC
= 0 Ω). In this case, the maximum drain current is affected while the saturation points
effectively keep unchanged as long as R
SC
does not get too large. At some resistance value,
R
SC
will start to dominate the I
D
V
DS
curve. This can be seen from the graphs in Fig. 4.8.
In conclusion, a noticeable resistance at the drain contact will inﬂuence the saturation
voltage V
Sat
, the process conductance K
P
and oncurrents. A noticeable resistance at the
source contact on the other hand will inﬂuence the process conductance K
P
, the channel
length modulation λ and both the on/off current.
4.3.4 Compensation of Contact Resistance
The V
Sat
method only measures effective parameters. It does not separate the contributions of
contact resistors due to the nonlinear interaction between the transistor and R
DC
/R
SC
. These
resistances can be determined by a resistance measurement like the potential proﬁling (see
Section 3.3.1). If the approximate values are known they can be compensated for by placing
additional negative resistors (R
CD
and R
CS
) in series to the transistor during simulation as
shown in Fig. 4.9. At these points in the device setup, they neutralize the effect of the contact
resistances.
The presence of R
CD
and R
CS
leads to equal potentials at DRAIN and DP as well as
SOURCE and SP. In a computer simulation, the parameters of transistor M can now be ex
tracted using the usual methods:
1. Obtain effective parameters or a tablebased model of the transistor operating under the
inﬂuence of the contact resistances.
2. Derive the contact resistances by measurement.
3. Neutralize the contact resistance by a setup equivalent to Fig. 4.9. With this setup, the
drainsource voltage and gatesource voltage across transistor M are equivalent to the
4.3. Experimental Results on Transistor Fitting 83
a) b)
d)
c)
9.0m
9.5m
10.0m
10.5m
11.0m
−70.0
−60.0
−50.0
−40.0
−30.0
−20.0
−10.0
0.0
1.0p
2.0p
3.0p
4.0p
5.0p
6.0p
7.0p
8.0p
9.0p
10.0p
10.0n
1.0u
10.0u
0.0 2.0M 4.0M 6.0M 8.0M 10.0M 0.0 −5.0 −10.0 −15.0 −20.0
−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
0.1u
1.0 MΩ
0.1 MΩ
R
DC
= 0.0 MΩ
2.0 MΩ
5.0 MΩ
10.0 MΩ
K
P
[
A
/
V
2
]
λ
[
V
−
1
]
V
S
a
t
[
V
]
R
DC
[Ω] V
GS
[V]
V
GS
[V] V
GS
[V]
I
D
[
A
]
Fig. 4.7: Behavior of important transistor parameters with respect to different values for the
drainside contact resistance: a) saturation voltage, b) process conductance, c) channellength
modulation, d) on/off current.
84 Chapter 4. V
Sat
Method
a)
b)
c) d)
2.0p
3.0p
4.0p
5.0p
6.0p
7.0p
8.0p
9.0p
10.0p
2.0m
3.0m
4.0m
5.0m
6.0m
7.0m
8.0m
9.0m
10.0m
11.0m
10.0n
0.1u
1.0u
10.0u
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
−20.0 −15.0 −5.0 0.0 −10.0 −20.0 −15.0 −10.0 −5.0 0.0
−20.0 −15.0 −10.0 −5.0 0.0 0.0 2.0M 4.0M 6.0M 8.0M 10.0M
10.0 MΩ
R
SC
= 0.0 MΩ
0.1 MΩ
1.0 MΩ
5.0 MΩ
2.0 MΩ
V
S
a
t
[
V
]
V
GS
[V] V
GS
[V]
K
P
[
A
/
V
2
]
λ
[
V
−
1
]
V
GS
[V] R
SC
[Ω]
I
D
[
A
]
Fig. 4.8: Behavior of important transistor parameters with respect to different values of the
sourceside contact resistance: a) saturation voltage, b) process conductance, c) channel
length modulation, and d) on/off current.
4.3. Experimental Results on Transistor Fitting 85
DRAIN
GATE
DP
SP
SOURCE
M V
DS
R
DC
R
CD
= −R
DC
R
SC
R
CS
= −R
SC
V
GS
Fig. 4.9: Transistor with resistors neutralizing the contact resistances.
voltage drop between the terminals DRAIN and SOURCE and GATE and SOURCE,
respectively.
Results of the procedure are demonstrated in Fig. 4.10. The ﬁgure depicts extracted curves
vs. V
GS
for a device simulated with R
SC
= 2 MΩ, no R
DC
, and various compensation resistors.
The method of resistance compensation can also be used to determine the contact resis
tances R
SC
and R
DC
. The approach exploits the fact that the channellength modulation λ
is mainly affected by R
SC
and the saturation voltage V
Sat
only by R
DC
. By exploiting these
relationships, R
DC
can be determined by bringing V
Sat
to a straight line through varying R
CD
and R
SC
by bringing λ to a straight line through varying R
CS
.
86 Chapter 4. V
Sat
Method
a)
c) d)
b)
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
6.0p
7.0p
8.0p
9.0p
10.0p
11.0p
12.0p
13.0p
14.0p
15.0p
10.0n
1.0u
10.0u
−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
−20.0 −15.0 −10.0 −5.0 0.0 0.0 0.5M 1.0M 1.5M 2.0M 2.5M 3.0M
0.1u
R
SC
= 2 MΩ
R
SC
= 2 MΩ
R
SC
= 2 MΩ
R
SC
= 2 MΩ
3.0 MΩ
2.0 MΩ
1.0 MΩ
0.1 MΩ
R
CS
= 0.0 MΩ
λ
[
V
−
1
]
V
GS
[V] V
GS
[V]
V
GS
[V]
R
SC
[Ω]
V
S
a
t
[
V
]
I
D
[
A
]
K
P
[
A
/
V
2
]
Fig. 4.10: Behavior of important transistor parameters with respect to different values of
the sourceside compensation resistance: a) saturation voltage, b) process conductance,
c) channellength modulation, and d) on/off current. The contact resistance at the source
electrode is R
SC
= 2 MΩ.
4.3. Experimental Results on Transistor Fitting 87
4.3.5 Analysis of a PDHTT Transistor
Fig. 4.11 shows the I
D
−V
DS
curve of a poly(3,3”dihexyl2,2’:5’,2”terthiophene) (PDHTT)
transistor and the parameters extracted by the V
Sat
method. I/V data was taken from [95]. The
device has a channel width of 10,000 µm and a channel length of 10 µm.
The resulting curves show that the saturation voltage decreases linearly between gate volt
ages of 4 V and 24 V. At gate voltages below 24 V, V
Sat
begins to saturate. This behavior
can be attributed to V
GS
 approaching max. V
DS
, a voltage region where the V
Sat
method is
no longer reliable (see Section 4.3.1). The process conductance K
P
sharply increases between
gate voltages of 0 and 5.0 V and then slowly degenerates. At gatesource voltages below 24
V, it starts to rise again. This latter rise might also be due to the difﬁculties in extracting
the correct saturation voltages at these V
GS
ranges. The decline of K
P
between gatesource
voltages of 6 V and 24 V might be due to the presence of sourceside contact resistance.
Moreover, the shape of V
Sat
and K
P
implies that PsiTFT or Linvar modeling is not neces
sary for the transistor. Instead, the V
GS
dependent development of the parameters indicates a
Level1 model including contact resistances. However, for gatesource voltages above 5 V,
the Level1 model will fail and produce current values far in excess of the measured values
because a Level1 model would not map the decline of the process conductance parameter
K
P
between 5 V and 0 V. When using a sourceside compensation resistor of R
CS
= 400
kΩ, K
P
can be stabilized to 21 pA/V
2
for V
GS
< 10 V with V
T
= 0.7 V, λ = 0.001 V
−1
. The
compensation resistor indicates a sourceside contact resistance of R
SC
= −R
CS
= 400 kΩ. It
should be noted that such a Level1 model including a sourceside resistor will nonetheless
fail to match device behavior for V
GS
 < 5 V.
4.3.6 Modeling of a P3HT Transistor
In this section, the drain current of a P3HT transistor is analyzed using the V
Sat
method and
modeled with the Linvar approach. The device characteristics were obtained from activities
within the research project POLITAG
4
. The results of the measurements, extractions, and
approximations with the Linvar model are shown in Fig. 4.12. Solid lines mark measured
I/V curves or parameters extracted with the V
Sat
method. Dashed lines and/or cross markers
indicate approximations with the Linvar model. The plots show that the Linvar model sup
plies a reasonably good ﬁt. Model parameters in the Linvar model were KP
0
= 8 pA/V
2
,
f
k
= 2 pA/V
3
, V
T0
= 2.4 V, f
T
= 0.2 V, λ
0
= 5 mV
−1
, f
λ
= 0 V
−2
. In order to better ap
proximate the drain current at zero gatesource voltage, a normalized parallel resistor with
4
The devices were fabricated in topgate structure by lithographic structuring of gold electrodes. Spincoating
was used to deposit the semiconductor. Detailed speciﬁcations of the fabrication process were not provided by
the device manufacturer, a commercial source participating in the research project POLITAG. This project was
funded by the German Ministry for Education and Research (BMBF) under the ID 01BI150.
88 Chapter 4. V
Sat
Method
b)
d)
a)
c)
−6.0u
−5.0u
−4.0u
−3.0u
−2.0u
−1.0u
1.0u
0.0u
0.0
5.0p
10.0p
15.0p
20.0p
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.05
0.20
0.25
0.30
0.35
0.40
0.15
0.10
−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
0.00
−7.0u
25.0p
−20.0 −25.0 −30.0 −15.0 −10.0 −5.0 0.0 −30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0
30.0 V
27.5 V
25.0 V
V
GS
= 0.0 V
22.5 V
20.0 V
17.5 V
15.0 V
12.5 V
10.0 V
V
GS
[V]
V
GS
[V]
V
DS
[V] V
GS
[V]
λ
[
V
−
1
]
I
D
[
A
]
K
P
[
A
/
V
2
]
V
S
a
t
[
V
]
Fig. 4.11: Extraction of relevant parameters for a PDHTT transistor with channel width
W = 10 mm and channel length L = 10 µm: a) output characteristics (taken from [95]), b)
saturation voltage, c) process conductance, and d) channellength modulation.
4.4. Chapter Summary 89
R
′
par
= 10 TΩm was introduced between source and drain of the transistor (effective value
R
par
= 1.67 GΩ). This parallel resistor can be attributed e.g. to bulk conductance of the de
vice.
Alternatively, the device can be approximated using the PsiTFT model. When apply
ing the procedure described in Section 4.3.2, the following model set is obtained by calcu
lations: C
is
= 1 · 10
−7
F/cm
2
, µ
1
= 2.5 · 10
−5
cm
2
/Vs, V
T
= 2.9 V, α
sat
= 0.8, m
µ
= 0.886,
λ = 0.005 V
−1
. Here, C
is
and µ
0
are arbitrarily interchangeable
5
. Apart from subthreshold
behavior, which has been neglected in this example, the parameter set for the PsiTFT model
shows good agreement with the experimental data (not depicted in Fig. 4.12a). Here, the Psi
TFT model performs even better than the Linvar model. This better agreement is at the cost
of a more challenging extraction procedure, however.
4.3.7 Conclusions
Section 4.3 deals with the modeling of organic transistors. The analysis is based on the V
Sat
and Linvar methods of parameter extraction. In principle, the V
Sat
method indicates appro
priate models for a particular device by showing the linearity and slope of the V
GS
dependent
parameters.
The ﬁndings in Section 4.3.5 and Section 4.3.6 show that different transistors can consid
erably differ in behavior. Therefore, it is difﬁcult to ﬁnd model equations which are suitable
for a wider range of transistors. The dependence of model parameters could be approximated
by ﬁtting polynomials. This technique was analyzed in [94] but polynomials still fail to cor
rectly map the K
P
behavior presented in Section 4.3.5. Moreover, mere ﬁtting polynomials
do not comply with the requirement of compact device models derived in Section 3.1 because
numerous and obscure ﬁtting parameters are introduced. The Linvar model is also a ﬁtting
model but uses only as few parameters as possible.
4.4 Chapter Summary
In this chapter, a methodology for extracting parameters of transistor models in a twostep
approach was described. In a ﬁrst step, the saturation voltage of individual output charac
teristics I
D
vs. V
DS
at ﬁxed V
GS
values are extracted by a onedimensional search routine.
The methodology is centered on the derivation of the saturation voltage. Hence, it is called
V
Sat
method. Once V
Sat
has been obtained, Level1 parameters are calculated analytically for
the individual output characteristics. The advantage of this approach is that no user interac
5
Due to the fact that information on the relative permittivity and insulator thickness of the device was not
available, the default value has been chosen for C
is
.
90 Chapter 4. V
Sat
Method
a) b)
c) d)
extraction
approximation
extraction
approximation
extraction
approximation
extraction
approximation
0.0
5.0p
10.0p
15.0p
20.0p
25.0p
30.0p
35.0p
40.0p
45.0p
50.0p
55.0p
−6.0u
−5.0u
−4.0u
−3.0u
−2.0u
−1.0u
0.0
1.0u
approximation
measurement
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
35.0m
40.0m
−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0
−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0
0.0
V
GS
= 0 V
V
GS
= 4 V
V
GS
= 8 V
V
GS
= 12 V
V
GS
= 16 V
V
GS
= 20 V
I
D
[
A
]
λ
[
V
−
1
]
V
GS
[V] V
DS
[V]
V
GS
[V] V
GS
[V]
K
P
[
A
/
V
2
]
V
S
a
t
[
V
]
Fig. 4.12: Extraction of relevant parameters for a P3HT transistor with channel width
W = 6 mm and channel length L = 10 µm: a) output characteristics, b) saturation voltage,
c) process conductance, and d) channellength modulation. Measured and extracted data are
shown by solid lines, approximations by the Linvar model are shown by dashed lines and/or
cross markers.
4.4. Chapter Summary 91
tion is necessary regarding initial values or parameter bounds for the parameter extraction.
Therefore, the method can be carried out fully automatically.
By observing the V
GS
dependent shapes of the basic Level1 parameters, viable modeling
approaches (e.g. PsiTFT, Level1 modeling, etc.) can be identiﬁed and the respective models
can be applied in the second step. Currently, the only models directly using all of the interme
diate Level1 parameters are a V
Sat
type table model and the Linvar model, both presented in
this chapter. V
Sat
based analysis of more complex models like the PsiTFT model currently
only uses a small fraction (viz. V
T
) of the intermediate parameters in the derivation of their
own parameter values. In future work, mapping of the full range of intermediate parameters
to selected transistor models could be elaborated.
In conclusion, the V
Sat
method can contribute to modeling by providing a fully automated
way of deriving intermediate parameters which can be used a) to select feasible transistor
models for measured output characteristics, and b) to reﬁne these intermediate parameters
into parameters for more complex models.
92 Chapter 4. V
Sat
Method
93
Chapter 5
Analysis of OFETBased Logic Circuits
In this chapter, standard procedures used for characterizing OFETbased logic circuits will
be presented. First, commonlyused circuit concepts realizing OFETbased logic gates will
be discussed. Then, methods of assessing robustness and timingrelated performance ﬁgures
of logic gates are detailed. Subsequently, existing tools for characterizing logic circuits are
reviewed. The discussion aims at identifying useful performance ﬁgures which quantify the
performance of certain OFET generations or circuit technologies as well as requirements of
circuit analysis on an integrated analysis framework.
5.1 Logic Circuits
Logic gates are the principal building blocks of logic circuits. They can be considered as com
binations of “switching elements” used for computing operations from the Boolean algebra.
5.1.1 Basic Circuit Concepts
The most basic logic gate in a logic family is the inverter. In OFETbased logic circuits,
it is commonly represented in the form of a pulldown and a pullup element switching the
inverter’s output to ground (GND) or to the supply voltage (V
DD
) via a lowresistance path.
Fig. 5.1 shows the schematics of commonlyused conﬁgurations of inverters.
In circuits operating with only one type of semiconductor (either ntype or ptype) for
both the pullup and the pulldown element, the input of the inverter is connected to an input
or driving transistor. This transistor can shortcut the output to GND if the proper voltage
is applied. The pullup element is then realized by a load transistor where the gate is either
connected to its source or to its drain. If the gate is connected to the source, a ﬁxed gatesource
voltage V
GS
= 0 V results. This conﬁguration will only work if the transistor is switched
94 Chapter 5. Analysis of OFETBased Logic Circuits
Q
A
a)
Q
A
b)
Q
A
e)
Q A
d)
Q A
c)
M
D
M
L
V
DD
M
D
M
L
V
DD
M
D
R
L
V
DD
M
PU
M
PD
V
DD
M
PU
M
PD
V
DD
Fig. 5.1: Basic conﬁgurations to implement an inverter: a) Load transistor (M
L
) in current
source load conﬁguration, b) load transistor (M
L
) in diode load conﬁguration, c) comple
mentary pullup (M
PU
) and pulldown transistors (M
PD
), d) complementarylike ambipolar
transistors (M
PU
and M
PD
), and e) load resistor (R
L
) conﬁguration.
on at a gatesource voltage of zero – a behavior referred to as normallyon or depletion
mode in literature (e.g. [96, 97]). A normallyon transistor in this conﬁguration yields an
approximately constant drain current as long as it operates in the saturation region. Hence, the
conﬁguration of a load transistor with the gate connected to its source is referred to as current
source load (CSL) conﬁguration in this work following the deﬁnition of currentsourcing
load used by [98]. Fig. 5.2 shows the relationship between the output characteristics of the
transistors of a CSLtype inverter and its voltage transfer characteristic (VTC), which is the
plot of the output voltage vs. the input voltage. The numbered circles in both plots of the
ﬁgure denote corresponding operating points in the output characteristics and the VTC.
0
b)
load
transistor
driving
transistor
0
c)
output
input
a)
0
d
r
a
i
n
c
u
r
r
e
n
t
(
d
r
i
v
i
n
g
t
r
a
n
s
.
)
2
1
(load trans.)
drain current
output voltage
3
4 5
4
3
2
5
1
input voltage
o
u
t
p
u
t
v
o
l
t
a
g
e
V
DD
V
DD
V
DD
Fig. 5.2: Relationship between output characteristics and VTC of a CSLtype inverter:
a) schematic, b) output characteristics of driving and load transistor, and c) resulting voltage
transfer characteristics. The numbered points in b) and c) correspond.
5.1. Logic Circuits 95
If the gate of the load transistor is connected to the drain, a ﬁxed gatedrain voltage
V
GD
= 0 V results. This conﬁguration does not rely on a normallyon transistor and yields
an output characteristic similar to a diode for the pullup transistor. Therefore, this conﬁgura
tion will be referred to as diode load (DL) conﬁguration in the following. OFETbased logic
gates in diode load conﬁguration have been presented e.g. in [3].
Logic circuits in OFET technology usually employ load and input transistors of the same
semiconductor material. There are also reports on circuits using normallyoff input and
normallyon load transistors fabricated in laboratory setups. Normallyoff or enhancement
mode means that the transistor is switched off at a gatesource voltage of zero. For example,
Lee and colleagues [99] reported ptype inverters based on pentacene where the input transis
tor operated with a negative threshold voltage and the load transistor with a positive threshold
voltage. The threshold voltage of the driving transistor had been shifted by a special treatment
of the insulatorsemiconductor interface so that the device was switched off at a gatesource
voltage equal to zero. The combination of an enhancementmode input and a depletionmode
load transistor is a concept that was commonly used in the early days of MOS integrated
circuits and is referred to as enhancementdepletion (E/D) logic [97, 100].
The pullup element can also be a transistor of complementary semiconductor type, i.e. n
type charge carriers if the pulldown transistor is ptype and vice versa. This conﬁguration is
usually employed in stateoftheart logic circuits and is referred to as CMOS (complementary
metaloxide semiconductor
1
) logic [37, 101]. In CMOStype inverters, both the gate of the
pullup and the gate of the pulldown transistor are connected to the input. Examples of
organic complementary circuits can be found in [102, 103].
Alternatively, the transfer characteristics of ambipolar OFETs (see Section 3.2.8) can be
exploited to design inverters with CMOSlike voltagetransfer characteristics as shown in
Fig. 5.3. Unlike inverters with true normallyoff complementary transistors, ambipolar in
verters never reach the supply rails. This fact also complicates the implementation of more
complex logic gates like NANDs or NORs, because ambipolar transistors in series connec
tions do not fully switch off.
Another option is to use a resistor as the pullup element connecting the output to the
supply rail V
DD
. Examples of circuits utilizing resistor loads have been presented e.g. in
[104].
1
The expression MOS (metal oxide semiconductor) originates from the early material structure of inversion
layer CMOS transistors consisting of a silicon dioxide (SiO
2
) dielectric sandwiched between a metal gate and
the semiconductor.
96 Chapter 5. Analysis of OFETBased Logic Circuits
Output
Input
0
20
40
60
80
100
0 20 40 60 80 100
o
u
t
p
u
t
v
o
l
t
a
g
e
input voltage
V
DD
Fig. 5.3: Schematic and voltage transfer characteristic of an ambipolar inverter.
5.1.2 Enhancements
The fact that most organic semiconductor materials exhibit weakly normallyon or weakly
normallyoff behavior leads to poor performance of the input transistor as it can only be
switched off with difﬁculties. Unless the complementarytype circuit concept is used, the
logic levels are determined by the ratio between the channel resistance of the input transistor
at a given gatesource voltage and the resistance value of the load element. The switchoff be
havior of the input transistor can be improved by applying a positive voltage at its gate. This
observation led to the realization of level shifter concepts in OFETbased logic circuits [85].
In principle, the initial logic block is followed by an output stage which shifts the output volt
age to more favorable voltage levels. For ptype semiconductors, output voltages around zero
are shifted to positive voltages. This technique has already been described in the early 1960s
for transistorbased logic gates [105] and has also frequently been used in logic circuits em
ploying normallyon galliumarsenide transistors under the name Buffered FET Logic (BFL)
[106]. With a levelshifter concept, however, an additional supply voltage is required and the
real estate and wiring complexity of circuits increases. Fig. 5.4 shows the schematic of an
inverter in level shifter conﬁguration.
Other researchers switched from static to dynamic logic. Pullup elements in ratioed logic
are implemented by the same types of transistors as pulldown elements and are statically
driven. If the transistors operate in currentsource load conﬁgurations the sink current pro
vided by the pullup transistor is considerably lower than the drive current provided by the
pulldown transistor. An increased widthtolength ratio of the pullup device boosts its sink
current but also its gate capacitance. The increased capacitance will limit the attainable circuit
speed. Use of a diode load conﬁguration considerably reduces the parasitic capacitance at the
cost of a reduced noise margin (see Section 5.3.2) of the logic gates. In order to improve the
5.2. Circuit Characterization 97
A
Q
V
SS
V
DD
M
1
M
2
M
4
M
3
Fig. 5.4: Schematic of an inverter in levelshifter conﬁguration.
performance of OFETbased logic circuits, dynamic circuit concepts have been investigated.
Huitema et al. [107] reported on a logic circuit utilizing pentacene transistors and a 120stage
shiftregister with 2,160 transistors in a dynamic circuit concept. The basic idea of a dynamic
circuit concept is to add a clock input to the logic gates. This clock is used for dividing the
operation of the gate into two phases: setup (also called precharge) and evaluation phase. In
the setup phase, the output of the gate is precharged to the logic high voltage regardless of the
input values. In the evaluation phase, the output goes to the low level if the conﬁguration of
the input signals forces it to do so, but will otherwise stay at the high level. Details about the
actual OFETbased implementation were not given in [107] but the concept of dynamic logic
is frequently used for implementing highspeed siliconbased logic circuits. Fig. 5.5 shows
the schematic of a NOR gate in dynamic logic. During the precharge phase, the input PRE is
used for charging the output to the voltage level V
DD
while the inputs A and B stay at GND.
In the subsequent evaluation phase, the output may go to ground potential, depending on the
states of the inputs.
5.2 Circuit Characterization
Circuits are frequently implemented by combining prebuilt cells with different functionality in
order to implement the desired behavior [108]. Normally, chip manufacturers supply libraries
of the cells that can be used for developing the circuit with software for computeraided circuit
design. These libraries contain speciﬁcations of the cells which describe their functional and
electrical behavior.
There exist tools for characterizing the electrical behavior of cells using circuit simulation.
These tools generate testbenches, carry out circuit simulations, and compile characterization
98 Chapter 5. Analysis of OFETBased Logic Circuits
Q
B
PRE
A
V
DD
Fig. 5.5: Schematic of a NOR gate in a dynamic logic conﬁguration. The input PRE is used
for precharging the output to V
DD
via the load transistor.
reports on circuit behavior.
In the domain of logic circuits, the following properties are characterized [108, 109]:
2 Robustness, i.e. valid logic levels and noise margin.
2 Timing, including rise/fall times, transition times, clocking requirements.
2 Driving capability, i.e. fan out characterization.
2 Input capacitance.
2 Characterization of power consumption.
These characteristics and especially the ﬁrst two (logic levels/noise margin and timing) can
also be used for evaluating the performance of an OFET technology. Therefore, it is worth
while to take a closer look at the mechanisms of the characterization process. The following
two sections will provide a discussion of methods characterization robustness (Section 5.3)
and timing (Section 5.4).
Robustness is discussed because most OFETbased logic circuits suffer from nonideal
VTCs. The unitygain method as the standard procedure for analyzing noise margins of logic
circuits (see Section 5.3.3) can only be applied with care. Timing characterization is discussed
because standard methods of deriving delay times and other timing data often assume well
behaved clocking signals (with sharp slopes) which are not frequently used in lowcost organic
circuits. Therefore, alternate characterization methods have to be investigated.
Other characteristics will not be detailed in the following owing to the fact that standard
methods described in literature [37, 106, 110, 111] can readily be applied to organic logic
5.3. Characterization of Robustness 99
circuits. Moreover, these characteristics are more important for experienced chip designers
than for the analysis of the general performance potential of OFET technologies.
5.3 Characterization of Robustness
One important characteristic of logic circuits is their robustness. It deﬁnes the ability of a logic
circuit to safely detect and issue valid voltage levels for the distinct logic states in the presence
of adverse noise at the input signals. In a general way, noise is deﬁned as any deviation from
nominal voltages [112]. Sources for noise can e.g. be [113]:
2 Spurious signals or crosstalk which interfere with informationcarrying circuit nodes.
2 Inherent ﬂuctuations of device parameters owing to fabrication process or operating
point variations.
For OFETbased logic circuits, the contribution of device variations is more important
than spurious signals owing to the low packing density of organic logic circuits [114] and the
early stages in the fabrication technology. Several possibilities exist to derive information on
the robustness of logic circuits. A selection of these will be discussed in the following. First,
the method of equilibrium zones will be discussed as it helps deﬁning valid voltage levels for
logic circuits in the presence of VTC variation. At its core, this method is only a qualitative
approach. Therefore, the concept of noise margin is presented as it introduces ﬁgures of merit
which can be measured. Then, the unitygain method is detailed. It is the standard method for
stateoftheart integrated circuits using CMOS devices but occasionally fails in assessing the
robustness of organic logic circuits. Therefore, the method of maximum squares is discussed
which is often used in nonCMOS circuits to analyze robustness. Finally, methods inspecting
certain gain values of the VTC are reviewed.
5.3.1 Method of Equilibrium Zones
Pierce [115] treated the problem of tolerance and robustness in 1963 by inspecting signal
regeneration in the presence of VTC variations. He introduced “equilibrium zones” in order
to assess the compatibility between different types of logic gates. In the following text, this
method will hence be referred to as method of equilibrium zones in the following. To the
best knowledge of the author of this work, Pierce’s method is not used in other literature on
noisemargin calculations.
The method of equilibrium zones starts by inspecting the VTC of a singleinput non
inverting buffer performing the Boolean identity operation Q=A, where A is the input and Q
the output. The voltage V
out
at the output Q of the noninverting buffer is some function f of
100 Chapter 5. Analysis of OFETBased Logic Circuits
the input voltage V
in
at the input A, i.e. V
out
= f(V
in
). A stable VTC has three equilibrium
points where V
in
= V
out
(see Fig. 5.6):
2 voltage V
L
for stable low level,
2 voltage V
H
for stable high level,
2 voltage V
M
for the metastable point between these two.
If identical buffers are arranged in a long chain of gates with the output of each gate
connected to the input of its successor then the following relationship between the input V
in,1
of the ﬁrst gate and the output V
out,m
of the last gate is given by:
V
in,1
< V
M
⇒ V
out,m
= V
L
,
V
in,1
= V
M
⇒ V
out,m
= V
M
,
V
in,1
> V
M
⇒ V
out,m
= V
H
.
(5.1)
V
M
marks the boundary between valid voltage levels for the low and high states with
0 ≤ V
L
< V
M
< V
H
≤ V
DD
, (5.2)
when assuming positive supply voltages (V
DD
> 0).
1
A Q
0
V
in
V
out
V
DD
V
DD
V
M
V
H
V
L
V
M
V
H
V
L
V
in
V
out
Fig. 5.6: VTC of a noninverting buffer with equilibrium points V
L
, V
M
, and V
H
.
However, one single VTC for all gates is not realistic. Real gates will display slight
differences in their VTC shapes owing to parameter variations or switching noise. In these
cases, upper and lower bound VTCs can be deﬁned and used for the preceding equilibrium
5.3. Characterization of Robustness 101
analyses. In the presence of upper and lower bounds, the analysis will yield equilibrium zones
instead of single equilibrium points (see Fig. 5.7). These equilibrium zones deﬁne regions
in which the ﬁnal equilibrium points will lie. The points cannot be stated exactly owing to
the statistical nature in which the individual VTCs vary. More importantly, it is not known
in the region belonging to the metastable equilibrium points whether the output will increase
or decrease between two or more stages and eventually lead to a stable output high or low
voltage. Hence, the middle region is called indeterminate zone in [115]. Valid logic levels are
required to avoid the indeterminate zone.
0
o
u
t
p
u
t
v
o
l
t
a
g
e
input voltage
i
n
d
e
t
e
r
m
i
n
a
t
e
lower bound
VTC
upper bound
VTC
l
o
w
h
i
g
h
Fig. 5.7: Determination of equilibrium zones of noninverting buffers using upper and lower
bound VTCs. The individual equilibrium points are marked by circles.
The method of equilibrium zones can also be extended to inverters and more complex
gates. In the case of inverters, simply a pair of two gates is combined so to implement the
identity operation and getting plots in the form of Fig. 5.7.
Worstcase combinations of pairs of two inverters have to be considered in order to derive
the equilibrium zones. In spite of that, these zones are readily available when plotting the
upper and lower bound VTCs in a diagram together with their reﬂections about the x = y line
(see Fig. 5.8). Therefore, it is not necessary to calculate the VTC of the pair of inverters.
By use of the reﬂection, values on the x axis serve both as input of the ﬁrst and output of
the second inverter while values on the y axis serve both as output of the ﬁrst and input of the
second inverter. At each intersection between a true and a reﬂected VTC, an equilibrium point
of the VTC of the respective pair of inverters is located. This is due to the fact that there, the
second inverter will transform its input voltage to a value equivalent to the input voltage of
the ﬁrst inverter.
Once the equilibrium zones have been established their positions can be drawn in a dia
102 Chapter 5. Analysis of OFETBased Logic Circuits
0
o
u
t
p
u
t
v
o
l
t
a
g
e
,
f
i
r
s
t
i
n
v
e
r
t
e
r
output voltage, second inverter
i
n
p
u
t
v
o
l
t
a
g
e
,
s
e
c
o
n
d
i
n
v
e
r
t
e
r
input voltage, first inverter
l
o
w
i
n
d
e
t
e
r
m
i
n
a
t
e
h
i
g
h
inverter
1 1
first second
inverter
Fig. 5.8: Determination of equilibriumzones for pairs of inverters by plotting true (solid lines)
and reﬂected curves (broken lines) of the upper and lower bound VTCs. The individual equi
librium points are marked by circles. The inset shows the constellation of the two inverters.
gram to test the compatibility of gates with different equilibrium zones (see Fig. 5.9). If gates
are to be interconnected their indeterminate zones must not coincide with either the high or
low equilibrium zones of their partners in order to yield regenerating signals.
? high low
Driving Gate
0
0
low high ?
Sensing Gate
V
DD
V
DD
Voltage
Voltage
Fig. 5.9: Compatibility diagram of two gates of different types. The boxes with the question
marks denote the indeterminate zones.
5.3.2 Concept of Noise Margin
A drawback of the method of equilibrium zones is that, in its original form, it is only a qual
itative tool. In order to compare the performance potential of different circuit or device tech
nologies by numbers, the concept of noise margin is helpful.
The noise margin can be calculated by deﬁning four critical voltage levels in a VTC. An
5.3. Characterization of Robustness 103
inverter as the simplest form of logic gate detects and issues logic states according to the
following relationship between input voltage V
in
, output voltage V
out
, and the four critical
voltage levels V
IL,max
, V
IH,min
, V
OL,max
, and V
OH,min
[116, 117]:
V
in
≤ V
IL,max
⇒ V
out
≥ V
OH,min
,
V
in
> V
IH,min
⇒ V
out
< V
OL,max
.
(5.3)
Here, V
IL,max
(V
IH,min
) is the maximum (minimum) allowable voltage level for the logic
low (high) level at the input, V
OH,min
(V
OL,max
) is the minimum(maximum) allowable voltage
level for the logic high (low) level at the output. Moreover, positive voltages are assumed. The
relationships in (5.3) give rise to the voltage tolerance between inputs and outputs [116] as
NM
H
= V
OH,min
−V
IH,min
,
NM
L
= V
IL,max
−V
OL,max
.
(5.4)
The tolerance of a gate against variations of the input voltages is deﬁned in terms of the noise
margin NM
L
for the logic low level and NM
H
for the logic high level. In order to get both
NM
L
> 0 and NM
H
> 0, the following relationships are required:
0 < V
OL,max
< V
IL,max
< V
IH,min
< V
OH,min
< V
DD
. (5.5)
The diagram in Fig. 5.10 can be used for visualizing the deﬁnitions in (5.4) and (5.5). In
the lower part of the ﬁgure, two gates are connected via a noisy path. It should be stressed that
noise sources can be spurious signals or variations in the transistors of the gates. The upper
part of the ﬁgure represents the graphical equivalence of (5.4) and (5.5)
There exists no general rule for the deﬁnition of the critical voltages V
IL,max
, V
IH,min
,
V
OL,max
and V
OH,min
. Although the method of equilibrium zones can be used for deﬁning
the critical voltages (see Fig. 5.11), this approach is not used in literature on noise margin
calculations. Instead, the unity gain method presented in Section 5.3.3 is often used. For
OFETbased logic circuits, however, it will sometimes predict negative noise margin for fully
functional logic gates.
A simple graphical test to determine whether a particular gate complies with given noise
margins [116] can be carried out. In the test, the VTC f(V
in
) of the gate is drawn in the VTC
box and the shaded areas where V
out
< V
OH,min
for all 0 < V
in
< V
IL,max
and V
out
> V
OL,max
for all V
IH,min
< V
in
< V
DD
. A valid VTC does not enter these shaded areas (see Fig. 5.12).
104 Chapter 5. Analysis of OFETBased Logic Circuits
1 1 noise
V
OL,max
gate M gate M + 1
V
OUT
V
DD
V
IH,min
V
IL,max
V
OH,min
V
IN
NM
H
NM
L
Fig. 5.10: Deﬁnition of noise margins (adaption from [117]).
low
0
? high
V
DD
Voltage
V
OL,max
V
OH,min
V
IL,max
V
IH,min
Fig. 5.11: Deﬁnition of critical voltages using the method of equilibrium zones.
0
0
V
IL,max
V
OL,max
V
OH,min
V
DD
V
IH,min
V
DD
V
in
f(V
in
)
V
out
Fig. 5.12: Graphical VTC test for a robust inverter.
5.3. Characterization of Robustness 105
5.3.3 Unity Gain Method
A popular approach to determine V
IL,max
, V
IH,min
, V
OL,max
and V
OH,min
is the unity gain ap
proach (see [116] and the references therein). Currently, it is the method of choice in the deter
mination of noise margins of CMOS gates. In this approach, V
IL,max
and V
IH,min
are given by
the 1 slope points in the VTC. The output voltages can be deﬁned as V
OH,min
= f(V
IL,max
)
and V
OL,max
= f(V
IH,min
), see Fig. 5.13. This setup maximizes the sum of the two noise
margins [118]
NM
L
+ NM
H
= V
IL,max
−f(V
IH,min
) −V
IH,min
+ f(V
IL,max
). (5.6)
The maximumvalue can be derived by ﬁnding the zero of the derivative of NM
L
+NM
H
with
respect to V
IL,max
and V
IH,min
. Zero is reached at the unity gain points where the relations are
df(V
IL,max
)/dV
IL,max
= −1 and df(V
IH,min
)/dV
IH,min
= −1. The reader should note that
negative noise margins can occur for either NM
L
or NM
H
.
slope −1
slope −1
V
IH,min
V
IL,max
V
out
V
in
0
0
V
DD
V
OH,min
V
OL,max
V
DD
Fig. 5.13: Deﬁnition of input/output tolerance ranges with unitygain method.
A drawback of the unity gain method is that deﬁning V
IL,max
and V
IH,min
by the 1 slope
points is not a necessary condition when checking the validity of a VTC. Therefore, this
approach sometimes leads to negative noise margins for logic circuits because one of the 1
slope points does not exist. A negative value for a VTC would suggest that no regeneration of
input voltages to valid logic levels is possible. However, this is not true as can be seen from
the example in Fig. 5.14. For the VTC depicted in the ﬁgure, the unity gain method fails in
106 Chapter 5. Analysis of OFETBased Logic Circuits
the calculation of the noise margin as only one 1 slope point exists. Yet, the VTC possesses
three equilibrium points and hence, stable voltage levels for logic high and low exist.
slope −1
reflected VTC
inverter VTC
V
DD
V
OL,max
0 V
IH,min
V
in
V
DD
V
out
Fig. 5.14: Inverter VTC where the unity gain method fails but valid logic levels exist.
Another problemof the unity gain method is that taking the critical values V
IL,max
, V
IH,min
,
V
OL,max
, and V
OH,min
from a single VTC is not reasonable as device variations can alter the
VTC shapes. As a solution to this problem, upper and lower bound VTCs can be derived and
worstcase points for the critical values can be selected from these.
5.3.4 Method of Maximum Squares
The problem of noise margins was treated in [119, 120] by inspecting an inﬁnite chain of
inverters with identical VTCs. Noise can be modeled by voltage sources in series to the inputs
of the inverters in the chain. The worstcase noise condition occurs when noise sources are
present at the inputs of all gates with all low gate and high gate noise sources contributing in
the most deleterious way. This happens when driving the logic low inputs toward logic high
values and the logic high inputs toward logic low values.
In terms of noise analysis, the inﬁnite chain of inverters together with their associated
noise sources can be substituted by a latch consisting of two crosscoupled inverters with
noise voltages in series to the inputs. In this conﬁguration, only two inverters and two noise
sources have to be treated. The noise analysis is used for determining the noise levels which
force the latch to switch from a stored to the other logic state and consequently cause the
memory element to malfunction. The analysis can be carried out by inspecting the VTC of
the ﬁrst inverter in the latch together with a reﬂection about the x = y line so that for the
5.3. Characterization of Robustness 107
second inverter in the latch, the y axis serves as the input axis and the x axis as its output
axis. The same graphical representation was also used by Pierce [115] (see Section 5.3.1).
The latch retains the stored logic state as long as the two curves continue to intersect in three
points [121] even in the presence of deleterious noise, which will somehow shift the curves.
Fig. 5.15 shows a graphical representation of the extraction scheme. The latch in the left
part of the ﬁgure is used in the analysis and is equipped with noise sources. First/second
V
IN
/V
OUT
in the diagram are the input and output voltages of the ﬁrst and second inverter.
In order to obtain the noise margin for the worstcase series voltage, the maximum possible
square between the normal and reﬂected VTCis considered. The noise sources with maximum
allowable amplitude V
n,max
are represented by the equallysized sides of the maximum square
within the loop. Upon exerting V
n,max
at both noise sources in Fig. 5.15, the points of the
true and reﬂected VTCs at the corners of the maximum square coincide and there is only
one intersection point for both VTCs. For detrimental noise sources with amplitudes below
V
n,max
, there still exist three intersection points between the two.
1
1
noise first
noise
source
source
inverter
second
inverter
0
0
o
u
t
p
u
t
v
o
l
t
a
g
e
,
f
i
r
s
t
i
n
v
e
r
t
e
r
i
n
p
u
t
v
o
l
t
a
g
e
,
s
e
c
o
n
d
i
n
v
e
r
t
e
r
V
DD
V
DD
input voltage, ﬁrst inverter
output voltage, second inverter
V
n,max
V
n,max
Fig. 5.15: Graphical extraction of maximumsquare noise margin.
The approach yields the maximum square noise margin and hence, equal noise margins
for logic low and logic high states. In real gates, attainable noise margins for the logic high
and logic low stare are normally not equal [116]. Therefore, it is sometimes more favorable to
consider the maximum possible product between the noise margin for the logic low and logic
high state. However, the calculation of the maximum square is far more feasible than the
calculation of the maximum product. The maximum square noise margin can be calculated
by rotating the true and reﬂected VTCs by 45° and then calculating the differences between
the two curves. These differences are equivalent to the diagonals of the squares between
108 Chapter 5. Analysis of OFETBased Logic Circuits
diagonal points of the two VTCs. The calculation of the differences can even be carried out
in a circuit simulator as demonstrated by Seevinck and colleagues [122]. The procedure in
[122] consists of searching for the longest diagonal between the true and reﬂected VTC. Upon
rotating both curves by 45°, the original (x, y) coordinate system is translated into a (u, v)
coordinate system. In the latter coordinate system, the v values of the true and mirrored VTCs
can be subtracted in order to yield the diagonal. The magnitudes of the maximum positive
and maximum negative values correspond to the diagonal of the maximum square between
the two curves (see Fig. 5.16). [122] describes the true and reﬂected VTCs by the functions
y = F
1
(x) and y = F
′
2
(x). F
1
represents the true VTC and F
′
2
the reﬂected VTC of a second
gate with VTC F
2
. Owing to process variations or worstcase considerations, F
1
and F
2
may
differ. The transformation from (x, y) to (u, v) is
x =
1
√
2
u +
1
√
2
v, (5.7)
y = −
1
√
2
u +
1
√
2
v, (5.8)
so that y = F
1
(x) translates into
v = u +
√
2F
1
1
√
2
u +
1
√
2
v
(5.9)
and x = F
2
(y) into
v = −u +
√
2F
2
−
1
√
2
u +
1
√
2
v
. (5.10)
(5.9) and (5.10) can be used for calculating v as an implicit function of u. The maximum
value of the absolute difference between the two vs is equivalent to the maximumsquare noise
margin times
√
2. The solutions for v can be calculated in a circuit simulator using the setup
depicted in Fig. 5.17.
The noise margin as deﬁned by the method of maximum squares is not compatible with
the graphical test from Fig. 5.12. Unlike the unity gain method, it can easily cope with the
problem shown in Fig. 5.14. As long as there exists an opening in the loop between true and
reﬂected VTCs, a noise margin according to the method of maximum squares can be derived.
Like in the case of the unity gain method, calculating the maximum square from a single
VTC is not reasonable as device variations can alter the VTC shapes. Upper and lower bound
VTCs can be used for calculating worstcase maximum squares.
In work dealing with OFETbased noise margin calculations, the method of maximum
squares is preferably used (see [114, 123, 124]).
5.3. Characterization of Robustness 109
u
v
F
1
F
′
2
45
◦
y
x
F
1
(u) −F2
′
(u)
Fig. 5.16: Extraction of maximumsquare noise margin using a coordinate system rotated by
45° (adaption from [122]).
5.3.5 VTC Gain Considerations
In Section 5.3.1, the robustness of logic gates was treated by introducing the three equilibrium
points V
L
, V
M
, and V
H
for identity gates. V
L
and V
H
are stable equilibrium points while V
M
between them is metastable. Metastability is reached by a gain or slope of the VTC curve
at V
M
in excess of unity. For inverters, the VTC of a pair of inverters is inspected in order
to yield a logic identity function. If both inverters have identical VTCs, V
M
corresponds to
the intersection between the inverter VTC and the curve V
out
= V
in
. The inverter gain G
I
at V
in
= V
M
is critical to the robustness of the gates. Hence, the expression critical gain is
used in this work for g
crit
= G
I
(V
M
). In the case of inverters, the gain of the inverter pair
G(V
M
) = G
2
I
(V
M
) so that G
I
(V
M
) > 1 is required. Conventionally, G
I
(V
in
) ≤ 0 for all
sensible input voltages of an inverter so that a critical gain
g
crit
< −1 (5.11)
is required for robust operation. Therefore, the critical gain can be used as a qualitative ﬁgure
which represents the robustness of an inverter. To the knowledge of the author of this work,
the concept of critical gain is not used elsewhere in literature on noisemargin calculations.
Instead, the maximum negative gain g
max
= max G
I
 is sometimes used in other publications
110 Chapter 5. Analysis of OFETBased Logic Circuits
+
−
+
+
−
−
−
+
+
−
+
+
−
−
−
+
1
1
v
out
v
1
v
out
v
2
F
1
F
2
u
u
1
√
2
v
1
1
√
2
u
√
2v
out
+u
1
√
2
v
2
−
1
√
2
u
√
2v
out
−u
Fig. 5.17: Circuit to calculate maximumsquare noise margin according to [122].
(e.g. [125]) for describing the robustness of a logic gate.
The difference between the critical gain and the maximum negative gain can be explained
by using the inverter gain and VTC plot in Fig. 5.18. The plots show typical simulation results
for an inverter in currentsource conﬁguration. Channel length and width of the driving tran
sistor were L = 5 µm, W
D
= 1500 µm, and for the load transistor L = 5 µm, W
L
= 12 mm. In
the simulation, the driving transistor was mapped by a Linvar model while the load transistor
was mapped by a Level1 model speciﬁcally tailored toward reproducing the zero V
GS
curve.
More details about the simulations can be found in Section 6.3.1. The following values can
be extracted from the plot: V
M
≈ 5.15 V, critical gain g
crit
≈ 2.1, g
max
≈ 8.3.
In the VTC, g
crit
lies close to the negative unity gain while g
max
is located farther away.
This behavior is typical of OFETbased logic circuits without complementary devices for
the pullup and pulldown path. As will be shown on p. 142, the critical gain has a closer
relationship to the noise margin than the maximum negative gain.
5.3.6 Discussion of Characterization Methods
The method of equilibrium zones relies on knowledge about upper and lower bounds for the
VTC. This complicates application of the method because these bounds have to be found by
worstcase analysis, e.g. by timeconsuming stochastic simulations or by knowledge about the
inﬂuences of the device parameters. This knowledge has to be established beforehand for the
logic family in use. On the other hand, the method of equilibrium zones yields a tangible way
of determining the compatibility of logic gates. This behavior is very important in the case of
ratioed logic which suffers e.g. from biasinduced parameter shifts. As another advantage, a
5.3. Characterization of Robustness 111
gain
VTC
ratio = 8
i
n
p
u
t
=
o
u
t
p
u
t
−20
−15
−10
−5
0
−20 −15 −10 −5 0
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
o
u
t
p
u
t
v
o
l
t
a
g
e
[
V
]
−
−
>
input voltage [V] −−>
V
T
C
g
a
i
n
[
]
−
−
>
Fig. 5.18: Plot of inverter VTC and inverter gain for a gate in currentsource conﬁguration:
V
M
≈ 5.15 V, critical gain g
crit
≈ 2.1, g
max
≈ 8.3.
sort of worstcase analysis is implemented by this method as the lower and upper bounds mark
the expectable VTCconditions. Noise introduced by parameter variation and subsequent VTC
shift is explicitly treated and therefore, a precise analysis of static noise margins is possible.
The unity gain method is mainly used in the analysis of modern CMOS circuits. Noise
margins can easily be extracted from a measured or simulated VTC by considering the points
where the derivative of dV
out
/dV
in
= −1. However, there exist conclusions ([116]) that only
techniques based on embedding some area within the true and reﬂected VTCs give reliable
noise margin values for a broad range of possible VTCs. These results are consistent with
ﬁndings in this work (cf. p. 142). For nonCMOS circuits, noisemargin considerations based
on the unity gain method easily yield negative noise margins although the maximumsquare
method predicts the existence of positive noise margins.
With the method of maximum squares, the maximum square noise margin can easily be
obtained by simulation (see Section 5.3.1). A drawback of the method is that variations in
fabrication and environmental conditions are modeled with constant noise sources in the form
of series voltages. These variations lead nevertheless to nonlinear VTC changes. For example,
the noise margins for logic high and logic low states are affected differently as has been shown
in [126]. This problem could be solved by inspecting lowerbound and upperbound VTCs in
a similar way as in the method of equilibrium zones.
Evaluation of the critical gain of an inverter VTC is a quick method of checking the ro
bustness of the gate. The calculation of the maximum negative gain on the other hand is
more frequently used in literature on noisemargin calculations. It is more useful in the as
112 Chapter 5. Analysis of OFETBased Logic Circuits
sessment of CMOStype gates with wellbehaved VTCs. Both methods (critical gain and
maximum negative gain) suffer from calculation inaccuracies in the derivation of the gain
from the VTCs.
Generally, it is questionable whether voltage sources are sufﬁcient to map the noise con
tributions of parameter variations on VTC shapes in the derivation of noise margins. Further
investigation seems to be in order. For example, V
T
or λ shifts are more critical for the low
levels of CSLtype inverters (see Fig. 5.2). The resulting behavior will not be correctly repro
duced by shifting the VTC with voltage sources. Instead, worstcase considerations of VTCs
need to be used for deﬁning valid noise margins.
5.4 Timing Characterization
Timing characterization shows the attainable speed of a logic cell. Numerous timing ﬁgures
have been deﬁned as meaningful performance ﬁgures: rise, fall, and delay times. They mea
sure the response of a gate to a voltage pulse (e.g. [113]). The rise (fall) time is typically
measured from 10% to 90% (90% to 10%) of the difference between the logic low (high) and
logic high (low) state [101]. There also exist deﬁnitions using 20% and 80% thresholds [106].
The delay time t
D
represents the time interval between input and output levels being half way
between logic low and logic high states.
The delay time is an important timing ﬁgure in systems with a large number of logic gates
in series where the net delay between the input and the output of the system is large.
A step pulse is typically used for calculating the timing behavior of logic circuits. Analyti
cal expressions have been derived to predict these times. Popular methods rely on simplifying
assumptions like constant capacitances or negligible inﬂuence of feedback effects in the cir
cuits [127]. Moreover, the response time of a gate is normally longer than the transition time of
a step pulse at its input [128]. Hence, using step pulses overestimates the gate delay [129] and
more sophisticated analysis techniques have been developed to deal with the nonidealities of
logic gates (see e.g. [113, 128, 129, 130, 131, 132]).
Alternate deﬁnitions of relevant transition times can be found e.g. in [133], where the
input signal transitions are not restricted to unrealistically ideal steps but instead resort to
ramp signals with ﬁnite slopes. Fig. 5.19 details the deﬁnitions of the transition times, which
are derived as follows:
2 t
f
is the fall time indicating the time interval to decrease V
out
from its 90% to its 10%
point. This time is also referred to as slew [134].
2 t
r
is the rise time indicating the time interval to increase V
out
from its 10% to its 90%
point.
5.4. Timing Characterization 113
2 t
df
is the high–to–low delay time indicating the difference between the 50% point of the
input rising transition and the 50% point of the output transition from high to low.
2 t
dr
is the low–tohigh delay time indicating the difference between the 50% point of the
input falling transition and the 50% point of the output transition from low to high.
V
OH
V
OL
t
t
V
OH
V
OL
90%
10%
t
dr
t
df
t
f
t
r
50%
50%
V
in
(t)
V
out
(t)
Fig. 5.19: Deﬁnition of switching times based on an input signal with ramplike high and low
transition slopes.
In the case of unbalanced rise and fall times, an average propagation delay in the form of
t
P
=
1
2
(t
PHL
+ t
PLH
) can be deﬁned. Alternatively, the pair delay t
PD
represents the delay
of a pair of identical gates. The pair delay is equivalent to the time delay between the time
points where the input of the ﬁrst gate and the output of the second gate reach 50% of their
voltage swing [135].
The various response times presented in the preceding paragraphs always have to be re
lated to the capacitive load of the gate under characterization, i.e. the fanout. The fanout
(FO) is a value counting the number of identical gates driven by a speciﬁed output [101].
An increase in fanout leads to additional capacitance at the output of a gate. So, reports on
response times always need to specify the output capacitance for which the times have been
obtained. Similarly, a fanin (FI) can be deﬁned as the number of inputs a gate possesses
114 Chapter 5. Analysis of OFETBased Logic Circuits
[101]. For example, a 4input NOR gate has a fanin of four. The fanin can also be important
for the response times. This is due to the fact that input transistors inﬂuence the charging and
discharging of the output node by providing additional capacitance and/or leakage currents.
Schrom [125] points out that the relation between the response times and the average fan
in/fanout is difﬁcult to derive. Numerous models have therefore been developed to predict
this relationship [125, 134].
For numerical analyses in simulations, valid voltage levels for high and low voltages are
needed in order to calculate the measurement points. In CMOS concepts, there is no need to
derive logic levels as usually V
DD
/10, V
DD
/2, and V
DD
can be assumed. Conversely, the real
values of both logic levels in ratioed logic depend on device geometries and parameter varia
tions. Therefore, the voltage levels for these logic levels need to be established beforehand. A
practical approach in analysis, simulation, and measurement is to use ring oscillator circuits to
produce reasonable waveforms (e.g. [98, 125, 136]). A ring oscillator is a chain of inverting
gates with an odd number of stages. The simplest form of inverting gates can be inverters (see
Fig. 5.20) but other gates like NAND or NOR are also suitable. The output of each gate is
connected to the input of its successor. The output of the last gate is fed back to the input of
the ﬁrst gate. This conﬁguration leads to an oscillation with a frequency of f ≈ 1/(2nt
D
)
where n is the number of stages and t
D
is the delay per stage. The advantage of this approach
is that it yields the attainable voltage levels and transition times under realistic conditions. On
the other hand, n has to be chosen to be sufﬁciently large in order to allow the output voltages
of the gates to settle in response to rising and falling edges. But a large value for n also leads
to a long period time 1/f which has to be simulated.
1 1 1
Fig. 5.20: Schematic of a ring oscillator composed of inverters.
Generally, the deﬁnitions of the transit times need to be used carefully because the results
depend on the input waveform and output load [125]. Due to different rise and fall times, even
negative delay times may occur [108]. In order to model the inﬂuence of input waveform and
output loading, logic cells are usually characterized by tables or equations that relate delay
time and output slew as a function of load capacitance and input slew. By using tables or
equations, timing models for logic simulation and circuit synthesis are possible. In this work,
performance ﬁgures are only used for comparing different device generations or logic families.
Consequently, these advanced techniques are considered to be beyond the scope of this work.
The interested reader is referred e.g. to [137] and the references therein for a more detailed
discussion of the topic.
5.5. Automation of Circuit Characterization 115
5.5 Automation of Circuit Characterization
To carry out circuit characterization in an efﬁcient way, a high degree of automation is re
quired. Therefore, numerous software packages exist to aid the users in the process of circuit
analysis. In the ﬁeld of OFETbased semiconductor technologies, the analysis results assist
in the optimization of devices. Design automation tools can be used for determining various
electrical characteristics of circuits. These tools are referred to as circuit characterization
tools and can be broadly separated into characterization tools for logic circuits and general
characterization tools.
5.5.1 Tools for Characterization of Logic Circuits
Circuit characterization is frequently used for deriving various electrical characteristics of
logic circuits like timing, power consumption, or input capacitances in a form usable by digital
simulation and cellbased circuit synthesis. The latter transforms an abstract description of a
system into a real implementation by generating an integrated circuit. Logic cells like logic
gates or ﬂipﬂops are used as the building blocks of the system. The synthesis algorithms need
descriptions of these cells in order to take performance limits into account when numerous
inputs are connected to one single output, etc. Hence, issues like the determination of input
capacitance or timing behavior are emphasized in the characterization of logic circuits. The
focus in this domain is to provide simple models that can be used in calculations during the
synthesis or simulation process.
Characterization tools automatically characterize cells, i.e. provide model parameters use
ful for logic synthesis, logic simulation, timing and power optimization, or create data books
for designers. SPICE simulations are typically used for measuring and extracting the electri
cal parameters of logic cells. These parameters are calculated at individual process, voltage,
and temperature corners. A cell under characterization is embedded into a test circuit, where
it is evaluated with reasonable conditions.
Anonexhaustive list of commercial tools includes Z circuit ZChar [138], LibTech LibChar
[139], Synopsys NanoChar [140], Simucad AccuCell [141], or Magma SiliconSmart [142].
During the activities in this work, the author could only experimentally evaluate the open
source characterization tool Autochar [111]. The other packages were evaluated using the
respective operation manuals, user reports, or conference presentations. Autochar is written
in the popular scripting language Perl and is used for circuit characterization with Synopsys
StarHspice or Silvaco SmartSPICE. The tool automates the generation of test circuits useful
in the extraction of load delay, input capacitance, setup and hold times for Dtype ﬂipﬂops
(DFFs) as well as clock enable and clocktoQ time for clocked DFFs (Q=output of the ﬂip
ﬂop). Autochar is speciﬁcally tailored toward the characterization of CMOStype circuits.
116 Chapter 5. Analysis of OFETBased Logic Circuits
This property is reﬂected by the fact that e.g. delay times are measured between the ﬁxed
thresholds of 10 and 90% of the supply voltage V
DD
. In order to be useful in timing analysis
for OFETbased circuits, Autochar would have to adapt to varying voltage ranges for logic
levels. Moreover, the package does not provide the determination of static noise margins.
The analysis ﬂow is managed by a control ﬁle in Perl notation. References to netlists
and model sets are stored within this ﬁle as well as a speciﬁcation of the desired analyses
and characterization conditions. The tool reads the control ﬁle and generates the relevant test
circuit according to the speciﬁcations of the input vectors, waveform slopes, and gate loads.
Then, the tool calls the simulator and retrieves all required information from the simulation
results. The data are interpreted and a characterization report is generated.
In contrast to commercial tools, Autochar does not provide sophisticated automation of
cell characterization. The package does not automatically analyze the structure of cells un
der characterization in order to derive their logic functionality and required testbenches. It
is the responsibility of the user to deﬁne functionality and mode of input excitement. More
over, there exists no graphical user interface. Instead, Perlstyle conﬁguration ﬁles have to be
written. On the other hand, Autochar is open source software. Users can readily extend the
functionality of the package. However, the last ofﬁcial release of the software dates back to
the year 2000. Other tools like AccuCell are more ﬂexible when dealing with timing thresh
olds but do neither include analyses for static noise margins (see Section 5.3.2) nor graphical
user interfaces.
In general, characterization software for logic circuits already implements standard analy
ses necessary in the treatment of logic circuits (power consumption, circuit speed, etc.). Some
tools require only little work for the conﬁguration of the analyses. These tools try to derive the
logic functionality by inspecting the structure of the cells under consideration. Yet, commer
cial cell characterization packages are expensive tools where pricing starts at $55,000 [143].
Moreover, the tools mostly implement features not needed in the analysis of OFETbased
circuits with considerably lower structural complexity than the usual logic cells in CMOS li
braries. On the other hand, simple analyses like the automatic determination of frequencies of
ring oscillators or static noise margins are missing.
5.5.2 General Characterization Tools
The tools mentioned in the previous section focus on the treatment of logic circuits. In this
section, tools are discussed which characterize circuits in a general way. Normally, these
tools can also be used for automatically sizing the devices within a circuit, i.e. the lengths and
widths of the transistors or the resistance values of the resistors, etc., by use of optimization
strategies. There exist different tools with distinct applications, which also employ speciﬁc
5.5. Automation of Circuit Characterization 117
optimization schemes. Automatic sizing is less important for lowcomplexity circuits like
simple logic gates. These circuits can also be sized manually. Tools for circuit sizing get
important when circuits of higher complexities need to be implemented or optimized. In spite
of that, they provide interesting features for the analysis of OFETbased circuits like automatic
testbench generation or generic simulator interfaces. Hence, their evaluation is worthwhile.
In the following, a selection of tools with speciﬁc features is presented.
The schematic editor STAR [144] focuses on reusing designs in analog circuit design. The
idea is to add comments to circuit schematics in order to carry out predeﬁned functions from
a library. An execution engine then processes these comments in order to generate necessary
computation routines. The goal of STAR is to create a ﬂexible library which can be extended
with userspeciﬁed functions. The prototype tool is composed of four layers: a schematic
capture, a comment parser, an analysis layer, and a data processing layer at the bottom. The
system is implemented by a mixture of code in Tcl/Tk, Perl, and C. The central component
in STAR is the circuit schematic from which all further action is derived by inspecting the
comments embedded in it.
ASF (Analog Synthesis Framework) [145] employs simulation methods used by designers
to validate manual circuit designs during a circuit generation process. ASF incorporates mod
ular, reusable, and userconﬁgurable testbenches, which are called evaluators by the authors
of the package. The focus of ASF is to provide an easytouse and general tool where the
user can create any topology for any desired manufacturing process. The concept implements
an open framework for measuring arbitrary circuit characteristics with minimal effort. A ma
jor goal of ASF is to feature a robust optimization and search heuristic that operates within
reasonable runtime. In order to achieve this goal, a stochastic search engine is employed for
solution ﬁnding. A special feature of ASF is to encapsulate simulators within an abstract layer
so that any simulator with an appropriate interface can be used with the package. This concept
is called simulator encapsulation.
A commercial sizing tool is NeoCircuit from Cadence [146]. It automates circuit sizing
and uses the designer’s simulator, testbenches, and transistor models to automatically evaluate
circuit solutions generated by its solver. All explored sizing candidates are preserved in a
database for further analysis. A user report on NeoCircuit is given in [147]. The tool features
a text console used for controlling the ﬂow of the program as well as a graphical user interface
with almost the same functionality. For postprocessing purposes, data can be exchanged with
the engineering software Matlab and its opensource clone Octave.
Conn and colleagues [148] report a sizing system called JiffyTune. It utilizes a circuit
simulator called SPECS and an optimization engine called LANCELOT. JiffyTune requires
the speciﬁcation of a circuit schematic, input signals, a list of “tunable” transistors, with initial
widths, and a set of circuit performance requirements. The package determines the optimal
118 Chapter 5. Analysis of OFETBased Logic Circuits
assignment of transistor widths to achieve the requirements. SPECS is a circuit simulator
which uses simpliﬁed device models and eventdriven simulation to decrease simulation time.
LANCELOT, the optimization engine, repeatedly calls the simulator with different settings
for the transistor sizes in order to model the performance of the circuit. The authors in [148]
note that JiffyTune is driven by a textual control ﬁle and requires knowledgeable users. Nev
ertheless, it provides an interface to the Cadence design system.
The abovementioned packages focus on sizing transistors for a particular design, i.e. de
termining their optimal width and length. A more general characterization tool is the analysis
environment Decida, which was released as opensource in 2002 by Agere [149]. The envi
ronment allows a circuit designer to customize the set of analyses, to control and integrate
design tools, and to provide analysis and plotting capabilities [150]. Decida is implemented
using the scripting language Tcl/Tk and can be extended very ﬂexibly. Like JiffyTune, it
resorts to the optimization engine LANCELOT in order to optimize circuits.
The characterization tools discussed in this section focus on the characterization and/or
optimization of individual circuits. Therefore, their view and user concept centers on a par
ticular design (e.g. operational ampliﬁer, etc.) in the form of a netlist or schematic. Some
tools do not automatically generate testbenches. Instead, the users compose their own test
benches and deﬁne which parameters to optimize. Other tools already provide pregenerated
testbenches or allow the users to compile reusable libraries of testbenches.
The OFETbased approach discussed in this work focuses on bringing together models
and circuits and carrying out analyses on the combination of both. The circuit is not central
to the analysis but the results obtained from combining it with the transistor models. This
approach is more similar to batchmode circuit characterization of logic circuits. To carry out
this kind of analysis with the abovementioned general analysis tools, an additional step of
compiling a tractable schematic description would be necessary. Moreover, the existing tools
do not provide special means to generate and manage device models or heterogeneous sets of
data (schematics, models, data vectors, etc.).
5.5.3 Discussion
Characterization tools come in two ﬂavors: specialized characterization tools for logic circuits
and general circuit analyzers. The former focus on creating parameter sets useful in digital
simulation and synthesis. They work on libraries of gates with given models. Variations of cir
cuit or device parameters are not considered by these tools but have to be provided by the users
in the form of special models. General analysis tools on the other hand focus on the ﬂexible
manipulation of circuit parameters. Their primary building blocks are netlists or schemat
ics. These tools do not carry out batches of different analyses with different testbenches to
5.6. Chapter Summary 119
generate.
Individual tools manage design databases into which all generated data can be included.
Yet, since the tools do not completely cover the analysis of OFETbased circuits and transis
tors, e.g. modeling data are not included in the database.
From the user’s point of view, a combination of the cell characterization scheme (auto
matic testbench generation for different combinations of models and circuits) with the ﬂex
ibility of general circuit analyzers (parameter variation or performance optimization) would
considerably improve efﬁciency of the tools. This would also reduce the work in planning and
maintaining the computer experiments because the testbenches are automatically generated by
the computer.
For the human analysts who employ circuit characterization, implementation of the fol
lowing features by characterization tools is desirable:
2 Circuit Management – Alternative circuit designs need to be managed by the charac
terization tool. This allows the users to select benchmark circuits from different circuit
technologies (e.g. logic gates with load transistors in currentsource conﬁguration, etc.)
without the need to compile these libraries themselves. The libraries should also be
reusable in later analyses.
2 Reusable Analysis Procedures – The procedures for deriving the electrical performance
of circuits need to be reusable with different sets of models, model parameters, and cir
cuits to use. Even the operating conditions like supply voltage or ambient temperature
need to be adjustable.
2 Documentation of Analysis Procedures – In order to facilitate documentation and back
tracking of unexpected analysis results, the analysis procedures need to be documented.
2 Flexible Compilation of Analysis Procedures – General analysis procedures should be
easy to compile. In the analysis of OFETbased logic circuits, standard procedures for
deriving meaningful performance ﬁgures still need to be established. Therefore, the
analysis tools must be ﬂexible enough to allow the users to reconﬁgure the analysis
procedures.
5.6 Chapter Summary
In this chapter, procedures for characterizing OFETbased logic circuits were discussed. The
following items summarize the discussion results:
2 Circuit analysis with emphasis on organic electronics is still in the early stages. Only
few publications analyze the impact of OFET parameters on circuit performance.
120 Chapter 5. Analysis of OFETBased Logic Circuits
2 Characterization procedures established for traditional semiconductor technologies can
also be used for analyzing the performance of OFETbased logic circuits. These proce
dures include e.g. static noise margin determination, delay measurement, etc. However,
the methods have to be applied with care because they often predict false results when
dealing with OFETbased circuits. For example, the unity gain method of deriving noise
margins occasionally predicts negative noise margins for functional circuits. Besides,
deriving delay times using step pulses does not reﬂect the clock generation schemes in
organic logic circuits (where ring oscillators provide clock signals).
2 Existing tools for circuit characterization are not adapted to the special needs of OFET
technologies. Integration of transistor modeling is missing, or basic analyses like the
calculation of maximumsquare noise margin are not included. Moreover, the tools are
speciﬁcally designed for skilled users of simulators like SPICE and difﬁcult to work
with for the occasional and nonexpert user. Often, ﬂexible combinations of different
analysis steps into more complex analyses is not possible or requires special program
ming knowledge.
Chapter 6 will detail an analysis concept in which OFETbased logic circuits can be an
alyzed. The concept provides a ﬂexible interface which allows nonexpert users to compile
powerful analysis scripts in a graphical way. OFET modeling and data management are also
included.
121
Chapter 6
Analysis Concept
This chapter presents an analysis concept that automates modeling of organic transistors and
characterization of OFETbased logic circuits. The basic idea is to integrate the various soft
ware tools needed during the analysis into one single platform. The collaboration between
these tools is automated and the required data are managed in a coherent fashion. This ap
proach allows the device analyst to concentrate on improving the devices and circuits rather
than transferring data between different tools and manipulating result vectors in order to ex
tract meaningful performance ﬁgures. The novelty of the concept is the combination of all
of these tasks in a single environment. Automation of the analysis is reached by a graphical
scripting concept, which allows nonexpert users to compose new or alter existing analysis
procedures. With this framework, routine work is delegated to the computer.
The chapter is organized in the following way. First, the typical analysis ﬂow is exam
ined in order to identify drawbacks of existing solutions. Subsequently, the novel concept
is detailed. Finally, circuit analyses using an experimental implementation of the analysis
framework are demonstrated.
6.1 Typical Analysis Flow
The optimization of OFET devices and circuits based on circuit simulation is an iterative
process. In practical research work, the process typically consists of the following steps (cf.
Fig. 1.1):
1. Transistor models are extracted from the measured curves.
2. Netlists are generated. These contain test circuit, devices under test, and the necessary
models. The user has to compile the respective circuits into a netlist and to include the
model descriptions.
122 Chapter 6. Analysis Concept
3. The circuit simulator is executed, which interprets the netlists, simulates the circuits,
and reports calculated results.
4. The analysts (researchers or computer programs) interpret the results and generate data
sheets from the information. They ask questions like the following:
2 What is the performance of a given device generation in logic circuits?
2 Which device and circuit parameters deﬁne performance (e.g. robustness against
interfering noise, circuit speed, power consumption, etc.)?
2 Where have the parameters to be pushed to in order to increase the circuit perfor
mance?
Answering these questions involves variation of the circuit and model parameters so
that different device generations and parameter sets can be taken into account.
Existing software tools can cover the individual aspects of the process. The analysis cycle
is complicated by manually coordinating the steps due to the following reasons:
2 Data have to be transferred between the tools called in the individual operations. Model
sets need to be included into the netlists used in the simulations or circuits have to be
inserted into the testbenches, etc. These processes are timeconsuming and error prone.
2 Input data and analysis results have to be preserved in a database in order to document
the analysis process, to record the improvements of a fabrication process, or to support
replay of the analyses. Possibly, many iterations of the analysis are needed so that
preservation of data can quickly get out of hand.
2 The users need to understand numerous tools and data formats. After longer periods of
not working with the analysis tools, this knowledge often has to be reactivated.
The author of this thesis concludes from practical experience that existing tools will fail
to be used in the analysis of OFETbased devices and circuits as long as the following issues
are not resolved:
1. A single software environment is needed. It must be easy to use. The users, who
normally do not work in the domain of circuit simulation, are not interested in learning
to use the individual tools. Instead, they want to focus on getting their results quickly
and in a highly automated way. Therefore, they prefer graphical user interfaces and easy
access to all relevant data and functions.
6.1. Typical Analysis Flow 123
2. The environment must integrate modeling of the transistor devices in an easytouse
fashion. Contrary to more traditional semiconductor technologies, vendorsupplied
transistor models do currently not exist in organic electronics. For the user of OFETs,
modeling is therefore most often the starting point of the analysis cycle.
3. The environment must provide automatic generation of test circuits. These test circuits
include e.g. setups for measuring performance ﬁgures like noise margin or circuit speed.
4. The environment must provide preconﬁgured analysis procedures and libraries of pop
ular logic gates. For the users, it is important to have template setups and gates which
they can reuse and adapt to their special requirements. Otherwise, the users would have
to create the necessary circuits and analysis procedures manually.
5. In the generation of test circuits, transistor models must be easy to replace. There exist
many variations of OFETs (alternate semiconductor / dielectric / electrode materials,
topgate or bottomgate topology, etc.) and hence many model types. A generic analysis
tool must therefore manage different model types in all of its analyses. Here, model
management is understood to include the ability to conveniently replace models in test
circuits and analysis setups.
6. The analysis procedures must be easy to adapt to new requirements or to include novel
extraction schemes. Users prefer generic analysis procedures which they can manipu
late and ﬂexibly extend.
7. In the course of an analysis, model parameters or transistor geometries may have to be
varied. A framework must therefore provide mechanisms to dynamically vary model
and device parameters.
8. The environment must automatically collaborate with a variety of circuit simulators,
i.e. create simulationready netlists for the test circuit, execute the target simulators, or
extract the simulation results. This property is highly desirable because many different
simulation tools are available.
Existing tools easily cover individual aspects of the above list. But missing is an inte
gration framework in which all of these tasks are handled in a coherent fashion. This work
provides the concept for such a framework, which automates the analysis of novel OFET
devices by use of a generic, coherent, and ﬂexible analysis system.
124 Chapter 6. Analysis Concept
6.2 Novel Analysis Concept
The discussion in the previous section showed that an analysis ﬂow constructed from tradi
tional EDA tools suffers from numerous drawbacks. Therefore, a novel analysis concept has
been developed in this work. The concept describes how OFETrelated data are stored and
analyses of device performance are carried out. The novelty lies in the uniﬁed and object
oriented organization of data, analysis scripts, and analysis reports.
The concept consists of an interactive modeling and simulation environment, and deﬁnes
a set of central ideas:
2 Data Management: All relevant data items used in the analyses are stored in a hier
archical data tree similar to a directory structure on a computer disk. Data items can
be measurement data, model sets, circuit descriptions, or analysis scripts. Each data
item in the tree can also have a documentation text and userdeﬁned properties. The
hierarchical data tree serves as the analysis database and stores analysis procedures and
libraries of popular logic gates as well as usersupplied measurement data.
2 Modeling System: The modeling of devices is integrated into the framework. Model
sets can be created and altered within the software environment. A standardized mod
eling interface allows the users to add novel model extractors. This modeling interface
deﬁnes how the modeling tools are conﬁgured and used.
2 Analysis Control: Users employ analysis scripts to automate the analysis ﬂow. Each
script consists of a sequence of individual analysis steps which can be deﬁned and edited
using a graphical user interface. Parameters of circuits and models can be altered within
the scripting system. Batchmode analyses with automatic generation and simulation of
different testbenches are possible. A standardized execution interface allows the users
to include novel analysis steps. The execution interface deﬁnes the way how an analysis
step is graphically conﬁgured and executed.
2 Simulator encapsulation: Circuit simulators are integrated into the analysis concept by
use of standardized simulator interfaces. The interfaces cover netlist generation, sim
ulator control, and result propagation. This technique is known as simulator encapsu
lation [145] and has successfully been used in the optimization of circuits. Simulator
encapsulation is highly desirable as only the simulator interface has to be adapted in
order to link a novel circuit simulator to the analysis framework.
The following paragraphs provide a more detailed discussion of the concept.
6.2. Novel Analysis Concept 125
6.2.1 Data Management
Efﬁcient data management provides a sensible and easytouse way of managing heteroge
neous sets of data. Efﬁciency can be reached by using a uniﬁed datamanagement scheme,
i.e. all relevant data objects are stored within a coherent data repository. The analysis cycle
for OFETbased circuits typically includes objects of different types:
1. measurement data,
2. parameter sets for transistor models,
3. logic gates, i.e. circuits,
4. analysis scripts.
In the concept presented here, data are organized by storing all objects in a single hierar
chical structure. This structure can be accessed by the user in the form of a hierarchical data
tree. Hierarchical in this context means that objects can contain other objects. Drawbacks of a
hierarchical data tree are that more efﬁcient data management schemes which are utilized by
database management systems (DBMS) are not available, memory consumption is increased,
and searching the whole tree can take a long time. On the other hand, the advantage of the
hierarchical tree is that data can easily be structured, i.e. grouped, according to the desires of
the users. This increases ﬂexibility and ease of use because the users can organize and handle
the data according to their needs.
In order to facilitate use of the hierarchical data tree, it can e.g. be represented in a graph
ical way similar to the ﬁles of a computer disk by the ﬁle browsers of popular operating
systems. With a graphical user interface, nonexpert users do not need to learn the commands
of a system which works with batchmode command scripts or an interactive command line.
Moreover, most computer users are accustomed to the concept of a graphical ﬁle browser. The
principal idea of the concept is to organize data in a hierarchical tree of different items so to
cover all important datamanagement aspects of the analysis cycle.
Fig. 6.1 shows an example of a hierarchical data tree. Data types deﬁned by the concept
are:
2 analysis (icon )
An object of this type represents an analysis procedure, which deﬁnes the individual
steps in the characterization of circuits and models. In the analysis concept, analysis
procedures are represented by treeform scripts implementing execution trees. Details
about treeform scripts and execution trees are provided in Section 6.2.3.
126 Chapter 6. Analysis Concept
Fig. 6.1: Example of a hierarchical data tree.
2 circuit (icon )
An object of this type represents a circuit useful for testbench generation. The object
holds information on the structure and connectivity of the circuit. The structure deﬁnes
which devices are present in the circuit and how they are connected with each other.
Netlists or schematics are possible. The connectivity deﬁnes which terminals of a circuit
to the outer world are present in the circuit, their types (input, output, bidirectional, or
supply node), which parameters exist for the circuit (e.g. the dimensions of the critical
devices), and their default values.
6.2. Novel Analysis Concept 127
2 container (icon )
This object type enables the introduction of data hierarchy by acting as a folder into
which other objects can be grouped. It is comparable to a directory in a ﬁle system of a
computer.
2 model (icon )
An object of the type “model” is used for representing a transistor model in the analysis
system. The simplest form of a model is a property list in which the individual entries
denote the parameters of the model. The model can be bound to a model extractor,
which is used for deriving the model parameters.
2 wavevar (icon )
“wavevar” objects contain waveform data like measured current curves, xaxis values
in simulations or measurements, etc. This kind of object is generated when a data ﬁle is
imported or simulation results are stored in the data tree.
2 waveﬁle (icon )
A waveﬁle object is created when a data ﬁle containing measurement or simulation
results is imported into the data tree. The waveﬁle object represents the imported data
ﬁle and contains either wavevars or again waveﬁles.
In order to provide moredetailed descriptions of objects, meta data can be assigned to
objects. Meta data are a form of additional data describing the object [151] they belong to.
In the concept detailed in this chapter, meta data are used for providing classiﬁcation and
documentation of objects. The following forms of meta data are used:
2 A documentation text which is attached to an object so to document its use or method
of creation in a form easily readable by humans.
2 Property lists provide tables with pairs of names and values where additional object
related data can be stored in a more formal manner than in a documentation text. This
allows computer routines to directly access these tables. Therefore, search queries like
“list all objects with the property level > 1” get possible. The property list can e.g.
contain the creation date of the object, the ﬁle from which the object was created, or in
the case of transistors, the width and length of the device, etc.
Using a combination of documentation text and property lists allows a thorough descrip
tion in a form easily readable by humans and machines. Fig. 6.2 sketches the relationship
between objects and associated data.
128 Chapter 6. Analysis Concept
object
(text, ...)
documentation
value prop name
properties
type−specific data
e.g. waveform,
netlist, etc.
Fig. 6.2: Data association for objects: documentation, properties, typespeciﬁc data (wave
forms, netlists, etc.).
6.2.2 Modeling System
In the analysis framework, models are represented by objects of type “model”. These objects
use model extractors for extracting model parameters from measured curves. In this work, a
model extractor is regarded as a software module used for conﬁguring a model object. The
model extractor can be a piece of software entirely contained within the framework core or
an interface to an external program which carries out the actual parameter extraction. The
generator provides a dialog in which the extraction process is set up, carried out, and possibly
repeated later on with different settings.
Standardized Modeling Interface
Model extractors are used for transforming measured device characteristics into parameter
sets for a special model. They are realized in the analysis framework by use of dynamically
loadable modules. Each module provides a standardized function to create a graphical dialog
used for creating or modifying a model set. The details of the mechanisms are speciﬁc to the
actual implementation of the analysis framework and will not be discussed here.
6.2.3 Analysis Control
Automatic device and circuit analysis is an important aspect of the analysis cycle. The task
is handled by analysis control. In this work, the term analysis control refers to the deﬁnition
6.2. Novel Analysis Concept 129
and execution of analysis procedures.
Analysis Steps
The idea in this work is to decompose analysis procedures into smaller steps so to increase the
ability to modify them as opposed to monolithic analyses used e.g. in the cell characterization
tool Autochar (see Section 5.5.1). The individual analysis steps can be as simple as the def
inition of variables or as complex as the determination of the static noise margin. During its
execution in the course of the analysis, each step takes input parameters and generates output
parameters (see runtime data under the heading Analysis Sequencing on p. 130). The output
parameters can be propagated to successive steps so to create dependent steps. By doing so,
constructs like the determination of rise and fall times get possible where the attainable volt
age levels for the logic states are derived in one simulation step and propagated to the actual
timing simulation.
Each step is conﬁgured using a graphical dialog. An example of such a dialog in an
implementation of the concept is shown in Fig. 6.3, where a step to derive high/low voltage
and other important parameters from a gate’s voltage transfer characteristic is conﬁgured.
Fig. 6.3: Conﬁguration dialog for an analysis step.
By subdividing analysis procedures into smaller steps, questions like “How does the
threshold voltage inﬂuence the static noise margin and the rise time?” can be answered. This
is carried out by composing an analysis procedure that consists of a sweep of the threshold
voltage. The sweep carries out the extraction of static noise margin and the rise time (two sub
ordinate steps of the sweep). In this way, circuit characterization can be used as an exploration
tool.
It can be argued that circuit simulators already provide features for this kind of analysis.
Sophisticated SPICE simulators already contain powerful sweep directives and batchmode
130 Chapter 6. Analysis Concept
simulations. However, users of these tools have to manually write the testbenches and post
process the results.
By subdividing analysis procedures into smaller steps, more time is needed to conﬁgure
the numerous steps. Consequently, providing specialized analysis programs for each kind of
analysis scenario seems to be more convenient. These programs can contain all necessary
conﬁguration items in one dialog and carry out the simulations as predeﬁned by the program
developer. Moreover, utilization of an external simulator can be optimized for maximum
simulation speed because the analysis programs already know in which way the simulator is
used. While this approach is comfortable if only one analysis has to be carried out all the
time, it is not very ﬂexible. If a user wants to change the analysis ﬂow then reprogramming
might be necessary or the original program design has to foresee all sensible modiﬁcations to
the standard ﬂow.
Therefore, subdivision of the analysis procedure into smaller steps has been selected in this
work to implement the analysis ﬂow. Existing analyses can be reused as templates for other
analyses. Moreover, no reprogramming of the underlying computer program is necessary if
smaller modiﬁcations are introduced to the ﬂow. Analyses can also be cascaded into more
powerful extraction schemes.
Analysis Sequencing
Control of the analysis ﬂowtakes place by deﬁning a sequence of analysis steps to be executed.
The sequence is comparable to a computer script carrying out the individual steps and is stored
in the data tree in the form of an object called “analysis”. In this way, analyses can be treated
like normal data, i.e. can get documentation text or property lists and are stored together with
the data they are used for.
Individual steps of an analysis sequence can propagate results to successive steps by use
of runtime data. Runtime data is a form of dynamic data which only exists during execution
of the analysis procedure. The individual types of runtime data are:
2 Dynamic variables are used for propagating results between analysis steps or for varying
parameters.
2 Dynamic models are dynamic copies of models deﬁned in the data tree. Their purpose
is to allow temporary variations of model parameters in analyses. If e.g. the threshold
voltage of a model shall be varied in an analysis, a dynamic copy of the model in the
data tree is generated and the parameter “threshold voltage” of this dynamic model is
changed in the variation.
2 Dynamic circuits operate similarly to dynamic models. They are temporary copies of
6.2. Novel Analysis Concept 131
circuits deﬁned in the data tree. Their introduction allows varying parameters of a circuit
without affecting the original circuit deﬁnition.
2 Analysis results are the data vectors displayed at the end of the analysis. They are
generated and populated during runtime of the analysis.
The analysis sequences are formulated by treeformscripts which deﬁne the actual ﬂow. “tree
form” means that the steps in the sequence are organized as hierarchical trees where the in
dividual items are described in textual form. Treeform analysis scripts will also be denoted
as execution trees in the following. The term “script” refers to the fact that the sequences are
interpreted step by step each time the analysis process is started. The user creates the ﬂow by
instantiating steps in the execution tree. Fig. 6.4 shows a schematic example of an execution
tree.
The individual steps are executed in the order they appear in the execution tree. Subtrees
are executed before the step following their parent is processed. In Fig. 6.4, steps 3.1 and 3.2
are executed before step 4 is done. Step 3 could be a variable sweep from one value to another
or an optimization loop, etc.
step 2
step 3
step 4
step 3.1
step 3.2
analysis
step 1
Fig. 6.4: Schematic example of a simple execution tree for an analysis procedure.
With treeform scripting, analysis procedures can be expressed in an easytoread fashion.
Owing to its graphical user interface, treeform scripting enables nonexpert users to compose
their own procedures without the need to get acquainted with a new scripting language. The
treelike form is an intermediate form between a true programming language using text scripts
and a graphical programming language oriented toward dataﬂow modeling.
Aprogramming language using only textual scripts provides the most powerful description
as the procedures and functions can ﬂexibly be combined. Nevertheless, maintenance and
further development of text scripts requires programming skill and adherence to certain coding
132 Chapter 6. Analysis Concept
styles, i.e. consistent use of names for functions and variables, intense use of comments, etc.
Textual scripting languages include Perl, Tcl, Python, etc.
Dataﬂow languages describe programs by a graphical ﬂow chart. The chart consists of
functional elements in the form of icons or labeled blocks and connections between them.
The program developer deﬁnes the required function by drawing the elements and connections
between them. The connections determine the data ﬂow. Examples of dataﬂow languages are
LabVIEW from National Instruments [152], Simulink from The Mathworks [153], or Caslon
Flow from Gradual Software [154]. With dataﬂow languages, nonexpert users can develop
programs by drawing ﬂow charts. Moreover, the program already documents the ﬂow in an
intuitive way and visualizes the propagation of data. On the other hand, composing constructs
like switch operations between different options can be difﬁcult to draw. In addition to that,
reading complex ﬂow charts can also be troublesome.
Consideration of both styles (textbased coding and drawing of ﬂow charts) led to the ap
plication of an intermediate style, viz. treeform scripting. The ﬂow elements are described
in textual form but are conﬁgured using graphical dialogs. The operation sequence is de
scribed by an execution tree. With this scripting style, the scripting environment is easier to
implement and to use than a textbased scripting system as nonexpert users can conﬁgure
and alter programs. For small modiﬁcations or rearrangements of steps, treeform scripting is
the most compact description scheme. Moreover, the analysis concept already uses treeform
descriptions to hierarchically structure analysis data in the data tree. On the other hand, the
propagation of results from step to step is less intuitive as in dataﬂow programming. Results
are propagated between steps by use of variables. A step “determine high voltage” would
write its results to the variable “vhigh”. A step “determine delay time” could then refer to this
variable in order to conﬁgure the input waveform needed to extract reasonable delay times.
The mechanisms of using variables are hidden in the conﬁguration dialogs of the individual
steps. The variables are more difﬁcult to track when compared to textual programs or data
ﬂow drawings. For small programs, tracking the propagation of results is not difﬁcult, but for
larger projects, this might confuse users.
The behavior of the individual analysis steps is programmed in the underlying analysis
framework. Basic analysis steps are:
2 Deﬁnition of a variable – deﬁnes a variable to be used in subsequent steps. The variable
exists as runtime data until the analysis is ﬁnished.
2 Deﬁnition of a model – deﬁnes a dynamic model to be used in subsequent steps. The
model exists only during runtime of the analysis. It can be used for changing parameters
of existing models in the data tree without affecting the original model.
2 Deﬁnition of a circuit – deﬁnes a dynamic circuit for use in subsequent steps. The circuit
6.2. Novel Analysis Concept 133
exists only during runtime of the analysis. It can be used for temporarily changing
parameters of existing circuits in the data tree.
2 Deﬁnition of default connectivity – deﬁnes what to do with unused terminals in one
of the testbenchgenerating steps. This directive tells the testbench generator which
values to assign to supplyvoltage terminals or to unused input pins of the circuit under
characterization.
2 Sweep a variable – creates a variable, assigns the starting value to it and executes all
steps subordinate to the sweep. After all subordinate steps have been carried out, the
next sweep value is assigned to the variable, the subordinate steps are again carried out,
etc.
2 Accumulate a vector – creates a data vector for reporting at the end of the analysis.
More sophisticated analysis steps which also involve execution of external simulators include
for example:
2 Analyze the voltagetransfer characteristic of a gate – determine the nominal voltage
for logic high/low state and critical gain of a logic gate. At runtime, this step constructs
a testbench which contains the gate under characterization as a series of two instances
in a chain. During execution of the step, a simulator is called to analyze the testbench.
The nominal voltage levels and the critical gain are extracted and reported in runtime
variables. Fig. 6.5 sketches the testbench and the expected simulation results for the
VTC determination.
+
−
0
o
u
t
p
u
t
v
o
l
t
a
g
e
input voltage
DUT DUT
V
out1 V
out2
V
in
V
out1
V
in
V
out2
Fig. 6.5: Schematic of a testbench and expected simulation results for VTC determination.
The circles in the voltage plot denote the voltages for the logic states low, unstable, and high.
DUT is the device under test, i.e. the gate to be analyzed.
134 Chapter 6. Analysis Concept
2 Analyze ring oscillator – determine the oscillation frequency of a ring oscillator as well
as rise and fall times. A testbench is generated in which the individual gate is mounted
multiple times so to form the ring oscillator. This testbench is used for simulating
the oscillation frequency and extracting timing information of the ring oscillator (see
Fig. 6.6 for a sketch of testbench and expected simulation results).
0 time
o
s
c
i
l
l
a
t
i
o
n
v
o
l
t
a
g
e
DUT DUT DUT
V
RO
V
Low
V
RO
V
High
Fig. 6.6: Testbench and expected simulation results for analysis of ring oscillators. DUT is
the device under test, i.e. the gate to be analyzed.
2 Determine on and off currents of a transistor device. A single transistor is simulated
and analyzed in order to get on and off currents. The off current is regarded as the
current at maximum magnitude of drainsource voltage and minimum magnitude of
gatesource voltage. The on current is regarded as the current at maximum magnitude
of drainsource voltage and maximum magnitude of gatesource voltage.
2 Determine maximumsquare noise margin – extract the maximum square representing
the noise margin of a gate. Details about the determination of the maximumsquare
noise margin are presented in Section 5.3.4.
Standardized Execution Interface
Analysis steps are realized in the analysis framework by use of dynamically loadable software
modules. Each module provides a standardized function to create an objectoriented repre
sentation of the analysis step. The representation contains interface functions to load/setup,
graphically edit, execute, and save the analysis step. The details of the mechanism are speciﬁc
to the actual implementation of the analysis framework and will not be detailed here.
6.2. Novel Analysis Concept 135
6.2.4 Simulator Encapsulation
The analysis framework links to circuit simulators by use of simulator encapsulation [145].
This technique refers to the integration of simulators into a design framework in a generic way.
The simulation tool collaborates with the framework through an abstraction layer. This layer
deﬁnes a generic interface between the framework and target simulators. When a simulator
shall be integrated, no changes to either the framework core or the simulator are necessary.
Instead, only the interface between them is adapted. The interface provides the following
features:
2 Netlist generation – A generic description of the circuit structure is passed to the in
terface. The underlying interface code then constructs the appropriate netlist for the
simulator.
2 Simulator control – The simulation process is initiated.
2 Result propagation – The relevant information in the output ﬁles of the simulation pro
cess is transferred to the framework core.
Reasons for introducing simulator encapsulation are:
2 Different research teams utilize different simulator tools. The implementation of the
UMLVRH model disclosed in [65] (see Section 3.2.4.3) employs the circuit simulator
Eldo and models devices with VerilogA, the analog subset of VerilogAMS. Model
ing in this work was done with the opensource circuit simulator tclspice [155]. This
simulator resorts to the SPICE extension XSPICE [93] and model descriptions com
piled from C code. In order to be a generic tool, the framework has to disregard the
peculiarities of the individual simulators and has to use a generic interface.
2 Different simulators use different directives to include models. Mentor Graphics’ Eldo
uses the y directive to include external models, tclspice and all other XSPICE deriva
tives use the a directive, while e.g. Tanner TSpice resorts to the x (or subcircuit)
directive. These differences have to be dealt with in the generation of netlists.
2 Some simulators like the original Berkeley SPICE / XSPICE suite do not support param
eterizable subcircuits. These are nonetheless needed to provide variation of logic gates
in the course of analyses. The netlist generators of the encapsulation interface have
to translate these parameterized subcircuits into representations suitable for Berkeley
Spice / XSPICE.
2 If modeling systems like VHDLAMS, VerilogAMS, or Saber/MAST are used, netlists
are composed in a way different from SPICE. The netlist generator must also deal with
these modeling languages.
136 Chapter 6. Analysis Concept
2 Each simulator has its proprietary format for simulation ﬁles. The respective interface
must translate the data into a format readable by the framework core.
In an implementation of simulator encapsulation, a generic interface is deﬁned. Interac
tion with simulators takes place by use of this interface. A dedicated implementation of the
interface is provided for each simulator. Netlists are expressed in an intermediate form by
routines of the framework core and transferred to the simulator interface, which in turn gener
ates the real netlist fed into the simulator. With this twostep approach, simulators can easily
be replaced by other tools. On the other hand, the process of netlist generation is prolonged
because the description has to be translated into the target format.
Experimental tests with a prototype implementation of the framework showed that this
translation can affect the time needed to carry out the analysis. This behavior can prolong the
analysis if small circuits are simulated numerous times with tiny variations. A scenario of this
kind is the numerical optimization of circuits. However, the translation process can be sped
up by appropriate programming techniques. Therefore, performance issues are not a major
concern. Moreover, users will not accept the framework if it works with only one particular
simulation tool. Therefore, the advantages of direct netlist generation were sacriﬁced to a
more ﬂexible simulator interface.
6.3 Analysis Examples
The purpose of the following sections is to demonstrate the application of the analysis frame
work in the exploration of OFETbased logic circuits. Basic logic gates will be evaluated
in the examples using an experimental implementation of the methodology named DCI (De
sign and Circuit Investigator). The simulations are based on the model parameters derived
in Section 4.3.6. The extraction of performance ﬁgures (operational speed, attainable volt
age values for logic levels, and noise margin) of inverters, NOR gates, and ring oscillators
in currentsource conﬁguration is demonstrated. The following deﬁnitions for voltage levels
representing logic states will be used:
2 high – The stable voltage level closer to the supply voltage (V
DD
).
2 low – The stable voltage level closer to zero.
6.3.1 Analysis of an Inverter in CurrentSource Conﬁguration
A popular circuit technology implementing logic gates is the currentsource conﬁguration
(cf. Fig. 5.1). Currently, it is the method of choice in order to implement OFETbased logic
circuits. The load element of logic gates in currentsource conﬁguration is a transistor with
6.3. Analysis Examples 137
both gate and source connected to the output. The ratio between the load transistor M
L
and
the driving transistor M
D
as well as the supply voltage can be varied in order to get optimal
gate performance in terms of circuit speed and robustness.
Analysis Objective
The inﬂuence of the geometry ratio between load and driving transistor on the robustness (i.e.
noise margin) and speed of logic gates in currentsource conﬁguration shall be investigated.
Circuit speed will be measured by the oscillation frequency of a ring oscillator and the rise and
fall times of the output of one of its inverters. This approach requires more computation than
traditional timing extraction schemes like simulating the response to a step pulse but results
in more realistic waveform shapes.
The following settings shall be used in the analyses:
2 an inverter with load transistor in currentsource conﬁguration,
2 both load and driving transistor are ptype conducting and work with the same parameter
set,
2 channel length L = 5 µm,
2 channel width of driving transistor W
D
= 1500 µm,
2 channel width of load transistor W
L
= r × W
D
, where r is the ratio between the width
of the load transistor and the driving transistor,
2 supply voltage V
DD
= 20 V.
Analysis Scripting
The session to analyze inverters in DCI is depicted in Fig. 6.7. The lefthand side of the image
shows the session database. The righthand side depicts an analysis script for the determina
tion of robustness and circuit speed for inverters with different width ratios. The database
contains measured devices (in the folder Devices, not expanded in the screenshot), logic gates
in currentsource and other conﬁgurations (folder Circuits, subfolder for gates in current
source conﬁguration expanded), and numerous DCI analysis scripts in the folder Analyses.
The analysis scripts in the example all have names starting with “Analyze VTC for CSLoad
with ...” and are all variations of the same analysis with different models to use in the sim
ulations. The model conﬁgurations used in the analyses will be explained under the heading
“Impact of Modeling” in the following. The depicted analysis consists of sweeping the ratio
between the load and driving transistor and calculating the following performance ﬁgures:
138 Chapter 6. Analysis Concept
2 Nominal voltage levels for logic high and logic low using a pair of identical inverters.
High and low correspond to the stable intersections between the output of the second
inverter and the input voltage.
2 Maximum negative and critical gain of the voltagetransfer curve. The critical gain is
measured at the intersection between the input voltage and output voltage of an inverter.
2 Oscillation frequency of a 15stage ring oscillator.
2 20% / 80% rise and fall times of an individual stage within the ring oscillator. For
calculation of the 20% / 80% thresholds, the voltage swing between the nominal high
and low voltages is used. These voltages were derived above.
2 Unitygain and maximumsquare noise margin.
Fig. 6.7: DCI session to analyze the performance of inverters in currentsource conﬁguration.
6.3. Analysis Examples 139
Impact of Modeling
In order to test the inﬂuence of inaccuracies of modeling, four combinations of models are
investigated in the analysis:
1. one single table model for driving and load transistor (called combination with table
model, tablebased model, or simply otab in the following),
2. one single Linvar model for driving and load transistor (called allLinvar combination
in the following),
3. the Linvar model for the driving transistor and a Level1 model exactly mapping the
draincurrent curve for zero gatesource voltage (called Linvar/Level1 combination in
the following),
4. the Level1 model for the draincurrent curve at zero bias and a Level1 model approx
imating the output characteristics in the range of zero to 20 V of gate voltage (called
Level1/Level1 combination in the following).
The table model was derived by tabulating the original extraction values for K
P
, V
T
, and λ
in the Linvar extraction in Section 4.3.6 and using a linear interpolation for the V
GS
dependent
values. Model data are listed in Table 6.1.
Table 6.1: Parameter set for table model.
V
GS
[V ] K
P
[A/V
2
] V
T
[V] λ [V
−1
]
0 9.9393e13 8.0 0.0341730670859
4 1.3613e11 1.8 0.0125761040059
8 2.5627e11 0.5 0.00735829204921
12 3.4968e11 0.2 0.00542531729999
16 4.4147e11 1.0 0.00484211159415
20 5.0833e11 1.6 0.00453755973153
The parameter set for the Linvar model is KP
0
= 8 pA/V
2
, f
k
= 2 pA/V
3
, V
T0
= 2.4 V,
f
v
= 0.2, λ
0
= 50 · 10
−3
V
−1
, f
l
= 0 V
−2
, R
′
par
= 10 TΩm. The Level1 parameters for
the load transistor are K
P
= 0.994 pA/V
2
, V
T
= 8 V, λ = 34.2 · 10
−3
V
−1
. These values
correspond to the line for zero V
GS
in Table 6.1. Level1 parameters for the driving transistor
are K
P
= 51.6 pA/V
2
, V
T
= 2.4 V, and λ = 8.3 · 10
−3
V
−1
. They were derived using least
squaresﬁtting. All models used constant gatedrain and gatesource capacitors equivalent to
1
2
· C
spec
· W · L with C
spec
= 0.1 µF/cm
2
. It is acknowledged that this kind of capacitance
modeling only coarsely describes the capacitive behavior of real devices. More thorough
modeling will also take into account the nonlinear nature of device capacitances and the
contribution of layoutrelated parasitic capacitances.
140 Chapter 6. Analysis Concept
Analysis Results
The set of curves resulting from the analysis is depicted in Fig. 6.8, which also shows the VTC
plot for a width ratio of 8. With the exception of the Level1/Level1 combination, the logic
levels for the different model combinations roughly correspond. Owing to the fact that the
leastsquares ﬁt for the Level1 parameters of the driving transistor led to a negative threshold
voltage V
T
= 2.4 V, the Level1/Level1 setup realizes an enhancement/depletion gate leading
to high levels in the range of the supply voltage (≈ −20 V). The critical gains derived by the
allLinvar combination and Linvar/Level1 combination also show agreement. The circuit
combination using the tablebased model deviates from the other two combinations for ratios
below 6. For the Level1/Level1 combination, there is a surge in critical gain due to the
steeper transition between high and low (see Fig. 6.8f). Moreover, the criticalgain point is
situated within the region of steep transition so that the gain is considerably increased.
For the maximumsquare noise margin (Fig. 6.8e), the Level1/Level1 combination leads
to a considerably larger noise margin than the other combinations. Here, the VTC curve
is shifted to more negative values. The tablebased simulation also deviates from the other
two combinations by predicting zero noise margin for ratios of 4 and below. This can be
understood by inspecting the VTC curves in Fig. 6.8f, where the tablemodel VTC deviates
from the other VTCs in the range close to zero input voltage. There, the high level of the table
model VTCdoes not start to saturate and shows some irregularities at its ﬁxpoint (intersection
with the dotted line where the critical gain is measured, see Section 5.3.5).
Fig. 6.8a+b show the resulting oscillation frequencies and rise/fall times for the transient
simulations of the ring oscillators. Rise and fall times were measured between the 20% and
80% points of the voltage swing from low to high voltage.
The oscillation frequencies correspond to the stage delay t
D
according to t
D
= 1/(2nf
RO
),
where n is the number of inverters in the ring oscillator and f
RO
is the oscillation frequency.
Considerable deviations between the different modeling combinations can be seen. More
over, the tablebased simulation only yields oscillation at width ratios of 6 and higher. This
corresponds with the observation that there is no noise margin available for the tablebased
combination for ratios below 6. The differences in oscillation frequency might exist because
the Linvar model predicts currents which are up to 20% below the measured values for small
V
GS
 values. Therefore, this combination yields lowest speed because the load transistor sinks
less current. For the Level1/Level1 combination on the other hand, drain currents of the load
transistor are higher so that higher oscillation frequencies can be expected.
6.3. Analysis Examples 141
b)
d)
f)
a)
c)
e)
rise
fall
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 3 4 5 6 7 8 9 10
h
i
g
h
/
l
o
w
v
o
l
t
a
g
e
[
V
]
−
−
>
ratio of width load/driving trans. −−>
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2 3 4 5 6 7 8 9 10
m
a
x
.
−
s
q
u
a
r
e
n
o
i
s
e
m
a
r
g
i
n
[
V
]
−
−
>
ratio of width load/driving trans. −−>
0.5
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 3 4 5 6 7 8 9 10
ratio of width load/driving trans. −−>
5.0m
10.0m
15.0m
20.0m
25.0m
30.0m
2 3 4 5 6 7 8 9 10
ratio of width load/driving trans. −−>
0.0m
input voltage [V] −−>
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2 3 4 5 6 7 8 9 10
f
r
e
q
u
e
n
c
y
[
H
z
]
−
−
>
ratio of width load/driving trans. −−>
otab
all linvar
linvar+lev1
lev1+lev1
r
i
s
e
/
f
a
l
l
t
i
m
e
[
s
]
−
−
>
c
r
i
t
i
c
a
l
g
a
i
n
[
V
/
V
]
−
−
>
o
u
t
p
u
t
v
o
l
t
a
g
e
[
V
]
−
−
>
−20 −15 −10 −5 0
0.0
−2.0
−4.0
−6.0
−8.0
−10.0
−12.0
−14.0
−16.0
−18.0
−20.0
ratio width load/drive = 4
Fig. 6.8: Simulated data for an inverter in currentsource conﬁguration: a) ring oscillator
frequency, b) rise/fall times at a particular stage in the ring oscillator, c) nominal high and low
voltages, d) critical gain g
crit
, e) maximumsquare noise margins, and f) VTC plot for width
ratio of 4. Each plot contains curves for different combinations of simulation models.
142 Chapter 6. Analysis Concept
Analysis Conclusions
By observing the plots in Fig. 6.8, a width ratio of 6 can be identiﬁed as an acceptable com
promise between circuit speed and robustness on one hand and area usage of the logic gates
on the other hand. A further increase in ratio beyond 6 will also increase the oscillation fre
quency. However, frequency and nominal voltage levels only moderately improve.
Comparison between Gain and Noise Margin
A comparison of Fig. 6.8a and Fig. 6.8d shows that the presence of an oscillation (i.e. a robust
or regenerating operation of inverters in a chain) correlates with g
crit
 > 1. Therefore, it is
interesting to inspect g
crit
in order to derive the robustness of a logic gate. In literature on
noise margin calculations, a high g
max
 is also used as a criterion which reﬂects robustness
of a circuit (e.g. [125]). The relationship between critical gain, maximum negative gain, and
noise margin can be compared using the plots in Fig. 6.9.
a) b)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
2 3 4 5 6 7 8 9 10
g
a
i
n
[
]
&
n
o
i
s
e
m
a
r
g
i
n
[
V
]
max−square noise margin
−15.0
−10.0
−5.0
0.0
5.0
10.0
15.0
2 3 4 5 6 7 8 9 10
unity gain
max−square
n
o
i
s
e
m
a
r
g
i
n
[
V
]
−
−
>
W
L
/W
D
g
crit

W
L
/W
D
g
max

Fig. 6.9: Simulation data for noise margin analysis: a) magnitude of critical and mostnegative
gain together with maximumsquare noise margin, b) unitygain and maximumsquare noise
margin. Simulations were done with Linvar/Level1 combination for driving and load transis
tor.
The magnitude of the critical gain displays a behavior similar to the maximumsquare
noise margin while the magnitude of the maximum negative gain vs. the ratio develops differ
ently. Hence, designs optimizing g
crit
lead to different results than designs optimizing g
max
.
The unitygain noise margin also considerably differs from the maximumsquare data and
even yields negative values (for the low level). Again, designs optimizing the unitygain noise
margin and the maximumsquare noise margin will yield different results. The unitygain
6.3. Analysis Examples 143
method easily leads to large noise margins for the logic high level while negative (i.e. nonex
istent) noise margins for the logic low level might occur, even for circuits with a critical gain
g
crit
 > 1 and existing maximumsquare noise margin. The surge in unitygain noise margin
for a ratio of four is due to the fact that for smaller ratios, only one unitygain point exists.
Therefore, the noise margins get very small.
When inspecting g
crit
and g
max
, these two values strongly depend on the granularity of the
VTC curves from which they are calculated. The two gain values are numerically calculated,
i.e. by ﬁnite differences, and therefore strongly depend on the step size between neighboring
values of the VTC. This leads to the requirement that step sizes should be as small as possible,
e.g. 0.1 V.
Impact of DCI
The analyses presented so far can also be carried out using existing circuit simulators alone.
However, without an integration environment like DCI, the users are required to create and
update the testbenches by hand and to conﬁgure batch scripts controlling the simulation pro
cess. Some simulation environments feature the use of scripting systems, e.g. the original
SPICE3 distribution from the University of Berkeley, the simulation environment Synopsys
SaberDesigner, or the simulation tool SimPilot from Mentor Graphics. However, these tools
do generally not provide full transparency between different simulation engines. Moreover,
these systems do not automatically generate the required models or testbenches. On the other
hand, cell characterization packages generate testbenches and process simulation results, but
they generally do not explore more basic performance ﬁgures like static noise margin or the
critical gain, or provide heterogeneous analysis plans.
DCI interacts with different simulators, creates analysis testbenches as needed and com
bines transistor modeling, model and circuit management, analysis conﬁguration, and extrac
tion of performance ﬁgures within a single and interactive user interface. Device and circuit
information, analysis instructions, and analysis results are treated as a unit. Moreover, the
users can easily manipulate the complete set of data and scripts.
6.3.2 Analysis of NORGates in CurrentSource Conﬁguration
Inverters alone will not make up useful circuits. More complex gates like NORs are required.
The schematic of a NOR gate with the load transistor in currentsource conﬁguration is de
picted in Fig. 6.10. The gate consists of two driving transistors M
D1
and M
D2
in parallel and
a load transistor M
L
in currentsource conﬁguration. The driving transistors are controlled by
the two inputs V
in1
and V
in2
, respectively. For NOR3 gates in currentsource conﬁguration, a
third driving transistor M
D3
would be added in parallel to M
D1
and M
D2
.
144 Chapter 6. Analysis Concept
M
L
M
D1
M
D2
V
out
V
in2
V
in1
V
DD
Fig. 6.10: Schematic of a twoinput NOR with load transistor in currentsource conﬁguration.
Analysis Objective
A simple analysis of a twoand a threeinput NOR with a load transistor in currentsource
conﬁguration shall be carried out. The driving transistors shall have identical widths as deﬁned
by W
D1
= W
D2
= W
D
. The width of the load transistor M
L
shall be varied with respect to
W
D
so that W
L
= r · W
D
. In the course of the analysis, the VTC and transient behavior is
inspected by the methods already presented in Section 6.3.1. One input shall be used for the
characterization while the nominal low voltage V
low
shall excite the remaining input(s). V
low
shall also be varied.
Analysis Scripting
The analysis session to analyze NORs in DCI is similar to the inverterrelated session depicted
in Fig. 6.7. Differences are the use of NOR2 or NOR3 gates as circuits under test and terminal
“in1” as characterization input. The other inputs “in2” and “in3” (if available) are set to a value
V
low
using the “deﬁne connectivity” instruction. V
low
is added as a second parameter to sweep,
i.e. in an outer loop.
Analysis Results
The results of the analysis are presented in Fig. 6.11. For the calculations, the transistor model
from Section 4.3.6 was used. The data demonstrates that the anticipated low levels strongly
inﬂuence the choice of W
L
. The analysis can be used for ﬁnding the maximum tolerable low
level V
Low
 for a particular design. This voltage depends on device parameters but also on
the fanin, i.e. the number of inputs of a gate. This is demonstrated in Fig. 6.12, where a two
input NOR gate and a threeinput NOR gate with identical transistor dimensions are compared
6.3. Analysis Examples 145
at a ﬁxed supply voltage of 20 V and a low voltage V
Low
= 2 V.
−3 V
−4 V
−3 V
−4 V
−3 V
−4 V
−3 V
−4 V
−4 V −3 V
−2 V
rise
fall
a)
c)
b)
d)
NOR2
INV
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
14.0m
16.0m
18.0m
2 4 6 8 10 12 14
ratio of width load/driving trans. −−>
0.0m
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
0.0
2 3 4 5 6 7 8 9 10
ratio of width load/driving trans. −−>
−0.5
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 3 4 5 6 7 8 9 10
h
i
g
h
/
l
o
w
v
o
l
t
a
g
e
[
V
]
−
−
>
ratio of width load/driving trans. −−>
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2 3 4 5 6 7 8 9 10
f
r
e
q
u
e
n
c
y
[
H
z
]
−
−
>
ratio of width load/driving trans. −−>
r
i
s
e
/
f
a
l
l
t
i
m
e
[
s
]
−
−
>
c
r
i
t
i
c
a
l
g
a
i
n
[
V
/
V
]
−
−
>
V
low
= 2 V
V
low
= 2 V
V
low
= 2 V
V
low
= 2 V
Fig. 6.11: Simulated data for inverters and NOR2 gates with load transistor in currentsource
conﬁguration: a) ring oscillator frequency, b) rise/fall times, c) nominal high and low voltages,
d) critical gain. The second input of the NOR gate was biased with V
low
= 2/3/4 V.
Analysis Conclusions
The simulation results in Fig. 6.11 and Fig. 6.12 show that the fanin (FI) strongly inﬂuences
the attainable circuit speed and high levels. Increasing the width ratio of NOR gates does
not compensate for the detrimental effect of FI in comparison to the simple inverter. For the
transistor type used in this section, NOR2 gates should have a ratio of at least 8 and NOR3
gates of at least 10.
146 Chapter 6. Analysis Concept
a)
c)
rise
fall
b)
d)
NOR3
NOR2
INV
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
2 4 6 8 10 12 14
f
r
e
q
u
e
n
c
y
[
H
z
]
−
−
>
ratio of width load/driving trans. −−>
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
14.0m
16.0m
18.0m
20.0m
2 4 6 8 10 12 14
ratio of width load/driving trans. −−>
0.0m
−4.0
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
0.0
2 4 6 8 10 12 14
ratio of width load/driving trans. −−>
−0.5
c
r
i
t
i
c
a
l
g
a
i
n
[
V
/
V
]
−
−
>
r
i
s
e
/
f
a
l
l
t
i
m
e
[
s
]
−
−
>
−20.0
−18.0
−16.0
−14.0
−12.0
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2 4 6 8 10 12 14
h
i
g
h
/
l
o
w
v
o
l
t
a
g
e
[
V
]
−
−
>
ratio of width load/driving trans. −−>
Fig. 6.12: Comparison of simulation results for inverters and NOR2/NOR3 gates with
V
DD
= 20 V: a) ring oscillator frequency, b) rise/fall times, c) nominal high and low volt
ages, d) critical gain. Unused inputs were biased with V
low
= 2 V.
6.3.3 Analysis of Parameterdependent Gate Behavior
In the examples presented so far in Section 6.3, the analysis does not depend on the model
type. The analysis framework can also be used for predicting directions for material opti
mization. This is carried out by deliberately varying critical model parameters and inspect
ing resulting circuit performance. In this section, variation results obtained from DCI sim
ulations are presented. The analysis is carried out using the simpliﬁed Linvar model from
Section 4.3.6.
6.3. Analysis Examples 147
Analysis Objective
The proper function of a NORgate at a given supply voltage V
DD
in the presence of offcurrent
variations shall be veriﬁed. This is done using ring oscillator frequencies and the critical gain.
The same ring oscillator conﬁguration as in Section 6.3.1 is used. For demonstration purposes,
the analysis is restricted to the treatment of offcurrent variations. In principle, analysis of the
impact of oncurrent variation, thresholdvoltage variation, etc. can be done with similar
approaches.
Analysis Scripting
The analysis consists of varying the “off current” I
off
, i.e. the drain current at maximum
magnitude of drainsource voltage and zero gatesource voltage, while keeping constant the
“on current” I
on
, i.e. the drain current at maximummagnitude of drainsource and gatesource
voltage. In the Linvar model, this can be accomplished by varying K
P0
and calculating f
K
in
such a way that K
Pmax
remains unchanged. The corresponding formula for f
k
is
f
k
=
K
Pmax
−K
P0
V
GS,max
, (6.1)
where K
Pmax
is the conductance parameter at the maximum V
GS,max
, i.e. the gatesource
voltage for the “on current”.
Fig. 6.13 shows the DCI script for the analysis. The calculations corresponding to (6.1)
are outlined by boxes. The runtime variables kp0 and fk are used as mapping parameters for
the models describing the load and driving transistors, respectively.
Analysis Results
Fig. 6.14 shows the simulation results. The data suggests that I
off
strongly inﬂuences critical
gain, circuit speed, and attainable voltage level for logic high. A weaker inﬂuence on the low
level is observed because the VTC range for the logic low voltage is relatively large (see e.g.
Fig. 6.8f) so that a degenerate high level is not so crucial for the low level. For a ratio of 6, the
ring oscillator ceases to function with a zerobased process conductance of 12 pA/V
2
, where
the on/ratio dropped to a value below 200.
148 Chapter 6. Analysis Concept
Fig. 6.13: DCI script to analyze the inﬂuence of offcurrent variation on circuit performance.
6.4. Chapter Summary 149
c)
a)
d)
b)
150.0
200.0
250.0
300.0
350.0
400.0
450.0
500.0
550.0
600.0
0p 2p 4p 6p 8p 10p 12p 14p 16p
−3.5
−3.0
−2.5
−2.0
−1.5
−1.0
0p 2p 4p 6p 8p 10p 12p 14p 16p
−0.5
ratio = 6
ratio = 8
c
r
i
t
i
c
a
l
g
a
i
n
[
V
/
V
]
−
−
>
zero−based process conductance [A/V²] −−>
o
n
/
o
f
f
r
a
t
i
o
−
−
>
zero−based process conductance [A/V²] −−>
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
0p
ratio = 6
ratio = 8
−18
−16
−14
−12
−8
−6
−4
−2
0
6p 8p 12p 14p 16p
ratio = 6
ratio = 8
zero−based process conductance [A/V²] −−>
zero−based process conductance [A/V²] −−>
f
r
e
q
u
e
n
c
y
[
H
z
]
−
−
>
n
o
m
i
n
a
l
h
i
g
h
/
l
o
w
v
o
l
t
a
g
e
[
V
]
−
−
>
2p 4p 6p 8p 10p 12p 14p 16p
0p 2p 4p
−10
10p
Fig. 6.14: Simulations of twoinput NORs with varying zerobased process conductance K
P0
for two ratios (6 and 8): a) critical gain, b) oscillation frequency, c) on/off ratio of the driving
transistor, and d) nominal high and low voltages.
6.4 Chapter Summary
In this chapter, a novel analysis concept was discussed. The basic idea of the concept is to
combine data management, modeling, and circuit investigation in a single analysis framework.
Data is organized in a hierarchical data tree where all items relevant in the analysis (model
data, model sets, circuits, analysis scripts, results) can be stored. Analysis procedures are
described by use of treeform scripting in which the ﬂow of commands is expressed using
execution trees. Individual actions, i.e. analysis steps, are conﬁgured using graphical dialogs.
150 Chapter 6. Analysis Concept
Simulation tools are integrated into the framework via an abstraction layer which provides a
standardized interface.
The analysis framework resolves the following issues with existing tools (cf. p. 122):
1. A single software environment is provided. It is easy to use and allows the users to focus
on carrying out their analysis in a highly automated way. The environment features a
graphical user interface and easy access to all relevant data of the analysis.
2. The environment integrates modeling of transistor devices by use of model extractors,
which are fully integrated into the framework.
3. The environment provides automatic netlist generation for various performance analy
ses (noise margin detection, circuit speed, etc.).
4. Preconﬁgured analysis procedures and libraries of logic gates can be stored in the
database of the analysis environment and reused in later analyses.
5. The environment tracks all model references in the circuits used by the netlist generator.
Arbitrary models can be mapped to the references used in these circuits.
6. Analysis procedures are expressed as execution trees where all individual steps can be
conﬁgured using graphical dialogs. Different analysis steps exist to deﬁne variables,
perform sweeps, map models and circuits, or to carry out sophisticated simulations.
This setup allows ﬂexible manipulation and extension of existing analysis schemes.
7. During the analyses, model and circuit parameters can be ﬂexibly varied so to provide
means of exploring the parameterdependent behavior of devices and circuits. New
schemes can be deﬁned by composing the respective execution trees.
8. The environment automatically collaborates with external simulators by calling these
tools via an abstraction interface. If the simulation tool is replaced, only an implemen
tation of the interface to the replacing simulator is required.
151
Chapter 7
Summary and Further Work
This chapter summarizes the work presented in this thesis and discusses possible extensions
to the provided methods, analyses, and tools.
7.1 Summary
Organic ﬁeldeffect transistors (OFETs) are currently in the early stages of process develop
ment and device optimization. In the course of optimization, circuit simulation of reasonable
application circuits is a key point in ﬁnetuning the device parameters of OFET technologies
as it provides insight into the performance potential of given or hypothetical OFET genera
tions. However, many issues have to be overcome before circuit analysis by circuit simulation
can unfold its full potential in the ﬁeld of OFETbased circuits. Owing to the early stages in
the ﬁeld, adequate transistor models, modeling software, and analysis tools (proper perfor
mance ﬁgures, simulation software) dedicated to organic electronics are missing. Therefore, a
computeraided methodology to analyze the performance of OFETs in logic circuits has been
developed in this work. The basic idea of the concept is to provide an integrated environment
for data management, transistor modeling, and the automatic analysis of benchmark circuits.
In order to implement the methodology, issues in OFET modeling and circuit characterization
were analyzed in this work.
In the part dealing with OFET modeling, a model quality chart was deﬁned so to allow
formal comparison of individual modeling approaches. By using the model quality chart,
model accuracy, proper capacitance modeling, compactness of a model, parameter extraction,
and modeling of stress effects are rated. Existing modeling approaches for OFET devices,
extraction procedures for the respective parameters, and extraction tools were discussed. A
review of the tools showed that they are either very general or specialize on certain models.
The tools cannot visualize which model type can best ﬁt a given transistor. Therefore, users
152 Chapter 7. Summary and Further Work
have to carry out parameter extractions for different model types and have to compare the
resulting model accuracies in order to ﬁnd the mostappropriate model. In order to facilitate
modeling, a novel extraction scheme called V
Sat
method was therefore developed in this work.
The approach is used for extracting the basic parameters threshold voltage (V
T
), process con
ductance (K
P
), and channel length modulation (λ) for individual I
D
vs. V
DS
curves. The
V
GS
dependence of these parameters is used for identifying appropriate model types because
each type has characteristic V
GS
dependences for the basic model parameters. Two models
were presented which directly use the basic parameters extracted with the V
Sat
method: a
table model and an analytic model called Linvar model.
In the part dealing with the circuit characterization, a novel approach was introduced
which deﬁnes the robustness of logic gates by inspecting the gain of the ﬁx point in the
voltagetransfer characteristic. An existing method of qualitatively deﬁning the compatibility
of valid logic level ranges was extended to yield noise margins.
Traditional methods of deﬁning static and dynamic performance ﬁgures of basic logic
circuits were analyzed. Existing tools for circuit characterization were reviewed. Like in
the case of modeling, these tools are either very general or specialize on a limited set of
applications. Many tools lack automatic testbench generation, inclusion of documentation, or
ﬂexible manipulation of the analysis ﬂow and data. Seamless integration of device modeling
is generally not provided.
In view of the drawbacks of existing modeling and characterization tools, a novel analysis
methodology was developed in this work. The concepts of the methodology are:
2 Transistor modeling and circuit characterization are integrated into a single environ
ment.
2 The users have direct access to all items needed in the modeling and characterization
steps (models, circuits, waveforms, analysis procedures).
2 The items are organized in a data tree and can be arranged hierarchically according to
the needs of the users.
2 Documentation and a property set can be assigned to each item in the data tree. This
facilitates reuse of existing analyses and backtracking of unexpected results as every
item can be thoroughly described.
2 Automation of the analysis is reached using a graphical scripting concept that allows
nonexpert users to compose new or reuse existing analysis procedures.
2 Testbenches to analyze typically used performance ﬁgures like circuit speed or robust
ness, i.e. noise margin, are generated fully automatically. The generation process and
result extraction seamlessly integrate into the graphical scripting concept.
7.2. Further Work 153
Scientiﬁc progress could be made in this work in the formal comparison of models and
in the extraction of model parameters by use of the novel V
Sat
method. Novel model types
for OFET devices and a computeraided methodology for OFETbased modeling and circuit
characterization have been developed.
7.2 Further Work
This section summarizes methodological and practical issues which have not been resolved in
the design of the analysis concept presented in Chapter 6 or its experimental implementation,
DCI.
Modeling
The V
Sat
method could be used for generating a modeling wizard. Such a wizard is a program
which analyzes available transistor data and provides different action routes on the basis of
the analysis results. The wizard will run through a number of steps until a proper model has
been selected and the accompanying parameter sets have been derived. In future work, proper
models could be chosen according to the V
GS
dependent shapes of the extracted parameters.
The process could be automated by use of shapedetection algorithms. Alternatively, the basic
parameters could be used as initial values for curve ﬁtting.
Another issue is the separation of contact effects during parameter extraction. There have
been reports on the treatment of contact effects in transistor modeling but the extraction pro
cedures often require interference by the user. Methods like the Uniﬁed Extraction Method
(UEM) [56] could help in the extraction of contact effects. Additionally, UEM is also very
interesting for model extraction in general because it is speciﬁcally designed for thinﬁlm
transistors. However, UEM requires a sophisticated user interface and a high degree of user
interaction. Here, efﬁcient implementations and automation schemes for selecting appropriate
currentvoltage curves could be explored in further work.
Statistical modeling of OFETbased measurement series is currently not included in the
data organization scheme of the analysis concept. However, statistical analyses are important
for more realistic simulations of device performance in integrated circuits.
Capacitance modeling is currently approximated by constant capacitors in the analyses
presented in this work. The inﬂuence of nonlinear capacitances on simulation results for ring
oscillators needs to be investigated. Such nonlinear capacitances are included e.g. in models
for variable range hopping [63, 65].
There have been efforts to analytically explain the subthreshold behavior of OFETs [64] in
the framework of variable range hopping. A proper description of this operation region could
154 Chapter 7. Summary and Further Work
improve the accuracy of simulating NAND gates or transmission gates. However, research on
this topic is still in the early stages.
Circuit Characterization
Automatic circuit sizing is currently not addressed by DCI, the experimental implementation
of the methodology. Therefore, it is up to the user to provide sensible transistor conﬁgurations
for their circuits under analysis. Generic circuit sizers could be included in the implementation
of the analysis concept by providing appropriate commands to the graphical scripting system.
The special needs and techniques of statistical circuit analysis have currently been disre
garded in the design of the analysis concept. In spite of that, statistical variation is important
in order to provide realistic data on the performance potentials of OFETbased circuits. Yet,
there is currently only small activity in the research community regarding statistical methods
in the characterization of OFETbased logic circuits. Approaches like the method of equi
librium zones (MEQ) could be used in conjunction with statistical methods. The statistical
analyses would establish upper and lower bounds for the VTC curves.
155
Appendix A
List of Symbols
Symbol Description Unit
α effective overlap parameter between localized states in
VRH modeling
Å
−1
α power factor for V
GS
dependence of I
D
in TFT modeling
and UEM
–
α
sat
saturation variation parameter in PsiTFT modeling –
β device conductance parameter of a transistor A/V
2
β ratio between effective grainboundary size and channel
length in PsiTFT modeling
–
∆E voltagedependent contribution to extraction function E in
SJ method
V/A
ε
0
freespace permittivity constant (8.854187818 · 10
−12
) AsV
−1
m
−1
ε
r
relative permittivity of the insulator –
ε
s
relative permittivity of the semiconductor –
η diode ideality factor –
η
i
subthreshold ideality factor in PsiTFT modeling –
γ power parameter for aSi TFT mobility –
γ ﬁtting parameter for conductivity in UML modeling –
λ transistor channellength modulation V
−1
λ
0
constant channellength modulation in Linvar modeling V
−1
µ carrier mobility cm
2
/V·s
µ
0
upper mobility limit in PsiTFT modeling cm
2
/V·s
µ
1
lowﬁeld mobility in PsiTFT modeling cm
2
/V·s
µ
eff
effective mobility cm
2
/V·s
156 Appendix A. List of Symbols
Symbol Description Unit
µ
g
grain intrinsic mobility in PsiTFT modeling cm
2
/V·s
µ
gb
mobility at grain boundary in PsiTFT modeling cm
2
/V·s
µ
n
mobility of electrons cm
2
/V·s
µ
p
mobility of holes cm
2
/V·s
µ
s
subthreshold mobility in PsiTFT modeling cm
2
/V·s
σ conductivity S/cm
σ
0
prefactor for conductivity in VRH modeling S/cm
τ(V
GS
) delay function in Dresden modeling –
τ
s
statistical shift parameter for delay function in Dresden
modeling
–
a mobility factor in Hamburg VRH modeling cm
2
/V·s
a
i
ﬁtting parameter for shape function f in Dresden modeling –
b power factor for mobility in Hamburg VRH modeling –
b
i
ﬁtting parameter for shape function f in Dresden modeling –
B
c
critical number of bonds per site in largest cluster of a per
colation system
–
C
GD
gatedrain capacitance F
C
GS
gatesource capacitance F
c
i
ﬁtting parameter for scale function h in Dresden modeling –
C
is
insulator capacitance per unit area F/cm
2
d
i
ﬁtting parameter for scale function h in Dresden modeling –
E(V
GS
−V
T
) extraction function for contact resistance in SJ method V
2
/A
E
0
constant contribution to extraction function E in SJ method V
2
/A
E
b
barrier height at grain boundary in TFT modeling eV
E
C
energy of lower edge of conduction band eV
E
F
Fermi energy eV
E
V
energy of upper edge of valence band eV
f(V ) VTC of gate under consideration in unity gain method V
f(V
DS
) shape function in Dresden Modeling –
F
1
(x) VTC curve of gate under consideration in method of maxi
mum squares
V
F
2
(y) inverse VTC curve of gate under consideration in method
of maximum squares
V
f
λ
factor for V
GS
dependent channellength modulation in Lin
var modeling
V
−2
157
Symbol Description Unit
f
k
factor for V
GS
dependent process conductance in Linvar modeling A/V
3
f
T
factor for V
GS
dependent threshold voltage in Linvar modeling –
G
0
lengthindependent channel resistance of transistor Ω/m
g
crit
critical gain at ﬁx point of VTC curve of a logic gate –
g
d
drain conductance S
g
m
transconductance S
g
max
maximum negative gain of VTC curve of a logic gate –
H(V
GS
) extraction function in UEM for TFTs V
h(V
GS
) scale function in Dresden modeling –
I current A
I
00
current density in cutoff region of UML modeling A/m
I
a
abovethreshold current in PsiTFT modeling A
I
D
drain current A
I
DMax
maximum current in V
Sat
extraction A
I
DS0
saturation current clear of channellength modulation in V
Sat
ex
traction
A
I
DSat
current at transition between linear and saturation region A
I
leak
subthreshold leakage current A
I
S
saturation current of Schottky diode A
I
sub
subthreshold current in PsiTFT modeling A
K conductance parameter in UEM extraction for TFTs S
K ﬁtting parameter for mobility in UML modeling S
K
′
ﬁtting parameter for conductivity in UML modeling S
k
B
Boltzmann constant (1.380662 · 10
−23
) VAs/K
K
G
geometry factor in Dresden modeling A
K
P
process conductance parameter of a transistor A/V
2
KP
0
constant process conductance factor in Linvar modeling A/V
2
K
S
statistical current scale factor in Dresden modeling –
L length of the transistor channel m
L
n
length of electronaccumulating region in ambipolar transistors m
L
p
length of holeaccumulating region in ambipolar transistors m
m power factor for mobility in UML modeling –
m
µ
mobility parameter in PsiTFT modeling –
158 Appendix A. List of Symbols
Symbol Description Unit
n number of grain boundaries along channel in PsiTFT modeling –
N
A
dopinginduced charge density in UML modeling –
NM
H
noise margin for high level of a logic gate V
NM
L
noise margin for low level of a logic gate V
N
t
density of localized states in VRH modeling cm
−3
p
i
ﬁtting parameter for delay function τ in Dresden modeling –
q elementary charge (1.6021892 · 10
−19
) As
Q
D
drain charge of transistor C
Q
G
gate charge of transistor C
q
i
ﬁtting parameter for delay function τ in Dresden modeling –
Q
S
source charge of transistor C
r step function –
R
C
contact resistance Ω
R
CD
compensation resistance for drainside contact resistance Ω
R
CS
compensation resistance for sourceside contact resistance Ω
R
D
drainside contact resistance (synonymous to R
DC
) Ω
R
DC
drainside contact resistance (synonymous to R
D
Ω
R
M
effective channel resistance including contact effects Ω
R
par
bulk resistor in Linvartype OFETs Ω
R
′
par
widthindependent bulk resistor in Linvartype OFETs Ω · m
R
S
sourceside contact resistance (synonymous to R
SC
) Ω
R
SC
sourceside contact resistance (synonymous to R
S
) Ω
S subthreshold slope V/dec
T temperature K
T
0
width of exponential distribution in VRH modeling K
t
df
hightolow delay of logic gate s
t
dr
lowtohigh delay of logic gate s
t
f
fall time of of logic gate s
t
is
insulator thickness m
159
Symbol Description Unit
t
PD
pair delay of two identical gates s
t
r
rise time of logic gate s
u, v coordinates of rotated coordinate system in method of maximum
squares
V
V voltage V
V
AA
characteristic voltage for mobility in aSi TFT modeling V
V
B
potential barrier between grains in PsiTFT modeling V
V
D
drain voltage V
V
DD
supply voltage V
V
DMax
maximum (in magnitude) drain current in V
Sat
method V
V
DS
drainsource voltage (V
D
−V
S
) V
V
′
DS
drainsource voltage clear of contact effects V
V
DSat
saturation voltage (synonymous to V
Sat
) V
V
G
gate voltage V
V
GDT
V
G
−V
D
−V
T
V
V
GS
gatesource voltage (V
G
−V
S
) V
V
′
GS
gatesource voltage clear of contact effects V
V
GST
effective gatesource voltage (V
G
−V
S
−V
T
) V
V
GST
effective V
GST
clear of contact effects V
V
H
stable voltage level for logic high in VTC curve of a logic gate V
160 Appendix A. List of Symbols
Symbol Description Unit
V
IH,min
minimum allowable voltage level for logic high at the input of a
logic gate
V
V
IL,max
maximum allowable voltage level for logic low at the input of a
logic gate
V
V
in
input voltage of a logic gate V
V
L
stable voltage level for logic low in VTC curve of a logic gate V
V
M
metastable voltage level in VTC curve of a logic gate V
V
OH,min
minimum allowable voltage level for logic high at the output of a
logic gate
V
V
OL,max
maximum allowable voltage level for logic low at the output of a
logic gate
V
V
ON
on voltage V
V
ON
statistical quantity to shift switchon voltage in Dresden modeling V
V
out
output voltage of a logic gate V
V
S
source voltage V
V
Sat
saturation voltage (synonymous to V
DSat
) V
V
′
Sat
saturation voltage clear of contact effects V
V
SO
switchon voltage V
V
T
threshold voltage V
V
∗
T
effective threshold voltage including contact effects V
V
T0
constant threshold voltage parameter in Linvar modeling V
V
T,n
threshold voltage of electronaccumulating region of ambipolar
transistor
V
V
T,p
threshold voltage of holeaccumulating region of ambipolar tran
sistor
V
V
th
thermal voltage V
X
τ
power factor for delay function τ in Dresden modeling –
X
f
power factor for shape function f in Dresden modeling –
X
h
power factor for scale function h in Dresden modeling –
W width of the transistor channel m
161
Appendix B
List of Acronyms
aSi TFT amorphous silicon thinﬁlm transistor
BC bottom contact
BFL Buffered FET Logic
CMOS complementary metal oxide semiconductor
CSL currentsource load
DCI Device and Circuit Investigator
DL diodeload
DUT device under test
E/D logic enhancementdepletion logic
EDA electronic design automation
F8T2 poly(9,9dioctylﬂuorenecobithiophene); short: polyﬂuorene
FET ﬁeldeffect transistor
FI fanin
FO fanout
GND ground
IC integrated circuit
IGFET insulatedgate ﬁeldeffect transistor
KCL Kirchhoff Current Law
MOSFET metal oxide semiconductor ﬁeldeffect transistor
MQC Model Quality Chart
MTR multiple trapping and release
OFET organic ﬁeldeffect transistor
OLED organic lightemitting diode
OTFT organic thinﬁlm transistor
P3HT poly(3hexylthiophene)
PDHTT poly(3,3”dihexyl2,2’:5’,2”terthiophene)
162 Appendix B. List of Acronyms
PEDOT/PSS poly(ethylenedioxythiophene)/poly(styrene sulfonic)acid
PPV poly(phenylenevinylene)
Psi TFT polycrystalline silicon TFT
PTAA polytriarylamide
PTV poly(2,5thienylen vinylene)
RFID radiofrequency identiﬁcation
RO ring oscillator
RPI Rensselaer Polytechnic Institute
SPICE simulation program with integrated circuit emphasis
TC top contact
TFT thinﬁlm transistor
UEM Uniﬁed Extraction Method (→UMEM)
UMEM Uniﬁed Model and parameter Extraction Method (→UEM)
UML universal mobility law
VRH variable range hopping
VTC voltage transfer characteristic
163
Appendix C
Glossary
analysis/analysis sequence/analysis procedure/analysis ﬂow The four terms refer to a se
quence of operations carried out to study the characteristic behavior of a circuit or de
vice.
benchmark circuit A circuit useful in the extraction of typical performance ﬁgures of de
vices. In the domain of logic circuits, inverters, ring oscillators, ﬂipﬂops, counters, etc.
might be used.
characterization Process of extracting performance ﬁgures of a circuit (circuit characteriza
tion) or model parameters of a device (device characterization).
circuit This term refers to a combination of two or more devices which carries out a useful
function, i.e. acts as a logic gate, ampliﬁer, etc.
conjugation In chemistry, a system of covalently bonded atoms in a compound with an alter
nation of single and multiple bonds [9].
device One of the basic electrical elements supported by a semiconductor technology (tran
sistor, resistor, capacitor, etc.). In this work, the term mainly refers to transistors.
effective mobility See mobility.
ﬂexography printing A printing process where ink is transferred from a raised area. The
printing plate is made of a ﬂexible material.
ﬂipﬂop A memory element where the level changes of the inputs deﬁne the stored state, i.e.
a edgetriggered memory element [134] as opposed to levelsensitive latches. See also
latch.
164 Appendix C. Glossary
framework A software tool in which analysis projects can be developed and organized. The
framework integrates the various tools needed in the analysis process. The terms anal
ysis environment, analysis framework, and analysis concept are used synonymously.
gravure printing A printing process where ink is transferred from a recessed surface.
latch A memory element where the levels of the inputs deﬁne the stored state, i.e. a level
sensitive memory element [134] as opposed to edgetriggered ﬂipﬂops. The simplest
form of a latch is the socalled RS latch which consists of two crosscoupled twoinput
NAND or NOR gates, respectively (see Fig. D.2). See also ﬂipﬂop.
mobility This quantity (unit cm
2
/Vs) describes the mobility of charge carriers. Several types
of mobilities can be deﬁned (see [83]). In this work, the gatevoltagedependent effec
tive mobility, derived from experimental currentvoltage characteristics of a FET [52],
is used.
model The representation of the electrical behavior of a device useful in circuit simulation.
A model consists of a description of the electrical behavior in the form of equations
(analytical model or compact model) or a combination of devices (macro model) as
well as a set of model parameters.
noise Any deviation from nominal voltages [112]. Sources for noise can e.g. be [113] spu
rious signals/crosstalk which interfere with informationcarrying circuit nodes, or in
herent ﬂuctuations of device parameters owing to fabrication process or operating point
variations.
off current Current at maximummagnitude of drainsource voltage and minimummagnitude
of gatesource voltage. See also on current.
on current Current at maximummagnitude of drainsource voltage and maximummagnitude
of gatesource voltage. See also off current.
output characteristics Plot of the drain current vs. drainsource voltage of a transistor.
percolation theory This ﬁeld studies properties of disordered systems like conductivity by
means of statistical methods [156]. In organic electronics, percolation theory is used to
analyze transport in inhomogeneous organic semiconductors.
performance ﬁgures Figures representing the performance of a circuit or device in a certain
application. Performance ﬁgures can be switching speed, power consumption, robust
ness against parameter variation, etc.
165
polymer A compound consisting of organic chains. The length of the chains is not clearly
deﬁned [9].
ring oscillator A chain of inverting gates forming a loop with an odd number of stages. The
output of each gate is connected to the input of its successor. The output of the last gate
is fed back to the input of the ﬁrst gate. This conﬁguration leads to an oscillation with a
frequency of f ≈ 2nt
D
where n is the number of stages and t
D
is the delay per stage.
screen printing A printing process where ink is applied to a surface through a ﬁne mesh
screen. The image is deﬁned by blocking parts of the mesh screen [23].
testbench/test circuit A combination of one or more benchmark circuits together with the
required input signals and output loads. The testbench is used to derive performance
ﬁgures of devices or circuits during circuit characterization.
thinﬁlm transistor A type of transistor where the semiconducting channel is deposited as a
thin ﬁlm.
transfer characteristic Plot of the drain current vs. gatesource voltage of a transistor.
trap An energy level within the bandgap of a semiconductor due to the presence of impurities
or structural defects [14].
voltage transfer characteristic (VTC) Plot of the output voltage vs. input voltage of a logic
gate.
166 Appendix C. Glossary
167
Appendix D
Symbols and Truth Tables for Logic
Circuits
Logic Gates
A Q
L H
H L
A
B
Q &
A
B
Q
A B Q
L L H
L H H
H L H
H H L
L H L
A B Q
L L H
H L L
H H L
B
A
Q
B
A
Q
B
A
Q
Inverter
A B Q
L L H
L H L
H L L
H H H
XNOR
A
B
Q
Q Q A
NAND
NOR
A
Gate Type Truth Table
(EAN) Symbol
European North−American
(ANSI) Symbol
Fig. D.1: European/american symbols and truth tables for selected logic gates.
168 Appendix D. Symbols and Truth Tables for Logic Circuits
Latches
&
&
a)
b)
L L
L
L H
H H
L L
L
L
H
H
H H
H
L
X
X
L
H
H
Q
Q
R
¯
S
¯
R
S Q
n+1
Q
n
Q
n+1
Q
n
¯
Q
R
S
¯
R
¯
S
¯
Q
Fig. D.2: Schematics and truth tables for latches: a) NORbased, and b) NANDbased.
169
Appendix E
Simulation Software
The following software tools have been used during the experimental analyses and for the
implementation of the analysis framework:
2 the SPICE simulator TclSpice (available at http://tclspice.sf.net) for the simulation of
logic gates and circuits,
2 the numerical language GNU Octave (available at www.gnu.org/software/octave) for
the postprocessing in modeling issues,
2 the scripting language Python (available at www.python.org) for the implementation of
DCI, the experimental implementation of the analysis concept,
2 the C++ class library wxWidgets (available at www.wxwidgets.org) for the implemen
tation of the graphical user interface
2 the numerical C library Levmar (available at http://www.ics.forth.gr/∼lourakis/levmar/)
for the implementation of a LevenbergMarquardt optimizer
170 Appendix E. Simulation Software
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